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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool then_branch_divergent
;
93 static bool visit_cf_list(struct isel_context
*ctx
,
94 struct exec_list
*list
);
96 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
98 succ
->logical_preds
.emplace_back(pred_idx
);
102 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
104 succ
->linear_preds
.emplace_back(pred_idx
);
107 static void add_edge(unsigned pred_idx
, Block
*succ
)
109 add_logical_edge(pred_idx
, succ
);
110 add_linear_edge(pred_idx
, succ
);
113 static void append_logical_start(Block
*b
)
115 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
118 static void append_logical_end(Block
*b
)
120 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
123 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
125 assert(ctx
->allocated
[def
->index
].id());
126 return ctx
->allocated
[def
->index
];
129 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
130 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
132 Builder
bld(ctx
->program
, ctx
->block
);
133 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
134 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
136 if (ctx
->program
->wave_size
== 32) {
139 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
144 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
146 Builder
bld(ctx
->program
, ctx
->block
);
149 dst
= bld
.tmp(src
.regClass());
151 assert(src
.size() == dst
.size());
153 if (ctx
->stage
!= fragment_fs
) {
157 bld
.copy(Definition(dst
), src
);
161 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
162 ctx
->program
->needs_wqm
|= program_needs_wqm
;
166 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
168 if (index
.regClass() == s1
)
169 return bld
.readlane(bld
.def(s1
), data
, index
);
171 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
173 /* Currently not implemented on GFX6-7 */
174 assert(ctx
->options
->chip_class
>= GFX8
);
176 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
177 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
180 /* GFX10, wave64 mode:
181 * The bpermute instruction is limited to half-wave operation, which means that it can't
182 * properly support subgroup shuffle like older generations (or wave32 mode), so we
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
192 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
193 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
194 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
196 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
197 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
200 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
202 if (val
.type() == RegType::sgpr
) {
203 Builder
bld(ctx
->program
, ctx
->block
);
204 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
206 assert(val
.type() == RegType::vgpr
);
210 //assumes a != 0xffffffff
211 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
214 Builder
bld(ctx
->program
, ctx
->block
);
216 if (util_is_power_of_two_or_zero(b
)) {
217 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
221 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
223 assert(info
.multiplier
<= 0xffffffff);
225 bool pre_shift
= info
.pre_shift
!= 0;
226 bool increment
= info
.increment
!= 0;
227 bool multiply
= true;
228 bool post_shift
= info
.post_shift
!= 0;
230 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
231 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
235 Temp pre_shift_dst
= a
;
237 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
238 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
241 Temp increment_dst
= pre_shift_dst
;
243 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
244 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
247 Temp multiply_dst
= increment_dst
;
249 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
250 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
251 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
255 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
259 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
261 Builder
bld(ctx
->program
, ctx
->block
);
262 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
266 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
268 /* no need to extract the whole vector */
269 if (src
.regClass() == dst_rc
) {
273 assert(src
.size() > idx
);
274 Builder
bld(ctx
->program
, ctx
->block
);
275 auto it
= ctx
->allocated_vec
.find(src
.id());
276 /* the size check needs to be early because elements other than 0 may be garbage */
277 if (it
!= ctx
->allocated_vec
.end() && it
->second
[0].size() == dst_rc
.size()) {
278 if (it
->second
[idx
].regClass() == dst_rc
) {
279 return it
->second
[idx
];
281 assert(dst_rc
.size() == it
->second
[idx
].regClass().size());
282 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
283 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
287 if (src
.size() == dst_rc
.size()) {
289 return bld
.copy(bld
.def(dst_rc
), src
);
291 Temp dst
= bld
.tmp(dst_rc
);
292 emit_extract_vector(ctx
, src
, idx
, dst
);
297 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
299 if (num_components
== 1)
301 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
303 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
304 split
->operands
[0] = Operand(vec_src
);
305 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
306 for (unsigned i
= 0; i
< num_components
; i
++) {
307 elems
[i
] = {ctx
->program
->allocateId(), RegClass(vec_src
.type(), vec_src
.size() / num_components
)};
308 split
->definitions
[i
] = Definition(elems
[i
]);
310 ctx
->block
->instructions
.emplace_back(std::move(split
));
311 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
314 /* This vector expansion uses a mask to determine which elements in the new vector
315 * come from the original vector. The other elements are undefined. */
316 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
318 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
323 Builder
bld(ctx
->program
, ctx
->block
);
324 if (num_components
== 1) {
325 if (dst
.type() == RegType::sgpr
)
326 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
328 bld
.copy(Definition(dst
), vec_src
);
332 unsigned component_size
= dst
.size() / num_components
;
333 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
335 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
336 vec
->definitions
[0] = Definition(dst
);
338 for (unsigned i
= 0; i
< num_components
; i
++) {
339 if (mask
& (1 << i
)) {
340 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
341 if (dst
.type() == RegType::sgpr
)
342 src
= bld
.as_uniform(src
);
343 vec
->operands
[i
] = Operand(src
);
345 vec
->operands
[i
] = Operand(0u);
347 elems
[i
] = vec
->operands
[i
].getTemp();
349 ctx
->block
->instructions
.emplace_back(std::move(vec
));
350 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
353 /* adjust misaligned small bit size loads */
354 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
356 Builder
bld(ctx
->program
, ctx
->block
);
358 Temp select
= Temp();
359 if (offset
.isConstant()) {
360 assert(offset
.constantValue() && offset
.constantValue() < 4);
361 shift
= Operand(offset
.constantValue() * 8);
363 /* bit_offset = 8 * (offset & 0x3) */
364 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
365 select
= bld
.tmp(s1
);
366 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
369 if (vec
.size() == 1) {
370 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
371 } else if (vec
.size() == 2) {
372 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
373 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
375 emit_split_vector(ctx
, dst
, 2);
377 emit_extract_vector(ctx
, tmp
, 0, dst
);
378 } else if (vec
.size() == 4) {
379 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
380 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
381 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
382 if (select
!= Temp())
383 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
384 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
385 Temp mid
= bld
.tmp(s1
);
386 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
387 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
388 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
389 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
390 emit_split_vector(ctx
, dst
, 2);
394 /* this function trims subdword vectors:
395 * if dst is vgpr - split the src and create a shrunk version according to the mask.
396 * if dst is sgpr - split the src, but move the original to sgpr. */
397 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
399 assert(vec_src
.type() == RegType::vgpr
);
400 emit_split_vector(ctx
, vec_src
, num_components
);
402 Builder
bld(ctx
->program
, ctx
->block
);
403 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
404 unsigned component_size
= vec_src
.bytes() / num_components
;
405 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
408 for (unsigned i
= 0; i
< num_components
; i
++) {
410 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
413 if (dst
.type() == RegType::vgpr
) {
414 assert(dst
.bytes() == k
* component_size
);
415 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
416 for (unsigned i
= 0; i
< k
; i
++)
417 vec
->operands
[i
] = Operand(elems
[i
]);
418 vec
->definitions
[0] = Definition(dst
);
419 bld
.insert(std::move(vec
));
421 // TODO: alignbyte if mask doesn't start with 1?
423 assert(dst
.size() == vec_src
.size());
424 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
426 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
429 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
431 Builder
bld(ctx
->program
, ctx
->block
);
433 dst
= bld
.tmp(bld
.lm
);
435 assert(val
.regClass() == s1
);
436 assert(dst
.regClass() == bld
.lm
);
438 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
441 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
443 Builder
bld(ctx
->program
, ctx
->block
);
447 assert(val
.regClass() == bld
.lm
);
448 assert(dst
.regClass() == s1
);
450 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
451 Temp tmp
= bld
.tmp(s1
);
452 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
453 return emit_wqm(ctx
, tmp
, dst
);
456 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
458 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
459 return get_ssa_temp(ctx
, src
.src
.ssa
);
461 if (src
.src
.ssa
->num_components
== size
) {
462 bool identity_swizzle
= true;
463 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
464 if (src
.swizzle
[i
] != i
)
465 identity_swizzle
= false;
467 if (identity_swizzle
)
468 return get_ssa_temp(ctx
, src
.src
.ssa
);
471 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
472 unsigned elem_size
= vec
.size() / src
.src
.ssa
->num_components
;
473 assert(elem_size
> 0); /* TODO: 8 and 16-bit vectors not supported */
474 assert(vec
.size() % elem_size
== 0);
476 RegClass elem_rc
= RegClass(vec
.type(), elem_size
);
478 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
481 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
482 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
483 for (unsigned i
= 0; i
< size
; ++i
) {
484 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
485 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
487 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
)};
488 vec_instr
->definitions
[0] = Definition(dst
);
489 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
490 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
495 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
499 Builder
bld(ctx
->program
, ctx
->block
);
500 if (ptr
.type() == RegType::vgpr
)
501 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
502 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
503 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
506 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
508 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
509 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
510 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
511 sop2
->definitions
[0] = Definition(dst
);
513 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
514 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
517 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
518 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
520 Builder
bld(ctx
->program
, ctx
->block
);
521 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
522 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
523 if (src1
.type() == RegType::sgpr
) {
524 if (commutative
&& src0
.type() == RegType::vgpr
) {
528 } else if (src0
.type() == RegType::vgpr
&&
529 op
!= aco_opcode::v_madmk_f32
&&
530 op
!= aco_opcode::v_madak_f32
&&
531 op
!= aco_opcode::v_madmk_f16
&&
532 op
!= aco_opcode::v_madak_f16
) {
533 /* If the instruction is not commutative, we emit a VOP3A instruction */
534 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
537 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
541 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
542 assert(dst
.size() == 1);
543 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
544 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
546 bld
.vop2(op
, Definition(dst
), src0
, src1
);
550 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
551 bool flush_denorms
= false)
553 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
554 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
555 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
557 /* ensure that the instruction has at most 1 sgpr operand
558 * The optimizer will inline constants for us */
559 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
560 src0
= as_vgpr(ctx
, src0
);
561 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
562 src1
= as_vgpr(ctx
, src1
);
563 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
564 src2
= as_vgpr(ctx
, src2
);
566 Builder
bld(ctx
->program
, ctx
->block
);
567 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
568 assert(dst
.size() == 1);
569 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
570 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
572 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
576 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
578 Builder
bld(ctx
->program
, ctx
->block
);
579 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
582 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
584 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
585 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
586 assert(src0
.size() == src1
.size());
588 aco_ptr
<Instruction
> vopc
;
589 if (src1
.type() == RegType::sgpr
) {
590 if (src0
.type() == RegType::vgpr
) {
591 /* to swap the operands, we might also have to change the opcode */
593 case aco_opcode::v_cmp_lt_f32
:
594 op
= aco_opcode::v_cmp_gt_f32
;
596 case aco_opcode::v_cmp_ge_f32
:
597 op
= aco_opcode::v_cmp_le_f32
;
599 case aco_opcode::v_cmp_lt_i32
:
600 op
= aco_opcode::v_cmp_gt_i32
;
602 case aco_opcode::v_cmp_ge_i32
:
603 op
= aco_opcode::v_cmp_le_i32
;
605 case aco_opcode::v_cmp_lt_u32
:
606 op
= aco_opcode::v_cmp_gt_u32
;
608 case aco_opcode::v_cmp_ge_u32
:
609 op
= aco_opcode::v_cmp_le_u32
;
611 case aco_opcode::v_cmp_lt_f64
:
612 op
= aco_opcode::v_cmp_gt_f64
;
614 case aco_opcode::v_cmp_ge_f64
:
615 op
= aco_opcode::v_cmp_le_f64
;
617 case aco_opcode::v_cmp_lt_i64
:
618 op
= aco_opcode::v_cmp_gt_i64
;
620 case aco_opcode::v_cmp_ge_i64
:
621 op
= aco_opcode::v_cmp_le_i64
;
623 case aco_opcode::v_cmp_lt_u64
:
624 op
= aco_opcode::v_cmp_gt_u64
;
626 case aco_opcode::v_cmp_ge_u64
:
627 op
= aco_opcode::v_cmp_le_u64
;
629 default: /* eq and ne are commutative */
636 src1
= as_vgpr(ctx
, src1
);
640 Builder
bld(ctx
->program
, ctx
->block
);
641 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
644 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
646 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
647 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
648 Builder
bld(ctx
->program
, ctx
->block
);
650 assert(dst
.regClass() == bld
.lm
);
651 assert(src0
.type() == RegType::sgpr
);
652 assert(src1
.type() == RegType::sgpr
);
653 assert(src0
.regClass() == src1
.regClass());
655 /* Emit the SALU comparison instruction */
656 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
657 /* Turn the result into a per-lane bool */
658 bool_to_vector_condition(ctx
, cmp
, dst
);
661 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
662 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
664 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
665 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
666 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
667 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
669 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
670 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
671 aco_opcode op
= use_valu
? v_op
: s_op
;
672 assert(op
!= aco_opcode::num_opcodes
);
673 assert(dst
.regClass() == ctx
->program
->lane_mask
);
676 emit_vopc_instruction(ctx
, instr
, op
, dst
);
678 emit_sopc_instruction(ctx
, instr
, op
, dst
);
681 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
683 Builder
bld(ctx
->program
, ctx
->block
);
684 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
685 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
687 assert(dst
.regClass() == bld
.lm
);
688 assert(src0
.regClass() == bld
.lm
);
689 assert(src1
.regClass() == bld
.lm
);
691 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
694 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
696 Builder
bld(ctx
->program
, ctx
->block
);
697 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
698 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
699 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
701 assert(cond
.regClass() == bld
.lm
);
703 if (dst
.type() == RegType::vgpr
) {
704 aco_ptr
<Instruction
> bcsel
;
705 if (dst
.size() == 1) {
706 then
= as_vgpr(ctx
, then
);
707 els
= as_vgpr(ctx
, els
);
709 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
710 } else if (dst
.size() == 2) {
711 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
712 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
713 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
714 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
716 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
717 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
719 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
721 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
722 nir_print_instr(&instr
->instr
, stderr
);
723 fprintf(stderr
, "\n");
728 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
729 assert(dst
.regClass() == bld
.lm
);
730 assert(then
.regClass() == bld
.lm
);
731 assert(els
.regClass() == bld
.lm
);
734 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
735 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
736 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
737 assert(dst
.size() == then
.size());
738 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
739 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
741 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
742 nir_print_instr(&instr
->instr
, stderr
);
743 fprintf(stderr
, "\n");
748 /* divergent boolean bcsel
749 * this implements bcsel on bools: dst = s0 ? s1 : s2
750 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
751 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
753 if (cond
.id() != then
.id())
754 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
756 if (cond
.id() == els
.id())
757 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
759 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
760 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
763 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
764 aco_opcode op
, uint32_t undo
)
766 /* multiply by 16777216 to handle denormals */
767 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
768 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
769 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
770 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
771 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
773 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
775 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
778 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
780 if (ctx
->block
->fp_mode
.denorm32
== 0) {
781 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
785 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
788 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
790 if (ctx
->block
->fp_mode
.denorm32
== 0) {
791 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
795 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
798 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
800 if (ctx
->block
->fp_mode
.denorm32
== 0) {
801 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
805 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
808 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
810 if (ctx
->block
->fp_mode
.denorm32
== 0) {
811 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
815 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
818 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
820 if (ctx
->options
->chip_class
>= GFX7
)
821 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
823 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
824 /* TODO: create more efficient code! */
825 if (val
.type() == RegType::sgpr
)
826 val
= as_vgpr(ctx
, val
);
828 /* Split the input value. */
829 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
830 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
832 /* Extract the exponent and compute the unbiased value. */
833 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
835 /* Extract the fractional part. */
836 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
837 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
839 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
840 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
842 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
843 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
844 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
845 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
846 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
848 /* Get the sign bit. */
849 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
851 /* Decide the operation to apply depending on the unbiased exponent. */
852 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
853 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
854 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
855 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
856 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
857 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
859 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
862 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
864 if (ctx
->options
->chip_class
>= GFX7
)
865 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
867 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
868 Temp src0
= as_vgpr(ctx
, val
);
870 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
871 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
873 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
874 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
875 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
877 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
879 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
880 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
882 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
883 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
885 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
887 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
888 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
890 return add
->definitions
[0].getTemp();
893 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
895 if (!instr
->dest
.dest
.is_ssa
) {
896 fprintf(stderr
, "nir alu dst not in ssa: ");
897 nir_print_instr(&instr
->instr
, stderr
);
898 fprintf(stderr
, "\n");
901 Builder
bld(ctx
->program
, ctx
->block
);
902 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
907 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
908 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
909 for (unsigned i
= 0; i
< instr
->dest
.dest
.ssa
.num_components
; ++i
) {
910 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
911 vec
->operands
[i
] = Operand
{elems
[i
]};
913 vec
->definitions
[0] = Definition(dst
);
914 ctx
->block
->instructions
.emplace_back(std::move(vec
));
915 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
919 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
920 aco_ptr
<Instruction
> mov
;
921 if (dst
.type() == RegType::sgpr
) {
922 if (src
.type() == RegType::vgpr
)
923 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
924 else if (src
.regClass() == s1
)
925 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
926 else if (src
.regClass() == s2
)
927 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
929 unreachable("wrong src register class for nir_op_imov");
930 } else if (dst
.regClass() == v1
) {
931 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
932 } else if (dst
.regClass() == v2
) {
933 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
935 nir_print_instr(&instr
->instr
, stderr
);
936 unreachable("Should have been lowered to scalar.");
941 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
942 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
943 assert(src
.regClass() == bld
.lm
);
944 assert(dst
.regClass() == bld
.lm
);
945 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
946 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
947 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
948 } else if (dst
.regClass() == v1
) {
949 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
950 } else if (dst
.type() == RegType::sgpr
) {
951 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
952 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
954 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
955 nir_print_instr(&instr
->instr
, stderr
);
956 fprintf(stderr
, "\n");
961 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
962 if (dst
.regClass() == v1
) {
963 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
964 } else if (dst
.regClass() == s1
) {
965 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
966 } else if (dst
.size() == 2) {
967 Temp src0
= bld
.tmp(dst
.type(), 1);
968 Temp src1
= bld
.tmp(dst
.type(), 1);
969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
971 if (dst
.regClass() == s2
) {
972 Temp carry
= bld
.tmp(s1
);
973 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
974 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
975 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
977 Temp lower
= bld
.tmp(v1
);
978 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
979 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
980 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
983 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
984 nir_print_instr(&instr
->instr
, stderr
);
985 fprintf(stderr
, "\n");
990 if (dst
.regClass() == s1
) {
991 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
992 } else if (dst
.regClass() == v1
) {
993 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
994 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
996 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
997 nir_print_instr(&instr
->instr
, stderr
);
998 fprintf(stderr
, "\n");
1002 case nir_op_isign
: {
1003 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1004 if (dst
.regClass() == s1
) {
1005 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1006 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1007 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1008 } else if (dst
.regClass() == s2
) {
1009 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1011 if (ctx
->program
->chip_class
>= GFX8
)
1012 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1014 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1015 /* SCC gets zero-extended to 64 bit */
1016 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1017 } else if (dst
.regClass() == v1
) {
1018 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1019 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1020 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1021 } else if (dst
.regClass() == v2
) {
1022 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1023 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1024 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1025 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1026 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1027 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1029 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1030 nir_print_instr(&instr
->instr
, stderr
);
1031 fprintf(stderr
, "\n");
1036 if (dst
.regClass() == v1
) {
1037 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1038 } else if (dst
.regClass() == s1
) {
1039 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1041 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1042 nir_print_instr(&instr
->instr
, stderr
);
1043 fprintf(stderr
, "\n");
1048 if (dst
.regClass() == v1
) {
1049 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1050 } else if (dst
.regClass() == s1
) {
1051 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1053 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1054 nir_print_instr(&instr
->instr
, stderr
);
1055 fprintf(stderr
, "\n");
1060 if (dst
.regClass() == v1
) {
1061 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1062 } else if (dst
.regClass() == s1
) {
1063 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1065 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1066 nir_print_instr(&instr
->instr
, stderr
);
1067 fprintf(stderr
, "\n");
1072 if (dst
.regClass() == v1
) {
1073 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1074 } else if (dst
.regClass() == s1
) {
1075 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1077 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1078 nir_print_instr(&instr
->instr
, stderr
);
1079 fprintf(stderr
, "\n");
1084 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1085 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1086 } else if (dst
.regClass() == v1
) {
1087 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1088 } else if (dst
.regClass() == s1
) {
1089 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1090 } else if (dst
.regClass() == s2
) {
1091 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1093 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1094 nir_print_instr(&instr
->instr
, stderr
);
1095 fprintf(stderr
, "\n");
1100 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1101 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1102 } else if (dst
.regClass() == v1
) {
1103 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1104 } else if (dst
.regClass() == s1
) {
1105 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1106 } else if (dst
.regClass() == s2
) {
1107 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1109 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1110 nir_print_instr(&instr
->instr
, stderr
);
1111 fprintf(stderr
, "\n");
1116 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1117 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1118 } else if (dst
.regClass() == v1
) {
1119 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1120 } else if (dst
.regClass() == s1
) {
1121 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1122 } else if (dst
.regClass() == s2
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1134 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1135 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1136 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1137 } else if (dst
.regClass() == v2
) {
1138 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1139 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1140 } else if (dst
.regClass() == s2
) {
1141 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1142 } else if (dst
.regClass() == s1
) {
1143 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1145 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1146 nir_print_instr(&instr
->instr
, stderr
);
1147 fprintf(stderr
, "\n");
1152 if (dst
.regClass() == v1
) {
1153 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1154 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1155 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1156 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1157 } else if (dst
.regClass() == v2
) {
1158 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1159 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1160 } else if (dst
.regClass() == s1
) {
1161 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1162 } else if (dst
.regClass() == s2
) {
1163 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1165 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1166 nir_print_instr(&instr
->instr
, stderr
);
1167 fprintf(stderr
, "\n");
1172 if (dst
.regClass() == v1
) {
1173 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1174 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1175 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1176 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1177 } else if (dst
.regClass() == v2
) {
1178 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1179 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1180 } else if (dst
.regClass() == s1
) {
1181 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1182 } else if (dst
.regClass() == s2
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1191 case nir_op_find_lsb
: {
1192 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1193 if (src
.regClass() == s1
) {
1194 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1195 } else if (src
.regClass() == v1
) {
1196 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1197 } else if (src
.regClass() == s2
) {
1198 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1200 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1201 nir_print_instr(&instr
->instr
, stderr
);
1202 fprintf(stderr
, "\n");
1206 case nir_op_ufind_msb
:
1207 case nir_op_ifind_msb
: {
1208 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1209 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1210 aco_opcode op
= src
.regClass() == s2
?
1211 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1212 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1213 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1215 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1216 Operand(src
.size() * 32u - 1u), msb_rev
);
1217 Temp msb
= sub
.def(0).getTemp();
1218 Temp carry
= sub
.def(1).getTemp();
1220 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1221 } else if (src
.regClass() == v1
) {
1222 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1223 Temp msb_rev
= bld
.tmp(v1
);
1224 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1225 Temp msb
= bld
.tmp(v1
);
1226 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1227 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1235 case nir_op_bitfield_reverse
: {
1236 if (dst
.regClass() == s1
) {
1237 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1238 } else if (dst
.regClass() == v1
) {
1239 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1241 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1242 nir_print_instr(&instr
->instr
, stderr
);
1243 fprintf(stderr
, "\n");
1248 if (dst
.regClass() == s1
) {
1249 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1253 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1254 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1255 if (dst
.regClass() == v1
) {
1256 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1260 assert(src0
.size() == 2 && src1
.size() == 2);
1261 Temp src00
= bld
.tmp(src0
.type(), 1);
1262 Temp src01
= bld
.tmp(dst
.type(), 1);
1263 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1264 Temp src10
= bld
.tmp(src1
.type(), 1);
1265 Temp src11
= bld
.tmp(dst
.type(), 1);
1266 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1268 if (dst
.regClass() == s2
) {
1269 Temp carry
= bld
.tmp(s1
);
1270 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1271 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1272 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1273 } else if (dst
.regClass() == v2
) {
1274 Temp dst0
= bld
.tmp(v1
);
1275 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1276 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1277 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1279 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1280 nir_print_instr(&instr
->instr
, stderr
);
1281 fprintf(stderr
, "\n");
1285 case nir_op_uadd_sat
: {
1286 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1287 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1288 if (dst
.regClass() == s1
) {
1289 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1290 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1292 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1293 } else if (dst
.regClass() == v1
) {
1294 if (ctx
->options
->chip_class
>= GFX9
) {
1295 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1296 add
->operands
[0] = Operand(src0
);
1297 add
->operands
[1] = Operand(src1
);
1298 add
->definitions
[0] = Definition(dst
);
1300 ctx
->block
->instructions
.emplace_back(std::move(add
));
1302 if (src1
.regClass() != v1
)
1303 std::swap(src0
, src1
);
1304 assert(src1
.regClass() == v1
);
1305 Temp tmp
= bld
.tmp(v1
);
1306 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1307 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1310 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1311 nir_print_instr(&instr
->instr
, stderr
);
1312 fprintf(stderr
, "\n");
1316 case nir_op_uadd_carry
: {
1317 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1318 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1319 if (dst
.regClass() == s1
) {
1320 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1323 if (dst
.regClass() == v1
) {
1324 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1325 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1329 Temp src00
= bld
.tmp(src0
.type(), 1);
1330 Temp src01
= bld
.tmp(dst
.type(), 1);
1331 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1332 Temp src10
= bld
.tmp(src1
.type(), 1);
1333 Temp src11
= bld
.tmp(dst
.type(), 1);
1334 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1335 if (dst
.regClass() == s2
) {
1336 Temp carry
= bld
.tmp(s1
);
1337 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1338 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1339 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1340 } else if (dst
.regClass() == v2
) {
1341 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1342 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1343 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1344 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1346 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1347 nir_print_instr(&instr
->instr
, stderr
);
1348 fprintf(stderr
, "\n");
1353 if (dst
.regClass() == s1
) {
1354 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1358 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1359 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1360 if (dst
.regClass() == v1
) {
1361 bld
.vsub32(Definition(dst
), src0
, src1
);
1365 Temp src00
= bld
.tmp(src0
.type(), 1);
1366 Temp src01
= bld
.tmp(dst
.type(), 1);
1367 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1368 Temp src10
= bld
.tmp(src1
.type(), 1);
1369 Temp src11
= bld
.tmp(dst
.type(), 1);
1370 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1371 if (dst
.regClass() == s2
) {
1372 Temp carry
= bld
.tmp(s1
);
1373 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1374 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1375 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1376 } else if (dst
.regClass() == v2
) {
1377 Temp lower
= bld
.tmp(v1
);
1378 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1379 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1380 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1382 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1383 nir_print_instr(&instr
->instr
, stderr
);
1384 fprintf(stderr
, "\n");
1388 case nir_op_usub_borrow
: {
1389 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1390 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1391 if (dst
.regClass() == s1
) {
1392 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1394 } else if (dst
.regClass() == v1
) {
1395 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1396 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1400 Temp src00
= bld
.tmp(src0
.type(), 1);
1401 Temp src01
= bld
.tmp(dst
.type(), 1);
1402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1403 Temp src10
= bld
.tmp(src1
.type(), 1);
1404 Temp src11
= bld
.tmp(dst
.type(), 1);
1405 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1406 if (dst
.regClass() == s2
) {
1407 Temp borrow
= bld
.tmp(s1
);
1408 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1409 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1410 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1411 } else if (dst
.regClass() == v2
) {
1412 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1413 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1414 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1415 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1417 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1418 nir_print_instr(&instr
->instr
, stderr
);
1419 fprintf(stderr
, "\n");
1424 if (dst
.regClass() == v1
) {
1425 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1426 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1427 } else if (dst
.regClass() == s1
) {
1428 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1430 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1431 nir_print_instr(&instr
->instr
, stderr
);
1432 fprintf(stderr
, "\n");
1436 case nir_op_umul_high
: {
1437 if (dst
.regClass() == v1
) {
1438 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1439 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1440 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1441 } else if (dst
.regClass() == s1
) {
1442 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1443 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1444 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1446 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1447 nir_print_instr(&instr
->instr
, stderr
);
1448 fprintf(stderr
, "\n");
1452 case nir_op_imul_high
: {
1453 if (dst
.regClass() == v1
) {
1454 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1455 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1456 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1457 } else if (dst
.regClass() == s1
) {
1458 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1459 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1460 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1462 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1463 nir_print_instr(&instr
->instr
, stderr
);
1464 fprintf(stderr
, "\n");
1469 if (dst
.size() == 1) {
1470 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1471 } else if (dst
.size() == 2) {
1472 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1473 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1475 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1476 nir_print_instr(&instr
->instr
, stderr
);
1477 fprintf(stderr
, "\n");
1482 if (dst
.size() == 1) {
1483 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1484 } else if (dst
.size() == 2) {
1485 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1486 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1488 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1489 nir_print_instr(&instr
->instr
, stderr
);
1490 fprintf(stderr
, "\n");
1495 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1496 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1497 if (dst
.size() == 1) {
1498 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1499 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1501 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1502 } else if (dst
.size() == 2) {
1503 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1504 get_alu_src(ctx
, instr
->src
[0]),
1505 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1506 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1509 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1510 nir_print_instr(&instr
->instr
, stderr
);
1511 fprintf(stderr
, "\n");
1516 if (dst
.size() == 1) {
1517 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1518 } else if (dst
.size() == 2) {
1519 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1520 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
),
1521 get_alu_src(ctx
, instr
->src
[0]),
1522 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1523 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1525 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1526 get_alu_src(ctx
, instr
->src
[0]),
1527 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1530 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1531 nir_print_instr(&instr
->instr
, stderr
);
1532 fprintf(stderr
, "\n");
1537 if (dst
.size() == 1) {
1538 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1539 } else if (dst
.size() == 2) {
1540 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1541 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
),
1542 get_alu_src(ctx
, instr
->src
[0]),
1543 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1544 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1546 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1547 get_alu_src(ctx
, instr
->src
[0]),
1548 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1551 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1552 nir_print_instr(&instr
->instr
, stderr
);
1553 fprintf(stderr
, "\n");
1557 case nir_op_fmax3
: {
1558 if (dst
.size() == 1) {
1559 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1561 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1562 nir_print_instr(&instr
->instr
, stderr
);
1563 fprintf(stderr
, "\n");
1567 case nir_op_fmin3
: {
1568 if (dst
.size() == 1) {
1569 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1571 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1572 nir_print_instr(&instr
->instr
, stderr
);
1573 fprintf(stderr
, "\n");
1577 case nir_op_fmed3
: {
1578 if (dst
.size() == 1) {
1579 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1581 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1582 nir_print_instr(&instr
->instr
, stderr
);
1583 fprintf(stderr
, "\n");
1587 case nir_op_umax3
: {
1588 if (dst
.size() == 1) {
1589 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1591 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1592 nir_print_instr(&instr
->instr
, stderr
);
1593 fprintf(stderr
, "\n");
1597 case nir_op_umin3
: {
1598 if (dst
.size() == 1) {
1599 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1601 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1602 nir_print_instr(&instr
->instr
, stderr
);
1603 fprintf(stderr
, "\n");
1607 case nir_op_umed3
: {
1608 if (dst
.size() == 1) {
1609 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1611 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1612 nir_print_instr(&instr
->instr
, stderr
);
1613 fprintf(stderr
, "\n");
1617 case nir_op_imax3
: {
1618 if (dst
.size() == 1) {
1619 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1627 case nir_op_imin3
: {
1628 if (dst
.size() == 1) {
1629 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1632 nir_print_instr(&instr
->instr
, stderr
);
1633 fprintf(stderr
, "\n");
1637 case nir_op_imed3
: {
1638 if (dst
.size() == 1) {
1639 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1641 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1642 nir_print_instr(&instr
->instr
, stderr
);
1643 fprintf(stderr
, "\n");
1647 case nir_op_cube_face_coord
: {
1648 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1649 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1650 emit_extract_vector(ctx
, in
, 1, v1
),
1651 emit_extract_vector(ctx
, in
, 2, v1
) };
1652 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1653 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1654 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1655 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1656 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1657 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1658 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1661 case nir_op_cube_face_index
: {
1662 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1663 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1664 emit_extract_vector(ctx
, in
, 1, v1
),
1665 emit_extract_vector(ctx
, in
, 2, v1
) };
1666 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1669 case nir_op_bcsel
: {
1670 emit_bcsel(ctx
, instr
, dst
);
1674 if (dst
.size() == 1) {
1675 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1676 } else if (dst
.size() == 2) {
1677 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1679 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1680 nir_print_instr(&instr
->instr
, stderr
);
1681 fprintf(stderr
, "\n");
1686 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1687 if (dst
.size() == 1) {
1688 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1689 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1690 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1691 } else if (dst
.size() == 2) {
1692 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1693 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1694 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1695 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1696 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1697 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1700 nir_print_instr(&instr
->instr
, stderr
);
1701 fprintf(stderr
, "\n");
1706 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1707 if (dst
.size() == 1) {
1708 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1709 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1710 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1711 } else if (dst
.size() == 2) {
1712 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1713 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1714 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1716 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1717 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1726 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1727 if (dst
.size() == 1) {
1728 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1729 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1730 // TODO: confirm that this holds under any circumstances
1731 } else if (dst
.size() == 2) {
1732 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1733 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1736 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1737 nir_print_instr(&instr
->instr
, stderr
);
1738 fprintf(stderr
, "\n");
1742 case nir_op_flog2
: {
1743 if (dst
.size() == 1) {
1744 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1746 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1747 nir_print_instr(&instr
->instr
, stderr
);
1748 fprintf(stderr
, "\n");
1753 if (dst
.size() == 1) {
1754 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1755 } else if (dst
.size() == 2) {
1756 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1758 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1759 nir_print_instr(&instr
->instr
, stderr
);
1760 fprintf(stderr
, "\n");
1764 case nir_op_fexp2
: {
1765 if (dst
.size() == 1) {
1766 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1768 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1769 nir_print_instr(&instr
->instr
, stderr
);
1770 fprintf(stderr
, "\n");
1774 case nir_op_fsqrt
: {
1775 if (dst
.size() == 1) {
1776 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1777 } else if (dst
.size() == 2) {
1778 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1780 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1781 nir_print_instr(&instr
->instr
, stderr
);
1782 fprintf(stderr
, "\n");
1786 case nir_op_ffract
: {
1787 if (dst
.size() == 1) {
1788 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1789 } else if (dst
.size() == 2) {
1790 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1792 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1793 nir_print_instr(&instr
->instr
, stderr
);
1794 fprintf(stderr
, "\n");
1798 case nir_op_ffloor
: {
1799 if (dst
.size() == 1) {
1800 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1801 } else if (dst
.size() == 2) {
1802 emit_floor_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1804 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1805 nir_print_instr(&instr
->instr
, stderr
);
1806 fprintf(stderr
, "\n");
1810 case nir_op_fceil
: {
1811 if (dst
.size() == 1) {
1812 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1813 } else if (dst
.size() == 2) {
1814 if (ctx
->options
->chip_class
>= GFX7
) {
1815 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1817 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1818 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1820 /* trunc = trunc(src0)
1821 * if (src0 > 0.0 && src0 != trunc)
1824 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1825 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1826 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1827 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1828 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1829 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1830 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1833 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1834 nir_print_instr(&instr
->instr
, stderr
);
1835 fprintf(stderr
, "\n");
1839 case nir_op_ftrunc
: {
1840 if (dst
.size() == 1) {
1841 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1842 } else if (dst
.size() == 2) {
1843 emit_trunc_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1845 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1846 nir_print_instr(&instr
->instr
, stderr
);
1847 fprintf(stderr
, "\n");
1851 case nir_op_fround_even
: {
1852 if (dst
.size() == 1) {
1853 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1854 } else if (dst
.size() == 2) {
1855 if (ctx
->options
->chip_class
>= GFX7
) {
1856 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1858 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1859 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1861 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1864 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1865 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1866 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1867 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1868 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1869 tmp
= sub
->definitions
[0].getTemp();
1871 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
1872 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
1873 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
1874 Temp cond
= vop3
->definitions
[0].getTemp();
1876 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
1877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
1878 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
1879 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
1881 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1884 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1885 nir_print_instr(&instr
->instr
, stderr
);
1886 fprintf(stderr
, "\n");
1892 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1893 aco_ptr
<Instruction
> norm
;
1894 if (dst
.size() == 1) {
1895 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
1896 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
1898 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1899 if (ctx
->options
->chip_class
< GFX9
)
1900 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1902 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1903 bld
.vop1(opcode
, Definition(dst
), tmp
);
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_ldexp
: {
1912 if (dst
.size() == 1) {
1913 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1914 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1915 get_alu_src(ctx
, instr
->src
[1]));
1916 } else if (dst
.size() == 2) {
1917 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1918 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1919 get_alu_src(ctx
, instr
->src
[1]));
1921 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1922 nir_print_instr(&instr
->instr
, stderr
);
1923 fprintf(stderr
, "\n");
1927 case nir_op_frexp_sig
: {
1928 if (dst
.size() == 1) {
1929 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
),
1930 get_alu_src(ctx
, instr
->src
[0]));
1931 } else if (dst
.size() == 2) {
1932 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
),
1933 get_alu_src(ctx
, instr
->src
[0]));
1935 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1936 nir_print_instr(&instr
->instr
, stderr
);
1937 fprintf(stderr
, "\n");
1941 case nir_op_frexp_exp
: {
1942 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1943 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
),
1944 get_alu_src(ctx
, instr
->src
[0]));
1945 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1946 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
),
1947 get_alu_src(ctx
, instr
->src
[0]));
1949 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1950 nir_print_instr(&instr
->instr
, stderr
);
1951 fprintf(stderr
, "\n");
1955 case nir_op_fsign
: {
1956 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
1957 if (dst
.size() == 1) {
1958 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1959 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
1960 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1961 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
1962 } else if (dst
.size() == 2) {
1963 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1964 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
1965 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
1967 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1968 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
1969 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
1971 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
1973 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1974 nir_print_instr(&instr
->instr
, stderr
);
1975 fprintf(stderr
, "\n");
1980 case nir_op_f2f16_rtne
: {
1981 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1982 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
1983 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
1984 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
1985 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
1988 case nir_op_f2f16_rtz
: {
1989 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1990 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
1991 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
1992 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
1993 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
1996 case nir_op_f2f32
: {
1997 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
1998 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
1999 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2000 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2002 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2003 nir_print_instr(&instr
->instr
, stderr
);
2004 fprintf(stderr
, "\n");
2008 case nir_op_f2f64
: {
2009 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2010 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2011 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2012 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2015 case nir_op_i2f32
: {
2016 assert(dst
.size() == 1);
2017 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2020 case nir_op_i2f64
: {
2021 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2022 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2023 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2024 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2025 RegClass rc
= RegClass(src
.type(), 1);
2026 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2027 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2028 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2029 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2030 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2031 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2034 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2035 nir_print_instr(&instr
->instr
, stderr
);
2036 fprintf(stderr
, "\n");
2040 case nir_op_u2f32
: {
2041 assert(dst
.size() == 1);
2042 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2045 case nir_op_u2f64
: {
2046 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2047 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2048 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2049 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2050 RegClass rc
= RegClass(src
.type(), 1);
2051 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2052 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2053 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2054 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2055 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2056 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2058 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2059 nir_print_instr(&instr
->instr
, stderr
);
2060 fprintf(stderr
, "\n");
2064 case nir_op_f2i16
: {
2065 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2066 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2067 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2068 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2069 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2071 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2073 if (dst
.type() == RegType::vgpr
)
2074 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2076 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2079 case nir_op_f2u16
: {
2080 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2081 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2082 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2083 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2084 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2086 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2088 if (dst
.type() == RegType::vgpr
)
2089 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2091 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2094 case nir_op_f2i32
: {
2095 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2096 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2097 if (dst
.type() == RegType::vgpr
)
2098 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2100 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2101 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2103 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2104 if (dst
.type() == RegType::vgpr
)
2105 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2107 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2108 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2111 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2112 nir_print_instr(&instr
->instr
, stderr
);
2113 fprintf(stderr
, "\n");
2117 case nir_op_f2u32
: {
2118 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2119 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2120 if (dst
.type() == RegType::vgpr
)
2121 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2123 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2124 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2126 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2127 if (dst
.type() == RegType::vgpr
)
2128 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2130 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2131 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2134 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2135 nir_print_instr(&instr
->instr
, stderr
);
2136 fprintf(stderr
, "\n");
2140 case nir_op_f2i64
: {
2141 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2142 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2143 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2144 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2145 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2146 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2147 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2148 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2149 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2150 Temp new_exponent
= bld
.tmp(v1
);
2151 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2152 if (ctx
->program
->chip_class
>= GFX8
)
2153 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2155 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2156 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2157 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2158 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2159 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2160 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2161 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2162 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2163 Temp new_lower
= bld
.tmp(v1
);
2164 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2165 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2166 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2168 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2169 if (src
.type() == RegType::vgpr
)
2170 src
= bld
.as_uniform(src
);
2171 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2172 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2173 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2174 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2175 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2176 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2177 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2178 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2179 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2180 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2181 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2182 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2183 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2184 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2185 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2186 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2187 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2188 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2189 Temp borrow
= bld
.tmp(s1
);
2190 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2191 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2192 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2194 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2195 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2196 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2197 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2198 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2199 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2200 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2201 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2202 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2203 if (dst
.type() == RegType::sgpr
) {
2204 lower
= bld
.as_uniform(lower
);
2205 upper
= bld
.as_uniform(upper
);
2207 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2210 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2211 nir_print_instr(&instr
->instr
, stderr
);
2212 fprintf(stderr
, "\n");
2216 case nir_op_f2u64
: {
2217 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2218 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2219 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2220 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2221 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2222 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2223 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2224 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2225 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2226 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2227 Temp new_exponent
= bld
.tmp(v1
);
2228 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2229 if (ctx
->program
->chip_class
>= GFX8
)
2230 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2232 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2233 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2234 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2235 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2236 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2237 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2238 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2239 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2241 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2242 if (src
.type() == RegType::vgpr
)
2243 src
= bld
.as_uniform(src
);
2244 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2245 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2246 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2247 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2248 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2249 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2250 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2251 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2252 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2253 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2254 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2255 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2256 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2257 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2258 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2259 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2260 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2261 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2263 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2264 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2265 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2266 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2267 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2268 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2269 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2270 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2271 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2272 if (dst
.type() == RegType::sgpr
) {
2273 lower
= bld
.as_uniform(lower
);
2274 upper
= bld
.as_uniform(upper
);
2276 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2279 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2280 nir_print_instr(&instr
->instr
, stderr
);
2281 fprintf(stderr
, "\n");
2285 case nir_op_b2f32
: {
2286 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2287 assert(src
.regClass() == bld
.lm
);
2289 if (dst
.regClass() == s1
) {
2290 src
= bool_to_scalar_condition(ctx
, src
);
2291 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2292 } else if (dst
.regClass() == v1
) {
2293 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2295 unreachable("Wrong destination register class for nir_op_b2f32.");
2299 case nir_op_b2f64
: {
2300 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2301 assert(src
.regClass() == bld
.lm
);
2303 if (dst
.regClass() == s2
) {
2304 src
= bool_to_scalar_condition(ctx
, src
);
2305 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2306 } else if (dst
.regClass() == v2
) {
2307 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2308 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2309 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2311 unreachable("Wrong destination register class for nir_op_b2f64.");
2317 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2318 /* we can actually just say dst = src */
2319 if (src
.regClass() == s1
)
2320 bld
.copy(Definition(dst
), src
);
2322 emit_extract_vector(ctx
, src
, 0, dst
);
2325 case nir_op_i2i16
: {
2326 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2327 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2328 if (dst
.regClass() == s1
) {
2329 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2331 assert(src
.regClass() == v1b
);
2332 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2333 sdwa
->operands
[0] = Operand(src
);
2334 sdwa
->definitions
[0] = Definition(dst
);
2335 sdwa
->sel
[0] = sdwa_sbyte
;
2336 sdwa
->dst_sel
= sdwa_sword
;
2337 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2340 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2341 /* we can actually just say dst = src */
2342 if (src
.regClass() == s1
)
2343 bld
.copy(Definition(dst
), src
);
2345 emit_extract_vector(ctx
, src
, 0, dst
);
2349 case nir_op_u2u16
: {
2350 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2351 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2352 if (dst
.regClass() == s1
)
2353 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2355 assert(src
.regClass() == v1b
);
2356 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2357 sdwa
->operands
[0] = Operand(src
);
2358 sdwa
->definitions
[0] = Definition(dst
);
2359 sdwa
->sel
[0] = sdwa_ubyte
;
2360 sdwa
->dst_sel
= sdwa_uword
;
2361 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2364 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2365 /* we can actually just say dst = src */
2366 if (src
.regClass() == s1
)
2367 bld
.copy(Definition(dst
), src
);
2369 emit_extract_vector(ctx
, src
, 0, dst
);
2373 case nir_op_i2i32
: {
2374 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2375 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2376 if (dst
.regClass() == s1
) {
2377 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2379 assert(src
.regClass() == v1b
);
2380 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2381 sdwa
->operands
[0] = Operand(src
);
2382 sdwa
->definitions
[0] = Definition(dst
);
2383 sdwa
->sel
[0] = sdwa_sbyte
;
2384 sdwa
->dst_sel
= sdwa_sdword
;
2385 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2387 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2388 if (dst
.regClass() == s1
) {
2389 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2391 assert(src
.regClass() == v2b
);
2392 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2393 sdwa
->operands
[0] = Operand(src
);
2394 sdwa
->definitions
[0] = Definition(dst
);
2395 sdwa
->sel
[0] = sdwa_sword
;
2396 sdwa
->dst_sel
= sdwa_udword
;
2397 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2399 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2400 /* we can actually just say dst = src, as it would map the lower register */
2401 emit_extract_vector(ctx
, src
, 0, dst
);
2403 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2404 nir_print_instr(&instr
->instr
, stderr
);
2405 fprintf(stderr
, "\n");
2409 case nir_op_u2u32
: {
2410 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2411 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2412 if (dst
.regClass() == s1
)
2413 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2415 assert(src
.regClass() == v1b
);
2416 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2417 sdwa
->operands
[0] = Operand(src
);
2418 sdwa
->definitions
[0] = Definition(dst
);
2419 sdwa
->sel
[0] = sdwa_ubyte
;
2420 sdwa
->dst_sel
= sdwa_udword
;
2421 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2423 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2424 if (dst
.regClass() == s1
) {
2425 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2427 assert(src
.regClass() == v2b
);
2428 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2429 sdwa
->operands
[0] = Operand(src
);
2430 sdwa
->definitions
[0] = Definition(dst
);
2431 sdwa
->sel
[0] = sdwa_uword
;
2432 sdwa
->dst_sel
= sdwa_udword
;
2433 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2435 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2436 /* we can actually just say dst = src, as it would map the lower register */
2437 emit_extract_vector(ctx
, src
, 0, dst
);
2439 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2440 nir_print_instr(&instr
->instr
, stderr
);
2441 fprintf(stderr
, "\n");
2445 case nir_op_i2i64
: {
2446 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2447 if (src
.regClass() == s1
) {
2448 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2449 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2450 } else if (src
.regClass() == v1
) {
2451 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2452 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2454 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2455 nir_print_instr(&instr
->instr
, stderr
);
2456 fprintf(stderr
, "\n");
2460 case nir_op_u2u64
: {
2461 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2462 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2463 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2465 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2466 nir_print_instr(&instr
->instr
, stderr
);
2467 fprintf(stderr
, "\n");
2472 case nir_op_b2i32
: {
2473 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2474 assert(src
.regClass() == bld
.lm
);
2476 if (dst
.regClass() == s1
) {
2477 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2478 bool_to_scalar_condition(ctx
, src
, dst
);
2479 } else if (dst
.regClass() == v1
) {
2480 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2482 unreachable("Invalid register class for b2i32");
2488 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2489 assert(dst
.regClass() == bld
.lm
);
2491 if (src
.type() == RegType::vgpr
) {
2492 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2493 assert(dst
.regClass() == bld
.lm
);
2494 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2495 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2497 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2499 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2500 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2502 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2503 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2505 bool_to_vector_condition(ctx
, tmp
, dst
);
2509 case nir_op_pack_64_2x32_split
: {
2510 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2511 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2513 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2516 case nir_op_unpack_64_2x32_split_x
:
2517 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2519 case nir_op_unpack_64_2x32_split_y
:
2520 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2522 case nir_op_unpack_32_2x16_split_x
:
2523 if (dst
.type() == RegType::vgpr
) {
2524 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2526 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2529 case nir_op_unpack_32_2x16_split_y
:
2530 if (dst
.type() == RegType::vgpr
) {
2531 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2533 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2536 case nir_op_pack_32_2x16_split
: {
2537 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2538 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2539 if (dst
.regClass() == v1
) {
2540 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2542 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2543 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2544 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2548 case nir_op_pack_half_2x16
: {
2549 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2551 if (dst
.regClass() == v1
) {
2552 Temp src0
= bld
.tmp(v1
);
2553 Temp src1
= bld
.tmp(v1
);
2554 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2555 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2556 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2558 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2559 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2560 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2563 nir_print_instr(&instr
->instr
, stderr
);
2564 fprintf(stderr
, "\n");
2568 case nir_op_unpack_half_2x16_split_x
: {
2569 if (dst
.regClass() == v1
) {
2570 Builder
bld(ctx
->program
, ctx
->block
);
2571 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2573 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2574 nir_print_instr(&instr
->instr
, stderr
);
2575 fprintf(stderr
, "\n");
2579 case nir_op_unpack_half_2x16_split_y
: {
2580 if (dst
.regClass() == v1
) {
2581 Builder
bld(ctx
->program
, ctx
->block
);
2582 /* TODO: use SDWA here */
2583 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2584 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2586 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2587 nir_print_instr(&instr
->instr
, stderr
);
2588 fprintf(stderr
, "\n");
2592 case nir_op_fquantize2f16
: {
2593 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2594 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2597 if (ctx
->program
->chip_class
>= GFX8
) {
2598 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2599 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2600 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2602 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2603 * so compare the result and flush to 0 if it's smaller.
2605 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2606 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2607 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2608 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2609 cmp_res
= vop3
->definitions
[0].getTemp();
2612 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2613 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2614 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2616 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2621 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2622 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2624 if (dst
.regClass() == s1
) {
2625 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2626 } else if (dst
.regClass() == v1
) {
2627 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2629 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2630 nir_print_instr(&instr
->instr
, stderr
);
2631 fprintf(stderr
, "\n");
2635 case nir_op_bitfield_select
: {
2636 /* (mask & insert) | (~mask & base) */
2637 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2638 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2639 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2641 /* dst = (insert & bitmask) | (base & ~bitmask) */
2642 if (dst
.regClass() == s1
) {
2643 aco_ptr
<Instruction
> sop2
;
2644 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2645 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2647 if (const_insert
&& const_bitmask
) {
2648 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2650 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2651 lhs
= Operand(insert
);
2655 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2656 if (const_base
&& const_bitmask
) {
2657 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2659 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2660 rhs
= Operand(base
);
2663 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2665 } else if (dst
.regClass() == v1
) {
2666 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2667 base
= as_vgpr(ctx
, base
);
2668 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2669 insert
= as_vgpr(ctx
, insert
);
2671 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2675 nir_print_instr(&instr
->instr
, stderr
);
2676 fprintf(stderr
, "\n");
2682 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2683 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2684 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2686 if (dst
.type() == RegType::sgpr
) {
2688 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2689 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2690 if (const_offset
&& const_bits
) {
2691 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2692 extract
= Operand(const_extract
);
2696 width
= Operand(const_bits
->u32
<< 16);
2698 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2700 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2704 if (dst
.regClass() == s1
) {
2705 if (instr
->op
== nir_op_ubfe
)
2706 opcode
= aco_opcode::s_bfe_u32
;
2708 opcode
= aco_opcode::s_bfe_i32
;
2709 } else if (dst
.regClass() == s2
) {
2710 if (instr
->op
== nir_op_ubfe
)
2711 opcode
= aco_opcode::s_bfe_u64
;
2713 opcode
= aco_opcode::s_bfe_i64
;
2715 unreachable("Unsupported BFE bit size");
2718 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2722 if (dst
.regClass() == v1
) {
2723 if (instr
->op
== nir_op_ubfe
)
2724 opcode
= aco_opcode::v_bfe_u32
;
2726 opcode
= aco_opcode::v_bfe_i32
;
2728 unreachable("Unsupported BFE bit size");
2731 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2735 case nir_op_bit_count
: {
2736 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2737 if (src
.regClass() == s1
) {
2738 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2739 } else if (src
.regClass() == v1
) {
2740 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2741 } else if (src
.regClass() == v2
) {
2742 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2743 emit_extract_vector(ctx
, src
, 1, v1
),
2744 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2745 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2746 } else if (src
.regClass() == s2
) {
2747 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2749 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2750 nir_print_instr(&instr
->instr
, stderr
);
2751 fprintf(stderr
, "\n");
2756 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2760 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2764 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2768 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2772 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2776 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2780 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2781 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2783 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2784 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2788 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2789 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2791 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2792 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2796 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2800 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2805 case nir_op_fddx_fine
:
2806 case nir_op_fddy_fine
:
2807 case nir_op_fddx_coarse
:
2808 case nir_op_fddy_coarse
: {
2809 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2810 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2811 if (instr
->op
== nir_op_fddx_fine
) {
2812 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2813 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2814 } else if (instr
->op
== nir_op_fddy_fine
) {
2815 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2816 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2818 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2819 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2820 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2822 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2826 if (ctx
->program
->chip_class
>= GFX8
) {
2827 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2828 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2830 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2831 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2832 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2834 emit_wqm(ctx
, tmp
, dst
, true);
2838 fprintf(stderr
, "Unknown NIR ALU instr: ");
2839 nir_print_instr(&instr
->instr
, stderr
);
2840 fprintf(stderr
, "\n");
2844 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2846 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2848 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2849 // which get truncated the lsb if double and msb if int
2850 // for now, we only use s_mov_b64 with 64bit inline constants
2851 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2852 assert(dst
.type() == RegType::sgpr
);
2854 Builder
bld(ctx
->program
, ctx
->block
);
2856 if (instr
->def
.bit_size
== 1) {
2857 assert(dst
.regClass() == bld
.lm
);
2858 int val
= instr
->value
[0].b
? -1 : 0;
2859 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2860 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2861 } else if (dst
.size() == 1) {
2862 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2864 assert(dst
.size() != 1);
2865 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2866 if (instr
->def
.bit_size
== 64)
2867 for (unsigned i
= 0; i
< dst
.size(); i
++)
2868 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2870 for (unsigned i
= 0; i
< dst
.size(); i
++)
2871 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2873 vec
->definitions
[0] = Definition(dst
);
2874 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2878 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2880 uint32_t new_mask
= 0;
2881 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2882 if (mask
& (1u << i
))
2883 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2887 Operand
load_lds_size_m0(isel_context
*ctx
)
2889 /* TODO: m0 does not need to be initialized on GFX9+ */
2890 Builder
bld(ctx
->program
, ctx
->block
);
2891 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2894 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2895 Temp address
, unsigned base_offset
, unsigned align
)
2897 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2899 Builder
bld(ctx
->program
, ctx
->block
);
2901 Operand m
= load_lds_size_m0(ctx
);
2903 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2904 unsigned bytes_read
= 0;
2905 unsigned result_size
= 0;
2906 unsigned total_bytes
= num_components
* elem_size_bytes
;
2907 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
2908 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
2909 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
2911 while (bytes_read
< total_bytes
) {
2912 unsigned todo
= total_bytes
- bytes_read
;
2913 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2914 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2916 aco_opcode op
= aco_opcode::last_opcode
;
2918 if (todo
>= 16 && aligned16
&& large_ds_read
) {
2919 op
= aco_opcode::ds_read_b128
;
2921 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
2922 op
= aco_opcode::ds_read2_b64
;
2925 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
2926 op
= aco_opcode::ds_read_b96
;
2928 } else if (todo
>= 8 && aligned8
) {
2929 op
= aco_opcode::ds_read_b64
;
2931 } else if (todo
>= 8 && usable_read2
) {
2932 op
= aco_opcode::ds_read2_b32
;
2935 } else if (todo
>= 4) {
2936 op
= aco_opcode::ds_read_b32
;
2941 assert(todo
% elem_size_bytes
== 0);
2942 unsigned num_elements
= todo
/ elem_size_bytes
;
2943 unsigned offset
= base_offset
+ bytes_read
;
2944 unsigned max_offset
= read2
? 1019 : 65535;
2946 Temp address_offset
= address
;
2947 if (offset
> max_offset
) {
2948 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
2949 offset
= bytes_read
;
2951 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
2954 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
2957 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
2960 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
2962 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
2964 if (num_components
== 1) {
2965 assert(todo
== total_bytes
);
2966 if (dst
.type() == RegType::sgpr
)
2967 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
2971 if (dst
.type() == RegType::sgpr
) {
2972 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
2973 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
2977 if (num_elements
== 1) {
2978 result
[result_size
++] = res
;
2980 assert(res
!= dst
&& res
.size() % num_elements
== 0);
2981 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
2982 split
->operands
[0] = Operand(res
);
2983 for (unsigned i
= 0; i
< num_elements
; i
++)
2984 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
2985 ctx
->block
->instructions
.emplace_back(std::move(split
));
2991 assert(result_size
== num_components
&& result_size
> 1);
2992 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
2993 for (unsigned i
= 0; i
< result_size
; i
++)
2994 vec
->operands
[i
] = Operand(result
[i
]);
2995 vec
->definitions
[0] = Definition(dst
);
2996 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2997 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3002 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3004 if (start
== 0 && size
== data
.size())
3005 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3007 unsigned size_hint
= 1;
3008 auto it
= ctx
->allocated_vec
.find(data
.id());
3009 if (it
!= ctx
->allocated_vec
.end())
3010 size_hint
= it
->second
[0].size();
3011 if (size
% size_hint
|| start
% size_hint
)
3018 for (unsigned i
= 0; i
< size
; i
++)
3019 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3022 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3024 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3025 for (unsigned i
= 0; i
< size
; i
++)
3026 vec
->operands
[i
] = Operand(elems
[i
]);
3027 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3028 vec
->definitions
[0] = Definition(res
);
3029 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3033 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3035 Builder
bld(ctx
->program
, ctx
->block
);
3036 unsigned bytes_written
= 0;
3037 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3038 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3040 while (bytes_written
< total_size
* 4) {
3041 unsigned todo
= total_size
* 4 - bytes_written
;
3042 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3043 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3045 aco_opcode op
= aco_opcode::last_opcode
;
3046 bool write2
= false;
3048 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3049 op
= aco_opcode::ds_write_b128
;
3051 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3052 op
= aco_opcode::ds_write2_b64
;
3055 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3056 op
= aco_opcode::ds_write_b96
;
3058 } else if (todo
>= 8 && aligned8
) {
3059 op
= aco_opcode::ds_write_b64
;
3061 } else if (todo
>= 8 && usable_write2
) {
3062 op
= aco_opcode::ds_write2_b32
;
3065 } else if (todo
>= 4) {
3066 op
= aco_opcode::ds_write_b32
;
3072 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3073 unsigned max_offset
= write2
? 1020 : 65535;
3074 Temp address_offset
= address
;
3075 if (offset
> max_offset
) {
3076 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3077 offset
= offset1
+ bytes_written
;
3079 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3082 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3083 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3084 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3086 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3087 bld
.ds(op
, address_offset
, val
, m
, offset
);
3090 bytes_written
+= size
* 4;
3094 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3095 Temp address
, unsigned base_offset
, unsigned align
)
3097 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3098 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3100 Operand m
= load_lds_size_m0(ctx
);
3102 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3103 assert(wrmask
<= 0x0f);
3104 int start
[2], count
[2];
3105 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3106 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3107 assert(wrmask
== 0);
3109 /* one combined store is sufficient */
3110 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3111 Builder
bld(ctx
->program
, ctx
->block
);
3113 Temp address_offset
= address
;
3114 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3115 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3119 assert(count
[0] == 1);
3120 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3122 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3123 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3124 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3125 base_offset
= base_offset
/ elem_size_bytes
;
3126 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3127 base_offset
+ start
[0], base_offset
+ start
[1]);
3131 for (unsigned i
= 0; i
< 2; i
++) {
3135 unsigned elem_size_words
= elem_size_bytes
/ 4;
3136 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3137 base_offset
, start
[i
] * elem_size_bytes
, align
);
3142 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3144 unsigned align
= 16;
3146 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3152 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3153 unsigned split_cnt
= 0u, Temp dst
= Temp())
3155 Builder
bld(ctx
->program
, ctx
->block
);
3156 unsigned dword_size
= elem_size_bytes
/ 4;
3159 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3161 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3162 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3163 instr
->definitions
[0] = Definition(dst
);
3165 for (unsigned i
= 0; i
< cnt
; ++i
) {
3167 assert(arr
[i
].size() == dword_size
);
3168 allocated_vec
[i
] = arr
[i
];
3169 instr
->operands
[i
] = Operand(arr
[i
]);
3171 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3172 allocated_vec
[i
] = zero
;
3173 instr
->operands
[i
] = Operand(zero
);
3177 bld
.insert(std::move(instr
));
3180 emit_split_vector(ctx
, dst
, split_cnt
);
3182 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3187 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3189 if (const_offset
>= 4096) {
3190 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3191 const_offset
%= 4096u;
3194 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3195 else if (unlikely(voffset
.regClass() == s1
))
3196 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3197 else if (likely(voffset
.regClass() == v1
))
3198 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3200 unreachable("Unsupported register class of voffset");
3203 return const_offset
;
3206 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3207 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3210 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3211 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3213 Builder
bld(ctx
->program
, ctx
->block
);
3214 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3215 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3217 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3218 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3219 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3220 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3221 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3223 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3226 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3227 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3228 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3230 Builder
bld(ctx
->program
, ctx
->block
);
3231 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3234 if (elem_size_bytes
== 8) {
3235 elem_size_bytes
= 4;
3236 write_mask
= widen_mask(write_mask
, 2);
3239 while (write_mask
) {
3242 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3247 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3248 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3250 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3251 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3254 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3255 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3265 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3266 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3268 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3269 assert(size_dwords
>= 1 && size_dwords
<= 4);
3271 Builder
bld(ctx
->program
, ctx
->block
);
3272 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3273 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3274 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3276 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3277 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3278 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3279 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3280 /* disable_wqm */ false, /* glc */ true,
3281 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3283 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3288 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3289 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3290 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3292 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3293 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3294 assert(!!stride
!= allow_combining
);
3296 Builder
bld(ctx
->program
, ctx
->block
);
3297 unsigned split_cnt
= num_components
;
3299 if (elem_size_bytes
== 8) {
3300 elem_size_bytes
= 4;
3301 num_components
*= 2;
3305 stride
= elem_size_bytes
;
3307 unsigned load_size
= 1;
3308 if (allow_combining
) {
3309 if ((num_components
% 4) == 0)
3311 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3313 else if ((num_components
% 2) == 0)
3317 unsigned num_loads
= num_components
/ load_size
;
3318 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3320 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3321 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3322 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3325 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3328 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3330 Builder
bld(ctx
->program
, ctx
->block
);
3331 Temp offset
= base_offset
.first
;
3332 unsigned const_offset
= base_offset
.second
;
3334 if (!nir_src_is_const(*off_src
)) {
3335 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3338 /* Calculate indirect offset with stride */
3339 if (likely(indirect_offset_arg
.regClass() == v1
))
3340 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3341 else if (indirect_offset_arg
.regClass() == s1
)
3342 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3344 unreachable("Unsupported register class of indirect offset");
3346 /* Add to the supplied base offset */
3347 if (offset
.id() == 0)
3348 offset
= with_stride
;
3349 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3350 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3351 else if (offset
.size() == 1 && with_stride
.size() == 1)
3352 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3354 unreachable("Unsupported register class of indirect offset");
3356 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3357 const_offset
+= const_offset_arg
* stride
;
3360 return std::make_pair(offset
, const_offset
);
3363 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3365 Builder
bld(ctx
->program
, ctx
->block
);
3368 if (off1
.first
.id() && off2
.first
.id()) {
3369 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3370 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3371 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3372 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3374 unreachable("Unsupported register class of indirect offset");
3376 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3379 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3382 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3384 Builder
bld(ctx
->program
, ctx
->block
);
3385 unsigned const_offset
= offs
.second
* multiplier
;
3387 if (!offs
.first
.id())
3388 return std::make_pair(offs
.first
, const_offset
);
3390 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3391 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3392 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3394 return std::make_pair(offset
, const_offset
);
3397 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3399 Builder
bld(ctx
->program
, ctx
->block
);
3401 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3402 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3403 /* component is in bytes */
3404 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3406 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3407 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3408 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3411 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3413 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3416 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3418 Builder
bld(ctx
->program
, ctx
->block
);
3420 switch (ctx
->shader
->info
.stage
) {
3421 case MESA_SHADER_TESS_CTRL
:
3422 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3423 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3424 case MESA_SHADER_TESS_EVAL
:
3425 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3427 unreachable("Unsupported stage in get_tess_rel_patch_id");
3431 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3433 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3434 Builder
bld(ctx
->program
, ctx
->block
);
3436 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3437 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3439 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3441 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3442 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3444 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3445 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3446 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3448 return offset_mul(ctx
, offs
, 4u);
3451 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3453 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3454 Builder
bld(ctx
->program
, ctx
->block
);
3456 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3457 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3458 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3459 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3460 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3461 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3463 std::pair
<Temp
, unsigned> offs
= instr
3464 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3465 : std::make_pair(Temp(), 0u);
3467 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3468 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3473 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3474 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3476 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3477 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3479 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3480 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3486 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3488 Builder
bld(ctx
->program
, ctx
->block
);
3490 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3491 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3493 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3495 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3496 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3497 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3499 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3500 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3505 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3507 Builder
bld(ctx
->program
, ctx
->block
);
3509 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3510 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3511 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3513 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3514 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3515 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3516 unsigned attr_stride
= ctx
->tcs_num_patches
;
3518 std::pair
<Temp
, unsigned> offs
= instr
3519 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3520 : std::make_pair(Temp(), 0u);
3522 if (const_base_offset
)
3523 offs
.second
+= const_base_offset
* attr_stride
;
3525 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3526 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3527 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3532 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3534 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3535 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3537 if (!nir_src_is_const(*off_src
)) {
3543 off
+= nir_src_as_uint(*off_src
) * 16u;
3546 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3547 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3554 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3556 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3557 unsigned component
= nir_intrinsic_component(instr
);
3558 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3560 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3561 if (off_instr
->type
!= nir_instr_type_load_const
)
3564 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3565 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3567 if (instr
->src
[0].ssa
->bit_size
== 64)
3568 write_mask
= widen_mask(write_mask
, 2);
3570 for (unsigned i
= 0; i
< 8; ++i
) {
3571 if (write_mask
& (1 << i
)) {
3572 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3573 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3581 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3583 /* Only TCS per-vertex inputs are supported by this function.
3584 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3586 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3589 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3590 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3591 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3592 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3593 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3594 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3599 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3600 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3601 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3602 assert(vec
.size() == dst
.size());
3604 Builder
bld(ctx
->program
, ctx
->block
);
3605 bld
.copy(Definition(dst
), vec
);
3609 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3611 Builder
bld(ctx
->program
, ctx
->block
);
3613 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3614 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3615 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3616 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3618 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3619 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3620 bool indirect_write
;
3621 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3622 if (temp_only_input
&& !indirect_write
)
3626 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3627 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3628 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3629 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3630 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3634 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3635 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3636 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3637 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3638 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3639 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3640 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3641 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3642 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3643 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3644 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3645 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3646 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3648 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3649 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3650 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3652 unreachable("Invalid LS or ES stage");
3655 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3656 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3657 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3661 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3663 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3664 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3665 off
!= ctx
->tcs_tess_lvl_in_loc
;
3668 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3670 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3671 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3674 uint64_t mask
= per_vertex
3675 ? ctx
->shader
->info
.outputs_read
3676 : ctx
->shader
->info
.patch_outputs_read
;
3677 bool indirect_write
;
3678 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3679 return indirect_write
|| output_read
;
3682 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3684 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3685 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3687 Builder
bld(ctx
->program
, ctx
->block
);
3689 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3690 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3691 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3693 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3694 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3695 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3696 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3698 if (write_to_vmem
) {
3699 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3700 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3701 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3703 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3704 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3705 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3709 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3710 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3711 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3715 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3717 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3718 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3720 Builder
bld(ctx
->program
, ctx
->block
);
3722 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3723 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3724 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3725 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3727 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3730 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3732 if (ctx
->stage
== vertex_vs
||
3733 ctx
->stage
== tess_eval_vs
||
3734 ctx
->stage
== fragment_fs
||
3735 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3736 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3737 if (!stored_to_temps
) {
3738 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3739 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3740 fprintf(stderr
, "\n");
3743 } else if (ctx
->stage
== vertex_es
||
3744 ctx
->stage
== vertex_ls
||
3745 ctx
->stage
== tess_eval_es
||
3746 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3747 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3748 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3749 visit_store_ls_or_es_output(ctx
, instr
);
3750 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3751 visit_store_tcs_output(ctx
, instr
, false);
3753 unreachable("Shader stage not implemented");
3757 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3759 visit_load_tcs_output(ctx
, instr
, false);
3762 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3764 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3765 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3767 Builder
bld(ctx
->program
, ctx
->block
);
3768 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3769 if (ctx
->program
->has_16bank_lds
)
3770 interp_p1
.instr
->operands
[0].setLateKill(true);
3771 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3774 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3776 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3777 for (unsigned i
= 0; i
< num_components
; i
++)
3778 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3779 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3780 assert(num_components
== 4);
3781 Builder
bld(ctx
->program
, ctx
->block
);
3782 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3785 for (Operand
& op
: vec
->operands
)
3786 op
= op
.isUndefined() ? Operand(0u) : op
;
3788 vec
->definitions
[0] = Definition(dst
);
3789 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3790 emit_split_vector(ctx
, dst
, num_components
);
3794 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3796 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3797 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3798 unsigned idx
= nir_intrinsic_base(instr
);
3799 unsigned component
= nir_intrinsic_component(instr
);
3800 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3802 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3804 assert(offset
->u32
== 0);
3806 /* the lower 15bit of the prim_mask contain the offset into LDS
3807 * while the upper bits contain the number of prims */
3808 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3809 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3810 Builder
bld(ctx
->program
, ctx
->block
);
3811 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3812 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3813 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3814 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3815 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3818 if (instr
->dest
.ssa
.num_components
== 1) {
3819 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3821 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3822 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3824 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3825 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3826 vec
->operands
[i
] = Operand(tmp
);
3828 vec
->definitions
[0] = Definition(dst
);
3829 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3833 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3834 unsigned offset
, unsigned stride
, unsigned channels
)
3836 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
3837 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
3839 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
3840 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
3843 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3844 unsigned offset
, unsigned stride
, unsigned *channels
)
3846 if (!vtx_info
->chan_byte_size
) {
3847 *channels
= vtx_info
->num_channels
;
3848 return vtx_info
->chan_format
;
3851 unsigned num_channels
= *channels
;
3852 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
3853 unsigned new_channels
= num_channels
+ 1;
3854 /* first, assume more loads is worse and try using a larger data format */
3855 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
3857 /* don't make the attribute potentially out-of-bounds */
3858 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
3862 if (new_channels
== 5) {
3863 /* then try decreasing load size (at the cost of more loads) */
3864 new_channels
= *channels
;
3865 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
3869 if (new_channels
< *channels
)
3870 *channels
= new_channels
;
3871 num_channels
= new_channels
;
3874 switch (vtx_info
->chan_format
) {
3875 case V_008F0C_BUF_DATA_FORMAT_8
:
3876 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
3877 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
3878 case V_008F0C_BUF_DATA_FORMAT_16
:
3879 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
3880 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
3881 case V_008F0C_BUF_DATA_FORMAT_32
:
3882 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
3883 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
3885 unreachable("shouldn't reach here");
3886 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
3889 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3890 * so we may need to fix it up. */
3891 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3893 Builder
bld(ctx
->program
, ctx
->block
);
3895 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3896 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3898 /* For the integer-like cases, do a natural sign extension.
3900 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3901 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3904 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3905 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3907 /* Convert back to the right type. */
3908 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3909 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3910 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3911 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3912 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3913 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3919 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3921 Builder
bld(ctx
->program
, ctx
->block
);
3922 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3923 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
3925 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3926 if (off_instr
->type
!= nir_instr_type_load_const
) {
3927 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3928 nir_print_instr(off_instr
, stderr
);
3929 fprintf(stderr
, "\n");
3931 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3933 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
3935 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
3936 unsigned component
= nir_intrinsic_component(instr
);
3937 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
3938 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
3939 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
3940 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
3942 unsigned dfmt
= attrib_format
& 0xf;
3943 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
3944 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
3946 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
3947 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
3948 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
3949 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
3951 num_channels
= MAX2(num_channels
, 3);
3953 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
3954 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
3957 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
3958 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
3959 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
3961 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
3963 Temp divided
= bld
.tmp(v1
);
3964 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
3965 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
3967 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
3970 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
3973 index
= bld
.vadd32(bld
.def(v1
),
3974 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
3975 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
3978 Temp channels
[num_channels
];
3979 unsigned channel_start
= 0;
3980 bool direct_fetch
= false;
3982 /* skip unused channels at the start */
3983 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
3984 channel_start
= ffs(mask
) - 1;
3985 for (unsigned i
= 0; i
< channel_start
; i
++)
3986 channels
[i
] = Temp(0, s1
);
3987 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
3988 num_channels
= 3 - (ffs(mask
) - 1);
3992 while (channel_start
< num_channels
) {
3993 unsigned fetch_size
= num_channels
- channel_start
;
3994 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
3995 bool expanded
= false;
3997 /* use MUBUF when possible to avoid possible alignment issues */
3998 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3999 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4000 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4001 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4002 vtx_info
->chan_byte_size
== 4;
4003 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4005 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4007 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4008 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4014 Temp fetch_index
= index
;
4015 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4016 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4017 fetch_offset
= fetch_offset
% attrib_stride
;
4020 Operand
soffset(0u);
4021 if (fetch_offset
>= 4096) {
4022 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4023 fetch_offset
%= 4096;
4027 switch (fetch_size
) {
4029 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4032 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4035 assert(ctx
->options
->chip_class
>= GFX7
||
4036 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4037 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4040 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4043 unreachable("Unimplemented load_input vector size");
4047 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4048 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4049 num_channels
<= 3)) {
4050 direct_fetch
= true;
4053 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4057 Instruction
*mubuf
= bld
.mubuf(opcode
,
4058 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4059 fetch_offset
, false, true).instr
;
4060 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4062 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4063 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4064 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4065 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4068 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4070 if (fetch_size
== 1) {
4071 channels
[channel_start
] = fetch_dst
;
4073 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4074 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4077 channel_start
+= fetch_size
;
4080 if (!direct_fetch
) {
4081 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4082 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4084 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4085 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4086 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4088 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4089 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4090 unsigned num_temp
= 0;
4091 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4092 unsigned idx
= i
+ component
;
4093 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4094 Temp channel
= channels
[swizzle
[idx
]];
4095 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4096 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4097 vec
->operands
[i
] = Operand(channel
);
4101 } else if (is_float
&& idx
== 3) {
4102 vec
->operands
[i
] = Operand(0x3f800000u
);
4103 } else if (!is_float
&& idx
== 3) {
4104 vec
->operands
[i
] = Operand(1u);
4106 vec
->operands
[i
] = Operand(0u);
4109 vec
->definitions
[0] = Definition(dst
);
4110 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4111 emit_split_vector(ctx
, dst
, dst
.size());
4113 if (num_temp
== dst
.size())
4114 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4116 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4117 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4118 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4119 if (off_instr
->type
!= nir_instr_type_load_const
||
4120 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4121 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4122 nir_print_instr(off_instr
, stderr
);
4123 fprintf(stderr
, "\n");
4126 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4127 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4129 assert(offset
->u32
== 0);
4131 /* the lower 15bit of the prim_mask contain the offset into LDS
4132 * while the upper bits contain the number of prims */
4133 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4134 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4135 Builder
bld(ctx
->program
, ctx
->block
);
4136 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4137 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4138 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4139 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4140 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4143 unsigned idx
= nir_intrinsic_base(instr
);
4144 unsigned component
= nir_intrinsic_component(instr
);
4145 unsigned vertex_id
= 2; /* P0 */
4147 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4148 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4149 switch (src0
->u32
) {
4151 vertex_id
= 2; /* P0 */
4154 vertex_id
= 0; /* P10 */
4157 vertex_id
= 1; /* P20 */
4160 unreachable("invalid vertex index");
4164 if (dst
.size() == 1) {
4165 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4167 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4168 for (unsigned i
= 0; i
< dst
.size(); i
++)
4169 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4170 vec
->definitions
[0] = Definition(dst
);
4171 bld
.insert(std::move(vec
));
4174 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4175 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4176 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4177 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4178 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4180 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4182 unreachable("Shader stage not implemented");
4186 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4188 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4190 Builder
bld(ctx
->program
, ctx
->block
);
4191 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4194 if (!nir_src_is_const(*vertex_src
)) {
4195 /* better code could be created, but this case probably doesn't happen
4196 * much in practice */
4197 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4198 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4201 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4202 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4204 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4206 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4209 if (vertex_offset
.id()) {
4210 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4211 Operand(i
), indirect_vertex
);
4212 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4214 vertex_offset
= elem
;
4218 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4219 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4221 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4222 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4223 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4224 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4225 Operand((vertex
% 2u) * 16u), Operand(16u));
4227 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4230 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4231 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4232 return offset_mul(ctx
, offs
, 4u);
4235 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4237 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4239 Builder
bld(ctx
->program
, ctx
->block
);
4240 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4241 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4243 if (ctx
->stage
== geometry_gs
) {
4244 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4245 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4246 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4247 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4248 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4249 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4250 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4252 unreachable("Unsupported GS stage.");
4256 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4258 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4260 Builder
bld(ctx
->program
, ctx
->block
);
4261 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4263 if (load_input_from_temps(ctx
, instr
, dst
))
4266 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4267 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4268 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4270 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4273 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4275 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4277 Builder
bld(ctx
->program
, ctx
->block
);
4279 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4280 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4281 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4283 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4284 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4286 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4289 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4291 switch (ctx
->shader
->info
.stage
) {
4292 case MESA_SHADER_GEOMETRY
:
4293 visit_load_gs_per_vertex_input(ctx
, instr
);
4295 case MESA_SHADER_TESS_CTRL
:
4296 visit_load_tcs_per_vertex_input(ctx
, instr
);
4298 case MESA_SHADER_TESS_EVAL
:
4299 visit_load_tes_per_vertex_input(ctx
, instr
);
4302 unreachable("Unimplemented shader stage");
4306 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4308 visit_load_tcs_output(ctx
, instr
, true);
4311 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4313 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4314 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4316 visit_store_tcs_output(ctx
, instr
, true);
4319 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4321 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4323 Builder
bld(ctx
->program
, ctx
->block
);
4324 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4326 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4327 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4330 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4331 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4332 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4333 tes_w
= Operand(tmp
);
4336 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4337 emit_split_vector(ctx
, tess_coord
, 3);
4340 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4342 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4343 Builder
bld(ctx
->program
, ctx
->block
);
4344 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4345 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4346 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4349 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4353 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4355 Builder
bld(ctx
->program
, ctx
->block
);
4356 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4357 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4358 index
= bld
.as_uniform(index
);
4359 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4360 unsigned binding
= nir_intrinsic_binding(instr
);
4363 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4364 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4365 unsigned offset
= layout
->binding
[binding
].offset
;
4367 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4368 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4369 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4370 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4371 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4374 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4375 stride
= layout
->binding
[binding
].size
;
4378 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4379 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4381 if (nir_const_index
) {
4382 const_index
= const_index
* stride
;
4383 } else if (index
.type() == RegType::vgpr
) {
4384 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4385 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4387 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4391 if (nir_const_index
) {
4392 const_index
= const_index
+ offset
;
4393 } else if (index
.type() == RegType::vgpr
) {
4394 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4396 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4400 if (nir_const_index
&& const_index
== 0) {
4402 } else if (index
.type() == RegType::vgpr
) {
4403 index
= bld
.vadd32(bld
.def(v1
),
4404 nir_const_index
? Operand(const_index
) : Operand(index
),
4407 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4408 nir_const_index
? Operand(const_index
) : Operand(index
),
4412 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4415 void load_buffer(isel_context
*ctx
, unsigned num_components
, Temp dst
,
4416 Temp rsrc
, Temp offset
, bool glc
=false, bool readonly
=true)
4418 Builder
bld(ctx
->program
, ctx
->block
);
4420 unsigned num_bytes
= dst
.size() * 4;
4421 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4424 if (dst
.type() == RegType::vgpr
|| (ctx
->options
->chip_class
< GFX8
&& !readonly
)) {
4425 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4426 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4427 unsigned const_offset
= 0;
4429 Temp lower
= Temp();
4430 if (num_bytes
> 16) {
4431 assert(num_components
== 3 || num_components
== 4);
4432 op
= aco_opcode::buffer_load_dwordx4
;
4433 lower
= bld
.tmp(v4
);
4434 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4435 mubuf
->definitions
[0] = Definition(lower
);
4436 mubuf
->operands
[0] = Operand(rsrc
);
4437 mubuf
->operands
[1] = vaddr
;
4438 mubuf
->operands
[2] = soffset
;
4439 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4442 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4443 mubuf
->can_reorder
= readonly
;
4444 bld
.insert(std::move(mubuf
));
4445 emit_split_vector(ctx
, lower
, 2);
4448 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4449 /* GFX6 doesn't support loading vec3, expand to vec4. */
4453 switch (num_bytes
) {
4455 op
= aco_opcode::buffer_load_dword
;
4458 op
= aco_opcode::buffer_load_dwordx2
;
4461 assert(ctx
->options
->chip_class
> GFX6
);
4462 op
= aco_opcode::buffer_load_dwordx3
;
4465 op
= aco_opcode::buffer_load_dwordx4
;
4468 unreachable("Load SSBO not implemented for this size.");
4470 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4471 mubuf
->operands
[0] = Operand(rsrc
);
4472 mubuf
->operands
[1] = vaddr
;
4473 mubuf
->operands
[2] = soffset
;
4474 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4477 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4478 mubuf
->can_reorder
= readonly
;
4479 mubuf
->offset
= const_offset
;
4480 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4482 if (dst
.size() > 4) {
4483 assert(lower
!= Temp());
4484 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4485 instr
->definitions
[0] = Definition(upper
);
4486 bld
.insert(std::move(instr
));
4487 if (dst
.size() == 8)
4488 emit_split_vector(ctx
, upper
, 2);
4489 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4490 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4491 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4492 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4493 if (dst
.size() == 8)
4494 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4495 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4496 Temp vec
= bld
.tmp(v4
);
4497 instr
->definitions
[0] = Definition(vec
);
4498 bld
.insert(std::move(instr
));
4499 emit_split_vector(ctx
, vec
, 4);
4501 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4502 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4503 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4504 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4507 if (dst
.type() == RegType::sgpr
) {
4508 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4509 instr
->definitions
[0] = Definition(vec
);
4510 bld
.insert(std::move(instr
));
4511 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4513 instr
->definitions
[0] = Definition(dst
);
4514 bld
.insert(std::move(instr
));
4515 emit_split_vector(ctx
, dst
, num_components
);
4518 switch (num_bytes
) {
4520 op
= aco_opcode::s_buffer_load_dword
;
4523 op
= aco_opcode::s_buffer_load_dwordx2
;
4527 op
= aco_opcode::s_buffer_load_dwordx4
;
4531 op
= aco_opcode::s_buffer_load_dwordx8
;
4534 unreachable("Load SSBO not implemented for this size.");
4536 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4537 load
->operands
[0] = Operand(rsrc
);
4538 load
->operands
[1] = Operand(bld
.as_uniform(offset
));
4539 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4540 load
->definitions
[0] = Definition(dst
);
4543 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4544 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4545 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4548 if (dst
.size() == 3) {
4549 Temp vec
= bld
.tmp(s4
);
4550 load
->definitions
[0] = Definition(vec
);
4551 bld
.insert(std::move(load
));
4552 emit_split_vector(ctx
, vec
, 4);
4554 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4555 emit_extract_vector(ctx
, vec
, 0, s1
),
4556 emit_extract_vector(ctx
, vec
, 1, s1
),
4557 emit_extract_vector(ctx
, vec
, 2, s1
));
4558 } else if (dst
.size() == 6) {
4559 Temp vec
= bld
.tmp(s8
);
4560 load
->definitions
[0] = Definition(vec
);
4561 bld
.insert(std::move(load
));
4562 emit_split_vector(ctx
, vec
, 4);
4564 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4565 emit_extract_vector(ctx
, vec
, 0, s2
),
4566 emit_extract_vector(ctx
, vec
, 1, s2
),
4567 emit_extract_vector(ctx
, vec
, 2, s2
));
4569 bld
.insert(std::move(load
));
4571 emit_split_vector(ctx
, dst
, num_components
);
4575 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4577 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4578 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4580 Builder
bld(ctx
->program
, ctx
->block
);
4582 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4583 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4584 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4585 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4587 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4588 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4589 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4590 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4591 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4592 if (ctx
->options
->chip_class
>= GFX10
) {
4593 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4594 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4595 S_008F0C_RESOURCE_LEVEL(1);
4597 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4598 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4600 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4601 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4602 Operand(0xFFFFFFFFu
),
4603 Operand(desc_type
));
4604 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4605 rsrc
, upper_dwords
);
4607 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4608 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4611 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4614 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4616 Builder
bld(ctx
->program
, ctx
->block
);
4617 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4619 unsigned offset
= nir_intrinsic_base(instr
);
4620 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4621 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4623 unsigned count
= instr
->dest
.ssa
.num_components
;
4624 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4625 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4626 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4627 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4628 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4629 for (unsigned i
= 0; i
< count
; ++i
) {
4630 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4631 vec
->operands
[i
] = Operand
{elems
[i
]};
4633 vec
->definitions
[0] = Definition(dst
);
4634 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4635 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4640 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4641 if (offset
!= 0) // TODO check if index != 0 as well
4642 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4643 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4648 switch (dst
.size()) {
4650 op
= aco_opcode::s_load_dword
;
4653 op
= aco_opcode::s_load_dwordx2
;
4659 op
= aco_opcode::s_load_dwordx4
;
4665 op
= aco_opcode::s_load_dwordx8
;
4668 unreachable("unimplemented or forbidden load_push_constant.");
4671 bld
.smem(op
, Definition(vec
), ptr
, index
);
4674 emit_split_vector(ctx
, vec
, 4);
4675 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4676 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4677 emit_extract_vector(ctx
, vec
, 0, rc
),
4678 emit_extract_vector(ctx
, vec
, 1, rc
),
4679 emit_extract_vector(ctx
, vec
, 2, rc
));
4682 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4685 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4687 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4689 Builder
bld(ctx
->program
, ctx
->block
);
4691 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4692 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4693 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4694 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4695 if (ctx
->options
->chip_class
>= GFX10
) {
4696 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4697 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4698 S_008F0C_RESOURCE_LEVEL(1);
4700 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4701 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4704 unsigned base
= nir_intrinsic_base(instr
);
4705 unsigned range
= nir_intrinsic_range(instr
);
4707 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4708 if (base
&& offset
.type() == RegType::sgpr
)
4709 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4710 else if (base
&& offset
.type() == RegType::vgpr
)
4711 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4713 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4714 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4715 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4716 Operand(desc_type
));
4718 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, offset
);
4721 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4723 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4724 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4726 ctx
->program
->needs_exact
= true;
4728 // TODO: optimize uniform conditions
4729 Builder
bld(ctx
->program
, ctx
->block
);
4730 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4731 assert(src
.regClass() == bld
.lm
);
4732 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
4733 bld
.pseudo(aco_opcode::p_discard_if
, src
);
4734 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4738 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
4740 Builder
bld(ctx
->program
, ctx
->block
);
4742 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4743 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4745 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
4746 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
4748 if (ctx
->block
->loop_nest_depth
&&
4749 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
4750 /* we handle discards the same way as jump instructions */
4751 append_logical_end(ctx
->block
);
4753 /* in loops, discard behaves like break */
4754 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
4755 ctx
->block
->kind
|= block_kind_discard
;
4758 /* uniform discard - loop ends here */
4759 assert(nir_instr_is_last(&instr
->instr
));
4760 ctx
->block
->kind
|= block_kind_uniform
;
4761 ctx
->cf_info
.has_branch
= true;
4762 bld
.branch(aco_opcode::p_branch
);
4763 add_linear_edge(ctx
->block
->index
, linear_target
);
4767 /* we add a break right behind the discard() instructions */
4768 ctx
->block
->kind
|= block_kind_break
;
4769 unsigned idx
= ctx
->block
->index
;
4771 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
4772 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
4774 /* remove critical edges from linear CFG */
4775 bld
.branch(aco_opcode::p_branch
);
4776 Block
* break_block
= ctx
->program
->create_and_insert_block();
4777 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4778 break_block
->kind
|= block_kind_uniform
;
4779 add_linear_edge(idx
, break_block
);
4780 add_linear_edge(break_block
->index
, linear_target
);
4781 bld
.reset(break_block
);
4782 bld
.branch(aco_opcode::p_branch
);
4784 Block
* continue_block
= ctx
->program
->create_and_insert_block();
4785 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4786 add_linear_edge(idx
, continue_block
);
4787 append_logical_start(continue_block
);
4788 ctx
->block
= continue_block
;
4793 /* it can currently happen that NIR doesn't remove the unreachable code */
4794 if (!nir_instr_is_last(&instr
->instr
)) {
4795 ctx
->program
->needs_exact
= true;
4796 /* save exec somewhere temporarily so that it doesn't get
4797 * overwritten before the discard from outer exec masks */
4798 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
4799 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
4800 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4804 /* This condition is incorrect for uniformly branched discards in a loop
4805 * predicated by a divergent condition, but the above code catches that case
4806 * and the discard would end up turning into a discard_if.
4816 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
4817 /* program just ends here */
4818 ctx
->block
->kind
|= block_kind_uniform
;
4819 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
4820 0 /* enabled mask */, 9 /* dest */,
4821 false /* compressed */, true/* done */, true /* valid mask */);
4822 bld
.sopp(aco_opcode::s_endpgm
);
4823 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4825 ctx
->block
->kind
|= block_kind_discard
;
4826 /* branch and linear edge is added by visit_if() */
4830 enum aco_descriptor_type
{
4841 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
4842 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4844 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
4845 return dim
== ac_image_cube
||
4846 dim
== ac_image_1darray
||
4847 dim
== ac_image_2darray
||
4848 dim
== ac_image_2darraymsaa
;
4851 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
4852 enum aco_descriptor_type desc_type
,
4853 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
4855 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4856 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4857 if (it != ctx->tex_desc.end())
4860 Temp index
= Temp();
4861 bool index_set
= false;
4862 unsigned constant_index
= 0;
4863 unsigned descriptor_set
;
4864 unsigned base_index
;
4865 Builder
bld(ctx
->program
, ctx
->block
);
4868 assert(tex_instr
&& !image
);
4870 base_index
= tex_instr
->sampler_index
;
4872 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
4873 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
4877 assert(deref_instr
->deref_type
== nir_deref_type_array
);
4878 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
4880 constant_index
+= array_size
* const_value
->u32
;
4882 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
4883 if (indirect
.type() == RegType::vgpr
)
4884 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
4886 if (array_size
!= 1)
4887 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
4893 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
4897 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
4899 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
4900 base_index
= deref_instr
->var
->data
.binding
;
4903 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
4904 list
= convert_pointer_to_64_bit(ctx
, list
);
4906 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4907 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4908 unsigned offset
= binding
->offset
;
4909 unsigned stride
= binding
->size
;
4913 assert(base_index
< layout
->binding_count
);
4915 switch (desc_type
) {
4916 case ACO_DESC_IMAGE
:
4918 opcode
= aco_opcode::s_load_dwordx8
;
4920 case ACO_DESC_FMASK
:
4922 opcode
= aco_opcode::s_load_dwordx8
;
4925 case ACO_DESC_SAMPLER
:
4927 opcode
= aco_opcode::s_load_dwordx4
;
4928 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4929 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
4931 case ACO_DESC_BUFFER
:
4933 opcode
= aco_opcode::s_load_dwordx4
;
4935 case ACO_DESC_PLANE_0
:
4936 case ACO_DESC_PLANE_1
:
4938 opcode
= aco_opcode::s_load_dwordx8
;
4939 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
4941 case ACO_DESC_PLANE_2
:
4943 opcode
= aco_opcode::s_load_dwordx4
;
4947 unreachable("invalid desc_type\n");
4950 offset
+= constant_index
* stride
;
4952 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4953 (!index_set
|| binding
->immutable_samplers_equal
)) {
4954 if (binding
->immutable_samplers_equal
)
4957 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4958 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4959 Operand(samplers
[constant_index
* 4 + 0]),
4960 Operand(samplers
[constant_index
* 4 + 1]),
4961 Operand(samplers
[constant_index
* 4 + 2]),
4962 Operand(samplers
[constant_index
* 4 + 3]));
4967 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
4969 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
4970 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
4973 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
4975 if (desc_type
== ACO_DESC_PLANE_2
) {
4977 for (unsigned i
= 0; i
< 8; i
++)
4978 components
[i
] = bld
.tmp(s1
);
4979 bld
.pseudo(aco_opcode::p_split_vector
,
4980 Definition(components
[0]),
4981 Definition(components
[1]),
4982 Definition(components
[2]),
4983 Definition(components
[3]),
4986 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
4987 bld
.pseudo(aco_opcode::p_split_vector
,
4988 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
4989 Definition(components
[4]),
4990 Definition(components
[5]),
4991 Definition(components
[6]),
4992 Definition(components
[7]),
4995 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
4996 components
[0], components
[1], components
[2], components
[3],
4997 components
[4], components
[5], components
[6], components
[7]);
5003 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5006 case GLSL_SAMPLER_DIM_BUF
:
5008 case GLSL_SAMPLER_DIM_1D
:
5009 return array
? 2 : 1;
5010 case GLSL_SAMPLER_DIM_2D
:
5011 return array
? 3 : 2;
5012 case GLSL_SAMPLER_DIM_MS
:
5013 return array
? 4 : 3;
5014 case GLSL_SAMPLER_DIM_3D
:
5015 case GLSL_SAMPLER_DIM_CUBE
:
5017 case GLSL_SAMPLER_DIM_RECT
:
5018 case GLSL_SAMPLER_DIM_SUBPASS
:
5020 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5029 /* Adjust the sample index according to FMASK.
5031 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5032 * which is the identity mapping. Each nibble says which physical sample
5033 * should be fetched to get that sample.
5035 * For example, 0x11111100 means there are only 2 samples stored and
5036 * the second sample covers 3/4 of the pixel. When reading samples 0
5037 * and 1, return physical sample 0 (determined by the first two 0s
5038 * in FMASK), otherwise return physical sample 1.
5040 * The sample index should be adjusted as follows:
5041 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5043 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5045 Builder
bld(ctx
->program
, ctx
->block
);
5046 Temp fmask
= bld
.tmp(v1
);
5047 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5048 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5051 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5052 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5053 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5054 load
->operands
[0] = Operand(fmask_desc_ptr
);
5055 load
->operands
[1] = Operand(s4
); /* no sampler */
5056 load
->operands
[2] = Operand(coord
);
5057 load
->definitions
[0] = Definition(fmask
);
5064 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5065 ctx
->block
->instructions
.emplace_back(std::move(load
));
5067 Operand sample_index4
;
5068 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5069 sample_index4
= Operand(sample_index
.constantValue() << 2);
5070 } else if (sample_index
.regClass() == s1
) {
5071 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5073 assert(sample_index
.regClass() == v1
);
5074 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5078 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5079 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5080 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5081 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5083 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5085 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5086 * resource descriptor is 0 (invalid),
5088 Temp compare
= bld
.tmp(bld
.lm
);
5089 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5090 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5092 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5094 /* Replace the MSAA sample index. */
5095 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5098 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5101 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5102 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5103 bool is_array
= glsl_sampler_type_is_array(type
);
5104 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5105 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5106 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5107 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5108 int count
= image_type_to_components_count(dim
, is_array
);
5109 std::vector
<Temp
> coords(count
);
5110 Builder
bld(ctx
->program
, ctx
->block
);
5114 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5115 /* get sample index */
5116 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5117 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5118 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5119 std::vector
<Temp
> fmask_load_address
;
5120 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5121 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5123 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5124 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5126 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5131 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5132 coords
.resize(coords
.size() + 1);
5133 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5135 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5137 for (int i
= 0; i
< count
; i
++)
5138 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5141 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5142 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5143 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5144 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5147 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5150 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5151 for (unsigned i
= 0; i
< coords
.size(); i
++)
5152 vec
->operands
[i
] = Operand(coords
[i
]);
5153 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5154 vec
->definitions
[0] = Definition(res
);
5155 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5160 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5162 Builder
bld(ctx
->program
, ctx
->block
);
5163 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5164 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5165 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5166 bool is_array
= glsl_sampler_type_is_array(type
);
5167 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5169 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5170 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5171 unsigned num_channels
= util_last_bit(mask
);
5172 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5173 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5176 switch (num_channels
) {
5178 opcode
= aco_opcode::buffer_load_format_x
;
5181 opcode
= aco_opcode::buffer_load_format_xy
;
5184 opcode
= aco_opcode::buffer_load_format_xyz
;
5187 opcode
= aco_opcode::buffer_load_format_xyzw
;
5190 unreachable(">4 channel buffer image load");
5192 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5193 load
->operands
[0] = Operand(rsrc
);
5194 load
->operands
[1] = Operand(vindex
);
5195 load
->operands
[2] = Operand((uint32_t) 0);
5197 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5200 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5201 load
->definitions
[0] = Definition(tmp
);
5203 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5204 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5205 load
->barrier
= barrier_image
;
5206 ctx
->block
->instructions
.emplace_back(std::move(load
));
5208 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5212 Temp coords
= get_image_coords(ctx
, instr
, type
);
5213 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5215 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5216 unsigned num_components
= util_bitcount(dmask
);
5218 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5221 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5223 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5224 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5226 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5227 load
->operands
[0] = Operand(resource
);
5228 load
->operands
[1] = Operand(s4
); /* no sampler */
5229 load
->operands
[2] = Operand(coords
);
5230 load
->definitions
[0] = Definition(tmp
);
5231 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5232 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5233 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5234 load
->dmask
= dmask
;
5236 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5237 load
->barrier
= barrier_image
;
5238 ctx
->block
->instructions
.emplace_back(std::move(load
));
5240 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5244 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5246 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5247 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5248 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5249 bool is_array
= glsl_sampler_type_is_array(type
);
5250 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5252 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5254 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5255 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5256 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5258 switch (data
.size()) {
5260 opcode
= aco_opcode::buffer_store_format_x
;
5263 opcode
= aco_opcode::buffer_store_format_xy
;
5266 opcode
= aco_opcode::buffer_store_format_xyz
;
5269 opcode
= aco_opcode::buffer_store_format_xyzw
;
5272 unreachable(">4 channel buffer image store");
5274 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5275 store
->operands
[0] = Operand(rsrc
);
5276 store
->operands
[1] = Operand(vindex
);
5277 store
->operands
[2] = Operand((uint32_t) 0);
5278 store
->operands
[3] = Operand(data
);
5279 store
->idxen
= true;
5282 store
->disable_wqm
= true;
5283 store
->barrier
= barrier_image
;
5284 ctx
->program
->needs_exact
= true;
5285 ctx
->block
->instructions
.emplace_back(std::move(store
));
5289 assert(data
.type() == RegType::vgpr
);
5290 Temp coords
= get_image_coords(ctx
, instr
, type
);
5291 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5293 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5294 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5296 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5297 store
->operands
[0] = Operand(resource
);
5298 store
->operands
[1] = Operand(data
);
5299 store
->operands
[2] = Operand(coords
);
5302 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5303 store
->dmask
= (1 << data
.size()) - 1;
5305 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5306 store
->disable_wqm
= true;
5307 store
->barrier
= barrier_image
;
5308 ctx
->program
->needs_exact
= true;
5309 ctx
->block
->instructions
.emplace_back(std::move(store
));
5313 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5315 /* return the previous value if dest is ever used */
5316 bool return_previous
= false;
5317 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5318 return_previous
= true;
5321 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5322 return_previous
= true;
5326 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5327 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5328 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5329 bool is_array
= glsl_sampler_type_is_array(type
);
5330 Builder
bld(ctx
->program
, ctx
->block
);
5332 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5333 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5335 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5336 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5338 aco_opcode buf_op
, image_op
;
5339 switch (instr
->intrinsic
) {
5340 case nir_intrinsic_image_deref_atomic_add
:
5341 buf_op
= aco_opcode::buffer_atomic_add
;
5342 image_op
= aco_opcode::image_atomic_add
;
5344 case nir_intrinsic_image_deref_atomic_umin
:
5345 buf_op
= aco_opcode::buffer_atomic_umin
;
5346 image_op
= aco_opcode::image_atomic_umin
;
5348 case nir_intrinsic_image_deref_atomic_imin
:
5349 buf_op
= aco_opcode::buffer_atomic_smin
;
5350 image_op
= aco_opcode::image_atomic_smin
;
5352 case nir_intrinsic_image_deref_atomic_umax
:
5353 buf_op
= aco_opcode::buffer_atomic_umax
;
5354 image_op
= aco_opcode::image_atomic_umax
;
5356 case nir_intrinsic_image_deref_atomic_imax
:
5357 buf_op
= aco_opcode::buffer_atomic_smax
;
5358 image_op
= aco_opcode::image_atomic_smax
;
5360 case nir_intrinsic_image_deref_atomic_and
:
5361 buf_op
= aco_opcode::buffer_atomic_and
;
5362 image_op
= aco_opcode::image_atomic_and
;
5364 case nir_intrinsic_image_deref_atomic_or
:
5365 buf_op
= aco_opcode::buffer_atomic_or
;
5366 image_op
= aco_opcode::image_atomic_or
;
5368 case nir_intrinsic_image_deref_atomic_xor
:
5369 buf_op
= aco_opcode::buffer_atomic_xor
;
5370 image_op
= aco_opcode::image_atomic_xor
;
5372 case nir_intrinsic_image_deref_atomic_exchange
:
5373 buf_op
= aco_opcode::buffer_atomic_swap
;
5374 image_op
= aco_opcode::image_atomic_swap
;
5376 case nir_intrinsic_image_deref_atomic_comp_swap
:
5377 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5378 image_op
= aco_opcode::image_atomic_cmpswap
;
5381 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5384 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5386 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5387 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5388 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5389 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5390 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5391 mubuf
->operands
[0] = Operand(resource
);
5392 mubuf
->operands
[1] = Operand(vindex
);
5393 mubuf
->operands
[2] = Operand((uint32_t)0);
5394 mubuf
->operands
[3] = Operand(data
);
5395 if (return_previous
)
5396 mubuf
->definitions
[0] = Definition(dst
);
5398 mubuf
->idxen
= true;
5399 mubuf
->glc
= return_previous
;
5400 mubuf
->dlc
= false; /* Not needed for atomics */
5401 mubuf
->disable_wqm
= true;
5402 mubuf
->barrier
= barrier_image
;
5403 ctx
->program
->needs_exact
= true;
5404 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5408 Temp coords
= get_image_coords(ctx
, instr
, type
);
5409 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5410 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5411 mimg
->operands
[0] = Operand(resource
);
5412 mimg
->operands
[1] = Operand(data
);
5413 mimg
->operands
[2] = Operand(coords
);
5414 if (return_previous
)
5415 mimg
->definitions
[0] = Definition(dst
);
5416 mimg
->glc
= return_previous
;
5417 mimg
->dlc
= false; /* Not needed for atomics */
5418 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5419 mimg
->dmask
= (1 << data
.size()) - 1;
5421 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5422 mimg
->disable_wqm
= true;
5423 mimg
->barrier
= barrier_image
;
5424 ctx
->program
->needs_exact
= true;
5425 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5429 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5431 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5432 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5433 Builder
bld(ctx
->program
, ctx
->block
);
5435 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5437 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5438 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5440 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5441 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5443 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5444 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5446 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5447 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5448 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5449 if (dst
.type() == RegType::vgpr
)
5450 bld
.copy(Definition(dst
), shr_dst
);
5452 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5454 emit_extract_vector(ctx
, desc
, 2, dst
);
5458 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5460 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5461 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5462 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5463 bool is_array
= glsl_sampler_type_is_array(type
);
5464 Builder
bld(ctx
->program
, ctx
->block
);
5466 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5467 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5468 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5472 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5475 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5477 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5479 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5480 mimg
->operands
[0] = Operand(resource
);
5481 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5482 mimg
->operands
[2] = Operand(lod
);
5483 uint8_t& dmask
= mimg
->dmask
;
5484 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5485 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5486 mimg
->da
= glsl_sampler_type_is_array(type
);
5487 mimg
->can_reorder
= true;
5488 Definition
& def
= mimg
->definitions
[0];
5489 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5491 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5492 glsl_sampler_type_is_array(type
)) {
5494 assert(instr
->dest
.ssa
.num_components
== 3);
5495 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5496 def
= Definition(tmp
);
5497 emit_split_vector(ctx
, tmp
, 3);
5499 /* divide 3rd value by 6 by multiplying with magic number */
5500 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5501 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5503 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5504 emit_extract_vector(ctx
, tmp
, 0, v1
),
5505 emit_extract_vector(ctx
, tmp
, 1, v1
),
5508 } else if (ctx
->options
->chip_class
== GFX9
&&
5509 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5510 glsl_sampler_type_is_array(type
)) {
5511 assert(instr
->dest
.ssa
.num_components
== 2);
5512 def
= Definition(dst
);
5515 def
= Definition(dst
);
5518 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5521 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5523 Builder
bld(ctx
->program
, ctx
->block
);
5524 unsigned num_components
= instr
->num_components
;
5526 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5527 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5528 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5530 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5531 load_buffer(ctx
, num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), glc
, false);
5534 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5536 Builder
bld(ctx
->program
, ctx
->block
);
5537 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5538 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5539 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5540 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5542 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5543 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5545 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5546 ctx
->options
->chip_class
>= GFX8
;
5548 offset
= bld
.as_uniform(offset
);
5549 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5553 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5554 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5555 /* GFX6 doesn't support storing vec3, split it. */
5556 writemask
|= 1u << (start
+ 2);
5559 int num_bytes
= count
* elem_size_bytes
;
5561 if (num_bytes
> 16) {
5562 assert(elem_size_bytes
== 8);
5563 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5568 // TODO: check alignment of sub-dword stores
5569 // TODO: split 3 bytes. there is no store instruction for that
5572 if (count
!= instr
->num_components
) {
5573 emit_split_vector(ctx
, data
, instr
->num_components
);
5574 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5575 for (int i
= 0; i
< count
; i
++) {
5576 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5577 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5579 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5580 vec
->definitions
[0] = Definition(write_data
);
5581 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5582 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5583 assert(num_bytes
% 4 == 0);
5584 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5585 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5586 assert(num_bytes
% 4 == 0);
5587 write_data
= bld
.as_uniform(data
);
5592 aco_opcode vmem_op
, smem_op
;
5593 switch (num_bytes
) {
5595 vmem_op
= aco_opcode::buffer_store_dword
;
5596 smem_op
= aco_opcode::s_buffer_store_dword
;
5599 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5600 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5603 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5604 smem_op
= aco_opcode::last_opcode
;
5605 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5608 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5609 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5612 unreachable("Store SSBO not implemented for this size.");
5614 if (ctx
->stage
== fragment_fs
)
5615 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5618 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5619 store
->operands
[0] = Operand(rsrc
);
5621 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5622 offset
, Operand(start
* elem_size_bytes
));
5623 store
->operands
[1] = Operand(off
);
5625 store
->operands
[1] = Operand(offset
);
5627 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5628 store
->operands
[1].setFixed(m0
);
5629 store
->operands
[2] = Operand(write_data
);
5630 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5632 store
->disable_wqm
= true;
5633 store
->barrier
= barrier_buffer
;
5634 ctx
->block
->instructions
.emplace_back(std::move(store
));
5635 ctx
->program
->wb_smem_l1_on_end
= true;
5636 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5637 ctx
->block
->kind
|= block_kind_needs_lowering
;
5638 ctx
->program
->needs_exact
= true;
5641 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5642 store
->operands
[0] = Operand(rsrc
);
5643 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5644 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5645 store
->operands
[3] = Operand(write_data
);
5646 store
->offset
= start
* elem_size_bytes
;
5647 store
->offen
= (offset
.type() == RegType::vgpr
);
5648 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5650 store
->disable_wqm
= true;
5651 store
->barrier
= barrier_buffer
;
5652 ctx
->program
->needs_exact
= true;
5653 ctx
->block
->instructions
.emplace_back(std::move(store
));
5658 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5660 /* return the previous value if dest is ever used */
5661 bool return_previous
= false;
5662 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5663 return_previous
= true;
5666 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5667 return_previous
= true;
5671 Builder
bld(ctx
->program
, ctx
->block
);
5672 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5674 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5675 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5676 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5678 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5679 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5680 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5682 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5684 aco_opcode op32
, op64
;
5685 switch (instr
->intrinsic
) {
5686 case nir_intrinsic_ssbo_atomic_add
:
5687 op32
= aco_opcode::buffer_atomic_add
;
5688 op64
= aco_opcode::buffer_atomic_add_x2
;
5690 case nir_intrinsic_ssbo_atomic_imin
:
5691 op32
= aco_opcode::buffer_atomic_smin
;
5692 op64
= aco_opcode::buffer_atomic_smin_x2
;
5694 case nir_intrinsic_ssbo_atomic_umin
:
5695 op32
= aco_opcode::buffer_atomic_umin
;
5696 op64
= aco_opcode::buffer_atomic_umin_x2
;
5698 case nir_intrinsic_ssbo_atomic_imax
:
5699 op32
= aco_opcode::buffer_atomic_smax
;
5700 op64
= aco_opcode::buffer_atomic_smax_x2
;
5702 case nir_intrinsic_ssbo_atomic_umax
:
5703 op32
= aco_opcode::buffer_atomic_umax
;
5704 op64
= aco_opcode::buffer_atomic_umax_x2
;
5706 case nir_intrinsic_ssbo_atomic_and
:
5707 op32
= aco_opcode::buffer_atomic_and
;
5708 op64
= aco_opcode::buffer_atomic_and_x2
;
5710 case nir_intrinsic_ssbo_atomic_or
:
5711 op32
= aco_opcode::buffer_atomic_or
;
5712 op64
= aco_opcode::buffer_atomic_or_x2
;
5714 case nir_intrinsic_ssbo_atomic_xor
:
5715 op32
= aco_opcode::buffer_atomic_xor
;
5716 op64
= aco_opcode::buffer_atomic_xor_x2
;
5718 case nir_intrinsic_ssbo_atomic_exchange
:
5719 op32
= aco_opcode::buffer_atomic_swap
;
5720 op64
= aco_opcode::buffer_atomic_swap_x2
;
5722 case nir_intrinsic_ssbo_atomic_comp_swap
:
5723 op32
= aco_opcode::buffer_atomic_cmpswap
;
5724 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
5727 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5729 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5730 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5731 mubuf
->operands
[0] = Operand(rsrc
);
5732 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5733 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5734 mubuf
->operands
[3] = Operand(data
);
5735 if (return_previous
)
5736 mubuf
->definitions
[0] = Definition(dst
);
5738 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
5739 mubuf
->glc
= return_previous
;
5740 mubuf
->dlc
= false; /* Not needed for atomics */
5741 mubuf
->disable_wqm
= true;
5742 mubuf
->barrier
= barrier_buffer
;
5743 ctx
->program
->needs_exact
= true;
5744 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5747 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5749 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5750 Builder
bld(ctx
->program
, ctx
->block
);
5751 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
5752 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
5755 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
5757 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5758 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5760 if (addr
.type() == RegType::vgpr
)
5761 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
5762 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
5765 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5767 Builder
bld(ctx
->program
, ctx
->block
);
5768 unsigned num_components
= instr
->num_components
;
5769 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
5771 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5772 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5774 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5775 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
5777 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
5778 bool global
= ctx
->options
->chip_class
>= GFX9
;
5780 if (ctx
->options
->chip_class
>= GFX7
) {
5782 switch (num_bytes
) {
5784 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
5787 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
5790 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
5793 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
5796 unreachable("load_global not implemented for this size.");
5799 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
5800 flat
->operands
[0] = Operand(addr
);
5801 flat
->operands
[1] = Operand(s1
);
5804 flat
->barrier
= barrier_buffer
;
5806 if (dst
.type() == RegType::sgpr
) {
5807 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5808 flat
->definitions
[0] = Definition(vec
);
5809 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5810 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
5812 flat
->definitions
[0] = Definition(dst
);
5813 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5815 emit_split_vector(ctx
, dst
, num_components
);
5817 assert(ctx
->options
->chip_class
== GFX6
);
5819 /* GFX6 doesn't support loading vec3, expand to vec4. */
5820 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
5823 switch (num_bytes
) {
5825 op
= aco_opcode::buffer_load_dword
;
5828 op
= aco_opcode::buffer_load_dwordx2
;
5831 op
= aco_opcode::buffer_load_dwordx4
;
5834 unreachable("load_global not implemented for this size.");
5837 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
5839 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
5840 mubuf
->operands
[0] = Operand(rsrc
);
5841 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
5842 mubuf
->operands
[2] = Operand(0u);
5846 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
5847 mubuf
->disable_wqm
= false;
5848 mubuf
->barrier
= barrier_buffer
;
5849 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
5852 if (dst
.size() == 3) {
5853 Temp vec
= bld
.tmp(v4
);
5854 instr
->definitions
[0] = Definition(vec
);
5855 bld
.insert(std::move(instr
));
5856 emit_split_vector(ctx
, vec
, 4);
5858 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
5859 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
5860 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
5861 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
5864 if (dst
.type() == RegType::sgpr
) {
5865 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5866 instr
->definitions
[0] = Definition(vec
);
5867 bld
.insert(std::move(instr
));
5868 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
5869 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
5871 instr
->definitions
[0] = Definition(dst
);
5872 bld
.insert(std::move(instr
));
5873 emit_split_vector(ctx
, dst
, num_components
);
5877 switch (num_bytes
) {
5879 op
= aco_opcode::s_load_dword
;
5882 op
= aco_opcode::s_load_dwordx2
;
5886 op
= aco_opcode::s_load_dwordx4
;
5889 unreachable("load_global not implemented for this size.");
5891 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
5892 load
->operands
[0] = Operand(addr
);
5893 load
->operands
[1] = Operand(0u);
5894 load
->definitions
[0] = Definition(dst
);
5897 load
->barrier
= barrier_buffer
;
5898 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
5900 if (dst
.size() == 3) {
5902 Temp vec
= bld
.tmp(s4
);
5903 load
->definitions
[0] = Definition(vec
);
5904 ctx
->block
->instructions
.emplace_back(std::move(load
));
5905 emit_split_vector(ctx
, vec
, 4);
5907 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5908 emit_extract_vector(ctx
, vec
, 0, s1
),
5909 emit_extract_vector(ctx
, vec
, 1, s1
),
5910 emit_extract_vector(ctx
, vec
, 2, s1
));
5912 ctx
->block
->instructions
.emplace_back(std::move(load
));
5917 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5919 Builder
bld(ctx
->program
, ctx
->block
);
5920 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5922 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5923 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5925 if (ctx
->options
->chip_class
>= GFX7
)
5926 addr
= as_vgpr(ctx
, addr
);
5928 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5931 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5932 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
5933 /* GFX6 doesn't support storing vec3, split it. */
5934 writemask
|= 1u << (start
+ 2);
5937 unsigned num_bytes
= count
* elem_size_bytes
;
5939 Temp write_data
= data
;
5940 if (count
!= instr
->num_components
) {
5941 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5942 for (int i
= 0; i
< count
; i
++)
5943 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
5944 write_data
= bld
.tmp(RegType::vgpr
, count
);
5945 vec
->definitions
[0] = Definition(write_data
);
5946 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5949 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5950 unsigned offset
= start
* elem_size_bytes
;
5952 if (ctx
->options
->chip_class
>= GFX7
) {
5953 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
5954 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
5955 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
5956 Temp carry
= bld
.tmp(bld
.lm
);
5957 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
5959 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
5960 Operand(offset
), addr0
);
5961 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
5963 carry
).def(1).setHint(vcc
);
5965 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
5970 bool global
= ctx
->options
->chip_class
>= GFX9
;
5972 switch (num_bytes
) {
5974 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
5977 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
5980 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
5983 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
5986 unreachable("store_global not implemented for this size.");
5989 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
5990 flat
->operands
[0] = Operand(addr
);
5991 flat
->operands
[1] = Operand(s1
);
5992 flat
->operands
[2] = Operand(data
);
5995 flat
->offset
= offset
;
5996 flat
->disable_wqm
= true;
5997 flat
->barrier
= barrier_buffer
;
5998 ctx
->program
->needs_exact
= true;
5999 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6001 assert(ctx
->options
->chip_class
== GFX6
);
6004 switch (num_bytes
) {
6006 op
= aco_opcode::buffer_store_dword
;
6009 op
= aco_opcode::buffer_store_dwordx2
;
6012 op
= aco_opcode::buffer_store_dwordx4
;
6015 unreachable("store_global not implemented for this size.");
6018 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6020 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6021 mubuf
->operands
[0] = Operand(rsrc
);
6022 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6023 mubuf
->operands
[2] = Operand(0u);
6024 mubuf
->operands
[3] = Operand(write_data
);
6027 mubuf
->offset
= offset
;
6028 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6029 mubuf
->disable_wqm
= true;
6030 mubuf
->barrier
= barrier_buffer
;
6031 ctx
->program
->needs_exact
= true;
6032 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6037 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6039 /* return the previous value if dest is ever used */
6040 bool return_previous
= false;
6041 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6042 return_previous
= true;
6045 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6046 return_previous
= true;
6050 Builder
bld(ctx
->program
, ctx
->block
);
6051 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6052 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6054 if (ctx
->options
->chip_class
>= GFX7
)
6055 addr
= as_vgpr(ctx
, addr
);
6057 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6058 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6059 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6061 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6063 aco_opcode op32
, op64
;
6065 if (ctx
->options
->chip_class
>= GFX7
) {
6066 bool global
= ctx
->options
->chip_class
>= GFX9
;
6067 switch (instr
->intrinsic
) {
6068 case nir_intrinsic_global_atomic_add
:
6069 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6070 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6072 case nir_intrinsic_global_atomic_imin
:
6073 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6074 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6076 case nir_intrinsic_global_atomic_umin
:
6077 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6078 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6080 case nir_intrinsic_global_atomic_imax
:
6081 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6082 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6084 case nir_intrinsic_global_atomic_umax
:
6085 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6086 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6088 case nir_intrinsic_global_atomic_and
:
6089 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6090 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6092 case nir_intrinsic_global_atomic_or
:
6093 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6094 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6096 case nir_intrinsic_global_atomic_xor
:
6097 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6098 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6100 case nir_intrinsic_global_atomic_exchange
:
6101 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6102 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6104 case nir_intrinsic_global_atomic_comp_swap
:
6105 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6106 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6109 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6112 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6113 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6114 flat
->operands
[0] = Operand(addr
);
6115 flat
->operands
[1] = Operand(s1
);
6116 flat
->operands
[2] = Operand(data
);
6117 if (return_previous
)
6118 flat
->definitions
[0] = Definition(dst
);
6119 flat
->glc
= return_previous
;
6120 flat
->dlc
= false; /* Not needed for atomics */
6122 flat
->disable_wqm
= true;
6123 flat
->barrier
= barrier_buffer
;
6124 ctx
->program
->needs_exact
= true;
6125 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6127 assert(ctx
->options
->chip_class
== GFX6
);
6129 switch (instr
->intrinsic
) {
6130 case nir_intrinsic_global_atomic_add
:
6131 op32
= aco_opcode::buffer_atomic_add
;
6132 op64
= aco_opcode::buffer_atomic_add_x2
;
6134 case nir_intrinsic_global_atomic_imin
:
6135 op32
= aco_opcode::buffer_atomic_smin
;
6136 op64
= aco_opcode::buffer_atomic_smin_x2
;
6138 case nir_intrinsic_global_atomic_umin
:
6139 op32
= aco_opcode::buffer_atomic_umin
;
6140 op64
= aco_opcode::buffer_atomic_umin_x2
;
6142 case nir_intrinsic_global_atomic_imax
:
6143 op32
= aco_opcode::buffer_atomic_smax
;
6144 op64
= aco_opcode::buffer_atomic_smax_x2
;
6146 case nir_intrinsic_global_atomic_umax
:
6147 op32
= aco_opcode::buffer_atomic_umax
;
6148 op64
= aco_opcode::buffer_atomic_umax_x2
;
6150 case nir_intrinsic_global_atomic_and
:
6151 op32
= aco_opcode::buffer_atomic_and
;
6152 op64
= aco_opcode::buffer_atomic_and_x2
;
6154 case nir_intrinsic_global_atomic_or
:
6155 op32
= aco_opcode::buffer_atomic_or
;
6156 op64
= aco_opcode::buffer_atomic_or_x2
;
6158 case nir_intrinsic_global_atomic_xor
:
6159 op32
= aco_opcode::buffer_atomic_xor
;
6160 op64
= aco_opcode::buffer_atomic_xor_x2
;
6162 case nir_intrinsic_global_atomic_exchange
:
6163 op32
= aco_opcode::buffer_atomic_swap
;
6164 op64
= aco_opcode::buffer_atomic_swap_x2
;
6166 case nir_intrinsic_global_atomic_comp_swap
:
6167 op32
= aco_opcode::buffer_atomic_cmpswap
;
6168 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6171 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6174 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6176 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6178 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6179 mubuf
->operands
[0] = Operand(rsrc
);
6180 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6181 mubuf
->operands
[2] = Operand(0u);
6182 mubuf
->operands
[3] = Operand(data
);
6183 if (return_previous
)
6184 mubuf
->definitions
[0] = Definition(dst
);
6185 mubuf
->glc
= return_previous
;
6188 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6189 mubuf
->disable_wqm
= true;
6190 mubuf
->barrier
= barrier_buffer
;
6191 ctx
->program
->needs_exact
= true;
6192 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6196 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6197 Builder
bld(ctx
->program
, ctx
->block
);
6198 switch(instr
->intrinsic
) {
6199 case nir_intrinsic_group_memory_barrier
:
6200 case nir_intrinsic_memory_barrier
:
6201 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6203 case nir_intrinsic_memory_barrier_buffer
:
6204 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6206 case nir_intrinsic_memory_barrier_image
:
6207 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6209 case nir_intrinsic_memory_barrier_tcs_patch
:
6210 case nir_intrinsic_memory_barrier_shared
:
6211 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6214 unreachable("Unimplemented memory barrier intrinsic");
6219 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6221 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6222 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6223 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6224 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6225 Builder
bld(ctx
->program
, ctx
->block
);
6227 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6228 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6229 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6232 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6234 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6235 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6236 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6237 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6238 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6240 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6241 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6244 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6246 unsigned offset
= nir_intrinsic_base(instr
);
6247 Operand m
= load_lds_size_m0(ctx
);
6248 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6249 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6251 unsigned num_operands
= 3;
6252 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6253 switch(instr
->intrinsic
) {
6254 case nir_intrinsic_shared_atomic_add
:
6255 op32
= aco_opcode::ds_add_u32
;
6256 op64
= aco_opcode::ds_add_u64
;
6257 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6258 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6260 case nir_intrinsic_shared_atomic_imin
:
6261 op32
= aco_opcode::ds_min_i32
;
6262 op64
= aco_opcode::ds_min_i64
;
6263 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6264 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6266 case nir_intrinsic_shared_atomic_umin
:
6267 op32
= aco_opcode::ds_min_u32
;
6268 op64
= aco_opcode::ds_min_u64
;
6269 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6270 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6272 case nir_intrinsic_shared_atomic_imax
:
6273 op32
= aco_opcode::ds_max_i32
;
6274 op64
= aco_opcode::ds_max_i64
;
6275 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6276 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6278 case nir_intrinsic_shared_atomic_umax
:
6279 op32
= aco_opcode::ds_max_u32
;
6280 op64
= aco_opcode::ds_max_u64
;
6281 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6282 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6284 case nir_intrinsic_shared_atomic_and
:
6285 op32
= aco_opcode::ds_and_b32
;
6286 op64
= aco_opcode::ds_and_b64
;
6287 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6288 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6290 case nir_intrinsic_shared_atomic_or
:
6291 op32
= aco_opcode::ds_or_b32
;
6292 op64
= aco_opcode::ds_or_b64
;
6293 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6294 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6296 case nir_intrinsic_shared_atomic_xor
:
6297 op32
= aco_opcode::ds_xor_b32
;
6298 op64
= aco_opcode::ds_xor_b64
;
6299 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6300 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6302 case nir_intrinsic_shared_atomic_exchange
:
6303 op32
= aco_opcode::ds_write_b32
;
6304 op64
= aco_opcode::ds_write_b64
;
6305 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6306 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6308 case nir_intrinsic_shared_atomic_comp_swap
:
6309 op32
= aco_opcode::ds_cmpst_b32
;
6310 op64
= aco_opcode::ds_cmpst_b64
;
6311 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6312 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6316 unreachable("Unhandled shared atomic intrinsic");
6319 /* return the previous value if dest is ever used */
6320 bool return_previous
= false;
6321 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6322 return_previous
= true;
6325 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6326 return_previous
= true;
6331 if (data
.size() == 1) {
6332 assert(instr
->dest
.ssa
.bit_size
== 32);
6333 op
= return_previous
? op32_rtn
: op32
;
6335 assert(instr
->dest
.ssa
.bit_size
== 64);
6336 op
= return_previous
? op64_rtn
: op64
;
6339 if (offset
> 65535) {
6340 Builder
bld(ctx
->program
, ctx
->block
);
6341 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6345 aco_ptr
<DS_instruction
> ds
;
6346 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6347 ds
->operands
[0] = Operand(address
);
6348 ds
->operands
[1] = Operand(data
);
6349 if (num_operands
== 4)
6350 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6351 ds
->operands
[num_operands
- 1] = m
;
6352 ds
->offset0
= offset
;
6353 if (return_previous
)
6354 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6355 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6358 Temp
get_scratch_resource(isel_context
*ctx
)
6360 Builder
bld(ctx
->program
, ctx
->block
);
6361 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6362 if (ctx
->stage
!= compute_cs
)
6363 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6365 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6366 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6368 if (ctx
->program
->chip_class
>= GFX10
) {
6369 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6370 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6371 S_008F0C_RESOURCE_LEVEL(1);
6372 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6373 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6374 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6377 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6378 if (ctx
->program
->chip_class
<= GFX8
)
6379 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6381 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6384 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6385 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6386 Builder
bld(ctx
->program
, ctx
->block
);
6387 Temp rsrc
= get_scratch_resource(ctx
);
6388 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6389 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6392 switch (dst
.size()) {
6394 op
= aco_opcode::buffer_load_dword
;
6397 op
= aco_opcode::buffer_load_dwordx2
;
6400 op
= aco_opcode::buffer_load_dwordx3
;
6403 op
= aco_opcode::buffer_load_dwordx4
;
6407 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6408 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6409 bld
.def(v4
), rsrc
, offset
,
6410 ctx
->program
->scratch_offset
, 0, true);
6411 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6412 aco_opcode::buffer_load_dwordx4
,
6413 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6414 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6415 emit_split_vector(ctx
, lower
, 2);
6416 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6417 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6418 if (dst
.size() == 8) {
6419 emit_split_vector(ctx
, upper
, 2);
6420 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6421 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6426 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6427 Format::PSEUDO
, dst
.size() / 2, 1)};
6428 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6429 vec
->operands
[i
] = Operand(elems
[i
]);
6430 vec
->definitions
[0] = Definition(dst
);
6431 bld
.insert(std::move(vec
));
6432 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6436 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6439 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6440 emit_split_vector(ctx
, dst
, instr
->num_components
);
6443 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6444 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6445 Builder
bld(ctx
->program
, ctx
->block
);
6446 Temp rsrc
= get_scratch_resource(ctx
);
6447 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6448 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6450 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6451 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6455 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6456 int num_bytes
= count
* elem_size_bytes
;
6458 if (num_bytes
> 16) {
6459 assert(elem_size_bytes
== 8);
6460 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6465 // TODO: check alignment of sub-dword stores
6466 // TODO: split 3 bytes. there is no store instruction for that
6469 if (count
!= instr
->num_components
) {
6470 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6471 for (int i
= 0; i
< count
; i
++) {
6472 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6473 vec
->operands
[i
] = Operand(elem
);
6475 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6476 vec
->definitions
[0] = Definition(write_data
);
6477 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6483 switch (num_bytes
) {
6485 op
= aco_opcode::buffer_store_dword
;
6488 op
= aco_opcode::buffer_store_dwordx2
;
6491 op
= aco_opcode::buffer_store_dwordx3
;
6494 op
= aco_opcode::buffer_store_dwordx4
;
6497 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6500 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6504 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6505 uint8_t log2_ps_iter_samples
;
6506 if (ctx
->program
->info
->ps
.force_persample
) {
6507 log2_ps_iter_samples
=
6508 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6510 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6513 /* The bit pattern matches that used by fixed function fragment
6515 static const unsigned ps_iter_masks
[] = {
6516 0xffff, /* not used */
6522 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6524 Builder
bld(ctx
->program
, ctx
->block
);
6526 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6527 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6528 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6529 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6530 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6531 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6534 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6535 Builder
bld(ctx
->program
, ctx
->block
);
6537 unsigned stream
= nir_intrinsic_stream_id(instr
);
6538 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6539 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6540 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6543 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6545 unsigned num_components
=
6546 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6547 assert(num_components
);
6549 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6550 unsigned stream_offset
= 0;
6551 for (unsigned i
= 0; i
< stream
; i
++) {
6552 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6553 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6556 /* Limit on the stride field for <= GFX7. */
6557 assert(stride
< (1 << 14));
6559 Temp gsvs_dwords
[4];
6560 for (unsigned i
= 0; i
< 4; i
++)
6561 gsvs_dwords
[i
] = bld
.tmp(s1
);
6562 bld
.pseudo(aco_opcode::p_split_vector
,
6563 Definition(gsvs_dwords
[0]),
6564 Definition(gsvs_dwords
[1]),
6565 Definition(gsvs_dwords
[2]),
6566 Definition(gsvs_dwords
[3]),
6569 if (stream_offset
) {
6570 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6572 Temp carry
= bld
.tmp(s1
);
6573 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6574 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6577 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6578 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6580 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6581 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6583 unsigned offset
= 0;
6584 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6585 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6588 for (unsigned j
= 0; j
< 4; j
++) {
6589 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6592 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6593 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6594 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6595 if (const_offset
>= 4096u) {
6596 if (vaddr_offset
.isUndefined())
6597 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6599 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6600 const_offset
%= 4096u;
6603 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6604 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6605 mtbuf
->operands
[1] = vaddr_offset
;
6606 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6607 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6608 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6609 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6610 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6611 mtbuf
->offset
= const_offset
;
6614 mtbuf
->barrier
= barrier_gs_data
;
6615 mtbuf
->can_reorder
= true;
6616 bld
.insert(std::move(mtbuf
));
6619 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6622 /* outputs for the next vertex are undefined and keeping them around can
6623 * create invalid IR with control flow */
6624 ctx
->outputs
.mask
[i
] = 0;
6627 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6630 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6632 Builder
bld(ctx
->program
, ctx
->block
);
6634 if (cluster_size
== 1) {
6636 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6637 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6638 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6639 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6640 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6641 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6642 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6643 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6644 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6645 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6646 //subgroupAnd(val) -> (exec & ~val) == 0
6647 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6648 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6649 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6650 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6651 //subgroupOr(val) -> (val & exec) != 0
6652 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6653 return bool_to_vector_condition(ctx
, tmp
);
6654 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6655 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6656 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6657 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6658 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6659 return bool_to_vector_condition(ctx
, tmp
);
6661 //subgroupClustered{And,Or,Xor}(val, n) ->
6662 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6663 //cluster_offset = ~(n - 1) & lane_id
6664 //cluster_mask = ((1 << n) - 1)
6665 //subgroupClusteredAnd():
6666 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6667 //subgroupClusteredOr():
6668 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6669 //subgroupClusteredXor():
6670 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6671 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6672 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6675 if (op
== nir_op_iand
)
6676 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6678 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6680 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6682 if (ctx
->program
->chip_class
<= GFX7
)
6683 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6684 else if (ctx
->program
->wave_size
== 64)
6685 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6687 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6688 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6689 if (cluster_mask
!= 0xffffffff)
6690 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6692 Definition cmp_def
= Definition();
6693 if (op
== nir_op_iand
) {
6694 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6695 } else if (op
== nir_op_ior
) {
6696 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6697 } else if (op
== nir_op_ixor
) {
6698 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6699 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6700 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6702 cmp_def
.setHint(vcc
);
6703 return cmp_def
.getTemp();
6707 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6709 Builder
bld(ctx
->program
, ctx
->block
);
6711 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6712 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6713 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6715 if (op
== nir_op_iand
)
6716 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6718 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6720 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6721 Temp lo
= lohi
.def(0).getTemp();
6722 Temp hi
= lohi
.def(1).getTemp();
6723 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6725 Definition cmp_def
= Definition();
6726 if (op
== nir_op_iand
)
6727 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6728 else if (op
== nir_op_ior
)
6729 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6730 else if (op
== nir_op_ixor
)
6731 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6732 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6733 cmp_def
.setHint(vcc
);
6734 return cmp_def
.getTemp();
6737 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6739 Builder
bld(ctx
->program
, ctx
->block
);
6741 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6742 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6743 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6744 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6745 if (op
== nir_op_iand
)
6746 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6747 else if (op
== nir_op_ior
)
6748 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6749 else if (op
== nir_op_ixor
)
6750 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6756 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
6758 Builder
bld(ctx
->program
, ctx
->block
);
6759 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6760 if (src
.regClass().type() == RegType::vgpr
) {
6761 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
6762 } else if (src
.regClass() == s1
) {
6763 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
6764 } else if (src
.regClass() == s2
) {
6765 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
6767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6768 nir_print_instr(&instr
->instr
, stderr
);
6769 fprintf(stderr
, "\n");
6773 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
6775 Builder
bld(ctx
->program
, ctx
->block
);
6776 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6777 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
6778 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
6780 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
6781 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
6782 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
6783 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
6786 if (ctx
->program
->chip_class
>= GFX8
) {
6787 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
6788 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
6789 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
6790 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
6791 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
6792 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
6794 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
6795 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
6796 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
6797 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
6798 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
6799 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
6800 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
6801 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
6802 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
6803 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
6806 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6807 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
6808 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
6809 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
6810 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
6811 Temp wqm1
= bld
.tmp(v1
);
6812 emit_wqm(ctx
, tmp1
, wqm1
, true);
6813 Temp wqm2
= bld
.tmp(v1
);
6814 emit_wqm(ctx
, tmp2
, wqm2
, true);
6815 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
6819 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6821 Builder
bld(ctx
->program
, ctx
->block
);
6822 switch(instr
->intrinsic
) {
6823 case nir_intrinsic_load_barycentric_sample
:
6824 case nir_intrinsic_load_barycentric_pixel
:
6825 case nir_intrinsic_load_barycentric_centroid
: {
6826 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
6827 Temp bary
= Temp(0, s2
);
6829 case INTERP_MODE_SMOOTH
:
6830 case INTERP_MODE_NONE
:
6831 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
6832 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6833 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
6834 bary
= ctx
->persp_centroid
;
6835 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
6836 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
6838 case INTERP_MODE_NOPERSPECTIVE
:
6839 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
6840 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
6841 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
6842 bary
= ctx
->linear_centroid
;
6843 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
6844 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
6849 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6850 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
6851 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
6852 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6853 Operand(p1
), Operand(p2
));
6854 emit_split_vector(ctx
, dst
, 2);
6857 case nir_intrinsic_load_barycentric_model
: {
6858 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
6860 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6861 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
6862 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
6863 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
6864 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6865 Operand(p1
), Operand(p2
), Operand(p3
));
6866 emit_split_vector(ctx
, dst
, 3);
6869 case nir_intrinsic_load_barycentric_at_sample
: {
6870 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
6871 switch (ctx
->options
->key
.fs
.num_samples
) {
6872 case 2: sample_pos_offset
+= 1 << 3; break;
6873 case 4: sample_pos_offset
+= 3 << 3; break;
6874 case 8: sample_pos_offset
+= 7 << 3; break;
6878 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6879 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
6880 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
6881 if (addr
.type() == RegType::sgpr
) {
6884 sample_pos_offset
+= const_addr
->u32
<< 3;
6885 offset
= Operand(sample_pos_offset
);
6886 } else if (ctx
->options
->chip_class
>= GFX9
) {
6887 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
6889 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
6890 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
6893 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
6894 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
6896 } else if (ctx
->options
->chip_class
>= GFX9
) {
6897 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6898 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
6899 } else if (ctx
->options
->chip_class
>= GFX7
) {
6900 /* addr += private_segment_buffer + sample_pos_offset */
6901 Temp tmp0
= bld
.tmp(s1
);
6902 Temp tmp1
= bld
.tmp(s1
);
6903 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
6904 Definition scc_tmp
= bld
.def(s1
, scc
);
6905 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
6906 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
6907 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6908 Temp pck0
= bld
.tmp(v1
);
6909 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
6910 tmp1
= as_vgpr(ctx
, tmp1
);
6911 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
6912 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
6914 /* sample_pos = flat_load_dwordx2 addr */
6915 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
6917 assert(ctx
->options
->chip_class
== GFX6
);
6919 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6920 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6921 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
6923 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6924 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
6926 sample_pos
= bld
.tmp(v2
);
6928 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
6929 load
->definitions
[0] = Definition(sample_pos
);
6930 load
->operands
[0] = Operand(rsrc
);
6931 load
->operands
[1] = Operand(addr
);
6932 load
->operands
[2] = Operand(0u);
6933 load
->offset
= sample_pos_offset
;
6935 load
->addr64
= true;
6938 load
->disable_wqm
= false;
6939 load
->barrier
= barrier_none
;
6940 load
->can_reorder
= true;
6941 ctx
->block
->instructions
.emplace_back(std::move(load
));
6944 /* sample_pos -= 0.5 */
6945 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
6946 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
6947 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
6948 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
6949 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
6951 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
6954 case nir_intrinsic_load_barycentric_at_offset
: {
6955 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6956 RegClass rc
= RegClass(offset
.type(), 1);
6957 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
6958 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
6959 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
6962 case nir_intrinsic_load_front_face
: {
6963 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6964 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
6967 case nir_intrinsic_load_view_index
: {
6968 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
6969 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6970 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
6976 case nir_intrinsic_load_layer_id
: {
6977 unsigned idx
= nir_intrinsic_base(instr
);
6978 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6979 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
6982 case nir_intrinsic_load_frag_coord
: {
6983 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
6986 case nir_intrinsic_load_sample_pos
: {
6987 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
6988 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
6989 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6990 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
6991 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
6994 case nir_intrinsic_load_tess_coord
:
6995 visit_load_tess_coord(ctx
, instr
);
6997 case nir_intrinsic_load_interpolated_input
:
6998 visit_load_interpolated_input(ctx
, instr
);
7000 case nir_intrinsic_store_output
:
7001 visit_store_output(ctx
, instr
);
7003 case nir_intrinsic_load_input
:
7004 case nir_intrinsic_load_input_vertex
:
7005 visit_load_input(ctx
, instr
);
7007 case nir_intrinsic_load_output
:
7008 visit_load_output(ctx
, instr
);
7010 case nir_intrinsic_load_per_vertex_input
:
7011 visit_load_per_vertex_input(ctx
, instr
);
7013 case nir_intrinsic_load_per_vertex_output
:
7014 visit_load_per_vertex_output(ctx
, instr
);
7016 case nir_intrinsic_store_per_vertex_output
:
7017 visit_store_per_vertex_output(ctx
, instr
);
7019 case nir_intrinsic_load_ubo
:
7020 visit_load_ubo(ctx
, instr
);
7022 case nir_intrinsic_load_push_constant
:
7023 visit_load_push_constant(ctx
, instr
);
7025 case nir_intrinsic_load_constant
:
7026 visit_load_constant(ctx
, instr
);
7028 case nir_intrinsic_vulkan_resource_index
:
7029 visit_load_resource(ctx
, instr
);
7031 case nir_intrinsic_discard
:
7032 visit_discard(ctx
, instr
);
7034 case nir_intrinsic_discard_if
:
7035 visit_discard_if(ctx
, instr
);
7037 case nir_intrinsic_load_shared
:
7038 visit_load_shared(ctx
, instr
);
7040 case nir_intrinsic_store_shared
:
7041 visit_store_shared(ctx
, instr
);
7043 case nir_intrinsic_shared_atomic_add
:
7044 case nir_intrinsic_shared_atomic_imin
:
7045 case nir_intrinsic_shared_atomic_umin
:
7046 case nir_intrinsic_shared_atomic_imax
:
7047 case nir_intrinsic_shared_atomic_umax
:
7048 case nir_intrinsic_shared_atomic_and
:
7049 case nir_intrinsic_shared_atomic_or
:
7050 case nir_intrinsic_shared_atomic_xor
:
7051 case nir_intrinsic_shared_atomic_exchange
:
7052 case nir_intrinsic_shared_atomic_comp_swap
:
7053 visit_shared_atomic(ctx
, instr
);
7055 case nir_intrinsic_image_deref_load
:
7056 visit_image_load(ctx
, instr
);
7058 case nir_intrinsic_image_deref_store
:
7059 visit_image_store(ctx
, instr
);
7061 case nir_intrinsic_image_deref_atomic_add
:
7062 case nir_intrinsic_image_deref_atomic_umin
:
7063 case nir_intrinsic_image_deref_atomic_imin
:
7064 case nir_intrinsic_image_deref_atomic_umax
:
7065 case nir_intrinsic_image_deref_atomic_imax
:
7066 case nir_intrinsic_image_deref_atomic_and
:
7067 case nir_intrinsic_image_deref_atomic_or
:
7068 case nir_intrinsic_image_deref_atomic_xor
:
7069 case nir_intrinsic_image_deref_atomic_exchange
:
7070 case nir_intrinsic_image_deref_atomic_comp_swap
:
7071 visit_image_atomic(ctx
, instr
);
7073 case nir_intrinsic_image_deref_size
:
7074 visit_image_size(ctx
, instr
);
7076 case nir_intrinsic_load_ssbo
:
7077 visit_load_ssbo(ctx
, instr
);
7079 case nir_intrinsic_store_ssbo
:
7080 visit_store_ssbo(ctx
, instr
);
7082 case nir_intrinsic_load_global
:
7083 visit_load_global(ctx
, instr
);
7085 case nir_intrinsic_store_global
:
7086 visit_store_global(ctx
, instr
);
7088 case nir_intrinsic_global_atomic_add
:
7089 case nir_intrinsic_global_atomic_imin
:
7090 case nir_intrinsic_global_atomic_umin
:
7091 case nir_intrinsic_global_atomic_imax
:
7092 case nir_intrinsic_global_atomic_umax
:
7093 case nir_intrinsic_global_atomic_and
:
7094 case nir_intrinsic_global_atomic_or
:
7095 case nir_intrinsic_global_atomic_xor
:
7096 case nir_intrinsic_global_atomic_exchange
:
7097 case nir_intrinsic_global_atomic_comp_swap
:
7098 visit_global_atomic(ctx
, instr
);
7100 case nir_intrinsic_ssbo_atomic_add
:
7101 case nir_intrinsic_ssbo_atomic_imin
:
7102 case nir_intrinsic_ssbo_atomic_umin
:
7103 case nir_intrinsic_ssbo_atomic_imax
:
7104 case nir_intrinsic_ssbo_atomic_umax
:
7105 case nir_intrinsic_ssbo_atomic_and
:
7106 case nir_intrinsic_ssbo_atomic_or
:
7107 case nir_intrinsic_ssbo_atomic_xor
:
7108 case nir_intrinsic_ssbo_atomic_exchange
:
7109 case nir_intrinsic_ssbo_atomic_comp_swap
:
7110 visit_atomic_ssbo(ctx
, instr
);
7112 case nir_intrinsic_load_scratch
:
7113 visit_load_scratch(ctx
, instr
);
7115 case nir_intrinsic_store_scratch
:
7116 visit_store_scratch(ctx
, instr
);
7118 case nir_intrinsic_get_buffer_size
:
7119 visit_get_buffer_size(ctx
, instr
);
7121 case nir_intrinsic_control_barrier
: {
7122 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7123 /* GFX6 only (thanks to a hw bug workaround):
7124 * The real barrier instruction isn’t needed, because an entire patch
7125 * always fits into a single wave.
7130 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7131 bld
.sopp(aco_opcode::s_barrier
);
7135 case nir_intrinsic_memory_barrier_tcs_patch
:
7136 case nir_intrinsic_group_memory_barrier
:
7137 case nir_intrinsic_memory_barrier
:
7138 case nir_intrinsic_memory_barrier_buffer
:
7139 case nir_intrinsic_memory_barrier_image
:
7140 case nir_intrinsic_memory_barrier_shared
:
7141 emit_memory_barrier(ctx
, instr
);
7143 case nir_intrinsic_load_num_work_groups
: {
7144 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7145 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7146 emit_split_vector(ctx
, dst
, 3);
7149 case nir_intrinsic_load_local_invocation_id
: {
7150 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7151 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7152 emit_split_vector(ctx
, dst
, 3);
7155 case nir_intrinsic_load_work_group_id
: {
7156 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7157 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7159 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7160 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7161 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7162 emit_split_vector(ctx
, dst
, 3);
7165 case nir_intrinsic_load_local_invocation_index
: {
7166 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7168 /* The tg_size bits [6:11] contain the subgroup id,
7169 * we need this multiplied by the wave size, and then OR the thread id to it.
7171 if (ctx
->program
->wave_size
== 64) {
7172 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7173 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7174 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7175 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7177 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7178 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7179 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7180 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7184 case nir_intrinsic_load_subgroup_id
: {
7185 if (ctx
->stage
== compute_cs
) {
7186 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7187 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7189 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7193 case nir_intrinsic_load_subgroup_invocation
: {
7194 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7197 case nir_intrinsic_load_num_subgroups
: {
7198 if (ctx
->stage
== compute_cs
)
7199 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7200 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7202 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7205 case nir_intrinsic_ballot
: {
7206 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7207 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7208 Definition tmp
= bld
.def(dst
.regClass());
7209 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7210 if (instr
->src
[0].ssa
->bit_size
== 1) {
7211 assert(src
.regClass() == bld
.lm
);
7212 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7213 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7214 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7215 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7216 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7218 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7219 nir_print_instr(&instr
->instr
, stderr
);
7220 fprintf(stderr
, "\n");
7222 if (dst
.size() != bld
.lm
.size()) {
7223 /* Wave32 with ballot size set to 64 */
7224 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7226 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7229 case nir_intrinsic_shuffle
:
7230 case nir_intrinsic_read_invocation
: {
7231 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7232 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7233 emit_uniform_subgroup(ctx
, instr
, src
);
7235 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7236 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7237 tid
= bld
.as_uniform(tid
);
7238 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7239 if (src
.regClass() == v1
) {
7240 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7241 } else if (src
.regClass() == v2
) {
7242 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7243 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7244 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7245 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7246 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7247 emit_split_vector(ctx
, dst
, 2);
7248 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7249 assert(src
.regClass() == bld
.lm
);
7250 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7251 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7252 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7253 assert(src
.regClass() == bld
.lm
);
7255 if (ctx
->program
->chip_class
<= GFX7
)
7256 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7257 else if (ctx
->program
->wave_size
== 64)
7258 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7260 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7261 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7262 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7263 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7265 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7266 nir_print_instr(&instr
->instr
, stderr
);
7267 fprintf(stderr
, "\n");
7272 case nir_intrinsic_load_sample_id
: {
7273 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7274 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7277 case nir_intrinsic_load_sample_mask_in
: {
7278 visit_load_sample_mask_in(ctx
, instr
);
7281 case nir_intrinsic_read_first_invocation
: {
7282 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7283 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7284 if (src
.regClass() == v1
) {
7286 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7288 } else if (src
.regClass() == v2
) {
7289 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7290 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7291 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7292 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7293 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7294 emit_split_vector(ctx
, dst
, 2);
7295 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7296 assert(src
.regClass() == bld
.lm
);
7297 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7298 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7299 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7300 } else if (src
.regClass() == s1
) {
7301 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7302 } else if (src
.regClass() == s2
) {
7303 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7305 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7306 nir_print_instr(&instr
->instr
, stderr
);
7307 fprintf(stderr
, "\n");
7311 case nir_intrinsic_vote_all
: {
7312 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7313 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7314 assert(src
.regClass() == bld
.lm
);
7315 assert(dst
.regClass() == bld
.lm
);
7317 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7318 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7319 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7322 case nir_intrinsic_vote_any
: {
7323 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7324 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7325 assert(src
.regClass() == bld
.lm
);
7326 assert(dst
.regClass() == bld
.lm
);
7328 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7329 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7332 case nir_intrinsic_reduce
:
7333 case nir_intrinsic_inclusive_scan
:
7334 case nir_intrinsic_exclusive_scan
: {
7335 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7336 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7337 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7338 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7339 nir_intrinsic_cluster_size(instr
) : 0;
7340 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7342 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7343 emit_uniform_subgroup(ctx
, instr
, src
);
7344 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7345 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7347 else if (op
== nir_op_iadd
)
7349 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7351 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7353 switch (instr
->intrinsic
) {
7354 case nir_intrinsic_reduce
:
7355 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7357 case nir_intrinsic_exclusive_scan
:
7358 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7360 case nir_intrinsic_inclusive_scan
:
7361 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7366 } else if (cluster_size
== 1) {
7367 bld
.copy(Definition(dst
), src
);
7369 src
= as_vgpr(ctx
, src
);
7373 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7388 unreachable("unknown reduction op");
7393 switch (instr
->intrinsic
) {
7394 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7395 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7396 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7398 unreachable("unknown reduce intrinsic");
7401 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7402 reduce
->operands
[0] = Operand(src
);
7403 // filled in by aco_reduce_assign.cpp, used internally as part of the
7405 assert(dst
.size() == 1 || dst
.size() == 2);
7406 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7407 reduce
->operands
[2] = Operand(v1
.as_linear());
7409 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7410 reduce
->definitions
[0] = Definition(tmp_dst
);
7411 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7412 reduce
->definitions
[2] = Definition();
7413 reduce
->definitions
[3] = Definition(scc
, s1
);
7414 reduce
->definitions
[4] = Definition();
7415 reduce
->reduce_op
= reduce_op
;
7416 reduce
->cluster_size
= cluster_size
;
7417 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7419 emit_wqm(ctx
, tmp_dst
, dst
);
7423 case nir_intrinsic_quad_broadcast
: {
7424 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7425 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7426 emit_uniform_subgroup(ctx
, instr
, src
);
7428 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7429 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7430 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7432 if (instr
->dest
.ssa
.bit_size
== 1) {
7433 assert(src
.regClass() == bld
.lm
);
7434 assert(dst
.regClass() == bld
.lm
);
7435 uint32_t half_mask
= 0x11111111u
<< lane
;
7436 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7437 Temp tmp
= bld
.tmp(bld
.lm
);
7438 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7439 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7440 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7441 emit_wqm(ctx
, tmp
, dst
);
7442 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7443 if (ctx
->program
->chip_class
>= GFX8
)
7444 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7446 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7447 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7448 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7449 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7450 if (ctx
->program
->chip_class
>= GFX8
) {
7451 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7452 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7454 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7455 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7457 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7458 emit_split_vector(ctx
, dst
, 2);
7460 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7461 nir_print_instr(&instr
->instr
, stderr
);
7462 fprintf(stderr
, "\n");
7467 case nir_intrinsic_quad_swap_horizontal
:
7468 case nir_intrinsic_quad_swap_vertical
:
7469 case nir_intrinsic_quad_swap_diagonal
:
7470 case nir_intrinsic_quad_swizzle_amd
: {
7471 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7472 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7473 emit_uniform_subgroup(ctx
, instr
, src
);
7476 uint16_t dpp_ctrl
= 0;
7477 switch (instr
->intrinsic
) {
7478 case nir_intrinsic_quad_swap_horizontal
:
7479 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7481 case nir_intrinsic_quad_swap_vertical
:
7482 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7484 case nir_intrinsic_quad_swap_diagonal
:
7485 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7487 case nir_intrinsic_quad_swizzle_amd
:
7488 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7493 if (ctx
->program
->chip_class
< GFX8
)
7494 dpp_ctrl
|= (1 << 15);
7496 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7497 if (instr
->dest
.ssa
.bit_size
== 1) {
7498 assert(src
.regClass() == bld
.lm
);
7499 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7500 if (ctx
->program
->chip_class
>= GFX8
)
7501 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7503 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7504 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7505 emit_wqm(ctx
, tmp
, dst
);
7506 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7508 if (ctx
->program
->chip_class
>= GFX8
)
7509 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7511 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7512 emit_wqm(ctx
, tmp
, dst
);
7513 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7514 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7515 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7516 if (ctx
->program
->chip_class
>= GFX8
) {
7517 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7518 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7520 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7521 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7524 emit_split_vector(ctx
, dst
, 2);
7526 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7527 nir_print_instr(&instr
->instr
, stderr
);
7528 fprintf(stderr
, "\n");
7532 case nir_intrinsic_masked_swizzle_amd
: {
7533 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7534 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7535 emit_uniform_subgroup(ctx
, instr
, src
);
7538 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7539 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7540 if (dst
.regClass() == v1
) {
7542 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7544 } else if (dst
.regClass() == v2
) {
7545 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7546 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7547 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7548 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7549 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7550 emit_split_vector(ctx
, dst
, 2);
7552 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7553 nir_print_instr(&instr
->instr
, stderr
);
7554 fprintf(stderr
, "\n");
7558 case nir_intrinsic_write_invocation_amd
: {
7559 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7560 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7561 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7562 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7563 if (dst
.regClass() == v1
) {
7564 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7565 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7566 } else if (dst
.regClass() == v2
) {
7567 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7568 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7569 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7570 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7571 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7572 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7573 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7574 emit_split_vector(ctx
, dst
, 2);
7576 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7577 nir_print_instr(&instr
->instr
, stderr
);
7578 fprintf(stderr
, "\n");
7582 case nir_intrinsic_mbcnt_amd
: {
7583 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7584 RegClass rc
= RegClass(src
.type(), 1);
7585 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7586 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7587 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7588 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7589 emit_wqm(ctx
, wqm_tmp
, dst
);
7592 case nir_intrinsic_load_helper_invocation
: {
7593 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7594 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7595 ctx
->block
->kind
|= block_kind_needs_lowering
;
7596 ctx
->program
->needs_exact
= true;
7599 case nir_intrinsic_is_helper_invocation
: {
7600 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7601 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7602 ctx
->block
->kind
|= block_kind_needs_lowering
;
7603 ctx
->program
->needs_exact
= true;
7606 case nir_intrinsic_demote
:
7607 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7609 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7610 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7611 ctx
->block
->kind
|= block_kind_uses_demote
;
7612 ctx
->program
->needs_exact
= true;
7614 case nir_intrinsic_demote_if
: {
7615 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7616 assert(src
.regClass() == bld
.lm
);
7617 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7618 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7620 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7621 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7622 ctx
->block
->kind
|= block_kind_uses_demote
;
7623 ctx
->program
->needs_exact
= true;
7626 case nir_intrinsic_first_invocation
: {
7627 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7628 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7631 case nir_intrinsic_shader_clock
:
7632 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7633 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7635 case nir_intrinsic_load_vertex_id_zero_base
: {
7636 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7637 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7640 case nir_intrinsic_load_first_vertex
: {
7641 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7642 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7645 case nir_intrinsic_load_base_instance
: {
7646 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7647 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7650 case nir_intrinsic_load_instance_id
: {
7651 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7652 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7655 case nir_intrinsic_load_draw_id
: {
7656 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7657 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7660 case nir_intrinsic_load_invocation_id
: {
7661 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7663 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7664 if (ctx
->options
->chip_class
>= GFX10
)
7665 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7667 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7668 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7669 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7670 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7672 unreachable("Unsupported stage for load_invocation_id");
7677 case nir_intrinsic_load_primitive_id
: {
7678 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7680 switch (ctx
->shader
->info
.stage
) {
7681 case MESA_SHADER_GEOMETRY
:
7682 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7684 case MESA_SHADER_TESS_CTRL
:
7685 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7687 case MESA_SHADER_TESS_EVAL
:
7688 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7691 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7696 case nir_intrinsic_load_patch_vertices_in
: {
7697 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7698 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7700 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7701 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7704 case nir_intrinsic_emit_vertex_with_counter
: {
7705 visit_emit_vertex_with_counter(ctx
, instr
);
7708 case nir_intrinsic_end_primitive_with_counter
: {
7709 unsigned stream
= nir_intrinsic_stream_id(instr
);
7710 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7713 case nir_intrinsic_set_vertex_count
: {
7714 /* unused, the HW keeps track of this for us */
7718 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7719 nir_print_instr(&instr
->instr
, stderr
);
7720 fprintf(stderr
, "\n");
7728 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7729 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7730 enum glsl_base_type
*stype
)
7732 nir_deref_instr
*texture_deref_instr
= NULL
;
7733 nir_deref_instr
*sampler_deref_instr
= NULL
;
7736 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7737 switch (instr
->src
[i
].src_type
) {
7738 case nir_tex_src_texture_deref
:
7739 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7741 case nir_tex_src_sampler_deref
:
7742 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7744 case nir_tex_src_plane
:
7745 plane
= nir_src_as_int(instr
->src
[i
].src
);
7752 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
7754 if (!sampler_deref_instr
)
7755 sampler_deref_instr
= texture_deref_instr
;
7758 assert(instr
->op
!= nir_texop_txf_ms
&&
7759 instr
->op
!= nir_texop_samples_identical
);
7760 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
7761 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
7762 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
7763 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
7764 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
7765 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7767 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
7770 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
7772 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
7773 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7774 Builder
bld(ctx
->program
, ctx
->block
);
7776 /* to avoid unnecessary moves, we split and recombine sampler and image */
7777 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
7778 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7779 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7780 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
7781 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
7782 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
7783 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
7784 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
7786 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
7787 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
7788 img
[0], img
[1], img
[2], img
[3],
7789 img
[4], img
[5], img
[6], img
[7]);
7790 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7791 samp
[0], samp
[1], samp
[2], samp
[3]);
7794 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
7795 instr
->op
== nir_texop_samples_identical
))
7796 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7799 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
7800 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
7802 Builder
bld(ctx
->program
, ctx
->block
);
7804 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
7805 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
7806 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
7808 Operand
neg_one(0xbf800000u
);
7809 Operand
one(0x3f800000u
);
7810 Operand
two(0x40000000u
);
7811 Operand
four(0x40800000u
);
7813 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
7814 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
7815 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
7817 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
7818 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
7819 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
7820 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
7823 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
7824 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7825 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
7827 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
7830 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
7831 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
7832 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
7835 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7836 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
7838 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
7839 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
7842 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
7844 Builder
bld(ctx
->program
, ctx
->block
);
7845 Temp ma
, tc
, sc
, id
;
7848 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
7850 // see comment in ac_prepare_cube_coords()
7851 if (ctx
->options
->chip_class
<= GFX8
)
7852 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
7855 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7857 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
7858 vop3a
->operands
[0] = Operand(ma
);
7859 vop3a
->abs
[0] = true;
7860 Temp invma
= bld
.tmp(v1
);
7861 vop3a
->definitions
[0] = Definition(invma
);
7862 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
7864 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7866 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
7868 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7870 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
7872 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7875 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
7876 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
7878 for (unsigned i
= 0; i
< 2; i
++) {
7879 // see comment in ac_prepare_cube_coords()
7881 Temp deriv_sc
, deriv_tc
;
7882 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
7883 &deriv_ma
, &deriv_sc
, &deriv_tc
);
7885 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
7887 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
7888 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
7889 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
7890 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
7891 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
7892 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
7893 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
7896 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
7897 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
7901 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
7908 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
7910 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
7912 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
7913 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
7916 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
7917 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
7918 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
7922 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
7924 Builder
bld(ctx
->program
, ctx
->block
);
7925 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
7926 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
7927 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
7928 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
7929 std::vector
<Temp
> coords
;
7930 std::vector
<Temp
> derivs
;
7931 nir_const_value
*sample_index_cv
= NULL
;
7932 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
7933 enum glsl_base_type stype
;
7934 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
7936 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
7937 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
7938 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
7939 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
7941 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7942 switch (instr
->src
[i
].src_type
) {
7943 case nir_tex_src_coord
: {
7944 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7945 for (unsigned i
= 0; i
< coord
.size(); i
++)
7946 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
7949 case nir_tex_src_bias
:
7950 if (instr
->op
== nir_texop_txb
) {
7951 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7955 case nir_tex_src_lod
: {
7956 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
7958 if (val
&& val
->f32
<= 0.0) {
7961 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7966 case nir_tex_src_comparator
:
7967 if (instr
->is_shadow
) {
7968 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7972 case nir_tex_src_offset
:
7973 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7974 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
7977 case nir_tex_src_ddx
:
7978 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7981 case nir_tex_src_ddy
:
7982 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7985 case nir_tex_src_ms_index
:
7986 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7987 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
7988 has_sample_index
= true;
7990 case nir_tex_src_texture_offset
:
7991 case nir_tex_src_sampler_offset
:
7997 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
7998 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8000 if (instr
->op
== nir_texop_texture_samples
) {
8001 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8003 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8004 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8005 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8006 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8008 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8009 samples
, Operand(1u), bld
.scc(is_msaa
));
8013 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8014 aco_ptr
<Instruction
> tmp_instr
;
8015 Temp acc
, pack
= Temp();
8017 uint32_t pack_const
= 0;
8018 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8019 if (!const_offset
[i
])
8021 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8024 if (offset
.type() == RegType::sgpr
) {
8025 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8026 if (const_offset
[i
])
8029 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8030 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8033 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8036 if (pack
== Temp()) {
8039 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8043 if (pack_const
&& pack
!= Temp())
8044 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8046 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8047 if (const_offset
[i
])
8050 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8051 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8054 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8057 if (pack
== Temp()) {
8060 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8064 if (pack_const
&& pack
!= Temp())
8065 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8067 if (pack_const
&& pack
== Temp())
8068 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8069 else if (pack
== Temp())
8075 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8076 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8078 /* pack derivatives */
8079 if (has_ddx
|| has_ddy
) {
8080 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8081 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8082 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8083 derivs
= {ddy
, zero
, ddy
, zero
};
8085 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8086 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8087 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8088 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8093 if (instr
->coord_components
> 1 &&
8094 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8096 instr
->op
!= nir_texop_txf
)
8097 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8099 if (instr
->coord_components
> 2 &&
8100 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8101 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8102 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8103 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8105 instr
->op
!= nir_texop_txf
&&
8106 instr
->op
!= nir_texop_txf_ms
&&
8107 instr
->op
!= nir_texop_fragment_fetch
&&
8108 instr
->op
!= nir_texop_fragment_mask_fetch
)
8109 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8111 if (ctx
->options
->chip_class
== GFX9
&&
8112 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8113 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8114 assert(coords
.size() > 0 && coords
.size() < 3);
8116 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8117 Operand((uint32_t) 0) :
8118 Operand((uint32_t) 0x3f000000)));
8121 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8123 if (instr
->op
== nir_texop_samples_identical
)
8124 resource
= fmask_ptr
;
8126 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8127 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8128 instr
->op
!= nir_texop_txs
&&
8129 instr
->op
!= nir_texop_fragment_fetch
&&
8130 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8131 assert(has_sample_index
);
8132 Operand
op(sample_index
);
8133 if (sample_index_cv
)
8134 op
= Operand(sample_index_cv
->u32
);
8135 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8138 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8139 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8140 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8141 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8146 /* Build tex instruction */
8147 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8148 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8149 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8151 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8154 /* gather4 selects the component by dmask and always returns vec4 */
8155 if (instr
->op
== nir_texop_tg4
) {
8156 assert(instr
->dest
.ssa
.num_components
== 4);
8157 if (instr
->is_shadow
)
8160 dmask
= 1 << instr
->component
;
8161 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8162 tmp_dst
= bld
.tmp(v4
);
8163 } else if (instr
->op
== nir_texop_samples_identical
) {
8164 tmp_dst
= bld
.tmp(v1
);
8165 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8166 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8169 aco_ptr
<MIMG_instruction
> tex
;
8170 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8172 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8174 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8175 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8178 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8179 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8181 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8182 tex
->operands
[0] = Operand(resource
);
8183 tex
->operands
[1] = Operand(s4
); /* no sampler */
8184 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8185 if (ctx
->options
->chip_class
== GFX9
&&
8186 instr
->op
== nir_texop_txs
&&
8187 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8189 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8190 } else if (instr
->op
== nir_texop_query_levels
) {
8191 tex
->dmask
= 1 << 3;
8196 tex
->definitions
[0] = Definition(tmp_dst
);
8198 tex
->can_reorder
= true;
8199 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8202 /* divide 3rd value by 6 by multiplying with magic number */
8203 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8204 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8205 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8206 assert(instr
->dest
.ssa
.num_components
== 3);
8207 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8208 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8209 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8210 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8215 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8219 Temp tg4_compare_cube_wa64
= Temp();
8221 if (tg4_integer_workarounds
) {
8222 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8223 tex
->operands
[0] = Operand(resource
);
8224 tex
->operands
[1] = Operand(s4
); /* no sampler */
8225 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8229 Temp size
= bld
.tmp(v2
);
8230 tex
->definitions
[0] = Definition(size
);
8231 tex
->can_reorder
= true;
8232 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8233 emit_split_vector(ctx
, size
, size
.size());
8236 for (unsigned i
= 0; i
< 2; i
++) {
8237 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8238 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8239 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8240 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8243 Temp new_coords
[2] = {
8244 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8245 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8248 if (tg4_integer_cube_workaround
) {
8249 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8250 Temp desc
[resource
.size()];
8251 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8252 Format::PSEUDO
, 1, resource
.size())};
8253 split
->operands
[0] = Operand(resource
);
8254 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8255 desc
[i
] = bld
.tmp(s1
);
8256 split
->definitions
[i
] = Definition(desc
[i
]);
8258 ctx
->block
->instructions
.emplace_back(std::move(split
));
8260 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8261 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8262 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8265 if (stype
== GLSL_TYPE_UINT
) {
8266 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8267 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8268 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8269 bld
.scc(compare_cube_wa
));
8271 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8272 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8273 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8274 bld
.scc(compare_cube_wa
));
8276 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8277 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8279 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8281 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8282 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8283 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8285 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8286 Format::PSEUDO
, resource
.size(), 1)};
8287 for (unsigned i
= 0; i
< resource
.size(); i
++)
8288 vec
->operands
[i
] = Operand(desc
[i
]);
8289 resource
= bld
.tmp(resource
.regClass());
8290 vec
->definitions
[0] = Definition(resource
);
8291 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8293 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8294 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8295 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8296 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8298 coords
[0] = new_coords
[0];
8299 coords
[1] = new_coords
[1];
8302 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8303 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8305 assert(coords
.size() == 1);
8306 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8310 op
= aco_opcode::buffer_load_format_x
; break;
8312 op
= aco_opcode::buffer_load_format_xy
; break;
8314 op
= aco_opcode::buffer_load_format_xyz
; break;
8316 op
= aco_opcode::buffer_load_format_xyzw
; break;
8318 unreachable("Tex instruction loads more than 4 components.");
8321 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8322 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8325 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8327 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8328 mubuf
->operands
[0] = Operand(resource
);
8329 mubuf
->operands
[1] = Operand(coords
[0]);
8330 mubuf
->operands
[2] = Operand((uint32_t) 0);
8331 mubuf
->definitions
[0] = Definition(tmp_dst
);
8332 mubuf
->idxen
= true;
8333 mubuf
->can_reorder
= true;
8334 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8336 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8340 /* gather MIMG address components */
8341 std::vector
<Temp
> args
;
8343 args
.emplace_back(offset
);
8345 args
.emplace_back(bias
);
8347 args
.emplace_back(compare
);
8349 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8351 args
.insert(args
.end(), coords
.begin(), coords
.end());
8352 if (has_sample_index
)
8353 args
.emplace_back(sample_index
);
8355 args
.emplace_back(lod
);
8357 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8358 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8359 vec
->definitions
[0] = Definition(arg
);
8360 for (unsigned i
= 0; i
< args
.size(); i
++)
8361 vec
->operands
[i
] = Operand(args
[i
]);
8362 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8365 if (instr
->op
== nir_texop_txf
||
8366 instr
->op
== nir_texop_txf_ms
||
8367 instr
->op
== nir_texop_samples_identical
||
8368 instr
->op
== nir_texop_fragment_fetch
||
8369 instr
->op
== nir_texop_fragment_mask_fetch
) {
8370 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8371 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8372 tex
->operands
[0] = Operand(resource
);
8373 tex
->operands
[1] = Operand(s4
); /* no sampler */
8374 tex
->operands
[2] = Operand(arg
);
8379 tex
->definitions
[0] = Definition(tmp_dst
);
8380 tex
->can_reorder
= true;
8381 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8383 if (instr
->op
== nir_texop_samples_identical
) {
8384 assert(dmask
== 1 && dst
.regClass() == v1
);
8385 assert(dst
.id() != tmp_dst
.id());
8387 Temp tmp
= bld
.tmp(bld
.lm
);
8388 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8389 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8392 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8397 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8398 aco_opcode opcode
= aco_opcode::image_sample
;
8399 if (has_offset
) { /* image_sample_*_o */
8401 opcode
= aco_opcode::image_sample_c_o
;
8403 opcode
= aco_opcode::image_sample_c_d_o
;
8405 opcode
= aco_opcode::image_sample_c_b_o
;
8407 opcode
= aco_opcode::image_sample_c_lz_o
;
8409 opcode
= aco_opcode::image_sample_c_l_o
;
8411 opcode
= aco_opcode::image_sample_o
;
8413 opcode
= aco_opcode::image_sample_d_o
;
8415 opcode
= aco_opcode::image_sample_b_o
;
8417 opcode
= aco_opcode::image_sample_lz_o
;
8419 opcode
= aco_opcode::image_sample_l_o
;
8421 } else { /* no offset */
8423 opcode
= aco_opcode::image_sample_c
;
8425 opcode
= aco_opcode::image_sample_c_d
;
8427 opcode
= aco_opcode::image_sample_c_b
;
8429 opcode
= aco_opcode::image_sample_c_lz
;
8431 opcode
= aco_opcode::image_sample_c_l
;
8433 opcode
= aco_opcode::image_sample
;
8435 opcode
= aco_opcode::image_sample_d
;
8437 opcode
= aco_opcode::image_sample_b
;
8439 opcode
= aco_opcode::image_sample_lz
;
8441 opcode
= aco_opcode::image_sample_l
;
8445 if (instr
->op
== nir_texop_tg4
) {
8447 opcode
= aco_opcode::image_gather4_lz_o
;
8449 opcode
= aco_opcode::image_gather4_c_lz_o
;
8451 opcode
= aco_opcode::image_gather4_lz
;
8453 opcode
= aco_opcode::image_gather4_c_lz
;
8455 } else if (instr
->op
== nir_texop_lod
) {
8456 opcode
= aco_opcode::image_get_lod
;
8459 /* we don't need the bias, sample index, compare value or offset to be
8460 * computed in WQM but if the p_create_vector copies the coordinates, then it
8461 * needs to be in WQM */
8462 if (ctx
->stage
== fragment_fs
&&
8463 !has_derivs
&& !has_lod
&& !level_zero
&&
8464 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8465 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8466 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8468 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8469 tex
->operands
[0] = Operand(resource
);
8470 tex
->operands
[1] = Operand(sampler
);
8471 tex
->operands
[2] = Operand(arg
);
8475 tex
->definitions
[0] = Definition(tmp_dst
);
8476 tex
->can_reorder
= true;
8477 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8479 if (tg4_integer_cube_workaround
) {
8480 assert(tmp_dst
.id() != dst
.id());
8481 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8483 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8485 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8486 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8488 if (stype
== GLSL_TYPE_UINT
)
8489 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8491 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8492 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8494 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8495 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8496 val
[0], val
[1], val
[2], val
[3]);
8498 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8499 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8504 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8506 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8507 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8508 return Operand(tmp
.regClass());
8510 return Operand(tmp
);
8513 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8515 aco_ptr
<Pseudo_instruction
> phi
;
8516 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8517 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8519 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8520 logical
|= ctx
->block
->kind
& block_kind_merge
;
8521 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8523 /* we want a sorted list of sources, since the predecessor list is also sorted */
8524 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8525 nir_foreach_phi_src(src
, instr
)
8526 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8528 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8529 unsigned num_operands
= 0;
8530 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8531 unsigned num_defined
= 0;
8532 unsigned cur_pred_idx
= 0;
8533 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8534 if (cur_pred_idx
< preds
.size()) {
8535 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8536 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8537 unsigned skipped
= 0;
8538 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8540 if (cur_pred_idx
+ skipped
< preds
.size()) {
8541 for (unsigned i
= 0; i
< skipped
; i
++)
8542 operands
[num_operands
++] = Operand(dst
.regClass());
8543 cur_pred_idx
+= skipped
;
8548 /* Handle missing predecessors at the end. This shouldn't happen with loop
8549 * headers and we can't ignore these sources for loop header phis. */
8550 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8553 Operand op
= get_phi_operand(ctx
, src
.second
);
8554 operands
[num_operands
++] = op
;
8555 num_defined
+= !op
.isUndefined();
8557 /* handle block_kind_continue_or_break at loop exit blocks */
8558 while (cur_pred_idx
++ < preds
.size())
8559 operands
[num_operands
++] = Operand(dst
.regClass());
8561 /* If the loop ends with a break, still add a linear continue edge in case
8562 * that break is divergent or continue_or_break is used. We'll either remove
8563 * this operand later in visit_loop() if it's not necessary or replace the
8564 * undef with something correct. */
8565 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8566 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8567 nir_block
*last
= nir_loop_last_block(loop
);
8568 if (last
->successors
[0] != instr
->instr
.block
)
8569 operands
[num_operands
++] = Operand(RegClass());
8572 if (num_defined
== 0) {
8573 Builder
bld(ctx
->program
, ctx
->block
);
8574 if (dst
.regClass() == s1
) {
8575 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8576 } else if (dst
.regClass() == v1
) {
8577 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8579 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8580 for (unsigned i
= 0; i
< dst
.size(); i
++)
8581 vec
->operands
[i
] = Operand(0u);
8582 vec
->definitions
[0] = Definition(dst
);
8583 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8588 /* we can use a linear phi in some cases if one src is undef */
8589 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8590 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8592 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8593 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8594 assert(invert
->kind
& block_kind_invert
);
8596 unsigned then_block
= invert
->linear_preds
[0];
8598 Block
* insert_block
= NULL
;
8599 for (unsigned i
= 0; i
< num_operands
; i
++) {
8600 Operand op
= operands
[i
];
8601 if (op
.isUndefined())
8603 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8604 phi
->operands
[0] = op
;
8607 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8608 phi
->operands
[1] = Operand(dst
.regClass());
8609 phi
->definitions
[0] = Definition(dst
);
8610 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8614 /* try to scalarize vector phis */
8615 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8616 // TODO: scalarize linear phis on divergent ifs
8617 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8618 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8619 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8620 Operand src
= operands
[i
];
8621 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8622 can_scalarize
= false;
8624 if (can_scalarize
) {
8625 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8626 assert(dst
.size() % num_components
== 0);
8627 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8629 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8630 for (unsigned k
= 0; k
< num_components
; k
++) {
8631 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8632 for (unsigned i
= 0; i
< num_operands
; i
++) {
8633 Operand src
= operands
[i
];
8634 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8636 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8637 phi
->definitions
[0] = Definition(phi_dst
);
8638 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8639 new_vec
[k
] = phi_dst
;
8640 vec
->operands
[k
] = Operand(phi_dst
);
8642 vec
->definitions
[0] = Definition(dst
);
8643 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8644 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8649 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8650 for (unsigned i
= 0; i
< num_operands
; i
++)
8651 phi
->operands
[i
] = operands
[i
];
8652 phi
->definitions
[0] = Definition(dst
);
8653 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8657 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8659 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8661 assert(dst
.type() == RegType::sgpr
);
8663 if (dst
.size() == 1) {
8664 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8666 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8667 for (unsigned i
= 0; i
< dst
.size(); i
++)
8668 vec
->operands
[i
] = Operand(0u);
8669 vec
->definitions
[0] = Definition(dst
);
8670 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8674 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8676 Builder
bld(ctx
->program
, ctx
->block
);
8677 Block
*logical_target
;
8678 append_logical_end(ctx
->block
);
8679 unsigned idx
= ctx
->block
->index
;
8681 switch (instr
->type
) {
8682 case nir_jump_break
:
8683 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8684 add_logical_edge(idx
, logical_target
);
8685 ctx
->block
->kind
|= block_kind_break
;
8687 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8688 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8689 /* uniform break - directly jump out of the loop */
8690 ctx
->block
->kind
|= block_kind_uniform
;
8691 ctx
->cf_info
.has_branch
= true;
8692 bld
.branch(aco_opcode::p_branch
);
8693 add_linear_edge(idx
, logical_target
);
8696 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8697 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8699 case nir_jump_continue
:
8700 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8701 add_logical_edge(idx
, logical_target
);
8702 ctx
->block
->kind
|= block_kind_continue
;
8704 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8705 /* for potential uniform breaks after this continue,
8706 we must ensure that they are handled correctly */
8707 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8708 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8709 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8711 /* uniform continue - directly jump to the loop header */
8712 ctx
->block
->kind
|= block_kind_uniform
;
8713 ctx
->cf_info
.has_branch
= true;
8714 bld
.branch(aco_opcode::p_branch
);
8715 add_linear_edge(idx
, logical_target
);
8720 fprintf(stderr
, "Unknown NIR jump instr: ");
8721 nir_print_instr(&instr
->instr
, stderr
);
8722 fprintf(stderr
, "\n");
8726 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
8727 ctx
->cf_info
.exec_potentially_empty_break
= true;
8728 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
8731 /* remove critical edges from linear CFG */
8732 bld
.branch(aco_opcode::p_branch
);
8733 Block
* break_block
= ctx
->program
->create_and_insert_block();
8734 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8735 break_block
->kind
|= block_kind_uniform
;
8736 add_linear_edge(idx
, break_block
);
8737 /* the loop_header pointer might be invalidated by this point */
8738 if (instr
->type
== nir_jump_continue
)
8739 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8740 add_linear_edge(break_block
->index
, logical_target
);
8741 bld
.reset(break_block
);
8742 bld
.branch(aco_opcode::p_branch
);
8744 Block
* continue_block
= ctx
->program
->create_and_insert_block();
8745 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8746 add_linear_edge(idx
, continue_block
);
8747 append_logical_start(continue_block
);
8748 ctx
->block
= continue_block
;
8752 void visit_block(isel_context
*ctx
, nir_block
*block
)
8754 nir_foreach_instr(instr
, block
) {
8755 switch (instr
->type
) {
8756 case nir_instr_type_alu
:
8757 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
8759 case nir_instr_type_load_const
:
8760 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
8762 case nir_instr_type_intrinsic
:
8763 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
8765 case nir_instr_type_tex
:
8766 visit_tex(ctx
, nir_instr_as_tex(instr
));
8768 case nir_instr_type_phi
:
8769 visit_phi(ctx
, nir_instr_as_phi(instr
));
8771 case nir_instr_type_ssa_undef
:
8772 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
8774 case nir_instr_type_deref
:
8776 case nir_instr_type_jump
:
8777 visit_jump(ctx
, nir_instr_as_jump(instr
));
8780 fprintf(stderr
, "Unknown NIR instr type: ");
8781 nir_print_instr(instr
, stderr
);
8782 fprintf(stderr
, "\n");
8787 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8788 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
8793 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
8794 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
8796 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
8797 RegClass rc
= vals
[0].regClass();
8799 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
8801 unsigned next_pred
= 1;
8803 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
8804 Block
& block
= ctx
->program
->blocks
[idx
];
8805 if (block
.loop_nest_depth
!= loop_nest_depth
) {
8806 vals
[idx
- first
] = vals
[idx
- 1 - first
];
8810 if (block
.kind
& block_kind_continue
) {
8811 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
8816 bool all_same
= true;
8817 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
8818 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
8822 val
= vals
[block
.linear_preds
[0] - first
];
8824 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
8825 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
8826 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
8827 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
8828 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
8829 phi
->definitions
[0] = Definition(val
.getTemp());
8830 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
8832 vals
[idx
- first
] = val
;
8835 return vals
[last
- first
];
8838 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
8840 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8841 append_logical_end(ctx
->block
);
8842 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
8843 Builder
bld(ctx
->program
, ctx
->block
);
8844 bld
.branch(aco_opcode::p_branch
);
8845 unsigned loop_preheader_idx
= ctx
->block
->index
;
8847 Block loop_exit
= Block();
8848 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8849 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
8851 Block
* loop_header
= ctx
->program
->create_and_insert_block();
8852 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
8853 loop_header
->kind
|= block_kind_loop_header
;
8854 add_edge(loop_preheader_idx
, loop_header
);
8855 ctx
->block
= loop_header
;
8857 /* emit loop body */
8858 unsigned loop_header_idx
= loop_header
->index
;
8859 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
8860 append_logical_start(ctx
->block
);
8861 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
8863 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8864 if (!ctx
->cf_info
.has_branch
) {
8865 append_logical_end(ctx
->block
);
8866 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
8867 /* Discards can result in code running with an empty exec mask.
8868 * This would result in divergent breaks not ever being taken. As a
8869 * workaround, break the loop when the loop mask is empty instead of
8870 * always continuing. */
8871 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
8872 unsigned block_idx
= ctx
->block
->index
;
8874 /* create helper blocks to avoid critical edges */
8875 Block
*break_block
= ctx
->program
->create_and_insert_block();
8876 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8877 break_block
->kind
= block_kind_uniform
;
8878 bld
.reset(break_block
);
8879 bld
.branch(aco_opcode::p_branch
);
8880 add_linear_edge(block_idx
, break_block
);
8881 add_linear_edge(break_block
->index
, &loop_exit
);
8883 Block
*continue_block
= ctx
->program
->create_and_insert_block();
8884 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8885 continue_block
->kind
= block_kind_uniform
;
8886 bld
.reset(continue_block
);
8887 bld
.branch(aco_opcode::p_branch
);
8888 add_linear_edge(block_idx
, continue_block
);
8889 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8891 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8892 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
8893 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
8895 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
8896 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8897 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8899 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8902 bld
.reset(ctx
->block
);
8903 bld
.branch(aco_opcode::p_branch
);
8906 /* Fixup phis in loop header from unreachable blocks.
8907 * has_branch/has_divergent_branch also indicates if the loop ends with a
8908 * break/continue instruction, but we don't emit those if unreachable=true */
8910 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
8911 bool linear
= ctx
->cf_info
.has_branch
;
8912 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
8913 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
8914 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
8915 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
8916 /* the last operand should be the one that needs to be removed */
8917 instr
->operands
.pop_back();
8918 } else if (!is_phi(instr
)) {
8924 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
8925 * and the previous one shouldn't both happen at once because a break in the
8926 * merge block would get CSE'd */
8927 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
8928 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
8929 Operand vals
[num_vals
];
8930 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
8931 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
8932 if (ctx
->cf_info
.has_branch
)
8933 instr
->operands
.pop_back();
8935 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
8936 } else if (!is_phi(instr
)) {
8942 ctx
->cf_info
.has_branch
= false;
8944 // TODO: if the loop has not a single exit, we must add one °°
8945 /* emit loop successor block */
8946 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
8947 append_logical_start(ctx
->block
);
8950 // TODO: check if it is beneficial to not branch on continues
8951 /* trim linear phis in loop header */
8952 for (auto&& instr
: loop_entry
->instructions
) {
8953 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
8954 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
8955 new_phi
->definitions
[0] = instr
->definitions
[0];
8956 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
8957 new_phi
->operands
[i
] = instr
->operands
[i
];
8958 /* check that the remaining operands are all the same */
8959 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
8960 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
8961 instr
.swap(new_phi
);
8962 } else if (instr
->opcode
== aco_opcode::p_phi
) {
8971 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
8975 append_logical_end(ctx
->block
);
8976 ctx
->block
->kind
|= block_kind_branch
;
8978 /* branch to linear then block */
8979 assert(cond
.regClass() == ctx
->program
->lane_mask
);
8980 aco_ptr
<Pseudo_branch_instruction
> branch
;
8981 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
8982 branch
->operands
[0] = Operand(cond
);
8983 ctx
->block
->instructions
.push_back(std::move(branch
));
8985 ic
->BB_if_idx
= ctx
->block
->index
;
8986 ic
->BB_invert
= Block();
8987 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8988 /* Invert blocks are intentionally not marked as top level because they
8989 * are not part of the logical cfg. */
8990 ic
->BB_invert
.kind
|= block_kind_invert
;
8991 ic
->BB_endif
= Block();
8992 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8993 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
8995 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
8996 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
8997 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
8998 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
8999 ctx
->cf_info
.parent_if
.is_divergent
= true;
9001 /* divergent branches use cbranch_execz */
9002 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9003 ctx
->cf_info
.exec_potentially_empty_break
= false;
9004 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9006 /** emit logical then block */
9007 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9008 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9009 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9010 ctx
->block
= BB_then_logical
;
9011 append_logical_start(BB_then_logical
);
9014 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9016 Block
*BB_then_logical
= ctx
->block
;
9017 append_logical_end(BB_then_logical
);
9018 /* branch from logical then block to invert block */
9019 aco_ptr
<Pseudo_branch_instruction
> branch
;
9020 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9021 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9022 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9023 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9024 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9025 BB_then_logical
->kind
|= block_kind_uniform
;
9026 assert(!ctx
->cf_info
.has_branch
);
9027 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9028 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9030 /** emit linear then block */
9031 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9032 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9033 BB_then_linear
->kind
|= block_kind_uniform
;
9034 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9035 /* branch from linear then block to invert block */
9036 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9037 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9038 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9040 /** emit invert merge block */
9041 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9042 ic
->invert_idx
= ctx
->block
->index
;
9044 /* branch to linear else block (skip else) */
9045 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9046 branch
->operands
[0] = Operand(ic
->cond
);
9047 ctx
->block
->instructions
.push_back(std::move(branch
));
9049 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9050 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9051 ic
->exec_potentially_empty_break_depth_old
=
9052 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9053 /* divergent branches use cbranch_execz */
9054 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9055 ctx
->cf_info
.exec_potentially_empty_break
= false;
9056 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9058 /** emit logical else block */
9059 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9060 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9061 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9062 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9063 ctx
->block
= BB_else_logical
;
9064 append_logical_start(BB_else_logical
);
9067 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9069 Block
*BB_else_logical
= ctx
->block
;
9070 append_logical_end(BB_else_logical
);
9072 /* branch from logical else block to endif block */
9073 aco_ptr
<Pseudo_branch_instruction
> branch
;
9074 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9075 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9076 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9077 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9078 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9079 BB_else_logical
->kind
|= block_kind_uniform
;
9081 assert(!ctx
->cf_info
.has_branch
);
9082 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9085 /** emit linear else block */
9086 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9087 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9088 BB_else_linear
->kind
|= block_kind_uniform
;
9089 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9091 /* branch from linear else block to endif block */
9092 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9093 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9094 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9097 /** emit endif merge block */
9098 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9099 append_logical_start(ctx
->block
);
9102 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9103 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9104 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9105 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9106 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9107 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9108 !ctx
->cf_info
.parent_if
.is_divergent
) {
9109 ctx
->cf_info
.exec_potentially_empty_break
= false;
9110 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9112 /* uniform control flow never has an empty exec-mask */
9113 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9114 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9115 ctx
->cf_info
.exec_potentially_empty_break
= false;
9116 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9120 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9122 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9123 Builder
bld(ctx
->program
, ctx
->block
);
9124 aco_ptr
<Pseudo_branch_instruction
> branch
;
9126 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9128 * Uniform conditionals are represented in the following way*) :
9130 * The linear and logical CFG:
9133 * BB_THEN (logical) BB_ELSE (logical)
9137 * *) Exceptions may be due to break and continue statements within loops
9138 * If a break/continue happens within uniform control flow, it branches
9139 * to the loop exit/entry block. Otherwise, it branches to the next
9142 append_logical_end(ctx
->block
);
9143 ctx
->block
->kind
|= block_kind_uniform
;
9146 assert(cond
.regClass() == bld
.lm
);
9147 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9148 cond
= bool_to_scalar_condition(ctx
, cond
);
9150 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9151 branch
->operands
[0] = Operand(cond
);
9152 branch
->operands
[0].setFixed(scc
);
9153 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9155 unsigned BB_if_idx
= ctx
->block
->index
;
9156 Block BB_endif
= Block();
9157 BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9158 BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9160 /** emit then block */
9161 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9162 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9163 add_edge(BB_if_idx
, BB_then
);
9164 append_logical_start(BB_then
);
9165 ctx
->block
= BB_then
;
9166 visit_cf_list(ctx
, &if_stmt
->then_list
);
9167 BB_then
= ctx
->block
;
9168 bool then_branch
= ctx
->cf_info
.has_branch
;
9169 bool then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9172 append_logical_end(BB_then
);
9173 /* branch from then block to endif block */
9174 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9175 BB_then
->instructions
.emplace_back(std::move(branch
));
9176 add_linear_edge(BB_then
->index
, &BB_endif
);
9177 if (!then_branch_divergent
)
9178 add_logical_edge(BB_then
->index
, &BB_endif
);
9179 BB_then
->kind
|= block_kind_uniform
;
9182 ctx
->cf_info
.has_branch
= false;
9183 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9185 /** emit else block */
9186 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9187 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9188 add_edge(BB_if_idx
, BB_else
);
9189 append_logical_start(BB_else
);
9190 ctx
->block
= BB_else
;
9191 visit_cf_list(ctx
, &if_stmt
->else_list
);
9192 BB_else
= ctx
->block
;
9194 if (!ctx
->cf_info
.has_branch
) {
9195 append_logical_end(BB_else
);
9196 /* branch from then block to endif block */
9197 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9198 BB_else
->instructions
.emplace_back(std::move(branch
));
9199 add_linear_edge(BB_else
->index
, &BB_endif
);
9200 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9201 add_logical_edge(BB_else
->index
, &BB_endif
);
9202 BB_else
->kind
|= block_kind_uniform
;
9205 ctx
->cf_info
.has_branch
&= then_branch
;
9206 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= then_branch_divergent
;
9208 /** emit endif merge block */
9209 if (!ctx
->cf_info
.has_branch
) {
9210 ctx
->block
= ctx
->program
->insert_block(std::move(BB_endif
));
9211 append_logical_start(ctx
->block
);
9213 return !ctx
->cf_info
.has_branch
;
9214 } else { /* non-uniform condition */
9216 * To maintain a logical and linear CFG without critical edges,
9217 * non-uniform conditionals are represented in the following way*) :
9222 * BB_THEN (logical) BB_THEN (linear)
9224 * BB_INVERT (linear)
9226 * BB_ELSE (logical) BB_ELSE (linear)
9233 * BB_THEN (logical) BB_ELSE (logical)
9237 * *) Exceptions may be due to break and continue statements within loops
9242 begin_divergent_if_then(ctx
, &ic
, cond
);
9243 visit_cf_list(ctx
, &if_stmt
->then_list
);
9245 begin_divergent_if_else(ctx
, &ic
);
9246 visit_cf_list(ctx
, &if_stmt
->else_list
);
9248 end_divergent_if(ctx
, &ic
);
9254 static bool visit_cf_list(isel_context
*ctx
,
9255 struct exec_list
*list
)
9257 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9258 switch (node
->type
) {
9259 case nir_cf_node_block
:
9260 visit_block(ctx
, nir_cf_node_as_block(node
));
9262 case nir_cf_node_if
:
9263 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9266 case nir_cf_node_loop
:
9267 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9270 unreachable("unimplemented cf list type");
9276 static void create_null_export(isel_context
*ctx
)
9278 /* Some shader stages always need to have exports.
9279 * So when there is none, we need to add a null export.
9282 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9283 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9284 Builder
bld(ctx
->program
, ctx
->block
);
9285 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9286 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9289 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9291 assert(ctx
->stage
== vertex_vs
||
9292 ctx
->stage
== tess_eval_vs
||
9293 ctx
->stage
== gs_copy_vs
);
9295 int offset
= ctx
->stage
== tess_eval_vs
9296 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9297 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9298 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9299 if (!is_pos
&& !mask
)
9301 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9303 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9304 exp
->enabled_mask
= mask
;
9305 for (unsigned i
= 0; i
< 4; ++i
) {
9306 if (mask
& (1 << i
))
9307 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9309 exp
->operands
[i
] = Operand(v1
);
9311 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9312 * Setting valid_mask=1 prevents it and has no other effect.
9314 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9316 exp
->compressed
= false;
9318 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9320 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9321 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9326 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9328 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9329 exp
->enabled_mask
= 0;
9330 for (unsigned i
= 0; i
< 4; ++i
)
9331 exp
->operands
[i
] = Operand(v1
);
9332 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9333 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9334 exp
->enabled_mask
|= 0x1;
9336 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9337 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9338 exp
->enabled_mask
|= 0x4;
9340 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9341 if (ctx
->options
->chip_class
< GFX9
) {
9342 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9343 exp
->enabled_mask
|= 0x8;
9345 Builder
bld(ctx
->program
, ctx
->block
);
9347 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9348 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9349 if (exp
->operands
[2].isTemp())
9350 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9352 exp
->operands
[2] = Operand(out
);
9353 exp
->enabled_mask
|= 0x4;
9356 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9358 exp
->compressed
= false;
9359 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9360 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9363 static void create_vs_exports(isel_context
*ctx
)
9365 assert(ctx
->stage
== vertex_vs
||
9366 ctx
->stage
== tess_eval_vs
||
9367 ctx
->stage
== gs_copy_vs
);
9369 radv_vs_output_info
*outinfo
= ctx
->stage
== tess_eval_vs
9370 ? &ctx
->program
->info
->tes
.outinfo
9371 : &ctx
->program
->info
->vs
.outinfo
;
9373 if (outinfo
->export_prim_id
) {
9374 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9375 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9378 if (ctx
->options
->key
.has_multiview_view_index
) {
9379 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9380 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9383 /* the order these position exports are created is important */
9385 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9386 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9387 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9388 exported_pos
= true;
9390 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9391 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9392 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9393 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9395 if (ctx
->export_clip_dists
) {
9396 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9397 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9398 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9399 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9402 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9403 if (i
< VARYING_SLOT_VAR0
&& i
!= VARYING_SLOT_LAYER
&&
9404 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9407 export_vs_varying(ctx
, i
, false, NULL
);
9411 create_null_export(ctx
);
9414 static bool export_fs_mrt_z(isel_context
*ctx
)
9416 Builder
bld(ctx
->program
, ctx
->block
);
9417 unsigned enabled_channels
= 0;
9421 for (unsigned i
= 0; i
< 4; ++i
) {
9422 values
[i
] = Operand(v1
);
9425 /* Both stencil and sample mask only need 16-bits. */
9426 if (!ctx
->program
->info
->ps
.writes_z
&&
9427 (ctx
->program
->info
->ps
.writes_stencil
||
9428 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9429 compr
= true; /* COMPR flag */
9431 if (ctx
->program
->info
->ps
.writes_stencil
) {
9432 /* Stencil should be in X[23:16]. */
9433 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9434 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9435 enabled_channels
|= 0x3;
9438 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9439 /* SampleMask should be in Y[15:0]. */
9440 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9441 enabled_channels
|= 0xc;
9444 if (ctx
->program
->info
->ps
.writes_z
) {
9445 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9446 enabled_channels
|= 0x1;
9449 if (ctx
->program
->info
->ps
.writes_stencil
) {
9450 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9451 enabled_channels
|= 0x2;
9454 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9455 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9456 enabled_channels
|= 0x4;
9460 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9461 * writemask component.
9463 if (ctx
->options
->chip_class
== GFX6
&&
9464 ctx
->options
->family
!= CHIP_OLAND
&&
9465 ctx
->options
->family
!= CHIP_HAINAN
) {
9466 enabled_channels
|= 0x1;
9469 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9470 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9475 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9477 Builder
bld(ctx
->program
, ctx
->block
);
9478 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9481 for (unsigned i
= 0; i
< 4; ++i
) {
9482 if (write_mask
& (1 << i
)) {
9483 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9485 values
[i
] = Operand(v1
);
9489 unsigned target
, col_format
;
9490 unsigned enabled_channels
= 0;
9491 aco_opcode compr_op
= (aco_opcode
)0;
9493 slot
-= FRAG_RESULT_DATA0
;
9494 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9495 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9497 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9498 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9502 case V_028714_SPI_SHADER_ZERO
:
9503 enabled_channels
= 0; /* writemask */
9504 target
= V_008DFC_SQ_EXP_NULL
;
9507 case V_028714_SPI_SHADER_32_R
:
9508 enabled_channels
= 1;
9511 case V_028714_SPI_SHADER_32_GR
:
9512 enabled_channels
= 0x3;
9515 case V_028714_SPI_SHADER_32_AR
:
9516 if (ctx
->options
->chip_class
>= GFX10
) {
9517 /* Special case: on GFX10, the outputs are different for 32_AR */
9518 enabled_channels
= 0x3;
9519 values
[1] = values
[3];
9520 values
[3] = Operand(v1
);
9522 enabled_channels
= 0x9;
9526 case V_028714_SPI_SHADER_FP16_ABGR
:
9527 enabled_channels
= 0x5;
9528 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9531 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9532 enabled_channels
= 0x5;
9533 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9536 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9537 enabled_channels
= 0x5;
9538 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9541 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9542 enabled_channels
= 0x5;
9543 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9544 if (is_int8
|| is_int10
) {
9546 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9547 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9549 for (unsigned i
= 0; i
< 4; i
++) {
9550 if ((write_mask
>> i
) & 1) {
9551 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9552 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9560 case V_028714_SPI_SHADER_SINT16_ABGR
:
9561 enabled_channels
= 0x5;
9562 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9563 if (is_int8
|| is_int10
) {
9565 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9566 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9567 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9568 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9570 for (unsigned i
= 0; i
< 4; i
++) {
9571 if ((write_mask
>> i
) & 1) {
9572 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9573 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9575 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9576 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9583 case V_028714_SPI_SHADER_32_ABGR
:
9584 enabled_channels
= 0xF;
9591 if (target
== V_008DFC_SQ_EXP_NULL
)
9594 if ((bool) compr_op
) {
9595 for (int i
= 0; i
< 2; i
++) {
9596 /* check if at least one of the values to be compressed is enabled */
9597 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9599 enabled_channels
|= enabled
<< (i
*2);
9600 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9601 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9602 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9604 values
[i
] = Operand(v1
);
9607 values
[2] = Operand(v1
);
9608 values
[3] = Operand(v1
);
9610 for (int i
= 0; i
< 4; i
++)
9611 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9614 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9615 enabled_channels
, target
, (bool) compr_op
);
9619 static void create_fs_exports(isel_context
*ctx
)
9621 bool exported
= false;
9623 /* Export depth, stencil and sample mask. */
9624 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9625 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9626 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9627 exported
|= export_fs_mrt_z(ctx
);
9629 /* Export all color render targets. */
9630 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9631 if (ctx
->outputs
.mask
[i
])
9632 exported
|= export_fs_mrt_color(ctx
, i
);
9635 create_null_export(ctx
);
9638 static void write_tcs_tess_factors(isel_context
*ctx
)
9640 unsigned outer_comps
;
9641 unsigned inner_comps
;
9643 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9660 Builder
bld(ctx
->program
, ctx
->block
);
9662 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9663 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9664 bld
.sopp(aco_opcode::s_barrier
);
9666 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
9667 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
9669 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
9670 if_context ic_invocation_id_is_zero
;
9671 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
9672 bld
.reset(ctx
->block
);
9674 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
9676 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
9677 unsigned stride
= inner_comps
+ outer_comps
;
9678 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
9682 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
9684 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
9686 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9687 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
9688 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
9690 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9691 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
9693 for (unsigned i
= 0; i
< outer_comps
; ++i
)
9694 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
9695 for (unsigned i
= 0; i
< inner_comps
; ++i
)
9696 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
9699 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
9700 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
9701 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
9702 unsigned tf_const_offset
= 0;
9704 if (ctx
->program
->chip_class
<= GFX8
) {
9705 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
9706 if_context ic_rel_patch_id_is_zero
;
9707 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
9708 bld
.reset(ctx
->block
);
9710 /* Store the dynamic HS control word. */
9711 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
9712 bld
.mubuf(aco_opcode::buffer_store_dword
,
9713 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
9714 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9715 /* disable_wqm */ false, /* glc */ true);
9716 tf_const_offset
+= 4;
9718 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
9719 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
9720 bld
.reset(ctx
->block
);
9723 assert(stride
== 2 || stride
== 4 || stride
== 6);
9724 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
9725 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
9727 /* Store to offchip for TES to read - only if TES reads them */
9728 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
9729 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
9730 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
9732 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
9733 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
9735 if (likely(inner_comps
)) {
9736 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
9737 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
9741 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
9742 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
9745 static void emit_stream_output(isel_context
*ctx
,
9746 Temp
const *so_buffers
,
9747 Temp
const *so_write_offset
,
9748 const struct radv_stream_output
*output
)
9750 unsigned num_comps
= util_bitcount(output
->component_mask
);
9751 unsigned writemask
= (1 << num_comps
) - 1;
9752 unsigned loc
= output
->location
;
9753 unsigned buf
= output
->buffer
;
9755 assert(num_comps
&& num_comps
<= 4);
9756 if (!num_comps
|| num_comps
> 4)
9759 unsigned start
= ffs(output
->component_mask
) - 1;
9762 bool all_undef
= true;
9763 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
9764 for (unsigned i
= 0; i
< num_comps
; i
++) {
9765 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
9766 all_undef
= all_undef
&& !out
[i
].id();
9773 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
9774 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
9775 /* GFX6 doesn't support storing vec3, split it. */
9776 writemask
|= 1u << (start
+ 2);
9780 unsigned offset
= output
->offset
+ start
* 4;
9782 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
9783 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
9784 for (int i
= 0; i
< count
; ++i
)
9785 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
9786 vec
->definitions
[0] = Definition(write_data
);
9787 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9792 opcode
= aco_opcode::buffer_store_dword
;
9795 opcode
= aco_opcode::buffer_store_dwordx2
;
9798 opcode
= aco_opcode::buffer_store_dwordx3
;
9801 opcode
= aco_opcode::buffer_store_dwordx4
;
9804 unreachable("Unsupported dword count.");
9807 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
9808 store
->operands
[0] = Operand(so_buffers
[buf
]);
9809 store
->operands
[1] = Operand(so_write_offset
[buf
]);
9810 store
->operands
[2] = Operand((uint32_t) 0);
9811 store
->operands
[3] = Operand(write_data
);
9812 if (offset
> 4095) {
9813 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9814 Builder
bld(ctx
->program
, ctx
->block
);
9815 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
9817 store
->offset
= offset
;
9819 store
->offen
= true;
9823 store
->can_reorder
= true;
9824 ctx
->block
->instructions
.emplace_back(std::move(store
));
9828 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
9830 Builder
bld(ctx
->program
, ctx
->block
);
9833 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
9834 for (unsigned i
= 0; i
< 4; i
++) {
9835 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
9839 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
9840 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
9843 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
9844 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
9846 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
9848 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
9851 begin_divergent_if_then(ctx
, &ic
, can_emit
);
9853 bld
.reset(ctx
->block
);
9855 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
9857 Temp so_write_offset
[4];
9859 for (unsigned i
= 0; i
< 4; i
++) {
9860 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
9865 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
9866 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
9867 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
9868 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
9870 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
9872 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
9873 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
9874 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
9875 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
9879 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
9880 struct radv_stream_output
*output
=
9881 &ctx
->program
->info
->so
.outputs
[i
];
9882 if (stream
!= output
->stream
)
9885 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
9888 begin_divergent_if_else(ctx
, &ic
);
9889 end_divergent_if(ctx
, &ic
);
9892 } /* end namespace */
9894 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
9896 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
9897 Builder
bld(ctx
->program
, ctx
->block
);
9898 constexpr unsigned hs_idx
= 1u;
9899 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
9900 get_arg(ctx
, ctx
->args
->merged_wave_info
),
9901 Operand((8u << 16) | (hs_idx
* 8u)));
9902 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
9904 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9906 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9907 get_arg(ctx
, ctx
->args
->rel_auto_id
),
9908 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
9909 ls_has_nonzero_hs_threads
);
9910 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9911 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
9912 get_arg(ctx
, ctx
->args
->rel_auto_id
),
9913 ls_has_nonzero_hs_threads
);
9914 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9915 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
9916 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
9917 ls_has_nonzero_hs_threads
);
9919 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
9920 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
9921 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
9924 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
9926 /* Split all arguments except for the first (ring_offsets) and the last
9927 * (exec) so that the dead channels don't stay live throughout the program.
9929 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
9930 if (startpgm
->definitions
[i
].regClass().size() > 1) {
9931 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
9932 startpgm
->definitions
[i
].regClass().size());
9937 void handle_bc_optimize(isel_context
*ctx
)
9939 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9940 Builder
bld(ctx
->program
, ctx
->block
);
9941 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
9942 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
9943 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
9944 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
9945 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
9946 if (uses_center
&& uses_centroid
) {
9947 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
9948 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
9950 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
9952 for (unsigned i
= 0; i
< 2; i
++) {
9953 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
9954 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
9955 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9956 persp_centroid
, persp_center
, sel
);
9958 ctx
->persp_centroid
= bld
.tmp(v2
);
9959 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
9960 Operand(new_coord
[0]), Operand(new_coord
[1]));
9961 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
9964 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
9966 for (unsigned i
= 0; i
< 2; i
++) {
9967 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
9968 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
9969 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9970 linear_centroid
, linear_center
, sel
);
9972 ctx
->linear_centroid
= bld
.tmp(v2
);
9973 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
9974 Operand(new_coord
[0]), Operand(new_coord
[1]));
9975 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
9980 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
9982 Program
*program
= ctx
->program
;
9984 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
9986 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
9987 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
9988 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
9989 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
9990 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
9992 program
->next_fp_mode
.must_flush_denorms32
=
9993 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
9994 program
->next_fp_mode
.must_flush_denorms16_64
=
9995 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
9996 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
9998 program
->next_fp_mode
.care_about_round32
=
9999 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10001 program
->next_fp_mode
.care_about_round16_64
=
10002 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10003 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10005 /* default to preserving fp16 and fp64 denorms, since it's free */
10006 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10007 program
->next_fp_mode
.denorm16_64
= 0;
10009 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10011 /* preserving fp32 denorms is expensive, so only do it if asked */
10012 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10013 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10015 program
->next_fp_mode
.denorm32
= 0;
10017 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10018 program
->next_fp_mode
.round32
= fp_round_tz
;
10020 program
->next_fp_mode
.round32
= fp_round_ne
;
10022 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10023 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10025 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10027 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10030 void cleanup_cfg(Program
*program
)
10032 /* create linear_succs/logical_succs */
10033 for (Block
& BB
: program
->blocks
) {
10034 for (unsigned idx
: BB
.linear_preds
)
10035 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10036 for (unsigned idx
: BB
.logical_preds
)
10037 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10041 void select_program(Program
*program
,
10042 unsigned shader_count
,
10043 struct nir_shader
*const *shaders
,
10044 ac_shader_config
* config
,
10045 struct radv_shader_args
*args
)
10047 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10048 if_context ic_merged_wave_info
;
10050 for (unsigned i
= 0; i
< shader_count
; i
++) {
10051 nir_shader
*nir
= shaders
[i
];
10052 init_context(&ctx
, nir
);
10054 setup_fp_mode(&ctx
, nir
);
10057 /* needs to be after init_context() for FS */
10058 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10059 append_logical_start(ctx
.block
);
10061 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10062 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10064 split_arguments(&ctx
, startpgm
);
10067 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10068 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10069 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10070 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10071 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10072 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10073 ctx
.stage
== tess_eval_geometry_gs
));
10075 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : (shader_count
>= 2 && !empty_shader
);
10076 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10077 if (check_merged_wave_info
) {
10078 Builder
bld(ctx
.program
, ctx
.block
);
10080 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10081 Temp count
= i
== 0 ? get_arg(&ctx
, args
->merged_wave_info
)
10082 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10083 get_arg(&ctx
, args
->merged_wave_info
), Operand(i
* 8u));
10085 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10088 if (ctx
.program
->wave_size
== 64) {
10089 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10090 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10091 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10093 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10094 cond
= emit_extract_vector(&ctx
, mask
, 0, bld
.lm
);
10097 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10101 Builder
bld(ctx
.program
, ctx
.block
);
10103 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10104 bld
.sopp(aco_opcode::s_barrier
);
10106 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10107 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10109 } else if (ctx
.stage
== geometry_gs
)
10110 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10112 if (ctx
.stage
== fragment_fs
)
10113 handle_bc_optimize(&ctx
);
10115 visit_cf_list(&ctx
, &func
->body
);
10117 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
== vertex_vs
|| ctx
.stage
== tess_eval_vs
))
10118 emit_streamout(&ctx
, 0);
10120 if (ctx
.stage
== vertex_vs
|| ctx
.stage
== tess_eval_vs
) {
10121 create_vs_exports(&ctx
);
10122 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10123 Builder
bld(ctx
.program
, ctx
.block
);
10124 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10125 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10126 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10127 write_tcs_tess_factors(&ctx
);
10130 if (ctx
.stage
== fragment_fs
)
10131 create_fs_exports(&ctx
);
10133 if (endif_merged_wave_info
) {
10134 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10135 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10138 ralloc_free(ctx
.divergent_vals
);
10140 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10141 /* Outputs of the previous stage are inputs to the next stage */
10142 ctx
.inputs
= ctx
.outputs
;
10143 ctx
.outputs
= shader_io_state();
10147 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10149 append_logical_end(ctx
.block
);
10150 ctx
.block
->kind
|= block_kind_uniform
| block_kind_export_end
;
10151 Builder
bld(ctx
.program
, ctx
.block
);
10152 if (ctx
.program
->wb_smem_l1_on_end
)
10153 bld
.smem(aco_opcode::s_dcache_wb
, false);
10154 bld
.sopp(aco_opcode::s_endpgm
);
10156 cleanup_cfg(program
);
10159 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10160 ac_shader_config
* config
,
10161 struct radv_shader_args
*args
)
10163 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10165 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10166 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10167 program
->next_fp_mode
.must_flush_denorms32
= false;
10168 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10169 program
->next_fp_mode
.care_about_round32
= false;
10170 program
->next_fp_mode
.care_about_round16_64
= false;
10171 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10172 program
->next_fp_mode
.denorm32
= 0;
10173 program
->next_fp_mode
.round32
= fp_round_ne
;
10174 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10175 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10177 add_startpgm(&ctx
);
10178 append_logical_start(ctx
.block
);
10180 Builder
bld(ctx
.program
, ctx
.block
);
10182 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10184 Operand
stream_id(0u);
10185 if (args
->shader_info
->so
.num_outputs
)
10186 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10187 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10189 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10191 std::stack
<Block
> endif_blocks
;
10193 for (unsigned stream
= 0; stream
< 4; stream
++) {
10194 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10197 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10198 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10201 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10203 unsigned BB_if_idx
= ctx
.block
->index
;
10204 Block BB_endif
= Block();
10205 if (!stream_id
.isConstant()) {
10207 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10208 append_logical_end(ctx
.block
);
10209 ctx
.block
->kind
|= block_kind_uniform
;
10210 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10212 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10214 ctx
.block
= ctx
.program
->create_and_insert_block();
10215 add_edge(BB_if_idx
, ctx
.block
);
10216 bld
.reset(ctx
.block
);
10217 append_logical_start(ctx
.block
);
10220 unsigned offset
= 0;
10221 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10222 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10225 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10226 unsigned length
= util_last_bit(output_usage_mask
);
10227 for (unsigned j
= 0; j
< length
; ++j
) {
10228 if (!(output_usage_mask
& (1 << j
)))
10231 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10232 Temp voffset
= vtx_offset
;
10233 if (const_offset
>= 4096u) {
10234 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10235 const_offset
%= 4096u;
10238 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10239 mubuf
->definitions
[0] = bld
.def(v1
);
10240 mubuf
->operands
[0] = Operand(gsvs_ring
);
10241 mubuf
->operands
[1] = Operand(voffset
);
10242 mubuf
->operands
[2] = Operand(0u);
10243 mubuf
->offen
= true;
10244 mubuf
->offset
= const_offset
;
10247 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10248 mubuf
->barrier
= barrier_none
;
10249 mubuf
->can_reorder
= true;
10251 ctx
.outputs
.mask
[i
] |= 1 << j
;
10252 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10254 bld
.insert(std::move(mubuf
));
10260 if (args
->shader_info
->so
.num_outputs
) {
10261 emit_streamout(&ctx
, stream
);
10262 bld
.reset(ctx
.block
);
10266 create_vs_exports(&ctx
);
10267 ctx
.block
->kind
|= block_kind_export_end
;
10270 if (!stream_id
.isConstant()) {
10271 append_logical_end(ctx
.block
);
10273 /* branch from then block to endif block */
10274 bld
.branch(aco_opcode::p_branch
);
10275 add_edge(ctx
.block
->index
, &BB_endif
);
10276 ctx
.block
->kind
|= block_kind_uniform
;
10278 /* emit else block */
10279 ctx
.block
= ctx
.program
->create_and_insert_block();
10280 add_edge(BB_if_idx
, ctx
.block
);
10281 bld
.reset(ctx
.block
);
10282 append_logical_start(ctx
.block
);
10284 endif_blocks
.push(std::move(BB_endif
));
10288 while (!endif_blocks
.empty()) {
10289 Block BB_endif
= std::move(endif_blocks
.top());
10290 endif_blocks
.pop();
10292 Block
*BB_else
= ctx
.block
;
10294 append_logical_end(BB_else
);
10295 /* branch from else block to endif block */
10296 bld
.branch(aco_opcode::p_branch
);
10297 add_edge(BB_else
->index
, &BB_endif
);
10298 BB_else
->kind
|= block_kind_uniform
;
10300 /** emit endif merge block */
10301 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10302 bld
.reset(ctx
.block
);
10303 append_logical_start(ctx
.block
);
10306 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10308 append_logical_end(ctx
.block
);
10309 ctx
.block
->kind
|= block_kind_uniform
;
10310 bld
.sopp(aco_opcode::s_endpgm
);
10312 cleanup_cfg(program
);