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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
308 if (num_components
> vec_src
.size()) {
309 if (vec_src
.type() == RegType::sgpr
) {
310 /* should still help get_alu_src() */
311 emit_split_vector(ctx
, vec_src
, vec_src
.size());
314 /* sub-dword split */
315 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
317 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
319 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
320 split
->operands
[0] = Operand(vec_src
);
321 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
322 for (unsigned i
= 0; i
< num_components
; i
++) {
323 elems
[i
] = {ctx
->program
->allocateId(), rc
};
324 split
->definitions
[i
] = Definition(elems
[i
]);
326 ctx
->block
->instructions
.emplace_back(std::move(split
));
327 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
330 /* This vector expansion uses a mask to determine which elements in the new vector
331 * come from the original vector. The other elements are undefined. */
332 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
334 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
339 Builder
bld(ctx
->program
, ctx
->block
);
340 if (num_components
== 1) {
341 if (dst
.type() == RegType::sgpr
)
342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
344 bld
.copy(Definition(dst
), vec_src
);
348 unsigned component_size
= dst
.size() / num_components
;
349 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
351 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
352 vec
->definitions
[0] = Definition(dst
);
354 for (unsigned i
= 0; i
< num_components
; i
++) {
355 if (mask
& (1 << i
)) {
356 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
357 if (dst
.type() == RegType::sgpr
)
358 src
= bld
.as_uniform(src
);
359 vec
->operands
[i
] = Operand(src
);
361 vec
->operands
[i
] = Operand(0u);
363 elems
[i
] = vec
->operands
[i
].getTemp();
365 ctx
->block
->instructions
.emplace_back(std::move(vec
));
366 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
369 /* adjust misaligned small bit size loads */
370 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
372 Builder
bld(ctx
->program
, ctx
->block
);
374 Temp select
= Temp();
375 if (offset
.isConstant()) {
376 assert(offset
.constantValue() && offset
.constantValue() < 4);
377 shift
= Operand(offset
.constantValue() * 8);
379 /* bit_offset = 8 * (offset & 0x3) */
380 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
381 select
= bld
.tmp(s1
);
382 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
385 if (vec
.size() == 1) {
386 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
387 } else if (vec
.size() == 2) {
388 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
389 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
391 emit_split_vector(ctx
, dst
, 2);
393 emit_extract_vector(ctx
, tmp
, 0, dst
);
394 } else if (vec
.size() == 4) {
395 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
396 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
397 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
398 if (select
!= Temp())
399 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
400 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
401 Temp mid
= bld
.tmp(s1
);
402 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
403 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
404 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
405 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
406 emit_split_vector(ctx
, dst
, 2);
410 /* this function trims subdword vectors:
411 * if dst is vgpr - split the src and create a shrunk version according to the mask.
412 * if dst is sgpr - split the src, but move the original to sgpr. */
413 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
415 assert(vec_src
.type() == RegType::vgpr
);
416 emit_split_vector(ctx
, vec_src
, num_components
);
418 Builder
bld(ctx
->program
, ctx
->block
);
419 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
420 unsigned component_size
= vec_src
.bytes() / num_components
;
421 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
424 for (unsigned i
= 0; i
< num_components
; i
++) {
426 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
429 if (dst
.type() == RegType::vgpr
) {
430 assert(dst
.bytes() == k
* component_size
);
431 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
432 for (unsigned i
= 0; i
< k
; i
++)
433 vec
->operands
[i
] = Operand(elems
[i
]);
434 vec
->definitions
[0] = Definition(dst
);
435 bld
.insert(std::move(vec
));
437 // TODO: alignbyte if mask doesn't start with 1?
439 assert(dst
.size() == vec_src
.size());
440 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
442 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
445 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
447 Builder
bld(ctx
->program
, ctx
->block
);
449 dst
= bld
.tmp(bld
.lm
);
451 assert(val
.regClass() == s1
);
452 assert(dst
.regClass() == bld
.lm
);
454 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
457 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
459 Builder
bld(ctx
->program
, ctx
->block
);
463 assert(val
.regClass() == bld
.lm
);
464 assert(dst
.regClass() == s1
);
466 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
467 Temp tmp
= bld
.tmp(s1
);
468 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
469 return emit_wqm(ctx
, tmp
, dst
);
472 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
474 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
475 return get_ssa_temp(ctx
, src
.src
.ssa
);
477 if (src
.src
.ssa
->num_components
== size
) {
478 bool identity_swizzle
= true;
479 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
480 if (src
.swizzle
[i
] != i
)
481 identity_swizzle
= false;
483 if (identity_swizzle
)
484 return get_ssa_temp(ctx
, src
.src
.ssa
);
487 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
488 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
489 assert(elem_size
> 0);
490 assert(vec
.bytes() % elem_size
== 0);
492 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
493 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
495 unsigned swizzle
= src
.swizzle
[0];
496 if (vec
.size() > 1) {
497 assert(src
.src
.ssa
->bit_size
== 16);
498 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
499 swizzle
= swizzle
& 1;
504 Temp dst
{ctx
->program
->allocateId(), s1
};
505 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
506 bfe
->operands
[0] = Operand(vec
);
507 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
508 bfe
->definitions
[0] = Definition(dst
);
509 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
510 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
514 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
516 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
519 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
520 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
521 for (unsigned i
= 0; i
< size
; ++i
) {
522 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
523 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
525 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
526 vec_instr
->definitions
[0] = Definition(dst
);
527 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
528 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
533 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
537 Builder
bld(ctx
->program
, ctx
->block
);
538 if (ptr
.type() == RegType::vgpr
)
539 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
540 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
541 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
544 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
546 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
547 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
548 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
549 sop2
->definitions
[0] = Definition(dst
);
551 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
552 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
555 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
556 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
558 Builder
bld(ctx
->program
, ctx
->block
);
559 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
560 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
561 if (src1
.type() == RegType::sgpr
) {
562 if (commutative
&& src0
.type() == RegType::vgpr
) {
567 src1
= as_vgpr(ctx
, src1
);
571 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
572 assert(dst
.size() == 1);
573 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
574 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
576 bld
.vop2(op
, Definition(dst
), src0
, src1
);
580 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
581 bool flush_denorms
= false)
583 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
584 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
585 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
587 /* ensure that the instruction has at most 1 sgpr operand
588 * The optimizer will inline constants for us */
589 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
590 src0
= as_vgpr(ctx
, src0
);
591 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
592 src1
= as_vgpr(ctx
, src1
);
593 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
594 src2
= as_vgpr(ctx
, src2
);
596 Builder
bld(ctx
->program
, ctx
->block
);
597 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
598 assert(dst
.size() == 1);
599 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
600 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
602 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
608 Builder
bld(ctx
->program
, ctx
->block
);
609 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
612 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
615 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
616 assert(src0
.size() == src1
.size());
618 aco_ptr
<Instruction
> vopc
;
619 if (src1
.type() == RegType::sgpr
) {
620 if (src0
.type() == RegType::vgpr
) {
621 /* to swap the operands, we might also have to change the opcode */
623 case aco_opcode::v_cmp_lt_f16
:
624 op
= aco_opcode::v_cmp_gt_f16
;
626 case aco_opcode::v_cmp_ge_f16
:
627 op
= aco_opcode::v_cmp_le_f16
;
629 case aco_opcode::v_cmp_lt_i16
:
630 op
= aco_opcode::v_cmp_gt_i16
;
632 case aco_opcode::v_cmp_ge_i16
:
633 op
= aco_opcode::v_cmp_le_i16
;
635 case aco_opcode::v_cmp_lt_u16
:
636 op
= aco_opcode::v_cmp_gt_u16
;
638 case aco_opcode::v_cmp_ge_u16
:
639 op
= aco_opcode::v_cmp_le_u16
;
641 case aco_opcode::v_cmp_lt_f32
:
642 op
= aco_opcode::v_cmp_gt_f32
;
644 case aco_opcode::v_cmp_ge_f32
:
645 op
= aco_opcode::v_cmp_le_f32
;
647 case aco_opcode::v_cmp_lt_i32
:
648 op
= aco_opcode::v_cmp_gt_i32
;
650 case aco_opcode::v_cmp_ge_i32
:
651 op
= aco_opcode::v_cmp_le_i32
;
653 case aco_opcode::v_cmp_lt_u32
:
654 op
= aco_opcode::v_cmp_gt_u32
;
656 case aco_opcode::v_cmp_ge_u32
:
657 op
= aco_opcode::v_cmp_le_u32
;
659 case aco_opcode::v_cmp_lt_f64
:
660 op
= aco_opcode::v_cmp_gt_f64
;
662 case aco_opcode::v_cmp_ge_f64
:
663 op
= aco_opcode::v_cmp_le_f64
;
665 case aco_opcode::v_cmp_lt_i64
:
666 op
= aco_opcode::v_cmp_gt_i64
;
668 case aco_opcode::v_cmp_ge_i64
:
669 op
= aco_opcode::v_cmp_le_i64
;
671 case aco_opcode::v_cmp_lt_u64
:
672 op
= aco_opcode::v_cmp_gt_u64
;
674 case aco_opcode::v_cmp_ge_u64
:
675 op
= aco_opcode::v_cmp_le_u64
;
677 default: /* eq and ne are commutative */
684 src1
= as_vgpr(ctx
, src1
);
688 Builder
bld(ctx
->program
, ctx
->block
);
689 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
692 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
694 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
695 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
696 Builder
bld(ctx
->program
, ctx
->block
);
698 assert(dst
.regClass() == bld
.lm
);
699 assert(src0
.type() == RegType::sgpr
);
700 assert(src1
.type() == RegType::sgpr
);
701 assert(src0
.regClass() == src1
.regClass());
703 /* Emit the SALU comparison instruction */
704 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
705 /* Turn the result into a per-lane bool */
706 bool_to_vector_condition(ctx
, cmp
, dst
);
709 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
710 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
712 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
713 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
714 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
715 nir_dest_is_divergent(instr
->dest
.dest
) ||
716 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
717 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
718 aco_opcode op
= use_valu
? v_op
: s_op
;
719 assert(op
!= aco_opcode::num_opcodes
);
720 assert(dst
.regClass() == ctx
->program
->lane_mask
);
723 emit_vopc_instruction(ctx
, instr
, op
, dst
);
725 emit_sopc_instruction(ctx
, instr
, op
, dst
);
728 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
730 Builder
bld(ctx
->program
, ctx
->block
);
731 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
734 assert(dst
.regClass() == bld
.lm
);
735 assert(src0
.regClass() == bld
.lm
);
736 assert(src1
.regClass() == bld
.lm
);
738 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
741 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
743 Builder
bld(ctx
->program
, ctx
->block
);
744 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
745 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
746 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
748 assert(cond
.regClass() == bld
.lm
);
750 if (dst
.type() == RegType::vgpr
) {
751 aco_ptr
<Instruction
> bcsel
;
752 if (dst
.size() == 1) {
753 then
= as_vgpr(ctx
, then
);
754 els
= as_vgpr(ctx
, els
);
756 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
757 } else if (dst
.size() == 2) {
758 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
759 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
760 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
761 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
763 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
764 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
766 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
768 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
769 nir_print_instr(&instr
->instr
, stderr
);
770 fprintf(stderr
, "\n");
775 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
776 assert(dst
.regClass() == bld
.lm
);
777 assert(then
.regClass() == bld
.lm
);
778 assert(els
.regClass() == bld
.lm
);
781 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
782 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
783 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
784 assert(dst
.size() == then
.size());
785 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
786 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
788 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
789 nir_print_instr(&instr
->instr
, stderr
);
790 fprintf(stderr
, "\n");
795 /* divergent boolean bcsel
796 * this implements bcsel on bools: dst = s0 ? s1 : s2
797 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
798 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
800 if (cond
.id() != then
.id())
801 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
803 if (cond
.id() == els
.id())
804 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
806 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
807 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
810 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
811 aco_opcode op
, uint32_t undo
)
813 /* multiply by 16777216 to handle denormals */
814 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
815 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
816 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
817 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
818 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
820 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
822 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
825 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
827 if (ctx
->block
->fp_mode
.denorm32
== 0) {
828 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
832 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
835 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
837 if (ctx
->block
->fp_mode
.denorm32
== 0) {
838 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
842 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
845 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
847 if (ctx
->block
->fp_mode
.denorm32
== 0) {
848 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
852 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
855 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
857 if (ctx
->block
->fp_mode
.denorm32
== 0) {
858 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
862 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
865 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
867 if (ctx
->options
->chip_class
>= GFX7
)
868 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
870 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
871 /* TODO: create more efficient code! */
872 if (val
.type() == RegType::sgpr
)
873 val
= as_vgpr(ctx
, val
);
875 /* Split the input value. */
876 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
879 /* Extract the exponent and compute the unbiased value. */
880 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
881 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
883 /* Extract the fractional part. */
884 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
885 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
887 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
888 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
890 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
891 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
892 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
893 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
894 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
896 /* Get the sign bit. */
897 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
899 /* Decide the operation to apply depending on the unbiased exponent. */
900 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
901 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
902 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
903 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
904 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
905 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
907 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
910 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
912 if (ctx
->options
->chip_class
>= GFX7
)
913 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
915 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
916 Temp src0
= as_vgpr(ctx
, val
);
918 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
919 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
921 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
922 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
923 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
925 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
926 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
927 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
928 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
930 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
931 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
933 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
935 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
936 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
938 return add
->definitions
[0].getTemp();
941 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
943 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
944 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
946 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
949 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
950 return bld
.copy(Definition(dst
), src
);
951 else if (dst
.bytes() < src
.bytes())
952 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
956 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
959 } else if (src
.regClass() == s1
) {
961 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
963 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
965 assert(src_bits
!= 8 || src
.regClass() == v1b
);
966 assert(src_bits
!= 16 || src
.regClass() == v2b
);
967 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
968 sdwa
->operands
[0] = Operand(src
);
969 sdwa
->definitions
[0] = Definition(tmp
);
971 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
973 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
974 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
975 bld
.insert(std::move(sdwa
));
978 if (dst_bits
== 64) {
979 if (is_signed
&& dst
.regClass() == s2
) {
980 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
981 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
982 } else if (is_signed
&& dst
.regClass() == v2
) {
983 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
984 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
986 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
993 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
995 if (!instr
->dest
.dest
.is_ssa
) {
996 fprintf(stderr
, "nir alu dst not in ssa: ");
997 nir_print_instr(&instr
->instr
, stderr
);
998 fprintf(stderr
, "\n");
1001 Builder
bld(ctx
->program
, ctx
->block
);
1002 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1007 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1008 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1009 for (unsigned i
= 0; i
< num
; ++i
)
1010 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1012 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1013 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1014 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1015 for (unsigned i
= 0; i
< num
; ++i
) {
1016 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1017 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1019 vec
->operands
[i
] = Operand
{elems
[i
]};
1021 vec
->definitions
[0] = Definition(dst
);
1022 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1023 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1025 // TODO: that is a bit suboptimal..
1026 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1027 for (unsigned i
= 0; i
< num
- 1; ++i
)
1028 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1029 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1030 for (unsigned i
= 0; i
< num
; ++i
) {
1031 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1032 if (bit
% 32 == 0) {
1033 elems
[bit
/ 32] = elems
[i
];
1035 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1036 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1037 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1040 if (dst
.size() == 1)
1041 bld
.copy(Definition(dst
), elems
[0]);
1043 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1048 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1049 aco_ptr
<Instruction
> mov
;
1050 if (dst
.type() == RegType::sgpr
) {
1051 if (src
.type() == RegType::vgpr
)
1052 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1053 else if (src
.regClass() == s1
)
1054 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1055 else if (src
.regClass() == s2
)
1056 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1058 unreachable("wrong src register class for nir_op_imov");
1059 } else if (dst
.regClass() == v1
) {
1060 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1061 } else if (dst
.regClass() == v2
) {
1062 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1064 nir_print_instr(&instr
->instr
, stderr
);
1065 unreachable("Should have been lowered to scalar.");
1070 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1071 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1072 assert(src
.regClass() == bld
.lm
);
1073 assert(dst
.regClass() == bld
.lm
);
1074 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1075 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1076 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1077 } else if (dst
.regClass() == v1
) {
1078 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1079 } else if (dst
.type() == RegType::sgpr
) {
1080 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1081 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1083 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1084 nir_print_instr(&instr
->instr
, stderr
);
1085 fprintf(stderr
, "\n");
1090 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1091 if (dst
.regClass() == v1
) {
1092 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1093 } else if (dst
.regClass() == s1
) {
1094 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1095 } else if (dst
.size() == 2) {
1096 Temp src0
= bld
.tmp(dst
.type(), 1);
1097 Temp src1
= bld
.tmp(dst
.type(), 1);
1098 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1100 if (dst
.regClass() == s2
) {
1101 Temp carry
= bld
.tmp(s1
);
1102 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1103 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1104 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1106 Temp lower
= bld
.tmp(v1
);
1107 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1108 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1109 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1112 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1113 nir_print_instr(&instr
->instr
, stderr
);
1114 fprintf(stderr
, "\n");
1119 if (dst
.regClass() == s1
) {
1120 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1121 } else if (dst
.regClass() == v1
) {
1122 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1123 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1131 case nir_op_isign
: {
1132 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1133 if (dst
.regClass() == s1
) {
1134 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1135 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1136 } else if (dst
.regClass() == s2
) {
1137 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1139 if (ctx
->program
->chip_class
>= GFX8
)
1140 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1142 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1143 /* SCC gets zero-extended to 64 bit */
1144 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1145 } else if (dst
.regClass() == v1
) {
1146 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1147 } else if (dst
.regClass() == v2
) {
1148 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1149 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1150 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1151 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1152 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1156 nir_print_instr(&instr
->instr
, stderr
);
1157 fprintf(stderr
, "\n");
1162 if (dst
.regClass() == v1
) {
1163 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1164 } else if (dst
.regClass() == s1
) {
1165 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1167 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1168 nir_print_instr(&instr
->instr
, stderr
);
1169 fprintf(stderr
, "\n");
1174 if (dst
.regClass() == v1
) {
1175 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1176 } else if (dst
.regClass() == s1
) {
1177 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1179 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1180 nir_print_instr(&instr
->instr
, stderr
);
1181 fprintf(stderr
, "\n");
1186 if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1191 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1192 nir_print_instr(&instr
->instr
, stderr
);
1193 fprintf(stderr
, "\n");
1198 if (dst
.regClass() == v1
) {
1199 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1200 } else if (dst
.regClass() == s1
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1203 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1204 nir_print_instr(&instr
->instr
, stderr
);
1205 fprintf(stderr
, "\n");
1210 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1211 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1212 } else if (dst
.regClass() == v1
) {
1213 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1214 } else if (dst
.regClass() == s1
) {
1215 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1216 } else if (dst
.regClass() == s2
) {
1217 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1219 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1220 nir_print_instr(&instr
->instr
, stderr
);
1221 fprintf(stderr
, "\n");
1226 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1227 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1228 } else if (dst
.regClass() == v1
) {
1229 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1230 } else if (dst
.regClass() == s1
) {
1231 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1232 } else if (dst
.regClass() == s2
) {
1233 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1235 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1236 nir_print_instr(&instr
->instr
, stderr
);
1237 fprintf(stderr
, "\n");
1242 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1243 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1244 } else if (dst
.regClass() == v1
) {
1245 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1246 } else if (dst
.regClass() == s1
) {
1247 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1248 } else if (dst
.regClass() == s2
) {
1249 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1251 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1252 nir_print_instr(&instr
->instr
, stderr
);
1253 fprintf(stderr
, "\n");
1258 if (dst
.regClass() == v1
) {
1259 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1260 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1261 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1262 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1263 } else if (dst
.regClass() == v2
) {
1264 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1265 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1266 } else if (dst
.regClass() == s2
) {
1267 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1268 } else if (dst
.regClass() == s1
) {
1269 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1271 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1272 nir_print_instr(&instr
->instr
, stderr
);
1273 fprintf(stderr
, "\n");
1278 if (dst
.regClass() == v1
) {
1279 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1280 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1281 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1282 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1283 } else if (dst
.regClass() == v2
) {
1284 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1285 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1286 } else if (dst
.regClass() == s1
) {
1287 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1288 } else if (dst
.regClass() == s2
) {
1289 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1291 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1292 nir_print_instr(&instr
->instr
, stderr
);
1293 fprintf(stderr
, "\n");
1298 if (dst
.regClass() == v1
) {
1299 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1300 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1301 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1302 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1303 } else if (dst
.regClass() == v2
) {
1304 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1305 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1306 } else if (dst
.regClass() == s1
) {
1307 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1308 } else if (dst
.regClass() == s2
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1311 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1312 nir_print_instr(&instr
->instr
, stderr
);
1313 fprintf(stderr
, "\n");
1317 case nir_op_find_lsb
: {
1318 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1319 if (src
.regClass() == s1
) {
1320 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1321 } else if (src
.regClass() == v1
) {
1322 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1323 } else if (src
.regClass() == s2
) {
1324 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1326 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1327 nir_print_instr(&instr
->instr
, stderr
);
1328 fprintf(stderr
, "\n");
1332 case nir_op_ufind_msb
:
1333 case nir_op_ifind_msb
: {
1334 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1335 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1336 aco_opcode op
= src
.regClass() == s2
?
1337 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1338 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1339 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1341 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1342 Operand(src
.size() * 32u - 1u), msb_rev
);
1343 Temp msb
= sub
.def(0).getTemp();
1344 Temp carry
= sub
.def(1).getTemp();
1346 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1347 } else if (src
.regClass() == v1
) {
1348 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1349 Temp msb_rev
= bld
.tmp(v1
);
1350 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1351 Temp msb
= bld
.tmp(v1
);
1352 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1353 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1355 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1356 nir_print_instr(&instr
->instr
, stderr
);
1357 fprintf(stderr
, "\n");
1361 case nir_op_bitfield_reverse
: {
1362 if (dst
.regClass() == s1
) {
1363 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1364 } else if (dst
.regClass() == v1
) {
1365 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1367 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1368 nir_print_instr(&instr
->instr
, stderr
);
1369 fprintf(stderr
, "\n");
1374 if (dst
.regClass() == s1
) {
1375 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1379 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1380 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1381 if (dst
.regClass() == v1
) {
1382 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1386 assert(src0
.size() == 2 && src1
.size() == 2);
1387 Temp src00
= bld
.tmp(src0
.type(), 1);
1388 Temp src01
= bld
.tmp(dst
.type(), 1);
1389 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1390 Temp src10
= bld
.tmp(src1
.type(), 1);
1391 Temp src11
= bld
.tmp(dst
.type(), 1);
1392 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1394 if (dst
.regClass() == s2
) {
1395 Temp carry
= bld
.tmp(s1
);
1396 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1397 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1398 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1399 } else if (dst
.regClass() == v2
) {
1400 Temp dst0
= bld
.tmp(v1
);
1401 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1402 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1403 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1405 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1406 nir_print_instr(&instr
->instr
, stderr
);
1407 fprintf(stderr
, "\n");
1411 case nir_op_uadd_sat
: {
1412 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1413 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1414 if (dst
.regClass() == s1
) {
1415 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1416 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1418 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1419 } else if (dst
.regClass() == v1
) {
1420 if (ctx
->options
->chip_class
>= GFX9
) {
1421 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1422 add
->operands
[0] = Operand(src0
);
1423 add
->operands
[1] = Operand(src1
);
1424 add
->definitions
[0] = Definition(dst
);
1426 ctx
->block
->instructions
.emplace_back(std::move(add
));
1428 if (src1
.regClass() != v1
)
1429 std::swap(src0
, src1
);
1430 assert(src1
.regClass() == v1
);
1431 Temp tmp
= bld
.tmp(v1
);
1432 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1433 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1436 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1437 nir_print_instr(&instr
->instr
, stderr
);
1438 fprintf(stderr
, "\n");
1442 case nir_op_uadd_carry
: {
1443 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1444 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1445 if (dst
.regClass() == s1
) {
1446 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1449 if (dst
.regClass() == v1
) {
1450 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1451 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1455 Temp src00
= bld
.tmp(src0
.type(), 1);
1456 Temp src01
= bld
.tmp(dst
.type(), 1);
1457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1458 Temp src10
= bld
.tmp(src1
.type(), 1);
1459 Temp src11
= bld
.tmp(dst
.type(), 1);
1460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1461 if (dst
.regClass() == s2
) {
1462 Temp carry
= bld
.tmp(s1
);
1463 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1464 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1465 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1466 } else if (dst
.regClass() == v2
) {
1467 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1468 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1469 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1472 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1473 nir_print_instr(&instr
->instr
, stderr
);
1474 fprintf(stderr
, "\n");
1479 if (dst
.regClass() == s1
) {
1480 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1484 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1485 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1486 if (dst
.regClass() == v1
) {
1487 bld
.vsub32(Definition(dst
), src0
, src1
);
1491 Temp src00
= bld
.tmp(src0
.type(), 1);
1492 Temp src01
= bld
.tmp(dst
.type(), 1);
1493 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1494 Temp src10
= bld
.tmp(src1
.type(), 1);
1495 Temp src11
= bld
.tmp(dst
.type(), 1);
1496 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1497 if (dst
.regClass() == s2
) {
1498 Temp carry
= bld
.tmp(s1
);
1499 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1500 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1501 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1502 } else if (dst
.regClass() == v2
) {
1503 Temp lower
= bld
.tmp(v1
);
1504 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1505 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1506 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1508 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1509 nir_print_instr(&instr
->instr
, stderr
);
1510 fprintf(stderr
, "\n");
1514 case nir_op_usub_borrow
: {
1515 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1516 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1517 if (dst
.regClass() == s1
) {
1518 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1520 } else if (dst
.regClass() == v1
) {
1521 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1522 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1526 Temp src00
= bld
.tmp(src0
.type(), 1);
1527 Temp src01
= bld
.tmp(dst
.type(), 1);
1528 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1529 Temp src10
= bld
.tmp(src1
.type(), 1);
1530 Temp src11
= bld
.tmp(dst
.type(), 1);
1531 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1532 if (dst
.regClass() == s2
) {
1533 Temp borrow
= bld
.tmp(s1
);
1534 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1535 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1536 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1537 } else if (dst
.regClass() == v2
) {
1538 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1539 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1540 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1543 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1544 nir_print_instr(&instr
->instr
, stderr
);
1545 fprintf(stderr
, "\n");
1550 if (dst
.regClass() == v1
) {
1551 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1552 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1553 } else if (dst
.regClass() == s1
) {
1554 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1556 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1557 nir_print_instr(&instr
->instr
, stderr
);
1558 fprintf(stderr
, "\n");
1562 case nir_op_umul_high
: {
1563 if (dst
.regClass() == v1
) {
1564 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1565 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1566 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1567 } else if (dst
.regClass() == s1
) {
1568 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1569 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1570 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1572 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1573 nir_print_instr(&instr
->instr
, stderr
);
1574 fprintf(stderr
, "\n");
1578 case nir_op_imul_high
: {
1579 if (dst
.regClass() == v1
) {
1580 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1581 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1582 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1583 } else if (dst
.regClass() == s1
) {
1584 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1585 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1586 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1588 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1589 nir_print_instr(&instr
->instr
, stderr
);
1590 fprintf(stderr
, "\n");
1595 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1596 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1597 if (dst
.regClass() == v2b
) {
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1599 } else if (dst
.regClass() == v1
) {
1600 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1601 } else if (dst
.regClass() == v2
) {
1602 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1604 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1605 nir_print_instr(&instr
->instr
, stderr
);
1606 fprintf(stderr
, "\n");
1611 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1612 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1613 if (dst
.regClass() == v2b
) {
1614 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1615 } else if (dst
.regClass() == v1
) {
1616 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1617 } else if (dst
.regClass() == v2
) {
1618 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1620 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1621 nir_print_instr(&instr
->instr
, stderr
);
1622 fprintf(stderr
, "\n");
1627 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1628 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1629 if (dst
.regClass() == v2b
) {
1630 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1631 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1633 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1634 } else if (dst
.regClass() == v1
) {
1635 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1636 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1638 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1639 } else if (dst
.regClass() == v2
) {
1640 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1641 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1642 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1645 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1646 nir_print_instr(&instr
->instr
, stderr
);
1647 fprintf(stderr
, "\n");
1652 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1653 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1654 if (dst
.regClass() == v2b
) {
1655 // TODO: check fp_mode.must_flush_denorms16_64
1656 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1657 } else if (dst
.regClass() == v1
) {
1658 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1659 } else if (dst
.regClass() == v2
) {
1660 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1661 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1662 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1664 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1667 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1668 nir_print_instr(&instr
->instr
, stderr
);
1669 fprintf(stderr
, "\n");
1674 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1675 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1676 if (dst
.regClass() == v2b
) {
1677 // TODO: check fp_mode.must_flush_denorms16_64
1678 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1679 } else if (dst
.regClass() == v1
) {
1680 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1681 } else if (dst
.regClass() == v2
) {
1682 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1683 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1684 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1686 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1689 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1690 nir_print_instr(&instr
->instr
, stderr
);
1691 fprintf(stderr
, "\n");
1695 case nir_op_fmax3
: {
1696 if (dst
.regClass() == v2b
) {
1697 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1698 } else if (dst
.regClass() == v1
) {
1699 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1701 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1702 nir_print_instr(&instr
->instr
, stderr
);
1703 fprintf(stderr
, "\n");
1707 case nir_op_fmin3
: {
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1713 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1714 nir_print_instr(&instr
->instr
, stderr
);
1715 fprintf(stderr
, "\n");
1719 case nir_op_fmed3
: {
1720 if (dst
.regClass() == v2b
) {
1721 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1722 } else if (dst
.regClass() == v1
) {
1723 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1725 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1726 nir_print_instr(&instr
->instr
, stderr
);
1727 fprintf(stderr
, "\n");
1731 case nir_op_umax3
: {
1732 if (dst
.size() == 1) {
1733 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1735 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1736 nir_print_instr(&instr
->instr
, stderr
);
1737 fprintf(stderr
, "\n");
1741 case nir_op_umin3
: {
1742 if (dst
.size() == 1) {
1743 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1745 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1746 nir_print_instr(&instr
->instr
, stderr
);
1747 fprintf(stderr
, "\n");
1751 case nir_op_umed3
: {
1752 if (dst
.size() == 1) {
1753 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1755 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1756 nir_print_instr(&instr
->instr
, stderr
);
1757 fprintf(stderr
, "\n");
1761 case nir_op_imax3
: {
1762 if (dst
.size() == 1) {
1763 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1765 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1766 nir_print_instr(&instr
->instr
, stderr
);
1767 fprintf(stderr
, "\n");
1771 case nir_op_imin3
: {
1772 if (dst
.size() == 1) {
1773 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1776 nir_print_instr(&instr
->instr
, stderr
);
1777 fprintf(stderr
, "\n");
1781 case nir_op_imed3
: {
1782 if (dst
.size() == 1) {
1783 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1785 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1786 nir_print_instr(&instr
->instr
, stderr
);
1787 fprintf(stderr
, "\n");
1791 case nir_op_cube_face_coord
: {
1792 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1793 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1794 emit_extract_vector(ctx
, in
, 1, v1
),
1795 emit_extract_vector(ctx
, in
, 2, v1
) };
1796 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1797 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1798 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1799 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1800 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1801 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1802 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1805 case nir_op_cube_face_index
: {
1806 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1807 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1808 emit_extract_vector(ctx
, in
, 1, v1
),
1809 emit_extract_vector(ctx
, in
, 2, v1
) };
1810 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1813 case nir_op_bcsel
: {
1814 emit_bcsel(ctx
, instr
, dst
);
1818 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1819 if (dst
.regClass() == v2b
) {
1820 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1821 } else if (dst
.regClass() == v1
) {
1822 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1823 } else if (dst
.regClass() == v2
) {
1824 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1826 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1827 nir_print_instr(&instr
->instr
, stderr
);
1828 fprintf(stderr
, "\n");
1833 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1834 if (dst
.regClass() == v2b
) {
1835 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1836 } else if (dst
.regClass() == v1
) {
1837 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1838 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1839 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1840 } else if (dst
.regClass() == v2
) {
1841 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1842 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1843 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1844 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1845 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1846 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1848 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1849 nir_print_instr(&instr
->instr
, stderr
);
1850 fprintf(stderr
, "\n");
1855 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1856 if (dst
.regClass() == v2b
) {
1857 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1858 } else if (dst
.regClass() == v1
) {
1859 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1860 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1861 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1862 } else if (dst
.regClass() == v2
) {
1863 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1864 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1865 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1867 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1868 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1870 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1871 nir_print_instr(&instr
->instr
, stderr
);
1872 fprintf(stderr
, "\n");
1877 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1878 if (dst
.regClass() == v2b
) {
1879 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1880 } else if (dst
.regClass() == v1
) {
1881 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1882 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1883 // TODO: confirm that this holds under any circumstances
1884 } else if (dst
.regClass() == v2
) {
1885 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1886 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1889 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1890 nir_print_instr(&instr
->instr
, stderr
);
1891 fprintf(stderr
, "\n");
1895 case nir_op_flog2
: {
1896 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1897 if (dst
.regClass() == v2b
) {
1898 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1899 } else if (dst
.regClass() == v1
) {
1900 emit_log2(ctx
, bld
, Definition(dst
), src
);
1902 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1903 nir_print_instr(&instr
->instr
, stderr
);
1904 fprintf(stderr
, "\n");
1909 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1910 if (dst
.regClass() == v2b
) {
1911 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1912 } else if (dst
.regClass() == v1
) {
1913 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1914 } else if (dst
.regClass() == v2
) {
1915 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1917 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1918 nir_print_instr(&instr
->instr
, stderr
);
1919 fprintf(stderr
, "\n");
1923 case nir_op_fexp2
: {
1924 if (dst
.regClass() == v2b
) {
1925 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1926 } else if (dst
.regClass() == v1
) {
1927 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1929 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1930 nir_print_instr(&instr
->instr
, stderr
);
1931 fprintf(stderr
, "\n");
1935 case nir_op_fsqrt
: {
1936 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1937 if (dst
.regClass() == v2b
) {
1938 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1939 } else if (dst
.regClass() == v1
) {
1940 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1941 } else if (dst
.regClass() == v2
) {
1942 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1944 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1945 nir_print_instr(&instr
->instr
, stderr
);
1946 fprintf(stderr
, "\n");
1950 case nir_op_ffract
: {
1951 if (dst
.regClass() == v2b
) {
1952 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1953 } else if (dst
.regClass() == v1
) {
1954 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1955 } else if (dst
.regClass() == v2
) {
1956 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1958 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1959 nir_print_instr(&instr
->instr
, stderr
);
1960 fprintf(stderr
, "\n");
1964 case nir_op_ffloor
: {
1965 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1966 if (dst
.regClass() == v2b
) {
1967 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1968 } else if (dst
.regClass() == v1
) {
1969 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1970 } else if (dst
.regClass() == v2
) {
1971 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1973 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1974 nir_print_instr(&instr
->instr
, stderr
);
1975 fprintf(stderr
, "\n");
1979 case nir_op_fceil
: {
1980 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1981 if (dst
.regClass() == v2b
) {
1982 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1983 } else if (dst
.regClass() == v1
) {
1984 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1985 } else if (dst
.regClass() == v2
) {
1986 if (ctx
->options
->chip_class
>= GFX7
) {
1987 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1989 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1990 /* trunc = trunc(src0)
1991 * if (src0 > 0.0 && src0 != trunc)
1994 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1995 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1996 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1997 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1998 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1999 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2000 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2003 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2004 nir_print_instr(&instr
->instr
, stderr
);
2005 fprintf(stderr
, "\n");
2009 case nir_op_ftrunc
: {
2010 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2011 if (dst
.regClass() == v2b
) {
2012 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2013 } else if (dst
.regClass() == v1
) {
2014 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2015 } else if (dst
.regClass() == v2
) {
2016 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2018 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2019 nir_print_instr(&instr
->instr
, stderr
);
2020 fprintf(stderr
, "\n");
2024 case nir_op_fround_even
: {
2025 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2026 if (dst
.regClass() == v2b
) {
2027 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2028 } else if (dst
.regClass() == v1
) {
2029 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2030 } else if (dst
.regClass() == v2
) {
2031 if (ctx
->options
->chip_class
>= GFX7
) {
2032 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2034 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2035 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2036 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2038 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2039 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2040 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2041 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2042 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2043 tmp
= sub
->definitions
[0].getTemp();
2045 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2046 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2047 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2048 Temp cond
= vop3
->definitions
[0].getTemp();
2050 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2051 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2052 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2053 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2055 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2058 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2059 nir_print_instr(&instr
->instr
, stderr
);
2060 fprintf(stderr
, "\n");
2066 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2067 aco_ptr
<Instruction
> norm
;
2068 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2069 if (dst
.regClass() == v2b
) {
2070 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2071 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2072 bld
.vop1(opcode
, Definition(dst
), tmp
);
2073 } else if (dst
.regClass() == v1
) {
2074 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2076 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2077 if (ctx
->options
->chip_class
< GFX9
)
2078 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2080 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2081 bld
.vop1(opcode
, Definition(dst
), tmp
);
2083 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2084 nir_print_instr(&instr
->instr
, stderr
);
2085 fprintf(stderr
, "\n");
2089 case nir_op_ldexp
: {
2090 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2091 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2092 if (dst
.regClass() == v2b
) {
2093 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2094 } else if (dst
.regClass() == v1
) {
2095 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2096 } else if (dst
.regClass() == v2
) {
2097 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2099 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2100 nir_print_instr(&instr
->instr
, stderr
);
2101 fprintf(stderr
, "\n");
2105 case nir_op_frexp_sig
: {
2106 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2107 if (dst
.regClass() == v2b
) {
2108 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2109 } else if (dst
.regClass() == v1
) {
2110 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2111 } else if (dst
.regClass() == v2
) {
2112 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2114 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2115 nir_print_instr(&instr
->instr
, stderr
);
2116 fprintf(stderr
, "\n");
2120 case nir_op_frexp_exp
: {
2121 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2122 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2123 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2124 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2125 convert_int(bld
, tmp
, 8, 32, true, dst
);
2126 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2127 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2128 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2129 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2131 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2132 nir_print_instr(&instr
->instr
, stderr
);
2133 fprintf(stderr
, "\n");
2137 case nir_op_fsign
: {
2138 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2139 if (dst
.regClass() == v2b
) {
2140 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2141 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2142 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2143 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2144 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2145 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2146 } else if (dst
.regClass() == v1
) {
2147 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2148 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2149 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2150 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2151 } else if (dst
.regClass() == v2
) {
2152 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2153 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2154 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2156 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2157 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2158 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2160 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2162 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2163 nir_print_instr(&instr
->instr
, stderr
);
2164 fprintf(stderr
, "\n");
2169 case nir_op_f2f16_rtne
: {
2170 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2171 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2172 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2173 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2176 case nir_op_f2f16_rtz
: {
2177 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2178 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2179 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2180 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2183 case nir_op_f2f32
: {
2184 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2185 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2186 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2187 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2189 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2190 nir_print_instr(&instr
->instr
, stderr
);
2191 fprintf(stderr
, "\n");
2195 case nir_op_f2f64
: {
2196 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2197 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2198 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2199 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2202 case nir_op_i2f16
: {
2203 assert(dst
.regClass() == v2b
);
2204 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2205 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2206 src
= convert_int(bld
, src
, 8, 16, true);
2207 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2210 case nir_op_i2f32
: {
2211 assert(dst
.size() == 1);
2212 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2213 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2214 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2215 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2218 case nir_op_i2f64
: {
2219 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2220 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2221 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2222 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2223 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2224 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2225 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2226 RegClass rc
= RegClass(src
.type(), 1);
2227 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2228 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2229 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2230 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2231 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2232 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2235 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2236 nir_print_instr(&instr
->instr
, stderr
);
2237 fprintf(stderr
, "\n");
2241 case nir_op_u2f16
: {
2242 assert(dst
.regClass() == v2b
);
2243 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2244 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2245 src
= convert_int(bld
, src
, 8, 16, false);
2246 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2249 case nir_op_u2f32
: {
2250 assert(dst
.size() == 1);
2251 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2252 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2253 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2254 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2256 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2257 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2258 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2262 case nir_op_u2f64
: {
2263 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2264 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2265 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2266 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2267 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2268 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2269 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2270 RegClass rc
= RegClass(src
.type(), 1);
2271 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2272 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2273 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2274 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2275 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2276 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2278 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2279 nir_print_instr(&instr
->instr
, stderr
);
2280 fprintf(stderr
, "\n");
2285 case nir_op_f2i16
: {
2286 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2287 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2288 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2289 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2290 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2292 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2294 if (dst
.type() == RegType::vgpr
)
2295 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2297 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2301 case nir_op_f2u16
: {
2302 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2303 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2304 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2305 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2306 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2308 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2310 if (dst
.type() == RegType::vgpr
)
2311 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2313 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2316 case nir_op_f2i32
: {
2317 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2318 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2319 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2320 if (dst
.type() == RegType::vgpr
) {
2321 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2323 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2324 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2326 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2327 if (dst
.type() == RegType::vgpr
)
2328 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2330 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2331 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2333 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2334 if (dst
.type() == RegType::vgpr
)
2335 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2337 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2338 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2341 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2342 nir_print_instr(&instr
->instr
, stderr
);
2343 fprintf(stderr
, "\n");
2347 case nir_op_f2u32
: {
2348 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2349 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2350 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2351 if (dst
.type() == RegType::vgpr
) {
2352 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2354 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2355 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2357 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2358 if (dst
.type() == RegType::vgpr
)
2359 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2361 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2362 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2364 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2365 if (dst
.type() == RegType::vgpr
)
2366 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2368 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2369 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2372 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2373 nir_print_instr(&instr
->instr
, stderr
);
2374 fprintf(stderr
, "\n");
2378 case nir_op_f2i64
: {
2379 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2380 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2381 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2383 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2384 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2385 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2386 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2387 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2388 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2389 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2390 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2391 Temp new_exponent
= bld
.tmp(v1
);
2392 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2393 if (ctx
->program
->chip_class
>= GFX8
)
2394 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2396 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2397 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2398 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2399 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2400 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2401 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2402 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2403 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2404 Temp new_lower
= bld
.tmp(v1
);
2405 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2406 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2407 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2409 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2410 if (src
.type() == RegType::vgpr
)
2411 src
= bld
.as_uniform(src
);
2412 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2413 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2414 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2415 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2416 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2417 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2418 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2419 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2420 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2421 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2422 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2423 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2424 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2425 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2426 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2428 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2429 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2430 Temp borrow
= bld
.tmp(s1
);
2431 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2432 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2433 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2435 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2436 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2437 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2438 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2439 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2440 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2441 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2442 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2443 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2444 if (dst
.type() == RegType::sgpr
) {
2445 lower
= bld
.as_uniform(lower
);
2446 upper
= bld
.as_uniform(upper
);
2448 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2451 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2452 nir_print_instr(&instr
->instr
, stderr
);
2453 fprintf(stderr
, "\n");
2457 case nir_op_f2u64
: {
2458 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2459 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2460 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2462 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2463 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2464 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2465 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2466 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2467 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2468 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2469 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2470 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2471 Temp new_exponent
= bld
.tmp(v1
);
2472 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2473 if (ctx
->program
->chip_class
>= GFX8
)
2474 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2476 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2477 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2478 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2479 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2480 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2481 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2482 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2483 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2485 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2486 if (src
.type() == RegType::vgpr
)
2487 src
= bld
.as_uniform(src
);
2488 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2489 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2490 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2491 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2492 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2493 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2494 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2495 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2496 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2497 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2498 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2499 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2500 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2501 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2502 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2503 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2504 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2507 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2508 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2509 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2510 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2511 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2512 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2513 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2514 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2515 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2516 if (dst
.type() == RegType::sgpr
) {
2517 lower
= bld
.as_uniform(lower
);
2518 upper
= bld
.as_uniform(upper
);
2520 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2523 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2524 nir_print_instr(&instr
->instr
, stderr
);
2525 fprintf(stderr
, "\n");
2529 case nir_op_b2f16
: {
2530 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2531 assert(src
.regClass() == bld
.lm
);
2533 if (dst
.regClass() == s1
) {
2534 src
= bool_to_scalar_condition(ctx
, src
);
2535 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2536 } else if (dst
.regClass() == v2b
) {
2537 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2538 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2540 unreachable("Wrong destination register class for nir_op_b2f16.");
2544 case nir_op_b2f32
: {
2545 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2546 assert(src
.regClass() == bld
.lm
);
2548 if (dst
.regClass() == s1
) {
2549 src
= bool_to_scalar_condition(ctx
, src
);
2550 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2551 } else if (dst
.regClass() == v1
) {
2552 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2554 unreachable("Wrong destination register class for nir_op_b2f32.");
2558 case nir_op_b2f64
: {
2559 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2560 assert(src
.regClass() == bld
.lm
);
2562 if (dst
.regClass() == s2
) {
2563 src
= bool_to_scalar_condition(ctx
, src
);
2564 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2565 } else if (dst
.regClass() == v2
) {
2566 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2567 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2568 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2570 unreachable("Wrong destination register class for nir_op_b2f64.");
2577 case nir_op_i2i64
: {
2578 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2579 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2585 case nir_op_u2u64
: {
2586 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2587 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2591 case nir_op_b2i32
: {
2592 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2593 assert(src
.regClass() == bld
.lm
);
2595 if (dst
.regClass() == s1
) {
2596 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2597 bool_to_scalar_condition(ctx
, src
, dst
);
2598 } else if (dst
.regClass() == v1
) {
2599 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2601 unreachable("Invalid register class for b2i32");
2607 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2608 assert(dst
.regClass() == bld
.lm
);
2610 if (src
.type() == RegType::vgpr
) {
2611 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2612 assert(dst
.regClass() == bld
.lm
);
2613 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2614 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2616 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2618 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2619 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2621 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2622 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2624 bool_to_vector_condition(ctx
, tmp
, dst
);
2628 case nir_op_pack_64_2x32_split
: {
2629 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2630 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2632 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2635 case nir_op_unpack_64_2x32_split_x
:
2636 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2638 case nir_op_unpack_64_2x32_split_y
:
2639 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2641 case nir_op_unpack_32_2x16_split_x
:
2642 if (dst
.type() == RegType::vgpr
) {
2643 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2645 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2648 case nir_op_unpack_32_2x16_split_y
:
2649 if (dst
.type() == RegType::vgpr
) {
2650 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2652 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2655 case nir_op_pack_32_2x16_split
: {
2656 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2657 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2658 if (dst
.regClass() == v1
) {
2659 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2660 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2661 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2663 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2664 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2665 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2669 case nir_op_pack_half_2x16
: {
2670 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2672 if (dst
.regClass() == v1
) {
2673 Temp src0
= bld
.tmp(v1
);
2674 Temp src1
= bld
.tmp(v1
);
2675 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2676 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2677 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2679 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2680 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2681 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2683 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2684 nir_print_instr(&instr
->instr
, stderr
);
2685 fprintf(stderr
, "\n");
2689 case nir_op_unpack_half_2x16_split_x
: {
2690 if (dst
.regClass() == v1
) {
2691 Builder
bld(ctx
->program
, ctx
->block
);
2692 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2694 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2695 nir_print_instr(&instr
->instr
, stderr
);
2696 fprintf(stderr
, "\n");
2700 case nir_op_unpack_half_2x16_split_y
: {
2701 if (dst
.regClass() == v1
) {
2702 Builder
bld(ctx
->program
, ctx
->block
);
2703 /* TODO: use SDWA here */
2704 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2705 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2707 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2708 nir_print_instr(&instr
->instr
, stderr
);
2709 fprintf(stderr
, "\n");
2713 case nir_op_fquantize2f16
: {
2714 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2715 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2718 if (ctx
->program
->chip_class
>= GFX8
) {
2719 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2720 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2721 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2723 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2724 * so compare the result and flush to 0 if it's smaller.
2726 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2727 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2728 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2729 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2730 cmp_res
= vop3
->definitions
[0].getTemp();
2733 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2734 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2735 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2737 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2742 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2743 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2745 if (dst
.regClass() == s1
) {
2746 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2747 } else if (dst
.regClass() == v1
) {
2748 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2751 nir_print_instr(&instr
->instr
, stderr
);
2752 fprintf(stderr
, "\n");
2756 case nir_op_bitfield_select
: {
2757 /* (mask & insert) | (~mask & base) */
2758 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2759 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2760 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2762 /* dst = (insert & bitmask) | (base & ~bitmask) */
2763 if (dst
.regClass() == s1
) {
2764 aco_ptr
<Instruction
> sop2
;
2765 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2766 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2768 if (const_insert
&& const_bitmask
) {
2769 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2771 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2772 lhs
= Operand(insert
);
2776 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2777 if (const_base
&& const_bitmask
) {
2778 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2780 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2781 rhs
= Operand(base
);
2784 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2786 } else if (dst
.regClass() == v1
) {
2787 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2788 base
= as_vgpr(ctx
, base
);
2789 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2790 insert
= as_vgpr(ctx
, insert
);
2792 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2796 nir_print_instr(&instr
->instr
, stderr
);
2797 fprintf(stderr
, "\n");
2803 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2804 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2805 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2807 if (dst
.type() == RegType::sgpr
) {
2809 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2810 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2811 if (const_offset
&& const_bits
) {
2812 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2813 extract
= Operand(const_extract
);
2817 width
= Operand(const_bits
->u32
<< 16);
2819 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2821 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2825 if (dst
.regClass() == s1
) {
2826 if (instr
->op
== nir_op_ubfe
)
2827 opcode
= aco_opcode::s_bfe_u32
;
2829 opcode
= aco_opcode::s_bfe_i32
;
2830 } else if (dst
.regClass() == s2
) {
2831 if (instr
->op
== nir_op_ubfe
)
2832 opcode
= aco_opcode::s_bfe_u64
;
2834 opcode
= aco_opcode::s_bfe_i64
;
2836 unreachable("Unsupported BFE bit size");
2839 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2843 if (dst
.regClass() == v1
) {
2844 if (instr
->op
== nir_op_ubfe
)
2845 opcode
= aco_opcode::v_bfe_u32
;
2847 opcode
= aco_opcode::v_bfe_i32
;
2849 unreachable("Unsupported BFE bit size");
2852 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2856 case nir_op_bit_count
: {
2857 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2858 if (src
.regClass() == s1
) {
2859 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2860 } else if (src
.regClass() == v1
) {
2861 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2862 } else if (src
.regClass() == v2
) {
2863 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2864 emit_extract_vector(ctx
, src
, 1, v1
),
2865 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2866 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2867 } else if (src
.regClass() == s2
) {
2868 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2870 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2871 nir_print_instr(&instr
->instr
, stderr
);
2872 fprintf(stderr
, "\n");
2877 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2881 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2885 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2889 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2893 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2897 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2901 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2902 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2904 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2905 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2909 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2910 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2912 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2913 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2917 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2921 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2926 case nir_op_fddx_fine
:
2927 case nir_op_fddy_fine
:
2928 case nir_op_fddx_coarse
:
2929 case nir_op_fddy_coarse
: {
2930 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2931 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2932 if (instr
->op
== nir_op_fddx_fine
) {
2933 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2934 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2935 } else if (instr
->op
== nir_op_fddy_fine
) {
2936 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2937 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2939 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2940 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2941 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2943 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2947 if (ctx
->program
->chip_class
>= GFX8
) {
2948 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2949 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2951 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2952 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2953 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2955 emit_wqm(ctx
, tmp
, dst
, true);
2959 fprintf(stderr
, "Unknown NIR ALU instr: ");
2960 nir_print_instr(&instr
->instr
, stderr
);
2961 fprintf(stderr
, "\n");
2965 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2967 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2969 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2970 // which get truncated the lsb if double and msb if int
2971 // for now, we only use s_mov_b64 with 64bit inline constants
2972 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2973 assert(dst
.type() == RegType::sgpr
);
2975 Builder
bld(ctx
->program
, ctx
->block
);
2977 if (instr
->def
.bit_size
== 1) {
2978 assert(dst
.regClass() == bld
.lm
);
2979 int val
= instr
->value
[0].b
? -1 : 0;
2980 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2981 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2982 } else if (instr
->def
.bit_size
== 8) {
2983 /* ensure that the value is correctly represented in the low byte of the register */
2984 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2985 } else if (instr
->def
.bit_size
== 16) {
2986 /* ensure that the value is correctly represented in the low half of the register */
2987 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2988 } else if (dst
.size() == 1) {
2989 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2991 assert(dst
.size() != 1);
2992 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2993 if (instr
->def
.bit_size
== 64)
2994 for (unsigned i
= 0; i
< dst
.size(); i
++)
2995 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2997 for (unsigned i
= 0; i
< dst
.size(); i
++)
2998 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3000 vec
->definitions
[0] = Definition(dst
);
3001 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3005 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3007 uint32_t new_mask
= 0;
3008 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3009 if (mask
& (1u << i
))
3010 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3014 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3016 Builder
bld(ctx
->program
, ctx
->block
);
3017 if (offset
.isTemp()) {
3018 Temp tmp
[3] = {vec
, vec
, vec
};
3020 if (vec
.size() == 3) {
3021 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3022 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3023 } else if (vec
.size() == 2) {
3024 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3027 for (unsigned i
= 0; i
< dst
.size(); i
++)
3028 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3031 if (dst
.size() == 2)
3032 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3034 offset
= Operand(0u);
3037 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3038 bld
.copy(Definition(dst
), vec
);
3040 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3043 struct LoadEmitInfo
{
3046 unsigned num_components
;
3047 unsigned component_size
;
3048 Temp resource
= Temp(0, s1
);
3049 unsigned component_stride
= 0;
3050 unsigned const_offset
= 0;
3051 unsigned align_mul
= 0;
3052 unsigned align_offset
= 0;
3055 unsigned swizzle_component_size
= 0;
3056 barrier_interaction barrier
= barrier_none
;
3057 bool can_reorder
= true;
3058 Temp soffset
= Temp(0, s1
);
3061 using LoadCallback
= Temp(*)(
3062 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3063 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3065 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3066 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3068 unsigned load_size
= info
->num_components
* info
->component_size
;
3069 unsigned component_size
= info
->component_size
;
3071 unsigned num_vals
= 0;
3072 Temp vals
[info
->dst
.bytes()];
3074 unsigned const_offset
= info
->const_offset
;
3076 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3077 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3079 unsigned bytes_read
= 0;
3080 while (bytes_read
< load_size
) {
3081 unsigned bytes_needed
= load_size
- bytes_read
;
3083 /* add buffer for unaligned loads */
3084 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3087 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3088 if (info
->component_stride
) {
3089 assert(supports_8bit_16bit_loads
&& "unimplemented");
3093 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3094 bytes_needed
= align(bytes_needed
, 4);
3101 if (info
->swizzle_component_size
)
3102 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3103 if (info
->component_stride
)
3104 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3106 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3108 /* reduce constant offset */
3109 Operand offset
= info
->offset
;
3110 unsigned reduced_const_offset
= const_offset
;
3111 bool remove_const_offset_completely
= need_to_align_offset
;
3112 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3113 unsigned to_add
= const_offset
;
3114 if (remove_const_offset_completely
) {
3115 reduced_const_offset
= 0;
3117 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3118 reduced_const_offset
%= max_const_offset_plus_one
;
3120 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3121 if (offset
.isConstant()) {
3122 offset
= Operand(offset
.constantValue() + to_add
);
3123 } else if (offset_tmp
.regClass() == s1
) {
3124 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3125 offset_tmp
, Operand(to_add
));
3126 } else if (offset_tmp
.regClass() == v1
) {
3127 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3129 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3130 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3131 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3133 if (offset_tmp
.regClass() == s2
) {
3134 Temp carry
= bld
.tmp(s1
);
3135 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3136 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3137 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3139 Temp new_lo
= bld
.tmp(v1
);
3140 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3141 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3142 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3147 /* align offset down if needed */
3148 Operand aligned_offset
= offset
;
3149 if (need_to_align_offset
) {
3150 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3151 if (offset
.isConstant()) {
3152 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3153 } else if (offset_tmp
.regClass() == s1
) {
3154 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3155 } else if (offset_tmp
.regClass() == s2
) {
3156 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3157 } else if (offset_tmp
.regClass() == v1
) {
3158 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3159 } else if (offset_tmp
.regClass() == v2
) {
3160 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3161 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3162 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3163 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3166 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3167 bld
.copy(bld
.def(s1
), aligned_offset
);
3169 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3170 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3171 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3173 /* shift result right if needed */
3175 Operand
align((uint32_t)byte_align
);
3176 if (byte_align
== -1) {
3177 if (offset
.isConstant())
3178 align
= Operand(offset
.constantValue() % 4u);
3179 else if (offset
.size() == 2)
3180 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3185 if (align
.isTemp() || align
.constantValue()) {
3186 assert(val
.bytes() >= load_size
&& "unimplemented");
3187 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3188 if (val
.type() == RegType::sgpr
)
3189 byte_align_scalar(ctx
, val
, align
, new_val
);
3191 byte_align_vector(ctx
, val
, align
, new_val
);
3196 /* add result to list and advance */
3197 if (info
->component_stride
) {
3198 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3199 const_offset
+= info
->component_stride
;
3200 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3202 const_offset
+= val
.bytes();
3203 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3205 bytes_read
+= val
.bytes();
3206 vals
[num_vals
++] = val
;
3209 /* the callback wrote directly to dst */
3210 if (vals
[0] == info
->dst
) {
3211 assert(num_vals
== 1);
3212 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3216 /* create array of components */
3217 unsigned components_split
= 0;
3218 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3219 bool has_vgprs
= false;
3220 for (unsigned i
= 0; i
< num_vals
;) {
3222 unsigned num_tmps
= 0;
3223 unsigned tmp_size
= 0;
3224 RegType reg_type
= RegType::sgpr
;
3225 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3226 if (vals
[i
].type() == RegType::vgpr
)
3227 reg_type
= RegType::vgpr
;
3228 tmp_size
+= vals
[i
].bytes();
3229 tmp
[num_tmps
++] = vals
[i
++];
3232 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3233 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3234 for (unsigned i
= 0; i
< num_vals
; i
++)
3235 vec
->operands
[i
] = Operand(tmp
[i
]);
3236 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3237 vec
->definitions
[0] = Definition(tmp
[0]);
3238 bld
.insert(std::move(vec
));
3241 if (tmp
[0].bytes() % component_size
) {
3243 assert(i
== num_vals
);
3244 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3245 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3248 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3250 unsigned start
= components_split
;
3252 if (tmp_size
== elem_rc
.bytes()) {
3253 allocated_vec
[components_split
++] = tmp
[0];
3255 assert(tmp_size
% elem_rc
.bytes() == 0);
3256 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3257 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3258 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3259 Temp component
= bld
.tmp(elem_rc
);
3260 allocated_vec
[components_split
++] = component
;
3261 split
->definitions
[i
] = Definition(component
);
3263 split
->operands
[0] = Operand(tmp
[0]);
3264 bld
.insert(std::move(split
));
3267 /* try to p_as_uniform early so we can create more optimizable code and
3268 * also update allocated_vec */
3269 for (unsigned j
= start
; j
< components_split
; j
++) {
3270 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3271 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3272 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3276 /* concatenate components and p_as_uniform() result if needed */
3277 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3278 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3280 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3282 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3283 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3284 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3285 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3287 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3288 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3289 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3290 vec
->definitions
[0] = Definition(tmp
);
3291 bld
.insert(std::move(vec
));
3292 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3294 vec
->definitions
[0] = Definition(info
->dst
);
3295 bld
.insert(std::move(vec
));
3299 Operand
load_lds_size_m0(Builder
& bld
)
3301 /* TODO: m0 does not need to be initialized on GFX9+ */
3302 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3305 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3306 Temp offset
, unsigned bytes_needed
,
3307 unsigned align
, unsigned const_offset
,
3310 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3312 Operand m
= load_lds_size_m0(bld
);
3314 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3315 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3320 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3321 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3323 op
= aco_opcode::ds_read_b128
;
3324 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3327 op
= aco_opcode::ds_read2_b64
;
3328 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3330 op
= aco_opcode::ds_read_b96
;
3331 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3333 op
= aco_opcode::ds_read_b64
;
3334 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3337 op
= aco_opcode::ds_read2_b32
;
3338 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3340 op
= aco_opcode::ds_read_b32
;
3341 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3343 op
= aco_opcode::ds_read_u16
;
3346 op
= aco_opcode::ds_read_u8
;
3349 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3350 if (const_offset
>= max_offset_plus_one
) {
3351 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3352 const_offset
%= max_offset_plus_one
;
3356 const_offset
/= (size
/ 2u);
3358 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3359 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3361 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3363 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3366 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3371 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3373 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3374 Temp offset
, unsigned bytes_needed
,
3375 unsigned align
, unsigned const_offset
,
3380 if (bytes_needed
<= 4) {
3382 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3383 } else if (bytes_needed
<= 8) {
3385 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3386 } else if (bytes_needed
<= 16) {
3388 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3389 } else if (bytes_needed
<= 32) {
3391 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3394 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3396 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3397 if (info
->resource
.id()) {
3398 load
->operands
[0] = Operand(info
->resource
);
3399 load
->operands
[1] = Operand(offset
);
3401 load
->operands
[0] = Operand(offset
);
3402 load
->operands
[1] = Operand(0u);
3404 RegClass
rc(RegType::sgpr
, size
);
3405 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3406 load
->definitions
[0] = Definition(val
);
3407 load
->glc
= info
->glc
;
3408 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3409 load
->barrier
= info
->barrier
;
3410 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3411 bld
.insert(std::move(load
));
3415 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3417 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3418 Temp offset
, unsigned bytes_needed
,
3419 unsigned align_
, unsigned const_offset
,
3422 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3423 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3425 if (info
->soffset
.id()) {
3426 if (soffset
.isTemp())
3427 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3428 soffset
= Operand(info
->soffset
);
3431 unsigned bytes_size
= 0;
3433 if (bytes_needed
== 1) {
3435 op
= aco_opcode::buffer_load_ubyte
;
3436 } else if (bytes_needed
== 2) {
3438 op
= aco_opcode::buffer_load_ushort
;
3439 } else if (bytes_needed
<= 4) {
3441 op
= aco_opcode::buffer_load_dword
;
3442 } else if (bytes_needed
<= 8) {
3444 op
= aco_opcode::buffer_load_dwordx2
;
3445 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3447 op
= aco_opcode::buffer_load_dwordx3
;
3450 op
= aco_opcode::buffer_load_dwordx4
;
3452 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3453 mubuf
->operands
[0] = Operand(info
->resource
);
3454 mubuf
->operands
[1] = vaddr
;
3455 mubuf
->operands
[2] = soffset
;
3456 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3457 mubuf
->glc
= info
->glc
;
3458 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3459 mubuf
->barrier
= info
->barrier
;
3460 mubuf
->can_reorder
= info
->can_reorder
;
3461 mubuf
->offset
= const_offset
;
3462 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3463 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3464 mubuf
->definitions
[0] = Definition(val
);
3465 bld
.insert(std::move(mubuf
));
3468 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3473 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3475 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3477 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3478 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3480 if (addr
.type() == RegType::vgpr
)
3481 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3482 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3485 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3486 Temp offset
, unsigned bytes_needed
,
3487 unsigned align_
, unsigned const_offset
,
3490 unsigned bytes_size
= 0;
3491 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3492 bool global
= bld
.program
->chip_class
>= GFX9
;
3494 if (bytes_needed
== 1) {
3496 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3497 } else if (bytes_needed
== 2) {
3499 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3500 } else if (bytes_needed
<= 4) {
3502 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3503 } else if (bytes_needed
<= 8) {
3505 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3506 } else if (bytes_needed
<= 12 && !mubuf
) {
3508 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3511 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3513 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3514 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3516 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3517 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3518 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3519 mubuf
->operands
[2] = Operand(0u);
3520 mubuf
->glc
= info
->glc
;
3523 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3524 mubuf
->disable_wqm
= false;
3525 mubuf
->barrier
= info
->barrier
;
3526 mubuf
->definitions
[0] = Definition(val
);
3527 bld
.insert(std::move(mubuf
));
3529 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3531 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3532 flat
->operands
[0] = Operand(offset
);
3533 flat
->operands
[1] = Operand(s1
);
3534 flat
->glc
= info
->glc
;
3535 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3536 flat
->barrier
= info
->barrier
;
3538 flat
->definitions
[0] = Definition(val
);
3539 bld
.insert(std::move(flat
));
3543 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3548 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3550 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3551 Temp address
, unsigned base_offset
, unsigned align
)
3553 assert(util_is_power_of_two_nonzero(align
));
3555 Builder
bld(ctx
->program
, ctx
->block
);
3557 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3558 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3559 info
.align_mul
= align
;
3560 info
.align_offset
= 0;
3561 info
.barrier
= barrier_shared
;
3562 info
.can_reorder
= false;
3563 info
.const_offset
= base_offset
;
3564 emit_lds_load(ctx
, bld
, &info
);
3569 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3574 Builder
bld(ctx
->program
, ctx
->block
);
3576 ASSERTED
bool is_subdword
= false;
3577 for (unsigned i
= 0; i
< count
; i
++)
3578 is_subdword
|= offsets
[i
] % 4;
3579 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3580 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3582 /* count == 1 fast path */
3584 if (dst_type
== RegType::sgpr
)
3585 dst
[0] = bld
.as_uniform(src
);
3587 dst
[0] = as_vgpr(ctx
, src
);
3591 for (unsigned i
= 0; i
< count
- 1; i
++)
3592 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3593 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3595 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3596 src
= as_vgpr(ctx
, src
);
3598 /* use allocated_vec if possible */
3599 auto it
= ctx
->allocated_vec
.find(src
.id());
3600 if (it
!= ctx
->allocated_vec
.end()) {
3601 unsigned total_size
= 0;
3602 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3603 total_size
+= it
->second
[i
].bytes();
3604 if (total_size
!= src
.bytes())
3607 unsigned elem_size
= it
->second
[0].bytes();
3609 for (unsigned i
= 0; i
< count
; i
++) {
3610 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3614 for (unsigned i
= 0; i
< count
; i
++) {
3615 unsigned start_idx
= offsets
[i
] / elem_size
;
3616 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3617 if (op_count
== 1) {
3618 if (dst_type
== RegType::sgpr
)
3619 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3621 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3625 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3626 for (unsigned j
= 0; j
< op_count
; j
++) {
3627 Temp tmp
= it
->second
[start_idx
+ j
];
3628 if (dst_type
== RegType::sgpr
)
3629 tmp
= bld
.as_uniform(tmp
);
3630 vec
->operands
[j
] = Operand(tmp
);
3632 vec
->definitions
[0] = Definition(dst
[i
]);
3633 bld
.insert(std::move(vec
));
3639 if (dst_type
== RegType::sgpr
)
3640 src
= bld
.as_uniform(src
);
3644 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3645 split
->operands
[0] = Operand(src
);
3646 for (unsigned i
= 0; i
< count
; i
++)
3647 split
->definitions
[i
] = Definition(dst
[i
]);
3648 bld
.insert(std::move(split
));
3651 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3652 int *start
, int *count
)
3654 unsigned start_elem
= ffs(todo_mask
) - 1;
3655 bool skip
= !(mask
& (1 << start_elem
));
3657 mask
= ~mask
& todo_mask
;
3661 u_bit_scan_consecutive_range(&mask
, start
, count
);
3666 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3668 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3671 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3672 Temp address
, unsigned base_offset
, unsigned align
)
3674 assert(util_is_power_of_two_nonzero(align
));
3675 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3677 Builder
bld(ctx
->program
, ctx
->block
);
3678 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3679 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3681 unsigned write_count
= 0;
3682 Temp write_datas
[32];
3683 unsigned offsets
[32];
3684 aco_opcode opcodes
[32];
3686 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3688 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3691 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3692 offsets
[write_count
] = offset
;
3693 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3695 advance_write_mask(&todo
, offset
, bytes
);
3699 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3700 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3701 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3702 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3704 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3705 aco_opcode op
= aco_opcode::num_opcodes
;
3706 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3707 op
= aco_opcode::ds_write_b128
;
3709 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3710 op
= aco_opcode::ds_write_b96
;
3712 } else if (bytes
>= 8 && aligned8
) {
3713 op
= aco_opcode::ds_write_b64
;
3715 } else if (bytes
>= 4 && aligned4
) {
3716 op
= aco_opcode::ds_write_b32
;
3718 } else if (bytes
>= 2 && aligned2
) {
3719 op
= aco_opcode::ds_write_b16
;
3721 } else if (bytes
>= 1) {
3722 op
= aco_opcode::ds_write_b8
;
3728 offsets
[write_count
] = offset
;
3729 opcodes
[write_count
] = op
;
3731 advance_write_mask(&todo
, offset
, bytes
);
3734 Operand m
= load_lds_size_m0(bld
);
3736 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3738 for (unsigned i
= 0; i
< write_count
; i
++) {
3739 aco_opcode op
= opcodes
[i
];
3740 if (op
== aco_opcode::num_opcodes
)
3743 Temp data
= write_datas
[i
];
3745 unsigned second
= write_count
;
3746 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3747 for (second
= i
+ 1; second
< write_count
; second
++) {
3748 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3749 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3750 opcodes
[second
] = aco_opcode::num_opcodes
;
3756 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3757 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3759 unsigned inline_offset
= base_offset
+ offsets
[i
];
3760 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3761 Temp address_offset
= address
;
3762 if (inline_offset
> max_offset
) {
3763 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3764 inline_offset
= offsets
[i
];
3766 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3769 Temp second_data
= write_datas
[second
];
3770 inline_offset
/= data
.bytes();
3771 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3773 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3778 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3780 unsigned align
= 16;
3782 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3788 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3793 return aco_opcode::buffer_store_byte
;
3796 return aco_opcode::buffer_store_short
;
3798 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3800 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3803 return aco_opcode::buffer_store_dwordx3
;
3805 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3807 unreachable("Unexpected store size");
3808 return aco_opcode::num_opcodes
;
3811 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3812 Temp data
, unsigned writemask
, int swizzle_element_size
,
3813 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3815 unsigned write_count_with_skips
= 0;
3818 /* determine how to split the data */
3819 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3822 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3823 offsets
[write_count_with_skips
] = offset
;
3824 if (skips
[write_count_with_skips
]) {
3825 advance_write_mask(&todo
, offset
, bytes
);
3826 write_count_with_skips
++;
3830 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3831 * larger than swizzle_element_size */
3832 bytes
= MIN2(bytes
, swizzle_element_size
);
3834 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3836 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3837 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3840 /* dword or larger stores have to be dword-aligned */
3841 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3842 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3843 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3844 if (bytes
>= 4 && !dword_aligned
)
3845 bytes
= MIN2(bytes
, 2);
3847 advance_write_mask(&todo
, offset
, bytes
);
3848 write_count_with_skips
++;
3851 /* actually split data */
3852 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3855 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3858 write_datas
[*write_count
] = write_datas
[i
];
3859 offsets
[*write_count
] = offsets
[i
];
3864 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3865 unsigned split_cnt
= 0u, Temp dst
= Temp())
3867 Builder
bld(ctx
->program
, ctx
->block
);
3868 unsigned dword_size
= elem_size_bytes
/ 4;
3871 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3873 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3874 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3875 instr
->definitions
[0] = Definition(dst
);
3877 for (unsigned i
= 0; i
< cnt
; ++i
) {
3879 assert(arr
[i
].size() == dword_size
);
3880 allocated_vec
[i
] = arr
[i
];
3881 instr
->operands
[i
] = Operand(arr
[i
]);
3883 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3884 allocated_vec
[i
] = zero
;
3885 instr
->operands
[i
] = Operand(zero
);
3889 bld
.insert(std::move(instr
));
3892 emit_split_vector(ctx
, dst
, split_cnt
);
3894 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3899 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3901 if (const_offset
>= 4096) {
3902 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3903 const_offset
%= 4096u;
3906 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3907 else if (unlikely(voffset
.regClass() == s1
))
3908 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3909 else if (likely(voffset
.regClass() == v1
))
3910 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3912 unreachable("Unsupported register class of voffset");
3915 return const_offset
;
3918 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3919 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3922 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3923 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3925 Builder
bld(ctx
->program
, ctx
->block
);
3926 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3927 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3929 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3930 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3931 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3932 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3933 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3935 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3938 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3939 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3940 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3942 Builder
bld(ctx
->program
, ctx
->block
);
3943 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3945 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3947 unsigned write_count
= 0;
3948 Temp write_datas
[32];
3949 unsigned offsets
[32];
3950 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3951 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3953 for (unsigned i
= 0; i
< write_count
; i
++) {
3954 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3955 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3959 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3960 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3961 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3963 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3964 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3965 assert(!!stride
!= allow_combining
);
3967 Builder
bld(ctx
->program
, ctx
->block
);
3969 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3970 info
.component_stride
= allow_combining
? 0 : stride
;
3972 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3973 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3974 info
.align_offset
= 0;
3975 info
.soffset
= soffset
;
3976 info
.const_offset
= base_const_offset
;
3977 emit_mubuf_load(ctx
, bld
, &info
);
3980 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3982 Builder
bld(ctx
->program
, ctx
->block
);
3983 Temp offset
= base_offset
.first
;
3984 unsigned const_offset
= base_offset
.second
;
3986 if (!nir_src_is_const(*off_src
)) {
3987 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3990 /* Calculate indirect offset with stride */
3991 if (likely(indirect_offset_arg
.regClass() == v1
))
3992 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3993 else if (indirect_offset_arg
.regClass() == s1
)
3994 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3996 unreachable("Unsupported register class of indirect offset");
3998 /* Add to the supplied base offset */
3999 if (offset
.id() == 0)
4000 offset
= with_stride
;
4001 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4002 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4003 else if (offset
.size() == 1 && with_stride
.size() == 1)
4004 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4006 unreachable("Unsupported register class of indirect offset");
4008 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4009 const_offset
+= const_offset_arg
* stride
;
4012 return std::make_pair(offset
, const_offset
);
4015 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4017 Builder
bld(ctx
->program
, ctx
->block
);
4020 if (off1
.first
.id() && off2
.first
.id()) {
4021 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4022 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4023 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4024 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4026 unreachable("Unsupported register class of indirect offset");
4028 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4031 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4034 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4036 Builder
bld(ctx
->program
, ctx
->block
);
4037 unsigned const_offset
= offs
.second
* multiplier
;
4039 if (!offs
.first
.id())
4040 return std::make_pair(offs
.first
, const_offset
);
4042 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4043 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4044 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4046 return std::make_pair(offset
, const_offset
);
4049 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4051 Builder
bld(ctx
->program
, ctx
->block
);
4053 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4054 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4055 /* component is in bytes */
4056 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4058 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4059 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4060 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4063 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4065 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4068 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4070 Builder
bld(ctx
->program
, ctx
->block
);
4072 switch (ctx
->shader
->info
.stage
) {
4073 case MESA_SHADER_TESS_CTRL
:
4074 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4075 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4076 case MESA_SHADER_TESS_EVAL
:
4077 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4079 unreachable("Unsupported stage in get_tess_rel_patch_id");
4083 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4085 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4086 Builder
bld(ctx
->program
, ctx
->block
);
4088 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4089 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4091 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4093 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4094 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4096 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4097 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4098 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4100 return offset_mul(ctx
, offs
, 4u);
4103 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4105 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4106 Builder
bld(ctx
->program
, ctx
->block
);
4108 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4109 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4110 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4111 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4113 std::pair
<Temp
, unsigned> offs
= instr
4114 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4115 : std::make_pair(Temp(), 0u);
4117 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4118 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4123 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4124 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4126 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4127 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4129 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4130 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4136 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4138 Builder
bld(ctx
->program
, ctx
->block
);
4140 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4141 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4143 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4145 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4146 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4147 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4149 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4150 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4155 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4157 Builder
bld(ctx
->program
, ctx
->block
);
4159 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4160 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4161 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4162 unsigned attr_stride
= ctx
->tcs_num_patches
;
4164 std::pair
<Temp
, unsigned> offs
= instr
4165 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4166 : std::make_pair(Temp(), 0u);
4168 if (const_base_offset
)
4169 offs
.second
+= const_base_offset
* attr_stride
;
4171 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4172 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4173 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4178 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4180 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4185 unsigned drv_loc
= nir_intrinsic_base(instr
);
4186 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4188 if (!nir_src_is_const(*off_src
)) {
4194 uint64_t slot
= per_vertex
4195 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4196 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4197 return (((uint64_t) 1) << slot
) & mask
;
4200 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4202 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4203 unsigned component
= nir_intrinsic_component(instr
);
4204 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4206 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4207 if (off_instr
->type
!= nir_instr_type_load_const
)
4210 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4211 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4213 if (instr
->src
[0].ssa
->bit_size
== 64)
4214 write_mask
= widen_mask(write_mask
, 2);
4216 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4218 for (unsigned i
= 0; i
< 8; ++i
) {
4219 if (write_mask
& (1 << i
)) {
4220 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4221 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4229 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4231 /* Only TCS per-vertex inputs are supported by this function.
4232 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4234 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4237 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4238 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4239 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4240 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4241 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4242 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4247 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4248 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4249 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4254 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4256 Builder
bld(ctx
->program
, ctx
->block
);
4258 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4259 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4260 bool indirect_write
;
4261 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4262 if (temp_only_input
&& !indirect_write
)
4266 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4267 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4268 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4269 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4271 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4272 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4273 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4274 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4275 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4279 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4280 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4281 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4282 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4283 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4284 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4285 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4286 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4287 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4288 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4289 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4290 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4291 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4293 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4294 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4296 unreachable("Invalid LS or ES stage");
4299 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4300 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4301 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4305 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4310 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4311 return off
== ctx
->tcs_tess_lvl_out_loc
||
4312 off
== ctx
->tcs_tess_lvl_in_loc
;
4316 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4318 uint64_t mask
= per_vertex
4319 ? ctx
->program
->info
->tcs
.tes_inputs_read
4320 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4322 bool indirect_write
= false;
4323 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4324 return indirect_write
|| output_read_by_tes
;
4327 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4329 uint64_t mask
= per_vertex
4330 ? ctx
->shader
->info
.outputs_read
4331 : ctx
->shader
->info
.patch_outputs_read
;
4333 bool indirect_write
= false;
4334 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4335 return indirect_write
|| output_read
;
4338 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4340 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4341 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4343 Builder
bld(ctx
->program
, ctx
->block
);
4345 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4346 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4347 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4349 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4350 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4351 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4353 if (write_to_vmem
) {
4354 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4355 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4356 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4358 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4359 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4360 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4364 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4365 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4366 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4370 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4372 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4373 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4375 Builder
bld(ctx
->program
, ctx
->block
);
4377 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4378 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4379 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4380 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4382 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4385 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4387 if (ctx
->stage
== vertex_vs
||
4388 ctx
->stage
== tess_eval_vs
||
4389 ctx
->stage
== fragment_fs
||
4390 ctx
->stage
== ngg_vertex_gs
||
4391 ctx
->stage
== ngg_tess_eval_gs
||
4392 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4393 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4394 if (!stored_to_temps
) {
4395 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4396 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4397 fprintf(stderr
, "\n");
4400 } else if (ctx
->stage
== vertex_es
||
4401 ctx
->stage
== vertex_ls
||
4402 ctx
->stage
== tess_eval_es
||
4403 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4404 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4405 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4406 visit_store_ls_or_es_output(ctx
, instr
);
4407 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4408 visit_store_tcs_output(ctx
, instr
, false);
4410 unreachable("Shader stage not implemented");
4414 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4416 visit_load_tcs_output(ctx
, instr
, false);
4419 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4421 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4422 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4424 Builder
bld(ctx
->program
, ctx
->block
);
4425 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4426 if (ctx
->program
->has_16bank_lds
)
4427 interp_p1
.instr
->operands
[0].setLateKill(true);
4428 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4431 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4433 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4434 for (unsigned i
= 0; i
< num_components
; i
++)
4435 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4436 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4437 assert(num_components
== 4);
4438 Builder
bld(ctx
->program
, ctx
->block
);
4439 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4442 for (Operand
& op
: vec
->operands
)
4443 op
= op
.isUndefined() ? Operand(0u) : op
;
4445 vec
->definitions
[0] = Definition(dst
);
4446 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4447 emit_split_vector(ctx
, dst
, num_components
);
4451 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4453 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4454 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4455 unsigned idx
= nir_intrinsic_base(instr
);
4456 unsigned component
= nir_intrinsic_component(instr
);
4457 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4459 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4461 assert(offset
->u32
== 0);
4463 /* the lower 15bit of the prim_mask contain the offset into LDS
4464 * while the upper bits contain the number of prims */
4465 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4466 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4467 Builder
bld(ctx
->program
, ctx
->block
);
4468 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4469 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4470 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4471 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4472 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4475 if (instr
->dest
.ssa
.num_components
== 1) {
4476 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4478 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4479 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4481 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4482 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4483 vec
->operands
[i
] = Operand(tmp
);
4485 vec
->definitions
[0] = Definition(dst
);
4486 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4490 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4491 unsigned offset
, unsigned stride
, unsigned channels
)
4493 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4494 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4496 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4497 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4500 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4501 unsigned offset
, unsigned stride
, unsigned *channels
)
4503 if (!vtx_info
->chan_byte_size
) {
4504 *channels
= vtx_info
->num_channels
;
4505 return vtx_info
->chan_format
;
4508 unsigned num_channels
= *channels
;
4509 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4510 unsigned new_channels
= num_channels
+ 1;
4511 /* first, assume more loads is worse and try using a larger data format */
4512 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4514 /* don't make the attribute potentially out-of-bounds */
4515 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4519 if (new_channels
== 5) {
4520 /* then try decreasing load size (at the cost of more loads) */
4521 new_channels
= *channels
;
4522 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4526 if (new_channels
< *channels
)
4527 *channels
= new_channels
;
4528 num_channels
= new_channels
;
4531 switch (vtx_info
->chan_format
) {
4532 case V_008F0C_BUF_DATA_FORMAT_8
:
4533 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4534 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4535 case V_008F0C_BUF_DATA_FORMAT_16
:
4536 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4537 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4538 case V_008F0C_BUF_DATA_FORMAT_32
:
4539 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4540 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4542 unreachable("shouldn't reach here");
4543 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4546 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4547 * so we may need to fix it up. */
4548 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4550 Builder
bld(ctx
->program
, ctx
->block
);
4552 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4553 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4555 /* For the integer-like cases, do a natural sign extension.
4557 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4558 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4561 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4562 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4564 /* Convert back to the right type. */
4565 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4566 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4567 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4568 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4569 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4570 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4576 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4578 Builder
bld(ctx
->program
, ctx
->block
);
4579 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4580 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4582 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4583 if (off_instr
->type
!= nir_instr_type_load_const
) {
4584 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4585 nir_print_instr(off_instr
, stderr
);
4586 fprintf(stderr
, "\n");
4588 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4590 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4592 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4593 unsigned component
= nir_intrinsic_component(instr
);
4594 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4595 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4596 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4597 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4599 unsigned dfmt
= attrib_format
& 0xf;
4600 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4601 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4603 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4604 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4605 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4606 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4608 num_channels
= MAX2(num_channels
, 3);
4610 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4611 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4614 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4615 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4616 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4618 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4620 Temp divided
= bld
.tmp(v1
);
4621 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4622 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4624 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4627 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4630 index
= bld
.vadd32(bld
.def(v1
),
4631 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4632 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4635 Temp channels
[num_channels
];
4636 unsigned channel_start
= 0;
4637 bool direct_fetch
= false;
4639 /* skip unused channels at the start */
4640 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4641 channel_start
= ffs(mask
) - 1;
4642 for (unsigned i
= 0; i
< channel_start
; i
++)
4643 channels
[i
] = Temp(0, s1
);
4644 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4645 num_channels
= 3 - (ffs(mask
) - 1);
4649 while (channel_start
< num_channels
) {
4650 unsigned fetch_size
= num_channels
- channel_start
;
4651 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4652 bool expanded
= false;
4654 /* use MUBUF when possible to avoid possible alignment issues */
4655 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4656 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4657 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4658 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4659 vtx_info
->chan_byte_size
== 4;
4660 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4662 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4664 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4665 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4671 Temp fetch_index
= index
;
4672 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4673 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4674 fetch_offset
= fetch_offset
% attrib_stride
;
4677 Operand
soffset(0u);
4678 if (fetch_offset
>= 4096) {
4679 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4680 fetch_offset
%= 4096;
4684 switch (fetch_size
) {
4686 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4689 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4692 assert(ctx
->options
->chip_class
>= GFX7
||
4693 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4694 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4697 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4700 unreachable("Unimplemented load_input vector size");
4704 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4705 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4706 num_channels
<= 3)) {
4707 direct_fetch
= true;
4710 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4714 Instruction
*mubuf
= bld
.mubuf(opcode
,
4715 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4716 fetch_offset
, false, true).instr
;
4717 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4719 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4720 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4721 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4722 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4725 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4727 if (fetch_size
== 1) {
4728 channels
[channel_start
] = fetch_dst
;
4730 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4731 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4734 channel_start
+= fetch_size
;
4737 if (!direct_fetch
) {
4738 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4739 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4741 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4742 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4743 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4745 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4746 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4747 unsigned num_temp
= 0;
4748 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4749 unsigned idx
= i
+ component
;
4750 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4751 Temp channel
= channels
[swizzle
[idx
]];
4752 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4753 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4754 vec
->operands
[i
] = Operand(channel
);
4758 } else if (is_float
&& idx
== 3) {
4759 vec
->operands
[i
] = Operand(0x3f800000u
);
4760 } else if (!is_float
&& idx
== 3) {
4761 vec
->operands
[i
] = Operand(1u);
4763 vec
->operands
[i
] = Operand(0u);
4766 vec
->definitions
[0] = Definition(dst
);
4767 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4768 emit_split_vector(ctx
, dst
, dst
.size());
4770 if (num_temp
== dst
.size())
4771 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4773 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4774 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4775 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4776 if (off_instr
->type
!= nir_instr_type_load_const
||
4777 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4778 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4779 nir_print_instr(off_instr
, stderr
);
4780 fprintf(stderr
, "\n");
4783 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4784 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4786 assert(offset
->u32
== 0);
4788 /* the lower 15bit of the prim_mask contain the offset into LDS
4789 * while the upper bits contain the number of prims */
4790 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4791 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4792 Builder
bld(ctx
->program
, ctx
->block
);
4793 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4794 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4795 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4796 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4797 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4800 unsigned idx
= nir_intrinsic_base(instr
);
4801 unsigned component
= nir_intrinsic_component(instr
);
4802 unsigned vertex_id
= 2; /* P0 */
4804 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4805 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4806 switch (src0
->u32
) {
4808 vertex_id
= 2; /* P0 */
4811 vertex_id
= 0; /* P10 */
4814 vertex_id
= 1; /* P20 */
4817 unreachable("invalid vertex index");
4821 if (dst
.size() == 1) {
4822 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4824 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4825 for (unsigned i
= 0; i
< dst
.size(); i
++)
4826 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4827 vec
->definitions
[0] = Definition(dst
);
4828 bld
.insert(std::move(vec
));
4831 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4832 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4833 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4834 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4835 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4837 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4839 unreachable("Shader stage not implemented");
4843 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4845 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4847 Builder
bld(ctx
->program
, ctx
->block
);
4848 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4851 if (!nir_src_is_const(*vertex_src
)) {
4852 /* better code could be created, but this case probably doesn't happen
4853 * much in practice */
4854 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4855 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4858 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4859 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4861 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4863 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4866 if (vertex_offset
.id()) {
4867 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4868 Operand(i
), indirect_vertex
);
4869 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4871 vertex_offset
= elem
;
4875 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4876 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4878 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4879 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4880 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4881 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4882 Operand((vertex
% 2u) * 16u), Operand(16u));
4884 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4887 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4888 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4889 return offset_mul(ctx
, offs
, 4u);
4892 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4894 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4896 Builder
bld(ctx
->program
, ctx
->block
);
4897 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4898 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4900 if (ctx
->stage
== geometry_gs
) {
4901 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4902 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4903 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4904 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4905 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4906 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4907 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4909 unreachable("Unsupported GS stage.");
4913 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4915 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4917 Builder
bld(ctx
->program
, ctx
->block
);
4918 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4920 if (load_input_from_temps(ctx
, instr
, dst
))
4923 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4924 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4925 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4927 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4930 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4932 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4934 Builder
bld(ctx
->program
, ctx
->block
);
4936 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4937 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4940 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4941 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4943 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4946 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4948 switch (ctx
->shader
->info
.stage
) {
4949 case MESA_SHADER_GEOMETRY
:
4950 visit_load_gs_per_vertex_input(ctx
, instr
);
4952 case MESA_SHADER_TESS_CTRL
:
4953 visit_load_tcs_per_vertex_input(ctx
, instr
);
4955 case MESA_SHADER_TESS_EVAL
:
4956 visit_load_tes_per_vertex_input(ctx
, instr
);
4959 unreachable("Unimplemented shader stage");
4963 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4965 visit_load_tcs_output(ctx
, instr
, true);
4968 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4970 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4971 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4973 visit_store_tcs_output(ctx
, instr
, true);
4976 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4978 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4980 Builder
bld(ctx
->program
, ctx
->block
);
4981 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4983 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4984 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4987 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4988 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4989 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4990 tes_w
= Operand(tmp
);
4993 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4994 emit_split_vector(ctx
, tess_coord
, 3);
4997 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4999 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5000 Builder
bld(ctx
->program
, ctx
->block
);
5001 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5002 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5003 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5006 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5010 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5012 Builder
bld(ctx
->program
, ctx
->block
);
5013 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5014 if (!nir_dest_is_divergent(instr
->dest
))
5015 index
= bld
.as_uniform(index
);
5016 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5017 unsigned binding
= nir_intrinsic_binding(instr
);
5020 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5021 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5022 unsigned offset
= layout
->binding
[binding
].offset
;
5024 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5025 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5026 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5027 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5028 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5031 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5032 stride
= layout
->binding
[binding
].size
;
5035 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5036 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5038 if (nir_const_index
) {
5039 const_index
= const_index
* stride
;
5040 } else if (index
.type() == RegType::vgpr
) {
5041 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5042 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5044 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5048 if (nir_const_index
) {
5049 const_index
= const_index
+ offset
;
5050 } else if (index
.type() == RegType::vgpr
) {
5051 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5053 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5057 if (nir_const_index
&& const_index
== 0) {
5059 } else if (index
.type() == RegType::vgpr
) {
5060 index
= bld
.vadd32(bld
.def(v1
),
5061 nir_const_index
? Operand(const_index
) : Operand(index
),
5064 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5065 nir_const_index
? Operand(const_index
) : Operand(index
),
5069 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5072 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5073 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5074 bool glc
=false, bool readonly
=true)
5076 Builder
bld(ctx
->program
, ctx
->block
);
5078 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5080 offset
= bld
.as_uniform(offset
);
5082 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5084 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5085 info
.can_reorder
= readonly
;
5086 info
.align_mul
= align_mul
;
5087 info
.align_offset
= align_offset
;
5089 emit_smem_load(ctx
, bld
, &info
);
5091 emit_mubuf_load(ctx
, bld
, &info
);
5094 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5096 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5097 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5099 Builder
bld(ctx
->program
, ctx
->block
);
5101 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5102 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5103 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5104 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5106 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5107 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5108 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5109 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5110 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5111 if (ctx
->options
->chip_class
>= GFX10
) {
5112 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5113 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5114 S_008F0C_RESOURCE_LEVEL(1);
5116 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5117 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5119 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5120 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5121 Operand(0xFFFFFFFFu
),
5122 Operand(desc_type
));
5123 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5124 rsrc
, upper_dwords
);
5126 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5127 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5129 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5130 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5131 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5134 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5136 Builder
bld(ctx
->program
, ctx
->block
);
5137 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5138 unsigned offset
= nir_intrinsic_base(instr
);
5139 unsigned count
= instr
->dest
.ssa
.num_components
;
5140 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5142 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5143 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5144 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5145 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5146 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5147 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5148 for (unsigned i
= 0; i
< count
; ++i
) {
5149 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5150 vec
->operands
[i
] = Operand
{elems
[i
]};
5152 vec
->definitions
[0] = Definition(dst
);
5153 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5154 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5159 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5160 if (offset
!= 0) // TODO check if index != 0 as well
5161 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5162 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5165 bool aligned
= true;
5167 if (instr
->dest
.ssa
.bit_size
== 8) {
5168 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5169 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5171 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5172 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5173 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5175 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5180 switch (vec
.size()) {
5182 op
= aco_opcode::s_load_dword
;
5185 op
= aco_opcode::s_load_dwordx2
;
5191 op
= aco_opcode::s_load_dwordx4
;
5197 op
= aco_opcode::s_load_dwordx8
;
5200 unreachable("unimplemented or forbidden load_push_constant.");
5203 bld
.smem(op
, Definition(vec
), ptr
, index
);
5206 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5207 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5212 emit_split_vector(ctx
, vec
, 4);
5213 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5214 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5215 emit_extract_vector(ctx
, vec
, 0, rc
),
5216 emit_extract_vector(ctx
, vec
, 1, rc
),
5217 emit_extract_vector(ctx
, vec
, 2, rc
));
5220 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5223 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5225 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5227 Builder
bld(ctx
->program
, ctx
->block
);
5229 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5230 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5231 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5232 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5233 if (ctx
->options
->chip_class
>= GFX10
) {
5234 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5235 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5236 S_008F0C_RESOURCE_LEVEL(1);
5238 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5239 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5242 unsigned base
= nir_intrinsic_base(instr
);
5243 unsigned range
= nir_intrinsic_range(instr
);
5245 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5246 if (base
&& offset
.type() == RegType::sgpr
)
5247 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5248 else if (base
&& offset
.type() == RegType::vgpr
)
5249 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5251 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5252 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5253 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5254 Operand(desc_type
));
5255 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5256 // TODO: get alignment information for subdword constants
5257 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5260 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5262 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5263 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5265 ctx
->program
->needs_exact
= true;
5267 // TODO: optimize uniform conditions
5268 Builder
bld(ctx
->program
, ctx
->block
);
5269 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5270 assert(src
.regClass() == bld
.lm
);
5271 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5272 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5273 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5277 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5279 Builder
bld(ctx
->program
, ctx
->block
);
5281 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5282 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5284 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5285 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5287 if (ctx
->block
->loop_nest_depth
&&
5288 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5289 /* we handle discards the same way as jump instructions */
5290 append_logical_end(ctx
->block
);
5292 /* in loops, discard behaves like break */
5293 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5294 ctx
->block
->kind
|= block_kind_discard
;
5297 /* uniform discard - loop ends here */
5298 assert(nir_instr_is_last(&instr
->instr
));
5299 ctx
->block
->kind
|= block_kind_uniform
;
5300 ctx
->cf_info
.has_branch
= true;
5301 bld
.branch(aco_opcode::p_branch
);
5302 add_linear_edge(ctx
->block
->index
, linear_target
);
5306 /* we add a break right behind the discard() instructions */
5307 ctx
->block
->kind
|= block_kind_break
;
5308 unsigned idx
= ctx
->block
->index
;
5310 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5311 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5313 /* remove critical edges from linear CFG */
5314 bld
.branch(aco_opcode::p_branch
);
5315 Block
* break_block
= ctx
->program
->create_and_insert_block();
5316 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5317 break_block
->kind
|= block_kind_uniform
;
5318 add_linear_edge(idx
, break_block
);
5319 add_linear_edge(break_block
->index
, linear_target
);
5320 bld
.reset(break_block
);
5321 bld
.branch(aco_opcode::p_branch
);
5323 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5324 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5325 add_linear_edge(idx
, continue_block
);
5326 append_logical_start(continue_block
);
5327 ctx
->block
= continue_block
;
5332 /* it can currently happen that NIR doesn't remove the unreachable code */
5333 if (!nir_instr_is_last(&instr
->instr
)) {
5334 ctx
->program
->needs_exact
= true;
5335 /* save exec somewhere temporarily so that it doesn't get
5336 * overwritten before the discard from outer exec masks */
5337 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5338 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5339 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5343 /* This condition is incorrect for uniformly branched discards in a loop
5344 * predicated by a divergent condition, but the above code catches that case
5345 * and the discard would end up turning into a discard_if.
5355 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5356 /* program just ends here */
5357 ctx
->block
->kind
|= block_kind_uniform
;
5358 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5359 0 /* enabled mask */, 9 /* dest */,
5360 false /* compressed */, true/* done */, true /* valid mask */);
5361 bld
.sopp(aco_opcode::s_endpgm
);
5362 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5364 ctx
->block
->kind
|= block_kind_discard
;
5365 /* branch and linear edge is added by visit_if() */
5369 enum aco_descriptor_type
{
5380 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5381 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5383 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5384 return dim
== ac_image_cube
||
5385 dim
== ac_image_1darray
||
5386 dim
== ac_image_2darray
||
5387 dim
== ac_image_2darraymsaa
;
5390 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5391 enum aco_descriptor_type desc_type
,
5392 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5394 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5395 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5396 if (it != ctx->tex_desc.end())
5399 Temp index
= Temp();
5400 bool index_set
= false;
5401 unsigned constant_index
= 0;
5402 unsigned descriptor_set
;
5403 unsigned base_index
;
5404 Builder
bld(ctx
->program
, ctx
->block
);
5407 assert(tex_instr
&& !image
);
5409 base_index
= tex_instr
->sampler_index
;
5411 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5412 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5416 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5417 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5419 constant_index
+= array_size
* const_value
->u32
;
5421 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5422 if (indirect
.type() == RegType::vgpr
)
5423 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5425 if (array_size
!= 1)
5426 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5432 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5436 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5438 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5439 base_index
= deref_instr
->var
->data
.binding
;
5442 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5443 list
= convert_pointer_to_64_bit(ctx
, list
);
5445 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5446 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5447 unsigned offset
= binding
->offset
;
5448 unsigned stride
= binding
->size
;
5452 assert(base_index
< layout
->binding_count
);
5454 switch (desc_type
) {
5455 case ACO_DESC_IMAGE
:
5457 opcode
= aco_opcode::s_load_dwordx8
;
5459 case ACO_DESC_FMASK
:
5461 opcode
= aco_opcode::s_load_dwordx8
;
5464 case ACO_DESC_SAMPLER
:
5466 opcode
= aco_opcode::s_load_dwordx4
;
5467 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5468 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5470 case ACO_DESC_BUFFER
:
5472 opcode
= aco_opcode::s_load_dwordx4
;
5474 case ACO_DESC_PLANE_0
:
5475 case ACO_DESC_PLANE_1
:
5477 opcode
= aco_opcode::s_load_dwordx8
;
5478 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5480 case ACO_DESC_PLANE_2
:
5482 opcode
= aco_opcode::s_load_dwordx4
;
5486 unreachable("invalid desc_type\n");
5489 offset
+= constant_index
* stride
;
5491 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5492 (!index_set
|| binding
->immutable_samplers_equal
)) {
5493 if (binding
->immutable_samplers_equal
)
5496 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5497 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5498 Operand(samplers
[constant_index
* 4 + 0]),
5499 Operand(samplers
[constant_index
* 4 + 1]),
5500 Operand(samplers
[constant_index
* 4 + 2]),
5501 Operand(samplers
[constant_index
* 4 + 3]));
5506 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5508 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5509 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5512 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5514 if (desc_type
== ACO_DESC_PLANE_2
) {
5516 for (unsigned i
= 0; i
< 8; i
++)
5517 components
[i
] = bld
.tmp(s1
);
5518 bld
.pseudo(aco_opcode::p_split_vector
,
5519 Definition(components
[0]),
5520 Definition(components
[1]),
5521 Definition(components
[2]),
5522 Definition(components
[3]),
5525 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5526 bld
.pseudo(aco_opcode::p_split_vector
,
5527 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5528 Definition(components
[4]),
5529 Definition(components
[5]),
5530 Definition(components
[6]),
5531 Definition(components
[7]),
5534 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5535 components
[0], components
[1], components
[2], components
[3],
5536 components
[4], components
[5], components
[6], components
[7]);
5542 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5545 case GLSL_SAMPLER_DIM_BUF
:
5547 case GLSL_SAMPLER_DIM_1D
:
5548 return array
? 2 : 1;
5549 case GLSL_SAMPLER_DIM_2D
:
5550 return array
? 3 : 2;
5551 case GLSL_SAMPLER_DIM_MS
:
5552 return array
? 4 : 3;
5553 case GLSL_SAMPLER_DIM_3D
:
5554 case GLSL_SAMPLER_DIM_CUBE
:
5556 case GLSL_SAMPLER_DIM_RECT
:
5557 case GLSL_SAMPLER_DIM_SUBPASS
:
5559 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5568 /* Adjust the sample index according to FMASK.
5570 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5571 * which is the identity mapping. Each nibble says which physical sample
5572 * should be fetched to get that sample.
5574 * For example, 0x11111100 means there are only 2 samples stored and
5575 * the second sample covers 3/4 of the pixel. When reading samples 0
5576 * and 1, return physical sample 0 (determined by the first two 0s
5577 * in FMASK), otherwise return physical sample 1.
5579 * The sample index should be adjusted as follows:
5580 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5582 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5584 Builder
bld(ctx
->program
, ctx
->block
);
5585 Temp fmask
= bld
.tmp(v1
);
5586 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5587 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5590 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5591 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5592 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5593 load
->operands
[0] = Operand(fmask_desc_ptr
);
5594 load
->operands
[1] = Operand(s4
); /* no sampler */
5595 load
->operands
[2] = Operand(coord
);
5596 load
->definitions
[0] = Definition(fmask
);
5603 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5604 ctx
->block
->instructions
.emplace_back(std::move(load
));
5606 Operand sample_index4
;
5607 if (sample_index
.isConstant()) {
5608 if (sample_index
.constantValue() < 16) {
5609 sample_index4
= Operand(sample_index
.constantValue() << 2);
5611 sample_index4
= Operand(0u);
5613 } else if (sample_index
.regClass() == s1
) {
5614 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5616 assert(sample_index
.regClass() == v1
);
5617 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5621 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5622 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5623 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5624 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5626 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5628 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5629 * resource descriptor is 0 (invalid),
5631 Temp compare
= bld
.tmp(bld
.lm
);
5632 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5633 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5635 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5637 /* Replace the MSAA sample index. */
5638 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5641 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5644 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5645 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5646 bool is_array
= glsl_sampler_type_is_array(type
);
5647 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5648 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5649 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5650 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5651 int count
= image_type_to_components_count(dim
, is_array
);
5652 std::vector
<Temp
> coords(count
);
5653 Builder
bld(ctx
->program
, ctx
->block
);
5657 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5658 /* get sample index */
5659 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5660 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5661 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5662 std::vector
<Temp
> fmask_load_address
;
5663 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5664 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5666 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5667 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5669 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5674 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5675 coords
.resize(coords
.size() + 1);
5676 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5678 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5680 for (int i
= 0; i
< count
; i
++)
5681 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5684 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5685 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5686 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5687 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5690 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5693 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5694 for (unsigned i
= 0; i
< coords
.size(); i
++)
5695 vec
->operands
[i
] = Operand(coords
[i
]);
5696 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5697 vec
->definitions
[0] = Definition(res
);
5698 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5703 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5705 Builder
bld(ctx
->program
, ctx
->block
);
5706 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5707 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5708 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5709 bool is_array
= glsl_sampler_type_is_array(type
);
5710 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5712 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5713 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5714 unsigned num_channels
= util_last_bit(mask
);
5715 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5716 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5719 switch (num_channels
) {
5721 opcode
= aco_opcode::buffer_load_format_x
;
5724 opcode
= aco_opcode::buffer_load_format_xy
;
5727 opcode
= aco_opcode::buffer_load_format_xyz
;
5730 opcode
= aco_opcode::buffer_load_format_xyzw
;
5733 unreachable(">4 channel buffer image load");
5735 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5736 load
->operands
[0] = Operand(rsrc
);
5737 load
->operands
[1] = Operand(vindex
);
5738 load
->operands
[2] = Operand((uint32_t) 0);
5740 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5743 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5744 load
->definitions
[0] = Definition(tmp
);
5746 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5747 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5748 load
->barrier
= barrier_image
;
5749 ctx
->block
->instructions
.emplace_back(std::move(load
));
5751 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5755 Temp coords
= get_image_coords(ctx
, instr
, type
);
5756 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5758 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5759 unsigned num_components
= util_bitcount(dmask
);
5761 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5764 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5766 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5767 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5769 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5770 load
->operands
[0] = Operand(resource
);
5771 load
->operands
[1] = Operand(s4
); /* no sampler */
5772 load
->operands
[2] = Operand(coords
);
5773 load
->definitions
[0] = Definition(tmp
);
5774 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5775 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5776 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5777 load
->dmask
= dmask
;
5779 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5780 load
->barrier
= barrier_image
;
5781 ctx
->block
->instructions
.emplace_back(std::move(load
));
5783 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5787 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5789 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5790 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5791 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5792 bool is_array
= glsl_sampler_type_is_array(type
);
5793 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5795 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5797 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5798 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5799 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5801 switch (data
.size()) {
5803 opcode
= aco_opcode::buffer_store_format_x
;
5806 opcode
= aco_opcode::buffer_store_format_xy
;
5809 opcode
= aco_opcode::buffer_store_format_xyz
;
5812 opcode
= aco_opcode::buffer_store_format_xyzw
;
5815 unreachable(">4 channel buffer image store");
5817 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5818 store
->operands
[0] = Operand(rsrc
);
5819 store
->operands
[1] = Operand(vindex
);
5820 store
->operands
[2] = Operand((uint32_t) 0);
5821 store
->operands
[3] = Operand(data
);
5822 store
->idxen
= true;
5825 store
->disable_wqm
= true;
5826 store
->barrier
= barrier_image
;
5827 ctx
->program
->needs_exact
= true;
5828 ctx
->block
->instructions
.emplace_back(std::move(store
));
5832 assert(data
.type() == RegType::vgpr
);
5833 Temp coords
= get_image_coords(ctx
, instr
, type
);
5834 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5836 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5837 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5839 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5840 store
->operands
[0] = Operand(resource
);
5841 store
->operands
[1] = Operand(data
);
5842 store
->operands
[2] = Operand(coords
);
5845 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5846 store
->dmask
= (1 << data
.size()) - 1;
5848 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5849 store
->disable_wqm
= true;
5850 store
->barrier
= barrier_image
;
5851 ctx
->program
->needs_exact
= true;
5852 ctx
->block
->instructions
.emplace_back(std::move(store
));
5856 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5858 /* return the previous value if dest is ever used */
5859 bool return_previous
= false;
5860 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5861 return_previous
= true;
5864 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5865 return_previous
= true;
5869 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5870 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5871 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5872 bool is_array
= glsl_sampler_type_is_array(type
);
5873 Builder
bld(ctx
->program
, ctx
->block
);
5875 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5876 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5878 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5879 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5881 aco_opcode buf_op
, image_op
;
5882 switch (instr
->intrinsic
) {
5883 case nir_intrinsic_image_deref_atomic_add
:
5884 buf_op
= aco_opcode::buffer_atomic_add
;
5885 image_op
= aco_opcode::image_atomic_add
;
5887 case nir_intrinsic_image_deref_atomic_umin
:
5888 buf_op
= aco_opcode::buffer_atomic_umin
;
5889 image_op
= aco_opcode::image_atomic_umin
;
5891 case nir_intrinsic_image_deref_atomic_imin
:
5892 buf_op
= aco_opcode::buffer_atomic_smin
;
5893 image_op
= aco_opcode::image_atomic_smin
;
5895 case nir_intrinsic_image_deref_atomic_umax
:
5896 buf_op
= aco_opcode::buffer_atomic_umax
;
5897 image_op
= aco_opcode::image_atomic_umax
;
5899 case nir_intrinsic_image_deref_atomic_imax
:
5900 buf_op
= aco_opcode::buffer_atomic_smax
;
5901 image_op
= aco_opcode::image_atomic_smax
;
5903 case nir_intrinsic_image_deref_atomic_and
:
5904 buf_op
= aco_opcode::buffer_atomic_and
;
5905 image_op
= aco_opcode::image_atomic_and
;
5907 case nir_intrinsic_image_deref_atomic_or
:
5908 buf_op
= aco_opcode::buffer_atomic_or
;
5909 image_op
= aco_opcode::image_atomic_or
;
5911 case nir_intrinsic_image_deref_atomic_xor
:
5912 buf_op
= aco_opcode::buffer_atomic_xor
;
5913 image_op
= aco_opcode::image_atomic_xor
;
5915 case nir_intrinsic_image_deref_atomic_exchange
:
5916 buf_op
= aco_opcode::buffer_atomic_swap
;
5917 image_op
= aco_opcode::image_atomic_swap
;
5919 case nir_intrinsic_image_deref_atomic_comp_swap
:
5920 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5921 image_op
= aco_opcode::image_atomic_cmpswap
;
5924 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5927 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5929 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5930 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5931 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5932 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5933 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5934 mubuf
->operands
[0] = Operand(resource
);
5935 mubuf
->operands
[1] = Operand(vindex
);
5936 mubuf
->operands
[2] = Operand((uint32_t)0);
5937 mubuf
->operands
[3] = Operand(data
);
5938 if (return_previous
)
5939 mubuf
->definitions
[0] = Definition(dst
);
5941 mubuf
->idxen
= true;
5942 mubuf
->glc
= return_previous
;
5943 mubuf
->dlc
= false; /* Not needed for atomics */
5944 mubuf
->disable_wqm
= true;
5945 mubuf
->barrier
= barrier_image
;
5946 ctx
->program
->needs_exact
= true;
5947 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5951 Temp coords
= get_image_coords(ctx
, instr
, type
);
5952 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5953 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5954 mimg
->operands
[0] = Operand(resource
);
5955 mimg
->operands
[1] = Operand(data
);
5956 mimg
->operands
[2] = Operand(coords
);
5957 if (return_previous
)
5958 mimg
->definitions
[0] = Definition(dst
);
5959 mimg
->glc
= return_previous
;
5960 mimg
->dlc
= false; /* Not needed for atomics */
5961 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5962 mimg
->dmask
= (1 << data
.size()) - 1;
5964 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5965 mimg
->disable_wqm
= true;
5966 mimg
->barrier
= barrier_image
;
5967 ctx
->program
->needs_exact
= true;
5968 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5972 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5974 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5975 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5976 Builder
bld(ctx
->program
, ctx
->block
);
5978 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5980 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5981 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5983 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5984 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5986 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5987 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5989 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5990 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5991 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5992 if (dst
.type() == RegType::vgpr
)
5993 bld
.copy(Definition(dst
), shr_dst
);
5995 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5997 emit_extract_vector(ctx
, desc
, 2, dst
);
6001 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6003 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6004 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6005 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6006 bool is_array
= glsl_sampler_type_is_array(type
);
6007 Builder
bld(ctx
->program
, ctx
->block
);
6009 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6010 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6011 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6015 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6018 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6020 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6022 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6023 mimg
->operands
[0] = Operand(resource
);
6024 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6025 mimg
->operands
[2] = Operand(lod
);
6026 uint8_t& dmask
= mimg
->dmask
;
6027 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6028 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6029 mimg
->da
= glsl_sampler_type_is_array(type
);
6030 mimg
->can_reorder
= true;
6031 Definition
& def
= mimg
->definitions
[0];
6032 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6034 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6035 glsl_sampler_type_is_array(type
)) {
6037 assert(instr
->dest
.ssa
.num_components
== 3);
6038 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6039 def
= Definition(tmp
);
6040 emit_split_vector(ctx
, tmp
, 3);
6042 /* divide 3rd value by 6 by multiplying with magic number */
6043 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6044 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6046 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6047 emit_extract_vector(ctx
, tmp
, 0, v1
),
6048 emit_extract_vector(ctx
, tmp
, 1, v1
),
6051 } else if (ctx
->options
->chip_class
== GFX9
&&
6052 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6053 glsl_sampler_type_is_array(type
)) {
6054 assert(instr
->dest
.ssa
.num_components
== 2);
6055 def
= Definition(dst
);
6058 def
= Definition(dst
);
6061 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6064 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6066 Builder
bld(ctx
->program
, ctx
->block
);
6067 unsigned num_components
= instr
->num_components
;
6069 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6070 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6071 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6073 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6074 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6075 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6076 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6079 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6081 Builder
bld(ctx
->program
, ctx
->block
);
6082 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6083 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6084 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6085 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6087 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6088 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6090 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6091 ctx
->options
->chip_class
>= GFX8
&&
6092 elem_size_bytes
>= 4;
6094 offset
= bld
.as_uniform(offset
);
6095 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6097 unsigned write_count
= 0;
6098 Temp write_datas
[32];
6099 unsigned offsets
[32];
6100 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6101 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6103 for (unsigned i
= 0; i
< write_count
; i
++) {
6104 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6105 if (smem
&& ctx
->stage
== fragment_fs
)
6106 op
= aco_opcode::p_fs_buffer_store_smem
;
6109 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6110 store
->operands
[0] = Operand(rsrc
);
6112 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6113 offset
, Operand(offsets
[i
]));
6114 store
->operands
[1] = Operand(off
);
6116 store
->operands
[1] = Operand(offset
);
6118 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6119 store
->operands
[1].setFixed(m0
);
6120 store
->operands
[2] = Operand(write_datas
[i
]);
6121 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6123 store
->disable_wqm
= true;
6124 store
->barrier
= barrier_buffer
;
6125 ctx
->block
->instructions
.emplace_back(std::move(store
));
6126 ctx
->program
->wb_smem_l1_on_end
= true;
6127 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6128 ctx
->block
->kind
|= block_kind_needs_lowering
;
6129 ctx
->program
->needs_exact
= true;
6132 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6133 store
->operands
[0] = Operand(rsrc
);
6134 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6135 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6136 store
->operands
[3] = Operand(write_datas
[i
]);
6137 store
->offset
= offsets
[i
];
6138 store
->offen
= (offset
.type() == RegType::vgpr
);
6139 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6141 store
->disable_wqm
= true;
6142 store
->barrier
= barrier_buffer
;
6143 ctx
->program
->needs_exact
= true;
6144 ctx
->block
->instructions
.emplace_back(std::move(store
));
6149 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6151 /* return the previous value if dest is ever used */
6152 bool return_previous
= false;
6153 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6154 return_previous
= true;
6157 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6158 return_previous
= true;
6162 Builder
bld(ctx
->program
, ctx
->block
);
6163 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6165 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6166 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6167 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6169 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6170 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6171 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6173 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6175 aco_opcode op32
, op64
;
6176 switch (instr
->intrinsic
) {
6177 case nir_intrinsic_ssbo_atomic_add
:
6178 op32
= aco_opcode::buffer_atomic_add
;
6179 op64
= aco_opcode::buffer_atomic_add_x2
;
6181 case nir_intrinsic_ssbo_atomic_imin
:
6182 op32
= aco_opcode::buffer_atomic_smin
;
6183 op64
= aco_opcode::buffer_atomic_smin_x2
;
6185 case nir_intrinsic_ssbo_atomic_umin
:
6186 op32
= aco_opcode::buffer_atomic_umin
;
6187 op64
= aco_opcode::buffer_atomic_umin_x2
;
6189 case nir_intrinsic_ssbo_atomic_imax
:
6190 op32
= aco_opcode::buffer_atomic_smax
;
6191 op64
= aco_opcode::buffer_atomic_smax_x2
;
6193 case nir_intrinsic_ssbo_atomic_umax
:
6194 op32
= aco_opcode::buffer_atomic_umax
;
6195 op64
= aco_opcode::buffer_atomic_umax_x2
;
6197 case nir_intrinsic_ssbo_atomic_and
:
6198 op32
= aco_opcode::buffer_atomic_and
;
6199 op64
= aco_opcode::buffer_atomic_and_x2
;
6201 case nir_intrinsic_ssbo_atomic_or
:
6202 op32
= aco_opcode::buffer_atomic_or
;
6203 op64
= aco_opcode::buffer_atomic_or_x2
;
6205 case nir_intrinsic_ssbo_atomic_xor
:
6206 op32
= aco_opcode::buffer_atomic_xor
;
6207 op64
= aco_opcode::buffer_atomic_xor_x2
;
6209 case nir_intrinsic_ssbo_atomic_exchange
:
6210 op32
= aco_opcode::buffer_atomic_swap
;
6211 op64
= aco_opcode::buffer_atomic_swap_x2
;
6213 case nir_intrinsic_ssbo_atomic_comp_swap
:
6214 op32
= aco_opcode::buffer_atomic_cmpswap
;
6215 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6218 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6220 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6221 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6222 mubuf
->operands
[0] = Operand(rsrc
);
6223 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6224 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6225 mubuf
->operands
[3] = Operand(data
);
6226 if (return_previous
)
6227 mubuf
->definitions
[0] = Definition(dst
);
6229 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6230 mubuf
->glc
= return_previous
;
6231 mubuf
->dlc
= false; /* Not needed for atomics */
6232 mubuf
->disable_wqm
= true;
6233 mubuf
->barrier
= barrier_buffer
;
6234 ctx
->program
->needs_exact
= true;
6235 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6238 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6240 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6241 Builder
bld(ctx
->program
, ctx
->block
);
6242 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6243 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6246 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6248 Builder
bld(ctx
->program
, ctx
->block
);
6249 unsigned num_components
= instr
->num_components
;
6250 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6252 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6253 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6254 num_components
, component_size
};
6255 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6256 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6257 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6258 info
.barrier
= barrier_buffer
;
6259 info
.can_reorder
= false;
6260 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6261 * it's safe to use SMEM */
6262 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6263 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6264 emit_global_load(ctx
, bld
, &info
);
6266 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6267 emit_smem_load(ctx
, bld
, &info
);
6271 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6273 Builder
bld(ctx
->program
, ctx
->block
);
6274 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6275 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6277 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6278 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6279 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6281 if (ctx
->options
->chip_class
>= GFX7
)
6282 addr
= as_vgpr(ctx
, addr
);
6284 unsigned write_count
= 0;
6285 Temp write_datas
[32];
6286 unsigned offsets
[32];
6287 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6288 16, &write_count
, write_datas
, offsets
);
6290 for (unsigned i
= 0; i
< write_count
; i
++) {
6291 if (ctx
->options
->chip_class
>= GFX7
) {
6292 unsigned offset
= offsets
[i
];
6293 Temp store_addr
= addr
;
6294 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6295 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6296 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6297 Temp carry
= bld
.tmp(bld
.lm
);
6298 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6300 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6301 Operand(offset
), addr0
);
6302 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6304 carry
).def(1).setHint(vcc
);
6306 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6311 bool global
= ctx
->options
->chip_class
>= GFX9
;
6313 switch (write_datas
[i
].bytes()) {
6315 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6318 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6321 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6324 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6327 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6330 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6333 unreachable("store_global not implemented for this size.");
6336 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6337 flat
->operands
[0] = Operand(store_addr
);
6338 flat
->operands
[1] = Operand(s1
);
6339 flat
->operands
[2] = Operand(write_datas
[i
]);
6342 flat
->offset
= offset
;
6343 flat
->disable_wqm
= true;
6344 flat
->barrier
= barrier_buffer
;
6345 ctx
->program
->needs_exact
= true;
6346 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6348 assert(ctx
->options
->chip_class
== GFX6
);
6350 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6352 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6354 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6355 mubuf
->operands
[0] = Operand(rsrc
);
6356 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6357 mubuf
->operands
[2] = Operand(0u);
6358 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6361 mubuf
->offset
= offsets
[i
];
6362 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6363 mubuf
->disable_wqm
= true;
6364 mubuf
->barrier
= barrier_buffer
;
6365 ctx
->program
->needs_exact
= true;
6366 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6371 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6373 /* return the previous value if dest is ever used */
6374 bool return_previous
= false;
6375 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6376 return_previous
= true;
6379 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6380 return_previous
= true;
6384 Builder
bld(ctx
->program
, ctx
->block
);
6385 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6386 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6388 if (ctx
->options
->chip_class
>= GFX7
)
6389 addr
= as_vgpr(ctx
, addr
);
6391 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6392 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6393 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6395 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6397 aco_opcode op32
, op64
;
6399 if (ctx
->options
->chip_class
>= GFX7
) {
6400 bool global
= ctx
->options
->chip_class
>= GFX9
;
6401 switch (instr
->intrinsic
) {
6402 case nir_intrinsic_global_atomic_add
:
6403 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6404 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6406 case nir_intrinsic_global_atomic_imin
:
6407 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6408 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6410 case nir_intrinsic_global_atomic_umin
:
6411 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6412 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6414 case nir_intrinsic_global_atomic_imax
:
6415 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6416 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6418 case nir_intrinsic_global_atomic_umax
:
6419 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6420 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6422 case nir_intrinsic_global_atomic_and
:
6423 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6424 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6426 case nir_intrinsic_global_atomic_or
:
6427 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6428 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6430 case nir_intrinsic_global_atomic_xor
:
6431 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6432 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6434 case nir_intrinsic_global_atomic_exchange
:
6435 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6436 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6438 case nir_intrinsic_global_atomic_comp_swap
:
6439 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6440 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6443 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6446 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6447 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6448 flat
->operands
[0] = Operand(addr
);
6449 flat
->operands
[1] = Operand(s1
);
6450 flat
->operands
[2] = Operand(data
);
6451 if (return_previous
)
6452 flat
->definitions
[0] = Definition(dst
);
6453 flat
->glc
= return_previous
;
6454 flat
->dlc
= false; /* Not needed for atomics */
6456 flat
->disable_wqm
= true;
6457 flat
->barrier
= barrier_buffer
;
6458 ctx
->program
->needs_exact
= true;
6459 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6461 assert(ctx
->options
->chip_class
== GFX6
);
6463 switch (instr
->intrinsic
) {
6464 case nir_intrinsic_global_atomic_add
:
6465 op32
= aco_opcode::buffer_atomic_add
;
6466 op64
= aco_opcode::buffer_atomic_add_x2
;
6468 case nir_intrinsic_global_atomic_imin
:
6469 op32
= aco_opcode::buffer_atomic_smin
;
6470 op64
= aco_opcode::buffer_atomic_smin_x2
;
6472 case nir_intrinsic_global_atomic_umin
:
6473 op32
= aco_opcode::buffer_atomic_umin
;
6474 op64
= aco_opcode::buffer_atomic_umin_x2
;
6476 case nir_intrinsic_global_atomic_imax
:
6477 op32
= aco_opcode::buffer_atomic_smax
;
6478 op64
= aco_opcode::buffer_atomic_smax_x2
;
6480 case nir_intrinsic_global_atomic_umax
:
6481 op32
= aco_opcode::buffer_atomic_umax
;
6482 op64
= aco_opcode::buffer_atomic_umax_x2
;
6484 case nir_intrinsic_global_atomic_and
:
6485 op32
= aco_opcode::buffer_atomic_and
;
6486 op64
= aco_opcode::buffer_atomic_and_x2
;
6488 case nir_intrinsic_global_atomic_or
:
6489 op32
= aco_opcode::buffer_atomic_or
;
6490 op64
= aco_opcode::buffer_atomic_or_x2
;
6492 case nir_intrinsic_global_atomic_xor
:
6493 op32
= aco_opcode::buffer_atomic_xor
;
6494 op64
= aco_opcode::buffer_atomic_xor_x2
;
6496 case nir_intrinsic_global_atomic_exchange
:
6497 op32
= aco_opcode::buffer_atomic_swap
;
6498 op64
= aco_opcode::buffer_atomic_swap_x2
;
6500 case nir_intrinsic_global_atomic_comp_swap
:
6501 op32
= aco_opcode::buffer_atomic_cmpswap
;
6502 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6505 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6508 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6510 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6512 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6513 mubuf
->operands
[0] = Operand(rsrc
);
6514 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6515 mubuf
->operands
[2] = Operand(0u);
6516 mubuf
->operands
[3] = Operand(data
);
6517 if (return_previous
)
6518 mubuf
->definitions
[0] = Definition(dst
);
6519 mubuf
->glc
= return_previous
;
6522 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6523 mubuf
->disable_wqm
= true;
6524 mubuf
->barrier
= barrier_buffer
;
6525 ctx
->program
->needs_exact
= true;
6526 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6530 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6531 Builder
bld(ctx
->program
, ctx
->block
);
6532 switch(instr
->intrinsic
) {
6533 case nir_intrinsic_group_memory_barrier
:
6534 case nir_intrinsic_memory_barrier
:
6535 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6537 case nir_intrinsic_memory_barrier_buffer
:
6538 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6540 case nir_intrinsic_memory_barrier_image
:
6541 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6543 case nir_intrinsic_memory_barrier_tcs_patch
:
6544 case nir_intrinsic_memory_barrier_shared
:
6545 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6548 unreachable("Unimplemented memory barrier intrinsic");
6553 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6555 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6556 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6557 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6558 Builder
bld(ctx
->program
, ctx
->block
);
6560 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6561 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6562 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6565 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6567 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6568 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6569 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6570 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6572 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6573 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6576 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6578 unsigned offset
= nir_intrinsic_base(instr
);
6579 Builder
bld(ctx
->program
, ctx
->block
);
6580 Operand m
= load_lds_size_m0(bld
);
6581 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6582 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6584 unsigned num_operands
= 3;
6585 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6586 switch(instr
->intrinsic
) {
6587 case nir_intrinsic_shared_atomic_add
:
6588 op32
= aco_opcode::ds_add_u32
;
6589 op64
= aco_opcode::ds_add_u64
;
6590 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6591 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6593 case nir_intrinsic_shared_atomic_imin
:
6594 op32
= aco_opcode::ds_min_i32
;
6595 op64
= aco_opcode::ds_min_i64
;
6596 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6597 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6599 case nir_intrinsic_shared_atomic_umin
:
6600 op32
= aco_opcode::ds_min_u32
;
6601 op64
= aco_opcode::ds_min_u64
;
6602 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6603 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6605 case nir_intrinsic_shared_atomic_imax
:
6606 op32
= aco_opcode::ds_max_i32
;
6607 op64
= aco_opcode::ds_max_i64
;
6608 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6609 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6611 case nir_intrinsic_shared_atomic_umax
:
6612 op32
= aco_opcode::ds_max_u32
;
6613 op64
= aco_opcode::ds_max_u64
;
6614 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6615 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6617 case nir_intrinsic_shared_atomic_and
:
6618 op32
= aco_opcode::ds_and_b32
;
6619 op64
= aco_opcode::ds_and_b64
;
6620 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6621 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6623 case nir_intrinsic_shared_atomic_or
:
6624 op32
= aco_opcode::ds_or_b32
;
6625 op64
= aco_opcode::ds_or_b64
;
6626 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6627 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6629 case nir_intrinsic_shared_atomic_xor
:
6630 op32
= aco_opcode::ds_xor_b32
;
6631 op64
= aco_opcode::ds_xor_b64
;
6632 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6633 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6635 case nir_intrinsic_shared_atomic_exchange
:
6636 op32
= aco_opcode::ds_write_b32
;
6637 op64
= aco_opcode::ds_write_b64
;
6638 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6639 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6641 case nir_intrinsic_shared_atomic_comp_swap
:
6642 op32
= aco_opcode::ds_cmpst_b32
;
6643 op64
= aco_opcode::ds_cmpst_b64
;
6644 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6645 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6649 unreachable("Unhandled shared atomic intrinsic");
6652 /* return the previous value if dest is ever used */
6653 bool return_previous
= false;
6654 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6655 return_previous
= true;
6658 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6659 return_previous
= true;
6664 if (data
.size() == 1) {
6665 assert(instr
->dest
.ssa
.bit_size
== 32);
6666 op
= return_previous
? op32_rtn
: op32
;
6668 assert(instr
->dest
.ssa
.bit_size
== 64);
6669 op
= return_previous
? op64_rtn
: op64
;
6672 if (offset
> 65535) {
6673 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6677 aco_ptr
<DS_instruction
> ds
;
6678 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6679 ds
->operands
[0] = Operand(address
);
6680 ds
->operands
[1] = Operand(data
);
6681 if (num_operands
== 4)
6682 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6683 ds
->operands
[num_operands
- 1] = m
;
6684 ds
->offset0
= offset
;
6685 if (return_previous
)
6686 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6687 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6690 Temp
get_scratch_resource(isel_context
*ctx
)
6692 Builder
bld(ctx
->program
, ctx
->block
);
6693 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6694 if (ctx
->stage
!= compute_cs
)
6695 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6697 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6698 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6700 if (ctx
->program
->chip_class
>= GFX10
) {
6701 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6702 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6703 S_008F0C_RESOURCE_LEVEL(1);
6704 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6705 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6706 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6709 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6710 if (ctx
->program
->chip_class
<= GFX8
)
6711 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6713 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6716 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6717 Builder
bld(ctx
->program
, ctx
->block
);
6718 Temp rsrc
= get_scratch_resource(ctx
);
6719 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6720 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6722 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6723 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6724 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6725 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6726 info
.swizzle_component_size
= 16;
6727 info
.can_reorder
= false;
6728 info
.soffset
= ctx
->program
->scratch_offset
;
6729 emit_mubuf_load(ctx
, bld
, &info
);
6732 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6733 Builder
bld(ctx
->program
, ctx
->block
);
6734 Temp rsrc
= get_scratch_resource(ctx
);
6735 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6736 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6738 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6739 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6741 unsigned write_count
= 0;
6742 Temp write_datas
[32];
6743 unsigned offsets
[32];
6744 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6745 16, &write_count
, write_datas
, offsets
);
6747 for (unsigned i
= 0; i
< write_count
; i
++) {
6748 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6749 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6753 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6754 uint8_t log2_ps_iter_samples
;
6755 if (ctx
->program
->info
->ps
.force_persample
) {
6756 log2_ps_iter_samples
=
6757 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6759 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6762 /* The bit pattern matches that used by fixed function fragment
6764 static const unsigned ps_iter_masks
[] = {
6765 0xffff, /* not used */
6771 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6773 Builder
bld(ctx
->program
, ctx
->block
);
6775 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6776 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6777 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6778 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6779 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6780 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6783 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6784 Builder
bld(ctx
->program
, ctx
->block
);
6786 unsigned stream
= nir_intrinsic_stream_id(instr
);
6787 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6788 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6789 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6792 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6794 unsigned num_components
=
6795 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6796 assert(num_components
);
6798 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6799 unsigned stream_offset
= 0;
6800 for (unsigned i
= 0; i
< stream
; i
++) {
6801 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6802 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6805 /* Limit on the stride field for <= GFX7. */
6806 assert(stride
< (1 << 14));
6808 Temp gsvs_dwords
[4];
6809 for (unsigned i
= 0; i
< 4; i
++)
6810 gsvs_dwords
[i
] = bld
.tmp(s1
);
6811 bld
.pseudo(aco_opcode::p_split_vector
,
6812 Definition(gsvs_dwords
[0]),
6813 Definition(gsvs_dwords
[1]),
6814 Definition(gsvs_dwords
[2]),
6815 Definition(gsvs_dwords
[3]),
6818 if (stream_offset
) {
6819 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6821 Temp carry
= bld
.tmp(s1
);
6822 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6823 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6826 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6827 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6829 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6830 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6832 unsigned offset
= 0;
6833 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6834 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6837 for (unsigned j
= 0; j
< 4; j
++) {
6838 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6841 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6842 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6843 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6844 if (const_offset
>= 4096u) {
6845 if (vaddr_offset
.isUndefined())
6846 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6848 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6849 const_offset
%= 4096u;
6852 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6853 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6854 mtbuf
->operands
[1] = vaddr_offset
;
6855 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6856 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6857 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6858 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6859 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6860 mtbuf
->offset
= const_offset
;
6863 mtbuf
->barrier
= barrier_gs_data
;
6864 mtbuf
->can_reorder
= true;
6865 bld
.insert(std::move(mtbuf
));
6868 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6871 /* outputs for the next vertex are undefined and keeping them around can
6872 * create invalid IR with control flow */
6873 ctx
->outputs
.mask
[i
] = 0;
6876 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6879 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6881 Builder
bld(ctx
->program
, ctx
->block
);
6883 if (cluster_size
== 1) {
6885 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6886 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6887 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6888 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6889 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6890 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6891 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6892 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6893 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6894 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6895 //subgroupAnd(val) -> (exec & ~val) == 0
6896 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6897 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6898 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6899 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6900 //subgroupOr(val) -> (val & exec) != 0
6901 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6902 return bool_to_vector_condition(ctx
, tmp
);
6903 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6904 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6905 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6906 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6907 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6908 return bool_to_vector_condition(ctx
, tmp
);
6910 //subgroupClustered{And,Or,Xor}(val, n) ->
6911 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6912 //cluster_offset = ~(n - 1) & lane_id
6913 //cluster_mask = ((1 << n) - 1)
6914 //subgroupClusteredAnd():
6915 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6916 //subgroupClusteredOr():
6917 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6918 //subgroupClusteredXor():
6919 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6920 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6921 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6924 if (op
== nir_op_iand
)
6925 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6927 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6929 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6931 if (ctx
->program
->chip_class
<= GFX7
)
6932 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6933 else if (ctx
->program
->wave_size
== 64)
6934 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6936 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6937 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6938 if (cluster_mask
!= 0xffffffff)
6939 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6941 Definition cmp_def
= Definition();
6942 if (op
== nir_op_iand
) {
6943 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6944 } else if (op
== nir_op_ior
) {
6945 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6946 } else if (op
== nir_op_ixor
) {
6947 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6948 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6949 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6951 cmp_def
.setHint(vcc
);
6952 return cmp_def
.getTemp();
6956 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6958 Builder
bld(ctx
->program
, ctx
->block
);
6960 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6961 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6962 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6964 if (op
== nir_op_iand
)
6965 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6967 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6969 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6970 Temp lo
= lohi
.def(0).getTemp();
6971 Temp hi
= lohi
.def(1).getTemp();
6972 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6974 Definition cmp_def
= Definition();
6975 if (op
== nir_op_iand
)
6976 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6977 else if (op
== nir_op_ior
)
6978 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6979 else if (op
== nir_op_ixor
)
6980 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6981 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6982 cmp_def
.setHint(vcc
);
6983 return cmp_def
.getTemp();
6986 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6988 Builder
bld(ctx
->program
, ctx
->block
);
6990 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6991 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6992 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6993 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6994 if (op
== nir_op_iand
)
6995 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6996 else if (op
== nir_op_ior
)
6997 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6998 else if (op
== nir_op_ixor
)
6999 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7005 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7007 Builder
bld(ctx
->program
, ctx
->block
);
7008 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7009 if (src
.regClass().type() == RegType::vgpr
) {
7010 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7011 } else if (src
.regClass() == s1
) {
7012 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7013 } else if (src
.regClass() == s2
) {
7014 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7016 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7017 nir_print_instr(&instr
->instr
, stderr
);
7018 fprintf(stderr
, "\n");
7022 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7024 Builder
bld(ctx
->program
, ctx
->block
);
7025 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7026 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7027 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7029 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7030 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7031 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7032 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7035 if (ctx
->program
->chip_class
>= GFX8
) {
7036 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7037 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7038 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7039 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7040 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7041 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7043 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7044 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7045 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7046 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7047 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7048 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7049 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7050 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7051 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7052 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7055 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7056 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7057 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7058 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7059 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7060 Temp wqm1
= bld
.tmp(v1
);
7061 emit_wqm(ctx
, tmp1
, wqm1
, true);
7062 Temp wqm2
= bld
.tmp(v1
);
7063 emit_wqm(ctx
, tmp2
, wqm2
, true);
7064 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7068 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7070 Builder
bld(ctx
->program
, ctx
->block
);
7071 switch(instr
->intrinsic
) {
7072 case nir_intrinsic_load_barycentric_sample
:
7073 case nir_intrinsic_load_barycentric_pixel
:
7074 case nir_intrinsic_load_barycentric_centroid
: {
7075 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7076 Temp bary
= Temp(0, s2
);
7078 case INTERP_MODE_SMOOTH
:
7079 case INTERP_MODE_NONE
:
7080 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7081 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7082 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7083 bary
= ctx
->persp_centroid
;
7084 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7085 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7087 case INTERP_MODE_NOPERSPECTIVE
:
7088 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7089 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7090 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7091 bary
= ctx
->linear_centroid
;
7092 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7093 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7098 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7099 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7100 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7101 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7102 Operand(p1
), Operand(p2
));
7103 emit_split_vector(ctx
, dst
, 2);
7106 case nir_intrinsic_load_barycentric_model
: {
7107 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7109 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7110 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7111 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7112 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7113 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7114 Operand(p1
), Operand(p2
), Operand(p3
));
7115 emit_split_vector(ctx
, dst
, 3);
7118 case nir_intrinsic_load_barycentric_at_sample
: {
7119 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7120 switch (ctx
->options
->key
.fs
.num_samples
) {
7121 case 2: sample_pos_offset
+= 1 << 3; break;
7122 case 4: sample_pos_offset
+= 3 << 3; break;
7123 case 8: sample_pos_offset
+= 7 << 3; break;
7127 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7128 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7129 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7130 if (addr
.type() == RegType::sgpr
) {
7133 sample_pos_offset
+= const_addr
->u32
<< 3;
7134 offset
= Operand(sample_pos_offset
);
7135 } else if (ctx
->options
->chip_class
>= GFX9
) {
7136 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7138 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7139 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7142 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7143 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7145 } else if (ctx
->options
->chip_class
>= GFX9
) {
7146 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7147 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7148 } else if (ctx
->options
->chip_class
>= GFX7
) {
7149 /* addr += private_segment_buffer + sample_pos_offset */
7150 Temp tmp0
= bld
.tmp(s1
);
7151 Temp tmp1
= bld
.tmp(s1
);
7152 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7153 Definition scc_tmp
= bld
.def(s1
, scc
);
7154 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7155 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7156 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7157 Temp pck0
= bld
.tmp(v1
);
7158 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7159 tmp1
= as_vgpr(ctx
, tmp1
);
7160 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7161 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7163 /* sample_pos = flat_load_dwordx2 addr */
7164 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7166 assert(ctx
->options
->chip_class
== GFX6
);
7168 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7169 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7170 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7172 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7173 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7175 sample_pos
= bld
.tmp(v2
);
7177 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7178 load
->definitions
[0] = Definition(sample_pos
);
7179 load
->operands
[0] = Operand(rsrc
);
7180 load
->operands
[1] = Operand(addr
);
7181 load
->operands
[2] = Operand(0u);
7182 load
->offset
= sample_pos_offset
;
7184 load
->addr64
= true;
7187 load
->disable_wqm
= false;
7188 load
->barrier
= barrier_none
;
7189 load
->can_reorder
= true;
7190 ctx
->block
->instructions
.emplace_back(std::move(load
));
7193 /* sample_pos -= 0.5 */
7194 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7195 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7196 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7197 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7198 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7200 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7203 case nir_intrinsic_load_barycentric_at_offset
: {
7204 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7205 RegClass rc
= RegClass(offset
.type(), 1);
7206 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7207 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7208 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7211 case nir_intrinsic_load_front_face
: {
7212 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7213 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7216 case nir_intrinsic_load_view_index
: {
7217 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7218 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7219 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7225 case nir_intrinsic_load_layer_id
: {
7226 unsigned idx
= nir_intrinsic_base(instr
);
7227 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7228 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7231 case nir_intrinsic_load_frag_coord
: {
7232 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7235 case nir_intrinsic_load_sample_pos
: {
7236 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7237 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7238 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7239 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7240 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7243 case nir_intrinsic_load_tess_coord
:
7244 visit_load_tess_coord(ctx
, instr
);
7246 case nir_intrinsic_load_interpolated_input
:
7247 visit_load_interpolated_input(ctx
, instr
);
7249 case nir_intrinsic_store_output
:
7250 visit_store_output(ctx
, instr
);
7252 case nir_intrinsic_load_input
:
7253 case nir_intrinsic_load_input_vertex
:
7254 visit_load_input(ctx
, instr
);
7256 case nir_intrinsic_load_output
:
7257 visit_load_output(ctx
, instr
);
7259 case nir_intrinsic_load_per_vertex_input
:
7260 visit_load_per_vertex_input(ctx
, instr
);
7262 case nir_intrinsic_load_per_vertex_output
:
7263 visit_load_per_vertex_output(ctx
, instr
);
7265 case nir_intrinsic_store_per_vertex_output
:
7266 visit_store_per_vertex_output(ctx
, instr
);
7268 case nir_intrinsic_load_ubo
:
7269 visit_load_ubo(ctx
, instr
);
7271 case nir_intrinsic_load_push_constant
:
7272 visit_load_push_constant(ctx
, instr
);
7274 case nir_intrinsic_load_constant
:
7275 visit_load_constant(ctx
, instr
);
7277 case nir_intrinsic_vulkan_resource_index
:
7278 visit_load_resource(ctx
, instr
);
7280 case nir_intrinsic_discard
:
7281 visit_discard(ctx
, instr
);
7283 case nir_intrinsic_discard_if
:
7284 visit_discard_if(ctx
, instr
);
7286 case nir_intrinsic_load_shared
:
7287 visit_load_shared(ctx
, instr
);
7289 case nir_intrinsic_store_shared
:
7290 visit_store_shared(ctx
, instr
);
7292 case nir_intrinsic_shared_atomic_add
:
7293 case nir_intrinsic_shared_atomic_imin
:
7294 case nir_intrinsic_shared_atomic_umin
:
7295 case nir_intrinsic_shared_atomic_imax
:
7296 case nir_intrinsic_shared_atomic_umax
:
7297 case nir_intrinsic_shared_atomic_and
:
7298 case nir_intrinsic_shared_atomic_or
:
7299 case nir_intrinsic_shared_atomic_xor
:
7300 case nir_intrinsic_shared_atomic_exchange
:
7301 case nir_intrinsic_shared_atomic_comp_swap
:
7302 visit_shared_atomic(ctx
, instr
);
7304 case nir_intrinsic_image_deref_load
:
7305 visit_image_load(ctx
, instr
);
7307 case nir_intrinsic_image_deref_store
:
7308 visit_image_store(ctx
, instr
);
7310 case nir_intrinsic_image_deref_atomic_add
:
7311 case nir_intrinsic_image_deref_atomic_umin
:
7312 case nir_intrinsic_image_deref_atomic_imin
:
7313 case nir_intrinsic_image_deref_atomic_umax
:
7314 case nir_intrinsic_image_deref_atomic_imax
:
7315 case nir_intrinsic_image_deref_atomic_and
:
7316 case nir_intrinsic_image_deref_atomic_or
:
7317 case nir_intrinsic_image_deref_atomic_xor
:
7318 case nir_intrinsic_image_deref_atomic_exchange
:
7319 case nir_intrinsic_image_deref_atomic_comp_swap
:
7320 visit_image_atomic(ctx
, instr
);
7322 case nir_intrinsic_image_deref_size
:
7323 visit_image_size(ctx
, instr
);
7325 case nir_intrinsic_load_ssbo
:
7326 visit_load_ssbo(ctx
, instr
);
7328 case nir_intrinsic_store_ssbo
:
7329 visit_store_ssbo(ctx
, instr
);
7331 case nir_intrinsic_load_global
:
7332 visit_load_global(ctx
, instr
);
7334 case nir_intrinsic_store_global
:
7335 visit_store_global(ctx
, instr
);
7337 case nir_intrinsic_global_atomic_add
:
7338 case nir_intrinsic_global_atomic_imin
:
7339 case nir_intrinsic_global_atomic_umin
:
7340 case nir_intrinsic_global_atomic_imax
:
7341 case nir_intrinsic_global_atomic_umax
:
7342 case nir_intrinsic_global_atomic_and
:
7343 case nir_intrinsic_global_atomic_or
:
7344 case nir_intrinsic_global_atomic_xor
:
7345 case nir_intrinsic_global_atomic_exchange
:
7346 case nir_intrinsic_global_atomic_comp_swap
:
7347 visit_global_atomic(ctx
, instr
);
7349 case nir_intrinsic_ssbo_atomic_add
:
7350 case nir_intrinsic_ssbo_atomic_imin
:
7351 case nir_intrinsic_ssbo_atomic_umin
:
7352 case nir_intrinsic_ssbo_atomic_imax
:
7353 case nir_intrinsic_ssbo_atomic_umax
:
7354 case nir_intrinsic_ssbo_atomic_and
:
7355 case nir_intrinsic_ssbo_atomic_or
:
7356 case nir_intrinsic_ssbo_atomic_xor
:
7357 case nir_intrinsic_ssbo_atomic_exchange
:
7358 case nir_intrinsic_ssbo_atomic_comp_swap
:
7359 visit_atomic_ssbo(ctx
, instr
);
7361 case nir_intrinsic_load_scratch
:
7362 visit_load_scratch(ctx
, instr
);
7364 case nir_intrinsic_store_scratch
:
7365 visit_store_scratch(ctx
, instr
);
7367 case nir_intrinsic_get_buffer_size
:
7368 visit_get_buffer_size(ctx
, instr
);
7370 case nir_intrinsic_control_barrier
: {
7371 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7372 /* GFX6 only (thanks to a hw bug workaround):
7373 * The real barrier instruction isn’t needed, because an entire patch
7374 * always fits into a single wave.
7379 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7380 bld
.sopp(aco_opcode::s_barrier
);
7384 case nir_intrinsic_memory_barrier_tcs_patch
:
7385 case nir_intrinsic_group_memory_barrier
:
7386 case nir_intrinsic_memory_barrier
:
7387 case nir_intrinsic_memory_barrier_buffer
:
7388 case nir_intrinsic_memory_barrier_image
:
7389 case nir_intrinsic_memory_barrier_shared
:
7390 emit_memory_barrier(ctx
, instr
);
7392 case nir_intrinsic_load_num_work_groups
: {
7393 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7394 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7395 emit_split_vector(ctx
, dst
, 3);
7398 case nir_intrinsic_load_local_invocation_id
: {
7399 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7400 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7401 emit_split_vector(ctx
, dst
, 3);
7404 case nir_intrinsic_load_work_group_id
: {
7405 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7406 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7407 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7408 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7409 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7410 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7411 emit_split_vector(ctx
, dst
, 3);
7414 case nir_intrinsic_load_local_invocation_index
: {
7415 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7417 /* The tg_size bits [6:11] contain the subgroup id,
7418 * we need this multiplied by the wave size, and then OR the thread id to it.
7420 if (ctx
->program
->wave_size
== 64) {
7421 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7422 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7423 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7424 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7426 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7427 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7428 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7429 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7433 case nir_intrinsic_load_subgroup_id
: {
7434 if (ctx
->stage
== compute_cs
) {
7435 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7436 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7438 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7442 case nir_intrinsic_load_subgroup_invocation
: {
7443 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7446 case nir_intrinsic_load_num_subgroups
: {
7447 if (ctx
->stage
== compute_cs
)
7448 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7449 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7451 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7454 case nir_intrinsic_ballot
: {
7455 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7456 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7457 Definition tmp
= bld
.def(dst
.regClass());
7458 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7459 if (instr
->src
[0].ssa
->bit_size
== 1) {
7460 assert(src
.regClass() == bld
.lm
);
7461 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7462 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7463 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7464 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7465 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7467 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7468 nir_print_instr(&instr
->instr
, stderr
);
7469 fprintf(stderr
, "\n");
7471 if (dst
.size() != bld
.lm
.size()) {
7472 /* Wave32 with ballot size set to 64 */
7473 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7475 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7478 case nir_intrinsic_shuffle
:
7479 case nir_intrinsic_read_invocation
: {
7480 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7481 if (!nir_src_is_divergent(instr
->src
[0])) {
7482 emit_uniform_subgroup(ctx
, instr
, src
);
7484 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7485 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7486 tid
= bld
.as_uniform(tid
);
7487 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7488 if (src
.regClass() == v1
) {
7489 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7490 } else if (src
.regClass() == v2
) {
7491 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7492 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7493 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7494 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7495 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7496 emit_split_vector(ctx
, dst
, 2);
7497 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7498 assert(src
.regClass() == bld
.lm
);
7499 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7500 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7501 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7502 assert(src
.regClass() == bld
.lm
);
7504 if (ctx
->program
->chip_class
<= GFX7
)
7505 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7506 else if (ctx
->program
->wave_size
== 64)
7507 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7509 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7510 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7511 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7512 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7515 nir_print_instr(&instr
->instr
, stderr
);
7516 fprintf(stderr
, "\n");
7521 case nir_intrinsic_load_sample_id
: {
7522 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7523 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7526 case nir_intrinsic_load_sample_mask_in
: {
7527 visit_load_sample_mask_in(ctx
, instr
);
7530 case nir_intrinsic_read_first_invocation
: {
7531 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7532 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7533 if (src
.regClass() == v1
) {
7535 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7537 } else if (src
.regClass() == v2
) {
7538 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7539 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7540 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7541 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7542 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7543 emit_split_vector(ctx
, dst
, 2);
7544 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7545 assert(src
.regClass() == bld
.lm
);
7546 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7547 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7548 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7549 } else if (src
.regClass() == s1
) {
7550 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7551 } else if (src
.regClass() == s2
) {
7552 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7554 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7555 nir_print_instr(&instr
->instr
, stderr
);
7556 fprintf(stderr
, "\n");
7560 case nir_intrinsic_vote_all
: {
7561 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7562 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7563 assert(src
.regClass() == bld
.lm
);
7564 assert(dst
.regClass() == bld
.lm
);
7566 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7567 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7568 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7571 case nir_intrinsic_vote_any
: {
7572 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7573 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7574 assert(src
.regClass() == bld
.lm
);
7575 assert(dst
.regClass() == bld
.lm
);
7577 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7578 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7581 case nir_intrinsic_reduce
:
7582 case nir_intrinsic_inclusive_scan
:
7583 case nir_intrinsic_exclusive_scan
: {
7584 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7585 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7586 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7587 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7588 nir_intrinsic_cluster_size(instr
) : 0;
7589 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7591 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7592 emit_uniform_subgroup(ctx
, instr
, src
);
7593 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7594 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7596 else if (op
== nir_op_iadd
)
7598 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7600 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7602 switch (instr
->intrinsic
) {
7603 case nir_intrinsic_reduce
:
7604 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7606 case nir_intrinsic_exclusive_scan
:
7607 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7609 case nir_intrinsic_inclusive_scan
:
7610 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7615 } else if (cluster_size
== 1) {
7616 bld
.copy(Definition(dst
), src
);
7618 src
= as_vgpr(ctx
, src
);
7622 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7637 unreachable("unknown reduction op");
7642 switch (instr
->intrinsic
) {
7643 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7644 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7645 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7647 unreachable("unknown reduce intrinsic");
7650 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7651 reduce
->operands
[0] = Operand(src
);
7652 // filled in by aco_reduce_assign.cpp, used internally as part of the
7654 assert(dst
.size() == 1 || dst
.size() == 2);
7655 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7656 reduce
->operands
[2] = Operand(v1
.as_linear());
7658 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7659 reduce
->definitions
[0] = Definition(tmp_dst
);
7660 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7661 reduce
->definitions
[2] = Definition();
7662 reduce
->definitions
[3] = Definition(scc
, s1
);
7663 reduce
->definitions
[4] = Definition();
7664 reduce
->reduce_op
= reduce_op
;
7665 reduce
->cluster_size
= cluster_size
;
7666 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7668 emit_wqm(ctx
, tmp_dst
, dst
);
7672 case nir_intrinsic_quad_broadcast
: {
7673 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7674 if (!nir_dest_is_divergent(instr
->dest
)) {
7675 emit_uniform_subgroup(ctx
, instr
, src
);
7677 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7678 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7679 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7681 if (instr
->dest
.ssa
.bit_size
== 1) {
7682 assert(src
.regClass() == bld
.lm
);
7683 assert(dst
.regClass() == bld
.lm
);
7684 uint32_t half_mask
= 0x11111111u
<< lane
;
7685 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7686 Temp tmp
= bld
.tmp(bld
.lm
);
7687 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7688 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7689 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7690 emit_wqm(ctx
, tmp
, dst
);
7691 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7692 if (ctx
->program
->chip_class
>= GFX8
)
7693 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7695 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7696 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7697 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7698 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7699 if (ctx
->program
->chip_class
>= GFX8
) {
7700 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7701 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7703 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7704 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7706 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7707 emit_split_vector(ctx
, dst
, 2);
7709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7710 nir_print_instr(&instr
->instr
, stderr
);
7711 fprintf(stderr
, "\n");
7716 case nir_intrinsic_quad_swap_horizontal
:
7717 case nir_intrinsic_quad_swap_vertical
:
7718 case nir_intrinsic_quad_swap_diagonal
:
7719 case nir_intrinsic_quad_swizzle_amd
: {
7720 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7721 if (!nir_dest_is_divergent(instr
->dest
)) {
7722 emit_uniform_subgroup(ctx
, instr
, src
);
7725 uint16_t dpp_ctrl
= 0;
7726 switch (instr
->intrinsic
) {
7727 case nir_intrinsic_quad_swap_horizontal
:
7728 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7730 case nir_intrinsic_quad_swap_vertical
:
7731 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7733 case nir_intrinsic_quad_swap_diagonal
:
7734 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7736 case nir_intrinsic_quad_swizzle_amd
:
7737 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7742 if (ctx
->program
->chip_class
< GFX8
)
7743 dpp_ctrl
|= (1 << 15);
7745 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7746 if (instr
->dest
.ssa
.bit_size
== 1) {
7747 assert(src
.regClass() == bld
.lm
);
7748 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7749 if (ctx
->program
->chip_class
>= GFX8
)
7750 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7752 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7753 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7754 emit_wqm(ctx
, tmp
, dst
);
7755 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7757 if (ctx
->program
->chip_class
>= GFX8
)
7758 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7760 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7761 emit_wqm(ctx
, tmp
, dst
);
7762 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7763 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7765 if (ctx
->program
->chip_class
>= GFX8
) {
7766 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7767 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7769 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7770 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7772 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7773 emit_split_vector(ctx
, dst
, 2);
7775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7776 nir_print_instr(&instr
->instr
, stderr
);
7777 fprintf(stderr
, "\n");
7781 case nir_intrinsic_masked_swizzle_amd
: {
7782 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7783 if (!nir_dest_is_divergent(instr
->dest
)) {
7784 emit_uniform_subgroup(ctx
, instr
, src
);
7787 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7788 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7789 if (dst
.regClass() == v1
) {
7791 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7793 } else if (dst
.regClass() == v2
) {
7794 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7796 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7797 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7798 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7799 emit_split_vector(ctx
, dst
, 2);
7801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7802 nir_print_instr(&instr
->instr
, stderr
);
7803 fprintf(stderr
, "\n");
7807 case nir_intrinsic_write_invocation_amd
: {
7808 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7809 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7810 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7811 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7812 if (dst
.regClass() == v1
) {
7813 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7814 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7815 } else if (dst
.regClass() == v2
) {
7816 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7817 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7818 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7819 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7820 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7821 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7822 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7823 emit_split_vector(ctx
, dst
, 2);
7825 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7826 nir_print_instr(&instr
->instr
, stderr
);
7827 fprintf(stderr
, "\n");
7831 case nir_intrinsic_mbcnt_amd
: {
7832 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7833 RegClass rc
= RegClass(src
.type(), 1);
7834 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7835 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7836 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7837 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7838 emit_wqm(ctx
, wqm_tmp
, dst
);
7841 case nir_intrinsic_load_helper_invocation
: {
7842 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7843 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7844 ctx
->block
->kind
|= block_kind_needs_lowering
;
7845 ctx
->program
->needs_exact
= true;
7848 case nir_intrinsic_is_helper_invocation
: {
7849 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7850 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7851 ctx
->block
->kind
|= block_kind_needs_lowering
;
7852 ctx
->program
->needs_exact
= true;
7855 case nir_intrinsic_demote
:
7856 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7858 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7859 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7860 ctx
->block
->kind
|= block_kind_uses_demote
;
7861 ctx
->program
->needs_exact
= true;
7863 case nir_intrinsic_demote_if
: {
7864 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7865 assert(src
.regClass() == bld
.lm
);
7866 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7867 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7869 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7870 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7871 ctx
->block
->kind
|= block_kind_uses_demote
;
7872 ctx
->program
->needs_exact
= true;
7875 case nir_intrinsic_first_invocation
: {
7876 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7877 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7880 case nir_intrinsic_shader_clock
:
7881 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7882 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7884 case nir_intrinsic_load_vertex_id_zero_base
: {
7885 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7886 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7889 case nir_intrinsic_load_first_vertex
: {
7890 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7891 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7894 case nir_intrinsic_load_base_instance
: {
7895 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7896 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7899 case nir_intrinsic_load_instance_id
: {
7900 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7901 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7904 case nir_intrinsic_load_draw_id
: {
7905 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7906 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7909 case nir_intrinsic_load_invocation_id
: {
7910 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7912 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7913 if (ctx
->options
->chip_class
>= GFX10
)
7914 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7916 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7917 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7918 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7919 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7921 unreachable("Unsupported stage for load_invocation_id");
7926 case nir_intrinsic_load_primitive_id
: {
7927 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7929 switch (ctx
->shader
->info
.stage
) {
7930 case MESA_SHADER_GEOMETRY
:
7931 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7933 case MESA_SHADER_TESS_CTRL
:
7934 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7936 case MESA_SHADER_TESS_EVAL
:
7937 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7940 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7945 case nir_intrinsic_load_patch_vertices_in
: {
7946 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7947 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7949 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7950 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7953 case nir_intrinsic_emit_vertex_with_counter
: {
7954 visit_emit_vertex_with_counter(ctx
, instr
);
7957 case nir_intrinsic_end_primitive_with_counter
: {
7958 unsigned stream
= nir_intrinsic_stream_id(instr
);
7959 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7962 case nir_intrinsic_set_vertex_count
: {
7963 /* unused, the HW keeps track of this for us */
7967 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7968 nir_print_instr(&instr
->instr
, stderr
);
7969 fprintf(stderr
, "\n");
7977 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7978 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7979 enum glsl_base_type
*stype
)
7981 nir_deref_instr
*texture_deref_instr
= NULL
;
7982 nir_deref_instr
*sampler_deref_instr
= NULL
;
7985 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7986 switch (instr
->src
[i
].src_type
) {
7987 case nir_tex_src_texture_deref
:
7988 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7990 case nir_tex_src_sampler_deref
:
7991 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7993 case nir_tex_src_plane
:
7994 plane
= nir_src_as_int(instr
->src
[i
].src
);
8001 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8003 if (!sampler_deref_instr
)
8004 sampler_deref_instr
= texture_deref_instr
;
8007 assert(instr
->op
!= nir_texop_txf_ms
&&
8008 instr
->op
!= nir_texop_samples_identical
);
8009 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8010 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8011 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8012 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8013 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8014 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8016 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8019 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8021 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8022 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8023 Builder
bld(ctx
->program
, ctx
->block
);
8025 /* to avoid unnecessary moves, we split and recombine sampler and image */
8026 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8027 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8028 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8030 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8031 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8032 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8033 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8035 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8036 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8037 img
[0], img
[1], img
[2], img
[3],
8038 img
[4], img
[5], img
[6], img
[7]);
8039 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8040 samp
[0], samp
[1], samp
[2], samp
[3]);
8043 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8044 instr
->op
== nir_texop_samples_identical
))
8045 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8048 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8049 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8051 Builder
bld(ctx
->program
, ctx
->block
);
8053 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8054 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8055 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8057 Operand
neg_one(0xbf800000u
);
8058 Operand
one(0x3f800000u
);
8059 Operand
two(0x40000000u
);
8060 Operand
four(0x40800000u
);
8062 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8063 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8064 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8066 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8067 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8068 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8069 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8072 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8073 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8074 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8076 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8079 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8080 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8081 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8084 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8085 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8087 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8088 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8091 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8093 Builder
bld(ctx
->program
, ctx
->block
);
8094 Temp ma
, tc
, sc
, id
;
8097 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8099 // see comment in ac_prepare_cube_coords()
8100 if (ctx
->options
->chip_class
<= GFX8
)
8101 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8104 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8106 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8107 vop3a
->operands
[0] = Operand(ma
);
8108 vop3a
->abs
[0] = true;
8109 Temp invma
= bld
.tmp(v1
);
8110 vop3a
->definitions
[0] = Definition(invma
);
8111 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8113 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8115 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8117 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8119 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8121 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8124 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8125 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8127 for (unsigned i
= 0; i
< 2; i
++) {
8128 // see comment in ac_prepare_cube_coords()
8130 Temp deriv_sc
, deriv_tc
;
8131 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8132 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8134 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8136 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8137 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8138 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8139 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8140 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8141 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8142 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8145 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8146 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8150 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8157 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8159 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8161 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8162 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8165 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8166 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8167 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8171 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8173 Builder
bld(ctx
->program
, ctx
->block
);
8174 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8175 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8176 has_clamped_lod
= false;
8177 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8178 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8179 clamped_lod
= Temp();
8180 std::vector
<Temp
> coords
;
8181 std::vector
<Temp
> derivs
;
8182 nir_const_value
*sample_index_cv
= NULL
;
8183 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8184 enum glsl_base_type stype
;
8185 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8187 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8188 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8189 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8190 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8192 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8193 switch (instr
->src
[i
].src_type
) {
8194 case nir_tex_src_coord
: {
8195 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8196 for (unsigned i
= 0; i
< coord
.size(); i
++)
8197 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8200 case nir_tex_src_bias
:
8201 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8204 case nir_tex_src_lod
: {
8205 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8207 if (val
&& val
->f32
<= 0.0) {
8210 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8215 case nir_tex_src_min_lod
:
8216 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8217 has_clamped_lod
= true;
8219 case nir_tex_src_comparator
:
8220 if (instr
->is_shadow
) {
8221 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8225 case nir_tex_src_offset
:
8226 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8227 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8230 case nir_tex_src_ddx
:
8231 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8234 case nir_tex_src_ddy
:
8235 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8238 case nir_tex_src_ms_index
:
8239 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8240 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8241 has_sample_index
= true;
8243 case nir_tex_src_texture_offset
:
8244 case nir_tex_src_sampler_offset
:
8250 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8251 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8253 if (instr
->op
== nir_texop_texture_samples
) {
8254 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8256 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8257 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8258 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8260 Operand default_sample
= Operand(1u);
8261 if (ctx
->options
->robust_buffer_access
) {
8262 /* Extract the second dword of the descriptor, if it's
8263 * all zero, then it's a null descriptor.
8265 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8266 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8267 default_sample
= Operand(is_non_null_descriptor
);
8270 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8271 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8272 samples
, default_sample
, bld
.scc(is_msaa
));
8276 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8277 aco_ptr
<Instruction
> tmp_instr
;
8278 Temp acc
, pack
= Temp();
8280 uint32_t pack_const
= 0;
8281 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8282 if (!const_offset
[i
])
8284 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8287 if (offset
.type() == RegType::sgpr
) {
8288 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8289 if (const_offset
[i
])
8292 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8293 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8296 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8299 if (pack
== Temp()) {
8302 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8306 if (pack_const
&& pack
!= Temp())
8307 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8309 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8310 if (const_offset
[i
])
8313 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8314 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8317 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8320 if (pack
== Temp()) {
8323 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8327 if (pack_const
&& pack
!= Temp())
8328 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8330 if (pack_const
&& pack
== Temp())
8331 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8332 else if (pack
== Temp())
8338 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8339 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8341 /* pack derivatives */
8342 if (has_ddx
|| has_ddy
) {
8343 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8344 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8345 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8346 derivs
= {ddx
, zero
, ddy
, zero
};
8348 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8349 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8350 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8351 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8356 if (instr
->coord_components
> 1 &&
8357 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8359 instr
->op
!= nir_texop_txf
)
8360 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8362 if (instr
->coord_components
> 2 &&
8363 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8364 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8365 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8366 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8368 instr
->op
!= nir_texop_txf
&&
8369 instr
->op
!= nir_texop_txf_ms
&&
8370 instr
->op
!= nir_texop_fragment_fetch
&&
8371 instr
->op
!= nir_texop_fragment_mask_fetch
)
8372 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8374 if (ctx
->options
->chip_class
== GFX9
&&
8375 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8376 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8377 assert(coords
.size() > 0 && coords
.size() < 3);
8379 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8380 Operand((uint32_t) 0) :
8381 Operand((uint32_t) 0x3f000000)));
8384 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8386 if (instr
->op
== nir_texop_samples_identical
)
8387 resource
= fmask_ptr
;
8389 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8390 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8391 instr
->op
!= nir_texop_txs
&&
8392 instr
->op
!= nir_texop_fragment_fetch
&&
8393 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8394 assert(has_sample_index
);
8395 Operand
op(sample_index
);
8396 if (sample_index_cv
)
8397 op
= Operand(sample_index_cv
->u32
);
8398 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8401 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8402 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8403 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8404 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8409 /* Build tex instruction */
8410 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8411 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8412 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8414 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8417 /* gather4 selects the component by dmask and always returns vec4 */
8418 if (instr
->op
== nir_texop_tg4
) {
8419 assert(instr
->dest
.ssa
.num_components
== 4);
8420 if (instr
->is_shadow
)
8423 dmask
= 1 << instr
->component
;
8424 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8425 tmp_dst
= bld
.tmp(v4
);
8426 } else if (instr
->op
== nir_texop_samples_identical
) {
8427 tmp_dst
= bld
.tmp(v1
);
8428 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8429 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8432 aco_ptr
<MIMG_instruction
> tex
;
8433 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8435 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8437 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8438 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8441 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8442 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8444 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8445 tex
->operands
[0] = Operand(resource
);
8446 tex
->operands
[1] = Operand(s4
); /* no sampler */
8447 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8448 if (ctx
->options
->chip_class
== GFX9
&&
8449 instr
->op
== nir_texop_txs
&&
8450 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8452 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8453 } else if (instr
->op
== nir_texop_query_levels
) {
8454 tex
->dmask
= 1 << 3;
8459 tex
->definitions
[0] = Definition(tmp_dst
);
8461 tex
->can_reorder
= true;
8462 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8465 /* divide 3rd value by 6 by multiplying with magic number */
8466 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8467 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8468 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8469 assert(instr
->dest
.ssa
.num_components
== 3);
8470 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8471 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8472 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8473 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8478 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8482 Temp tg4_compare_cube_wa64
= Temp();
8484 if (tg4_integer_workarounds
) {
8485 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8486 tex
->operands
[0] = Operand(resource
);
8487 tex
->operands
[1] = Operand(s4
); /* no sampler */
8488 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8492 Temp size
= bld
.tmp(v2
);
8493 tex
->definitions
[0] = Definition(size
);
8494 tex
->can_reorder
= true;
8495 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8496 emit_split_vector(ctx
, size
, size
.size());
8499 for (unsigned i
= 0; i
< 2; i
++) {
8500 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8501 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8502 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8503 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8506 Temp new_coords
[2] = {
8507 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8508 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8511 if (tg4_integer_cube_workaround
) {
8512 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8513 Temp desc
[resource
.size()];
8514 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8515 Format::PSEUDO
, 1, resource
.size())};
8516 split
->operands
[0] = Operand(resource
);
8517 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8518 desc
[i
] = bld
.tmp(s1
);
8519 split
->definitions
[i
] = Definition(desc
[i
]);
8521 ctx
->block
->instructions
.emplace_back(std::move(split
));
8523 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8524 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8525 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8528 if (stype
== GLSL_TYPE_UINT
) {
8529 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8530 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8531 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8532 bld
.scc(compare_cube_wa
));
8534 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8535 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8536 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8537 bld
.scc(compare_cube_wa
));
8539 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8540 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8542 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8544 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8545 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8546 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8548 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8549 Format::PSEUDO
, resource
.size(), 1)};
8550 for (unsigned i
= 0; i
< resource
.size(); i
++)
8551 vec
->operands
[i
] = Operand(desc
[i
]);
8552 resource
= bld
.tmp(resource
.regClass());
8553 vec
->definitions
[0] = Definition(resource
);
8554 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8556 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8557 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8558 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8559 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8561 coords
[0] = new_coords
[0];
8562 coords
[1] = new_coords
[1];
8565 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8566 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8568 assert(coords
.size() == 1);
8569 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8573 op
= aco_opcode::buffer_load_format_x
; break;
8575 op
= aco_opcode::buffer_load_format_xy
; break;
8577 op
= aco_opcode::buffer_load_format_xyz
; break;
8579 op
= aco_opcode::buffer_load_format_xyzw
; break;
8581 unreachable("Tex instruction loads more than 4 components.");
8584 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8585 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8588 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8590 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8591 mubuf
->operands
[0] = Operand(resource
);
8592 mubuf
->operands
[1] = Operand(coords
[0]);
8593 mubuf
->operands
[2] = Operand((uint32_t) 0);
8594 mubuf
->definitions
[0] = Definition(tmp_dst
);
8595 mubuf
->idxen
= true;
8596 mubuf
->can_reorder
= true;
8597 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8599 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8603 /* gather MIMG address components */
8604 std::vector
<Temp
> args
;
8606 args
.emplace_back(offset
);
8608 args
.emplace_back(bias
);
8610 args
.emplace_back(compare
);
8612 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8614 args
.insert(args
.end(), coords
.begin(), coords
.end());
8615 if (has_sample_index
)
8616 args
.emplace_back(sample_index
);
8618 args
.emplace_back(lod
);
8619 if (has_clamped_lod
)
8620 args
.emplace_back(clamped_lod
);
8622 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8623 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8624 vec
->definitions
[0] = Definition(arg
);
8625 for (unsigned i
= 0; i
< args
.size(); i
++)
8626 vec
->operands
[i
] = Operand(args
[i
]);
8627 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8630 if (instr
->op
== nir_texop_txf
||
8631 instr
->op
== nir_texop_txf_ms
||
8632 instr
->op
== nir_texop_samples_identical
||
8633 instr
->op
== nir_texop_fragment_fetch
||
8634 instr
->op
== nir_texop_fragment_mask_fetch
) {
8635 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8636 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8637 tex
->operands
[0] = Operand(resource
);
8638 tex
->operands
[1] = Operand(s4
); /* no sampler */
8639 tex
->operands
[2] = Operand(arg
);
8644 tex
->definitions
[0] = Definition(tmp_dst
);
8645 tex
->can_reorder
= true;
8646 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8648 if (instr
->op
== nir_texop_samples_identical
) {
8649 assert(dmask
== 1 && dst
.regClass() == v1
);
8650 assert(dst
.id() != tmp_dst
.id());
8652 Temp tmp
= bld
.tmp(bld
.lm
);
8653 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8654 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8657 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8662 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8663 aco_opcode opcode
= aco_opcode::image_sample
;
8664 if (has_offset
) { /* image_sample_*_o */
8665 if (has_clamped_lod
) {
8667 opcode
= aco_opcode::image_sample_c_cl_o
;
8669 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8671 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8673 opcode
= aco_opcode::image_sample_cl_o
;
8675 opcode
= aco_opcode::image_sample_d_cl_o
;
8677 opcode
= aco_opcode::image_sample_b_cl_o
;
8679 } else if (has_compare
) {
8680 opcode
= aco_opcode::image_sample_c_o
;
8682 opcode
= aco_opcode::image_sample_c_d_o
;
8684 opcode
= aco_opcode::image_sample_c_b_o
;
8686 opcode
= aco_opcode::image_sample_c_lz_o
;
8688 opcode
= aco_opcode::image_sample_c_l_o
;
8690 opcode
= aco_opcode::image_sample_o
;
8692 opcode
= aco_opcode::image_sample_d_o
;
8694 opcode
= aco_opcode::image_sample_b_o
;
8696 opcode
= aco_opcode::image_sample_lz_o
;
8698 opcode
= aco_opcode::image_sample_l_o
;
8700 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8702 opcode
= aco_opcode::image_sample_c_cl
;
8704 opcode
= aco_opcode::image_sample_c_d_cl
;
8706 opcode
= aco_opcode::image_sample_c_b_cl
;
8708 opcode
= aco_opcode::image_sample_cl
;
8710 opcode
= aco_opcode::image_sample_d_cl
;
8712 opcode
= aco_opcode::image_sample_b_cl
;
8714 } else { /* no offset */
8716 opcode
= aco_opcode::image_sample_c
;
8718 opcode
= aco_opcode::image_sample_c_d
;
8720 opcode
= aco_opcode::image_sample_c_b
;
8722 opcode
= aco_opcode::image_sample_c_lz
;
8724 opcode
= aco_opcode::image_sample_c_l
;
8726 opcode
= aco_opcode::image_sample
;
8728 opcode
= aco_opcode::image_sample_d
;
8730 opcode
= aco_opcode::image_sample_b
;
8732 opcode
= aco_opcode::image_sample_lz
;
8734 opcode
= aco_opcode::image_sample_l
;
8738 if (instr
->op
== nir_texop_tg4
) {
8740 opcode
= aco_opcode::image_gather4_lz_o
;
8742 opcode
= aco_opcode::image_gather4_c_lz_o
;
8744 opcode
= aco_opcode::image_gather4_lz
;
8746 opcode
= aco_opcode::image_gather4_c_lz
;
8748 } else if (instr
->op
== nir_texop_lod
) {
8749 opcode
= aco_opcode::image_get_lod
;
8752 /* we don't need the bias, sample index, compare value or offset to be
8753 * computed in WQM but if the p_create_vector copies the coordinates, then it
8754 * needs to be in WQM */
8755 if (ctx
->stage
== fragment_fs
&&
8756 !has_derivs
&& !has_lod
&& !level_zero
&&
8757 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8758 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8759 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8761 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8762 tex
->operands
[0] = Operand(resource
);
8763 tex
->operands
[1] = Operand(sampler
);
8764 tex
->operands
[2] = Operand(arg
);
8768 tex
->definitions
[0] = Definition(tmp_dst
);
8769 tex
->can_reorder
= true;
8770 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8772 if (tg4_integer_cube_workaround
) {
8773 assert(tmp_dst
.id() != dst
.id());
8774 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8776 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8778 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8779 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8781 if (stype
== GLSL_TYPE_UINT
)
8782 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8784 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8785 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8787 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8788 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8789 val
[0], val
[1], val
[2], val
[3]);
8791 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8792 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8797 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8799 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8800 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8801 return Operand(tmp
.regClass());
8803 return Operand(tmp
);
8806 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8808 aco_ptr
<Pseudo_instruction
> phi
;
8809 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8810 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8812 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8813 logical
|= ctx
->block
->kind
& block_kind_merge
;
8814 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8816 /* we want a sorted list of sources, since the predecessor list is also sorted */
8817 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8818 nir_foreach_phi_src(src
, instr
)
8819 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8821 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8822 unsigned num_operands
= 0;
8823 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8824 unsigned num_defined
= 0;
8825 unsigned cur_pred_idx
= 0;
8826 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8827 if (cur_pred_idx
< preds
.size()) {
8828 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8829 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8830 unsigned skipped
= 0;
8831 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8833 if (cur_pred_idx
+ skipped
< preds
.size()) {
8834 for (unsigned i
= 0; i
< skipped
; i
++)
8835 operands
[num_operands
++] = Operand(dst
.regClass());
8836 cur_pred_idx
+= skipped
;
8841 /* Handle missing predecessors at the end. This shouldn't happen with loop
8842 * headers and we can't ignore these sources for loop header phis. */
8843 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8846 Operand op
= get_phi_operand(ctx
, src
.second
);
8847 operands
[num_operands
++] = op
;
8848 num_defined
+= !op
.isUndefined();
8850 /* handle block_kind_continue_or_break at loop exit blocks */
8851 while (cur_pred_idx
++ < preds
.size())
8852 operands
[num_operands
++] = Operand(dst
.regClass());
8854 /* If the loop ends with a break, still add a linear continue edge in case
8855 * that break is divergent or continue_or_break is used. We'll either remove
8856 * this operand later in visit_loop() if it's not necessary or replace the
8857 * undef with something correct. */
8858 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8859 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8860 nir_block
*last
= nir_loop_last_block(loop
);
8861 if (last
->successors
[0] != instr
->instr
.block
)
8862 operands
[num_operands
++] = Operand(RegClass());
8865 if (num_defined
== 0) {
8866 Builder
bld(ctx
->program
, ctx
->block
);
8867 if (dst
.regClass() == s1
) {
8868 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8869 } else if (dst
.regClass() == v1
) {
8870 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8872 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8873 for (unsigned i
= 0; i
< dst
.size(); i
++)
8874 vec
->operands
[i
] = Operand(0u);
8875 vec
->definitions
[0] = Definition(dst
);
8876 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8881 /* we can use a linear phi in some cases if one src is undef */
8882 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8883 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8885 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8886 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8887 assert(invert
->kind
& block_kind_invert
);
8889 unsigned then_block
= invert
->linear_preds
[0];
8891 Block
* insert_block
= NULL
;
8892 for (unsigned i
= 0; i
< num_operands
; i
++) {
8893 Operand op
= operands
[i
];
8894 if (op
.isUndefined())
8896 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8897 phi
->operands
[0] = op
;
8900 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8901 phi
->operands
[1] = Operand(dst
.regClass());
8902 phi
->definitions
[0] = Definition(dst
);
8903 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8907 /* try to scalarize vector phis */
8908 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8909 // TODO: scalarize linear phis on divergent ifs
8910 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8911 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8912 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8913 Operand src
= operands
[i
];
8914 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8915 can_scalarize
= false;
8917 if (can_scalarize
) {
8918 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8919 assert(dst
.size() % num_components
== 0);
8920 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8922 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8923 for (unsigned k
= 0; k
< num_components
; k
++) {
8924 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8925 for (unsigned i
= 0; i
< num_operands
; i
++) {
8926 Operand src
= operands
[i
];
8927 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8929 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8930 phi
->definitions
[0] = Definition(phi_dst
);
8931 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8932 new_vec
[k
] = phi_dst
;
8933 vec
->operands
[k
] = Operand(phi_dst
);
8935 vec
->definitions
[0] = Definition(dst
);
8936 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8937 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8942 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8943 for (unsigned i
= 0; i
< num_operands
; i
++)
8944 phi
->operands
[i
] = operands
[i
];
8945 phi
->definitions
[0] = Definition(dst
);
8946 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8950 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8952 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8954 assert(dst
.type() == RegType::sgpr
);
8956 if (dst
.size() == 1) {
8957 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8959 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8960 for (unsigned i
= 0; i
< dst
.size(); i
++)
8961 vec
->operands
[i
] = Operand(0u);
8962 vec
->definitions
[0] = Definition(dst
);
8963 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8967 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8969 Builder
bld(ctx
->program
, ctx
->block
);
8970 Block
*logical_target
;
8971 append_logical_end(ctx
->block
);
8972 unsigned idx
= ctx
->block
->index
;
8974 switch (instr
->type
) {
8975 case nir_jump_break
:
8976 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8977 add_logical_edge(idx
, logical_target
);
8978 ctx
->block
->kind
|= block_kind_break
;
8980 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8981 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8982 /* uniform break - directly jump out of the loop */
8983 ctx
->block
->kind
|= block_kind_uniform
;
8984 ctx
->cf_info
.has_branch
= true;
8985 bld
.branch(aco_opcode::p_branch
);
8986 add_linear_edge(idx
, logical_target
);
8989 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8990 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8992 case nir_jump_continue
:
8993 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8994 add_logical_edge(idx
, logical_target
);
8995 ctx
->block
->kind
|= block_kind_continue
;
8997 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8998 /* for potential uniform breaks after this continue,
8999 we must ensure that they are handled correctly */
9000 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9001 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9002 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9004 /* uniform continue - directly jump to the loop header */
9005 ctx
->block
->kind
|= block_kind_uniform
;
9006 ctx
->cf_info
.has_branch
= true;
9007 bld
.branch(aco_opcode::p_branch
);
9008 add_linear_edge(idx
, logical_target
);
9013 fprintf(stderr
, "Unknown NIR jump instr: ");
9014 nir_print_instr(&instr
->instr
, stderr
);
9015 fprintf(stderr
, "\n");
9019 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9020 ctx
->cf_info
.exec_potentially_empty_break
= true;
9021 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9024 /* remove critical edges from linear CFG */
9025 bld
.branch(aco_opcode::p_branch
);
9026 Block
* break_block
= ctx
->program
->create_and_insert_block();
9027 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9028 break_block
->kind
|= block_kind_uniform
;
9029 add_linear_edge(idx
, break_block
);
9030 /* the loop_header pointer might be invalidated by this point */
9031 if (instr
->type
== nir_jump_continue
)
9032 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9033 add_linear_edge(break_block
->index
, logical_target
);
9034 bld
.reset(break_block
);
9035 bld
.branch(aco_opcode::p_branch
);
9037 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9038 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9039 add_linear_edge(idx
, continue_block
);
9040 append_logical_start(continue_block
);
9041 ctx
->block
= continue_block
;
9045 void visit_block(isel_context
*ctx
, nir_block
*block
)
9047 nir_foreach_instr(instr
, block
) {
9048 switch (instr
->type
) {
9049 case nir_instr_type_alu
:
9050 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9052 case nir_instr_type_load_const
:
9053 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9055 case nir_instr_type_intrinsic
:
9056 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9058 case nir_instr_type_tex
:
9059 visit_tex(ctx
, nir_instr_as_tex(instr
));
9061 case nir_instr_type_phi
:
9062 visit_phi(ctx
, nir_instr_as_phi(instr
));
9064 case nir_instr_type_ssa_undef
:
9065 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9067 case nir_instr_type_deref
:
9069 case nir_instr_type_jump
:
9070 visit_jump(ctx
, nir_instr_as_jump(instr
));
9073 fprintf(stderr
, "Unknown NIR instr type: ");
9074 nir_print_instr(instr
, stderr
);
9075 fprintf(stderr
, "\n");
9080 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9081 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9086 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9087 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9089 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9090 RegClass rc
= vals
[0].regClass();
9092 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9094 unsigned next_pred
= 1;
9096 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9097 Block
& block
= ctx
->program
->blocks
[idx
];
9098 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9099 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9103 if (block
.kind
& block_kind_continue
) {
9104 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9109 bool all_same
= true;
9110 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9111 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9115 val
= vals
[block
.linear_preds
[0] - first
];
9117 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9118 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9119 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9120 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9121 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9122 phi
->definitions
[0] = Definition(val
.getTemp());
9123 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9125 vals
[idx
- first
] = val
;
9128 return vals
[last
- first
];
9131 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9133 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9134 append_logical_end(ctx
->block
);
9135 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9136 Builder
bld(ctx
->program
, ctx
->block
);
9137 bld
.branch(aco_opcode::p_branch
);
9138 unsigned loop_preheader_idx
= ctx
->block
->index
;
9140 Block loop_exit
= Block();
9141 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9142 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9144 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9145 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9146 loop_header
->kind
|= block_kind_loop_header
;
9147 add_edge(loop_preheader_idx
, loop_header
);
9148 ctx
->block
= loop_header
;
9150 /* emit loop body */
9151 unsigned loop_header_idx
= loop_header
->index
;
9152 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9153 append_logical_start(ctx
->block
);
9154 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9156 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9157 if (!ctx
->cf_info
.has_branch
) {
9158 append_logical_end(ctx
->block
);
9159 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9160 /* Discards can result in code running with an empty exec mask.
9161 * This would result in divergent breaks not ever being taken. As a
9162 * workaround, break the loop when the loop mask is empty instead of
9163 * always continuing. */
9164 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9165 unsigned block_idx
= ctx
->block
->index
;
9167 /* create helper blocks to avoid critical edges */
9168 Block
*break_block
= ctx
->program
->create_and_insert_block();
9169 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9170 break_block
->kind
= block_kind_uniform
;
9171 bld
.reset(break_block
);
9172 bld
.branch(aco_opcode::p_branch
);
9173 add_linear_edge(block_idx
, break_block
);
9174 add_linear_edge(break_block
->index
, &loop_exit
);
9176 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9177 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9178 continue_block
->kind
= block_kind_uniform
;
9179 bld
.reset(continue_block
);
9180 bld
.branch(aco_opcode::p_branch
);
9181 add_linear_edge(block_idx
, continue_block
);
9182 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9184 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9185 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9186 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9188 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9189 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9190 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9192 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9195 bld
.reset(ctx
->block
);
9196 bld
.branch(aco_opcode::p_branch
);
9199 /* Fixup phis in loop header from unreachable blocks.
9200 * has_branch/has_divergent_branch also indicates if the loop ends with a
9201 * break/continue instruction, but we don't emit those if unreachable=true */
9203 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9204 bool linear
= ctx
->cf_info
.has_branch
;
9205 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9206 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9207 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9208 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9209 /* the last operand should be the one that needs to be removed */
9210 instr
->operands
.pop_back();
9211 } else if (!is_phi(instr
)) {
9217 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9218 * and the previous one shouldn't both happen at once because a break in the
9219 * merge block would get CSE'd */
9220 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9221 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9222 Operand vals
[num_vals
];
9223 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9224 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9225 if (ctx
->cf_info
.has_branch
)
9226 instr
->operands
.pop_back();
9228 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9229 } else if (!is_phi(instr
)) {
9235 ctx
->cf_info
.has_branch
= false;
9237 // TODO: if the loop has not a single exit, we must add one °°
9238 /* emit loop successor block */
9239 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9240 append_logical_start(ctx
->block
);
9243 // TODO: check if it is beneficial to not branch on continues
9244 /* trim linear phis in loop header */
9245 for (auto&& instr
: loop_entry
->instructions
) {
9246 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9247 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9248 new_phi
->definitions
[0] = instr
->definitions
[0];
9249 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9250 new_phi
->operands
[i
] = instr
->operands
[i
];
9251 /* check that the remaining operands are all the same */
9252 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9253 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9254 instr
.swap(new_phi
);
9255 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9264 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9268 append_logical_end(ctx
->block
);
9269 ctx
->block
->kind
|= block_kind_branch
;
9271 /* branch to linear then block */
9272 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9273 aco_ptr
<Pseudo_branch_instruction
> branch
;
9274 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9275 branch
->operands
[0] = Operand(cond
);
9276 ctx
->block
->instructions
.push_back(std::move(branch
));
9278 ic
->BB_if_idx
= ctx
->block
->index
;
9279 ic
->BB_invert
= Block();
9280 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9281 /* Invert blocks are intentionally not marked as top level because they
9282 * are not part of the logical cfg. */
9283 ic
->BB_invert
.kind
|= block_kind_invert
;
9284 ic
->BB_endif
= Block();
9285 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9286 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9288 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9289 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9290 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9291 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9292 ctx
->cf_info
.parent_if
.is_divergent
= true;
9294 /* divergent branches use cbranch_execz */
9295 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9296 ctx
->cf_info
.exec_potentially_empty_break
= false;
9297 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9299 /** emit logical then block */
9300 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9301 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9302 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9303 ctx
->block
= BB_then_logical
;
9304 append_logical_start(BB_then_logical
);
9307 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9309 Block
*BB_then_logical
= ctx
->block
;
9310 append_logical_end(BB_then_logical
);
9311 /* branch from logical then block to invert block */
9312 aco_ptr
<Pseudo_branch_instruction
> branch
;
9313 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9314 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9315 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9316 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9317 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9318 BB_then_logical
->kind
|= block_kind_uniform
;
9319 assert(!ctx
->cf_info
.has_branch
);
9320 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9321 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9323 /** emit linear then block */
9324 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9325 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9326 BB_then_linear
->kind
|= block_kind_uniform
;
9327 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9328 /* branch from linear then block to invert block */
9329 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9330 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9331 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9333 /** emit invert merge block */
9334 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9335 ic
->invert_idx
= ctx
->block
->index
;
9337 /* branch to linear else block (skip else) */
9338 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9339 branch
->operands
[0] = Operand(ic
->cond
);
9340 ctx
->block
->instructions
.push_back(std::move(branch
));
9342 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9343 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9344 ic
->exec_potentially_empty_break_depth_old
=
9345 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9346 /* divergent branches use cbranch_execz */
9347 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9348 ctx
->cf_info
.exec_potentially_empty_break
= false;
9349 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9351 /** emit logical else block */
9352 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9353 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9354 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9355 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9356 ctx
->block
= BB_else_logical
;
9357 append_logical_start(BB_else_logical
);
9360 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9362 Block
*BB_else_logical
= ctx
->block
;
9363 append_logical_end(BB_else_logical
);
9365 /* branch from logical else block to endif block */
9366 aco_ptr
<Pseudo_branch_instruction
> branch
;
9367 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9368 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9369 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9370 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9371 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9372 BB_else_logical
->kind
|= block_kind_uniform
;
9374 assert(!ctx
->cf_info
.has_branch
);
9375 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9378 /** emit linear else block */
9379 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9380 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9381 BB_else_linear
->kind
|= block_kind_uniform
;
9382 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9384 /* branch from linear else block to endif block */
9385 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9386 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9387 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9390 /** emit endif merge block */
9391 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9392 append_logical_start(ctx
->block
);
9395 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9396 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9397 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9398 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9399 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9400 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9401 !ctx
->cf_info
.parent_if
.is_divergent
) {
9402 ctx
->cf_info
.exec_potentially_empty_break
= false;
9403 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9405 /* uniform control flow never has an empty exec-mask */
9406 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9407 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9408 ctx
->cf_info
.exec_potentially_empty_break
= false;
9409 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9413 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9415 assert(cond
.regClass() == s1
);
9417 append_logical_end(ctx
->block
);
9418 ctx
->block
->kind
|= block_kind_uniform
;
9420 aco_ptr
<Pseudo_branch_instruction
> branch
;
9421 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9422 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9423 branch
->operands
[0] = Operand(cond
);
9424 branch
->operands
[0].setFixed(scc
);
9425 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9427 ic
->BB_if_idx
= ctx
->block
->index
;
9428 ic
->BB_endif
= Block();
9429 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9430 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9432 ctx
->cf_info
.has_branch
= false;
9433 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9435 /** emit then block */
9436 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9437 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9438 add_edge(ic
->BB_if_idx
, BB_then
);
9439 append_logical_start(BB_then
);
9440 ctx
->block
= BB_then
;
9443 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9445 Block
*BB_then
= ctx
->block
;
9447 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9448 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9450 if (!ic
->uniform_has_then_branch
) {
9451 append_logical_end(BB_then
);
9452 /* branch from then block to endif block */
9453 aco_ptr
<Pseudo_branch_instruction
> branch
;
9454 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9455 BB_then
->instructions
.emplace_back(std::move(branch
));
9456 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9457 if (!ic
->then_branch_divergent
)
9458 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9459 BB_then
->kind
|= block_kind_uniform
;
9462 ctx
->cf_info
.has_branch
= false;
9463 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9465 /** emit else block */
9466 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9467 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9468 add_edge(ic
->BB_if_idx
, BB_else
);
9469 append_logical_start(BB_else
);
9470 ctx
->block
= BB_else
;
9473 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9475 Block
*BB_else
= ctx
->block
;
9477 if (!ctx
->cf_info
.has_branch
) {
9478 append_logical_end(BB_else
);
9479 /* branch from then block to endif block */
9480 aco_ptr
<Pseudo_branch_instruction
> branch
;
9481 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9482 BB_else
->instructions
.emplace_back(std::move(branch
));
9483 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9484 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9485 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9486 BB_else
->kind
|= block_kind_uniform
;
9489 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9490 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9492 /** emit endif merge block */
9493 if (!ctx
->cf_info
.has_branch
) {
9494 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9495 append_logical_start(ctx
->block
);
9499 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9501 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9502 Builder
bld(ctx
->program
, ctx
->block
);
9503 aco_ptr
<Pseudo_branch_instruction
> branch
;
9506 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9508 * Uniform conditionals are represented in the following way*) :
9510 * The linear and logical CFG:
9513 * BB_THEN (logical) BB_ELSE (logical)
9517 * *) Exceptions may be due to break and continue statements within loops
9518 * If a break/continue happens within uniform control flow, it branches
9519 * to the loop exit/entry block. Otherwise, it branches to the next
9523 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9524 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9525 cond
= bool_to_scalar_condition(ctx
, cond
);
9527 begin_uniform_if_then(ctx
, &ic
, cond
);
9528 visit_cf_list(ctx
, &if_stmt
->then_list
);
9530 begin_uniform_if_else(ctx
, &ic
);
9531 visit_cf_list(ctx
, &if_stmt
->else_list
);
9533 end_uniform_if(ctx
, &ic
);
9534 } else { /* non-uniform condition */
9536 * To maintain a logical and linear CFG without critical edges,
9537 * non-uniform conditionals are represented in the following way*) :
9542 * BB_THEN (logical) BB_THEN (linear)
9544 * BB_INVERT (linear)
9546 * BB_ELSE (logical) BB_ELSE (linear)
9553 * BB_THEN (logical) BB_ELSE (logical)
9557 * *) Exceptions may be due to break and continue statements within loops
9560 begin_divergent_if_then(ctx
, &ic
, cond
);
9561 visit_cf_list(ctx
, &if_stmt
->then_list
);
9563 begin_divergent_if_else(ctx
, &ic
);
9564 visit_cf_list(ctx
, &if_stmt
->else_list
);
9566 end_divergent_if(ctx
, &ic
);
9569 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9572 static bool visit_cf_list(isel_context
*ctx
,
9573 struct exec_list
*list
)
9575 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9576 switch (node
->type
) {
9577 case nir_cf_node_block
:
9578 visit_block(ctx
, nir_cf_node_as_block(node
));
9580 case nir_cf_node_if
:
9581 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9584 case nir_cf_node_loop
:
9585 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9588 unreachable("unimplemented cf list type");
9594 static void create_null_export(isel_context
*ctx
)
9596 /* Some shader stages always need to have exports.
9597 * So when there is none, we need to add a null export.
9600 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9601 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9602 Builder
bld(ctx
->program
, ctx
->block
);
9603 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9604 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9607 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9609 assert(ctx
->stage
== vertex_vs
||
9610 ctx
->stage
== tess_eval_vs
||
9611 ctx
->stage
== gs_copy_vs
||
9612 ctx
->stage
== ngg_vertex_gs
||
9613 ctx
->stage
== ngg_tess_eval_gs
);
9615 int offset
= (ctx
->stage
& sw_tes
)
9616 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9617 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9618 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9619 if (!is_pos
&& !mask
)
9621 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9623 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9624 exp
->enabled_mask
= mask
;
9625 for (unsigned i
= 0; i
< 4; ++i
) {
9626 if (mask
& (1 << i
))
9627 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9629 exp
->operands
[i
] = Operand(v1
);
9631 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9632 * Setting valid_mask=1 prevents it and has no other effect.
9634 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9636 exp
->compressed
= false;
9638 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9640 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9641 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9646 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9648 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9649 exp
->enabled_mask
= 0;
9650 for (unsigned i
= 0; i
< 4; ++i
)
9651 exp
->operands
[i
] = Operand(v1
);
9652 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9653 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9654 exp
->enabled_mask
|= 0x1;
9656 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9657 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9658 exp
->enabled_mask
|= 0x4;
9660 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9661 if (ctx
->options
->chip_class
< GFX9
) {
9662 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9663 exp
->enabled_mask
|= 0x8;
9665 Builder
bld(ctx
->program
, ctx
->block
);
9667 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9668 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9669 if (exp
->operands
[2].isTemp())
9670 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9672 exp
->operands
[2] = Operand(out
);
9673 exp
->enabled_mask
|= 0x4;
9676 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9678 exp
->compressed
= false;
9679 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9680 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9683 static void create_export_phis(isel_context
*ctx
)
9685 /* Used when exports are needed, but the output temps are defined in a preceding block.
9686 * This function will set up phis in order to access the outputs in the next block.
9689 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9690 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9691 ctx
->block
->instructions
.pop_back();
9693 Builder
bld(ctx
->program
, ctx
->block
);
9695 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9696 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9697 for (unsigned i
= 0; i
< 4; ++i
) {
9698 if (!(mask
& (1 << i
)))
9701 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9702 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9703 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9707 bld
.insert(std::move(logical_start
));
9710 static void create_vs_exports(isel_context
*ctx
)
9712 assert(ctx
->stage
== vertex_vs
||
9713 ctx
->stage
== tess_eval_vs
||
9714 ctx
->stage
== gs_copy_vs
||
9715 ctx
->stage
== ngg_vertex_gs
||
9716 ctx
->stage
== ngg_tess_eval_gs
);
9718 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9719 ? &ctx
->program
->info
->tes
.outinfo
9720 : &ctx
->program
->info
->vs
.outinfo
;
9722 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9723 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9724 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9727 if (ctx
->options
->key
.has_multiview_view_index
) {
9728 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9729 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9732 /* the order these position exports are created is important */
9734 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9735 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9736 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9737 exported_pos
= true;
9739 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9740 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9741 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9742 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9744 if (ctx
->export_clip_dists
) {
9745 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9746 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9747 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9748 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9751 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9752 if (i
< VARYING_SLOT_VAR0
&&
9753 i
!= VARYING_SLOT_LAYER
&&
9754 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9755 i
!= VARYING_SLOT_VIEWPORT
)
9758 export_vs_varying(ctx
, i
, false, NULL
);
9762 create_null_export(ctx
);
9765 static bool export_fs_mrt_z(isel_context
*ctx
)
9767 Builder
bld(ctx
->program
, ctx
->block
);
9768 unsigned enabled_channels
= 0;
9772 for (unsigned i
= 0; i
< 4; ++i
) {
9773 values
[i
] = Operand(v1
);
9776 /* Both stencil and sample mask only need 16-bits. */
9777 if (!ctx
->program
->info
->ps
.writes_z
&&
9778 (ctx
->program
->info
->ps
.writes_stencil
||
9779 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9780 compr
= true; /* COMPR flag */
9782 if (ctx
->program
->info
->ps
.writes_stencil
) {
9783 /* Stencil should be in X[23:16]. */
9784 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9785 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9786 enabled_channels
|= 0x3;
9789 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9790 /* SampleMask should be in Y[15:0]. */
9791 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9792 enabled_channels
|= 0xc;
9795 if (ctx
->program
->info
->ps
.writes_z
) {
9796 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9797 enabled_channels
|= 0x1;
9800 if (ctx
->program
->info
->ps
.writes_stencil
) {
9801 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9802 enabled_channels
|= 0x2;
9805 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9806 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9807 enabled_channels
|= 0x4;
9811 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9812 * writemask component.
9814 if (ctx
->options
->chip_class
== GFX6
&&
9815 ctx
->options
->family
!= CHIP_OLAND
&&
9816 ctx
->options
->family
!= CHIP_HAINAN
) {
9817 enabled_channels
|= 0x1;
9820 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9821 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9826 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9828 Builder
bld(ctx
->program
, ctx
->block
);
9829 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9832 for (unsigned i
= 0; i
< 4; ++i
) {
9833 if (write_mask
& (1 << i
)) {
9834 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9836 values
[i
] = Operand(v1
);
9840 unsigned target
, col_format
;
9841 unsigned enabled_channels
= 0;
9842 aco_opcode compr_op
= (aco_opcode
)0;
9844 slot
-= FRAG_RESULT_DATA0
;
9845 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9846 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9848 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9849 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9850 bool is_16bit
= values
[0].regClass() == v2b
;
9854 case V_028714_SPI_SHADER_ZERO
:
9855 enabled_channels
= 0; /* writemask */
9856 target
= V_008DFC_SQ_EXP_NULL
;
9859 case V_028714_SPI_SHADER_32_R
:
9860 enabled_channels
= 1;
9863 case V_028714_SPI_SHADER_32_GR
:
9864 enabled_channels
= 0x3;
9867 case V_028714_SPI_SHADER_32_AR
:
9868 if (ctx
->options
->chip_class
>= GFX10
) {
9869 /* Special case: on GFX10, the outputs are different for 32_AR */
9870 enabled_channels
= 0x3;
9871 values
[1] = values
[3];
9872 values
[3] = Operand(v1
);
9874 enabled_channels
= 0x9;
9878 case V_028714_SPI_SHADER_FP16_ABGR
:
9879 enabled_channels
= 0x5;
9880 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9882 if (ctx
->options
->chip_class
>= GFX9
) {
9883 /* Pack the FP16 values together instead of converting them to
9884 * FP32 and back to FP16.
9885 * TODO: use p_create_vector and let the compiler optimizes.
9887 compr_op
= aco_opcode::v_pack_b32_f16
;
9889 for (unsigned i
= 0; i
< 4; i
++) {
9890 if ((write_mask
>> i
) & 1)
9891 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9897 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9898 enabled_channels
= 0x5;
9899 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9900 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9902 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9906 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9907 enabled_channels
= 0x5;
9908 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9909 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
9911 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9915 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9916 enabled_channels
= 0x5;
9917 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9918 if (is_int8
|| is_int10
) {
9920 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9921 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9923 for (unsigned i
= 0; i
< 4; i
++) {
9924 if ((write_mask
>> i
) & 1) {
9925 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9926 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9930 } else if (is_16bit
) {
9931 for (unsigned i
= 0; i
< 4; i
++) {
9932 if ((write_mask
>> i
) & 1) {
9933 Temp tmp
= convert_int(bld
, values
[i
].getTemp(), 16, 32, false);
9934 values
[i
] = Operand(tmp
);
9941 case V_028714_SPI_SHADER_SINT16_ABGR
:
9942 enabled_channels
= 0x5;
9943 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9944 if (is_int8
|| is_int10
) {
9946 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9947 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9948 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9949 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9951 for (unsigned i
= 0; i
< 4; i
++) {
9952 if ((write_mask
>> i
) & 1) {
9953 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9954 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9956 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9957 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9961 } else if (is_16bit
) {
9962 for (unsigned i
= 0; i
< 4; i
++) {
9963 if ((write_mask
>> i
) & 1) {
9964 Temp tmp
= convert_int(bld
, values
[i
].getTemp(), 16, 32, true);
9965 values
[i
] = Operand(tmp
);
9971 case V_028714_SPI_SHADER_32_ABGR
:
9972 enabled_channels
= 0xF;
9979 if (target
== V_008DFC_SQ_EXP_NULL
)
9982 if ((bool) compr_op
) {
9983 for (int i
= 0; i
< 2; i
++) {
9984 /* check if at least one of the values to be compressed is enabled */
9985 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9987 enabled_channels
|= enabled
<< (i
*2);
9988 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9989 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9990 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9992 values
[i
] = Operand(v1
);
9995 values
[2] = Operand(v1
);
9996 values
[3] = Operand(v1
);
9998 for (int i
= 0; i
< 4; i
++)
9999 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10002 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10003 enabled_channels
, target
, (bool) compr_op
);
10007 static void create_fs_exports(isel_context
*ctx
)
10009 bool exported
= false;
10011 /* Export depth, stencil and sample mask. */
10012 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10013 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10014 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10015 exported
|= export_fs_mrt_z(ctx
);
10017 /* Export all color render targets. */
10018 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10019 if (ctx
->outputs
.mask
[i
])
10020 exported
|= export_fs_mrt_color(ctx
, i
);
10023 create_null_export(ctx
);
10026 static void write_tcs_tess_factors(isel_context
*ctx
)
10028 unsigned outer_comps
;
10029 unsigned inner_comps
;
10031 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10048 Builder
bld(ctx
->program
, ctx
->block
);
10050 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10051 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10052 bld
.sopp(aco_opcode::s_barrier
);
10054 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10055 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10057 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10058 if_context ic_invocation_id_is_zero
;
10059 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10060 bld
.reset(ctx
->block
);
10062 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10064 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10065 unsigned stride
= inner_comps
+ outer_comps
;
10066 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10070 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10072 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10074 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10075 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10076 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10078 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10079 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10081 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10082 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10083 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10084 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10087 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10088 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10089 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10090 unsigned tf_const_offset
= 0;
10092 if (ctx
->program
->chip_class
<= GFX8
) {
10093 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10094 if_context ic_rel_patch_id_is_zero
;
10095 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10096 bld
.reset(ctx
->block
);
10098 /* Store the dynamic HS control word. */
10099 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10100 bld
.mubuf(aco_opcode::buffer_store_dword
,
10101 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10102 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10103 /* disable_wqm */ false, /* glc */ true);
10104 tf_const_offset
+= 4;
10106 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10107 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10108 bld
.reset(ctx
->block
);
10111 assert(stride
== 2 || stride
== 4 || stride
== 6);
10112 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10113 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10115 /* Store to offchip for TES to read - only if TES reads them */
10116 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10117 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10118 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10120 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10121 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10123 if (likely(inner_comps
)) {
10124 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10125 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10129 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10130 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10133 static void emit_stream_output(isel_context
*ctx
,
10134 Temp
const *so_buffers
,
10135 Temp
const *so_write_offset
,
10136 const struct radv_stream_output
*output
)
10138 unsigned num_comps
= util_bitcount(output
->component_mask
);
10139 unsigned writemask
= (1 << num_comps
) - 1;
10140 unsigned loc
= output
->location
;
10141 unsigned buf
= output
->buffer
;
10143 assert(num_comps
&& num_comps
<= 4);
10144 if (!num_comps
|| num_comps
> 4)
10147 unsigned start
= ffs(output
->component_mask
) - 1;
10150 bool all_undef
= true;
10151 assert(ctx
->stage
& hw_vs
);
10152 for (unsigned i
= 0; i
< num_comps
; i
++) {
10153 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10154 all_undef
= all_undef
&& !out
[i
].id();
10159 while (writemask
) {
10161 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10162 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10163 /* GFX6 doesn't support storing vec3, split it. */
10164 writemask
|= 1u << (start
+ 2);
10168 unsigned offset
= output
->offset
+ start
* 4;
10170 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10171 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10172 for (int i
= 0; i
< count
; ++i
)
10173 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10174 vec
->definitions
[0] = Definition(write_data
);
10175 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10180 opcode
= aco_opcode::buffer_store_dword
;
10183 opcode
= aco_opcode::buffer_store_dwordx2
;
10186 opcode
= aco_opcode::buffer_store_dwordx3
;
10189 opcode
= aco_opcode::buffer_store_dwordx4
;
10192 unreachable("Unsupported dword count.");
10195 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10196 store
->operands
[0] = Operand(so_buffers
[buf
]);
10197 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10198 store
->operands
[2] = Operand((uint32_t) 0);
10199 store
->operands
[3] = Operand(write_data
);
10200 if (offset
> 4095) {
10201 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10202 Builder
bld(ctx
->program
, ctx
->block
);
10203 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10205 store
->offset
= offset
;
10207 store
->offen
= true;
10209 store
->dlc
= false;
10211 store
->can_reorder
= true;
10212 ctx
->block
->instructions
.emplace_back(std::move(store
));
10216 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10218 Builder
bld(ctx
->program
, ctx
->block
);
10220 Temp so_buffers
[4];
10221 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10222 for (unsigned i
= 0; i
< 4; i
++) {
10223 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10227 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10228 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10231 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10232 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10234 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10236 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10239 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10241 bld
.reset(ctx
->block
);
10243 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10245 Temp so_write_offset
[4];
10247 for (unsigned i
= 0; i
< 4; i
++) {
10248 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10253 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10254 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10255 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10256 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10258 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10260 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10261 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10262 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10263 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10267 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10268 struct radv_stream_output
*output
=
10269 &ctx
->program
->info
->so
.outputs
[i
];
10270 if (stream
!= output
->stream
)
10273 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10276 begin_divergent_if_else(ctx
, &ic
);
10277 end_divergent_if(ctx
, &ic
);
10280 } /* end namespace */
10282 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10284 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10285 Builder
bld(ctx
->program
, ctx
->block
);
10286 constexpr unsigned hs_idx
= 1u;
10287 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10288 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10289 Operand((8u << 16) | (hs_idx
* 8u)));
10290 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10292 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10294 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10295 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10296 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10297 ls_has_nonzero_hs_threads
);
10298 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10299 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10300 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10301 ls_has_nonzero_hs_threads
);
10302 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10303 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10304 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10305 ls_has_nonzero_hs_threads
);
10307 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10308 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10309 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10312 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10314 /* Split all arguments except for the first (ring_offsets) and the last
10315 * (exec) so that the dead channels don't stay live throughout the program.
10317 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10318 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10319 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10320 startpgm
->definitions
[i
].regClass().size());
10325 void handle_bc_optimize(isel_context
*ctx
)
10327 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10328 Builder
bld(ctx
->program
, ctx
->block
);
10329 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10330 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10331 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10332 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10333 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10334 if (uses_center
&& uses_centroid
) {
10335 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10336 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10338 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10340 for (unsigned i
= 0; i
< 2; i
++) {
10341 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10342 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10343 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10344 persp_centroid
, persp_center
, sel
);
10346 ctx
->persp_centroid
= bld
.tmp(v2
);
10347 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10348 Operand(new_coord
[0]), Operand(new_coord
[1]));
10349 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10352 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10354 for (unsigned i
= 0; i
< 2; i
++) {
10355 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10356 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10357 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10358 linear_centroid
, linear_center
, sel
);
10360 ctx
->linear_centroid
= bld
.tmp(v2
);
10361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10362 Operand(new_coord
[0]), Operand(new_coord
[1]));
10363 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10368 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10370 Program
*program
= ctx
->program
;
10372 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10374 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10375 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10376 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10377 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10378 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10380 program
->next_fp_mode
.must_flush_denorms32
=
10381 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10382 program
->next_fp_mode
.must_flush_denorms16_64
=
10383 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10384 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10386 program
->next_fp_mode
.care_about_round32
=
10387 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10389 program
->next_fp_mode
.care_about_round16_64
=
10390 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10391 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10393 /* default to preserving fp16 and fp64 denorms, since it's free */
10394 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10395 program
->next_fp_mode
.denorm16_64
= 0;
10397 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10399 /* preserving fp32 denorms is expensive, so only do it if asked */
10400 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10401 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10403 program
->next_fp_mode
.denorm32
= 0;
10405 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10406 program
->next_fp_mode
.round32
= fp_round_tz
;
10408 program
->next_fp_mode
.round32
= fp_round_ne
;
10410 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10411 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10413 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10415 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10418 void cleanup_cfg(Program
*program
)
10420 /* create linear_succs/logical_succs */
10421 for (Block
& BB
: program
->blocks
) {
10422 for (unsigned idx
: BB
.linear_preds
)
10423 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10424 for (unsigned idx
: BB
.logical_preds
)
10425 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10429 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10431 Builder
bld(ctx
->program
, ctx
->block
);
10433 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10434 Temp count
= i
== 0
10435 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10436 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10437 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10439 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10442 if (ctx
->program
->wave_size
== 64) {
10443 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10444 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10445 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10447 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10448 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10454 bool ngg_early_prim_export(isel_context
*ctx
)
10456 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10460 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10462 Builder
bld(ctx
->program
, ctx
->block
);
10464 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10465 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10467 /* Get the id of the current wave within the threadgroup (workgroup) */
10468 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10469 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10471 /* Execute the following code only on the first wave (wave id 0),
10472 * use the SCC def to tell if the wave id is zero or not.
10474 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10476 begin_uniform_if_then(ctx
, &ic
, cond
);
10477 begin_uniform_if_else(ctx
, &ic
);
10478 bld
.reset(ctx
->block
);
10480 /* Number of vertices output by VS/TES */
10481 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10482 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10483 /* Number of primitives output by VS/TES */
10484 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10485 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10487 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10488 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10489 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10491 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10492 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10494 end_uniform_if(ctx
, &ic
);
10496 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10497 bld
.reset(ctx
->block
);
10498 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10501 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10503 Builder
bld(ctx
->program
, ctx
->block
);
10505 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10506 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10509 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10512 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10513 assert(vtxindex
[i
].id());
10516 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10520 /* The initial edge flag is always false in tess eval shaders. */
10521 if (ctx
->stage
== ngg_vertex_gs
) {
10522 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10523 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10527 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10532 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10534 Builder
bld(ctx
->program
, ctx
->block
);
10535 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10537 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10538 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10539 false /* compressed */, true/* done */, false /* valid mask */);
10542 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10544 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10545 * These must always come before VS exports.
10547 * It is recommended to do these as early as possible. They can be at the beginning when
10548 * there is no SW GS and the shader doesn't write edge flags.
10552 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10553 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10555 Builder
bld(ctx
->program
, ctx
->block
);
10556 constexpr unsigned max_vertices_per_primitive
= 3;
10557 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10559 if (ctx
->stage
== ngg_vertex_gs
) {
10560 /* TODO: optimize for points & lines */
10561 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10562 if (ctx
->shader
->info
.tess
.point_mode
)
10563 num_vertices_per_primitive
= 1;
10564 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10565 num_vertices_per_primitive
= 2;
10567 unreachable("Unsupported NGG shader stage");
10570 Temp vtxindex
[max_vertices_per_primitive
];
10571 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10572 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10573 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10574 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10575 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10576 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10577 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10578 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10580 /* Export primitive data to the index buffer. */
10581 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10583 /* Export primitive ID. */
10584 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10585 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10586 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10587 Temp provoking_vtx_index
= vtxindex
[0];
10588 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10590 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10593 begin_divergent_if_else(ctx
, &ic
);
10594 end_divergent_if(ctx
, &ic
);
10597 void ngg_emit_nogs_output(isel_context
*ctx
)
10599 /* Emits NGG GS output, for stages that don't have SW GS. */
10602 Builder
bld(ctx
->program
, ctx
->block
);
10603 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10605 /* NGG streamout is currently disabled by default. */
10606 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10608 if (late_prim_export
) {
10609 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10610 create_export_phis(ctx
);
10611 /* Do what we need to do in the GS threads. */
10612 ngg_emit_nogs_gsthreads(ctx
);
10614 /* What comes next should be executed on ES threads. */
10615 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10616 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10617 bld
.reset(ctx
->block
);
10620 /* Export VS outputs */
10621 ctx
->block
->kind
|= block_kind_export_end
;
10622 create_vs_exports(ctx
);
10624 /* Export primitive ID */
10625 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10628 if (ctx
->stage
== ngg_vertex_gs
) {
10629 /* Wait for GS threads to store primitive ID in LDS. */
10630 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10631 bld
.sopp(aco_opcode::s_barrier
);
10633 /* Calculate LDS address where the GS threads stored the primitive ID. */
10634 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10635 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10636 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10637 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10638 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10639 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10641 /* Load primitive ID from LDS. */
10642 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10643 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10644 /* TES: Just use the patch ID as the primitive ID. */
10645 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10647 unreachable("unsupported NGG shader stage.");
10650 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10651 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10653 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10656 if (late_prim_export
) {
10657 begin_divergent_if_else(ctx
, &ic
);
10658 end_divergent_if(ctx
, &ic
);
10659 bld
.reset(ctx
->block
);
10663 void select_program(Program
*program
,
10664 unsigned shader_count
,
10665 struct nir_shader
*const *shaders
,
10666 ac_shader_config
* config
,
10667 struct radv_shader_args
*args
)
10669 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10670 if_context ic_merged_wave_info
;
10671 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10673 for (unsigned i
= 0; i
< shader_count
; i
++) {
10674 nir_shader
*nir
= shaders
[i
];
10675 init_context(&ctx
, nir
);
10677 setup_fp_mode(&ctx
, nir
);
10680 /* needs to be after init_context() for FS */
10681 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10682 append_logical_start(ctx
.block
);
10684 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10685 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10687 split_arguments(&ctx
, startpgm
);
10691 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10693 if (ngg_early_prim_export(&ctx
))
10694 ngg_emit_nogs_gsthreads(&ctx
);
10697 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10698 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10699 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10700 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10701 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10702 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10703 ctx
.stage
== tess_eval_geometry_gs
));
10705 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10706 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10707 if (check_merged_wave_info
) {
10708 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10709 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10713 Builder
bld(ctx
.program
, ctx
.block
);
10715 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10716 bld
.sopp(aco_opcode::s_barrier
);
10718 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10719 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10721 } else if (ctx
.stage
== geometry_gs
)
10722 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10724 if (ctx
.stage
== fragment_fs
)
10725 handle_bc_optimize(&ctx
);
10727 visit_cf_list(&ctx
, &func
->body
);
10729 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10730 emit_streamout(&ctx
, 0);
10732 if (ctx
.stage
& hw_vs
) {
10733 create_vs_exports(&ctx
);
10734 ctx
.block
->kind
|= block_kind_export_end
;
10735 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10736 ngg_emit_nogs_output(&ctx
);
10737 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10738 Builder
bld(ctx
.program
, ctx
.block
);
10739 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10740 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10741 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10742 write_tcs_tess_factors(&ctx
);
10745 if (ctx
.stage
== fragment_fs
) {
10746 create_fs_exports(&ctx
);
10747 ctx
.block
->kind
|= block_kind_export_end
;
10750 if (endif_merged_wave_info
) {
10751 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10752 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10755 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10756 ngg_emit_nogs_output(&ctx
);
10758 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10759 /* Outputs of the previous stage are inputs to the next stage */
10760 ctx
.inputs
= ctx
.outputs
;
10761 ctx
.outputs
= shader_io_state();
10765 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10767 append_logical_end(ctx
.block
);
10768 ctx
.block
->kind
|= block_kind_uniform
;
10769 Builder
bld(ctx
.program
, ctx
.block
);
10770 if (ctx
.program
->wb_smem_l1_on_end
)
10771 bld
.smem(aco_opcode::s_dcache_wb
, false);
10772 bld
.sopp(aco_opcode::s_endpgm
);
10774 cleanup_cfg(program
);
10777 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10778 ac_shader_config
* config
,
10779 struct radv_shader_args
*args
)
10781 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10783 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10784 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10785 program
->next_fp_mode
.must_flush_denorms32
= false;
10786 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10787 program
->next_fp_mode
.care_about_round32
= false;
10788 program
->next_fp_mode
.care_about_round16_64
= false;
10789 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10790 program
->next_fp_mode
.denorm32
= 0;
10791 program
->next_fp_mode
.round32
= fp_round_ne
;
10792 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10793 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10795 add_startpgm(&ctx
);
10796 append_logical_start(ctx
.block
);
10798 Builder
bld(ctx
.program
, ctx
.block
);
10800 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10802 Operand
stream_id(0u);
10803 if (args
->shader_info
->so
.num_outputs
)
10804 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10805 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10807 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10809 std::stack
<Block
> endif_blocks
;
10811 for (unsigned stream
= 0; stream
< 4; stream
++) {
10812 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10815 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10816 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10819 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10821 unsigned BB_if_idx
= ctx
.block
->index
;
10822 Block BB_endif
= Block();
10823 if (!stream_id
.isConstant()) {
10825 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10826 append_logical_end(ctx
.block
);
10827 ctx
.block
->kind
|= block_kind_uniform
;
10828 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10830 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10832 ctx
.block
= ctx
.program
->create_and_insert_block();
10833 add_edge(BB_if_idx
, ctx
.block
);
10834 bld
.reset(ctx
.block
);
10835 append_logical_start(ctx
.block
);
10838 unsigned offset
= 0;
10839 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10840 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10843 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10844 unsigned length
= util_last_bit(output_usage_mask
);
10845 for (unsigned j
= 0; j
< length
; ++j
) {
10846 if (!(output_usage_mask
& (1 << j
)))
10849 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10850 Temp voffset
= vtx_offset
;
10851 if (const_offset
>= 4096u) {
10852 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10853 const_offset
%= 4096u;
10856 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10857 mubuf
->definitions
[0] = bld
.def(v1
);
10858 mubuf
->operands
[0] = Operand(gsvs_ring
);
10859 mubuf
->operands
[1] = Operand(voffset
);
10860 mubuf
->operands
[2] = Operand(0u);
10861 mubuf
->offen
= true;
10862 mubuf
->offset
= const_offset
;
10865 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10866 mubuf
->barrier
= barrier_none
;
10867 mubuf
->can_reorder
= true;
10869 ctx
.outputs
.mask
[i
] |= 1 << j
;
10870 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10872 bld
.insert(std::move(mubuf
));
10878 if (args
->shader_info
->so
.num_outputs
) {
10879 emit_streamout(&ctx
, stream
);
10880 bld
.reset(ctx
.block
);
10884 create_vs_exports(&ctx
);
10885 ctx
.block
->kind
|= block_kind_export_end
;
10888 if (!stream_id
.isConstant()) {
10889 append_logical_end(ctx
.block
);
10891 /* branch from then block to endif block */
10892 bld
.branch(aco_opcode::p_branch
);
10893 add_edge(ctx
.block
->index
, &BB_endif
);
10894 ctx
.block
->kind
|= block_kind_uniform
;
10896 /* emit else block */
10897 ctx
.block
= ctx
.program
->create_and_insert_block();
10898 add_edge(BB_if_idx
, ctx
.block
);
10899 bld
.reset(ctx
.block
);
10900 append_logical_start(ctx
.block
);
10902 endif_blocks
.push(std::move(BB_endif
));
10906 while (!endif_blocks
.empty()) {
10907 Block BB_endif
= std::move(endif_blocks
.top());
10908 endif_blocks
.pop();
10910 Block
*BB_else
= ctx
.block
;
10912 append_logical_end(BB_else
);
10913 /* branch from else block to endif block */
10914 bld
.branch(aco_opcode::p_branch
);
10915 add_edge(BB_else
->index
, &BB_endif
);
10916 BB_else
->kind
|= block_kind_uniform
;
10918 /** emit endif merge block */
10919 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10920 bld
.reset(ctx
.block
);
10921 append_logical_start(ctx
.block
);
10924 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10926 append_logical_end(ctx
.block
);
10927 ctx
.block
->kind
|= block_kind_uniform
;
10928 bld
.sopp(aco_opcode::s_endpgm
);
10930 cleanup_cfg(program
);