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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool then_branch_divergent
;
93 static bool visit_cf_list(struct isel_context
*ctx
,
94 struct exec_list
*list
);
96 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
98 succ
->logical_preds
.emplace_back(pred_idx
);
102 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
104 succ
->linear_preds
.emplace_back(pred_idx
);
107 static void add_edge(unsigned pred_idx
, Block
*succ
)
109 add_logical_edge(pred_idx
, succ
);
110 add_linear_edge(pred_idx
, succ
);
113 static void append_logical_start(Block
*b
)
115 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
118 static void append_logical_end(Block
*b
)
120 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
123 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
125 assert(ctx
->allocated
[def
->index
].id());
126 return ctx
->allocated
[def
->index
];
129 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
130 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
132 Builder
bld(ctx
->program
, ctx
->block
);
133 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
134 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
136 if (ctx
->program
->wave_size
== 32) {
139 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
144 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
146 Builder
bld(ctx
->program
, ctx
->block
);
149 dst
= bld
.tmp(src
.regClass());
151 assert(src
.size() == dst
.size());
153 if (ctx
->stage
!= fragment_fs
) {
157 bld
.copy(Definition(dst
), src
);
161 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
162 ctx
->program
->needs_wqm
|= program_needs_wqm
;
166 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
168 if (index
.regClass() == s1
)
169 return bld
.readlane(bld
.def(s1
), data
, index
);
171 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
173 /* Currently not implemented on GFX6-7 */
174 assert(ctx
->options
->chip_class
>= GFX8
);
176 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
177 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
180 /* GFX10, wave64 mode:
181 * The bpermute instruction is limited to half-wave operation, which means that it can't
182 * properly support subgroup shuffle like older generations (or wave32 mode), so we
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
192 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
193 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
194 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
196 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
197 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
200 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
202 if (val
.type() == RegType::sgpr
) {
203 Builder
bld(ctx
->program
, ctx
->block
);
204 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
206 assert(val
.type() == RegType::vgpr
);
210 //assumes a != 0xffffffff
211 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
214 Builder
bld(ctx
->program
, ctx
->block
);
216 if (util_is_power_of_two_or_zero(b
)) {
217 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
221 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
223 assert(info
.multiplier
<= 0xffffffff);
225 bool pre_shift
= info
.pre_shift
!= 0;
226 bool increment
= info
.increment
!= 0;
227 bool multiply
= true;
228 bool post_shift
= info
.post_shift
!= 0;
230 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
231 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
235 Temp pre_shift_dst
= a
;
237 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
238 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
241 Temp increment_dst
= pre_shift_dst
;
243 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
244 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
247 Temp multiply_dst
= increment_dst
;
249 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
250 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
251 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
255 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
259 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
261 Builder
bld(ctx
->program
, ctx
->block
);
262 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
266 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
268 /* no need to extract the whole vector */
269 if (src
.regClass() == dst_rc
) {
274 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
275 Builder
bld(ctx
->program
, ctx
->block
);
276 auto it
= ctx
->allocated_vec
.find(src
.id());
277 /* the size check needs to be early because elements other than 0 may be garbage */
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f32
:
630 op
= aco_opcode::v_cmp_gt_f32
;
632 case aco_opcode::v_cmp_ge_f32
:
633 op
= aco_opcode::v_cmp_le_f32
;
635 case aco_opcode::v_cmp_lt_i32
:
636 op
= aco_opcode::v_cmp_gt_i32
;
638 case aco_opcode::v_cmp_ge_i32
:
639 op
= aco_opcode::v_cmp_le_i32
;
641 case aco_opcode::v_cmp_lt_u32
:
642 op
= aco_opcode::v_cmp_gt_u32
;
644 case aco_opcode::v_cmp_ge_u32
:
645 op
= aco_opcode::v_cmp_le_u32
;
647 case aco_opcode::v_cmp_lt_f64
:
648 op
= aco_opcode::v_cmp_gt_f64
;
650 case aco_opcode::v_cmp_ge_f64
:
651 op
= aco_opcode::v_cmp_le_f64
;
653 case aco_opcode::v_cmp_lt_i64
:
654 op
= aco_opcode::v_cmp_gt_i64
;
656 case aco_opcode::v_cmp_ge_i64
:
657 op
= aco_opcode::v_cmp_le_i64
;
659 case aco_opcode::v_cmp_lt_u64
:
660 op
= aco_opcode::v_cmp_gt_u64
;
662 case aco_opcode::v_cmp_ge_u64
:
663 op
= aco_opcode::v_cmp_le_u64
;
665 default: /* eq and ne are commutative */
672 src1
= as_vgpr(ctx
, src1
);
676 Builder
bld(ctx
->program
, ctx
->block
);
677 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
680 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
684 Builder
bld(ctx
->program
, ctx
->block
);
686 assert(dst
.regClass() == bld
.lm
);
687 assert(src0
.type() == RegType::sgpr
);
688 assert(src1
.type() == RegType::sgpr
);
689 assert(src0
.regClass() == src1
.regClass());
691 /* Emit the SALU comparison instruction */
692 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
693 /* Turn the result into a per-lane bool */
694 bool_to_vector_condition(ctx
, cmp
, dst
);
697 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
698 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
700 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
701 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
702 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
703 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
705 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
706 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
707 aco_opcode op
= use_valu
? v_op
: s_op
;
708 assert(op
!= aco_opcode::num_opcodes
);
709 assert(dst
.regClass() == ctx
->program
->lane_mask
);
712 emit_vopc_instruction(ctx
, instr
, op
, dst
);
714 emit_sopc_instruction(ctx
, instr
, op
, dst
);
717 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
719 Builder
bld(ctx
->program
, ctx
->block
);
720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
721 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
723 assert(dst
.regClass() == bld
.lm
);
724 assert(src0
.regClass() == bld
.lm
);
725 assert(src1
.regClass() == bld
.lm
);
727 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
730 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
732 Builder
bld(ctx
->program
, ctx
->block
);
733 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
734 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
735 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
737 assert(cond
.regClass() == bld
.lm
);
739 if (dst
.type() == RegType::vgpr
) {
740 aco_ptr
<Instruction
> bcsel
;
741 if (dst
.size() == 1) {
742 then
= as_vgpr(ctx
, then
);
743 els
= as_vgpr(ctx
, els
);
745 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
746 } else if (dst
.size() == 2) {
747 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
749 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
750 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
752 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
753 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
755 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
758 nir_print_instr(&instr
->instr
, stderr
);
759 fprintf(stderr
, "\n");
764 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
765 assert(dst
.regClass() == bld
.lm
);
766 assert(then
.regClass() == bld
.lm
);
767 assert(els
.regClass() == bld
.lm
);
770 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
771 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
772 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
773 assert(dst
.size() == then
.size());
774 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
775 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
777 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
778 nir_print_instr(&instr
->instr
, stderr
);
779 fprintf(stderr
, "\n");
784 /* divergent boolean bcsel
785 * this implements bcsel on bools: dst = s0 ? s1 : s2
786 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
787 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
789 if (cond
.id() != then
.id())
790 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
792 if (cond
.id() == els
.id())
793 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
795 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
796 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
799 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
800 aco_opcode op
, uint32_t undo
)
802 /* multiply by 16777216 to handle denormals */
803 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
804 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
805 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
806 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
807 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
809 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
811 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
814 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
816 if (ctx
->block
->fp_mode
.denorm32
== 0) {
817 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
821 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
824 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
826 if (ctx
->block
->fp_mode
.denorm32
== 0) {
827 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
831 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
834 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
836 if (ctx
->block
->fp_mode
.denorm32
== 0) {
837 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
841 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
844 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
846 if (ctx
->block
->fp_mode
.denorm32
== 0) {
847 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
851 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
854 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
856 if (ctx
->options
->chip_class
>= GFX7
)
857 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
859 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
860 /* TODO: create more efficient code! */
861 if (val
.type() == RegType::sgpr
)
862 val
= as_vgpr(ctx
, val
);
864 /* Split the input value. */
865 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
868 /* Extract the exponent and compute the unbiased value. */
869 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
871 /* Extract the fractional part. */
872 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
873 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
875 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
878 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
879 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
880 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
881 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
882 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
884 /* Get the sign bit. */
885 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
887 /* Decide the operation to apply depending on the unbiased exponent. */
888 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
889 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
890 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
891 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
892 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
893 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
895 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
898 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
900 if (ctx
->options
->chip_class
>= GFX7
)
901 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
903 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
904 Temp src0
= as_vgpr(ctx
, val
);
906 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
907 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
909 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
910 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
911 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
913 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
915 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
918 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
919 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
921 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
923 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
924 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
926 return add
->definitions
[0].getTemp();
929 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
931 if (!instr
->dest
.dest
.is_ssa
) {
932 fprintf(stderr
, "nir alu dst not in ssa: ");
933 nir_print_instr(&instr
->instr
, stderr
);
934 fprintf(stderr
, "\n");
937 Builder
bld(ctx
->program
, ctx
->block
);
938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
943 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
944 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
945 for (unsigned i
= 0; i
< instr
->dest
.dest
.ssa
.num_components
; ++i
) {
946 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
947 vec
->operands
[i
] = Operand
{elems
[i
]};
949 vec
->definitions
[0] = Definition(dst
);
950 ctx
->block
->instructions
.emplace_back(std::move(vec
));
951 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
955 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
956 aco_ptr
<Instruction
> mov
;
957 if (dst
.type() == RegType::sgpr
) {
958 if (src
.type() == RegType::vgpr
)
959 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
960 else if (src
.regClass() == s1
)
961 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
962 else if (src
.regClass() == s2
)
963 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
965 unreachable("wrong src register class for nir_op_imov");
966 } else if (dst
.regClass() == v1
) {
967 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
968 } else if (dst
.regClass() == v2
) {
969 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
971 nir_print_instr(&instr
->instr
, stderr
);
972 unreachable("Should have been lowered to scalar.");
977 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
978 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
979 assert(src
.regClass() == bld
.lm
);
980 assert(dst
.regClass() == bld
.lm
);
981 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
982 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
983 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
984 } else if (dst
.regClass() == v1
) {
985 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
986 } else if (dst
.type() == RegType::sgpr
) {
987 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
988 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
990 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
991 nir_print_instr(&instr
->instr
, stderr
);
992 fprintf(stderr
, "\n");
997 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
998 if (dst
.regClass() == v1
) {
999 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1000 } else if (dst
.regClass() == s1
) {
1001 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1002 } else if (dst
.size() == 2) {
1003 Temp src0
= bld
.tmp(dst
.type(), 1);
1004 Temp src1
= bld
.tmp(dst
.type(), 1);
1005 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1007 if (dst
.regClass() == s2
) {
1008 Temp carry
= bld
.tmp(s1
);
1009 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1010 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1011 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1013 Temp lower
= bld
.tmp(v1
);
1014 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1015 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1016 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1019 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1020 nir_print_instr(&instr
->instr
, stderr
);
1021 fprintf(stderr
, "\n");
1026 if (dst
.regClass() == s1
) {
1027 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1028 } else if (dst
.regClass() == v1
) {
1029 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1030 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1032 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1033 nir_print_instr(&instr
->instr
, stderr
);
1034 fprintf(stderr
, "\n");
1038 case nir_op_isign
: {
1039 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1040 if (dst
.regClass() == s1
) {
1041 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1042 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1043 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1044 } else if (dst
.regClass() == s2
) {
1045 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1047 if (ctx
->program
->chip_class
>= GFX8
)
1048 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1050 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1051 /* SCC gets zero-extended to 64 bit */
1052 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1053 } else if (dst
.regClass() == v1
) {
1054 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1055 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1056 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1057 } else if (dst
.regClass() == v2
) {
1058 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1059 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1060 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1061 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1062 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1063 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1065 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1066 nir_print_instr(&instr
->instr
, stderr
);
1067 fprintf(stderr
, "\n");
1072 if (dst
.regClass() == v1
) {
1073 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1074 } else if (dst
.regClass() == s1
) {
1075 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1077 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1078 nir_print_instr(&instr
->instr
, stderr
);
1079 fprintf(stderr
, "\n");
1084 if (dst
.regClass() == v1
) {
1085 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1086 } else if (dst
.regClass() == s1
) {
1087 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 if (dst
.regClass() == v1
) {
1097 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1098 } else if (dst
.regClass() == s1
) {
1099 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1108 if (dst
.regClass() == v1
) {
1109 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1110 } else if (dst
.regClass() == s1
) {
1111 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1121 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1122 } else if (dst
.regClass() == v1
) {
1123 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1124 } else if (dst
.regClass() == s1
) {
1125 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1126 } else if (dst
.regClass() == s2
) {
1127 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1129 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1130 nir_print_instr(&instr
->instr
, stderr
);
1131 fprintf(stderr
, "\n");
1136 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1137 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1138 } else if (dst
.regClass() == v1
) {
1139 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1140 } else if (dst
.regClass() == s1
) {
1141 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1142 } else if (dst
.regClass() == s2
) {
1143 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1145 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1146 nir_print_instr(&instr
->instr
, stderr
);
1147 fprintf(stderr
, "\n");
1152 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1153 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1154 } else if (dst
.regClass() == v1
) {
1155 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1156 } else if (dst
.regClass() == s1
) {
1157 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1158 } else if (dst
.regClass() == s2
) {
1159 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (dst
.regClass() == v1
) {
1169 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1170 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1171 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1172 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1173 } else if (dst
.regClass() == v2
) {
1174 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1175 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1176 } else if (dst
.regClass() == s2
) {
1177 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1178 } else if (dst
.regClass() == s1
) {
1179 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1181 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1182 nir_print_instr(&instr
->instr
, stderr
);
1183 fprintf(stderr
, "\n");
1188 if (dst
.regClass() == v1
) {
1189 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1190 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1191 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1192 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1193 } else if (dst
.regClass() == v2
) {
1194 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1195 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1196 } else if (dst
.regClass() == s1
) {
1197 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1198 } else if (dst
.regClass() == s2
) {
1199 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1201 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1202 nir_print_instr(&instr
->instr
, stderr
);
1203 fprintf(stderr
, "\n");
1208 if (dst
.regClass() == v1
) {
1209 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1210 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1211 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1212 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1213 } else if (dst
.regClass() == v2
) {
1214 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1215 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1216 } else if (dst
.regClass() == s1
) {
1217 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1218 } else if (dst
.regClass() == s2
) {
1219 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1221 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1222 nir_print_instr(&instr
->instr
, stderr
);
1223 fprintf(stderr
, "\n");
1227 case nir_op_find_lsb
: {
1228 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1229 if (src
.regClass() == s1
) {
1230 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1231 } else if (src
.regClass() == v1
) {
1232 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1233 } else if (src
.regClass() == s2
) {
1234 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1236 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1237 nir_print_instr(&instr
->instr
, stderr
);
1238 fprintf(stderr
, "\n");
1242 case nir_op_ufind_msb
:
1243 case nir_op_ifind_msb
: {
1244 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1245 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1246 aco_opcode op
= src
.regClass() == s2
?
1247 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1248 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1249 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1251 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1252 Operand(src
.size() * 32u - 1u), msb_rev
);
1253 Temp msb
= sub
.def(0).getTemp();
1254 Temp carry
= sub
.def(1).getTemp();
1256 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1257 } else if (src
.regClass() == v1
) {
1258 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1259 Temp msb_rev
= bld
.tmp(v1
);
1260 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1261 Temp msb
= bld
.tmp(v1
);
1262 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1263 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1265 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1266 nir_print_instr(&instr
->instr
, stderr
);
1267 fprintf(stderr
, "\n");
1271 case nir_op_bitfield_reverse
: {
1272 if (dst
.regClass() == s1
) {
1273 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1274 } else if (dst
.regClass() == v1
) {
1275 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1277 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1278 nir_print_instr(&instr
->instr
, stderr
);
1279 fprintf(stderr
, "\n");
1284 if (dst
.regClass() == s1
) {
1285 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1289 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1290 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1291 if (dst
.regClass() == v1
) {
1292 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1296 assert(src0
.size() == 2 && src1
.size() == 2);
1297 Temp src00
= bld
.tmp(src0
.type(), 1);
1298 Temp src01
= bld
.tmp(dst
.type(), 1);
1299 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1300 Temp src10
= bld
.tmp(src1
.type(), 1);
1301 Temp src11
= bld
.tmp(dst
.type(), 1);
1302 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1304 if (dst
.regClass() == s2
) {
1305 Temp carry
= bld
.tmp(s1
);
1306 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1307 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1308 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1309 } else if (dst
.regClass() == v2
) {
1310 Temp dst0
= bld
.tmp(v1
);
1311 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1312 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1313 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1315 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1316 nir_print_instr(&instr
->instr
, stderr
);
1317 fprintf(stderr
, "\n");
1321 case nir_op_uadd_sat
: {
1322 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1323 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1324 if (dst
.regClass() == s1
) {
1325 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1326 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1328 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1329 } else if (dst
.regClass() == v1
) {
1330 if (ctx
->options
->chip_class
>= GFX9
) {
1331 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1332 add
->operands
[0] = Operand(src0
);
1333 add
->operands
[1] = Operand(src1
);
1334 add
->definitions
[0] = Definition(dst
);
1336 ctx
->block
->instructions
.emplace_back(std::move(add
));
1338 if (src1
.regClass() != v1
)
1339 std::swap(src0
, src1
);
1340 assert(src1
.regClass() == v1
);
1341 Temp tmp
= bld
.tmp(v1
);
1342 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1343 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1346 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1347 nir_print_instr(&instr
->instr
, stderr
);
1348 fprintf(stderr
, "\n");
1352 case nir_op_uadd_carry
: {
1353 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1354 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1355 if (dst
.regClass() == s1
) {
1356 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1359 if (dst
.regClass() == v1
) {
1360 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1361 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1365 Temp src00
= bld
.tmp(src0
.type(), 1);
1366 Temp src01
= bld
.tmp(dst
.type(), 1);
1367 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1368 Temp src10
= bld
.tmp(src1
.type(), 1);
1369 Temp src11
= bld
.tmp(dst
.type(), 1);
1370 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1371 if (dst
.regClass() == s2
) {
1372 Temp carry
= bld
.tmp(s1
);
1373 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1374 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1375 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1376 } else if (dst
.regClass() == v2
) {
1377 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1378 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1379 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1380 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1382 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1383 nir_print_instr(&instr
->instr
, stderr
);
1384 fprintf(stderr
, "\n");
1389 if (dst
.regClass() == s1
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1394 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1395 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1396 if (dst
.regClass() == v1
) {
1397 bld
.vsub32(Definition(dst
), src0
, src1
);
1401 Temp src00
= bld
.tmp(src0
.type(), 1);
1402 Temp src01
= bld
.tmp(dst
.type(), 1);
1403 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1404 Temp src10
= bld
.tmp(src1
.type(), 1);
1405 Temp src11
= bld
.tmp(dst
.type(), 1);
1406 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1407 if (dst
.regClass() == s2
) {
1408 Temp carry
= bld
.tmp(s1
);
1409 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1410 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1412 } else if (dst
.regClass() == v2
) {
1413 Temp lower
= bld
.tmp(v1
);
1414 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1415 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1416 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1418 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1419 nir_print_instr(&instr
->instr
, stderr
);
1420 fprintf(stderr
, "\n");
1424 case nir_op_usub_borrow
: {
1425 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1426 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1427 if (dst
.regClass() == s1
) {
1428 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1430 } else if (dst
.regClass() == v1
) {
1431 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1432 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1436 Temp src00
= bld
.tmp(src0
.type(), 1);
1437 Temp src01
= bld
.tmp(dst
.type(), 1);
1438 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1439 Temp src10
= bld
.tmp(src1
.type(), 1);
1440 Temp src11
= bld
.tmp(dst
.type(), 1);
1441 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1442 if (dst
.regClass() == s2
) {
1443 Temp borrow
= bld
.tmp(s1
);
1444 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1445 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1446 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1447 } else if (dst
.regClass() == v2
) {
1448 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1449 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1450 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1451 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1453 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1454 nir_print_instr(&instr
->instr
, stderr
);
1455 fprintf(stderr
, "\n");
1460 if (dst
.regClass() == v1
) {
1461 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1462 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1463 } else if (dst
.regClass() == s1
) {
1464 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1466 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1467 nir_print_instr(&instr
->instr
, stderr
);
1468 fprintf(stderr
, "\n");
1472 case nir_op_umul_high
: {
1473 if (dst
.regClass() == v1
) {
1474 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1475 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1476 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1477 } else if (dst
.regClass() == s1
) {
1478 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1479 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1480 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1482 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1483 nir_print_instr(&instr
->instr
, stderr
);
1484 fprintf(stderr
, "\n");
1488 case nir_op_imul_high
: {
1489 if (dst
.regClass() == v1
) {
1490 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1491 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1492 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1493 } else if (dst
.regClass() == s1
) {
1494 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1495 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1496 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1498 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1499 nir_print_instr(&instr
->instr
, stderr
);
1500 fprintf(stderr
, "\n");
1505 if (dst
.size() == 1) {
1506 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1507 } else if (dst
.size() == 2) {
1508 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1509 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1511 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1512 nir_print_instr(&instr
->instr
, stderr
);
1513 fprintf(stderr
, "\n");
1518 if (dst
.size() == 1) {
1519 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1520 } else if (dst
.size() == 2) {
1521 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1522 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1524 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1525 nir_print_instr(&instr
->instr
, stderr
);
1526 fprintf(stderr
, "\n");
1531 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1532 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1533 if (dst
.size() == 1) {
1534 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1535 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1537 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1538 } else if (dst
.size() == 2) {
1539 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1540 get_alu_src(ctx
, instr
->src
[0]),
1541 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1542 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1545 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1546 nir_print_instr(&instr
->instr
, stderr
);
1547 fprintf(stderr
, "\n");
1552 if (dst
.size() == 1) {
1553 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1554 } else if (dst
.size() == 2) {
1555 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1556 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
),
1557 get_alu_src(ctx
, instr
->src
[0]),
1558 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1559 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1561 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1562 get_alu_src(ctx
, instr
->src
[0]),
1563 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1566 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1567 nir_print_instr(&instr
->instr
, stderr
);
1568 fprintf(stderr
, "\n");
1573 if (dst
.size() == 1) {
1574 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1575 } else if (dst
.size() == 2) {
1576 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1577 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
),
1578 get_alu_src(ctx
, instr
->src
[0]),
1579 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1580 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1582 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1583 get_alu_src(ctx
, instr
->src
[0]),
1584 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1587 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1588 nir_print_instr(&instr
->instr
, stderr
);
1589 fprintf(stderr
, "\n");
1593 case nir_op_fmax3
: {
1594 if (dst
.size() == 1) {
1595 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1597 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1598 nir_print_instr(&instr
->instr
, stderr
);
1599 fprintf(stderr
, "\n");
1603 case nir_op_fmin3
: {
1604 if (dst
.size() == 1) {
1605 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1607 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1608 nir_print_instr(&instr
->instr
, stderr
);
1609 fprintf(stderr
, "\n");
1613 case nir_op_fmed3
: {
1614 if (dst
.size() == 1) {
1615 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1617 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1618 nir_print_instr(&instr
->instr
, stderr
);
1619 fprintf(stderr
, "\n");
1623 case nir_op_umax3
: {
1624 if (dst
.size() == 1) {
1625 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1627 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1628 nir_print_instr(&instr
->instr
, stderr
);
1629 fprintf(stderr
, "\n");
1633 case nir_op_umin3
: {
1634 if (dst
.size() == 1) {
1635 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1637 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1638 nir_print_instr(&instr
->instr
, stderr
);
1639 fprintf(stderr
, "\n");
1643 case nir_op_umed3
: {
1644 if (dst
.size() == 1) {
1645 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1647 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1648 nir_print_instr(&instr
->instr
, stderr
);
1649 fprintf(stderr
, "\n");
1653 case nir_op_imax3
: {
1654 if (dst
.size() == 1) {
1655 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1663 case nir_op_imin3
: {
1664 if (dst
.size() == 1) {
1665 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1667 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1668 nir_print_instr(&instr
->instr
, stderr
);
1669 fprintf(stderr
, "\n");
1673 case nir_op_imed3
: {
1674 if (dst
.size() == 1) {
1675 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1677 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1678 nir_print_instr(&instr
->instr
, stderr
);
1679 fprintf(stderr
, "\n");
1683 case nir_op_cube_face_coord
: {
1684 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1685 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1686 emit_extract_vector(ctx
, in
, 1, v1
),
1687 emit_extract_vector(ctx
, in
, 2, v1
) };
1688 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1689 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1690 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1691 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1692 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1693 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1694 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1697 case nir_op_cube_face_index
: {
1698 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1699 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1700 emit_extract_vector(ctx
, in
, 1, v1
),
1701 emit_extract_vector(ctx
, in
, 2, v1
) };
1702 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1705 case nir_op_bcsel
: {
1706 emit_bcsel(ctx
, instr
, dst
);
1710 if (dst
.size() == 1) {
1711 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1712 } else if (dst
.size() == 2) {
1713 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1715 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1716 nir_print_instr(&instr
->instr
, stderr
);
1717 fprintf(stderr
, "\n");
1722 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1723 if (dst
.size() == 1) {
1724 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1725 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1726 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1727 } else if (dst
.size() == 2) {
1728 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1729 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1730 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1731 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1732 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1733 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1735 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1736 nir_print_instr(&instr
->instr
, stderr
);
1737 fprintf(stderr
, "\n");
1742 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1743 if (dst
.size() == 1) {
1744 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1745 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1746 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1747 } else if (dst
.size() == 2) {
1748 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1749 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1750 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1751 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1752 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1753 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1755 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1756 nir_print_instr(&instr
->instr
, stderr
);
1757 fprintf(stderr
, "\n");
1762 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1763 if (dst
.size() == 1) {
1764 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1765 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1766 // TODO: confirm that this holds under any circumstances
1767 } else if (dst
.size() == 2) {
1768 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1769 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1772 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1773 nir_print_instr(&instr
->instr
, stderr
);
1774 fprintf(stderr
, "\n");
1778 case nir_op_flog2
: {
1779 if (dst
.size() == 1) {
1780 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1782 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1783 nir_print_instr(&instr
->instr
, stderr
);
1784 fprintf(stderr
, "\n");
1789 if (dst
.size() == 1) {
1790 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1791 } else if (dst
.size() == 2) {
1792 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1794 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1795 nir_print_instr(&instr
->instr
, stderr
);
1796 fprintf(stderr
, "\n");
1800 case nir_op_fexp2
: {
1801 if (dst
.size() == 1) {
1802 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1804 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1805 nir_print_instr(&instr
->instr
, stderr
);
1806 fprintf(stderr
, "\n");
1810 case nir_op_fsqrt
: {
1811 if (dst
.size() == 1) {
1812 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1813 } else if (dst
.size() == 2) {
1814 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1816 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1817 nir_print_instr(&instr
->instr
, stderr
);
1818 fprintf(stderr
, "\n");
1822 case nir_op_ffract
: {
1823 if (dst
.size() == 1) {
1824 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1825 } else if (dst
.size() == 2) {
1826 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1828 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1829 nir_print_instr(&instr
->instr
, stderr
);
1830 fprintf(stderr
, "\n");
1834 case nir_op_ffloor
: {
1835 if (dst
.size() == 1) {
1836 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1837 } else if (dst
.size() == 2) {
1838 emit_floor_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1840 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1841 nir_print_instr(&instr
->instr
, stderr
);
1842 fprintf(stderr
, "\n");
1846 case nir_op_fceil
: {
1847 if (dst
.size() == 1) {
1848 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1849 } else if (dst
.size() == 2) {
1850 if (ctx
->options
->chip_class
>= GFX7
) {
1851 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1853 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1854 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1856 /* trunc = trunc(src0)
1857 * if (src0 > 0.0 && src0 != trunc)
1860 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1861 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1862 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1863 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1864 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1865 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1866 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1869 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1870 nir_print_instr(&instr
->instr
, stderr
);
1871 fprintf(stderr
, "\n");
1875 case nir_op_ftrunc
: {
1876 if (dst
.size() == 1) {
1877 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1878 } else if (dst
.size() == 2) {
1879 emit_trunc_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1881 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1882 nir_print_instr(&instr
->instr
, stderr
);
1883 fprintf(stderr
, "\n");
1887 case nir_op_fround_even
: {
1888 if (dst
.size() == 1) {
1889 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1890 } else if (dst
.size() == 2) {
1891 if (ctx
->options
->chip_class
>= GFX7
) {
1892 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1894 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1895 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1897 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1898 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1900 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1901 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1902 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1903 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1904 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1905 tmp
= sub
->definitions
[0].getTemp();
1907 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
1908 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
1909 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
1910 Temp cond
= vop3
->definitions
[0].getTemp();
1912 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
1913 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
1914 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
1915 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
1917 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1920 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1921 nir_print_instr(&instr
->instr
, stderr
);
1922 fprintf(stderr
, "\n");
1928 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1929 aco_ptr
<Instruction
> norm
;
1930 if (dst
.size() == 1) {
1931 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
1932 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
1934 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1935 if (ctx
->options
->chip_class
< GFX9
)
1936 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1938 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1939 bld
.vop1(opcode
, Definition(dst
), tmp
);
1941 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1942 nir_print_instr(&instr
->instr
, stderr
);
1943 fprintf(stderr
, "\n");
1947 case nir_op_ldexp
: {
1948 if (dst
.size() == 1) {
1949 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1950 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1951 get_alu_src(ctx
, instr
->src
[1]));
1952 } else if (dst
.size() == 2) {
1953 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1954 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1955 get_alu_src(ctx
, instr
->src
[1]));
1957 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1958 nir_print_instr(&instr
->instr
, stderr
);
1959 fprintf(stderr
, "\n");
1963 case nir_op_frexp_sig
: {
1964 if (dst
.size() == 1) {
1965 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
),
1966 get_alu_src(ctx
, instr
->src
[0]));
1967 } else if (dst
.size() == 2) {
1968 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
),
1969 get_alu_src(ctx
, instr
->src
[0]));
1971 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1972 nir_print_instr(&instr
->instr
, stderr
);
1973 fprintf(stderr
, "\n");
1977 case nir_op_frexp_exp
: {
1978 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1979 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
),
1980 get_alu_src(ctx
, instr
->src
[0]));
1981 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1982 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
),
1983 get_alu_src(ctx
, instr
->src
[0]));
1985 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1986 nir_print_instr(&instr
->instr
, stderr
);
1987 fprintf(stderr
, "\n");
1991 case nir_op_fsign
: {
1992 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
1993 if (dst
.size() == 1) {
1994 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1995 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
1996 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1997 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
1998 } else if (dst
.size() == 2) {
1999 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2000 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2001 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2003 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2004 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2005 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2007 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2009 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2010 nir_print_instr(&instr
->instr
, stderr
);
2011 fprintf(stderr
, "\n");
2016 case nir_op_f2f16_rtne
: {
2017 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2018 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2019 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2020 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2021 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2024 case nir_op_f2f16_rtz
: {
2025 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2026 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2027 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2028 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2032 case nir_op_f2f32
: {
2033 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2034 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2035 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2036 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2039 nir_print_instr(&instr
->instr
, stderr
);
2040 fprintf(stderr
, "\n");
2044 case nir_op_f2f64
: {
2045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2046 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2047 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2048 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2051 case nir_op_i2f32
: {
2052 assert(dst
.size() == 1);
2053 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2056 case nir_op_i2f64
: {
2057 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2058 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2059 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2060 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2061 RegClass rc
= RegClass(src
.type(), 1);
2062 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2063 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2064 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2065 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2066 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2067 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2070 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2071 nir_print_instr(&instr
->instr
, stderr
);
2072 fprintf(stderr
, "\n");
2076 case nir_op_u2f32
: {
2077 assert(dst
.size() == 1);
2078 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2081 case nir_op_u2f64
: {
2082 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2083 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2084 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2085 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2086 RegClass rc
= RegClass(src
.type(), 1);
2087 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2088 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2089 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2090 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2091 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2092 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2094 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2095 nir_print_instr(&instr
->instr
, stderr
);
2096 fprintf(stderr
, "\n");
2100 case nir_op_f2i16
: {
2101 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2102 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2103 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2104 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2105 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2107 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2109 if (dst
.type() == RegType::vgpr
)
2110 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2112 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2115 case nir_op_f2u16
: {
2116 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2117 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2118 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2119 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2120 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2122 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2124 if (dst
.type() == RegType::vgpr
)
2125 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2127 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2130 case nir_op_f2i32
: {
2131 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2132 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2133 if (dst
.type() == RegType::vgpr
)
2134 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2136 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2137 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2139 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2140 if (dst
.type() == RegType::vgpr
)
2141 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2143 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2144 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2147 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2148 nir_print_instr(&instr
->instr
, stderr
);
2149 fprintf(stderr
, "\n");
2153 case nir_op_f2u32
: {
2154 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2155 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2156 if (dst
.type() == RegType::vgpr
)
2157 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2159 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2160 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2162 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2163 if (dst
.type() == RegType::vgpr
)
2164 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2166 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2167 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2170 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2171 nir_print_instr(&instr
->instr
, stderr
);
2172 fprintf(stderr
, "\n");
2176 case nir_op_f2i64
: {
2177 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2178 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2179 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2180 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2181 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2182 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2183 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2184 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2185 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2186 Temp new_exponent
= bld
.tmp(v1
);
2187 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2188 if (ctx
->program
->chip_class
>= GFX8
)
2189 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2191 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2192 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2193 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2194 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2195 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2196 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2197 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2198 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2199 Temp new_lower
= bld
.tmp(v1
);
2200 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2201 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2202 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2204 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2205 if (src
.type() == RegType::vgpr
)
2206 src
= bld
.as_uniform(src
);
2207 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2208 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2209 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2210 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2211 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2212 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2213 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2214 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2215 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2216 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2217 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2218 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2219 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2220 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2221 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2222 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2223 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2224 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2225 Temp borrow
= bld
.tmp(s1
);
2226 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2227 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2228 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2230 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2231 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2232 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2233 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2234 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2235 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2236 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2237 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2238 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2239 if (dst
.type() == RegType::sgpr
) {
2240 lower
= bld
.as_uniform(lower
);
2241 upper
= bld
.as_uniform(upper
);
2243 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2246 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2247 nir_print_instr(&instr
->instr
, stderr
);
2248 fprintf(stderr
, "\n");
2252 case nir_op_f2u64
: {
2253 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2254 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2255 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2256 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2257 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2258 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2259 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2260 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2261 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2262 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2263 Temp new_exponent
= bld
.tmp(v1
);
2264 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2265 if (ctx
->program
->chip_class
>= GFX8
)
2266 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2268 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2269 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2270 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2271 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2272 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2273 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2274 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2275 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2277 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2278 if (src
.type() == RegType::vgpr
)
2279 src
= bld
.as_uniform(src
);
2280 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2281 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2282 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2283 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2284 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2285 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2286 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2287 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2288 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2289 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2290 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2291 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2292 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2293 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2294 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2295 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2296 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2297 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2299 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2300 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2301 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2302 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2303 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2304 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2305 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2306 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2307 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2308 if (dst
.type() == RegType::sgpr
) {
2309 lower
= bld
.as_uniform(lower
);
2310 upper
= bld
.as_uniform(upper
);
2312 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2315 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2316 nir_print_instr(&instr
->instr
, stderr
);
2317 fprintf(stderr
, "\n");
2321 case nir_op_b2f32
: {
2322 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2323 assert(src
.regClass() == bld
.lm
);
2325 if (dst
.regClass() == s1
) {
2326 src
= bool_to_scalar_condition(ctx
, src
);
2327 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2328 } else if (dst
.regClass() == v1
) {
2329 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2331 unreachable("Wrong destination register class for nir_op_b2f32.");
2335 case nir_op_b2f64
: {
2336 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2337 assert(src
.regClass() == bld
.lm
);
2339 if (dst
.regClass() == s2
) {
2340 src
= bool_to_scalar_condition(ctx
, src
);
2341 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2342 } else if (dst
.regClass() == v2
) {
2343 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2344 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2345 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2347 unreachable("Wrong destination register class for nir_op_b2f64.");
2353 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2354 /* we can actually just say dst = src */
2355 if (src
.regClass() == s1
)
2356 bld
.copy(Definition(dst
), src
);
2358 emit_extract_vector(ctx
, src
, 0, dst
);
2361 case nir_op_i2i16
: {
2362 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2363 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2364 if (dst
.regClass() == s1
) {
2365 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2367 assert(src
.regClass() == v1b
);
2368 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2369 sdwa
->operands
[0] = Operand(src
);
2370 sdwa
->definitions
[0] = Definition(dst
);
2371 sdwa
->sel
[0] = sdwa_sbyte
;
2372 sdwa
->dst_sel
= sdwa_sword
;
2373 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2376 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2377 /* we can actually just say dst = src */
2378 if (src
.regClass() == s1
)
2379 bld
.copy(Definition(dst
), src
);
2381 emit_extract_vector(ctx
, src
, 0, dst
);
2385 case nir_op_u2u16
: {
2386 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2387 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2388 if (dst
.regClass() == s1
)
2389 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2391 assert(src
.regClass() == v1b
);
2392 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2393 sdwa
->operands
[0] = Operand(src
);
2394 sdwa
->definitions
[0] = Definition(dst
);
2395 sdwa
->sel
[0] = sdwa_ubyte
;
2396 sdwa
->dst_sel
= sdwa_uword
;
2397 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2400 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2401 /* we can actually just say dst = src */
2402 if (src
.regClass() == s1
)
2403 bld
.copy(Definition(dst
), src
);
2405 emit_extract_vector(ctx
, src
, 0, dst
);
2409 case nir_op_i2i32
: {
2410 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2411 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2412 if (dst
.regClass() == s1
) {
2413 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2415 assert(src
.regClass() == v1b
);
2416 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2417 sdwa
->operands
[0] = Operand(src
);
2418 sdwa
->definitions
[0] = Definition(dst
);
2419 sdwa
->sel
[0] = sdwa_sbyte
;
2420 sdwa
->dst_sel
= sdwa_sdword
;
2421 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2423 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2424 if (dst
.regClass() == s1
) {
2425 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2427 assert(src
.regClass() == v2b
);
2428 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2429 sdwa
->operands
[0] = Operand(src
);
2430 sdwa
->definitions
[0] = Definition(dst
);
2431 sdwa
->sel
[0] = sdwa_sword
;
2432 sdwa
->dst_sel
= sdwa_udword
;
2433 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2435 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2436 /* we can actually just say dst = src, as it would map the lower register */
2437 emit_extract_vector(ctx
, src
, 0, dst
);
2439 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2440 nir_print_instr(&instr
->instr
, stderr
);
2441 fprintf(stderr
, "\n");
2445 case nir_op_u2u32
: {
2446 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2447 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2448 if (dst
.regClass() == s1
)
2449 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2451 assert(src
.regClass() == v1b
);
2452 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2453 sdwa
->operands
[0] = Operand(src
);
2454 sdwa
->definitions
[0] = Definition(dst
);
2455 sdwa
->sel
[0] = sdwa_ubyte
;
2456 sdwa
->dst_sel
= sdwa_udword
;
2457 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2459 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2460 if (dst
.regClass() == s1
) {
2461 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2463 assert(src
.regClass() == v2b
);
2464 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2465 sdwa
->operands
[0] = Operand(src
);
2466 sdwa
->definitions
[0] = Definition(dst
);
2467 sdwa
->sel
[0] = sdwa_uword
;
2468 sdwa
->dst_sel
= sdwa_udword
;
2469 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2471 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2472 /* we can actually just say dst = src, as it would map the lower register */
2473 emit_extract_vector(ctx
, src
, 0, dst
);
2475 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2476 nir_print_instr(&instr
->instr
, stderr
);
2477 fprintf(stderr
, "\n");
2481 case nir_op_i2i64
: {
2482 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2483 if (src
.regClass() == s1
) {
2484 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2485 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2486 } else if (src
.regClass() == v1
) {
2487 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2488 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2491 nir_print_instr(&instr
->instr
, stderr
);
2492 fprintf(stderr
, "\n");
2496 case nir_op_u2u64
: {
2497 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2498 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2499 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2501 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2502 nir_print_instr(&instr
->instr
, stderr
);
2503 fprintf(stderr
, "\n");
2508 case nir_op_b2i32
: {
2509 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2510 assert(src
.regClass() == bld
.lm
);
2512 if (dst
.regClass() == s1
) {
2513 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2514 bool_to_scalar_condition(ctx
, src
, dst
);
2515 } else if (dst
.regClass() == v1
) {
2516 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2518 unreachable("Invalid register class for b2i32");
2524 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2525 assert(dst
.regClass() == bld
.lm
);
2527 if (src
.type() == RegType::vgpr
) {
2528 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2529 assert(dst
.regClass() == bld
.lm
);
2530 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2531 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2533 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2535 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2536 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2538 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2539 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2541 bool_to_vector_condition(ctx
, tmp
, dst
);
2545 case nir_op_pack_64_2x32_split
: {
2546 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2547 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2549 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2552 case nir_op_unpack_64_2x32_split_x
:
2553 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2555 case nir_op_unpack_64_2x32_split_y
:
2556 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2558 case nir_op_unpack_32_2x16_split_x
:
2559 if (dst
.type() == RegType::vgpr
) {
2560 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2562 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2565 case nir_op_unpack_32_2x16_split_y
:
2566 if (dst
.type() == RegType::vgpr
) {
2567 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2569 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2572 case nir_op_pack_32_2x16_split
: {
2573 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2574 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2575 if (dst
.regClass() == v1
) {
2576 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2578 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2579 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2580 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2584 case nir_op_pack_half_2x16
: {
2585 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2587 if (dst
.regClass() == v1
) {
2588 Temp src0
= bld
.tmp(v1
);
2589 Temp src1
= bld
.tmp(v1
);
2590 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2591 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2592 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2594 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2595 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2596 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2598 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2599 nir_print_instr(&instr
->instr
, stderr
);
2600 fprintf(stderr
, "\n");
2604 case nir_op_unpack_half_2x16_split_x
: {
2605 if (dst
.regClass() == v1
) {
2606 Builder
bld(ctx
->program
, ctx
->block
);
2607 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2609 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2610 nir_print_instr(&instr
->instr
, stderr
);
2611 fprintf(stderr
, "\n");
2615 case nir_op_unpack_half_2x16_split_y
: {
2616 if (dst
.regClass() == v1
) {
2617 Builder
bld(ctx
->program
, ctx
->block
);
2618 /* TODO: use SDWA here */
2619 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2620 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2622 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2623 nir_print_instr(&instr
->instr
, stderr
);
2624 fprintf(stderr
, "\n");
2628 case nir_op_fquantize2f16
: {
2629 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2630 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2633 if (ctx
->program
->chip_class
>= GFX8
) {
2634 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2635 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2636 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2638 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2639 * so compare the result and flush to 0 if it's smaller.
2641 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2642 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2643 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2644 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2645 cmp_res
= vop3
->definitions
[0].getTemp();
2648 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2649 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2650 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2652 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2657 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2658 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2660 if (dst
.regClass() == s1
) {
2661 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2662 } else if (dst
.regClass() == v1
) {
2663 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2665 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2666 nir_print_instr(&instr
->instr
, stderr
);
2667 fprintf(stderr
, "\n");
2671 case nir_op_bitfield_select
: {
2672 /* (mask & insert) | (~mask & base) */
2673 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2674 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2675 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2677 /* dst = (insert & bitmask) | (base & ~bitmask) */
2678 if (dst
.regClass() == s1
) {
2679 aco_ptr
<Instruction
> sop2
;
2680 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2681 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2683 if (const_insert
&& const_bitmask
) {
2684 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2686 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2687 lhs
= Operand(insert
);
2691 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2692 if (const_base
&& const_bitmask
) {
2693 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2695 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2696 rhs
= Operand(base
);
2699 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2701 } else if (dst
.regClass() == v1
) {
2702 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2703 base
= as_vgpr(ctx
, base
);
2704 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2705 insert
= as_vgpr(ctx
, insert
);
2707 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2710 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2711 nir_print_instr(&instr
->instr
, stderr
);
2712 fprintf(stderr
, "\n");
2718 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2719 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2720 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2722 if (dst
.type() == RegType::sgpr
) {
2724 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2725 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2726 if (const_offset
&& const_bits
) {
2727 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2728 extract
= Operand(const_extract
);
2732 width
= Operand(const_bits
->u32
<< 16);
2734 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2736 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2740 if (dst
.regClass() == s1
) {
2741 if (instr
->op
== nir_op_ubfe
)
2742 opcode
= aco_opcode::s_bfe_u32
;
2744 opcode
= aco_opcode::s_bfe_i32
;
2745 } else if (dst
.regClass() == s2
) {
2746 if (instr
->op
== nir_op_ubfe
)
2747 opcode
= aco_opcode::s_bfe_u64
;
2749 opcode
= aco_opcode::s_bfe_i64
;
2751 unreachable("Unsupported BFE bit size");
2754 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2758 if (dst
.regClass() == v1
) {
2759 if (instr
->op
== nir_op_ubfe
)
2760 opcode
= aco_opcode::v_bfe_u32
;
2762 opcode
= aco_opcode::v_bfe_i32
;
2764 unreachable("Unsupported BFE bit size");
2767 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2771 case nir_op_bit_count
: {
2772 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2773 if (src
.regClass() == s1
) {
2774 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2775 } else if (src
.regClass() == v1
) {
2776 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2777 } else if (src
.regClass() == v2
) {
2778 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2779 emit_extract_vector(ctx
, src
, 1, v1
),
2780 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2781 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2782 } else if (src
.regClass() == s2
) {
2783 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2785 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2786 nir_print_instr(&instr
->instr
, stderr
);
2787 fprintf(stderr
, "\n");
2792 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2796 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2800 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2804 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2808 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2812 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2816 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2817 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2819 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2820 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2824 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2825 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2827 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2828 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2832 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2836 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2841 case nir_op_fddx_fine
:
2842 case nir_op_fddy_fine
:
2843 case nir_op_fddx_coarse
:
2844 case nir_op_fddy_coarse
: {
2845 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2846 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2847 if (instr
->op
== nir_op_fddx_fine
) {
2848 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2849 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2850 } else if (instr
->op
== nir_op_fddy_fine
) {
2851 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2852 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2854 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2855 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2856 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2858 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2862 if (ctx
->program
->chip_class
>= GFX8
) {
2863 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2864 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2866 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2867 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2868 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2870 emit_wqm(ctx
, tmp
, dst
, true);
2874 fprintf(stderr
, "Unknown NIR ALU instr: ");
2875 nir_print_instr(&instr
->instr
, stderr
);
2876 fprintf(stderr
, "\n");
2880 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2882 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2884 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2885 // which get truncated the lsb if double and msb if int
2886 // for now, we only use s_mov_b64 with 64bit inline constants
2887 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2888 assert(dst
.type() == RegType::sgpr
);
2890 Builder
bld(ctx
->program
, ctx
->block
);
2892 if (instr
->def
.bit_size
== 1) {
2893 assert(dst
.regClass() == bld
.lm
);
2894 int val
= instr
->value
[0].b
? -1 : 0;
2895 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2896 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2897 } else if (dst
.size() == 1) {
2898 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2900 assert(dst
.size() != 1);
2901 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2902 if (instr
->def
.bit_size
== 64)
2903 for (unsigned i
= 0; i
< dst
.size(); i
++)
2904 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2906 for (unsigned i
= 0; i
< dst
.size(); i
++)
2907 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2909 vec
->definitions
[0] = Definition(dst
);
2910 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2914 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2916 uint32_t new_mask
= 0;
2917 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2918 if (mask
& (1u << i
))
2919 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2923 Operand
load_lds_size_m0(isel_context
*ctx
)
2925 /* TODO: m0 does not need to be initialized on GFX9+ */
2926 Builder
bld(ctx
->program
, ctx
->block
);
2927 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2930 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2931 Temp address
, unsigned base_offset
, unsigned align
)
2933 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2935 Builder
bld(ctx
->program
, ctx
->block
);
2937 Operand m
= load_lds_size_m0(ctx
);
2939 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2940 unsigned bytes_read
= 0;
2941 unsigned result_size
= 0;
2942 unsigned total_bytes
= num_components
* elem_size_bytes
;
2943 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
2944 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
2945 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
2947 while (bytes_read
< total_bytes
) {
2948 unsigned todo
= total_bytes
- bytes_read
;
2949 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2950 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2952 aco_opcode op
= aco_opcode::last_opcode
;
2954 if (todo
>= 16 && aligned16
&& large_ds_read
) {
2955 op
= aco_opcode::ds_read_b128
;
2957 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
2958 op
= aco_opcode::ds_read2_b64
;
2961 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
2962 op
= aco_opcode::ds_read_b96
;
2964 } else if (todo
>= 8 && aligned8
) {
2965 op
= aco_opcode::ds_read_b64
;
2967 } else if (todo
>= 8 && usable_read2
) {
2968 op
= aco_opcode::ds_read2_b32
;
2971 } else if (todo
>= 4) {
2972 op
= aco_opcode::ds_read_b32
;
2977 assert(todo
% elem_size_bytes
== 0);
2978 unsigned num_elements
= todo
/ elem_size_bytes
;
2979 unsigned offset
= base_offset
+ bytes_read
;
2980 unsigned max_offset
= read2
? 1019 : 65535;
2982 Temp address_offset
= address
;
2983 if (offset
> max_offset
) {
2984 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
2985 offset
= bytes_read
;
2987 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
2990 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
2993 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
2996 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
2998 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3000 if (num_components
== 1) {
3001 assert(todo
== total_bytes
);
3002 if (dst
.type() == RegType::sgpr
)
3003 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3007 if (dst
.type() == RegType::sgpr
) {
3008 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3009 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3013 if (num_elements
== 1) {
3014 result
[result_size
++] = res
;
3016 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3017 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3018 split
->operands
[0] = Operand(res
);
3019 for (unsigned i
= 0; i
< num_elements
; i
++)
3020 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3021 ctx
->block
->instructions
.emplace_back(std::move(split
));
3027 assert(result_size
== num_components
&& result_size
> 1);
3028 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3029 for (unsigned i
= 0; i
< result_size
; i
++)
3030 vec
->operands
[i
] = Operand(result
[i
]);
3031 vec
->definitions
[0] = Definition(dst
);
3032 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3033 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3038 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3040 if (start
== 0 && size
== data
.size())
3041 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3043 unsigned size_hint
= 1;
3044 auto it
= ctx
->allocated_vec
.find(data
.id());
3045 if (it
!= ctx
->allocated_vec
.end())
3046 size_hint
= it
->second
[0].size();
3047 if (size
% size_hint
|| start
% size_hint
)
3054 for (unsigned i
= 0; i
< size
; i
++)
3055 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3058 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3060 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3061 for (unsigned i
= 0; i
< size
; i
++)
3062 vec
->operands
[i
] = Operand(elems
[i
]);
3063 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3064 vec
->definitions
[0] = Definition(res
);
3065 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3069 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3071 Builder
bld(ctx
->program
, ctx
->block
);
3072 unsigned bytes_written
= 0;
3073 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3074 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3076 while (bytes_written
< total_size
* 4) {
3077 unsigned todo
= total_size
* 4 - bytes_written
;
3078 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3079 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3081 aco_opcode op
= aco_opcode::last_opcode
;
3082 bool write2
= false;
3084 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3085 op
= aco_opcode::ds_write_b128
;
3087 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3088 op
= aco_opcode::ds_write2_b64
;
3091 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3092 op
= aco_opcode::ds_write_b96
;
3094 } else if (todo
>= 8 && aligned8
) {
3095 op
= aco_opcode::ds_write_b64
;
3097 } else if (todo
>= 8 && usable_write2
) {
3098 op
= aco_opcode::ds_write2_b32
;
3101 } else if (todo
>= 4) {
3102 op
= aco_opcode::ds_write_b32
;
3108 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3109 unsigned max_offset
= write2
? 1020 : 65535;
3110 Temp address_offset
= address
;
3111 if (offset
> max_offset
) {
3112 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3113 offset
= offset1
+ bytes_written
;
3115 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3118 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3119 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3120 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3122 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3123 bld
.ds(op
, address_offset
, val
, m
, offset
);
3126 bytes_written
+= size
* 4;
3130 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3131 Temp address
, unsigned base_offset
, unsigned align
)
3133 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3134 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3136 Operand m
= load_lds_size_m0(ctx
);
3138 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3139 assert(wrmask
<= 0x0f);
3140 int start
[2], count
[2];
3141 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3142 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3143 assert(wrmask
== 0);
3145 /* one combined store is sufficient */
3146 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3147 Builder
bld(ctx
->program
, ctx
->block
);
3149 Temp address_offset
= address
;
3150 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3151 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3155 assert(count
[0] == 1);
3156 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3158 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3159 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3160 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3161 base_offset
= base_offset
/ elem_size_bytes
;
3162 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3163 base_offset
+ start
[0], base_offset
+ start
[1]);
3167 for (unsigned i
= 0; i
< 2; i
++) {
3171 unsigned elem_size_words
= elem_size_bytes
/ 4;
3172 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3173 base_offset
, start
[i
] * elem_size_bytes
, align
);
3178 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3180 unsigned align
= 16;
3182 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3188 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3189 unsigned split_cnt
= 0u, Temp dst
= Temp())
3191 Builder
bld(ctx
->program
, ctx
->block
);
3192 unsigned dword_size
= elem_size_bytes
/ 4;
3195 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3197 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3198 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3199 instr
->definitions
[0] = Definition(dst
);
3201 for (unsigned i
= 0; i
< cnt
; ++i
) {
3203 assert(arr
[i
].size() == dword_size
);
3204 allocated_vec
[i
] = arr
[i
];
3205 instr
->operands
[i
] = Operand(arr
[i
]);
3207 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3208 allocated_vec
[i
] = zero
;
3209 instr
->operands
[i
] = Operand(zero
);
3213 bld
.insert(std::move(instr
));
3216 emit_split_vector(ctx
, dst
, split_cnt
);
3218 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3223 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3225 if (const_offset
>= 4096) {
3226 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3227 const_offset
%= 4096u;
3230 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3231 else if (unlikely(voffset
.regClass() == s1
))
3232 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3233 else if (likely(voffset
.regClass() == v1
))
3234 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3236 unreachable("Unsupported register class of voffset");
3239 return const_offset
;
3242 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3243 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3246 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3247 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3249 Builder
bld(ctx
->program
, ctx
->block
);
3250 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3251 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3253 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3254 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3255 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3256 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3257 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3259 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3262 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3263 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3264 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3266 Builder
bld(ctx
->program
, ctx
->block
);
3267 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3270 if (elem_size_bytes
== 8) {
3271 elem_size_bytes
= 4;
3272 write_mask
= widen_mask(write_mask
, 2);
3275 while (write_mask
) {
3278 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3283 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3284 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3286 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3287 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3290 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3291 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3301 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3302 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3304 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3305 assert(size_dwords
>= 1 && size_dwords
<= 4);
3307 Builder
bld(ctx
->program
, ctx
->block
);
3308 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3309 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3310 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3312 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3313 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3314 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3315 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3316 /* disable_wqm */ false, /* glc */ true,
3317 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3319 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3324 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3325 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3326 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3328 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3329 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3330 assert(!!stride
!= allow_combining
);
3332 Builder
bld(ctx
->program
, ctx
->block
);
3333 unsigned split_cnt
= num_components
;
3335 if (elem_size_bytes
== 8) {
3336 elem_size_bytes
= 4;
3337 num_components
*= 2;
3341 stride
= elem_size_bytes
;
3343 unsigned load_size
= 1;
3344 if (allow_combining
) {
3345 if ((num_components
% 4) == 0)
3347 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3349 else if ((num_components
% 2) == 0)
3353 unsigned num_loads
= num_components
/ load_size
;
3354 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3356 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3357 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3358 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3361 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3364 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3366 Builder
bld(ctx
->program
, ctx
->block
);
3367 Temp offset
= base_offset
.first
;
3368 unsigned const_offset
= base_offset
.second
;
3370 if (!nir_src_is_const(*off_src
)) {
3371 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3374 /* Calculate indirect offset with stride */
3375 if (likely(indirect_offset_arg
.regClass() == v1
))
3376 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3377 else if (indirect_offset_arg
.regClass() == s1
)
3378 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3380 unreachable("Unsupported register class of indirect offset");
3382 /* Add to the supplied base offset */
3383 if (offset
.id() == 0)
3384 offset
= with_stride
;
3385 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3386 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3387 else if (offset
.size() == 1 && with_stride
.size() == 1)
3388 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3390 unreachable("Unsupported register class of indirect offset");
3392 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3393 const_offset
+= const_offset_arg
* stride
;
3396 return std::make_pair(offset
, const_offset
);
3399 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3401 Builder
bld(ctx
->program
, ctx
->block
);
3404 if (off1
.first
.id() && off2
.first
.id()) {
3405 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3406 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3407 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3408 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3410 unreachable("Unsupported register class of indirect offset");
3412 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3415 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3418 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3420 Builder
bld(ctx
->program
, ctx
->block
);
3421 unsigned const_offset
= offs
.second
* multiplier
;
3423 if (!offs
.first
.id())
3424 return std::make_pair(offs
.first
, const_offset
);
3426 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3427 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3428 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3430 return std::make_pair(offset
, const_offset
);
3433 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3435 Builder
bld(ctx
->program
, ctx
->block
);
3437 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3438 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3439 /* component is in bytes */
3440 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3442 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3443 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3444 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3447 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3449 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3452 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3454 Builder
bld(ctx
->program
, ctx
->block
);
3456 switch (ctx
->shader
->info
.stage
) {
3457 case MESA_SHADER_TESS_CTRL
:
3458 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3459 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3460 case MESA_SHADER_TESS_EVAL
:
3461 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3463 unreachable("Unsupported stage in get_tess_rel_patch_id");
3467 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3469 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3470 Builder
bld(ctx
->program
, ctx
->block
);
3472 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3473 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3475 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3477 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3478 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3480 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3481 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3482 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3484 return offset_mul(ctx
, offs
, 4u);
3487 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3489 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3490 Builder
bld(ctx
->program
, ctx
->block
);
3492 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3493 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3494 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3495 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3496 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3497 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3499 std::pair
<Temp
, unsigned> offs
= instr
3500 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3501 : std::make_pair(Temp(), 0u);
3503 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3504 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3509 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3510 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3512 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3513 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3515 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3516 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3522 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3524 Builder
bld(ctx
->program
, ctx
->block
);
3526 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3527 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3529 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3531 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3532 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3533 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3535 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3536 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3541 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3543 Builder
bld(ctx
->program
, ctx
->block
);
3545 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3546 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3547 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3549 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3550 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3551 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3552 unsigned attr_stride
= ctx
->tcs_num_patches
;
3554 std::pair
<Temp
, unsigned> offs
= instr
3555 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3556 : std::make_pair(Temp(), 0u);
3558 if (const_base_offset
)
3559 offs
.second
+= const_base_offset
* attr_stride
;
3561 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3562 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3563 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3568 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3570 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3571 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3573 if (!nir_src_is_const(*off_src
)) {
3579 off
+= nir_src_as_uint(*off_src
) * 16u;
3582 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3583 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3590 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3592 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3593 unsigned component
= nir_intrinsic_component(instr
);
3594 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3596 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3597 if (off_instr
->type
!= nir_instr_type_load_const
)
3600 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3601 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3603 if (instr
->src
[0].ssa
->bit_size
== 64)
3604 write_mask
= widen_mask(write_mask
, 2);
3606 for (unsigned i
= 0; i
< 8; ++i
) {
3607 if (write_mask
& (1 << i
)) {
3608 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3609 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3617 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3619 /* Only TCS per-vertex inputs are supported by this function.
3620 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3622 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3625 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3626 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3627 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3628 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3629 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3630 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3635 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3636 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3637 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3638 assert(vec
.size() == dst
.size());
3640 Builder
bld(ctx
->program
, ctx
->block
);
3641 bld
.copy(Definition(dst
), vec
);
3645 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3647 Builder
bld(ctx
->program
, ctx
->block
);
3649 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3650 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3651 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3652 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3654 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3655 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3656 bool indirect_write
;
3657 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3658 if (temp_only_input
&& !indirect_write
)
3662 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3663 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3664 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3665 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3666 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3670 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3671 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3672 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3673 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3674 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3675 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3676 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3677 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3678 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3679 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3680 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3681 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3682 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3684 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3685 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3686 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3688 unreachable("Invalid LS or ES stage");
3691 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3692 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3693 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3697 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3699 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3700 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3701 off
!= ctx
->tcs_tess_lvl_in_loc
;
3704 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3706 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3707 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3710 uint64_t mask
= per_vertex
3711 ? ctx
->shader
->info
.outputs_read
3712 : ctx
->shader
->info
.patch_outputs_read
;
3713 bool indirect_write
;
3714 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3715 return indirect_write
|| output_read
;
3718 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3720 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3721 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3723 Builder
bld(ctx
->program
, ctx
->block
);
3725 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3726 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3727 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3729 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3730 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3731 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3732 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3734 if (write_to_vmem
) {
3735 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3736 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3737 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3739 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3740 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3741 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3745 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3746 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3747 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3751 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3753 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3754 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3756 Builder
bld(ctx
->program
, ctx
->block
);
3758 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3759 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3760 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3761 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3763 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3766 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3768 if (ctx
->stage
== vertex_vs
||
3769 ctx
->stage
== tess_eval_vs
||
3770 ctx
->stage
== fragment_fs
||
3771 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3772 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3773 if (!stored_to_temps
) {
3774 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3775 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3776 fprintf(stderr
, "\n");
3779 } else if (ctx
->stage
== vertex_es
||
3780 ctx
->stage
== vertex_ls
||
3781 ctx
->stage
== tess_eval_es
||
3782 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3783 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3784 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3785 visit_store_ls_or_es_output(ctx
, instr
);
3786 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3787 visit_store_tcs_output(ctx
, instr
, false);
3789 unreachable("Shader stage not implemented");
3793 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3795 visit_load_tcs_output(ctx
, instr
, false);
3798 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3800 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3801 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3803 Builder
bld(ctx
->program
, ctx
->block
);
3804 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3805 if (ctx
->program
->has_16bank_lds
)
3806 interp_p1
.instr
->operands
[0].setLateKill(true);
3807 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3810 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3812 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3813 for (unsigned i
= 0; i
< num_components
; i
++)
3814 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3815 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3816 assert(num_components
== 4);
3817 Builder
bld(ctx
->program
, ctx
->block
);
3818 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3821 for (Operand
& op
: vec
->operands
)
3822 op
= op
.isUndefined() ? Operand(0u) : op
;
3824 vec
->definitions
[0] = Definition(dst
);
3825 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3826 emit_split_vector(ctx
, dst
, num_components
);
3830 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3832 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3833 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3834 unsigned idx
= nir_intrinsic_base(instr
);
3835 unsigned component
= nir_intrinsic_component(instr
);
3836 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3838 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3840 assert(offset
->u32
== 0);
3842 /* the lower 15bit of the prim_mask contain the offset into LDS
3843 * while the upper bits contain the number of prims */
3844 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3845 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3846 Builder
bld(ctx
->program
, ctx
->block
);
3847 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3848 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3849 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3850 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3851 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3854 if (instr
->dest
.ssa
.num_components
== 1) {
3855 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3857 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3858 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3860 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3861 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3862 vec
->operands
[i
] = Operand(tmp
);
3864 vec
->definitions
[0] = Definition(dst
);
3865 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3869 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3870 unsigned offset
, unsigned stride
, unsigned channels
)
3872 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
3873 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
3875 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
3876 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
3879 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3880 unsigned offset
, unsigned stride
, unsigned *channels
)
3882 if (!vtx_info
->chan_byte_size
) {
3883 *channels
= vtx_info
->num_channels
;
3884 return vtx_info
->chan_format
;
3887 unsigned num_channels
= *channels
;
3888 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
3889 unsigned new_channels
= num_channels
+ 1;
3890 /* first, assume more loads is worse and try using a larger data format */
3891 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
3893 /* don't make the attribute potentially out-of-bounds */
3894 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
3898 if (new_channels
== 5) {
3899 /* then try decreasing load size (at the cost of more loads) */
3900 new_channels
= *channels
;
3901 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
3905 if (new_channels
< *channels
)
3906 *channels
= new_channels
;
3907 num_channels
= new_channels
;
3910 switch (vtx_info
->chan_format
) {
3911 case V_008F0C_BUF_DATA_FORMAT_8
:
3912 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
3913 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
3914 case V_008F0C_BUF_DATA_FORMAT_16
:
3915 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
3916 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
3917 case V_008F0C_BUF_DATA_FORMAT_32
:
3918 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
3919 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
3921 unreachable("shouldn't reach here");
3922 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
3925 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3926 * so we may need to fix it up. */
3927 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3929 Builder
bld(ctx
->program
, ctx
->block
);
3931 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3932 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3934 /* For the integer-like cases, do a natural sign extension.
3936 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3937 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3940 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3941 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3943 /* Convert back to the right type. */
3944 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3945 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3946 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3947 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3948 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3949 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3955 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3957 Builder
bld(ctx
->program
, ctx
->block
);
3958 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3959 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
3961 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3962 if (off_instr
->type
!= nir_instr_type_load_const
) {
3963 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3964 nir_print_instr(off_instr
, stderr
);
3965 fprintf(stderr
, "\n");
3967 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3969 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
3971 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
3972 unsigned component
= nir_intrinsic_component(instr
);
3973 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
3974 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
3975 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
3976 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
3978 unsigned dfmt
= attrib_format
& 0xf;
3979 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
3980 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
3982 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
3983 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
3984 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
3985 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
3987 num_channels
= MAX2(num_channels
, 3);
3989 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
3990 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
3993 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
3994 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
3995 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
3997 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
3999 Temp divided
= bld
.tmp(v1
);
4000 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4001 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4003 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4006 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4009 index
= bld
.vadd32(bld
.def(v1
),
4010 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4011 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4014 Temp channels
[num_channels
];
4015 unsigned channel_start
= 0;
4016 bool direct_fetch
= false;
4018 /* skip unused channels at the start */
4019 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4020 channel_start
= ffs(mask
) - 1;
4021 for (unsigned i
= 0; i
< channel_start
; i
++)
4022 channels
[i
] = Temp(0, s1
);
4023 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4024 num_channels
= 3 - (ffs(mask
) - 1);
4028 while (channel_start
< num_channels
) {
4029 unsigned fetch_size
= num_channels
- channel_start
;
4030 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4031 bool expanded
= false;
4033 /* use MUBUF when possible to avoid possible alignment issues */
4034 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4035 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4036 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4037 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4038 vtx_info
->chan_byte_size
== 4;
4039 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4041 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4043 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4044 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4050 Temp fetch_index
= index
;
4051 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4052 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4053 fetch_offset
= fetch_offset
% attrib_stride
;
4056 Operand
soffset(0u);
4057 if (fetch_offset
>= 4096) {
4058 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4059 fetch_offset
%= 4096;
4063 switch (fetch_size
) {
4065 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4068 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4071 assert(ctx
->options
->chip_class
>= GFX7
||
4072 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4073 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4076 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4079 unreachable("Unimplemented load_input vector size");
4083 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4084 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4085 num_channels
<= 3)) {
4086 direct_fetch
= true;
4089 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4093 Instruction
*mubuf
= bld
.mubuf(opcode
,
4094 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4095 fetch_offset
, false, true).instr
;
4096 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4098 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4099 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4100 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4101 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4104 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4106 if (fetch_size
== 1) {
4107 channels
[channel_start
] = fetch_dst
;
4109 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4110 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4113 channel_start
+= fetch_size
;
4116 if (!direct_fetch
) {
4117 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4118 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4120 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4121 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4122 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4124 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4125 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4126 unsigned num_temp
= 0;
4127 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4128 unsigned idx
= i
+ component
;
4129 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4130 Temp channel
= channels
[swizzle
[idx
]];
4131 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4132 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4133 vec
->operands
[i
] = Operand(channel
);
4137 } else if (is_float
&& idx
== 3) {
4138 vec
->operands
[i
] = Operand(0x3f800000u
);
4139 } else if (!is_float
&& idx
== 3) {
4140 vec
->operands
[i
] = Operand(1u);
4142 vec
->operands
[i
] = Operand(0u);
4145 vec
->definitions
[0] = Definition(dst
);
4146 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4147 emit_split_vector(ctx
, dst
, dst
.size());
4149 if (num_temp
== dst
.size())
4150 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4152 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4153 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4154 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4155 if (off_instr
->type
!= nir_instr_type_load_const
||
4156 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4157 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4158 nir_print_instr(off_instr
, stderr
);
4159 fprintf(stderr
, "\n");
4162 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4163 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4165 assert(offset
->u32
== 0);
4167 /* the lower 15bit of the prim_mask contain the offset into LDS
4168 * while the upper bits contain the number of prims */
4169 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4170 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4171 Builder
bld(ctx
->program
, ctx
->block
);
4172 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4173 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4174 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4175 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4176 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4179 unsigned idx
= nir_intrinsic_base(instr
);
4180 unsigned component
= nir_intrinsic_component(instr
);
4181 unsigned vertex_id
= 2; /* P0 */
4183 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4184 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4185 switch (src0
->u32
) {
4187 vertex_id
= 2; /* P0 */
4190 vertex_id
= 0; /* P10 */
4193 vertex_id
= 1; /* P20 */
4196 unreachable("invalid vertex index");
4200 if (dst
.size() == 1) {
4201 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4203 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4204 for (unsigned i
= 0; i
< dst
.size(); i
++)
4205 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4206 vec
->definitions
[0] = Definition(dst
);
4207 bld
.insert(std::move(vec
));
4210 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4211 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4212 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4213 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4214 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4216 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4218 unreachable("Shader stage not implemented");
4222 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4224 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4226 Builder
bld(ctx
->program
, ctx
->block
);
4227 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4230 if (!nir_src_is_const(*vertex_src
)) {
4231 /* better code could be created, but this case probably doesn't happen
4232 * much in practice */
4233 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4234 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4237 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4238 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4240 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4242 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4245 if (vertex_offset
.id()) {
4246 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4247 Operand(i
), indirect_vertex
);
4248 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4250 vertex_offset
= elem
;
4254 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4255 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4257 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4258 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4259 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4260 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4261 Operand((vertex
% 2u) * 16u), Operand(16u));
4263 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4266 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4267 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4268 return offset_mul(ctx
, offs
, 4u);
4271 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4273 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4275 Builder
bld(ctx
->program
, ctx
->block
);
4276 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4277 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4279 if (ctx
->stage
== geometry_gs
) {
4280 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4281 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4282 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4283 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4284 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4285 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4286 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4288 unreachable("Unsupported GS stage.");
4292 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4294 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4296 Builder
bld(ctx
->program
, ctx
->block
);
4297 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4299 if (load_input_from_temps(ctx
, instr
, dst
))
4302 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4303 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4304 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4306 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4309 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4311 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4313 Builder
bld(ctx
->program
, ctx
->block
);
4315 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4316 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4317 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4319 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4320 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4322 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4325 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4327 switch (ctx
->shader
->info
.stage
) {
4328 case MESA_SHADER_GEOMETRY
:
4329 visit_load_gs_per_vertex_input(ctx
, instr
);
4331 case MESA_SHADER_TESS_CTRL
:
4332 visit_load_tcs_per_vertex_input(ctx
, instr
);
4334 case MESA_SHADER_TESS_EVAL
:
4335 visit_load_tes_per_vertex_input(ctx
, instr
);
4338 unreachable("Unimplemented shader stage");
4342 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4344 visit_load_tcs_output(ctx
, instr
, true);
4347 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4349 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4350 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4352 visit_store_tcs_output(ctx
, instr
, true);
4355 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4357 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4359 Builder
bld(ctx
->program
, ctx
->block
);
4360 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4362 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4363 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4366 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4367 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4368 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4369 tes_w
= Operand(tmp
);
4372 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4373 emit_split_vector(ctx
, tess_coord
, 3);
4376 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4378 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4379 Builder
bld(ctx
->program
, ctx
->block
);
4380 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4381 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4382 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4385 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4389 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4391 Builder
bld(ctx
->program
, ctx
->block
);
4392 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4393 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4394 index
= bld
.as_uniform(index
);
4395 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4396 unsigned binding
= nir_intrinsic_binding(instr
);
4399 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4400 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4401 unsigned offset
= layout
->binding
[binding
].offset
;
4403 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4404 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4405 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4406 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4407 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4410 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4411 stride
= layout
->binding
[binding
].size
;
4414 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4415 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4417 if (nir_const_index
) {
4418 const_index
= const_index
* stride
;
4419 } else if (index
.type() == RegType::vgpr
) {
4420 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4421 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4423 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4427 if (nir_const_index
) {
4428 const_index
= const_index
+ offset
;
4429 } else if (index
.type() == RegType::vgpr
) {
4430 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4432 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4436 if (nir_const_index
&& const_index
== 0) {
4438 } else if (index
.type() == RegType::vgpr
) {
4439 index
= bld
.vadd32(bld
.def(v1
),
4440 nir_const_index
? Operand(const_index
) : Operand(index
),
4443 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4444 nir_const_index
? Operand(const_index
) : Operand(index
),
4448 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4451 void load_buffer(isel_context
*ctx
, unsigned num_components
, Temp dst
,
4452 Temp rsrc
, Temp offset
, bool glc
=false, bool readonly
=true)
4454 Builder
bld(ctx
->program
, ctx
->block
);
4456 unsigned num_bytes
= dst
.size() * 4;
4457 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4460 if (dst
.type() == RegType::vgpr
|| (ctx
->options
->chip_class
< GFX8
&& !readonly
)) {
4461 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4462 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4463 unsigned const_offset
= 0;
4465 Temp lower
= Temp();
4466 if (num_bytes
> 16) {
4467 assert(num_components
== 3 || num_components
== 4);
4468 op
= aco_opcode::buffer_load_dwordx4
;
4469 lower
= bld
.tmp(v4
);
4470 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4471 mubuf
->definitions
[0] = Definition(lower
);
4472 mubuf
->operands
[0] = Operand(rsrc
);
4473 mubuf
->operands
[1] = vaddr
;
4474 mubuf
->operands
[2] = soffset
;
4475 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4478 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4479 mubuf
->can_reorder
= readonly
;
4480 bld
.insert(std::move(mubuf
));
4481 emit_split_vector(ctx
, lower
, 2);
4484 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4485 /* GFX6 doesn't support loading vec3, expand to vec4. */
4489 switch (num_bytes
) {
4491 op
= aco_opcode::buffer_load_dword
;
4494 op
= aco_opcode::buffer_load_dwordx2
;
4497 assert(ctx
->options
->chip_class
> GFX6
);
4498 op
= aco_opcode::buffer_load_dwordx3
;
4501 op
= aco_opcode::buffer_load_dwordx4
;
4504 unreachable("Load SSBO not implemented for this size.");
4506 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4507 mubuf
->operands
[0] = Operand(rsrc
);
4508 mubuf
->operands
[1] = vaddr
;
4509 mubuf
->operands
[2] = soffset
;
4510 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4513 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4514 mubuf
->can_reorder
= readonly
;
4515 mubuf
->offset
= const_offset
;
4516 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4518 if (dst
.size() > 4) {
4519 assert(lower
!= Temp());
4520 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4521 instr
->definitions
[0] = Definition(upper
);
4522 bld
.insert(std::move(instr
));
4523 if (dst
.size() == 8)
4524 emit_split_vector(ctx
, upper
, 2);
4525 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4526 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4527 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4528 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4529 if (dst
.size() == 8)
4530 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4531 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4532 Temp vec
= bld
.tmp(v4
);
4533 instr
->definitions
[0] = Definition(vec
);
4534 bld
.insert(std::move(instr
));
4535 emit_split_vector(ctx
, vec
, 4);
4537 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4538 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4539 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4540 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4543 if (dst
.type() == RegType::sgpr
) {
4544 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4545 instr
->definitions
[0] = Definition(vec
);
4546 bld
.insert(std::move(instr
));
4547 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4549 instr
->definitions
[0] = Definition(dst
);
4550 bld
.insert(std::move(instr
));
4551 emit_split_vector(ctx
, dst
, num_components
);
4554 switch (num_bytes
) {
4556 op
= aco_opcode::s_buffer_load_dword
;
4559 op
= aco_opcode::s_buffer_load_dwordx2
;
4563 op
= aco_opcode::s_buffer_load_dwordx4
;
4567 op
= aco_opcode::s_buffer_load_dwordx8
;
4570 unreachable("Load SSBO not implemented for this size.");
4572 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4573 load
->operands
[0] = Operand(rsrc
);
4574 load
->operands
[1] = Operand(bld
.as_uniform(offset
));
4575 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4576 load
->definitions
[0] = Definition(dst
);
4579 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4580 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4581 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4584 if (dst
.size() == 3) {
4585 Temp vec
= bld
.tmp(s4
);
4586 load
->definitions
[0] = Definition(vec
);
4587 bld
.insert(std::move(load
));
4588 emit_split_vector(ctx
, vec
, 4);
4590 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4591 emit_extract_vector(ctx
, vec
, 0, s1
),
4592 emit_extract_vector(ctx
, vec
, 1, s1
),
4593 emit_extract_vector(ctx
, vec
, 2, s1
));
4594 } else if (dst
.size() == 6) {
4595 Temp vec
= bld
.tmp(s8
);
4596 load
->definitions
[0] = Definition(vec
);
4597 bld
.insert(std::move(load
));
4598 emit_split_vector(ctx
, vec
, 4);
4600 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4601 emit_extract_vector(ctx
, vec
, 0, s2
),
4602 emit_extract_vector(ctx
, vec
, 1, s2
),
4603 emit_extract_vector(ctx
, vec
, 2, s2
));
4605 bld
.insert(std::move(load
));
4607 emit_split_vector(ctx
, dst
, num_components
);
4611 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4613 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4614 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4616 Builder
bld(ctx
->program
, ctx
->block
);
4618 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4619 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4620 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4621 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4623 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4624 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4625 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4626 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4627 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4628 if (ctx
->options
->chip_class
>= GFX10
) {
4629 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4630 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4631 S_008F0C_RESOURCE_LEVEL(1);
4633 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4634 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4636 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4637 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4638 Operand(0xFFFFFFFFu
),
4639 Operand(desc_type
));
4640 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4641 rsrc
, upper_dwords
);
4643 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4644 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4647 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4650 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4652 Builder
bld(ctx
->program
, ctx
->block
);
4653 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4655 unsigned offset
= nir_intrinsic_base(instr
);
4656 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4657 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4659 unsigned count
= instr
->dest
.ssa
.num_components
;
4660 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4661 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4662 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4663 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4664 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4665 for (unsigned i
= 0; i
< count
; ++i
) {
4666 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4667 vec
->operands
[i
] = Operand
{elems
[i
]};
4669 vec
->definitions
[0] = Definition(dst
);
4670 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4671 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4676 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4677 if (offset
!= 0) // TODO check if index != 0 as well
4678 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4679 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4684 switch (dst
.size()) {
4686 op
= aco_opcode::s_load_dword
;
4689 op
= aco_opcode::s_load_dwordx2
;
4695 op
= aco_opcode::s_load_dwordx4
;
4701 op
= aco_opcode::s_load_dwordx8
;
4704 unreachable("unimplemented or forbidden load_push_constant.");
4707 bld
.smem(op
, Definition(vec
), ptr
, index
);
4710 emit_split_vector(ctx
, vec
, 4);
4711 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4712 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4713 emit_extract_vector(ctx
, vec
, 0, rc
),
4714 emit_extract_vector(ctx
, vec
, 1, rc
),
4715 emit_extract_vector(ctx
, vec
, 2, rc
));
4718 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4721 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4723 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4725 Builder
bld(ctx
->program
, ctx
->block
);
4727 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4728 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4729 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4730 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4731 if (ctx
->options
->chip_class
>= GFX10
) {
4732 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4733 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4734 S_008F0C_RESOURCE_LEVEL(1);
4736 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4737 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4740 unsigned base
= nir_intrinsic_base(instr
);
4741 unsigned range
= nir_intrinsic_range(instr
);
4743 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4744 if (base
&& offset
.type() == RegType::sgpr
)
4745 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4746 else if (base
&& offset
.type() == RegType::vgpr
)
4747 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4749 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4750 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4751 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4752 Operand(desc_type
));
4754 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, offset
);
4757 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4759 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4760 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4762 ctx
->program
->needs_exact
= true;
4764 // TODO: optimize uniform conditions
4765 Builder
bld(ctx
->program
, ctx
->block
);
4766 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4767 assert(src
.regClass() == bld
.lm
);
4768 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
4769 bld
.pseudo(aco_opcode::p_discard_if
, src
);
4770 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4774 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
4776 Builder
bld(ctx
->program
, ctx
->block
);
4778 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4779 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4781 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
4782 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
4784 if (ctx
->block
->loop_nest_depth
&&
4785 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
4786 /* we handle discards the same way as jump instructions */
4787 append_logical_end(ctx
->block
);
4789 /* in loops, discard behaves like break */
4790 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
4791 ctx
->block
->kind
|= block_kind_discard
;
4794 /* uniform discard - loop ends here */
4795 assert(nir_instr_is_last(&instr
->instr
));
4796 ctx
->block
->kind
|= block_kind_uniform
;
4797 ctx
->cf_info
.has_branch
= true;
4798 bld
.branch(aco_opcode::p_branch
);
4799 add_linear_edge(ctx
->block
->index
, linear_target
);
4803 /* we add a break right behind the discard() instructions */
4804 ctx
->block
->kind
|= block_kind_break
;
4805 unsigned idx
= ctx
->block
->index
;
4807 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
4808 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
4810 /* remove critical edges from linear CFG */
4811 bld
.branch(aco_opcode::p_branch
);
4812 Block
* break_block
= ctx
->program
->create_and_insert_block();
4813 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4814 break_block
->kind
|= block_kind_uniform
;
4815 add_linear_edge(idx
, break_block
);
4816 add_linear_edge(break_block
->index
, linear_target
);
4817 bld
.reset(break_block
);
4818 bld
.branch(aco_opcode::p_branch
);
4820 Block
* continue_block
= ctx
->program
->create_and_insert_block();
4821 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4822 add_linear_edge(idx
, continue_block
);
4823 append_logical_start(continue_block
);
4824 ctx
->block
= continue_block
;
4829 /* it can currently happen that NIR doesn't remove the unreachable code */
4830 if (!nir_instr_is_last(&instr
->instr
)) {
4831 ctx
->program
->needs_exact
= true;
4832 /* save exec somewhere temporarily so that it doesn't get
4833 * overwritten before the discard from outer exec masks */
4834 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
4835 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
4836 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4840 /* This condition is incorrect for uniformly branched discards in a loop
4841 * predicated by a divergent condition, but the above code catches that case
4842 * and the discard would end up turning into a discard_if.
4852 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
4853 /* program just ends here */
4854 ctx
->block
->kind
|= block_kind_uniform
;
4855 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
4856 0 /* enabled mask */, 9 /* dest */,
4857 false /* compressed */, true/* done */, true /* valid mask */);
4858 bld
.sopp(aco_opcode::s_endpgm
);
4859 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4861 ctx
->block
->kind
|= block_kind_discard
;
4862 /* branch and linear edge is added by visit_if() */
4866 enum aco_descriptor_type
{
4877 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
4878 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4880 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
4881 return dim
== ac_image_cube
||
4882 dim
== ac_image_1darray
||
4883 dim
== ac_image_2darray
||
4884 dim
== ac_image_2darraymsaa
;
4887 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
4888 enum aco_descriptor_type desc_type
,
4889 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
4891 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4892 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4893 if (it != ctx->tex_desc.end())
4896 Temp index
= Temp();
4897 bool index_set
= false;
4898 unsigned constant_index
= 0;
4899 unsigned descriptor_set
;
4900 unsigned base_index
;
4901 Builder
bld(ctx
->program
, ctx
->block
);
4904 assert(tex_instr
&& !image
);
4906 base_index
= tex_instr
->sampler_index
;
4908 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
4909 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
4913 assert(deref_instr
->deref_type
== nir_deref_type_array
);
4914 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
4916 constant_index
+= array_size
* const_value
->u32
;
4918 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
4919 if (indirect
.type() == RegType::vgpr
)
4920 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
4922 if (array_size
!= 1)
4923 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
4929 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
4933 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
4935 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
4936 base_index
= deref_instr
->var
->data
.binding
;
4939 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
4940 list
= convert_pointer_to_64_bit(ctx
, list
);
4942 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4943 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4944 unsigned offset
= binding
->offset
;
4945 unsigned stride
= binding
->size
;
4949 assert(base_index
< layout
->binding_count
);
4951 switch (desc_type
) {
4952 case ACO_DESC_IMAGE
:
4954 opcode
= aco_opcode::s_load_dwordx8
;
4956 case ACO_DESC_FMASK
:
4958 opcode
= aco_opcode::s_load_dwordx8
;
4961 case ACO_DESC_SAMPLER
:
4963 opcode
= aco_opcode::s_load_dwordx4
;
4964 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4965 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
4967 case ACO_DESC_BUFFER
:
4969 opcode
= aco_opcode::s_load_dwordx4
;
4971 case ACO_DESC_PLANE_0
:
4972 case ACO_DESC_PLANE_1
:
4974 opcode
= aco_opcode::s_load_dwordx8
;
4975 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
4977 case ACO_DESC_PLANE_2
:
4979 opcode
= aco_opcode::s_load_dwordx4
;
4983 unreachable("invalid desc_type\n");
4986 offset
+= constant_index
* stride
;
4988 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4989 (!index_set
|| binding
->immutable_samplers_equal
)) {
4990 if (binding
->immutable_samplers_equal
)
4993 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4994 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4995 Operand(samplers
[constant_index
* 4 + 0]),
4996 Operand(samplers
[constant_index
* 4 + 1]),
4997 Operand(samplers
[constant_index
* 4 + 2]),
4998 Operand(samplers
[constant_index
* 4 + 3]));
5003 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5005 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5006 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5009 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5011 if (desc_type
== ACO_DESC_PLANE_2
) {
5013 for (unsigned i
= 0; i
< 8; i
++)
5014 components
[i
] = bld
.tmp(s1
);
5015 bld
.pseudo(aco_opcode::p_split_vector
,
5016 Definition(components
[0]),
5017 Definition(components
[1]),
5018 Definition(components
[2]),
5019 Definition(components
[3]),
5022 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5023 bld
.pseudo(aco_opcode::p_split_vector
,
5024 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5025 Definition(components
[4]),
5026 Definition(components
[5]),
5027 Definition(components
[6]),
5028 Definition(components
[7]),
5031 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5032 components
[0], components
[1], components
[2], components
[3],
5033 components
[4], components
[5], components
[6], components
[7]);
5039 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5042 case GLSL_SAMPLER_DIM_BUF
:
5044 case GLSL_SAMPLER_DIM_1D
:
5045 return array
? 2 : 1;
5046 case GLSL_SAMPLER_DIM_2D
:
5047 return array
? 3 : 2;
5048 case GLSL_SAMPLER_DIM_MS
:
5049 return array
? 4 : 3;
5050 case GLSL_SAMPLER_DIM_3D
:
5051 case GLSL_SAMPLER_DIM_CUBE
:
5053 case GLSL_SAMPLER_DIM_RECT
:
5054 case GLSL_SAMPLER_DIM_SUBPASS
:
5056 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5065 /* Adjust the sample index according to FMASK.
5067 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5068 * which is the identity mapping. Each nibble says which physical sample
5069 * should be fetched to get that sample.
5071 * For example, 0x11111100 means there are only 2 samples stored and
5072 * the second sample covers 3/4 of the pixel. When reading samples 0
5073 * and 1, return physical sample 0 (determined by the first two 0s
5074 * in FMASK), otherwise return physical sample 1.
5076 * The sample index should be adjusted as follows:
5077 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5079 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5081 Builder
bld(ctx
->program
, ctx
->block
);
5082 Temp fmask
= bld
.tmp(v1
);
5083 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5084 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5087 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5088 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5089 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5090 load
->operands
[0] = Operand(fmask_desc_ptr
);
5091 load
->operands
[1] = Operand(s4
); /* no sampler */
5092 load
->operands
[2] = Operand(coord
);
5093 load
->definitions
[0] = Definition(fmask
);
5100 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5101 ctx
->block
->instructions
.emplace_back(std::move(load
));
5103 Operand sample_index4
;
5104 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5105 sample_index4
= Operand(sample_index
.constantValue() << 2);
5106 } else if (sample_index
.regClass() == s1
) {
5107 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5109 assert(sample_index
.regClass() == v1
);
5110 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5114 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5115 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5116 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5117 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5119 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5121 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5122 * resource descriptor is 0 (invalid),
5124 Temp compare
= bld
.tmp(bld
.lm
);
5125 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5126 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5128 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5130 /* Replace the MSAA sample index. */
5131 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5134 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5137 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5138 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5139 bool is_array
= glsl_sampler_type_is_array(type
);
5140 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5141 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5142 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5143 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5144 int count
= image_type_to_components_count(dim
, is_array
);
5145 std::vector
<Temp
> coords(count
);
5146 Builder
bld(ctx
->program
, ctx
->block
);
5150 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5151 /* get sample index */
5152 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5153 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5154 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5155 std::vector
<Temp
> fmask_load_address
;
5156 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5157 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5159 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5160 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5162 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5167 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5168 coords
.resize(coords
.size() + 1);
5169 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5171 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5173 for (int i
= 0; i
< count
; i
++)
5174 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5177 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5178 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5179 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5180 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5183 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5186 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5187 for (unsigned i
= 0; i
< coords
.size(); i
++)
5188 vec
->operands
[i
] = Operand(coords
[i
]);
5189 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5190 vec
->definitions
[0] = Definition(res
);
5191 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5196 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5198 Builder
bld(ctx
->program
, ctx
->block
);
5199 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5200 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5201 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5202 bool is_array
= glsl_sampler_type_is_array(type
);
5203 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5205 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5206 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5207 unsigned num_channels
= util_last_bit(mask
);
5208 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5209 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5212 switch (num_channels
) {
5214 opcode
= aco_opcode::buffer_load_format_x
;
5217 opcode
= aco_opcode::buffer_load_format_xy
;
5220 opcode
= aco_opcode::buffer_load_format_xyz
;
5223 opcode
= aco_opcode::buffer_load_format_xyzw
;
5226 unreachable(">4 channel buffer image load");
5228 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5229 load
->operands
[0] = Operand(rsrc
);
5230 load
->operands
[1] = Operand(vindex
);
5231 load
->operands
[2] = Operand((uint32_t) 0);
5233 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5236 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5237 load
->definitions
[0] = Definition(tmp
);
5239 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5240 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5241 load
->barrier
= barrier_image
;
5242 ctx
->block
->instructions
.emplace_back(std::move(load
));
5244 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5248 Temp coords
= get_image_coords(ctx
, instr
, type
);
5249 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5251 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5252 unsigned num_components
= util_bitcount(dmask
);
5254 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5257 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5259 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5260 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5262 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5263 load
->operands
[0] = Operand(resource
);
5264 load
->operands
[1] = Operand(s4
); /* no sampler */
5265 load
->operands
[2] = Operand(coords
);
5266 load
->definitions
[0] = Definition(tmp
);
5267 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5268 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5269 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5270 load
->dmask
= dmask
;
5272 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5273 load
->barrier
= barrier_image
;
5274 ctx
->block
->instructions
.emplace_back(std::move(load
));
5276 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5280 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5282 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5283 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5284 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5285 bool is_array
= glsl_sampler_type_is_array(type
);
5286 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5288 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5290 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5291 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5292 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5294 switch (data
.size()) {
5296 opcode
= aco_opcode::buffer_store_format_x
;
5299 opcode
= aco_opcode::buffer_store_format_xy
;
5302 opcode
= aco_opcode::buffer_store_format_xyz
;
5305 opcode
= aco_opcode::buffer_store_format_xyzw
;
5308 unreachable(">4 channel buffer image store");
5310 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5311 store
->operands
[0] = Operand(rsrc
);
5312 store
->operands
[1] = Operand(vindex
);
5313 store
->operands
[2] = Operand((uint32_t) 0);
5314 store
->operands
[3] = Operand(data
);
5315 store
->idxen
= true;
5318 store
->disable_wqm
= true;
5319 store
->barrier
= barrier_image
;
5320 ctx
->program
->needs_exact
= true;
5321 ctx
->block
->instructions
.emplace_back(std::move(store
));
5325 assert(data
.type() == RegType::vgpr
);
5326 Temp coords
= get_image_coords(ctx
, instr
, type
);
5327 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5329 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5330 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5332 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5333 store
->operands
[0] = Operand(resource
);
5334 store
->operands
[1] = Operand(data
);
5335 store
->operands
[2] = Operand(coords
);
5338 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5339 store
->dmask
= (1 << data
.size()) - 1;
5341 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5342 store
->disable_wqm
= true;
5343 store
->barrier
= barrier_image
;
5344 ctx
->program
->needs_exact
= true;
5345 ctx
->block
->instructions
.emplace_back(std::move(store
));
5349 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5351 /* return the previous value if dest is ever used */
5352 bool return_previous
= false;
5353 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5354 return_previous
= true;
5357 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5358 return_previous
= true;
5362 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5363 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5364 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5365 bool is_array
= glsl_sampler_type_is_array(type
);
5366 Builder
bld(ctx
->program
, ctx
->block
);
5368 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5369 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5371 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5372 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5374 aco_opcode buf_op
, image_op
;
5375 switch (instr
->intrinsic
) {
5376 case nir_intrinsic_image_deref_atomic_add
:
5377 buf_op
= aco_opcode::buffer_atomic_add
;
5378 image_op
= aco_opcode::image_atomic_add
;
5380 case nir_intrinsic_image_deref_atomic_umin
:
5381 buf_op
= aco_opcode::buffer_atomic_umin
;
5382 image_op
= aco_opcode::image_atomic_umin
;
5384 case nir_intrinsic_image_deref_atomic_imin
:
5385 buf_op
= aco_opcode::buffer_atomic_smin
;
5386 image_op
= aco_opcode::image_atomic_smin
;
5388 case nir_intrinsic_image_deref_atomic_umax
:
5389 buf_op
= aco_opcode::buffer_atomic_umax
;
5390 image_op
= aco_opcode::image_atomic_umax
;
5392 case nir_intrinsic_image_deref_atomic_imax
:
5393 buf_op
= aco_opcode::buffer_atomic_smax
;
5394 image_op
= aco_opcode::image_atomic_smax
;
5396 case nir_intrinsic_image_deref_atomic_and
:
5397 buf_op
= aco_opcode::buffer_atomic_and
;
5398 image_op
= aco_opcode::image_atomic_and
;
5400 case nir_intrinsic_image_deref_atomic_or
:
5401 buf_op
= aco_opcode::buffer_atomic_or
;
5402 image_op
= aco_opcode::image_atomic_or
;
5404 case nir_intrinsic_image_deref_atomic_xor
:
5405 buf_op
= aco_opcode::buffer_atomic_xor
;
5406 image_op
= aco_opcode::image_atomic_xor
;
5408 case nir_intrinsic_image_deref_atomic_exchange
:
5409 buf_op
= aco_opcode::buffer_atomic_swap
;
5410 image_op
= aco_opcode::image_atomic_swap
;
5412 case nir_intrinsic_image_deref_atomic_comp_swap
:
5413 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5414 image_op
= aco_opcode::image_atomic_cmpswap
;
5417 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5420 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5422 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5423 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5424 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5425 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5426 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5427 mubuf
->operands
[0] = Operand(resource
);
5428 mubuf
->operands
[1] = Operand(vindex
);
5429 mubuf
->operands
[2] = Operand((uint32_t)0);
5430 mubuf
->operands
[3] = Operand(data
);
5431 if (return_previous
)
5432 mubuf
->definitions
[0] = Definition(dst
);
5434 mubuf
->idxen
= true;
5435 mubuf
->glc
= return_previous
;
5436 mubuf
->dlc
= false; /* Not needed for atomics */
5437 mubuf
->disable_wqm
= true;
5438 mubuf
->barrier
= barrier_image
;
5439 ctx
->program
->needs_exact
= true;
5440 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5444 Temp coords
= get_image_coords(ctx
, instr
, type
);
5445 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5446 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5447 mimg
->operands
[0] = Operand(resource
);
5448 mimg
->operands
[1] = Operand(data
);
5449 mimg
->operands
[2] = Operand(coords
);
5450 if (return_previous
)
5451 mimg
->definitions
[0] = Definition(dst
);
5452 mimg
->glc
= return_previous
;
5453 mimg
->dlc
= false; /* Not needed for atomics */
5454 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5455 mimg
->dmask
= (1 << data
.size()) - 1;
5457 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5458 mimg
->disable_wqm
= true;
5459 mimg
->barrier
= barrier_image
;
5460 ctx
->program
->needs_exact
= true;
5461 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5465 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5467 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5468 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5469 Builder
bld(ctx
->program
, ctx
->block
);
5471 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5473 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5474 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5476 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5477 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5479 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5480 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5482 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5483 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5484 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5485 if (dst
.type() == RegType::vgpr
)
5486 bld
.copy(Definition(dst
), shr_dst
);
5488 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5490 emit_extract_vector(ctx
, desc
, 2, dst
);
5494 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5496 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5497 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5498 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5499 bool is_array
= glsl_sampler_type_is_array(type
);
5500 Builder
bld(ctx
->program
, ctx
->block
);
5502 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5503 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5504 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5508 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5511 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5513 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5515 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5516 mimg
->operands
[0] = Operand(resource
);
5517 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5518 mimg
->operands
[2] = Operand(lod
);
5519 uint8_t& dmask
= mimg
->dmask
;
5520 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5521 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5522 mimg
->da
= glsl_sampler_type_is_array(type
);
5523 mimg
->can_reorder
= true;
5524 Definition
& def
= mimg
->definitions
[0];
5525 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5527 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5528 glsl_sampler_type_is_array(type
)) {
5530 assert(instr
->dest
.ssa
.num_components
== 3);
5531 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5532 def
= Definition(tmp
);
5533 emit_split_vector(ctx
, tmp
, 3);
5535 /* divide 3rd value by 6 by multiplying with magic number */
5536 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5537 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5539 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5540 emit_extract_vector(ctx
, tmp
, 0, v1
),
5541 emit_extract_vector(ctx
, tmp
, 1, v1
),
5544 } else if (ctx
->options
->chip_class
== GFX9
&&
5545 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5546 glsl_sampler_type_is_array(type
)) {
5547 assert(instr
->dest
.ssa
.num_components
== 2);
5548 def
= Definition(dst
);
5551 def
= Definition(dst
);
5554 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5557 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5559 Builder
bld(ctx
->program
, ctx
->block
);
5560 unsigned num_components
= instr
->num_components
;
5562 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5563 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5564 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5566 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5567 load_buffer(ctx
, num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), glc
, false);
5570 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5572 Builder
bld(ctx
->program
, ctx
->block
);
5573 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5574 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5575 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5576 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5578 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5579 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5581 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5582 ctx
->options
->chip_class
>= GFX8
;
5584 offset
= bld
.as_uniform(offset
);
5585 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5589 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5590 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5591 /* GFX6 doesn't support storing vec3, split it. */
5592 writemask
|= 1u << (start
+ 2);
5595 int num_bytes
= count
* elem_size_bytes
;
5597 if (num_bytes
> 16) {
5598 assert(elem_size_bytes
== 8);
5599 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5604 // TODO: check alignment of sub-dword stores
5605 // TODO: split 3 bytes. there is no store instruction for that
5608 if (count
!= instr
->num_components
) {
5609 emit_split_vector(ctx
, data
, instr
->num_components
);
5610 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5611 for (int i
= 0; i
< count
; i
++) {
5612 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5613 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5615 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5616 vec
->definitions
[0] = Definition(write_data
);
5617 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5618 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5619 assert(num_bytes
% 4 == 0);
5620 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5621 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5622 assert(num_bytes
% 4 == 0);
5623 write_data
= bld
.as_uniform(data
);
5628 aco_opcode vmem_op
, smem_op
;
5629 switch (num_bytes
) {
5631 vmem_op
= aco_opcode::buffer_store_dword
;
5632 smem_op
= aco_opcode::s_buffer_store_dword
;
5635 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5636 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5639 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5640 smem_op
= aco_opcode::last_opcode
;
5641 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5644 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5645 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5648 unreachable("Store SSBO not implemented for this size.");
5650 if (ctx
->stage
== fragment_fs
)
5651 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5654 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5655 store
->operands
[0] = Operand(rsrc
);
5657 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5658 offset
, Operand(start
* elem_size_bytes
));
5659 store
->operands
[1] = Operand(off
);
5661 store
->operands
[1] = Operand(offset
);
5663 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5664 store
->operands
[1].setFixed(m0
);
5665 store
->operands
[2] = Operand(write_data
);
5666 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5668 store
->disable_wqm
= true;
5669 store
->barrier
= barrier_buffer
;
5670 ctx
->block
->instructions
.emplace_back(std::move(store
));
5671 ctx
->program
->wb_smem_l1_on_end
= true;
5672 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5673 ctx
->block
->kind
|= block_kind_needs_lowering
;
5674 ctx
->program
->needs_exact
= true;
5677 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5678 store
->operands
[0] = Operand(rsrc
);
5679 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5680 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5681 store
->operands
[3] = Operand(write_data
);
5682 store
->offset
= start
* elem_size_bytes
;
5683 store
->offen
= (offset
.type() == RegType::vgpr
);
5684 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5686 store
->disable_wqm
= true;
5687 store
->barrier
= barrier_buffer
;
5688 ctx
->program
->needs_exact
= true;
5689 ctx
->block
->instructions
.emplace_back(std::move(store
));
5694 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5696 /* return the previous value if dest is ever used */
5697 bool return_previous
= false;
5698 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5699 return_previous
= true;
5702 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5703 return_previous
= true;
5707 Builder
bld(ctx
->program
, ctx
->block
);
5708 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5710 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5711 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5712 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5714 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5715 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5716 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5718 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5720 aco_opcode op32
, op64
;
5721 switch (instr
->intrinsic
) {
5722 case nir_intrinsic_ssbo_atomic_add
:
5723 op32
= aco_opcode::buffer_atomic_add
;
5724 op64
= aco_opcode::buffer_atomic_add_x2
;
5726 case nir_intrinsic_ssbo_atomic_imin
:
5727 op32
= aco_opcode::buffer_atomic_smin
;
5728 op64
= aco_opcode::buffer_atomic_smin_x2
;
5730 case nir_intrinsic_ssbo_atomic_umin
:
5731 op32
= aco_opcode::buffer_atomic_umin
;
5732 op64
= aco_opcode::buffer_atomic_umin_x2
;
5734 case nir_intrinsic_ssbo_atomic_imax
:
5735 op32
= aco_opcode::buffer_atomic_smax
;
5736 op64
= aco_opcode::buffer_atomic_smax_x2
;
5738 case nir_intrinsic_ssbo_atomic_umax
:
5739 op32
= aco_opcode::buffer_atomic_umax
;
5740 op64
= aco_opcode::buffer_atomic_umax_x2
;
5742 case nir_intrinsic_ssbo_atomic_and
:
5743 op32
= aco_opcode::buffer_atomic_and
;
5744 op64
= aco_opcode::buffer_atomic_and_x2
;
5746 case nir_intrinsic_ssbo_atomic_or
:
5747 op32
= aco_opcode::buffer_atomic_or
;
5748 op64
= aco_opcode::buffer_atomic_or_x2
;
5750 case nir_intrinsic_ssbo_atomic_xor
:
5751 op32
= aco_opcode::buffer_atomic_xor
;
5752 op64
= aco_opcode::buffer_atomic_xor_x2
;
5754 case nir_intrinsic_ssbo_atomic_exchange
:
5755 op32
= aco_opcode::buffer_atomic_swap
;
5756 op64
= aco_opcode::buffer_atomic_swap_x2
;
5758 case nir_intrinsic_ssbo_atomic_comp_swap
:
5759 op32
= aco_opcode::buffer_atomic_cmpswap
;
5760 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
5763 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5765 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5766 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5767 mubuf
->operands
[0] = Operand(rsrc
);
5768 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5769 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5770 mubuf
->operands
[3] = Operand(data
);
5771 if (return_previous
)
5772 mubuf
->definitions
[0] = Definition(dst
);
5774 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
5775 mubuf
->glc
= return_previous
;
5776 mubuf
->dlc
= false; /* Not needed for atomics */
5777 mubuf
->disable_wqm
= true;
5778 mubuf
->barrier
= barrier_buffer
;
5779 ctx
->program
->needs_exact
= true;
5780 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5783 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5785 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5786 Builder
bld(ctx
->program
, ctx
->block
);
5787 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
5788 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
5791 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
5793 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5794 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5796 if (addr
.type() == RegType::vgpr
)
5797 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
5798 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
5801 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5803 Builder
bld(ctx
->program
, ctx
->block
);
5804 unsigned num_components
= instr
->num_components
;
5805 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
5807 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5808 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5810 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5811 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
5813 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
5814 bool global
= ctx
->options
->chip_class
>= GFX9
;
5816 if (ctx
->options
->chip_class
>= GFX7
) {
5818 switch (num_bytes
) {
5820 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
5823 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
5826 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
5829 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
5832 unreachable("load_global not implemented for this size.");
5835 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
5836 flat
->operands
[0] = Operand(addr
);
5837 flat
->operands
[1] = Operand(s1
);
5840 flat
->barrier
= barrier_buffer
;
5842 if (dst
.type() == RegType::sgpr
) {
5843 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5844 flat
->definitions
[0] = Definition(vec
);
5845 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5846 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
5848 flat
->definitions
[0] = Definition(dst
);
5849 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5851 emit_split_vector(ctx
, dst
, num_components
);
5853 assert(ctx
->options
->chip_class
== GFX6
);
5855 /* GFX6 doesn't support loading vec3, expand to vec4. */
5856 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
5859 switch (num_bytes
) {
5861 op
= aco_opcode::buffer_load_dword
;
5864 op
= aco_opcode::buffer_load_dwordx2
;
5867 op
= aco_opcode::buffer_load_dwordx4
;
5870 unreachable("load_global not implemented for this size.");
5873 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
5875 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
5876 mubuf
->operands
[0] = Operand(rsrc
);
5877 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
5878 mubuf
->operands
[2] = Operand(0u);
5882 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
5883 mubuf
->disable_wqm
= false;
5884 mubuf
->barrier
= barrier_buffer
;
5885 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
5888 if (dst
.size() == 3) {
5889 Temp vec
= bld
.tmp(v4
);
5890 instr
->definitions
[0] = Definition(vec
);
5891 bld
.insert(std::move(instr
));
5892 emit_split_vector(ctx
, vec
, 4);
5894 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
5895 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
5896 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
5897 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
5900 if (dst
.type() == RegType::sgpr
) {
5901 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5902 instr
->definitions
[0] = Definition(vec
);
5903 bld
.insert(std::move(instr
));
5904 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
5905 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
5907 instr
->definitions
[0] = Definition(dst
);
5908 bld
.insert(std::move(instr
));
5909 emit_split_vector(ctx
, dst
, num_components
);
5913 switch (num_bytes
) {
5915 op
= aco_opcode::s_load_dword
;
5918 op
= aco_opcode::s_load_dwordx2
;
5922 op
= aco_opcode::s_load_dwordx4
;
5925 unreachable("load_global not implemented for this size.");
5927 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
5928 load
->operands
[0] = Operand(addr
);
5929 load
->operands
[1] = Operand(0u);
5930 load
->definitions
[0] = Definition(dst
);
5933 load
->barrier
= barrier_buffer
;
5934 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
5936 if (dst
.size() == 3) {
5938 Temp vec
= bld
.tmp(s4
);
5939 load
->definitions
[0] = Definition(vec
);
5940 ctx
->block
->instructions
.emplace_back(std::move(load
));
5941 emit_split_vector(ctx
, vec
, 4);
5943 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5944 emit_extract_vector(ctx
, vec
, 0, s1
),
5945 emit_extract_vector(ctx
, vec
, 1, s1
),
5946 emit_extract_vector(ctx
, vec
, 2, s1
));
5948 ctx
->block
->instructions
.emplace_back(std::move(load
));
5953 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5955 Builder
bld(ctx
->program
, ctx
->block
);
5956 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5958 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5959 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5961 if (ctx
->options
->chip_class
>= GFX7
)
5962 addr
= as_vgpr(ctx
, addr
);
5964 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5967 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5968 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
5969 /* GFX6 doesn't support storing vec3, split it. */
5970 writemask
|= 1u << (start
+ 2);
5973 unsigned num_bytes
= count
* elem_size_bytes
;
5975 Temp write_data
= data
;
5976 if (count
!= instr
->num_components
) {
5977 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5978 for (int i
= 0; i
< count
; i
++)
5979 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
5980 write_data
= bld
.tmp(RegType::vgpr
, count
);
5981 vec
->definitions
[0] = Definition(write_data
);
5982 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5985 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5986 unsigned offset
= start
* elem_size_bytes
;
5988 if (ctx
->options
->chip_class
>= GFX7
) {
5989 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
5990 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
5991 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
5992 Temp carry
= bld
.tmp(bld
.lm
);
5993 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
5995 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
5996 Operand(offset
), addr0
);
5997 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
5999 carry
).def(1).setHint(vcc
);
6001 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6006 bool global
= ctx
->options
->chip_class
>= GFX9
;
6008 switch (num_bytes
) {
6010 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6013 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6016 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6019 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6022 unreachable("store_global not implemented for this size.");
6025 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6026 flat
->operands
[0] = Operand(addr
);
6027 flat
->operands
[1] = Operand(s1
);
6028 flat
->operands
[2] = Operand(data
);
6031 flat
->offset
= offset
;
6032 flat
->disable_wqm
= true;
6033 flat
->barrier
= barrier_buffer
;
6034 ctx
->program
->needs_exact
= true;
6035 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6037 assert(ctx
->options
->chip_class
== GFX6
);
6040 switch (num_bytes
) {
6042 op
= aco_opcode::buffer_store_dword
;
6045 op
= aco_opcode::buffer_store_dwordx2
;
6048 op
= aco_opcode::buffer_store_dwordx4
;
6051 unreachable("store_global not implemented for this size.");
6054 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6056 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6057 mubuf
->operands
[0] = Operand(rsrc
);
6058 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6059 mubuf
->operands
[2] = Operand(0u);
6060 mubuf
->operands
[3] = Operand(write_data
);
6063 mubuf
->offset
= offset
;
6064 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6065 mubuf
->disable_wqm
= true;
6066 mubuf
->barrier
= barrier_buffer
;
6067 ctx
->program
->needs_exact
= true;
6068 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6073 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6075 /* return the previous value if dest is ever used */
6076 bool return_previous
= false;
6077 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6078 return_previous
= true;
6081 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6082 return_previous
= true;
6086 Builder
bld(ctx
->program
, ctx
->block
);
6087 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6088 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6090 if (ctx
->options
->chip_class
>= GFX7
)
6091 addr
= as_vgpr(ctx
, addr
);
6093 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6094 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6095 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6097 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6099 aco_opcode op32
, op64
;
6101 if (ctx
->options
->chip_class
>= GFX7
) {
6102 bool global
= ctx
->options
->chip_class
>= GFX9
;
6103 switch (instr
->intrinsic
) {
6104 case nir_intrinsic_global_atomic_add
:
6105 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6106 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6108 case nir_intrinsic_global_atomic_imin
:
6109 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6110 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6112 case nir_intrinsic_global_atomic_umin
:
6113 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6114 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6116 case nir_intrinsic_global_atomic_imax
:
6117 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6118 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6120 case nir_intrinsic_global_atomic_umax
:
6121 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6122 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6124 case nir_intrinsic_global_atomic_and
:
6125 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6126 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6128 case nir_intrinsic_global_atomic_or
:
6129 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6130 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6132 case nir_intrinsic_global_atomic_xor
:
6133 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6134 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6136 case nir_intrinsic_global_atomic_exchange
:
6137 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6138 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6140 case nir_intrinsic_global_atomic_comp_swap
:
6141 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6142 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6145 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6148 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6149 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6150 flat
->operands
[0] = Operand(addr
);
6151 flat
->operands
[1] = Operand(s1
);
6152 flat
->operands
[2] = Operand(data
);
6153 if (return_previous
)
6154 flat
->definitions
[0] = Definition(dst
);
6155 flat
->glc
= return_previous
;
6156 flat
->dlc
= false; /* Not needed for atomics */
6158 flat
->disable_wqm
= true;
6159 flat
->barrier
= barrier_buffer
;
6160 ctx
->program
->needs_exact
= true;
6161 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6163 assert(ctx
->options
->chip_class
== GFX6
);
6165 switch (instr
->intrinsic
) {
6166 case nir_intrinsic_global_atomic_add
:
6167 op32
= aco_opcode::buffer_atomic_add
;
6168 op64
= aco_opcode::buffer_atomic_add_x2
;
6170 case nir_intrinsic_global_atomic_imin
:
6171 op32
= aco_opcode::buffer_atomic_smin
;
6172 op64
= aco_opcode::buffer_atomic_smin_x2
;
6174 case nir_intrinsic_global_atomic_umin
:
6175 op32
= aco_opcode::buffer_atomic_umin
;
6176 op64
= aco_opcode::buffer_atomic_umin_x2
;
6178 case nir_intrinsic_global_atomic_imax
:
6179 op32
= aco_opcode::buffer_atomic_smax
;
6180 op64
= aco_opcode::buffer_atomic_smax_x2
;
6182 case nir_intrinsic_global_atomic_umax
:
6183 op32
= aco_opcode::buffer_atomic_umax
;
6184 op64
= aco_opcode::buffer_atomic_umax_x2
;
6186 case nir_intrinsic_global_atomic_and
:
6187 op32
= aco_opcode::buffer_atomic_and
;
6188 op64
= aco_opcode::buffer_atomic_and_x2
;
6190 case nir_intrinsic_global_atomic_or
:
6191 op32
= aco_opcode::buffer_atomic_or
;
6192 op64
= aco_opcode::buffer_atomic_or_x2
;
6194 case nir_intrinsic_global_atomic_xor
:
6195 op32
= aco_opcode::buffer_atomic_xor
;
6196 op64
= aco_opcode::buffer_atomic_xor_x2
;
6198 case nir_intrinsic_global_atomic_exchange
:
6199 op32
= aco_opcode::buffer_atomic_swap
;
6200 op64
= aco_opcode::buffer_atomic_swap_x2
;
6202 case nir_intrinsic_global_atomic_comp_swap
:
6203 op32
= aco_opcode::buffer_atomic_cmpswap
;
6204 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6207 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6210 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6212 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6214 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6215 mubuf
->operands
[0] = Operand(rsrc
);
6216 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6217 mubuf
->operands
[2] = Operand(0u);
6218 mubuf
->operands
[3] = Operand(data
);
6219 if (return_previous
)
6220 mubuf
->definitions
[0] = Definition(dst
);
6221 mubuf
->glc
= return_previous
;
6224 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6225 mubuf
->disable_wqm
= true;
6226 mubuf
->barrier
= barrier_buffer
;
6227 ctx
->program
->needs_exact
= true;
6228 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6232 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6233 Builder
bld(ctx
->program
, ctx
->block
);
6234 switch(instr
->intrinsic
) {
6235 case nir_intrinsic_group_memory_barrier
:
6236 case nir_intrinsic_memory_barrier
:
6237 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6239 case nir_intrinsic_memory_barrier_buffer
:
6240 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6242 case nir_intrinsic_memory_barrier_image
:
6243 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6245 case nir_intrinsic_memory_barrier_tcs_patch
:
6246 case nir_intrinsic_memory_barrier_shared
:
6247 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6250 unreachable("Unimplemented memory barrier intrinsic");
6255 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6257 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6258 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6259 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6260 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6261 Builder
bld(ctx
->program
, ctx
->block
);
6263 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6264 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6265 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6268 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6270 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6271 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6272 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6273 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6274 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6276 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6277 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6280 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6282 unsigned offset
= nir_intrinsic_base(instr
);
6283 Operand m
= load_lds_size_m0(ctx
);
6284 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6285 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6287 unsigned num_operands
= 3;
6288 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6289 switch(instr
->intrinsic
) {
6290 case nir_intrinsic_shared_atomic_add
:
6291 op32
= aco_opcode::ds_add_u32
;
6292 op64
= aco_opcode::ds_add_u64
;
6293 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6294 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6296 case nir_intrinsic_shared_atomic_imin
:
6297 op32
= aco_opcode::ds_min_i32
;
6298 op64
= aco_opcode::ds_min_i64
;
6299 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6300 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6302 case nir_intrinsic_shared_atomic_umin
:
6303 op32
= aco_opcode::ds_min_u32
;
6304 op64
= aco_opcode::ds_min_u64
;
6305 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6306 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6308 case nir_intrinsic_shared_atomic_imax
:
6309 op32
= aco_opcode::ds_max_i32
;
6310 op64
= aco_opcode::ds_max_i64
;
6311 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6312 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6314 case nir_intrinsic_shared_atomic_umax
:
6315 op32
= aco_opcode::ds_max_u32
;
6316 op64
= aco_opcode::ds_max_u64
;
6317 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6318 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6320 case nir_intrinsic_shared_atomic_and
:
6321 op32
= aco_opcode::ds_and_b32
;
6322 op64
= aco_opcode::ds_and_b64
;
6323 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6324 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6326 case nir_intrinsic_shared_atomic_or
:
6327 op32
= aco_opcode::ds_or_b32
;
6328 op64
= aco_opcode::ds_or_b64
;
6329 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6330 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6332 case nir_intrinsic_shared_atomic_xor
:
6333 op32
= aco_opcode::ds_xor_b32
;
6334 op64
= aco_opcode::ds_xor_b64
;
6335 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6336 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6338 case nir_intrinsic_shared_atomic_exchange
:
6339 op32
= aco_opcode::ds_write_b32
;
6340 op64
= aco_opcode::ds_write_b64
;
6341 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6342 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6344 case nir_intrinsic_shared_atomic_comp_swap
:
6345 op32
= aco_opcode::ds_cmpst_b32
;
6346 op64
= aco_opcode::ds_cmpst_b64
;
6347 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6348 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6352 unreachable("Unhandled shared atomic intrinsic");
6355 /* return the previous value if dest is ever used */
6356 bool return_previous
= false;
6357 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6358 return_previous
= true;
6361 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6362 return_previous
= true;
6367 if (data
.size() == 1) {
6368 assert(instr
->dest
.ssa
.bit_size
== 32);
6369 op
= return_previous
? op32_rtn
: op32
;
6371 assert(instr
->dest
.ssa
.bit_size
== 64);
6372 op
= return_previous
? op64_rtn
: op64
;
6375 if (offset
> 65535) {
6376 Builder
bld(ctx
->program
, ctx
->block
);
6377 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6381 aco_ptr
<DS_instruction
> ds
;
6382 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6383 ds
->operands
[0] = Operand(address
);
6384 ds
->operands
[1] = Operand(data
);
6385 if (num_operands
== 4)
6386 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6387 ds
->operands
[num_operands
- 1] = m
;
6388 ds
->offset0
= offset
;
6389 if (return_previous
)
6390 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6391 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6394 Temp
get_scratch_resource(isel_context
*ctx
)
6396 Builder
bld(ctx
->program
, ctx
->block
);
6397 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6398 if (ctx
->stage
!= compute_cs
)
6399 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6401 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6402 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6404 if (ctx
->program
->chip_class
>= GFX10
) {
6405 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6406 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6407 S_008F0C_RESOURCE_LEVEL(1);
6408 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6409 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6410 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6413 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6414 if (ctx
->program
->chip_class
<= GFX8
)
6415 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6417 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6420 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6421 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6422 Builder
bld(ctx
->program
, ctx
->block
);
6423 Temp rsrc
= get_scratch_resource(ctx
);
6424 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6425 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6428 switch (dst
.size()) {
6430 op
= aco_opcode::buffer_load_dword
;
6433 op
= aco_opcode::buffer_load_dwordx2
;
6436 op
= aco_opcode::buffer_load_dwordx3
;
6439 op
= aco_opcode::buffer_load_dwordx4
;
6443 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6444 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6445 bld
.def(v4
), rsrc
, offset
,
6446 ctx
->program
->scratch_offset
, 0, true);
6447 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6448 aco_opcode::buffer_load_dwordx4
,
6449 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6450 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6451 emit_split_vector(ctx
, lower
, 2);
6452 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6453 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6454 if (dst
.size() == 8) {
6455 emit_split_vector(ctx
, upper
, 2);
6456 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6457 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6462 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6463 Format::PSEUDO
, dst
.size() / 2, 1)};
6464 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6465 vec
->operands
[i
] = Operand(elems
[i
]);
6466 vec
->definitions
[0] = Definition(dst
);
6467 bld
.insert(std::move(vec
));
6468 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6472 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6475 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6476 emit_split_vector(ctx
, dst
, instr
->num_components
);
6479 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6480 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6481 Builder
bld(ctx
->program
, ctx
->block
);
6482 Temp rsrc
= get_scratch_resource(ctx
);
6483 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6484 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6486 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6487 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6491 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6492 int num_bytes
= count
* elem_size_bytes
;
6494 if (num_bytes
> 16) {
6495 assert(elem_size_bytes
== 8);
6496 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6501 // TODO: check alignment of sub-dword stores
6502 // TODO: split 3 bytes. there is no store instruction for that
6505 if (count
!= instr
->num_components
) {
6506 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6507 for (int i
= 0; i
< count
; i
++) {
6508 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6509 vec
->operands
[i
] = Operand(elem
);
6511 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6512 vec
->definitions
[0] = Definition(write_data
);
6513 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6519 switch (num_bytes
) {
6521 op
= aco_opcode::buffer_store_dword
;
6524 op
= aco_opcode::buffer_store_dwordx2
;
6527 op
= aco_opcode::buffer_store_dwordx3
;
6530 op
= aco_opcode::buffer_store_dwordx4
;
6533 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6536 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6540 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6541 uint8_t log2_ps_iter_samples
;
6542 if (ctx
->program
->info
->ps
.force_persample
) {
6543 log2_ps_iter_samples
=
6544 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6546 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6549 /* The bit pattern matches that used by fixed function fragment
6551 static const unsigned ps_iter_masks
[] = {
6552 0xffff, /* not used */
6558 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6560 Builder
bld(ctx
->program
, ctx
->block
);
6562 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6563 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6564 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6565 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6566 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6567 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6570 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6571 Builder
bld(ctx
->program
, ctx
->block
);
6573 unsigned stream
= nir_intrinsic_stream_id(instr
);
6574 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6575 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6576 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6579 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6581 unsigned num_components
=
6582 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6583 assert(num_components
);
6585 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6586 unsigned stream_offset
= 0;
6587 for (unsigned i
= 0; i
< stream
; i
++) {
6588 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6589 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6592 /* Limit on the stride field for <= GFX7. */
6593 assert(stride
< (1 << 14));
6595 Temp gsvs_dwords
[4];
6596 for (unsigned i
= 0; i
< 4; i
++)
6597 gsvs_dwords
[i
] = bld
.tmp(s1
);
6598 bld
.pseudo(aco_opcode::p_split_vector
,
6599 Definition(gsvs_dwords
[0]),
6600 Definition(gsvs_dwords
[1]),
6601 Definition(gsvs_dwords
[2]),
6602 Definition(gsvs_dwords
[3]),
6605 if (stream_offset
) {
6606 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6608 Temp carry
= bld
.tmp(s1
);
6609 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6610 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6613 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6614 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6616 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6617 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6619 unsigned offset
= 0;
6620 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6621 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6624 for (unsigned j
= 0; j
< 4; j
++) {
6625 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6628 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6629 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6630 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6631 if (const_offset
>= 4096u) {
6632 if (vaddr_offset
.isUndefined())
6633 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6635 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6636 const_offset
%= 4096u;
6639 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6640 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6641 mtbuf
->operands
[1] = vaddr_offset
;
6642 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6643 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6644 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6645 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6646 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6647 mtbuf
->offset
= const_offset
;
6650 mtbuf
->barrier
= barrier_gs_data
;
6651 mtbuf
->can_reorder
= true;
6652 bld
.insert(std::move(mtbuf
));
6655 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6658 /* outputs for the next vertex are undefined and keeping them around can
6659 * create invalid IR with control flow */
6660 ctx
->outputs
.mask
[i
] = 0;
6663 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6666 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6668 Builder
bld(ctx
->program
, ctx
->block
);
6670 if (cluster_size
== 1) {
6672 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6673 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6674 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6675 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6676 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6677 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6678 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6679 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6680 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6681 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6682 //subgroupAnd(val) -> (exec & ~val) == 0
6683 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6684 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6685 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6686 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6687 //subgroupOr(val) -> (val & exec) != 0
6688 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6689 return bool_to_vector_condition(ctx
, tmp
);
6690 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6691 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6692 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6693 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6694 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6695 return bool_to_vector_condition(ctx
, tmp
);
6697 //subgroupClustered{And,Or,Xor}(val, n) ->
6698 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6699 //cluster_offset = ~(n - 1) & lane_id
6700 //cluster_mask = ((1 << n) - 1)
6701 //subgroupClusteredAnd():
6702 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6703 //subgroupClusteredOr():
6704 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6705 //subgroupClusteredXor():
6706 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6707 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6708 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6711 if (op
== nir_op_iand
)
6712 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6714 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6716 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6718 if (ctx
->program
->chip_class
<= GFX7
)
6719 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6720 else if (ctx
->program
->wave_size
== 64)
6721 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6723 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6724 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6725 if (cluster_mask
!= 0xffffffff)
6726 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6728 Definition cmp_def
= Definition();
6729 if (op
== nir_op_iand
) {
6730 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6731 } else if (op
== nir_op_ior
) {
6732 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6733 } else if (op
== nir_op_ixor
) {
6734 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6735 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6736 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6738 cmp_def
.setHint(vcc
);
6739 return cmp_def
.getTemp();
6743 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6745 Builder
bld(ctx
->program
, ctx
->block
);
6747 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6748 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6749 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6751 if (op
== nir_op_iand
)
6752 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6754 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6756 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6757 Temp lo
= lohi
.def(0).getTemp();
6758 Temp hi
= lohi
.def(1).getTemp();
6759 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6761 Definition cmp_def
= Definition();
6762 if (op
== nir_op_iand
)
6763 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6764 else if (op
== nir_op_ior
)
6765 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6766 else if (op
== nir_op_ixor
)
6767 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6768 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6769 cmp_def
.setHint(vcc
);
6770 return cmp_def
.getTemp();
6773 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6775 Builder
bld(ctx
->program
, ctx
->block
);
6777 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6778 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6779 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6780 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6781 if (op
== nir_op_iand
)
6782 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6783 else if (op
== nir_op_ior
)
6784 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6785 else if (op
== nir_op_ixor
)
6786 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6792 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
6794 Builder
bld(ctx
->program
, ctx
->block
);
6795 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6796 if (src
.regClass().type() == RegType::vgpr
) {
6797 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
6798 } else if (src
.regClass() == s1
) {
6799 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
6800 } else if (src
.regClass() == s2
) {
6801 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
6803 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6804 nir_print_instr(&instr
->instr
, stderr
);
6805 fprintf(stderr
, "\n");
6809 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
6811 Builder
bld(ctx
->program
, ctx
->block
);
6812 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6813 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
6814 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
6816 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
6817 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
6818 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
6819 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
6822 if (ctx
->program
->chip_class
>= GFX8
) {
6823 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
6824 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
6825 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
6826 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
6827 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
6828 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
6830 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
6831 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
6832 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
6833 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
6834 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
6835 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
6836 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
6837 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
6838 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
6839 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
6842 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6843 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
6844 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
6845 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
6846 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
6847 Temp wqm1
= bld
.tmp(v1
);
6848 emit_wqm(ctx
, tmp1
, wqm1
, true);
6849 Temp wqm2
= bld
.tmp(v1
);
6850 emit_wqm(ctx
, tmp2
, wqm2
, true);
6851 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
6855 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6857 Builder
bld(ctx
->program
, ctx
->block
);
6858 switch(instr
->intrinsic
) {
6859 case nir_intrinsic_load_barycentric_sample
:
6860 case nir_intrinsic_load_barycentric_pixel
:
6861 case nir_intrinsic_load_barycentric_centroid
: {
6862 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
6863 Temp bary
= Temp(0, s2
);
6865 case INTERP_MODE_SMOOTH
:
6866 case INTERP_MODE_NONE
:
6867 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
6868 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6869 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
6870 bary
= ctx
->persp_centroid
;
6871 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
6872 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
6874 case INTERP_MODE_NOPERSPECTIVE
:
6875 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
6876 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
6877 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
6878 bary
= ctx
->linear_centroid
;
6879 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
6880 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
6885 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6886 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
6887 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
6888 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6889 Operand(p1
), Operand(p2
));
6890 emit_split_vector(ctx
, dst
, 2);
6893 case nir_intrinsic_load_barycentric_model
: {
6894 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
6896 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6897 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
6898 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
6899 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
6900 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6901 Operand(p1
), Operand(p2
), Operand(p3
));
6902 emit_split_vector(ctx
, dst
, 3);
6905 case nir_intrinsic_load_barycentric_at_sample
: {
6906 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
6907 switch (ctx
->options
->key
.fs
.num_samples
) {
6908 case 2: sample_pos_offset
+= 1 << 3; break;
6909 case 4: sample_pos_offset
+= 3 << 3; break;
6910 case 8: sample_pos_offset
+= 7 << 3; break;
6914 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6915 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
6916 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
6917 if (addr
.type() == RegType::sgpr
) {
6920 sample_pos_offset
+= const_addr
->u32
<< 3;
6921 offset
= Operand(sample_pos_offset
);
6922 } else if (ctx
->options
->chip_class
>= GFX9
) {
6923 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
6925 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
6926 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
6929 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
6930 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
6932 } else if (ctx
->options
->chip_class
>= GFX9
) {
6933 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6934 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
6935 } else if (ctx
->options
->chip_class
>= GFX7
) {
6936 /* addr += private_segment_buffer + sample_pos_offset */
6937 Temp tmp0
= bld
.tmp(s1
);
6938 Temp tmp1
= bld
.tmp(s1
);
6939 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
6940 Definition scc_tmp
= bld
.def(s1
, scc
);
6941 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
6942 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
6943 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6944 Temp pck0
= bld
.tmp(v1
);
6945 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
6946 tmp1
= as_vgpr(ctx
, tmp1
);
6947 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
6948 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
6950 /* sample_pos = flat_load_dwordx2 addr */
6951 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
6953 assert(ctx
->options
->chip_class
== GFX6
);
6955 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6956 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6957 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
6959 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6960 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
6962 sample_pos
= bld
.tmp(v2
);
6964 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
6965 load
->definitions
[0] = Definition(sample_pos
);
6966 load
->operands
[0] = Operand(rsrc
);
6967 load
->operands
[1] = Operand(addr
);
6968 load
->operands
[2] = Operand(0u);
6969 load
->offset
= sample_pos_offset
;
6971 load
->addr64
= true;
6974 load
->disable_wqm
= false;
6975 load
->barrier
= barrier_none
;
6976 load
->can_reorder
= true;
6977 ctx
->block
->instructions
.emplace_back(std::move(load
));
6980 /* sample_pos -= 0.5 */
6981 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
6982 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
6983 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
6984 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
6985 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
6987 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
6990 case nir_intrinsic_load_barycentric_at_offset
: {
6991 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6992 RegClass rc
= RegClass(offset
.type(), 1);
6993 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
6994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
6995 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
6998 case nir_intrinsic_load_front_face
: {
6999 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7000 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7003 case nir_intrinsic_load_view_index
: {
7004 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7005 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7006 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7012 case nir_intrinsic_load_layer_id
: {
7013 unsigned idx
= nir_intrinsic_base(instr
);
7014 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7015 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7018 case nir_intrinsic_load_frag_coord
: {
7019 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7022 case nir_intrinsic_load_sample_pos
: {
7023 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7024 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7025 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7026 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7027 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7030 case nir_intrinsic_load_tess_coord
:
7031 visit_load_tess_coord(ctx
, instr
);
7033 case nir_intrinsic_load_interpolated_input
:
7034 visit_load_interpolated_input(ctx
, instr
);
7036 case nir_intrinsic_store_output
:
7037 visit_store_output(ctx
, instr
);
7039 case nir_intrinsic_load_input
:
7040 case nir_intrinsic_load_input_vertex
:
7041 visit_load_input(ctx
, instr
);
7043 case nir_intrinsic_load_output
:
7044 visit_load_output(ctx
, instr
);
7046 case nir_intrinsic_load_per_vertex_input
:
7047 visit_load_per_vertex_input(ctx
, instr
);
7049 case nir_intrinsic_load_per_vertex_output
:
7050 visit_load_per_vertex_output(ctx
, instr
);
7052 case nir_intrinsic_store_per_vertex_output
:
7053 visit_store_per_vertex_output(ctx
, instr
);
7055 case nir_intrinsic_load_ubo
:
7056 visit_load_ubo(ctx
, instr
);
7058 case nir_intrinsic_load_push_constant
:
7059 visit_load_push_constant(ctx
, instr
);
7061 case nir_intrinsic_load_constant
:
7062 visit_load_constant(ctx
, instr
);
7064 case nir_intrinsic_vulkan_resource_index
:
7065 visit_load_resource(ctx
, instr
);
7067 case nir_intrinsic_discard
:
7068 visit_discard(ctx
, instr
);
7070 case nir_intrinsic_discard_if
:
7071 visit_discard_if(ctx
, instr
);
7073 case nir_intrinsic_load_shared
:
7074 visit_load_shared(ctx
, instr
);
7076 case nir_intrinsic_store_shared
:
7077 visit_store_shared(ctx
, instr
);
7079 case nir_intrinsic_shared_atomic_add
:
7080 case nir_intrinsic_shared_atomic_imin
:
7081 case nir_intrinsic_shared_atomic_umin
:
7082 case nir_intrinsic_shared_atomic_imax
:
7083 case nir_intrinsic_shared_atomic_umax
:
7084 case nir_intrinsic_shared_atomic_and
:
7085 case nir_intrinsic_shared_atomic_or
:
7086 case nir_intrinsic_shared_atomic_xor
:
7087 case nir_intrinsic_shared_atomic_exchange
:
7088 case nir_intrinsic_shared_atomic_comp_swap
:
7089 visit_shared_atomic(ctx
, instr
);
7091 case nir_intrinsic_image_deref_load
:
7092 visit_image_load(ctx
, instr
);
7094 case nir_intrinsic_image_deref_store
:
7095 visit_image_store(ctx
, instr
);
7097 case nir_intrinsic_image_deref_atomic_add
:
7098 case nir_intrinsic_image_deref_atomic_umin
:
7099 case nir_intrinsic_image_deref_atomic_imin
:
7100 case nir_intrinsic_image_deref_atomic_umax
:
7101 case nir_intrinsic_image_deref_atomic_imax
:
7102 case nir_intrinsic_image_deref_atomic_and
:
7103 case nir_intrinsic_image_deref_atomic_or
:
7104 case nir_intrinsic_image_deref_atomic_xor
:
7105 case nir_intrinsic_image_deref_atomic_exchange
:
7106 case nir_intrinsic_image_deref_atomic_comp_swap
:
7107 visit_image_atomic(ctx
, instr
);
7109 case nir_intrinsic_image_deref_size
:
7110 visit_image_size(ctx
, instr
);
7112 case nir_intrinsic_load_ssbo
:
7113 visit_load_ssbo(ctx
, instr
);
7115 case nir_intrinsic_store_ssbo
:
7116 visit_store_ssbo(ctx
, instr
);
7118 case nir_intrinsic_load_global
:
7119 visit_load_global(ctx
, instr
);
7121 case nir_intrinsic_store_global
:
7122 visit_store_global(ctx
, instr
);
7124 case nir_intrinsic_global_atomic_add
:
7125 case nir_intrinsic_global_atomic_imin
:
7126 case nir_intrinsic_global_atomic_umin
:
7127 case nir_intrinsic_global_atomic_imax
:
7128 case nir_intrinsic_global_atomic_umax
:
7129 case nir_intrinsic_global_atomic_and
:
7130 case nir_intrinsic_global_atomic_or
:
7131 case nir_intrinsic_global_atomic_xor
:
7132 case nir_intrinsic_global_atomic_exchange
:
7133 case nir_intrinsic_global_atomic_comp_swap
:
7134 visit_global_atomic(ctx
, instr
);
7136 case nir_intrinsic_ssbo_atomic_add
:
7137 case nir_intrinsic_ssbo_atomic_imin
:
7138 case nir_intrinsic_ssbo_atomic_umin
:
7139 case nir_intrinsic_ssbo_atomic_imax
:
7140 case nir_intrinsic_ssbo_atomic_umax
:
7141 case nir_intrinsic_ssbo_atomic_and
:
7142 case nir_intrinsic_ssbo_atomic_or
:
7143 case nir_intrinsic_ssbo_atomic_xor
:
7144 case nir_intrinsic_ssbo_atomic_exchange
:
7145 case nir_intrinsic_ssbo_atomic_comp_swap
:
7146 visit_atomic_ssbo(ctx
, instr
);
7148 case nir_intrinsic_load_scratch
:
7149 visit_load_scratch(ctx
, instr
);
7151 case nir_intrinsic_store_scratch
:
7152 visit_store_scratch(ctx
, instr
);
7154 case nir_intrinsic_get_buffer_size
:
7155 visit_get_buffer_size(ctx
, instr
);
7157 case nir_intrinsic_control_barrier
: {
7158 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7159 /* GFX6 only (thanks to a hw bug workaround):
7160 * The real barrier instruction isn’t needed, because an entire patch
7161 * always fits into a single wave.
7166 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7167 bld
.sopp(aco_opcode::s_barrier
);
7171 case nir_intrinsic_memory_barrier_tcs_patch
:
7172 case nir_intrinsic_group_memory_barrier
:
7173 case nir_intrinsic_memory_barrier
:
7174 case nir_intrinsic_memory_barrier_buffer
:
7175 case nir_intrinsic_memory_barrier_image
:
7176 case nir_intrinsic_memory_barrier_shared
:
7177 emit_memory_barrier(ctx
, instr
);
7179 case nir_intrinsic_load_num_work_groups
: {
7180 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7181 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7182 emit_split_vector(ctx
, dst
, 3);
7185 case nir_intrinsic_load_local_invocation_id
: {
7186 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7187 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7188 emit_split_vector(ctx
, dst
, 3);
7191 case nir_intrinsic_load_work_group_id
: {
7192 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7193 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7194 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7195 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7196 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7197 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7198 emit_split_vector(ctx
, dst
, 3);
7201 case nir_intrinsic_load_local_invocation_index
: {
7202 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7204 /* The tg_size bits [6:11] contain the subgroup id,
7205 * we need this multiplied by the wave size, and then OR the thread id to it.
7207 if (ctx
->program
->wave_size
== 64) {
7208 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7209 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7210 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7211 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7213 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7214 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7215 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7216 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7220 case nir_intrinsic_load_subgroup_id
: {
7221 if (ctx
->stage
== compute_cs
) {
7222 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7223 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7225 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7229 case nir_intrinsic_load_subgroup_invocation
: {
7230 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7233 case nir_intrinsic_load_num_subgroups
: {
7234 if (ctx
->stage
== compute_cs
)
7235 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7236 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7238 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7241 case nir_intrinsic_ballot
: {
7242 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7243 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7244 Definition tmp
= bld
.def(dst
.regClass());
7245 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7246 if (instr
->src
[0].ssa
->bit_size
== 1) {
7247 assert(src
.regClass() == bld
.lm
);
7248 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7249 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7250 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7251 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7252 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7254 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7255 nir_print_instr(&instr
->instr
, stderr
);
7256 fprintf(stderr
, "\n");
7258 if (dst
.size() != bld
.lm
.size()) {
7259 /* Wave32 with ballot size set to 64 */
7260 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7262 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7265 case nir_intrinsic_shuffle
:
7266 case nir_intrinsic_read_invocation
: {
7267 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7268 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7269 emit_uniform_subgroup(ctx
, instr
, src
);
7271 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7272 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7273 tid
= bld
.as_uniform(tid
);
7274 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7275 if (src
.regClass() == v1
) {
7276 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7277 } else if (src
.regClass() == v2
) {
7278 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7279 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7280 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7281 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7282 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7283 emit_split_vector(ctx
, dst
, 2);
7284 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7285 assert(src
.regClass() == bld
.lm
);
7286 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7287 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7288 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7289 assert(src
.regClass() == bld
.lm
);
7291 if (ctx
->program
->chip_class
<= GFX7
)
7292 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7293 else if (ctx
->program
->wave_size
== 64)
7294 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7296 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7297 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7298 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7299 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7302 nir_print_instr(&instr
->instr
, stderr
);
7303 fprintf(stderr
, "\n");
7308 case nir_intrinsic_load_sample_id
: {
7309 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7310 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7313 case nir_intrinsic_load_sample_mask_in
: {
7314 visit_load_sample_mask_in(ctx
, instr
);
7317 case nir_intrinsic_read_first_invocation
: {
7318 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7319 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7320 if (src
.regClass() == v1
) {
7322 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7324 } else if (src
.regClass() == v2
) {
7325 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7326 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7327 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7328 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7329 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7330 emit_split_vector(ctx
, dst
, 2);
7331 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7332 assert(src
.regClass() == bld
.lm
);
7333 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7334 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7335 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7336 } else if (src
.regClass() == s1
) {
7337 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7338 } else if (src
.regClass() == s2
) {
7339 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7341 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7342 nir_print_instr(&instr
->instr
, stderr
);
7343 fprintf(stderr
, "\n");
7347 case nir_intrinsic_vote_all
: {
7348 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7349 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7350 assert(src
.regClass() == bld
.lm
);
7351 assert(dst
.regClass() == bld
.lm
);
7353 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7354 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7355 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7358 case nir_intrinsic_vote_any
: {
7359 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7360 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7361 assert(src
.regClass() == bld
.lm
);
7362 assert(dst
.regClass() == bld
.lm
);
7364 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7365 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7368 case nir_intrinsic_reduce
:
7369 case nir_intrinsic_inclusive_scan
:
7370 case nir_intrinsic_exclusive_scan
: {
7371 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7372 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7373 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7374 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7375 nir_intrinsic_cluster_size(instr
) : 0;
7376 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7378 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7379 emit_uniform_subgroup(ctx
, instr
, src
);
7380 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7381 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7383 else if (op
== nir_op_iadd
)
7385 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7387 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7389 switch (instr
->intrinsic
) {
7390 case nir_intrinsic_reduce
:
7391 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7393 case nir_intrinsic_exclusive_scan
:
7394 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7396 case nir_intrinsic_inclusive_scan
:
7397 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7402 } else if (cluster_size
== 1) {
7403 bld
.copy(Definition(dst
), src
);
7405 src
= as_vgpr(ctx
, src
);
7409 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7424 unreachable("unknown reduction op");
7429 switch (instr
->intrinsic
) {
7430 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7431 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7432 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7434 unreachable("unknown reduce intrinsic");
7437 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7438 reduce
->operands
[0] = Operand(src
);
7439 // filled in by aco_reduce_assign.cpp, used internally as part of the
7441 assert(dst
.size() == 1 || dst
.size() == 2);
7442 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7443 reduce
->operands
[2] = Operand(v1
.as_linear());
7445 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7446 reduce
->definitions
[0] = Definition(tmp_dst
);
7447 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7448 reduce
->definitions
[2] = Definition();
7449 reduce
->definitions
[3] = Definition(scc
, s1
);
7450 reduce
->definitions
[4] = Definition();
7451 reduce
->reduce_op
= reduce_op
;
7452 reduce
->cluster_size
= cluster_size
;
7453 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7455 emit_wqm(ctx
, tmp_dst
, dst
);
7459 case nir_intrinsic_quad_broadcast
: {
7460 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7461 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7462 emit_uniform_subgroup(ctx
, instr
, src
);
7464 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7465 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7466 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7468 if (instr
->dest
.ssa
.bit_size
== 1) {
7469 assert(src
.regClass() == bld
.lm
);
7470 assert(dst
.regClass() == bld
.lm
);
7471 uint32_t half_mask
= 0x11111111u
<< lane
;
7472 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7473 Temp tmp
= bld
.tmp(bld
.lm
);
7474 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7475 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7476 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7477 emit_wqm(ctx
, tmp
, dst
);
7478 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7479 if (ctx
->program
->chip_class
>= GFX8
)
7480 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7482 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7483 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7484 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7485 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7486 if (ctx
->program
->chip_class
>= GFX8
) {
7487 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7488 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7490 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7491 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7493 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7494 emit_split_vector(ctx
, dst
, 2);
7496 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7497 nir_print_instr(&instr
->instr
, stderr
);
7498 fprintf(stderr
, "\n");
7503 case nir_intrinsic_quad_swap_horizontal
:
7504 case nir_intrinsic_quad_swap_vertical
:
7505 case nir_intrinsic_quad_swap_diagonal
:
7506 case nir_intrinsic_quad_swizzle_amd
: {
7507 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7508 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7509 emit_uniform_subgroup(ctx
, instr
, src
);
7512 uint16_t dpp_ctrl
= 0;
7513 switch (instr
->intrinsic
) {
7514 case nir_intrinsic_quad_swap_horizontal
:
7515 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7517 case nir_intrinsic_quad_swap_vertical
:
7518 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7520 case nir_intrinsic_quad_swap_diagonal
:
7521 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7523 case nir_intrinsic_quad_swizzle_amd
:
7524 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7529 if (ctx
->program
->chip_class
< GFX8
)
7530 dpp_ctrl
|= (1 << 15);
7532 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7533 if (instr
->dest
.ssa
.bit_size
== 1) {
7534 assert(src
.regClass() == bld
.lm
);
7535 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7536 if (ctx
->program
->chip_class
>= GFX8
)
7537 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7539 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7540 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7541 emit_wqm(ctx
, tmp
, dst
);
7542 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7544 if (ctx
->program
->chip_class
>= GFX8
)
7545 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7547 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7548 emit_wqm(ctx
, tmp
, dst
);
7549 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7550 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7551 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7552 if (ctx
->program
->chip_class
>= GFX8
) {
7553 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7554 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7556 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7557 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7559 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7560 emit_split_vector(ctx
, dst
, 2);
7562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7563 nir_print_instr(&instr
->instr
, stderr
);
7564 fprintf(stderr
, "\n");
7568 case nir_intrinsic_masked_swizzle_amd
: {
7569 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7570 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7571 emit_uniform_subgroup(ctx
, instr
, src
);
7574 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7575 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7576 if (dst
.regClass() == v1
) {
7578 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7580 } else if (dst
.regClass() == v2
) {
7581 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7582 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7583 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7584 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7586 emit_split_vector(ctx
, dst
, 2);
7588 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7589 nir_print_instr(&instr
->instr
, stderr
);
7590 fprintf(stderr
, "\n");
7594 case nir_intrinsic_write_invocation_amd
: {
7595 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7596 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7597 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7598 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7599 if (dst
.regClass() == v1
) {
7600 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7601 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7602 } else if (dst
.regClass() == v2
) {
7603 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7604 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7605 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7607 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7608 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7609 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7610 emit_split_vector(ctx
, dst
, 2);
7612 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7613 nir_print_instr(&instr
->instr
, stderr
);
7614 fprintf(stderr
, "\n");
7618 case nir_intrinsic_mbcnt_amd
: {
7619 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7620 RegClass rc
= RegClass(src
.type(), 1);
7621 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7622 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7623 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7624 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7625 emit_wqm(ctx
, wqm_tmp
, dst
);
7628 case nir_intrinsic_load_helper_invocation
: {
7629 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7630 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7631 ctx
->block
->kind
|= block_kind_needs_lowering
;
7632 ctx
->program
->needs_exact
= true;
7635 case nir_intrinsic_is_helper_invocation
: {
7636 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7637 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7638 ctx
->block
->kind
|= block_kind_needs_lowering
;
7639 ctx
->program
->needs_exact
= true;
7642 case nir_intrinsic_demote
:
7643 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7645 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7646 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7647 ctx
->block
->kind
|= block_kind_uses_demote
;
7648 ctx
->program
->needs_exact
= true;
7650 case nir_intrinsic_demote_if
: {
7651 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7652 assert(src
.regClass() == bld
.lm
);
7653 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7654 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7656 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7657 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7658 ctx
->block
->kind
|= block_kind_uses_demote
;
7659 ctx
->program
->needs_exact
= true;
7662 case nir_intrinsic_first_invocation
: {
7663 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7664 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7667 case nir_intrinsic_shader_clock
:
7668 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7669 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7671 case nir_intrinsic_load_vertex_id_zero_base
: {
7672 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7673 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7676 case nir_intrinsic_load_first_vertex
: {
7677 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7678 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7681 case nir_intrinsic_load_base_instance
: {
7682 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7683 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7686 case nir_intrinsic_load_instance_id
: {
7687 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7688 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7691 case nir_intrinsic_load_draw_id
: {
7692 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7693 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7696 case nir_intrinsic_load_invocation_id
: {
7697 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7699 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7700 if (ctx
->options
->chip_class
>= GFX10
)
7701 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7703 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7704 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7705 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7706 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7708 unreachable("Unsupported stage for load_invocation_id");
7713 case nir_intrinsic_load_primitive_id
: {
7714 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7716 switch (ctx
->shader
->info
.stage
) {
7717 case MESA_SHADER_GEOMETRY
:
7718 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7720 case MESA_SHADER_TESS_CTRL
:
7721 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7723 case MESA_SHADER_TESS_EVAL
:
7724 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7727 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7732 case nir_intrinsic_load_patch_vertices_in
: {
7733 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7734 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7736 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7737 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7740 case nir_intrinsic_emit_vertex_with_counter
: {
7741 visit_emit_vertex_with_counter(ctx
, instr
);
7744 case nir_intrinsic_end_primitive_with_counter
: {
7745 unsigned stream
= nir_intrinsic_stream_id(instr
);
7746 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7749 case nir_intrinsic_set_vertex_count
: {
7750 /* unused, the HW keeps track of this for us */
7754 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7755 nir_print_instr(&instr
->instr
, stderr
);
7756 fprintf(stderr
, "\n");
7764 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7765 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7766 enum glsl_base_type
*stype
)
7768 nir_deref_instr
*texture_deref_instr
= NULL
;
7769 nir_deref_instr
*sampler_deref_instr
= NULL
;
7772 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7773 switch (instr
->src
[i
].src_type
) {
7774 case nir_tex_src_texture_deref
:
7775 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7777 case nir_tex_src_sampler_deref
:
7778 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7780 case nir_tex_src_plane
:
7781 plane
= nir_src_as_int(instr
->src
[i
].src
);
7788 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
7790 if (!sampler_deref_instr
)
7791 sampler_deref_instr
= texture_deref_instr
;
7794 assert(instr
->op
!= nir_texop_txf_ms
&&
7795 instr
->op
!= nir_texop_samples_identical
);
7796 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
7797 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
7798 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
7799 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
7800 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
7801 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7803 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
7806 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
7808 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
7809 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7810 Builder
bld(ctx
->program
, ctx
->block
);
7812 /* to avoid unnecessary moves, we split and recombine sampler and image */
7813 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
7814 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7815 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7816 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
7817 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
7818 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
7819 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
7820 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
7822 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
7823 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
7824 img
[0], img
[1], img
[2], img
[3],
7825 img
[4], img
[5], img
[6], img
[7]);
7826 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7827 samp
[0], samp
[1], samp
[2], samp
[3]);
7830 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
7831 instr
->op
== nir_texop_samples_identical
))
7832 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7835 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
7836 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
7838 Builder
bld(ctx
->program
, ctx
->block
);
7840 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
7841 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
7842 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
7844 Operand
neg_one(0xbf800000u
);
7845 Operand
one(0x3f800000u
);
7846 Operand
two(0x40000000u
);
7847 Operand
four(0x40800000u
);
7849 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
7850 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
7851 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
7853 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
7854 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
7855 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
7856 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
7859 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
7860 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7861 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
7863 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
7866 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
7867 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
7868 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
7871 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7872 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
7874 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
7875 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
7878 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
7880 Builder
bld(ctx
->program
, ctx
->block
);
7881 Temp ma
, tc
, sc
, id
;
7884 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
7886 // see comment in ac_prepare_cube_coords()
7887 if (ctx
->options
->chip_class
<= GFX8
)
7888 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
7891 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7893 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
7894 vop3a
->operands
[0] = Operand(ma
);
7895 vop3a
->abs
[0] = true;
7896 Temp invma
= bld
.tmp(v1
);
7897 vop3a
->definitions
[0] = Definition(invma
);
7898 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
7900 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7902 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
7904 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7906 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
7908 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7911 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
7912 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
7914 for (unsigned i
= 0; i
< 2; i
++) {
7915 // see comment in ac_prepare_cube_coords()
7917 Temp deriv_sc
, deriv_tc
;
7918 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
7919 &deriv_ma
, &deriv_sc
, &deriv_tc
);
7921 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
7923 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
7924 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
7925 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
7926 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
7927 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
7928 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
7929 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
7932 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
7933 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
7937 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
7944 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
7946 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
7948 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
7949 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
7952 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
7953 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
7954 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
7958 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
7960 Builder
bld(ctx
->program
, ctx
->block
);
7961 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
7962 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
7963 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
7964 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
7965 std::vector
<Temp
> coords
;
7966 std::vector
<Temp
> derivs
;
7967 nir_const_value
*sample_index_cv
= NULL
;
7968 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
7969 enum glsl_base_type stype
;
7970 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
7972 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
7973 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
7974 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
7975 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
7977 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7978 switch (instr
->src
[i
].src_type
) {
7979 case nir_tex_src_coord
: {
7980 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7981 for (unsigned i
= 0; i
< coord
.size(); i
++)
7982 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
7985 case nir_tex_src_bias
:
7986 if (instr
->op
== nir_texop_txb
) {
7987 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7991 case nir_tex_src_lod
: {
7992 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
7994 if (val
&& val
->f32
<= 0.0) {
7997 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8002 case nir_tex_src_comparator
:
8003 if (instr
->is_shadow
) {
8004 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8008 case nir_tex_src_offset
:
8009 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8010 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8013 case nir_tex_src_ddx
:
8014 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8017 case nir_tex_src_ddy
:
8018 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8021 case nir_tex_src_ms_index
:
8022 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8023 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8024 has_sample_index
= true;
8026 case nir_tex_src_texture_offset
:
8027 case nir_tex_src_sampler_offset
:
8033 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8034 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8036 if (instr
->op
== nir_texop_texture_samples
) {
8037 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8039 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8040 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8041 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8042 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8044 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8045 samples
, Operand(1u), bld
.scc(is_msaa
));
8049 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8050 aco_ptr
<Instruction
> tmp_instr
;
8051 Temp acc
, pack
= Temp();
8053 uint32_t pack_const
= 0;
8054 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8055 if (!const_offset
[i
])
8057 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8060 if (offset
.type() == RegType::sgpr
) {
8061 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8062 if (const_offset
[i
])
8065 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8066 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8069 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8072 if (pack
== Temp()) {
8075 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8079 if (pack_const
&& pack
!= Temp())
8080 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8082 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8083 if (const_offset
[i
])
8086 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8087 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8090 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8093 if (pack
== Temp()) {
8096 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8100 if (pack_const
&& pack
!= Temp())
8101 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8103 if (pack_const
&& pack
== Temp())
8104 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8105 else if (pack
== Temp())
8111 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8112 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8114 /* pack derivatives */
8115 if (has_ddx
|| has_ddy
) {
8116 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8117 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8118 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8119 derivs
= {ddy
, zero
, ddy
, zero
};
8121 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8122 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8123 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8124 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8129 if (instr
->coord_components
> 1 &&
8130 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8132 instr
->op
!= nir_texop_txf
)
8133 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8135 if (instr
->coord_components
> 2 &&
8136 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8137 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8138 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8139 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8141 instr
->op
!= nir_texop_txf
&&
8142 instr
->op
!= nir_texop_txf_ms
&&
8143 instr
->op
!= nir_texop_fragment_fetch
&&
8144 instr
->op
!= nir_texop_fragment_mask_fetch
)
8145 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8147 if (ctx
->options
->chip_class
== GFX9
&&
8148 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8149 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8150 assert(coords
.size() > 0 && coords
.size() < 3);
8152 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8153 Operand((uint32_t) 0) :
8154 Operand((uint32_t) 0x3f000000)));
8157 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8159 if (instr
->op
== nir_texop_samples_identical
)
8160 resource
= fmask_ptr
;
8162 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8163 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8164 instr
->op
!= nir_texop_txs
&&
8165 instr
->op
!= nir_texop_fragment_fetch
&&
8166 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8167 assert(has_sample_index
);
8168 Operand
op(sample_index
);
8169 if (sample_index_cv
)
8170 op
= Operand(sample_index_cv
->u32
);
8171 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8174 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8175 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8176 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8177 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8182 /* Build tex instruction */
8183 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8184 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8185 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8187 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8190 /* gather4 selects the component by dmask and always returns vec4 */
8191 if (instr
->op
== nir_texop_tg4
) {
8192 assert(instr
->dest
.ssa
.num_components
== 4);
8193 if (instr
->is_shadow
)
8196 dmask
= 1 << instr
->component
;
8197 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8198 tmp_dst
= bld
.tmp(v4
);
8199 } else if (instr
->op
== nir_texop_samples_identical
) {
8200 tmp_dst
= bld
.tmp(v1
);
8201 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8202 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8205 aco_ptr
<MIMG_instruction
> tex
;
8206 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8208 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8210 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8211 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8214 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8215 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8217 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8218 tex
->operands
[0] = Operand(resource
);
8219 tex
->operands
[1] = Operand(s4
); /* no sampler */
8220 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8221 if (ctx
->options
->chip_class
== GFX9
&&
8222 instr
->op
== nir_texop_txs
&&
8223 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8225 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8226 } else if (instr
->op
== nir_texop_query_levels
) {
8227 tex
->dmask
= 1 << 3;
8232 tex
->definitions
[0] = Definition(tmp_dst
);
8234 tex
->can_reorder
= true;
8235 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8238 /* divide 3rd value by 6 by multiplying with magic number */
8239 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8240 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8241 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8242 assert(instr
->dest
.ssa
.num_components
== 3);
8243 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8244 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8245 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8246 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8251 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8255 Temp tg4_compare_cube_wa64
= Temp();
8257 if (tg4_integer_workarounds
) {
8258 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8259 tex
->operands
[0] = Operand(resource
);
8260 tex
->operands
[1] = Operand(s4
); /* no sampler */
8261 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8265 Temp size
= bld
.tmp(v2
);
8266 tex
->definitions
[0] = Definition(size
);
8267 tex
->can_reorder
= true;
8268 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8269 emit_split_vector(ctx
, size
, size
.size());
8272 for (unsigned i
= 0; i
< 2; i
++) {
8273 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8274 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8275 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8276 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8279 Temp new_coords
[2] = {
8280 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8281 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8284 if (tg4_integer_cube_workaround
) {
8285 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8286 Temp desc
[resource
.size()];
8287 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8288 Format::PSEUDO
, 1, resource
.size())};
8289 split
->operands
[0] = Operand(resource
);
8290 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8291 desc
[i
] = bld
.tmp(s1
);
8292 split
->definitions
[i
] = Definition(desc
[i
]);
8294 ctx
->block
->instructions
.emplace_back(std::move(split
));
8296 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8297 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8298 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8301 if (stype
== GLSL_TYPE_UINT
) {
8302 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8303 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8304 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8305 bld
.scc(compare_cube_wa
));
8307 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8308 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8309 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8310 bld
.scc(compare_cube_wa
));
8312 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8313 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8315 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8317 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8318 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8319 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8321 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8322 Format::PSEUDO
, resource
.size(), 1)};
8323 for (unsigned i
= 0; i
< resource
.size(); i
++)
8324 vec
->operands
[i
] = Operand(desc
[i
]);
8325 resource
= bld
.tmp(resource
.regClass());
8326 vec
->definitions
[0] = Definition(resource
);
8327 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8329 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8330 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8331 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8332 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8334 coords
[0] = new_coords
[0];
8335 coords
[1] = new_coords
[1];
8338 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8339 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8341 assert(coords
.size() == 1);
8342 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8346 op
= aco_opcode::buffer_load_format_x
; break;
8348 op
= aco_opcode::buffer_load_format_xy
; break;
8350 op
= aco_opcode::buffer_load_format_xyz
; break;
8352 op
= aco_opcode::buffer_load_format_xyzw
; break;
8354 unreachable("Tex instruction loads more than 4 components.");
8357 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8358 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8361 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8363 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8364 mubuf
->operands
[0] = Operand(resource
);
8365 mubuf
->operands
[1] = Operand(coords
[0]);
8366 mubuf
->operands
[2] = Operand((uint32_t) 0);
8367 mubuf
->definitions
[0] = Definition(tmp_dst
);
8368 mubuf
->idxen
= true;
8369 mubuf
->can_reorder
= true;
8370 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8372 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8376 /* gather MIMG address components */
8377 std::vector
<Temp
> args
;
8379 args
.emplace_back(offset
);
8381 args
.emplace_back(bias
);
8383 args
.emplace_back(compare
);
8385 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8387 args
.insert(args
.end(), coords
.begin(), coords
.end());
8388 if (has_sample_index
)
8389 args
.emplace_back(sample_index
);
8391 args
.emplace_back(lod
);
8393 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8394 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8395 vec
->definitions
[0] = Definition(arg
);
8396 for (unsigned i
= 0; i
< args
.size(); i
++)
8397 vec
->operands
[i
] = Operand(args
[i
]);
8398 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8401 if (instr
->op
== nir_texop_txf
||
8402 instr
->op
== nir_texop_txf_ms
||
8403 instr
->op
== nir_texop_samples_identical
||
8404 instr
->op
== nir_texop_fragment_fetch
||
8405 instr
->op
== nir_texop_fragment_mask_fetch
) {
8406 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8407 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8408 tex
->operands
[0] = Operand(resource
);
8409 tex
->operands
[1] = Operand(s4
); /* no sampler */
8410 tex
->operands
[2] = Operand(arg
);
8415 tex
->definitions
[0] = Definition(tmp_dst
);
8416 tex
->can_reorder
= true;
8417 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8419 if (instr
->op
== nir_texop_samples_identical
) {
8420 assert(dmask
== 1 && dst
.regClass() == v1
);
8421 assert(dst
.id() != tmp_dst
.id());
8423 Temp tmp
= bld
.tmp(bld
.lm
);
8424 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8425 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8428 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8433 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8434 aco_opcode opcode
= aco_opcode::image_sample
;
8435 if (has_offset
) { /* image_sample_*_o */
8437 opcode
= aco_opcode::image_sample_c_o
;
8439 opcode
= aco_opcode::image_sample_c_d_o
;
8441 opcode
= aco_opcode::image_sample_c_b_o
;
8443 opcode
= aco_opcode::image_sample_c_lz_o
;
8445 opcode
= aco_opcode::image_sample_c_l_o
;
8447 opcode
= aco_opcode::image_sample_o
;
8449 opcode
= aco_opcode::image_sample_d_o
;
8451 opcode
= aco_opcode::image_sample_b_o
;
8453 opcode
= aco_opcode::image_sample_lz_o
;
8455 opcode
= aco_opcode::image_sample_l_o
;
8457 } else { /* no offset */
8459 opcode
= aco_opcode::image_sample_c
;
8461 opcode
= aco_opcode::image_sample_c_d
;
8463 opcode
= aco_opcode::image_sample_c_b
;
8465 opcode
= aco_opcode::image_sample_c_lz
;
8467 opcode
= aco_opcode::image_sample_c_l
;
8469 opcode
= aco_opcode::image_sample
;
8471 opcode
= aco_opcode::image_sample_d
;
8473 opcode
= aco_opcode::image_sample_b
;
8475 opcode
= aco_opcode::image_sample_lz
;
8477 opcode
= aco_opcode::image_sample_l
;
8481 if (instr
->op
== nir_texop_tg4
) {
8483 opcode
= aco_opcode::image_gather4_lz_o
;
8485 opcode
= aco_opcode::image_gather4_c_lz_o
;
8487 opcode
= aco_opcode::image_gather4_lz
;
8489 opcode
= aco_opcode::image_gather4_c_lz
;
8491 } else if (instr
->op
== nir_texop_lod
) {
8492 opcode
= aco_opcode::image_get_lod
;
8495 /* we don't need the bias, sample index, compare value or offset to be
8496 * computed in WQM but if the p_create_vector copies the coordinates, then it
8497 * needs to be in WQM */
8498 if (ctx
->stage
== fragment_fs
&&
8499 !has_derivs
&& !has_lod
&& !level_zero
&&
8500 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8501 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8502 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8504 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8505 tex
->operands
[0] = Operand(resource
);
8506 tex
->operands
[1] = Operand(sampler
);
8507 tex
->operands
[2] = Operand(arg
);
8511 tex
->definitions
[0] = Definition(tmp_dst
);
8512 tex
->can_reorder
= true;
8513 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8515 if (tg4_integer_cube_workaround
) {
8516 assert(tmp_dst
.id() != dst
.id());
8517 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8519 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8521 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8522 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8524 if (stype
== GLSL_TYPE_UINT
)
8525 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8527 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8528 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8530 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8531 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8532 val
[0], val
[1], val
[2], val
[3]);
8534 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8535 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8540 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8542 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8543 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8544 return Operand(tmp
.regClass());
8546 return Operand(tmp
);
8549 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8551 aco_ptr
<Pseudo_instruction
> phi
;
8552 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8553 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8555 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8556 logical
|= ctx
->block
->kind
& block_kind_merge
;
8557 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8559 /* we want a sorted list of sources, since the predecessor list is also sorted */
8560 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8561 nir_foreach_phi_src(src
, instr
)
8562 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8564 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8565 unsigned num_operands
= 0;
8566 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8567 unsigned num_defined
= 0;
8568 unsigned cur_pred_idx
= 0;
8569 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8570 if (cur_pred_idx
< preds
.size()) {
8571 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8572 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8573 unsigned skipped
= 0;
8574 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8576 if (cur_pred_idx
+ skipped
< preds
.size()) {
8577 for (unsigned i
= 0; i
< skipped
; i
++)
8578 operands
[num_operands
++] = Operand(dst
.regClass());
8579 cur_pred_idx
+= skipped
;
8584 /* Handle missing predecessors at the end. This shouldn't happen with loop
8585 * headers and we can't ignore these sources for loop header phis. */
8586 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8589 Operand op
= get_phi_operand(ctx
, src
.second
);
8590 operands
[num_operands
++] = op
;
8591 num_defined
+= !op
.isUndefined();
8593 /* handle block_kind_continue_or_break at loop exit blocks */
8594 while (cur_pred_idx
++ < preds
.size())
8595 operands
[num_operands
++] = Operand(dst
.regClass());
8597 /* If the loop ends with a break, still add a linear continue edge in case
8598 * that break is divergent or continue_or_break is used. We'll either remove
8599 * this operand later in visit_loop() if it's not necessary or replace the
8600 * undef with something correct. */
8601 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8602 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8603 nir_block
*last
= nir_loop_last_block(loop
);
8604 if (last
->successors
[0] != instr
->instr
.block
)
8605 operands
[num_operands
++] = Operand(RegClass());
8608 if (num_defined
== 0) {
8609 Builder
bld(ctx
->program
, ctx
->block
);
8610 if (dst
.regClass() == s1
) {
8611 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8612 } else if (dst
.regClass() == v1
) {
8613 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8615 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8616 for (unsigned i
= 0; i
< dst
.size(); i
++)
8617 vec
->operands
[i
] = Operand(0u);
8618 vec
->definitions
[0] = Definition(dst
);
8619 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8624 /* we can use a linear phi in some cases if one src is undef */
8625 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8626 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8628 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8629 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8630 assert(invert
->kind
& block_kind_invert
);
8632 unsigned then_block
= invert
->linear_preds
[0];
8634 Block
* insert_block
= NULL
;
8635 for (unsigned i
= 0; i
< num_operands
; i
++) {
8636 Operand op
= operands
[i
];
8637 if (op
.isUndefined())
8639 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8640 phi
->operands
[0] = op
;
8643 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8644 phi
->operands
[1] = Operand(dst
.regClass());
8645 phi
->definitions
[0] = Definition(dst
);
8646 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8650 /* try to scalarize vector phis */
8651 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8652 // TODO: scalarize linear phis on divergent ifs
8653 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8654 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8655 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8656 Operand src
= operands
[i
];
8657 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8658 can_scalarize
= false;
8660 if (can_scalarize
) {
8661 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8662 assert(dst
.size() % num_components
== 0);
8663 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8665 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8666 for (unsigned k
= 0; k
< num_components
; k
++) {
8667 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8668 for (unsigned i
= 0; i
< num_operands
; i
++) {
8669 Operand src
= operands
[i
];
8670 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8672 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8673 phi
->definitions
[0] = Definition(phi_dst
);
8674 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8675 new_vec
[k
] = phi_dst
;
8676 vec
->operands
[k
] = Operand(phi_dst
);
8678 vec
->definitions
[0] = Definition(dst
);
8679 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8680 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8685 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8686 for (unsigned i
= 0; i
< num_operands
; i
++)
8687 phi
->operands
[i
] = operands
[i
];
8688 phi
->definitions
[0] = Definition(dst
);
8689 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8693 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8695 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8697 assert(dst
.type() == RegType::sgpr
);
8699 if (dst
.size() == 1) {
8700 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8702 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8703 for (unsigned i
= 0; i
< dst
.size(); i
++)
8704 vec
->operands
[i
] = Operand(0u);
8705 vec
->definitions
[0] = Definition(dst
);
8706 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8710 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8712 Builder
bld(ctx
->program
, ctx
->block
);
8713 Block
*logical_target
;
8714 append_logical_end(ctx
->block
);
8715 unsigned idx
= ctx
->block
->index
;
8717 switch (instr
->type
) {
8718 case nir_jump_break
:
8719 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8720 add_logical_edge(idx
, logical_target
);
8721 ctx
->block
->kind
|= block_kind_break
;
8723 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8724 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8725 /* uniform break - directly jump out of the loop */
8726 ctx
->block
->kind
|= block_kind_uniform
;
8727 ctx
->cf_info
.has_branch
= true;
8728 bld
.branch(aco_opcode::p_branch
);
8729 add_linear_edge(idx
, logical_target
);
8732 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8733 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8735 case nir_jump_continue
:
8736 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8737 add_logical_edge(idx
, logical_target
);
8738 ctx
->block
->kind
|= block_kind_continue
;
8740 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8741 /* for potential uniform breaks after this continue,
8742 we must ensure that they are handled correctly */
8743 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8744 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8745 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8747 /* uniform continue - directly jump to the loop header */
8748 ctx
->block
->kind
|= block_kind_uniform
;
8749 ctx
->cf_info
.has_branch
= true;
8750 bld
.branch(aco_opcode::p_branch
);
8751 add_linear_edge(idx
, logical_target
);
8756 fprintf(stderr
, "Unknown NIR jump instr: ");
8757 nir_print_instr(&instr
->instr
, stderr
);
8758 fprintf(stderr
, "\n");
8762 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
8763 ctx
->cf_info
.exec_potentially_empty_break
= true;
8764 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
8767 /* remove critical edges from linear CFG */
8768 bld
.branch(aco_opcode::p_branch
);
8769 Block
* break_block
= ctx
->program
->create_and_insert_block();
8770 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8771 break_block
->kind
|= block_kind_uniform
;
8772 add_linear_edge(idx
, break_block
);
8773 /* the loop_header pointer might be invalidated by this point */
8774 if (instr
->type
== nir_jump_continue
)
8775 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8776 add_linear_edge(break_block
->index
, logical_target
);
8777 bld
.reset(break_block
);
8778 bld
.branch(aco_opcode::p_branch
);
8780 Block
* continue_block
= ctx
->program
->create_and_insert_block();
8781 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8782 add_linear_edge(idx
, continue_block
);
8783 append_logical_start(continue_block
);
8784 ctx
->block
= continue_block
;
8788 void visit_block(isel_context
*ctx
, nir_block
*block
)
8790 nir_foreach_instr(instr
, block
) {
8791 switch (instr
->type
) {
8792 case nir_instr_type_alu
:
8793 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
8795 case nir_instr_type_load_const
:
8796 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
8798 case nir_instr_type_intrinsic
:
8799 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
8801 case nir_instr_type_tex
:
8802 visit_tex(ctx
, nir_instr_as_tex(instr
));
8804 case nir_instr_type_phi
:
8805 visit_phi(ctx
, nir_instr_as_phi(instr
));
8807 case nir_instr_type_ssa_undef
:
8808 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
8810 case nir_instr_type_deref
:
8812 case nir_instr_type_jump
:
8813 visit_jump(ctx
, nir_instr_as_jump(instr
));
8816 fprintf(stderr
, "Unknown NIR instr type: ");
8817 nir_print_instr(instr
, stderr
);
8818 fprintf(stderr
, "\n");
8823 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8824 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
8829 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
8830 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
8832 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
8833 RegClass rc
= vals
[0].regClass();
8835 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
8837 unsigned next_pred
= 1;
8839 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
8840 Block
& block
= ctx
->program
->blocks
[idx
];
8841 if (block
.loop_nest_depth
!= loop_nest_depth
) {
8842 vals
[idx
- first
] = vals
[idx
- 1 - first
];
8846 if (block
.kind
& block_kind_continue
) {
8847 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
8852 bool all_same
= true;
8853 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
8854 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
8858 val
= vals
[block
.linear_preds
[0] - first
];
8860 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
8861 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
8862 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
8863 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
8864 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
8865 phi
->definitions
[0] = Definition(val
.getTemp());
8866 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
8868 vals
[idx
- first
] = val
;
8871 return vals
[last
- first
];
8874 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
8876 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8877 append_logical_end(ctx
->block
);
8878 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
8879 Builder
bld(ctx
->program
, ctx
->block
);
8880 bld
.branch(aco_opcode::p_branch
);
8881 unsigned loop_preheader_idx
= ctx
->block
->index
;
8883 Block loop_exit
= Block();
8884 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8885 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
8887 Block
* loop_header
= ctx
->program
->create_and_insert_block();
8888 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
8889 loop_header
->kind
|= block_kind_loop_header
;
8890 add_edge(loop_preheader_idx
, loop_header
);
8891 ctx
->block
= loop_header
;
8893 /* emit loop body */
8894 unsigned loop_header_idx
= loop_header
->index
;
8895 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
8896 append_logical_start(ctx
->block
);
8897 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
8899 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8900 if (!ctx
->cf_info
.has_branch
) {
8901 append_logical_end(ctx
->block
);
8902 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
8903 /* Discards can result in code running with an empty exec mask.
8904 * This would result in divergent breaks not ever being taken. As a
8905 * workaround, break the loop when the loop mask is empty instead of
8906 * always continuing. */
8907 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
8908 unsigned block_idx
= ctx
->block
->index
;
8910 /* create helper blocks to avoid critical edges */
8911 Block
*break_block
= ctx
->program
->create_and_insert_block();
8912 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8913 break_block
->kind
= block_kind_uniform
;
8914 bld
.reset(break_block
);
8915 bld
.branch(aco_opcode::p_branch
);
8916 add_linear_edge(block_idx
, break_block
);
8917 add_linear_edge(break_block
->index
, &loop_exit
);
8919 Block
*continue_block
= ctx
->program
->create_and_insert_block();
8920 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8921 continue_block
->kind
= block_kind_uniform
;
8922 bld
.reset(continue_block
);
8923 bld
.branch(aco_opcode::p_branch
);
8924 add_linear_edge(block_idx
, continue_block
);
8925 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8927 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8928 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
8929 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
8931 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
8932 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8933 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8935 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8938 bld
.reset(ctx
->block
);
8939 bld
.branch(aco_opcode::p_branch
);
8942 /* Fixup phis in loop header from unreachable blocks.
8943 * has_branch/has_divergent_branch also indicates if the loop ends with a
8944 * break/continue instruction, but we don't emit those if unreachable=true */
8946 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
8947 bool linear
= ctx
->cf_info
.has_branch
;
8948 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
8949 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
8950 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
8951 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
8952 /* the last operand should be the one that needs to be removed */
8953 instr
->operands
.pop_back();
8954 } else if (!is_phi(instr
)) {
8960 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
8961 * and the previous one shouldn't both happen at once because a break in the
8962 * merge block would get CSE'd */
8963 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
8964 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
8965 Operand vals
[num_vals
];
8966 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
8967 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
8968 if (ctx
->cf_info
.has_branch
)
8969 instr
->operands
.pop_back();
8971 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
8972 } else if (!is_phi(instr
)) {
8978 ctx
->cf_info
.has_branch
= false;
8980 // TODO: if the loop has not a single exit, we must add one °°
8981 /* emit loop successor block */
8982 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
8983 append_logical_start(ctx
->block
);
8986 // TODO: check if it is beneficial to not branch on continues
8987 /* trim linear phis in loop header */
8988 for (auto&& instr
: loop_entry
->instructions
) {
8989 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
8990 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
8991 new_phi
->definitions
[0] = instr
->definitions
[0];
8992 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
8993 new_phi
->operands
[i
] = instr
->operands
[i
];
8994 /* check that the remaining operands are all the same */
8995 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
8996 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
8997 instr
.swap(new_phi
);
8998 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9007 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9011 append_logical_end(ctx
->block
);
9012 ctx
->block
->kind
|= block_kind_branch
;
9014 /* branch to linear then block */
9015 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9016 aco_ptr
<Pseudo_branch_instruction
> branch
;
9017 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9018 branch
->operands
[0] = Operand(cond
);
9019 ctx
->block
->instructions
.push_back(std::move(branch
));
9021 ic
->BB_if_idx
= ctx
->block
->index
;
9022 ic
->BB_invert
= Block();
9023 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9024 /* Invert blocks are intentionally not marked as top level because they
9025 * are not part of the logical cfg. */
9026 ic
->BB_invert
.kind
|= block_kind_invert
;
9027 ic
->BB_endif
= Block();
9028 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9029 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9031 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9032 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9033 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9034 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9035 ctx
->cf_info
.parent_if
.is_divergent
= true;
9037 /* divergent branches use cbranch_execz */
9038 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9039 ctx
->cf_info
.exec_potentially_empty_break
= false;
9040 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9042 /** emit logical then block */
9043 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9044 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9045 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9046 ctx
->block
= BB_then_logical
;
9047 append_logical_start(BB_then_logical
);
9050 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9052 Block
*BB_then_logical
= ctx
->block
;
9053 append_logical_end(BB_then_logical
);
9054 /* branch from logical then block to invert block */
9055 aco_ptr
<Pseudo_branch_instruction
> branch
;
9056 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9057 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9058 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9059 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9060 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9061 BB_then_logical
->kind
|= block_kind_uniform
;
9062 assert(!ctx
->cf_info
.has_branch
);
9063 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9064 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9066 /** emit linear then block */
9067 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9068 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9069 BB_then_linear
->kind
|= block_kind_uniform
;
9070 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9071 /* branch from linear then block to invert block */
9072 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9073 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9074 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9076 /** emit invert merge block */
9077 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9078 ic
->invert_idx
= ctx
->block
->index
;
9080 /* branch to linear else block (skip else) */
9081 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9082 branch
->operands
[0] = Operand(ic
->cond
);
9083 ctx
->block
->instructions
.push_back(std::move(branch
));
9085 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9086 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9087 ic
->exec_potentially_empty_break_depth_old
=
9088 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9089 /* divergent branches use cbranch_execz */
9090 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9091 ctx
->cf_info
.exec_potentially_empty_break
= false;
9092 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9094 /** emit logical else block */
9095 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9096 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9097 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9098 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9099 ctx
->block
= BB_else_logical
;
9100 append_logical_start(BB_else_logical
);
9103 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9105 Block
*BB_else_logical
= ctx
->block
;
9106 append_logical_end(BB_else_logical
);
9108 /* branch from logical else block to endif block */
9109 aco_ptr
<Pseudo_branch_instruction
> branch
;
9110 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9111 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9112 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9113 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9114 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9115 BB_else_logical
->kind
|= block_kind_uniform
;
9117 assert(!ctx
->cf_info
.has_branch
);
9118 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9121 /** emit linear else block */
9122 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9123 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9124 BB_else_linear
->kind
|= block_kind_uniform
;
9125 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9127 /* branch from linear else block to endif block */
9128 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9129 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9130 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9133 /** emit endif merge block */
9134 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9135 append_logical_start(ctx
->block
);
9138 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9139 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9140 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9141 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9142 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9143 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9144 !ctx
->cf_info
.parent_if
.is_divergent
) {
9145 ctx
->cf_info
.exec_potentially_empty_break
= false;
9146 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9148 /* uniform control flow never has an empty exec-mask */
9149 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9150 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9151 ctx
->cf_info
.exec_potentially_empty_break
= false;
9152 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9156 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9158 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9159 Builder
bld(ctx
->program
, ctx
->block
);
9160 aco_ptr
<Pseudo_branch_instruction
> branch
;
9162 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9164 * Uniform conditionals are represented in the following way*) :
9166 * The linear and logical CFG:
9169 * BB_THEN (logical) BB_ELSE (logical)
9173 * *) Exceptions may be due to break and continue statements within loops
9174 * If a break/continue happens within uniform control flow, it branches
9175 * to the loop exit/entry block. Otherwise, it branches to the next
9178 append_logical_end(ctx
->block
);
9179 ctx
->block
->kind
|= block_kind_uniform
;
9182 assert(cond
.regClass() == bld
.lm
);
9183 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9184 cond
= bool_to_scalar_condition(ctx
, cond
);
9186 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9187 branch
->operands
[0] = Operand(cond
);
9188 branch
->operands
[0].setFixed(scc
);
9189 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9191 unsigned BB_if_idx
= ctx
->block
->index
;
9192 Block BB_endif
= Block();
9193 BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9194 BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9196 /** emit then block */
9197 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9198 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9199 add_edge(BB_if_idx
, BB_then
);
9200 append_logical_start(BB_then
);
9201 ctx
->block
= BB_then
;
9202 visit_cf_list(ctx
, &if_stmt
->then_list
);
9203 BB_then
= ctx
->block
;
9204 bool then_branch
= ctx
->cf_info
.has_branch
;
9205 bool then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9208 append_logical_end(BB_then
);
9209 /* branch from then block to endif block */
9210 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9211 BB_then
->instructions
.emplace_back(std::move(branch
));
9212 add_linear_edge(BB_then
->index
, &BB_endif
);
9213 if (!then_branch_divergent
)
9214 add_logical_edge(BB_then
->index
, &BB_endif
);
9215 BB_then
->kind
|= block_kind_uniform
;
9218 ctx
->cf_info
.has_branch
= false;
9219 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9221 /** emit else block */
9222 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9223 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9224 add_edge(BB_if_idx
, BB_else
);
9225 append_logical_start(BB_else
);
9226 ctx
->block
= BB_else
;
9227 visit_cf_list(ctx
, &if_stmt
->else_list
);
9228 BB_else
= ctx
->block
;
9230 if (!ctx
->cf_info
.has_branch
) {
9231 append_logical_end(BB_else
);
9232 /* branch from then block to endif block */
9233 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9234 BB_else
->instructions
.emplace_back(std::move(branch
));
9235 add_linear_edge(BB_else
->index
, &BB_endif
);
9236 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9237 add_logical_edge(BB_else
->index
, &BB_endif
);
9238 BB_else
->kind
|= block_kind_uniform
;
9241 ctx
->cf_info
.has_branch
&= then_branch
;
9242 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= then_branch_divergent
;
9244 /** emit endif merge block */
9245 if (!ctx
->cf_info
.has_branch
) {
9246 ctx
->block
= ctx
->program
->insert_block(std::move(BB_endif
));
9247 append_logical_start(ctx
->block
);
9249 return !ctx
->cf_info
.has_branch
;
9250 } else { /* non-uniform condition */
9252 * To maintain a logical and linear CFG without critical edges,
9253 * non-uniform conditionals are represented in the following way*) :
9258 * BB_THEN (logical) BB_THEN (linear)
9260 * BB_INVERT (linear)
9262 * BB_ELSE (logical) BB_ELSE (linear)
9269 * BB_THEN (logical) BB_ELSE (logical)
9273 * *) Exceptions may be due to break and continue statements within loops
9278 begin_divergent_if_then(ctx
, &ic
, cond
);
9279 visit_cf_list(ctx
, &if_stmt
->then_list
);
9281 begin_divergent_if_else(ctx
, &ic
);
9282 visit_cf_list(ctx
, &if_stmt
->else_list
);
9284 end_divergent_if(ctx
, &ic
);
9290 static bool visit_cf_list(isel_context
*ctx
,
9291 struct exec_list
*list
)
9293 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9294 switch (node
->type
) {
9295 case nir_cf_node_block
:
9296 visit_block(ctx
, nir_cf_node_as_block(node
));
9298 case nir_cf_node_if
:
9299 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9302 case nir_cf_node_loop
:
9303 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9306 unreachable("unimplemented cf list type");
9312 static void create_null_export(isel_context
*ctx
)
9314 /* Some shader stages always need to have exports.
9315 * So when there is none, we need to add a null export.
9318 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9319 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9320 Builder
bld(ctx
->program
, ctx
->block
);
9321 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9322 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9325 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9327 assert(ctx
->stage
== vertex_vs
||
9328 ctx
->stage
== tess_eval_vs
||
9329 ctx
->stage
== gs_copy_vs
);
9331 int offset
= ctx
->stage
== tess_eval_vs
9332 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9333 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9334 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9335 if (!is_pos
&& !mask
)
9337 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9339 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9340 exp
->enabled_mask
= mask
;
9341 for (unsigned i
= 0; i
< 4; ++i
) {
9342 if (mask
& (1 << i
))
9343 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9345 exp
->operands
[i
] = Operand(v1
);
9347 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9348 * Setting valid_mask=1 prevents it and has no other effect.
9350 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9352 exp
->compressed
= false;
9354 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9356 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9357 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9362 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9364 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9365 exp
->enabled_mask
= 0;
9366 for (unsigned i
= 0; i
< 4; ++i
)
9367 exp
->operands
[i
] = Operand(v1
);
9368 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9369 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9370 exp
->enabled_mask
|= 0x1;
9372 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9373 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9374 exp
->enabled_mask
|= 0x4;
9376 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9377 if (ctx
->options
->chip_class
< GFX9
) {
9378 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9379 exp
->enabled_mask
|= 0x8;
9381 Builder
bld(ctx
->program
, ctx
->block
);
9383 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9384 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9385 if (exp
->operands
[2].isTemp())
9386 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9388 exp
->operands
[2] = Operand(out
);
9389 exp
->enabled_mask
|= 0x4;
9392 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9394 exp
->compressed
= false;
9395 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9396 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9399 static void create_vs_exports(isel_context
*ctx
)
9401 assert(ctx
->stage
== vertex_vs
||
9402 ctx
->stage
== tess_eval_vs
||
9403 ctx
->stage
== gs_copy_vs
);
9405 radv_vs_output_info
*outinfo
= ctx
->stage
== tess_eval_vs
9406 ? &ctx
->program
->info
->tes
.outinfo
9407 : &ctx
->program
->info
->vs
.outinfo
;
9409 if (outinfo
->export_prim_id
) {
9410 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9411 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9414 if (ctx
->options
->key
.has_multiview_view_index
) {
9415 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9416 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9419 /* the order these position exports are created is important */
9421 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9422 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9423 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9424 exported_pos
= true;
9426 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9427 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9428 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9429 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9431 if (ctx
->export_clip_dists
) {
9432 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9433 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9434 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9435 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9438 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9439 if (i
< VARYING_SLOT_VAR0
&& i
!= VARYING_SLOT_LAYER
&&
9440 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9443 export_vs_varying(ctx
, i
, false, NULL
);
9447 create_null_export(ctx
);
9450 static bool export_fs_mrt_z(isel_context
*ctx
)
9452 Builder
bld(ctx
->program
, ctx
->block
);
9453 unsigned enabled_channels
= 0;
9457 for (unsigned i
= 0; i
< 4; ++i
) {
9458 values
[i
] = Operand(v1
);
9461 /* Both stencil and sample mask only need 16-bits. */
9462 if (!ctx
->program
->info
->ps
.writes_z
&&
9463 (ctx
->program
->info
->ps
.writes_stencil
||
9464 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9465 compr
= true; /* COMPR flag */
9467 if (ctx
->program
->info
->ps
.writes_stencil
) {
9468 /* Stencil should be in X[23:16]. */
9469 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9470 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9471 enabled_channels
|= 0x3;
9474 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9475 /* SampleMask should be in Y[15:0]. */
9476 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9477 enabled_channels
|= 0xc;
9480 if (ctx
->program
->info
->ps
.writes_z
) {
9481 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9482 enabled_channels
|= 0x1;
9485 if (ctx
->program
->info
->ps
.writes_stencil
) {
9486 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9487 enabled_channels
|= 0x2;
9490 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9491 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9492 enabled_channels
|= 0x4;
9496 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9497 * writemask component.
9499 if (ctx
->options
->chip_class
== GFX6
&&
9500 ctx
->options
->family
!= CHIP_OLAND
&&
9501 ctx
->options
->family
!= CHIP_HAINAN
) {
9502 enabled_channels
|= 0x1;
9505 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9506 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9511 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9513 Builder
bld(ctx
->program
, ctx
->block
);
9514 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9517 for (unsigned i
= 0; i
< 4; ++i
) {
9518 if (write_mask
& (1 << i
)) {
9519 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9521 values
[i
] = Operand(v1
);
9525 unsigned target
, col_format
;
9526 unsigned enabled_channels
= 0;
9527 aco_opcode compr_op
= (aco_opcode
)0;
9529 slot
-= FRAG_RESULT_DATA0
;
9530 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9531 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9533 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9534 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9538 case V_028714_SPI_SHADER_ZERO
:
9539 enabled_channels
= 0; /* writemask */
9540 target
= V_008DFC_SQ_EXP_NULL
;
9543 case V_028714_SPI_SHADER_32_R
:
9544 enabled_channels
= 1;
9547 case V_028714_SPI_SHADER_32_GR
:
9548 enabled_channels
= 0x3;
9551 case V_028714_SPI_SHADER_32_AR
:
9552 if (ctx
->options
->chip_class
>= GFX10
) {
9553 /* Special case: on GFX10, the outputs are different for 32_AR */
9554 enabled_channels
= 0x3;
9555 values
[1] = values
[3];
9556 values
[3] = Operand(v1
);
9558 enabled_channels
= 0x9;
9562 case V_028714_SPI_SHADER_FP16_ABGR
:
9563 enabled_channels
= 0x5;
9564 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9567 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9568 enabled_channels
= 0x5;
9569 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9572 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9573 enabled_channels
= 0x5;
9574 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9577 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9578 enabled_channels
= 0x5;
9579 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9580 if (is_int8
|| is_int10
) {
9582 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9583 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9585 for (unsigned i
= 0; i
< 4; i
++) {
9586 if ((write_mask
>> i
) & 1) {
9587 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9588 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9596 case V_028714_SPI_SHADER_SINT16_ABGR
:
9597 enabled_channels
= 0x5;
9598 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9599 if (is_int8
|| is_int10
) {
9601 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9602 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9603 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9604 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9606 for (unsigned i
= 0; i
< 4; i
++) {
9607 if ((write_mask
>> i
) & 1) {
9608 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9609 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9611 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9612 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9619 case V_028714_SPI_SHADER_32_ABGR
:
9620 enabled_channels
= 0xF;
9627 if (target
== V_008DFC_SQ_EXP_NULL
)
9630 if ((bool) compr_op
) {
9631 for (int i
= 0; i
< 2; i
++) {
9632 /* check if at least one of the values to be compressed is enabled */
9633 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9635 enabled_channels
|= enabled
<< (i
*2);
9636 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9637 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9638 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9640 values
[i
] = Operand(v1
);
9643 values
[2] = Operand(v1
);
9644 values
[3] = Operand(v1
);
9646 for (int i
= 0; i
< 4; i
++)
9647 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9650 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9651 enabled_channels
, target
, (bool) compr_op
);
9655 static void create_fs_exports(isel_context
*ctx
)
9657 bool exported
= false;
9659 /* Export depth, stencil and sample mask. */
9660 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9661 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9662 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9663 exported
|= export_fs_mrt_z(ctx
);
9665 /* Export all color render targets. */
9666 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9667 if (ctx
->outputs
.mask
[i
])
9668 exported
|= export_fs_mrt_color(ctx
, i
);
9671 create_null_export(ctx
);
9674 static void write_tcs_tess_factors(isel_context
*ctx
)
9676 unsigned outer_comps
;
9677 unsigned inner_comps
;
9679 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9696 Builder
bld(ctx
->program
, ctx
->block
);
9698 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9699 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9700 bld
.sopp(aco_opcode::s_barrier
);
9702 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
9703 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
9705 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
9706 if_context ic_invocation_id_is_zero
;
9707 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
9708 bld
.reset(ctx
->block
);
9710 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
9712 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
9713 unsigned stride
= inner_comps
+ outer_comps
;
9714 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
9718 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
9720 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
9722 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9723 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
9724 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
9726 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9727 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
9729 for (unsigned i
= 0; i
< outer_comps
; ++i
)
9730 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
9731 for (unsigned i
= 0; i
< inner_comps
; ++i
)
9732 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
9735 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
9736 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
9737 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
9738 unsigned tf_const_offset
= 0;
9740 if (ctx
->program
->chip_class
<= GFX8
) {
9741 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
9742 if_context ic_rel_patch_id_is_zero
;
9743 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
9744 bld
.reset(ctx
->block
);
9746 /* Store the dynamic HS control word. */
9747 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
9748 bld
.mubuf(aco_opcode::buffer_store_dword
,
9749 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
9750 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9751 /* disable_wqm */ false, /* glc */ true);
9752 tf_const_offset
+= 4;
9754 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
9755 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
9756 bld
.reset(ctx
->block
);
9759 assert(stride
== 2 || stride
== 4 || stride
== 6);
9760 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
9761 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
9763 /* Store to offchip for TES to read - only if TES reads them */
9764 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
9765 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
9766 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
9768 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
9769 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
9771 if (likely(inner_comps
)) {
9772 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
9773 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
9777 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
9778 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
9781 static void emit_stream_output(isel_context
*ctx
,
9782 Temp
const *so_buffers
,
9783 Temp
const *so_write_offset
,
9784 const struct radv_stream_output
*output
)
9786 unsigned num_comps
= util_bitcount(output
->component_mask
);
9787 unsigned writemask
= (1 << num_comps
) - 1;
9788 unsigned loc
= output
->location
;
9789 unsigned buf
= output
->buffer
;
9791 assert(num_comps
&& num_comps
<= 4);
9792 if (!num_comps
|| num_comps
> 4)
9795 unsigned start
= ffs(output
->component_mask
) - 1;
9798 bool all_undef
= true;
9799 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
9800 for (unsigned i
= 0; i
< num_comps
; i
++) {
9801 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
9802 all_undef
= all_undef
&& !out
[i
].id();
9809 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
9810 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
9811 /* GFX6 doesn't support storing vec3, split it. */
9812 writemask
|= 1u << (start
+ 2);
9816 unsigned offset
= output
->offset
+ start
* 4;
9818 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
9819 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
9820 for (int i
= 0; i
< count
; ++i
)
9821 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
9822 vec
->definitions
[0] = Definition(write_data
);
9823 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9828 opcode
= aco_opcode::buffer_store_dword
;
9831 opcode
= aco_opcode::buffer_store_dwordx2
;
9834 opcode
= aco_opcode::buffer_store_dwordx3
;
9837 opcode
= aco_opcode::buffer_store_dwordx4
;
9840 unreachable("Unsupported dword count.");
9843 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
9844 store
->operands
[0] = Operand(so_buffers
[buf
]);
9845 store
->operands
[1] = Operand(so_write_offset
[buf
]);
9846 store
->operands
[2] = Operand((uint32_t) 0);
9847 store
->operands
[3] = Operand(write_data
);
9848 if (offset
> 4095) {
9849 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9850 Builder
bld(ctx
->program
, ctx
->block
);
9851 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
9853 store
->offset
= offset
;
9855 store
->offen
= true;
9859 store
->can_reorder
= true;
9860 ctx
->block
->instructions
.emplace_back(std::move(store
));
9864 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
9866 Builder
bld(ctx
->program
, ctx
->block
);
9869 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
9870 for (unsigned i
= 0; i
< 4; i
++) {
9871 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
9875 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
9876 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
9879 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
9880 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
9882 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
9884 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
9887 begin_divergent_if_then(ctx
, &ic
, can_emit
);
9889 bld
.reset(ctx
->block
);
9891 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
9893 Temp so_write_offset
[4];
9895 for (unsigned i
= 0; i
< 4; i
++) {
9896 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
9901 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
9902 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
9903 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
9904 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
9906 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
9908 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
9909 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
9910 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
9911 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
9915 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
9916 struct radv_stream_output
*output
=
9917 &ctx
->program
->info
->so
.outputs
[i
];
9918 if (stream
!= output
->stream
)
9921 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
9924 begin_divergent_if_else(ctx
, &ic
);
9925 end_divergent_if(ctx
, &ic
);
9928 } /* end namespace */
9930 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
9932 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
9933 Builder
bld(ctx
->program
, ctx
->block
);
9934 constexpr unsigned hs_idx
= 1u;
9935 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
9936 get_arg(ctx
, ctx
->args
->merged_wave_info
),
9937 Operand((8u << 16) | (hs_idx
* 8u)));
9938 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
9940 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9942 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9943 get_arg(ctx
, ctx
->args
->rel_auto_id
),
9944 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
9945 ls_has_nonzero_hs_threads
);
9946 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9947 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
9948 get_arg(ctx
, ctx
->args
->rel_auto_id
),
9949 ls_has_nonzero_hs_threads
);
9950 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9951 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
9952 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
9953 ls_has_nonzero_hs_threads
);
9955 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
9956 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
9957 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
9960 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
9962 /* Split all arguments except for the first (ring_offsets) and the last
9963 * (exec) so that the dead channels don't stay live throughout the program.
9965 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
9966 if (startpgm
->definitions
[i
].regClass().size() > 1) {
9967 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
9968 startpgm
->definitions
[i
].regClass().size());
9973 void handle_bc_optimize(isel_context
*ctx
)
9975 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9976 Builder
bld(ctx
->program
, ctx
->block
);
9977 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
9978 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
9979 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
9980 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
9981 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
9982 if (uses_center
&& uses_centroid
) {
9983 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
9984 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
9986 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
9988 for (unsigned i
= 0; i
< 2; i
++) {
9989 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
9990 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
9991 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9992 persp_centroid
, persp_center
, sel
);
9994 ctx
->persp_centroid
= bld
.tmp(v2
);
9995 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
9996 Operand(new_coord
[0]), Operand(new_coord
[1]));
9997 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10000 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10002 for (unsigned i
= 0; i
< 2; i
++) {
10003 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10004 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10005 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10006 linear_centroid
, linear_center
, sel
);
10008 ctx
->linear_centroid
= bld
.tmp(v2
);
10009 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10010 Operand(new_coord
[0]), Operand(new_coord
[1]));
10011 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10016 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10018 Program
*program
= ctx
->program
;
10020 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10022 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10023 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10024 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10025 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10026 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10028 program
->next_fp_mode
.must_flush_denorms32
=
10029 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10030 program
->next_fp_mode
.must_flush_denorms16_64
=
10031 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10032 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10034 program
->next_fp_mode
.care_about_round32
=
10035 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10037 program
->next_fp_mode
.care_about_round16_64
=
10038 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10039 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10041 /* default to preserving fp16 and fp64 denorms, since it's free */
10042 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10043 program
->next_fp_mode
.denorm16_64
= 0;
10045 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10047 /* preserving fp32 denorms is expensive, so only do it if asked */
10048 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10049 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10051 program
->next_fp_mode
.denorm32
= 0;
10053 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10054 program
->next_fp_mode
.round32
= fp_round_tz
;
10056 program
->next_fp_mode
.round32
= fp_round_ne
;
10058 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10059 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10061 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10063 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10066 void cleanup_cfg(Program
*program
)
10068 /* create linear_succs/logical_succs */
10069 for (Block
& BB
: program
->blocks
) {
10070 for (unsigned idx
: BB
.linear_preds
)
10071 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10072 for (unsigned idx
: BB
.logical_preds
)
10073 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10077 void select_program(Program
*program
,
10078 unsigned shader_count
,
10079 struct nir_shader
*const *shaders
,
10080 ac_shader_config
* config
,
10081 struct radv_shader_args
*args
)
10083 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10084 if_context ic_merged_wave_info
;
10086 for (unsigned i
= 0; i
< shader_count
; i
++) {
10087 nir_shader
*nir
= shaders
[i
];
10088 init_context(&ctx
, nir
);
10090 setup_fp_mode(&ctx
, nir
);
10093 /* needs to be after init_context() for FS */
10094 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10095 append_logical_start(ctx
.block
);
10097 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10098 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10100 split_arguments(&ctx
, startpgm
);
10103 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10104 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10105 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10106 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10107 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10108 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10109 ctx
.stage
== tess_eval_geometry_gs
));
10111 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : (shader_count
>= 2 && !empty_shader
);
10112 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10113 if (check_merged_wave_info
) {
10114 Builder
bld(ctx
.program
, ctx
.block
);
10116 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10117 Temp count
= i
== 0 ? get_arg(&ctx
, args
->merged_wave_info
)
10118 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10119 get_arg(&ctx
, args
->merged_wave_info
), Operand(i
* 8u));
10121 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10124 if (ctx
.program
->wave_size
== 64) {
10125 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10126 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10127 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10129 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10130 cond
= emit_extract_vector(&ctx
, mask
, 0, bld
.lm
);
10133 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10137 Builder
bld(ctx
.program
, ctx
.block
);
10139 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10140 bld
.sopp(aco_opcode::s_barrier
);
10142 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10143 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10145 } else if (ctx
.stage
== geometry_gs
)
10146 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10148 if (ctx
.stage
== fragment_fs
)
10149 handle_bc_optimize(&ctx
);
10151 visit_cf_list(&ctx
, &func
->body
);
10153 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
== vertex_vs
|| ctx
.stage
== tess_eval_vs
))
10154 emit_streamout(&ctx
, 0);
10156 if (ctx
.stage
== vertex_vs
|| ctx
.stage
== tess_eval_vs
) {
10157 create_vs_exports(&ctx
);
10158 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10159 Builder
bld(ctx
.program
, ctx
.block
);
10160 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10161 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10162 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10163 write_tcs_tess_factors(&ctx
);
10166 if (ctx
.stage
== fragment_fs
)
10167 create_fs_exports(&ctx
);
10169 if (endif_merged_wave_info
) {
10170 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10171 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10174 ralloc_free(ctx
.divergent_vals
);
10176 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10177 /* Outputs of the previous stage are inputs to the next stage */
10178 ctx
.inputs
= ctx
.outputs
;
10179 ctx
.outputs
= shader_io_state();
10183 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10185 append_logical_end(ctx
.block
);
10186 ctx
.block
->kind
|= block_kind_uniform
| block_kind_export_end
;
10187 Builder
bld(ctx
.program
, ctx
.block
);
10188 if (ctx
.program
->wb_smem_l1_on_end
)
10189 bld
.smem(aco_opcode::s_dcache_wb
, false);
10190 bld
.sopp(aco_opcode::s_endpgm
);
10192 cleanup_cfg(program
);
10195 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10196 ac_shader_config
* config
,
10197 struct radv_shader_args
*args
)
10199 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10201 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10202 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10203 program
->next_fp_mode
.must_flush_denorms32
= false;
10204 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10205 program
->next_fp_mode
.care_about_round32
= false;
10206 program
->next_fp_mode
.care_about_round16_64
= false;
10207 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10208 program
->next_fp_mode
.denorm32
= 0;
10209 program
->next_fp_mode
.round32
= fp_round_ne
;
10210 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10211 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10213 add_startpgm(&ctx
);
10214 append_logical_start(ctx
.block
);
10216 Builder
bld(ctx
.program
, ctx
.block
);
10218 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10220 Operand
stream_id(0u);
10221 if (args
->shader_info
->so
.num_outputs
)
10222 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10223 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10225 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10227 std::stack
<Block
> endif_blocks
;
10229 for (unsigned stream
= 0; stream
< 4; stream
++) {
10230 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10233 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10234 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10237 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10239 unsigned BB_if_idx
= ctx
.block
->index
;
10240 Block BB_endif
= Block();
10241 if (!stream_id
.isConstant()) {
10243 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10244 append_logical_end(ctx
.block
);
10245 ctx
.block
->kind
|= block_kind_uniform
;
10246 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10248 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10250 ctx
.block
= ctx
.program
->create_and_insert_block();
10251 add_edge(BB_if_idx
, ctx
.block
);
10252 bld
.reset(ctx
.block
);
10253 append_logical_start(ctx
.block
);
10256 unsigned offset
= 0;
10257 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10258 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10261 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10262 unsigned length
= util_last_bit(output_usage_mask
);
10263 for (unsigned j
= 0; j
< length
; ++j
) {
10264 if (!(output_usage_mask
& (1 << j
)))
10267 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10268 Temp voffset
= vtx_offset
;
10269 if (const_offset
>= 4096u) {
10270 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10271 const_offset
%= 4096u;
10274 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10275 mubuf
->definitions
[0] = bld
.def(v1
);
10276 mubuf
->operands
[0] = Operand(gsvs_ring
);
10277 mubuf
->operands
[1] = Operand(voffset
);
10278 mubuf
->operands
[2] = Operand(0u);
10279 mubuf
->offen
= true;
10280 mubuf
->offset
= const_offset
;
10283 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10284 mubuf
->barrier
= barrier_none
;
10285 mubuf
->can_reorder
= true;
10287 ctx
.outputs
.mask
[i
] |= 1 << j
;
10288 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10290 bld
.insert(std::move(mubuf
));
10296 if (args
->shader_info
->so
.num_outputs
) {
10297 emit_streamout(&ctx
, stream
);
10298 bld
.reset(ctx
.block
);
10302 create_vs_exports(&ctx
);
10303 ctx
.block
->kind
|= block_kind_export_end
;
10306 if (!stream_id
.isConstant()) {
10307 append_logical_end(ctx
.block
);
10309 /* branch from then block to endif block */
10310 bld
.branch(aco_opcode::p_branch
);
10311 add_edge(ctx
.block
->index
, &BB_endif
);
10312 ctx
.block
->kind
|= block_kind_uniform
;
10314 /* emit else block */
10315 ctx
.block
= ctx
.program
->create_and_insert_block();
10316 add_edge(BB_if_idx
, ctx
.block
);
10317 bld
.reset(ctx
.block
);
10318 append_logical_start(ctx
.block
);
10320 endif_blocks
.push(std::move(BB_endif
));
10324 while (!endif_blocks
.empty()) {
10325 Block BB_endif
= std::move(endif_blocks
.top());
10326 endif_blocks
.pop();
10328 Block
*BB_else
= ctx
.block
;
10330 append_logical_end(BB_else
);
10331 /* branch from else block to endif block */
10332 bld
.branch(aco_opcode::p_branch
);
10333 add_edge(BB_else
->index
, &BB_endif
);
10334 BB_else
->kind
|= block_kind_uniform
;
10336 /** emit endif merge block */
10337 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10338 bld
.reset(ctx
.block
);
10339 append_logical_start(ctx
.block
);
10342 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10344 append_logical_end(ctx
.block
);
10345 ctx
.block
->kind
|= block_kind_uniform
;
10346 bld
.sopp(aco_opcode::s_endpgm
);
10348 cleanup_cfg(program
);