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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
565 src1
= as_vgpr(ctx
, src1
);
569 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
570 assert(dst
.size() == 1);
571 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
572 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
574 bld
.vop2(op
, Definition(dst
), src0
, src1
);
578 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
579 bool flush_denorms
= false)
581 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
582 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
583 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
585 /* ensure that the instruction has at most 1 sgpr operand
586 * The optimizer will inline constants for us */
587 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
588 src0
= as_vgpr(ctx
, src0
);
589 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
590 src1
= as_vgpr(ctx
, src1
);
591 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
592 src2
= as_vgpr(ctx
, src2
);
594 Builder
bld(ctx
->program
, ctx
->block
);
595 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
596 assert(dst
.size() == 1);
597 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
598 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
600 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
604 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
606 Builder
bld(ctx
->program
, ctx
->block
);
607 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
610 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
613 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
614 assert(src0
.size() == src1
.size());
616 aco_ptr
<Instruction
> vopc
;
617 if (src1
.type() == RegType::sgpr
) {
618 if (src0
.type() == RegType::vgpr
) {
619 /* to swap the operands, we might also have to change the opcode */
621 case aco_opcode::v_cmp_lt_f16
:
622 op
= aco_opcode::v_cmp_gt_f16
;
624 case aco_opcode::v_cmp_ge_f16
:
625 op
= aco_opcode::v_cmp_le_f16
;
627 case aco_opcode::v_cmp_lt_i16
:
628 op
= aco_opcode::v_cmp_gt_i16
;
630 case aco_opcode::v_cmp_ge_i16
:
631 op
= aco_opcode::v_cmp_le_i16
;
633 case aco_opcode::v_cmp_lt_u16
:
634 op
= aco_opcode::v_cmp_gt_u16
;
636 case aco_opcode::v_cmp_ge_u16
:
637 op
= aco_opcode::v_cmp_le_u16
;
639 case aco_opcode::v_cmp_lt_f32
:
640 op
= aco_opcode::v_cmp_gt_f32
;
642 case aco_opcode::v_cmp_ge_f32
:
643 op
= aco_opcode::v_cmp_le_f32
;
645 case aco_opcode::v_cmp_lt_i32
:
646 op
= aco_opcode::v_cmp_gt_i32
;
648 case aco_opcode::v_cmp_ge_i32
:
649 op
= aco_opcode::v_cmp_le_i32
;
651 case aco_opcode::v_cmp_lt_u32
:
652 op
= aco_opcode::v_cmp_gt_u32
;
654 case aco_opcode::v_cmp_ge_u32
:
655 op
= aco_opcode::v_cmp_le_u32
;
657 case aco_opcode::v_cmp_lt_f64
:
658 op
= aco_opcode::v_cmp_gt_f64
;
660 case aco_opcode::v_cmp_ge_f64
:
661 op
= aco_opcode::v_cmp_le_f64
;
663 case aco_opcode::v_cmp_lt_i64
:
664 op
= aco_opcode::v_cmp_gt_i64
;
666 case aco_opcode::v_cmp_ge_i64
:
667 op
= aco_opcode::v_cmp_le_i64
;
669 case aco_opcode::v_cmp_lt_u64
:
670 op
= aco_opcode::v_cmp_gt_u64
;
672 case aco_opcode::v_cmp_ge_u64
:
673 op
= aco_opcode::v_cmp_le_u64
;
675 default: /* eq and ne are commutative */
682 src1
= as_vgpr(ctx
, src1
);
686 Builder
bld(ctx
->program
, ctx
->block
);
687 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
690 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
692 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
693 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
694 Builder
bld(ctx
->program
, ctx
->block
);
696 assert(dst
.regClass() == bld
.lm
);
697 assert(src0
.type() == RegType::sgpr
);
698 assert(src1
.type() == RegType::sgpr
);
699 assert(src0
.regClass() == src1
.regClass());
701 /* Emit the SALU comparison instruction */
702 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
703 /* Turn the result into a per-lane bool */
704 bool_to_vector_condition(ctx
, cmp
, dst
);
707 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
708 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
710 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
711 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
712 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
713 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
715 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
716 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
717 aco_opcode op
= use_valu
? v_op
: s_op
;
718 assert(op
!= aco_opcode::num_opcodes
);
719 assert(dst
.regClass() == ctx
->program
->lane_mask
);
722 emit_vopc_instruction(ctx
, instr
, op
, dst
);
724 emit_sopc_instruction(ctx
, instr
, op
, dst
);
727 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
729 Builder
bld(ctx
->program
, ctx
->block
);
730 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
731 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
733 assert(dst
.regClass() == bld
.lm
);
734 assert(src0
.regClass() == bld
.lm
);
735 assert(src1
.regClass() == bld
.lm
);
737 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
740 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
742 Builder
bld(ctx
->program
, ctx
->block
);
743 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
744 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
745 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
747 assert(cond
.regClass() == bld
.lm
);
749 if (dst
.type() == RegType::vgpr
) {
750 aco_ptr
<Instruction
> bcsel
;
751 if (dst
.regClass() == v2b
) {
752 then
= as_vgpr(ctx
, then
);
753 els
= as_vgpr(ctx
, els
);
755 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
756 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
757 } else if (dst
.regClass() == v1
) {
758 then
= as_vgpr(ctx
, then
);
759 els
= as_vgpr(ctx
, els
);
761 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
762 } else if (dst
.regClass() == v2
) {
763 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
765 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
766 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
768 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
769 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
771 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
773 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
774 nir_print_instr(&instr
->instr
, stderr
);
775 fprintf(stderr
, "\n");
780 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
781 assert(dst
.regClass() == bld
.lm
);
782 assert(then
.regClass() == bld
.lm
);
783 assert(els
.regClass() == bld
.lm
);
786 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
787 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
788 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
789 assert(dst
.size() == then
.size());
790 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
791 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
793 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
794 nir_print_instr(&instr
->instr
, stderr
);
795 fprintf(stderr
, "\n");
800 /* divergent boolean bcsel
801 * this implements bcsel on bools: dst = s0 ? s1 : s2
802 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
803 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
805 if (cond
.id() != then
.id())
806 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
808 if (cond
.id() == els
.id())
809 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
811 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
812 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
815 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
816 aco_opcode op
, uint32_t undo
)
818 /* multiply by 16777216 to handle denormals */
819 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
820 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
821 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
822 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
823 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
825 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
827 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
830 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
832 if (ctx
->block
->fp_mode
.denorm32
== 0) {
833 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
837 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
840 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
842 if (ctx
->block
->fp_mode
.denorm32
== 0) {
843 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
847 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
850 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
852 if (ctx
->block
->fp_mode
.denorm32
== 0) {
853 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
857 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
860 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
862 if (ctx
->block
->fp_mode
.denorm32
== 0) {
863 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
867 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
870 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
872 if (ctx
->options
->chip_class
>= GFX7
)
873 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
875 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
876 /* TODO: create more efficient code! */
877 if (val
.type() == RegType::sgpr
)
878 val
= as_vgpr(ctx
, val
);
880 /* Split the input value. */
881 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
882 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
884 /* Extract the exponent and compute the unbiased value. */
885 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
887 /* Extract the fractional part. */
888 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
889 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
891 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
892 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
894 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
895 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
896 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
897 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
898 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
900 /* Get the sign bit. */
901 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
903 /* Decide the operation to apply depending on the unbiased exponent. */
904 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
905 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
906 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
907 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
908 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
909 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
911 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
914 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
916 if (ctx
->options
->chip_class
>= GFX7
)
917 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
919 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
920 Temp src0
= as_vgpr(ctx
, val
);
922 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
923 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
925 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
926 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
927 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
929 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
931 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
934 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
935 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
937 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
939 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
940 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
942 return add
->definitions
[0].getTemp();
945 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
947 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
948 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
950 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
953 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
954 return bld
.copy(Definition(dst
), src
);
955 else if (dst
.bytes() < src
.bytes())
956 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
960 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
963 } else if (src
.regClass() == s1
) {
965 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
967 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
969 assert(src_bits
!= 8 || src
.regClass() == v1b
);
970 assert(src_bits
!= 16 || src
.regClass() == v2b
);
971 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
972 sdwa
->operands
[0] = Operand(src
);
973 sdwa
->definitions
[0] = Definition(tmp
);
975 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
977 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
978 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
979 bld
.insert(std::move(sdwa
));
982 if (dst_bits
== 64) {
983 if (is_signed
&& dst
.regClass() == s2
) {
984 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
985 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
986 } else if (is_signed
&& dst
.regClass() == v2
) {
987 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
988 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
990 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
997 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
999 if (!instr
->dest
.dest
.is_ssa
) {
1000 fprintf(stderr
, "nir alu dst not in ssa: ");
1001 nir_print_instr(&instr
->instr
, stderr
);
1002 fprintf(stderr
, "\n");
1005 Builder
bld(ctx
->program
, ctx
->block
);
1006 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1011 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1012 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1013 for (unsigned i
= 0; i
< num
; ++i
)
1014 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1016 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1017 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1018 for (unsigned i
= 0; i
< num
; ++i
)
1019 vec
->operands
[i
] = Operand
{elems
[i
]};
1020 vec
->definitions
[0] = Definition(dst
);
1021 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1022 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1024 // TODO: that is a bit suboptimal..
1025 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1026 for (unsigned i
= 0; i
< num
- 1; ++i
)
1027 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1028 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1029 for (unsigned i
= 0; i
< num
; ++i
) {
1030 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1031 if (bit
% 32 == 0) {
1032 elems
[bit
/ 32] = elems
[i
];
1034 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1035 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1036 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1039 if (dst
.size() == 1)
1040 bld
.copy(Definition(dst
), elems
[0]);
1042 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1047 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1048 aco_ptr
<Instruction
> mov
;
1049 if (dst
.type() == RegType::sgpr
) {
1050 if (src
.type() == RegType::vgpr
)
1051 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1052 else if (src
.regClass() == s1
)
1053 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1054 else if (src
.regClass() == s2
)
1055 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1057 unreachable("wrong src register class for nir_op_imov");
1058 } else if (dst
.regClass() == v1
) {
1059 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1060 } else if (dst
.regClass() == v2
) {
1061 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1063 nir_print_instr(&instr
->instr
, stderr
);
1064 unreachable("Should have been lowered to scalar.");
1069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1070 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1071 assert(src
.regClass() == bld
.lm
);
1072 assert(dst
.regClass() == bld
.lm
);
1073 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1074 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1075 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1076 } else if (dst
.regClass() == v1
) {
1077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1078 } else if (dst
.type() == RegType::sgpr
) {
1079 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1080 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1082 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1083 nir_print_instr(&instr
->instr
, stderr
);
1084 fprintf(stderr
, "\n");
1089 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1090 if (dst
.regClass() == v1
) {
1091 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1092 } else if (dst
.regClass() == s1
) {
1093 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1094 } else if (dst
.size() == 2) {
1095 Temp src0
= bld
.tmp(dst
.type(), 1);
1096 Temp src1
= bld
.tmp(dst
.type(), 1);
1097 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1099 if (dst
.regClass() == s2
) {
1100 Temp carry
= bld
.tmp(s1
);
1101 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1102 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1103 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1105 Temp lower
= bld
.tmp(v1
);
1106 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1107 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1108 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1111 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1112 nir_print_instr(&instr
->instr
, stderr
);
1113 fprintf(stderr
, "\n");
1118 if (dst
.regClass() == s1
) {
1119 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1120 } else if (dst
.regClass() == v1
) {
1121 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1122 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1124 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1125 nir_print_instr(&instr
->instr
, stderr
);
1126 fprintf(stderr
, "\n");
1130 case nir_op_isign
: {
1131 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1132 if (dst
.regClass() == s1
) {
1133 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1134 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1135 } else if (dst
.regClass() == s2
) {
1136 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1138 if (ctx
->program
->chip_class
>= GFX8
)
1139 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1141 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1142 /* SCC gets zero-extended to 64 bit */
1143 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1144 } else if (dst
.regClass() == v1
) {
1145 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1146 } else if (dst
.regClass() == v2
) {
1147 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1148 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1149 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1150 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1151 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1154 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1155 nir_print_instr(&instr
->instr
, stderr
);
1156 fprintf(stderr
, "\n");
1161 if (dst
.regClass() == v1
) {
1162 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1163 } else if (dst
.regClass() == s1
) {
1164 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1166 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1167 nir_print_instr(&instr
->instr
, stderr
);
1168 fprintf(stderr
, "\n");
1173 if (dst
.regClass() == v1
) {
1174 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1175 } else if (dst
.regClass() == s1
) {
1176 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1178 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1179 nir_print_instr(&instr
->instr
, stderr
);
1180 fprintf(stderr
, "\n");
1185 if (dst
.regClass() == v1
) {
1186 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1187 } else if (dst
.regClass() == s1
) {
1188 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1190 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1191 nir_print_instr(&instr
->instr
, stderr
);
1192 fprintf(stderr
, "\n");
1197 if (dst
.regClass() == v1
) {
1198 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1199 } else if (dst
.regClass() == s1
) {
1200 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1202 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1203 nir_print_instr(&instr
->instr
, stderr
);
1204 fprintf(stderr
, "\n");
1209 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1210 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1211 } else if (dst
.regClass() == v1
) {
1212 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1213 } else if (dst
.regClass() == s1
) {
1214 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1215 } else if (dst
.regClass() == s2
) {
1216 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1218 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1219 nir_print_instr(&instr
->instr
, stderr
);
1220 fprintf(stderr
, "\n");
1225 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1226 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1227 } else if (dst
.regClass() == v1
) {
1228 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1229 } else if (dst
.regClass() == s1
) {
1230 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1231 } else if (dst
.regClass() == s2
) {
1232 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1234 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1235 nir_print_instr(&instr
->instr
, stderr
);
1236 fprintf(stderr
, "\n");
1241 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1242 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1243 } else if (dst
.regClass() == v1
) {
1244 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1245 } else if (dst
.regClass() == s1
) {
1246 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1247 } else if (dst
.regClass() == s2
) {
1248 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1250 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1251 nir_print_instr(&instr
->instr
, stderr
);
1252 fprintf(stderr
, "\n");
1257 if (dst
.regClass() == v1
) {
1258 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1259 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1260 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1261 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1262 } else if (dst
.regClass() == v2
) {
1263 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1264 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1265 } else if (dst
.regClass() == s2
) {
1266 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1267 } else if (dst
.regClass() == s1
) {
1268 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1270 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1271 nir_print_instr(&instr
->instr
, stderr
);
1272 fprintf(stderr
, "\n");
1277 if (dst
.regClass() == v1
) {
1278 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1279 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1280 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1281 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1282 } else if (dst
.regClass() == v2
) {
1283 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1284 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1285 } else if (dst
.regClass() == s1
) {
1286 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1287 } else if (dst
.regClass() == s2
) {
1288 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1290 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1291 nir_print_instr(&instr
->instr
, stderr
);
1292 fprintf(stderr
, "\n");
1297 if (dst
.regClass() == v1
) {
1298 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1299 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1300 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1301 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1302 } else if (dst
.regClass() == v2
) {
1303 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1304 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1305 } else if (dst
.regClass() == s1
) {
1306 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1307 } else if (dst
.regClass() == s2
) {
1308 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1310 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1311 nir_print_instr(&instr
->instr
, stderr
);
1312 fprintf(stderr
, "\n");
1316 case nir_op_find_lsb
: {
1317 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1318 if (src
.regClass() == s1
) {
1319 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1320 } else if (src
.regClass() == v1
) {
1321 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1322 } else if (src
.regClass() == s2
) {
1323 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1331 case nir_op_ufind_msb
:
1332 case nir_op_ifind_msb
: {
1333 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1334 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1335 aco_opcode op
= src
.regClass() == s2
?
1336 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1337 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1338 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1340 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1341 Operand(src
.size() * 32u - 1u), msb_rev
);
1342 Temp msb
= sub
.def(0).getTemp();
1343 Temp carry
= sub
.def(1).getTemp();
1345 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1346 } else if (src
.regClass() == v1
) {
1347 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1348 Temp msb_rev
= bld
.tmp(v1
);
1349 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1350 Temp msb
= bld
.tmp(v1
);
1351 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1352 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1354 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1355 nir_print_instr(&instr
->instr
, stderr
);
1356 fprintf(stderr
, "\n");
1360 case nir_op_bitfield_reverse
: {
1361 if (dst
.regClass() == s1
) {
1362 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1363 } else if (dst
.regClass() == v1
) {
1364 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1366 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1367 nir_print_instr(&instr
->instr
, stderr
);
1368 fprintf(stderr
, "\n");
1373 if (dst
.regClass() == s1
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1378 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1379 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1380 if (dst
.regClass() == v1
) {
1381 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1385 assert(src0
.size() == 2 && src1
.size() == 2);
1386 Temp src00
= bld
.tmp(src0
.type(), 1);
1387 Temp src01
= bld
.tmp(dst
.type(), 1);
1388 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1389 Temp src10
= bld
.tmp(src1
.type(), 1);
1390 Temp src11
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1393 if (dst
.regClass() == s2
) {
1394 Temp carry
= bld
.tmp(s1
);
1395 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1396 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1397 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1398 } else if (dst
.regClass() == v2
) {
1399 Temp dst0
= bld
.tmp(v1
);
1400 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1401 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1402 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1404 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1405 nir_print_instr(&instr
->instr
, stderr
);
1406 fprintf(stderr
, "\n");
1410 case nir_op_uadd_sat
: {
1411 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1412 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1413 if (dst
.regClass() == s1
) {
1414 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1415 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1417 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1418 } else if (dst
.regClass() == v1
) {
1419 if (ctx
->options
->chip_class
>= GFX9
) {
1420 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1421 add
->operands
[0] = Operand(src0
);
1422 add
->operands
[1] = Operand(src1
);
1423 add
->definitions
[0] = Definition(dst
);
1425 ctx
->block
->instructions
.emplace_back(std::move(add
));
1427 if (src1
.regClass() != v1
)
1428 std::swap(src0
, src1
);
1429 assert(src1
.regClass() == v1
);
1430 Temp tmp
= bld
.tmp(v1
);
1431 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1432 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1435 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1436 nir_print_instr(&instr
->instr
, stderr
);
1437 fprintf(stderr
, "\n");
1441 case nir_op_uadd_carry
: {
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == s1
) {
1445 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1448 if (dst
.regClass() == v1
) {
1449 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1450 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1454 Temp src00
= bld
.tmp(src0
.type(), 1);
1455 Temp src01
= bld
.tmp(dst
.type(), 1);
1456 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1457 Temp src10
= bld
.tmp(src1
.type(), 1);
1458 Temp src11
= bld
.tmp(dst
.type(), 1);
1459 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1460 if (dst
.regClass() == s2
) {
1461 Temp carry
= bld
.tmp(s1
);
1462 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1463 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1465 } else if (dst
.regClass() == v2
) {
1466 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1467 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1468 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1469 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1471 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1472 nir_print_instr(&instr
->instr
, stderr
);
1473 fprintf(stderr
, "\n");
1478 if (dst
.regClass() == s1
) {
1479 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1483 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1484 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1485 if (dst
.regClass() == v1
) {
1486 bld
.vsub32(Definition(dst
), src0
, src1
);
1490 Temp src00
= bld
.tmp(src0
.type(), 1);
1491 Temp src01
= bld
.tmp(dst
.type(), 1);
1492 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1493 Temp src10
= bld
.tmp(src1
.type(), 1);
1494 Temp src11
= bld
.tmp(dst
.type(), 1);
1495 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1496 if (dst
.regClass() == s2
) {
1497 Temp carry
= bld
.tmp(s1
);
1498 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1499 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1500 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1501 } else if (dst
.regClass() == v2
) {
1502 Temp lower
= bld
.tmp(v1
);
1503 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1504 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1507 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1508 nir_print_instr(&instr
->instr
, stderr
);
1509 fprintf(stderr
, "\n");
1513 case nir_op_usub_borrow
: {
1514 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1515 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1516 if (dst
.regClass() == s1
) {
1517 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1519 } else if (dst
.regClass() == v1
) {
1520 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1521 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1525 Temp src00
= bld
.tmp(src0
.type(), 1);
1526 Temp src01
= bld
.tmp(dst
.type(), 1);
1527 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1528 Temp src10
= bld
.tmp(src1
.type(), 1);
1529 Temp src11
= bld
.tmp(dst
.type(), 1);
1530 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1531 if (dst
.regClass() == s2
) {
1532 Temp borrow
= bld
.tmp(s1
);
1533 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1534 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1535 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1536 } else if (dst
.regClass() == v2
) {
1537 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1538 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1539 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1540 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1542 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1543 nir_print_instr(&instr
->instr
, stderr
);
1544 fprintf(stderr
, "\n");
1549 if (dst
.regClass() == v1
) {
1550 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1551 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1552 } else if (dst
.regClass() == s1
) {
1553 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1555 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1556 nir_print_instr(&instr
->instr
, stderr
);
1557 fprintf(stderr
, "\n");
1561 case nir_op_umul_high
: {
1562 if (dst
.regClass() == v1
) {
1563 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1564 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1565 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1566 } else if (dst
.regClass() == s1
) {
1567 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1568 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1569 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1571 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1572 nir_print_instr(&instr
->instr
, stderr
);
1573 fprintf(stderr
, "\n");
1577 case nir_op_imul_high
: {
1578 if (dst
.regClass() == v1
) {
1579 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1580 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1581 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1582 } else if (dst
.regClass() == s1
) {
1583 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1584 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1585 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1587 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1588 nir_print_instr(&instr
->instr
, stderr
);
1589 fprintf(stderr
, "\n");
1594 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1595 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1596 if (dst
.regClass() == v2b
) {
1597 Temp tmp
= bld
.tmp(v1
);
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1599 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1600 } else if (dst
.regClass() == v1
) {
1601 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1602 } else if (dst
.regClass() == v2
) {
1603 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1606 nir_print_instr(&instr
->instr
, stderr
);
1607 fprintf(stderr
, "\n");
1612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1613 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1614 if (dst
.regClass() == v2b
) {
1615 Temp tmp
= bld
.tmp(v1
);
1616 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1618 } else if (dst
.regClass() == v1
) {
1619 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1620 } else if (dst
.regClass() == v2
) {
1621 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1623 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1624 nir_print_instr(&instr
->instr
, stderr
);
1625 fprintf(stderr
, "\n");
1630 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1631 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1632 if (dst
.regClass() == v2b
) {
1633 Temp tmp
= bld
.tmp(v1
);
1634 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1635 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1637 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1639 } else if (dst
.regClass() == v1
) {
1640 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1641 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1643 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1644 } else if (dst
.regClass() == v2
) {
1645 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1646 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1647 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1650 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1651 nir_print_instr(&instr
->instr
, stderr
);
1652 fprintf(stderr
, "\n");
1657 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1658 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1659 if (dst
.regClass() == v2b
) {
1660 // TODO: check fp_mode.must_flush_denorms16_64
1661 Temp tmp
= bld
.tmp(v1
);
1662 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1663 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1664 } else if (dst
.regClass() == v1
) {
1665 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1666 } else if (dst
.regClass() == v2
) {
1667 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1668 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1669 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1671 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1675 nir_print_instr(&instr
->instr
, stderr
);
1676 fprintf(stderr
, "\n");
1681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1682 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1683 if (dst
.regClass() == v2b
) {
1684 // TODO: check fp_mode.must_flush_denorms16_64
1685 Temp tmp
= bld
.tmp(v1
);
1686 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1687 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1688 } else if (dst
.regClass() == v1
) {
1689 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1690 } else if (dst
.regClass() == v2
) {
1691 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1692 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1693 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1695 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1698 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1699 nir_print_instr(&instr
->instr
, stderr
);
1700 fprintf(stderr
, "\n");
1704 case nir_op_fmax3
: {
1705 if (dst
.regClass() == v2b
) {
1706 Temp tmp
= bld
.tmp(v1
);
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1708 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1709 } else if (dst
.regClass() == v1
) {
1710 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1712 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1713 nir_print_instr(&instr
->instr
, stderr
);
1714 fprintf(stderr
, "\n");
1718 case nir_op_fmin3
: {
1719 if (dst
.regClass() == v2b
) {
1720 Temp tmp
= bld
.tmp(v1
);
1721 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1722 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1723 } else if (dst
.regClass() == v1
) {
1724 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1726 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1727 nir_print_instr(&instr
->instr
, stderr
);
1728 fprintf(stderr
, "\n");
1732 case nir_op_fmed3
: {
1733 if (dst
.regClass() == v2b
) {
1734 Temp tmp
= bld
.tmp(v1
);
1735 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1736 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1737 } else if (dst
.regClass() == v1
) {
1738 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1740 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1741 nir_print_instr(&instr
->instr
, stderr
);
1742 fprintf(stderr
, "\n");
1746 case nir_op_umax3
: {
1747 if (dst
.size() == 1) {
1748 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1751 nir_print_instr(&instr
->instr
, stderr
);
1752 fprintf(stderr
, "\n");
1756 case nir_op_umin3
: {
1757 if (dst
.size() == 1) {
1758 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1760 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1761 nir_print_instr(&instr
->instr
, stderr
);
1762 fprintf(stderr
, "\n");
1766 case nir_op_umed3
: {
1767 if (dst
.size() == 1) {
1768 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1770 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1771 nir_print_instr(&instr
->instr
, stderr
);
1772 fprintf(stderr
, "\n");
1776 case nir_op_imax3
: {
1777 if (dst
.size() == 1) {
1778 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1780 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1781 nir_print_instr(&instr
->instr
, stderr
);
1782 fprintf(stderr
, "\n");
1786 case nir_op_imin3
: {
1787 if (dst
.size() == 1) {
1788 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1791 nir_print_instr(&instr
->instr
, stderr
);
1792 fprintf(stderr
, "\n");
1796 case nir_op_imed3
: {
1797 if (dst
.size() == 1) {
1798 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1801 nir_print_instr(&instr
->instr
, stderr
);
1802 fprintf(stderr
, "\n");
1806 case nir_op_cube_face_coord
: {
1807 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1808 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1809 emit_extract_vector(ctx
, in
, 1, v1
),
1810 emit_extract_vector(ctx
, in
, 2, v1
) };
1811 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1812 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1813 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1814 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1815 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1816 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1817 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1820 case nir_op_cube_face_index
: {
1821 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1822 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1823 emit_extract_vector(ctx
, in
, 1, v1
),
1824 emit_extract_vector(ctx
, in
, 2, v1
) };
1825 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1828 case nir_op_bcsel
: {
1829 emit_bcsel(ctx
, instr
, dst
);
1833 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1834 if (dst
.regClass() == v2b
) {
1835 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1836 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1837 } else if (dst
.regClass() == v1
) {
1838 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1839 } else if (dst
.regClass() == v2
) {
1840 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1843 nir_print_instr(&instr
->instr
, stderr
);
1844 fprintf(stderr
, "\n");
1849 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1850 if (dst
.regClass() == v2b
) {
1851 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1852 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1853 } else if (dst
.regClass() == v1
) {
1854 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1855 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1856 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1857 } else if (dst
.regClass() == v2
) {
1858 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1859 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1860 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1862 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1863 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1865 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1866 nir_print_instr(&instr
->instr
, stderr
);
1867 fprintf(stderr
, "\n");
1872 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1873 if (dst
.regClass() == v2b
) {
1874 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1875 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1876 } else if (dst
.regClass() == v1
) {
1877 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1878 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1879 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1880 } else if (dst
.regClass() == v2
) {
1881 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1882 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1883 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1884 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1885 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1886 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1895 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1896 if (dst
.regClass() == v2b
) {
1897 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1898 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1899 } else if (dst
.regClass() == v1
) {
1900 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1901 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1902 // TODO: confirm that this holds under any circumstances
1903 } else if (dst
.regClass() == v2
) {
1904 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1905 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1909 nir_print_instr(&instr
->instr
, stderr
);
1910 fprintf(stderr
, "\n");
1914 case nir_op_flog2
: {
1915 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1916 if (dst
.regClass() == v2b
) {
1917 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1918 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1919 } else if (dst
.regClass() == v1
) {
1920 emit_log2(ctx
, bld
, Definition(dst
), src
);
1922 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1923 nir_print_instr(&instr
->instr
, stderr
);
1924 fprintf(stderr
, "\n");
1929 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1930 if (dst
.regClass() == v2b
) {
1931 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1933 } else if (dst
.regClass() == v1
) {
1934 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1935 } else if (dst
.regClass() == v2
) {
1936 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1938 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1939 nir_print_instr(&instr
->instr
, stderr
);
1940 fprintf(stderr
, "\n");
1944 case nir_op_fexp2
: {
1945 if (dst
.regClass() == v2b
) {
1946 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1947 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1948 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1949 } else if (dst
.regClass() == v1
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1952 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1953 nir_print_instr(&instr
->instr
, stderr
);
1954 fprintf(stderr
, "\n");
1958 case nir_op_fsqrt
: {
1959 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1960 if (dst
.regClass() == v2b
) {
1961 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1963 } else if (dst
.regClass() == v1
) {
1964 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1965 } else if (dst
.regClass() == v2
) {
1966 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1968 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1969 nir_print_instr(&instr
->instr
, stderr
);
1970 fprintf(stderr
, "\n");
1974 case nir_op_ffract
: {
1975 if (dst
.regClass() == v2b
) {
1976 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1977 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1978 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1979 } else if (dst
.regClass() == v1
) {
1980 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1981 } else if (dst
.regClass() == v2
) {
1982 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1984 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1985 nir_print_instr(&instr
->instr
, stderr
);
1986 fprintf(stderr
, "\n");
1990 case nir_op_ffloor
: {
1991 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1992 if (dst
.regClass() == v2b
) {
1993 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1995 } else if (dst
.regClass() == v1
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1997 } else if (dst
.regClass() == v2
) {
1998 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2000 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2001 nir_print_instr(&instr
->instr
, stderr
);
2002 fprintf(stderr
, "\n");
2006 case nir_op_fceil
: {
2007 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2008 if (dst
.regClass() == v2b
) {
2009 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
2010 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2011 } else if (dst
.regClass() == v1
) {
2012 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2013 } else if (dst
.regClass() == v2
) {
2014 if (ctx
->options
->chip_class
>= GFX7
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2017 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2018 /* trunc = trunc(src0)
2019 * if (src0 > 0.0 && src0 != trunc)
2022 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2023 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2024 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2025 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2026 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2027 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2028 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2031 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2032 nir_print_instr(&instr
->instr
, stderr
);
2033 fprintf(stderr
, "\n");
2037 case nir_op_ftrunc
: {
2038 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2039 if (dst
.regClass() == v2b
) {
2040 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2041 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2042 } else if (dst
.regClass() == v1
) {
2043 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2044 } else if (dst
.regClass() == v2
) {
2045 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2053 case nir_op_fround_even
: {
2054 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2055 if (dst
.regClass() == v2b
) {
2056 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2057 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2058 } else if (dst
.regClass() == v1
) {
2059 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2060 } else if (dst
.regClass() == v2
) {
2061 if (ctx
->options
->chip_class
>= GFX7
) {
2062 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2064 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2065 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2066 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2068 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2069 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2070 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2071 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2072 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2073 tmp
= sub
->definitions
[0].getTemp();
2075 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2076 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2077 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2078 Temp cond
= vop3
->definitions
[0].getTemp();
2080 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2081 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2082 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2083 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2085 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2088 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2089 nir_print_instr(&instr
->instr
, stderr
);
2090 fprintf(stderr
, "\n");
2096 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2097 aco_ptr
<Instruction
> norm
;
2098 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2101 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2102 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2103 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2104 } else if (dst
.regClass() == v1
) {
2105 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2107 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2108 if (ctx
->options
->chip_class
< GFX9
)
2109 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2111 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2112 bld
.vop1(opcode
, Definition(dst
), tmp
);
2114 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2115 nir_print_instr(&instr
->instr
, stderr
);
2116 fprintf(stderr
, "\n");
2120 case nir_op_ldexp
: {
2121 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2122 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2123 if (dst
.regClass() == v2b
) {
2124 Temp tmp
= bld
.tmp(v1
);
2125 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2127 } else if (dst
.regClass() == v1
) {
2128 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2129 } else if (dst
.regClass() == v2
) {
2130 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2133 nir_print_instr(&instr
->instr
, stderr
);
2134 fprintf(stderr
, "\n");
2138 case nir_op_frexp_sig
: {
2139 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2140 if (dst
.regClass() == v2b
) {
2141 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2143 } else if (dst
.regClass() == v1
) {
2144 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2145 } else if (dst
.regClass() == v2
) {
2146 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2154 case nir_op_frexp_exp
: {
2155 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2157 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2158 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2159 convert_int(bld
, tmp
, 8, 32, true, dst
);
2160 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2161 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2162 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2163 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2165 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2166 nir_print_instr(&instr
->instr
, stderr
);
2167 fprintf(stderr
, "\n");
2171 case nir_op_fsign
: {
2172 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2173 if (dst
.regClass() == v2b
) {
2174 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2175 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2176 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2177 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2178 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2179 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2180 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2181 } else if (dst
.regClass() == v1
) {
2182 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2183 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2184 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2185 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2186 } else if (dst
.regClass() == v2
) {
2187 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2188 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2189 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2191 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2192 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2193 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2195 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2198 nir_print_instr(&instr
->instr
, stderr
);
2199 fprintf(stderr
, "\n");
2204 case nir_op_f2f16_rtne
: {
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2207 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2208 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2209 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2212 case nir_op_f2f16_rtz
: {
2213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2214 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2215 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2216 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2217 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2220 case nir_op_f2f32
: {
2221 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2222 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2223 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2224 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2226 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2227 nir_print_instr(&instr
->instr
, stderr
);
2228 fprintf(stderr
, "\n");
2232 case nir_op_f2f64
: {
2233 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2234 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2235 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2236 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2239 case nir_op_i2f16
: {
2240 assert(dst
.regClass() == v2b
);
2241 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2242 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2243 src
= convert_int(bld
, src
, 8, 16, true);
2244 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
), src
);
2245 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2248 case nir_op_i2f32
: {
2249 assert(dst
.size() == 1);
2250 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2251 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2252 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2253 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2256 case nir_op_i2f64
: {
2257 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2258 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2259 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2260 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2261 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2262 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 RegClass rc
= RegClass(src
.type(), 1);
2265 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2266 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2267 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2268 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2269 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2270 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2273 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2274 nir_print_instr(&instr
->instr
, stderr
);
2275 fprintf(stderr
, "\n");
2279 case nir_op_u2f16
: {
2280 assert(dst
.regClass() == v2b
);
2281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2282 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2283 src
= convert_int(bld
, src
, 8, 16, false);
2284 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
), src
);
2285 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2288 case nir_op_u2f32
: {
2289 assert(dst
.size() == 1);
2290 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2291 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2292 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2293 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2295 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2296 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2297 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2301 case nir_op_u2f64
: {
2302 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2303 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2304 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2305 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2306 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2308 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2309 RegClass rc
= RegClass(src
.type(), 1);
2310 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2311 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2312 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2313 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2314 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2315 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2317 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2318 nir_print_instr(&instr
->instr
, stderr
);
2319 fprintf(stderr
, "\n");
2324 case nir_op_f2i16
: {
2325 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2326 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2327 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2328 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2329 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2331 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2333 if (dst
.type() == RegType::vgpr
)
2334 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2336 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2340 case nir_op_f2u16
: {
2341 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2342 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2343 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2344 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2345 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2347 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2349 if (dst
.type() == RegType::vgpr
)
2350 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2352 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2355 case nir_op_f2i32
: {
2356 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2357 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2358 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2359 if (dst
.type() == RegType::vgpr
) {
2360 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2362 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2363 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2365 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2366 if (dst
.type() == RegType::vgpr
)
2367 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2369 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2370 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2372 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2373 if (dst
.type() == RegType::vgpr
)
2374 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2376 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2377 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2380 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2381 nir_print_instr(&instr
->instr
, stderr
);
2382 fprintf(stderr
, "\n");
2386 case nir_op_f2u32
: {
2387 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2388 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2389 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2390 if (dst
.type() == RegType::vgpr
) {
2391 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2393 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2394 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2396 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2397 if (dst
.type() == RegType::vgpr
)
2398 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2400 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2401 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2403 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2404 if (dst
.type() == RegType::vgpr
)
2405 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2407 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2408 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2412 nir_print_instr(&instr
->instr
, stderr
);
2413 fprintf(stderr
, "\n");
2417 case nir_op_f2i64
: {
2418 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2419 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2420 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2422 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2423 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2424 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2425 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2426 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2427 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2428 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2429 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2430 Temp new_exponent
= bld
.tmp(v1
);
2431 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2432 if (ctx
->program
->chip_class
>= GFX8
)
2433 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2435 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2436 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2437 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2438 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2439 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2440 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2441 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2442 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2443 Temp new_lower
= bld
.tmp(v1
);
2444 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2445 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2446 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2448 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2449 if (src
.type() == RegType::vgpr
)
2450 src
= bld
.as_uniform(src
);
2451 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2452 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2453 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2454 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2455 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2456 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2457 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2458 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2459 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2460 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2461 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2462 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2463 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2464 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2465 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2466 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2467 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2468 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2469 Temp borrow
= bld
.tmp(s1
);
2470 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2471 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2474 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2475 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2476 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2477 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2478 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2479 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2480 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2481 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2482 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2483 if (dst
.type() == RegType::sgpr
) {
2484 lower
= bld
.as_uniform(lower
);
2485 upper
= bld
.as_uniform(upper
);
2487 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2491 nir_print_instr(&instr
->instr
, stderr
);
2492 fprintf(stderr
, "\n");
2496 case nir_op_f2u64
: {
2497 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2498 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2499 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2501 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2502 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2503 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2504 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2505 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2506 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2507 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2508 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2509 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2510 Temp new_exponent
= bld
.tmp(v1
);
2511 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2512 if (ctx
->program
->chip_class
>= GFX8
)
2513 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2515 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2516 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2517 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2518 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2519 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2520 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2521 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2522 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2524 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2525 if (src
.type() == RegType::vgpr
)
2526 src
= bld
.as_uniform(src
);
2527 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2528 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2529 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2530 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2531 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2532 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2533 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2534 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2535 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2536 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2537 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2538 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2539 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2541 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2542 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2543 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2544 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2546 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2547 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2548 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2549 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2550 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2551 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2552 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2553 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2554 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2555 if (dst
.type() == RegType::sgpr
) {
2556 lower
= bld
.as_uniform(lower
);
2557 upper
= bld
.as_uniform(upper
);
2559 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2563 nir_print_instr(&instr
->instr
, stderr
);
2564 fprintf(stderr
, "\n");
2568 case nir_op_b2f16
: {
2569 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2570 assert(src
.regClass() == bld
.lm
);
2572 if (dst
.regClass() == s1
) {
2573 src
= bool_to_scalar_condition(ctx
, src
);
2574 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2575 } else if (dst
.regClass() == v2b
) {
2576 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2577 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2578 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2580 unreachable("Wrong destination register class for nir_op_b2f16.");
2584 case nir_op_b2f32
: {
2585 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2586 assert(src
.regClass() == bld
.lm
);
2588 if (dst
.regClass() == s1
) {
2589 src
= bool_to_scalar_condition(ctx
, src
);
2590 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2591 } else if (dst
.regClass() == v1
) {
2592 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2594 unreachable("Wrong destination register class for nir_op_b2f32.");
2598 case nir_op_b2f64
: {
2599 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2600 assert(src
.regClass() == bld
.lm
);
2602 if (dst
.regClass() == s2
) {
2603 src
= bool_to_scalar_condition(ctx
, src
);
2604 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2605 } else if (dst
.regClass() == v2
) {
2606 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2607 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2608 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2610 unreachable("Wrong destination register class for nir_op_b2f64.");
2617 case nir_op_i2i64
: {
2618 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2619 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2625 case nir_op_u2u64
: {
2626 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2627 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2631 case nir_op_b2i32
: {
2632 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2633 assert(src
.regClass() == bld
.lm
);
2635 if (dst
.regClass() == s1
) {
2636 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2637 bool_to_scalar_condition(ctx
, src
, dst
);
2638 } else if (dst
.regClass() == v1
) {
2639 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2641 unreachable("Invalid register class for b2i32");
2647 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2648 assert(dst
.regClass() == bld
.lm
);
2650 if (src
.type() == RegType::vgpr
) {
2651 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2652 assert(dst
.regClass() == bld
.lm
);
2653 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2654 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2656 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2658 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2659 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2661 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2662 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2664 bool_to_vector_condition(ctx
, tmp
, dst
);
2668 case nir_op_pack_64_2x32_split
: {
2669 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2670 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2672 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2675 case nir_op_unpack_64_2x32_split_x
:
2676 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2678 case nir_op_unpack_64_2x32_split_y
:
2679 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2681 case nir_op_unpack_32_2x16_split_x
:
2682 if (dst
.type() == RegType::vgpr
) {
2683 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2685 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2688 case nir_op_unpack_32_2x16_split_y
:
2689 if (dst
.type() == RegType::vgpr
) {
2690 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2692 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2695 case nir_op_pack_32_2x16_split
: {
2696 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2697 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2698 if (dst
.regClass() == v1
) {
2699 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2700 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2701 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2703 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2704 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2705 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2709 case nir_op_pack_half_2x16
: {
2710 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2712 if (dst
.regClass() == v1
) {
2713 Temp src0
= bld
.tmp(v1
);
2714 Temp src1
= bld
.tmp(v1
);
2715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2716 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2717 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2719 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2720 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2721 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2723 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2724 nir_print_instr(&instr
->instr
, stderr
);
2725 fprintf(stderr
, "\n");
2729 case nir_op_unpack_half_2x16_split_x
: {
2730 if (dst
.regClass() == v1
) {
2731 Builder
bld(ctx
->program
, ctx
->block
);
2732 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2734 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2735 nir_print_instr(&instr
->instr
, stderr
);
2736 fprintf(stderr
, "\n");
2740 case nir_op_unpack_half_2x16_split_y
: {
2741 if (dst
.regClass() == v1
) {
2742 Builder
bld(ctx
->program
, ctx
->block
);
2743 /* TODO: use SDWA here */
2744 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2745 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2748 nir_print_instr(&instr
->instr
, stderr
);
2749 fprintf(stderr
, "\n");
2753 case nir_op_fquantize2f16
: {
2754 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2755 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2758 if (ctx
->program
->chip_class
>= GFX8
) {
2759 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2760 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2761 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2763 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2764 * so compare the result and flush to 0 if it's smaller.
2766 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2767 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2768 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2769 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2770 cmp_res
= vop3
->definitions
[0].getTemp();
2773 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2774 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2775 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2777 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2782 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2783 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2785 if (dst
.regClass() == s1
) {
2786 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2787 } else if (dst
.regClass() == v1
) {
2788 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2791 nir_print_instr(&instr
->instr
, stderr
);
2792 fprintf(stderr
, "\n");
2796 case nir_op_bitfield_select
: {
2797 /* (mask & insert) | (~mask & base) */
2798 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2799 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2800 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2802 /* dst = (insert & bitmask) | (base & ~bitmask) */
2803 if (dst
.regClass() == s1
) {
2804 aco_ptr
<Instruction
> sop2
;
2805 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2806 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2808 if (const_insert
&& const_bitmask
) {
2809 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2811 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2812 lhs
= Operand(insert
);
2816 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2817 if (const_base
&& const_bitmask
) {
2818 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2820 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2821 rhs
= Operand(base
);
2824 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2826 } else if (dst
.regClass() == v1
) {
2827 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2828 base
= as_vgpr(ctx
, base
);
2829 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2830 insert
= as_vgpr(ctx
, insert
);
2832 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2835 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2836 nir_print_instr(&instr
->instr
, stderr
);
2837 fprintf(stderr
, "\n");
2843 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2844 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2845 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2847 if (dst
.type() == RegType::sgpr
) {
2849 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2850 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2851 if (const_offset
&& const_bits
) {
2852 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2853 extract
= Operand(const_extract
);
2857 width
= Operand(const_bits
->u32
<< 16);
2859 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2861 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2865 if (dst
.regClass() == s1
) {
2866 if (instr
->op
== nir_op_ubfe
)
2867 opcode
= aco_opcode::s_bfe_u32
;
2869 opcode
= aco_opcode::s_bfe_i32
;
2870 } else if (dst
.regClass() == s2
) {
2871 if (instr
->op
== nir_op_ubfe
)
2872 opcode
= aco_opcode::s_bfe_u64
;
2874 opcode
= aco_opcode::s_bfe_i64
;
2876 unreachable("Unsupported BFE bit size");
2879 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2883 if (dst
.regClass() == v1
) {
2884 if (instr
->op
== nir_op_ubfe
)
2885 opcode
= aco_opcode::v_bfe_u32
;
2887 opcode
= aco_opcode::v_bfe_i32
;
2889 unreachable("Unsupported BFE bit size");
2892 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2896 case nir_op_bit_count
: {
2897 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2898 if (src
.regClass() == s1
) {
2899 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2900 } else if (src
.regClass() == v1
) {
2901 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2902 } else if (src
.regClass() == v2
) {
2903 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2904 emit_extract_vector(ctx
, src
, 1, v1
),
2905 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2906 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2907 } else if (src
.regClass() == s2
) {
2908 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2910 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2911 nir_print_instr(&instr
->instr
, stderr
);
2912 fprintf(stderr
, "\n");
2917 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2921 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2925 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2929 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2941 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2942 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2944 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2945 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2949 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2950 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2952 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2953 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2957 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2961 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2966 case nir_op_fddx_fine
:
2967 case nir_op_fddy_fine
:
2968 case nir_op_fddx_coarse
:
2969 case nir_op_fddy_coarse
: {
2970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2971 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2972 if (instr
->op
== nir_op_fddx_fine
) {
2973 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2974 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2975 } else if (instr
->op
== nir_op_fddy_fine
) {
2976 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2977 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2979 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2980 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2981 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2983 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2987 if (ctx
->program
->chip_class
>= GFX8
) {
2988 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2989 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2991 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2992 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2993 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2995 emit_wqm(ctx
, tmp
, dst
, true);
2999 fprintf(stderr
, "Unknown NIR ALU instr: ");
3000 nir_print_instr(&instr
->instr
, stderr
);
3001 fprintf(stderr
, "\n");
3005 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3007 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3009 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3010 // which get truncated the lsb if double and msb if int
3011 // for now, we only use s_mov_b64 with 64bit inline constants
3012 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3013 assert(dst
.type() == RegType::sgpr
);
3015 Builder
bld(ctx
->program
, ctx
->block
);
3017 if (instr
->def
.bit_size
== 1) {
3018 assert(dst
.regClass() == bld
.lm
);
3019 int val
= instr
->value
[0].b
? -1 : 0;
3020 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3021 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3022 } else if (instr
->def
.bit_size
== 8) {
3023 /* ensure that the value is correctly represented in the low byte of the register */
3024 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3025 } else if (instr
->def
.bit_size
== 16) {
3026 /* ensure that the value is correctly represented in the low half of the register */
3027 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3028 } else if (dst
.size() == 1) {
3029 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3031 assert(dst
.size() != 1);
3032 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3033 if (instr
->def
.bit_size
== 64)
3034 for (unsigned i
= 0; i
< dst
.size(); i
++)
3035 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3037 for (unsigned i
= 0; i
< dst
.size(); i
++)
3038 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3040 vec
->definitions
[0] = Definition(dst
);
3041 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3045 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3047 uint32_t new_mask
= 0;
3048 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3049 if (mask
& (1u << i
))
3050 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3054 Operand
load_lds_size_m0(isel_context
*ctx
)
3056 /* TODO: m0 does not need to be initialized on GFX9+ */
3057 Builder
bld(ctx
->program
, ctx
->block
);
3058 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3061 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3062 Temp address
, unsigned base_offset
, unsigned align
)
3064 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3066 Builder
bld(ctx
->program
, ctx
->block
);
3068 Operand m
= load_lds_size_m0(ctx
);
3070 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3071 unsigned bytes_read
= 0;
3072 unsigned result_size
= 0;
3073 unsigned total_bytes
= num_components
* elem_size_bytes
;
3074 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3075 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3076 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3078 while (bytes_read
< total_bytes
) {
3079 unsigned todo
= total_bytes
- bytes_read
;
3080 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3081 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3083 aco_opcode op
= aco_opcode::last_opcode
;
3085 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3086 op
= aco_opcode::ds_read_b128
;
3088 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3089 op
= aco_opcode::ds_read2_b64
;
3092 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3093 op
= aco_opcode::ds_read_b96
;
3095 } else if (todo
>= 8 && aligned8
) {
3096 op
= aco_opcode::ds_read_b64
;
3098 } else if (todo
>= 8 && usable_read2
) {
3099 op
= aco_opcode::ds_read2_b32
;
3102 } else if (todo
>= 4) {
3103 op
= aco_opcode::ds_read_b32
;
3108 assert(todo
% elem_size_bytes
== 0);
3109 unsigned num_elements
= todo
/ elem_size_bytes
;
3110 unsigned offset
= base_offset
+ bytes_read
;
3111 unsigned max_offset
= read2
? 1019 : 65535;
3113 Temp address_offset
= address
;
3114 if (offset
> max_offset
) {
3115 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3116 offset
= bytes_read
;
3118 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3121 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3124 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3127 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3129 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3131 if (num_components
== 1) {
3132 assert(todo
== total_bytes
);
3133 if (dst
.type() == RegType::sgpr
)
3134 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3138 if (dst
.type() == RegType::sgpr
) {
3139 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3140 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3144 if (num_elements
== 1) {
3145 result
[result_size
++] = res
;
3147 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3148 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3149 split
->operands
[0] = Operand(res
);
3150 for (unsigned i
= 0; i
< num_elements
; i
++)
3151 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3152 ctx
->block
->instructions
.emplace_back(std::move(split
));
3158 assert(result_size
== num_components
&& result_size
> 1);
3159 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3160 for (unsigned i
= 0; i
< result_size
; i
++)
3161 vec
->operands
[i
] = Operand(result
[i
]);
3162 vec
->definitions
[0] = Definition(dst
);
3163 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3164 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3169 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3171 if (start
== 0 && size
== data
.size())
3172 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3174 unsigned size_hint
= 1;
3175 auto it
= ctx
->allocated_vec
.find(data
.id());
3176 if (it
!= ctx
->allocated_vec
.end())
3177 size_hint
= it
->second
[0].size();
3178 if (size
% size_hint
|| start
% size_hint
)
3185 for (unsigned i
= 0; i
< size
; i
++)
3186 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3189 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3191 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3192 for (unsigned i
= 0; i
< size
; i
++)
3193 vec
->operands
[i
] = Operand(elems
[i
]);
3194 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3195 vec
->definitions
[0] = Definition(res
);
3196 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3200 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3202 Builder
bld(ctx
->program
, ctx
->block
);
3203 unsigned bytes_written
= 0;
3204 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3205 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3207 while (bytes_written
< total_size
* 4) {
3208 unsigned todo
= total_size
* 4 - bytes_written
;
3209 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3210 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3212 aco_opcode op
= aco_opcode::last_opcode
;
3213 bool write2
= false;
3215 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3216 op
= aco_opcode::ds_write_b128
;
3218 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3219 op
= aco_opcode::ds_write2_b64
;
3222 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3223 op
= aco_opcode::ds_write_b96
;
3225 } else if (todo
>= 8 && aligned8
) {
3226 op
= aco_opcode::ds_write_b64
;
3228 } else if (todo
>= 8 && usable_write2
) {
3229 op
= aco_opcode::ds_write2_b32
;
3232 } else if (todo
>= 4) {
3233 op
= aco_opcode::ds_write_b32
;
3239 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3240 unsigned max_offset
= write2
? 1020 : 65535;
3241 Temp address_offset
= address
;
3242 if (offset
> max_offset
) {
3243 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3244 offset
= offset1
+ bytes_written
;
3246 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3249 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3250 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3251 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3253 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3254 bld
.ds(op
, address_offset
, val
, m
, offset
);
3257 bytes_written
+= size
* 4;
3261 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3262 Temp address
, unsigned base_offset
, unsigned align
)
3264 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3265 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3267 Operand m
= load_lds_size_m0(ctx
);
3269 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3270 assert(wrmask
<= 0x0f);
3271 int start
[2], count
[2];
3272 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3273 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3274 assert(wrmask
== 0);
3276 /* one combined store is sufficient */
3277 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3278 Builder
bld(ctx
->program
, ctx
->block
);
3280 Temp address_offset
= address
;
3281 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3282 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3286 assert(count
[0] == 1);
3287 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3289 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3290 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3291 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3292 base_offset
= base_offset
/ elem_size_bytes
;
3293 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3294 base_offset
+ start
[0], base_offset
+ start
[1]);
3298 for (unsigned i
= 0; i
< 2; i
++) {
3302 unsigned elem_size_words
= elem_size_bytes
/ 4;
3303 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3304 base_offset
, start
[i
] * elem_size_bytes
, align
);
3309 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3311 unsigned align
= 16;
3313 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3319 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3320 unsigned split_cnt
= 0u, Temp dst
= Temp())
3322 Builder
bld(ctx
->program
, ctx
->block
);
3323 unsigned dword_size
= elem_size_bytes
/ 4;
3326 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3328 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3329 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3330 instr
->definitions
[0] = Definition(dst
);
3332 for (unsigned i
= 0; i
< cnt
; ++i
) {
3334 assert(arr
[i
].size() == dword_size
);
3335 allocated_vec
[i
] = arr
[i
];
3336 instr
->operands
[i
] = Operand(arr
[i
]);
3338 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3339 allocated_vec
[i
] = zero
;
3340 instr
->operands
[i
] = Operand(zero
);
3344 bld
.insert(std::move(instr
));
3347 emit_split_vector(ctx
, dst
, split_cnt
);
3349 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3354 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3356 if (const_offset
>= 4096) {
3357 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3358 const_offset
%= 4096u;
3361 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3362 else if (unlikely(voffset
.regClass() == s1
))
3363 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3364 else if (likely(voffset
.regClass() == v1
))
3365 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3367 unreachable("Unsupported register class of voffset");
3370 return const_offset
;
3373 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3374 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3377 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3378 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3380 Builder
bld(ctx
->program
, ctx
->block
);
3381 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3382 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3384 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3385 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3386 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3387 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3388 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3390 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3393 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3394 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3395 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3397 Builder
bld(ctx
->program
, ctx
->block
);
3398 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3401 if (elem_size_bytes
== 8) {
3402 elem_size_bytes
= 4;
3403 write_mask
= widen_mask(write_mask
, 2);
3406 while (write_mask
) {
3409 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3414 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3415 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3417 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3418 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3421 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3422 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3432 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3433 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3435 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3436 assert(size_dwords
>= 1 && size_dwords
<= 4);
3438 Builder
bld(ctx
->program
, ctx
->block
);
3439 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3440 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3441 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3443 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3444 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3445 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3446 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3447 /* disable_wqm */ false, /* glc */ true,
3448 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3450 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3455 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3456 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3457 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3459 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3460 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3461 assert(!!stride
!= allow_combining
);
3463 Builder
bld(ctx
->program
, ctx
->block
);
3464 unsigned split_cnt
= num_components
;
3466 if (elem_size_bytes
== 8) {
3467 elem_size_bytes
= 4;
3468 num_components
*= 2;
3472 stride
= elem_size_bytes
;
3474 unsigned load_size
= 1;
3475 if (allow_combining
) {
3476 if ((num_components
% 4) == 0)
3478 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3480 else if ((num_components
% 2) == 0)
3484 unsigned num_loads
= num_components
/ load_size
;
3485 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3487 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3488 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3489 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3492 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3495 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3497 Builder
bld(ctx
->program
, ctx
->block
);
3498 Temp offset
= base_offset
.first
;
3499 unsigned const_offset
= base_offset
.second
;
3501 if (!nir_src_is_const(*off_src
)) {
3502 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3505 /* Calculate indirect offset with stride */
3506 if (likely(indirect_offset_arg
.regClass() == v1
))
3507 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3508 else if (indirect_offset_arg
.regClass() == s1
)
3509 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3511 unreachable("Unsupported register class of indirect offset");
3513 /* Add to the supplied base offset */
3514 if (offset
.id() == 0)
3515 offset
= with_stride
;
3516 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3517 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3518 else if (offset
.size() == 1 && with_stride
.size() == 1)
3519 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3521 unreachable("Unsupported register class of indirect offset");
3523 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3524 const_offset
+= const_offset_arg
* stride
;
3527 return std::make_pair(offset
, const_offset
);
3530 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3532 Builder
bld(ctx
->program
, ctx
->block
);
3535 if (off1
.first
.id() && off2
.first
.id()) {
3536 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3537 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3538 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3539 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3541 unreachable("Unsupported register class of indirect offset");
3543 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3546 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3549 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3551 Builder
bld(ctx
->program
, ctx
->block
);
3552 unsigned const_offset
= offs
.second
* multiplier
;
3554 if (!offs
.first
.id())
3555 return std::make_pair(offs
.first
, const_offset
);
3557 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3558 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3559 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
3561 return std::make_pair(offset
, const_offset
);
3564 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3566 Builder
bld(ctx
->program
, ctx
->block
);
3568 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3569 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3570 /* component is in bytes */
3571 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3573 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3574 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3575 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3578 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3580 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3583 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3585 Builder
bld(ctx
->program
, ctx
->block
);
3587 switch (ctx
->shader
->info
.stage
) {
3588 case MESA_SHADER_TESS_CTRL
:
3589 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3590 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3591 case MESA_SHADER_TESS_EVAL
:
3592 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3594 unreachable("Unsupported stage in get_tess_rel_patch_id");
3598 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3600 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3601 Builder
bld(ctx
->program
, ctx
->block
);
3603 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3604 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3606 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3608 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3609 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3611 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3612 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3613 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3615 return offset_mul(ctx
, offs
, 4u);
3618 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3620 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3621 Builder
bld(ctx
->program
, ctx
->block
);
3623 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3624 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3625 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3626 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3627 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3628 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3630 std::pair
<Temp
, unsigned> offs
= instr
3631 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3632 : std::make_pair(Temp(), 0u);
3634 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3635 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3640 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3641 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3643 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3644 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3646 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3647 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3653 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3655 Builder
bld(ctx
->program
, ctx
->block
);
3657 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3658 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3660 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3662 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3663 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3664 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3666 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3667 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3672 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3674 Builder
bld(ctx
->program
, ctx
->block
);
3676 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3677 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3678 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3680 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3681 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3682 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3683 unsigned attr_stride
= ctx
->tcs_num_patches
;
3685 std::pair
<Temp
, unsigned> offs
= instr
3686 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3687 : std::make_pair(Temp(), 0u);
3689 if (const_base_offset
)
3690 offs
.second
+= const_base_offset
* attr_stride
;
3692 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3693 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
3694 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3699 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3704 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3705 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3707 if (!nir_src_is_const(*off_src
)) {
3713 off
+= nir_src_as_uint(*off_src
) * 16u;
3716 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3717 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3724 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3726 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3727 unsigned component
= nir_intrinsic_component(instr
);
3728 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3730 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3731 if (off_instr
->type
!= nir_instr_type_load_const
)
3734 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3735 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3737 if (instr
->src
[0].ssa
->bit_size
== 64)
3738 write_mask
= widen_mask(write_mask
, 2);
3740 for (unsigned i
= 0; i
< 8; ++i
) {
3741 if (write_mask
& (1 << i
)) {
3742 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3743 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3751 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3753 /* Only TCS per-vertex inputs are supported by this function.
3754 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3756 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3759 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3760 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3761 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3762 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3763 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3764 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3769 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3770 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3771 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
3776 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3778 Builder
bld(ctx
->program
, ctx
->block
);
3780 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3781 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3782 bool indirect_write
;
3783 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3784 if (temp_only_input
&& !indirect_write
)
3788 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3789 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3790 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3791 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3793 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3794 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3795 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3796 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3797 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3801 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3802 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3803 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3804 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3805 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3806 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3807 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3808 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3809 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3810 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3811 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3812 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3813 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3815 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3816 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3817 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3819 unreachable("Invalid LS or ES stage");
3822 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3823 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3824 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3828 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3833 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3834 return off
== ctx
->tcs_tess_lvl_out_loc
||
3835 off
== ctx
->tcs_tess_lvl_in_loc
;
3839 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3841 uint64_t mask
= per_vertex
3842 ? ctx
->program
->info
->tcs
.tes_inputs_read
3843 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
3845 bool indirect_write
= false;
3846 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3847 return indirect_write
|| output_read_by_tes
;
3850 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3852 uint64_t mask
= per_vertex
3853 ? ctx
->shader
->info
.outputs_read
3854 : ctx
->shader
->info
.patch_outputs_read
;
3856 bool indirect_write
= false;
3857 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3858 return indirect_write
|| output_read
;
3861 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3863 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3864 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3866 Builder
bld(ctx
->program
, ctx
->block
);
3868 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3869 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3870 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3872 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
3873 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
3874 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
3876 if (write_to_vmem
) {
3877 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3878 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3879 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3881 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3882 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3883 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3887 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3888 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3889 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3893 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3895 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3896 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3898 Builder
bld(ctx
->program
, ctx
->block
);
3900 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3901 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3902 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3903 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3905 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3908 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3910 if (ctx
->stage
== vertex_vs
||
3911 ctx
->stage
== tess_eval_vs
||
3912 ctx
->stage
== fragment_fs
||
3913 ctx
->stage
== ngg_vertex_gs
||
3914 ctx
->stage
== ngg_tess_eval_gs
||
3915 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3916 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3917 if (!stored_to_temps
) {
3918 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3919 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3920 fprintf(stderr
, "\n");
3923 } else if (ctx
->stage
== vertex_es
||
3924 ctx
->stage
== vertex_ls
||
3925 ctx
->stage
== tess_eval_es
||
3926 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3927 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3928 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3929 visit_store_ls_or_es_output(ctx
, instr
);
3930 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3931 visit_store_tcs_output(ctx
, instr
, false);
3933 unreachable("Shader stage not implemented");
3937 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3939 visit_load_tcs_output(ctx
, instr
, false);
3942 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3944 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3945 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3947 Builder
bld(ctx
->program
, ctx
->block
);
3948 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3949 if (ctx
->program
->has_16bank_lds
)
3950 interp_p1
.instr
->operands
[0].setLateKill(true);
3951 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3954 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3956 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3957 for (unsigned i
= 0; i
< num_components
; i
++)
3958 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3959 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3960 assert(num_components
== 4);
3961 Builder
bld(ctx
->program
, ctx
->block
);
3962 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3965 for (Operand
& op
: vec
->operands
)
3966 op
= op
.isUndefined() ? Operand(0u) : op
;
3968 vec
->definitions
[0] = Definition(dst
);
3969 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3970 emit_split_vector(ctx
, dst
, num_components
);
3974 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3977 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3978 unsigned idx
= nir_intrinsic_base(instr
);
3979 unsigned component
= nir_intrinsic_component(instr
);
3980 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3982 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3984 assert(offset
->u32
== 0);
3986 /* the lower 15bit of the prim_mask contain the offset into LDS
3987 * while the upper bits contain the number of prims */
3988 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3989 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3990 Builder
bld(ctx
->program
, ctx
->block
);
3991 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3992 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3993 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3994 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3995 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3998 if (instr
->dest
.ssa
.num_components
== 1) {
3999 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4001 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4002 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4004 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4005 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4006 vec
->operands
[i
] = Operand(tmp
);
4008 vec
->definitions
[0] = Definition(dst
);
4009 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4013 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4014 unsigned offset
, unsigned stride
, unsigned channels
)
4016 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4017 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4019 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4020 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4023 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4024 unsigned offset
, unsigned stride
, unsigned *channels
)
4026 if (!vtx_info
->chan_byte_size
) {
4027 *channels
= vtx_info
->num_channels
;
4028 return vtx_info
->chan_format
;
4031 unsigned num_channels
= *channels
;
4032 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4033 unsigned new_channels
= num_channels
+ 1;
4034 /* first, assume more loads is worse and try using a larger data format */
4035 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4037 /* don't make the attribute potentially out-of-bounds */
4038 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4042 if (new_channels
== 5) {
4043 /* then try decreasing load size (at the cost of more loads) */
4044 new_channels
= *channels
;
4045 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4049 if (new_channels
< *channels
)
4050 *channels
= new_channels
;
4051 num_channels
= new_channels
;
4054 switch (vtx_info
->chan_format
) {
4055 case V_008F0C_BUF_DATA_FORMAT_8
:
4056 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4057 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4058 case V_008F0C_BUF_DATA_FORMAT_16
:
4059 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4060 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4061 case V_008F0C_BUF_DATA_FORMAT_32
:
4062 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4063 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4065 unreachable("shouldn't reach here");
4066 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4069 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4070 * so we may need to fix it up. */
4071 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4073 Builder
bld(ctx
->program
, ctx
->block
);
4075 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4076 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4078 /* For the integer-like cases, do a natural sign extension.
4080 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4081 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4084 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4085 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4087 /* Convert back to the right type. */
4088 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4089 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4090 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4091 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4092 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4093 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4099 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4101 Builder
bld(ctx
->program
, ctx
->block
);
4102 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4103 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4105 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4106 if (off_instr
->type
!= nir_instr_type_load_const
) {
4107 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4108 nir_print_instr(off_instr
, stderr
);
4109 fprintf(stderr
, "\n");
4111 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4113 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4115 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4116 unsigned component
= nir_intrinsic_component(instr
);
4117 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4118 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4119 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4120 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4122 unsigned dfmt
= attrib_format
& 0xf;
4123 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4124 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4126 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4127 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4128 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4129 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4131 num_channels
= MAX2(num_channels
, 3);
4133 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4134 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4137 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4138 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4139 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4141 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4143 Temp divided
= bld
.tmp(v1
);
4144 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4145 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4147 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4150 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4153 index
= bld
.vadd32(bld
.def(v1
),
4154 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4155 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4158 Temp channels
[num_channels
];
4159 unsigned channel_start
= 0;
4160 bool direct_fetch
= false;
4162 /* skip unused channels at the start */
4163 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4164 channel_start
= ffs(mask
) - 1;
4165 for (unsigned i
= 0; i
< channel_start
; i
++)
4166 channels
[i
] = Temp(0, s1
);
4167 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4168 num_channels
= 3 - (ffs(mask
) - 1);
4172 while (channel_start
< num_channels
) {
4173 unsigned fetch_size
= num_channels
- channel_start
;
4174 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4175 bool expanded
= false;
4177 /* use MUBUF when possible to avoid possible alignment issues */
4178 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4179 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4180 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4181 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4182 vtx_info
->chan_byte_size
== 4;
4183 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4185 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4187 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4188 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4194 Temp fetch_index
= index
;
4195 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4196 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4197 fetch_offset
= fetch_offset
% attrib_stride
;
4200 Operand
soffset(0u);
4201 if (fetch_offset
>= 4096) {
4202 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4203 fetch_offset
%= 4096;
4207 switch (fetch_size
) {
4209 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4212 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4215 assert(ctx
->options
->chip_class
>= GFX7
||
4216 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4217 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4220 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4223 unreachable("Unimplemented load_input vector size");
4227 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4228 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4229 num_channels
<= 3)) {
4230 direct_fetch
= true;
4233 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4237 Instruction
*mubuf
= bld
.mubuf(opcode
,
4238 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4239 fetch_offset
, false, true).instr
;
4240 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4242 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4243 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4244 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4245 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4248 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4250 if (fetch_size
== 1) {
4251 channels
[channel_start
] = fetch_dst
;
4253 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4254 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4257 channel_start
+= fetch_size
;
4260 if (!direct_fetch
) {
4261 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4262 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4264 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4265 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4266 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4268 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4269 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4270 unsigned num_temp
= 0;
4271 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4272 unsigned idx
= i
+ component
;
4273 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4274 Temp channel
= channels
[swizzle
[idx
]];
4275 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4276 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4277 vec
->operands
[i
] = Operand(channel
);
4281 } else if (is_float
&& idx
== 3) {
4282 vec
->operands
[i
] = Operand(0x3f800000u
);
4283 } else if (!is_float
&& idx
== 3) {
4284 vec
->operands
[i
] = Operand(1u);
4286 vec
->operands
[i
] = Operand(0u);
4289 vec
->definitions
[0] = Definition(dst
);
4290 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4291 emit_split_vector(ctx
, dst
, dst
.size());
4293 if (num_temp
== dst
.size())
4294 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4296 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4297 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4298 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4299 if (off_instr
->type
!= nir_instr_type_load_const
||
4300 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4301 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4302 nir_print_instr(off_instr
, stderr
);
4303 fprintf(stderr
, "\n");
4306 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4307 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4309 assert(offset
->u32
== 0);
4311 /* the lower 15bit of the prim_mask contain the offset into LDS
4312 * while the upper bits contain the number of prims */
4313 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4314 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4315 Builder
bld(ctx
->program
, ctx
->block
);
4316 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4317 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4318 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4319 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4320 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4323 unsigned idx
= nir_intrinsic_base(instr
);
4324 unsigned component
= nir_intrinsic_component(instr
);
4325 unsigned vertex_id
= 2; /* P0 */
4327 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4328 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4329 switch (src0
->u32
) {
4331 vertex_id
= 2; /* P0 */
4334 vertex_id
= 0; /* P10 */
4337 vertex_id
= 1; /* P20 */
4340 unreachable("invalid vertex index");
4344 if (dst
.size() == 1) {
4345 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4347 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4348 for (unsigned i
= 0; i
< dst
.size(); i
++)
4349 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4350 vec
->definitions
[0] = Definition(dst
);
4351 bld
.insert(std::move(vec
));
4354 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4355 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4356 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4357 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4358 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4360 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4362 unreachable("Shader stage not implemented");
4366 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4368 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4370 Builder
bld(ctx
->program
, ctx
->block
);
4371 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4374 if (!nir_src_is_const(*vertex_src
)) {
4375 /* better code could be created, but this case probably doesn't happen
4376 * much in practice */
4377 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4378 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4381 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4382 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4384 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4386 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4389 if (vertex_offset
.id()) {
4390 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4391 Operand(i
), indirect_vertex
);
4392 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4394 vertex_offset
= elem
;
4398 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4399 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4401 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4402 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4403 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4404 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4405 Operand((vertex
% 2u) * 16u), Operand(16u));
4407 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4410 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4411 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4412 return offset_mul(ctx
, offs
, 4u);
4415 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4417 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4419 Builder
bld(ctx
->program
, ctx
->block
);
4420 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4421 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4423 if (ctx
->stage
== geometry_gs
) {
4424 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4425 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4426 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4427 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4428 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4429 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4430 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4432 unreachable("Unsupported GS stage.");
4436 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4438 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4440 Builder
bld(ctx
->program
, ctx
->block
);
4441 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4443 if (load_input_from_temps(ctx
, instr
, dst
))
4446 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4447 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4448 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4450 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4453 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4455 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4457 Builder
bld(ctx
->program
, ctx
->block
);
4459 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4460 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4461 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4463 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4464 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4466 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4469 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4471 switch (ctx
->shader
->info
.stage
) {
4472 case MESA_SHADER_GEOMETRY
:
4473 visit_load_gs_per_vertex_input(ctx
, instr
);
4475 case MESA_SHADER_TESS_CTRL
:
4476 visit_load_tcs_per_vertex_input(ctx
, instr
);
4478 case MESA_SHADER_TESS_EVAL
:
4479 visit_load_tes_per_vertex_input(ctx
, instr
);
4482 unreachable("Unimplemented shader stage");
4486 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4488 visit_load_tcs_output(ctx
, instr
, true);
4491 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4493 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4494 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4496 visit_store_tcs_output(ctx
, instr
, true);
4499 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4501 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4503 Builder
bld(ctx
->program
, ctx
->block
);
4504 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4506 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4507 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4510 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4511 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4512 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4513 tes_w
= Operand(tmp
);
4516 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4517 emit_split_vector(ctx
, tess_coord
, 3);
4520 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4522 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4523 Builder
bld(ctx
->program
, ctx
->block
);
4524 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4525 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4526 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4529 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4533 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4535 Builder
bld(ctx
->program
, ctx
->block
);
4536 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4537 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4538 index
= bld
.as_uniform(index
);
4539 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4540 unsigned binding
= nir_intrinsic_binding(instr
);
4543 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4544 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4545 unsigned offset
= layout
->binding
[binding
].offset
;
4547 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4548 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4549 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4550 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4551 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4554 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4555 stride
= layout
->binding
[binding
].size
;
4558 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4559 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4561 if (nir_const_index
) {
4562 const_index
= const_index
* stride
;
4563 } else if (index
.type() == RegType::vgpr
) {
4564 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4565 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4567 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4571 if (nir_const_index
) {
4572 const_index
= const_index
+ offset
;
4573 } else if (index
.type() == RegType::vgpr
) {
4574 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4576 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4580 if (nir_const_index
&& const_index
== 0) {
4582 } else if (index
.type() == RegType::vgpr
) {
4583 index
= bld
.vadd32(bld
.def(v1
),
4584 nir_const_index
? Operand(const_index
) : Operand(index
),
4587 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4588 nir_const_index
? Operand(const_index
) : Operand(index
),
4592 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4595 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4596 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4597 bool glc
=false, bool readonly
=true)
4599 Builder
bld(ctx
->program
, ctx
->block
);
4600 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4601 unsigned num_bytes
= num_components
* component_size
;
4604 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4605 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4606 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4607 unsigned const_offset
= 0;
4609 /* for small bit sizes add buffer for unaligned loads */
4612 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4617 Temp lower
= Temp();
4618 if (num_bytes
> 16) {
4619 assert(num_components
== 3 || num_components
== 4);
4620 op
= aco_opcode::buffer_load_dwordx4
;
4621 lower
= bld
.tmp(v4
);
4622 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4623 mubuf
->definitions
[0] = Definition(lower
);
4624 mubuf
->operands
[0] = Operand(rsrc
);
4625 mubuf
->operands
[1] = vaddr
;
4626 mubuf
->operands
[2] = soffset
;
4627 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4630 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4631 mubuf
->can_reorder
= readonly
;
4632 bld
.insert(std::move(mubuf
));
4633 emit_split_vector(ctx
, lower
, 2);
4636 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4637 /* GFX6 doesn't support loading vec3, expand to vec4. */
4641 switch (num_bytes
) {
4643 op
= aco_opcode::buffer_load_ubyte
;
4646 op
= aco_opcode::buffer_load_ushort
;
4650 op
= aco_opcode::buffer_load_dword
;
4656 op
= aco_opcode::buffer_load_dwordx2
;
4660 assert(ctx
->options
->chip_class
> GFX6
);
4661 op
= aco_opcode::buffer_load_dwordx3
;
4664 op
= aco_opcode::buffer_load_dwordx4
;
4667 unreachable("Load SSBO not implemented for this size.");
4669 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4670 mubuf
->operands
[0] = Operand(rsrc
);
4671 mubuf
->operands
[1] = vaddr
;
4672 mubuf
->operands
[2] = soffset
;
4673 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4676 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4677 mubuf
->can_reorder
= readonly
;
4678 mubuf
->offset
= const_offset
;
4679 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4681 if (component_size
< 4) {
4682 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4683 instr
->definitions
[0] = Definition(vec
);
4684 bld
.insert(std::move(instr
));
4686 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4687 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4688 Temp tmp
[3] = {vec
, vec
, vec
};
4690 if (vec
.size() == 3) {
4691 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4692 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4693 } else if (vec
.size() == 2) {
4694 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4695 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4697 for (unsigned i
= 0; i
< dst
.size(); i
++)
4698 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4701 if (dst
.size() == 2)
4702 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4707 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4708 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4710 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4715 } else if (dst
.size() > 4) {
4716 assert(lower
!= Temp());
4717 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4718 instr
->definitions
[0] = Definition(upper
);
4719 bld
.insert(std::move(instr
));
4720 if (dst
.size() == 8)
4721 emit_split_vector(ctx
, upper
, 2);
4722 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4723 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4724 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4725 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4726 if (dst
.size() == 8)
4727 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4728 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4729 Temp vec
= bld
.tmp(v4
);
4730 instr
->definitions
[0] = Definition(vec
);
4731 bld
.insert(std::move(instr
));
4732 emit_split_vector(ctx
, vec
, 4);
4734 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4735 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4736 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4737 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4740 if (dst
.type() == RegType::sgpr
) {
4741 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4742 instr
->definitions
[0] = Definition(vec
);
4743 bld
.insert(std::move(instr
));
4744 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4746 instr
->definitions
[0] = Definition(dst
);
4747 bld
.insert(std::move(instr
));
4748 emit_split_vector(ctx
, dst
, num_components
);
4751 /* for small bit sizes add buffer for unaligned loads */
4753 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4755 switch (num_bytes
) {
4760 op
= aco_opcode::s_buffer_load_dword
;
4766 op
= aco_opcode::s_buffer_load_dwordx2
;
4771 op
= aco_opcode::s_buffer_load_dwordx4
;
4775 op
= aco_opcode::s_buffer_load_dwordx8
;
4778 unreachable("Load SSBO not implemented for this size.");
4780 offset
= bld
.as_uniform(offset
);
4781 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4782 load
->operands
[0] = Operand(rsrc
);
4783 load
->operands
[1] = Operand(offset
);
4784 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4785 load
->definitions
[0] = Definition(dst
);
4788 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4789 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4790 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4792 /* adjust misaligned small bit size loads */
4794 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4795 load
->definitions
[0] = Definition(vec
);
4796 bld
.insert(std::move(load
));
4797 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4798 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4801 } else if (dst
.size() == 3) {
4802 Temp vec
= bld
.tmp(s4
);
4803 load
->definitions
[0] = Definition(vec
);
4804 bld
.insert(std::move(load
));
4805 emit_split_vector(ctx
, vec
, 4);
4807 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4808 emit_extract_vector(ctx
, vec
, 0, s1
),
4809 emit_extract_vector(ctx
, vec
, 1, s1
),
4810 emit_extract_vector(ctx
, vec
, 2, s1
));
4811 } else if (dst
.size() == 6) {
4812 Temp vec
= bld
.tmp(s8
);
4813 load
->definitions
[0] = Definition(vec
);
4814 bld
.insert(std::move(load
));
4815 emit_split_vector(ctx
, vec
, 4);
4817 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4818 emit_extract_vector(ctx
, vec
, 0, s2
),
4819 emit_extract_vector(ctx
, vec
, 1, s2
),
4820 emit_extract_vector(ctx
, vec
, 2, s2
));
4822 bld
.insert(std::move(load
));
4824 emit_split_vector(ctx
, dst
, num_components
);
4828 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4830 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4831 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4833 Builder
bld(ctx
->program
, ctx
->block
);
4835 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4836 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4837 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4838 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4840 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4841 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4842 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4843 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4844 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4845 if (ctx
->options
->chip_class
>= GFX10
) {
4846 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4847 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4848 S_008F0C_RESOURCE_LEVEL(1);
4850 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4851 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4853 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4854 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4855 Operand(0xFFFFFFFFu
),
4856 Operand(desc_type
));
4857 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4858 rsrc
, upper_dwords
);
4860 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4861 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4863 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4866 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4867 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4868 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4870 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4873 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4875 Builder
bld(ctx
->program
, ctx
->block
);
4876 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4877 unsigned offset
= nir_intrinsic_base(instr
);
4878 unsigned count
= instr
->dest
.ssa
.num_components
;
4879 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4881 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4882 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4883 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4884 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4885 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4886 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4887 for (unsigned i
= 0; i
< count
; ++i
) {
4888 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4889 vec
->operands
[i
] = Operand
{elems
[i
]};
4891 vec
->definitions
[0] = Definition(dst
);
4892 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4893 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4898 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4899 if (offset
!= 0) // TODO check if index != 0 as well
4900 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4901 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4904 bool aligned
= true;
4906 if (instr
->dest
.ssa
.bit_size
== 8) {
4907 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4908 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4910 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4911 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4912 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4914 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4919 switch (vec
.size()) {
4921 op
= aco_opcode::s_load_dword
;
4924 op
= aco_opcode::s_load_dwordx2
;
4930 op
= aco_opcode::s_load_dwordx4
;
4936 op
= aco_opcode::s_load_dwordx8
;
4939 unreachable("unimplemented or forbidden load_push_constant.");
4942 bld
.smem(op
, Definition(vec
), ptr
, index
);
4945 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4946 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4951 emit_split_vector(ctx
, vec
, 4);
4952 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4953 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4954 emit_extract_vector(ctx
, vec
, 0, rc
),
4955 emit_extract_vector(ctx
, vec
, 1, rc
),
4956 emit_extract_vector(ctx
, vec
, 2, rc
));
4959 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4962 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4964 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4966 Builder
bld(ctx
->program
, ctx
->block
);
4968 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4969 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4970 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4971 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4972 if (ctx
->options
->chip_class
>= GFX10
) {
4973 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4974 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4975 S_008F0C_RESOURCE_LEVEL(1);
4977 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4978 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4981 unsigned base
= nir_intrinsic_base(instr
);
4982 unsigned range
= nir_intrinsic_range(instr
);
4984 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4985 if (base
&& offset
.type() == RegType::sgpr
)
4986 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4987 else if (base
&& offset
.type() == RegType::vgpr
)
4988 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4990 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4991 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4992 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4993 Operand(desc_type
));
4994 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4995 // TODO: get alignment information for subdword constants
4996 unsigned byte_align
= size
< 4 ? -1 : 0;
4997 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
5000 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5002 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5003 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5005 ctx
->program
->needs_exact
= true;
5007 // TODO: optimize uniform conditions
5008 Builder
bld(ctx
->program
, ctx
->block
);
5009 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5010 assert(src
.regClass() == bld
.lm
);
5011 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5012 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5013 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5017 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5019 Builder
bld(ctx
->program
, ctx
->block
);
5021 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5022 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5024 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5025 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5027 if (ctx
->block
->loop_nest_depth
&&
5028 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5029 /* we handle discards the same way as jump instructions */
5030 append_logical_end(ctx
->block
);
5032 /* in loops, discard behaves like break */
5033 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5034 ctx
->block
->kind
|= block_kind_discard
;
5037 /* uniform discard - loop ends here */
5038 assert(nir_instr_is_last(&instr
->instr
));
5039 ctx
->block
->kind
|= block_kind_uniform
;
5040 ctx
->cf_info
.has_branch
= true;
5041 bld
.branch(aco_opcode::p_branch
);
5042 add_linear_edge(ctx
->block
->index
, linear_target
);
5046 /* we add a break right behind the discard() instructions */
5047 ctx
->block
->kind
|= block_kind_break
;
5048 unsigned idx
= ctx
->block
->index
;
5050 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5051 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5053 /* remove critical edges from linear CFG */
5054 bld
.branch(aco_opcode::p_branch
);
5055 Block
* break_block
= ctx
->program
->create_and_insert_block();
5056 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5057 break_block
->kind
|= block_kind_uniform
;
5058 add_linear_edge(idx
, break_block
);
5059 add_linear_edge(break_block
->index
, linear_target
);
5060 bld
.reset(break_block
);
5061 bld
.branch(aco_opcode::p_branch
);
5063 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5064 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5065 add_linear_edge(idx
, continue_block
);
5066 append_logical_start(continue_block
);
5067 ctx
->block
= continue_block
;
5072 /* it can currently happen that NIR doesn't remove the unreachable code */
5073 if (!nir_instr_is_last(&instr
->instr
)) {
5074 ctx
->program
->needs_exact
= true;
5075 /* save exec somewhere temporarily so that it doesn't get
5076 * overwritten before the discard from outer exec masks */
5077 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5078 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5079 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5083 /* This condition is incorrect for uniformly branched discards in a loop
5084 * predicated by a divergent condition, but the above code catches that case
5085 * and the discard would end up turning into a discard_if.
5095 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5096 /* program just ends here */
5097 ctx
->block
->kind
|= block_kind_uniform
;
5098 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5099 0 /* enabled mask */, 9 /* dest */,
5100 false /* compressed */, true/* done */, true /* valid mask */);
5101 bld
.sopp(aco_opcode::s_endpgm
);
5102 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5104 ctx
->block
->kind
|= block_kind_discard
;
5105 /* branch and linear edge is added by visit_if() */
5109 enum aco_descriptor_type
{
5120 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5121 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5123 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5124 return dim
== ac_image_cube
||
5125 dim
== ac_image_1darray
||
5126 dim
== ac_image_2darray
||
5127 dim
== ac_image_2darraymsaa
;
5130 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5131 enum aco_descriptor_type desc_type
,
5132 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5134 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5135 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5136 if (it != ctx->tex_desc.end())
5139 Temp index
= Temp();
5140 bool index_set
= false;
5141 unsigned constant_index
= 0;
5142 unsigned descriptor_set
;
5143 unsigned base_index
;
5144 Builder
bld(ctx
->program
, ctx
->block
);
5147 assert(tex_instr
&& !image
);
5149 base_index
= tex_instr
->sampler_index
;
5151 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5152 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5156 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5157 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5159 constant_index
+= array_size
* const_value
->u32
;
5161 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5162 if (indirect
.type() == RegType::vgpr
)
5163 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5165 if (array_size
!= 1)
5166 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5172 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5176 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5178 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5179 base_index
= deref_instr
->var
->data
.binding
;
5182 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5183 list
= convert_pointer_to_64_bit(ctx
, list
);
5185 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5186 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5187 unsigned offset
= binding
->offset
;
5188 unsigned stride
= binding
->size
;
5192 assert(base_index
< layout
->binding_count
);
5194 switch (desc_type
) {
5195 case ACO_DESC_IMAGE
:
5197 opcode
= aco_opcode::s_load_dwordx8
;
5199 case ACO_DESC_FMASK
:
5201 opcode
= aco_opcode::s_load_dwordx8
;
5204 case ACO_DESC_SAMPLER
:
5206 opcode
= aco_opcode::s_load_dwordx4
;
5207 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5208 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5210 case ACO_DESC_BUFFER
:
5212 opcode
= aco_opcode::s_load_dwordx4
;
5214 case ACO_DESC_PLANE_0
:
5215 case ACO_DESC_PLANE_1
:
5217 opcode
= aco_opcode::s_load_dwordx8
;
5218 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5220 case ACO_DESC_PLANE_2
:
5222 opcode
= aco_opcode::s_load_dwordx4
;
5226 unreachable("invalid desc_type\n");
5229 offset
+= constant_index
* stride
;
5231 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5232 (!index_set
|| binding
->immutable_samplers_equal
)) {
5233 if (binding
->immutable_samplers_equal
)
5236 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5237 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5238 Operand(samplers
[constant_index
* 4 + 0]),
5239 Operand(samplers
[constant_index
* 4 + 1]),
5240 Operand(samplers
[constant_index
* 4 + 2]),
5241 Operand(samplers
[constant_index
* 4 + 3]));
5246 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5248 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5249 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5252 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5254 if (desc_type
== ACO_DESC_PLANE_2
) {
5256 for (unsigned i
= 0; i
< 8; i
++)
5257 components
[i
] = bld
.tmp(s1
);
5258 bld
.pseudo(aco_opcode::p_split_vector
,
5259 Definition(components
[0]),
5260 Definition(components
[1]),
5261 Definition(components
[2]),
5262 Definition(components
[3]),
5265 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5266 bld
.pseudo(aco_opcode::p_split_vector
,
5267 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5268 Definition(components
[4]),
5269 Definition(components
[5]),
5270 Definition(components
[6]),
5271 Definition(components
[7]),
5274 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5275 components
[0], components
[1], components
[2], components
[3],
5276 components
[4], components
[5], components
[6], components
[7]);
5282 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5285 case GLSL_SAMPLER_DIM_BUF
:
5287 case GLSL_SAMPLER_DIM_1D
:
5288 return array
? 2 : 1;
5289 case GLSL_SAMPLER_DIM_2D
:
5290 return array
? 3 : 2;
5291 case GLSL_SAMPLER_DIM_MS
:
5292 return array
? 4 : 3;
5293 case GLSL_SAMPLER_DIM_3D
:
5294 case GLSL_SAMPLER_DIM_CUBE
:
5296 case GLSL_SAMPLER_DIM_RECT
:
5297 case GLSL_SAMPLER_DIM_SUBPASS
:
5299 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5308 /* Adjust the sample index according to FMASK.
5310 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5311 * which is the identity mapping. Each nibble says which physical sample
5312 * should be fetched to get that sample.
5314 * For example, 0x11111100 means there are only 2 samples stored and
5315 * the second sample covers 3/4 of the pixel. When reading samples 0
5316 * and 1, return physical sample 0 (determined by the first two 0s
5317 * in FMASK), otherwise return physical sample 1.
5319 * The sample index should be adjusted as follows:
5320 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5322 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5324 Builder
bld(ctx
->program
, ctx
->block
);
5325 Temp fmask
= bld
.tmp(v1
);
5326 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5327 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5330 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5331 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5332 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5333 load
->operands
[0] = Operand(fmask_desc_ptr
);
5334 load
->operands
[1] = Operand(s4
); /* no sampler */
5335 load
->operands
[2] = Operand(coord
);
5336 load
->definitions
[0] = Definition(fmask
);
5343 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5344 ctx
->block
->instructions
.emplace_back(std::move(load
));
5346 Operand sample_index4
;
5347 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5348 sample_index4
= Operand(sample_index
.constantValue() << 2);
5349 } else if (sample_index
.regClass() == s1
) {
5350 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5352 assert(sample_index
.regClass() == v1
);
5353 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5357 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5358 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5359 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5360 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5362 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5364 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5365 * resource descriptor is 0 (invalid),
5367 Temp compare
= bld
.tmp(bld
.lm
);
5368 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5369 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5371 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5373 /* Replace the MSAA sample index. */
5374 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5377 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5380 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5381 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5382 bool is_array
= glsl_sampler_type_is_array(type
);
5383 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5384 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5385 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5386 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5387 int count
= image_type_to_components_count(dim
, is_array
);
5388 std::vector
<Temp
> coords(count
);
5389 Builder
bld(ctx
->program
, ctx
->block
);
5393 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5394 /* get sample index */
5395 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5396 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5397 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5398 std::vector
<Temp
> fmask_load_address
;
5399 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5400 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5402 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5403 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5405 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5410 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5411 coords
.resize(coords
.size() + 1);
5412 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5414 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5416 for (int i
= 0; i
< count
; i
++)
5417 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5420 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5421 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5422 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5423 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5426 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5429 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5430 for (unsigned i
= 0; i
< coords
.size(); i
++)
5431 vec
->operands
[i
] = Operand(coords
[i
]);
5432 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5433 vec
->definitions
[0] = Definition(res
);
5434 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5439 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5441 Builder
bld(ctx
->program
, ctx
->block
);
5442 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5443 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5444 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5445 bool is_array
= glsl_sampler_type_is_array(type
);
5446 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5448 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5449 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5450 unsigned num_channels
= util_last_bit(mask
);
5451 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5452 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5455 switch (num_channels
) {
5457 opcode
= aco_opcode::buffer_load_format_x
;
5460 opcode
= aco_opcode::buffer_load_format_xy
;
5463 opcode
= aco_opcode::buffer_load_format_xyz
;
5466 opcode
= aco_opcode::buffer_load_format_xyzw
;
5469 unreachable(">4 channel buffer image load");
5471 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5472 load
->operands
[0] = Operand(rsrc
);
5473 load
->operands
[1] = Operand(vindex
);
5474 load
->operands
[2] = Operand((uint32_t) 0);
5476 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5479 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5480 load
->definitions
[0] = Definition(tmp
);
5482 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5483 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5484 load
->barrier
= barrier_image
;
5485 ctx
->block
->instructions
.emplace_back(std::move(load
));
5487 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5491 Temp coords
= get_image_coords(ctx
, instr
, type
);
5492 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5494 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5495 unsigned num_components
= util_bitcount(dmask
);
5497 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5500 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5502 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5503 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5505 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5506 load
->operands
[0] = Operand(resource
);
5507 load
->operands
[1] = Operand(s4
); /* no sampler */
5508 load
->operands
[2] = Operand(coords
);
5509 load
->definitions
[0] = Definition(tmp
);
5510 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5511 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5512 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5513 load
->dmask
= dmask
;
5515 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5516 load
->barrier
= barrier_image
;
5517 ctx
->block
->instructions
.emplace_back(std::move(load
));
5519 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5523 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5525 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5526 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5527 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5528 bool is_array
= glsl_sampler_type_is_array(type
);
5529 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5531 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5533 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5534 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5535 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5537 switch (data
.size()) {
5539 opcode
= aco_opcode::buffer_store_format_x
;
5542 opcode
= aco_opcode::buffer_store_format_xy
;
5545 opcode
= aco_opcode::buffer_store_format_xyz
;
5548 opcode
= aco_opcode::buffer_store_format_xyzw
;
5551 unreachable(">4 channel buffer image store");
5553 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5554 store
->operands
[0] = Operand(rsrc
);
5555 store
->operands
[1] = Operand(vindex
);
5556 store
->operands
[2] = Operand((uint32_t) 0);
5557 store
->operands
[3] = Operand(data
);
5558 store
->idxen
= true;
5561 store
->disable_wqm
= true;
5562 store
->barrier
= barrier_image
;
5563 ctx
->program
->needs_exact
= true;
5564 ctx
->block
->instructions
.emplace_back(std::move(store
));
5568 assert(data
.type() == RegType::vgpr
);
5569 Temp coords
= get_image_coords(ctx
, instr
, type
);
5570 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5572 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5573 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5575 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5576 store
->operands
[0] = Operand(resource
);
5577 store
->operands
[1] = Operand(data
);
5578 store
->operands
[2] = Operand(coords
);
5581 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5582 store
->dmask
= (1 << data
.size()) - 1;
5584 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5585 store
->disable_wqm
= true;
5586 store
->barrier
= barrier_image
;
5587 ctx
->program
->needs_exact
= true;
5588 ctx
->block
->instructions
.emplace_back(std::move(store
));
5592 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5594 /* return the previous value if dest is ever used */
5595 bool return_previous
= false;
5596 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5597 return_previous
= true;
5600 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5601 return_previous
= true;
5605 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5606 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5607 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5608 bool is_array
= glsl_sampler_type_is_array(type
);
5609 Builder
bld(ctx
->program
, ctx
->block
);
5611 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5612 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5614 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5615 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5617 aco_opcode buf_op
, image_op
;
5618 switch (instr
->intrinsic
) {
5619 case nir_intrinsic_image_deref_atomic_add
:
5620 buf_op
= aco_opcode::buffer_atomic_add
;
5621 image_op
= aco_opcode::image_atomic_add
;
5623 case nir_intrinsic_image_deref_atomic_umin
:
5624 buf_op
= aco_opcode::buffer_atomic_umin
;
5625 image_op
= aco_opcode::image_atomic_umin
;
5627 case nir_intrinsic_image_deref_atomic_imin
:
5628 buf_op
= aco_opcode::buffer_atomic_smin
;
5629 image_op
= aco_opcode::image_atomic_smin
;
5631 case nir_intrinsic_image_deref_atomic_umax
:
5632 buf_op
= aco_opcode::buffer_atomic_umax
;
5633 image_op
= aco_opcode::image_atomic_umax
;
5635 case nir_intrinsic_image_deref_atomic_imax
:
5636 buf_op
= aco_opcode::buffer_atomic_smax
;
5637 image_op
= aco_opcode::image_atomic_smax
;
5639 case nir_intrinsic_image_deref_atomic_and
:
5640 buf_op
= aco_opcode::buffer_atomic_and
;
5641 image_op
= aco_opcode::image_atomic_and
;
5643 case nir_intrinsic_image_deref_atomic_or
:
5644 buf_op
= aco_opcode::buffer_atomic_or
;
5645 image_op
= aco_opcode::image_atomic_or
;
5647 case nir_intrinsic_image_deref_atomic_xor
:
5648 buf_op
= aco_opcode::buffer_atomic_xor
;
5649 image_op
= aco_opcode::image_atomic_xor
;
5651 case nir_intrinsic_image_deref_atomic_exchange
:
5652 buf_op
= aco_opcode::buffer_atomic_swap
;
5653 image_op
= aco_opcode::image_atomic_swap
;
5655 case nir_intrinsic_image_deref_atomic_comp_swap
:
5656 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5657 image_op
= aco_opcode::image_atomic_cmpswap
;
5660 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5663 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5665 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5666 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5667 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5668 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5669 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5670 mubuf
->operands
[0] = Operand(resource
);
5671 mubuf
->operands
[1] = Operand(vindex
);
5672 mubuf
->operands
[2] = Operand((uint32_t)0);
5673 mubuf
->operands
[3] = Operand(data
);
5674 if (return_previous
)
5675 mubuf
->definitions
[0] = Definition(dst
);
5677 mubuf
->idxen
= true;
5678 mubuf
->glc
= return_previous
;
5679 mubuf
->dlc
= false; /* Not needed for atomics */
5680 mubuf
->disable_wqm
= true;
5681 mubuf
->barrier
= barrier_image
;
5682 ctx
->program
->needs_exact
= true;
5683 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5687 Temp coords
= get_image_coords(ctx
, instr
, type
);
5688 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5689 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5690 mimg
->operands
[0] = Operand(resource
);
5691 mimg
->operands
[1] = Operand(data
);
5692 mimg
->operands
[2] = Operand(coords
);
5693 if (return_previous
)
5694 mimg
->definitions
[0] = Definition(dst
);
5695 mimg
->glc
= return_previous
;
5696 mimg
->dlc
= false; /* Not needed for atomics */
5697 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5698 mimg
->dmask
= (1 << data
.size()) - 1;
5700 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5701 mimg
->disable_wqm
= true;
5702 mimg
->barrier
= barrier_image
;
5703 ctx
->program
->needs_exact
= true;
5704 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5708 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5710 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5711 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5712 Builder
bld(ctx
->program
, ctx
->block
);
5714 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5716 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5717 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5719 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5720 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5722 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5723 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5725 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5726 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5727 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5728 if (dst
.type() == RegType::vgpr
)
5729 bld
.copy(Definition(dst
), shr_dst
);
5731 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5733 emit_extract_vector(ctx
, desc
, 2, dst
);
5737 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5739 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5740 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5741 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5742 bool is_array
= glsl_sampler_type_is_array(type
);
5743 Builder
bld(ctx
->program
, ctx
->block
);
5745 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5746 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5747 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5751 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5754 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5756 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5758 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5759 mimg
->operands
[0] = Operand(resource
);
5760 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5761 mimg
->operands
[2] = Operand(lod
);
5762 uint8_t& dmask
= mimg
->dmask
;
5763 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5764 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5765 mimg
->da
= glsl_sampler_type_is_array(type
);
5766 mimg
->can_reorder
= true;
5767 Definition
& def
= mimg
->definitions
[0];
5768 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5770 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5771 glsl_sampler_type_is_array(type
)) {
5773 assert(instr
->dest
.ssa
.num_components
== 3);
5774 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5775 def
= Definition(tmp
);
5776 emit_split_vector(ctx
, tmp
, 3);
5778 /* divide 3rd value by 6 by multiplying with magic number */
5779 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5780 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5782 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5783 emit_extract_vector(ctx
, tmp
, 0, v1
),
5784 emit_extract_vector(ctx
, tmp
, 1, v1
),
5787 } else if (ctx
->options
->chip_class
== GFX9
&&
5788 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5789 glsl_sampler_type_is_array(type
)) {
5790 assert(instr
->dest
.ssa
.num_components
== 2);
5791 def
= Definition(dst
);
5794 def
= Definition(dst
);
5797 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5800 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5802 Builder
bld(ctx
->program
, ctx
->block
);
5803 unsigned num_components
= instr
->num_components
;
5805 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5806 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5807 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5809 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5810 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5813 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5814 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5815 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5817 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5820 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5822 Builder
bld(ctx
->program
, ctx
->block
);
5823 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5824 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5825 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5826 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5828 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5829 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5831 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5832 ctx
->options
->chip_class
>= GFX8
&&
5833 elem_size_bytes
>= 4;
5835 offset
= bld
.as_uniform(offset
);
5836 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5840 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5841 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5842 /* GFX6 doesn't support storing vec3, split it. */
5843 writemask
|= 1u << (start
+ 2);
5846 int num_bytes
= count
* elem_size_bytes
;
5848 /* dword or larger stores have to be dword-aligned */
5849 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5850 // TODO: improve alignment check of sub-dword stores
5851 unsigned count_new
= 2 / elem_size_bytes
;
5852 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5857 if (num_bytes
> 16) {
5858 assert(elem_size_bytes
== 8);
5859 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5865 if (elem_size_bytes
< 4) {
5866 if (data
.type() == RegType::sgpr
) {
5867 data
= as_vgpr(ctx
, data
);
5868 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5870 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5871 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5872 for (int i
= 0; i
< count
; i
++)
5873 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5874 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5875 vec
->definitions
[0] = Definition(write_data
);
5876 bld
.insert(std::move(vec
));
5877 } else if (count
!= instr
->num_components
) {
5878 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5879 for (int i
= 0; i
< count
; i
++) {
5880 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5881 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5883 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5884 vec
->definitions
[0] = Definition(write_data
);
5885 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5886 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5887 assert(num_bytes
% 4 == 0);
5888 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5889 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5890 assert(num_bytes
% 4 == 0);
5891 write_data
= bld
.as_uniform(data
);
5896 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5897 switch (num_bytes
) {
5899 vmem_op
= aco_opcode::buffer_store_byte
;
5902 vmem_op
= aco_opcode::buffer_store_short
;
5905 vmem_op
= aco_opcode::buffer_store_dword
;
5906 smem_op
= aco_opcode::s_buffer_store_dword
;
5909 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5910 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5913 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5914 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5917 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5918 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5921 unreachable("Store SSBO not implemented for this size.");
5923 if (ctx
->stage
== fragment_fs
)
5924 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5927 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5928 store
->operands
[0] = Operand(rsrc
);
5930 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5931 offset
, Operand(start
* elem_size_bytes
));
5932 store
->operands
[1] = Operand(off
);
5934 store
->operands
[1] = Operand(offset
);
5936 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5937 store
->operands
[1].setFixed(m0
);
5938 store
->operands
[2] = Operand(write_data
);
5939 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5941 store
->disable_wqm
= true;
5942 store
->barrier
= barrier_buffer
;
5943 ctx
->block
->instructions
.emplace_back(std::move(store
));
5944 ctx
->program
->wb_smem_l1_on_end
= true;
5945 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5946 ctx
->block
->kind
|= block_kind_needs_lowering
;
5947 ctx
->program
->needs_exact
= true;
5950 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5951 store
->operands
[0] = Operand(rsrc
);
5952 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5953 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5954 store
->operands
[3] = Operand(write_data
);
5955 store
->offset
= start
* elem_size_bytes
;
5956 store
->offen
= (offset
.type() == RegType::vgpr
);
5957 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5959 store
->disable_wqm
= true;
5960 store
->barrier
= barrier_buffer
;
5961 ctx
->program
->needs_exact
= true;
5962 ctx
->block
->instructions
.emplace_back(std::move(store
));
5967 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5969 /* return the previous value if dest is ever used */
5970 bool return_previous
= false;
5971 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5972 return_previous
= true;
5975 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5976 return_previous
= true;
5980 Builder
bld(ctx
->program
, ctx
->block
);
5981 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5983 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5984 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5985 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5987 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5988 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5989 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5991 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5993 aco_opcode op32
, op64
;
5994 switch (instr
->intrinsic
) {
5995 case nir_intrinsic_ssbo_atomic_add
:
5996 op32
= aco_opcode::buffer_atomic_add
;
5997 op64
= aco_opcode::buffer_atomic_add_x2
;
5999 case nir_intrinsic_ssbo_atomic_imin
:
6000 op32
= aco_opcode::buffer_atomic_smin
;
6001 op64
= aco_opcode::buffer_atomic_smin_x2
;
6003 case nir_intrinsic_ssbo_atomic_umin
:
6004 op32
= aco_opcode::buffer_atomic_umin
;
6005 op64
= aco_opcode::buffer_atomic_umin_x2
;
6007 case nir_intrinsic_ssbo_atomic_imax
:
6008 op32
= aco_opcode::buffer_atomic_smax
;
6009 op64
= aco_opcode::buffer_atomic_smax_x2
;
6011 case nir_intrinsic_ssbo_atomic_umax
:
6012 op32
= aco_opcode::buffer_atomic_umax
;
6013 op64
= aco_opcode::buffer_atomic_umax_x2
;
6015 case nir_intrinsic_ssbo_atomic_and
:
6016 op32
= aco_opcode::buffer_atomic_and
;
6017 op64
= aco_opcode::buffer_atomic_and_x2
;
6019 case nir_intrinsic_ssbo_atomic_or
:
6020 op32
= aco_opcode::buffer_atomic_or
;
6021 op64
= aco_opcode::buffer_atomic_or_x2
;
6023 case nir_intrinsic_ssbo_atomic_xor
:
6024 op32
= aco_opcode::buffer_atomic_xor
;
6025 op64
= aco_opcode::buffer_atomic_xor_x2
;
6027 case nir_intrinsic_ssbo_atomic_exchange
:
6028 op32
= aco_opcode::buffer_atomic_swap
;
6029 op64
= aco_opcode::buffer_atomic_swap_x2
;
6031 case nir_intrinsic_ssbo_atomic_comp_swap
:
6032 op32
= aco_opcode::buffer_atomic_cmpswap
;
6033 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6036 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6038 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6039 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6040 mubuf
->operands
[0] = Operand(rsrc
);
6041 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6042 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6043 mubuf
->operands
[3] = Operand(data
);
6044 if (return_previous
)
6045 mubuf
->definitions
[0] = Definition(dst
);
6047 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6048 mubuf
->glc
= return_previous
;
6049 mubuf
->dlc
= false; /* Not needed for atomics */
6050 mubuf
->disable_wqm
= true;
6051 mubuf
->barrier
= barrier_buffer
;
6052 ctx
->program
->needs_exact
= true;
6053 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6056 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6058 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6059 Builder
bld(ctx
->program
, ctx
->block
);
6060 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6061 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6064 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6066 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6067 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6069 if (addr
.type() == RegType::vgpr
)
6070 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6071 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6074 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6076 Builder
bld(ctx
->program
, ctx
->block
);
6077 unsigned num_components
= instr
->num_components
;
6078 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6080 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6081 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6083 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6084 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6086 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6087 bool global
= ctx
->options
->chip_class
>= GFX9
;
6089 if (ctx
->options
->chip_class
>= GFX7
) {
6091 switch (num_bytes
) {
6093 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6096 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6099 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6102 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6105 unreachable("load_global not implemented for this size.");
6108 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6109 flat
->operands
[0] = Operand(addr
);
6110 flat
->operands
[1] = Operand(s1
);
6113 flat
->barrier
= barrier_buffer
;
6115 if (dst
.type() == RegType::sgpr
) {
6116 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6117 flat
->definitions
[0] = Definition(vec
);
6118 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6119 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6121 flat
->definitions
[0] = Definition(dst
);
6122 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6124 emit_split_vector(ctx
, dst
, num_components
);
6126 assert(ctx
->options
->chip_class
== GFX6
);
6128 /* GFX6 doesn't support loading vec3, expand to vec4. */
6129 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6132 switch (num_bytes
) {
6134 op
= aco_opcode::buffer_load_dword
;
6137 op
= aco_opcode::buffer_load_dwordx2
;
6140 op
= aco_opcode::buffer_load_dwordx4
;
6143 unreachable("load_global not implemented for this size.");
6146 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6148 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6149 mubuf
->operands
[0] = Operand(rsrc
);
6150 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6151 mubuf
->operands
[2] = Operand(0u);
6155 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6156 mubuf
->disable_wqm
= false;
6157 mubuf
->barrier
= barrier_buffer
;
6158 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6161 if (dst
.size() == 3) {
6162 Temp vec
= bld
.tmp(v4
);
6163 instr
->definitions
[0] = Definition(vec
);
6164 bld
.insert(std::move(instr
));
6165 emit_split_vector(ctx
, vec
, 4);
6167 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6168 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6169 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6170 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6173 if (dst
.type() == RegType::sgpr
) {
6174 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6175 instr
->definitions
[0] = Definition(vec
);
6176 bld
.insert(std::move(instr
));
6177 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6178 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6180 instr
->definitions
[0] = Definition(dst
);
6181 bld
.insert(std::move(instr
));
6182 emit_split_vector(ctx
, dst
, num_components
);
6186 switch (num_bytes
) {
6188 op
= aco_opcode::s_load_dword
;
6191 op
= aco_opcode::s_load_dwordx2
;
6195 op
= aco_opcode::s_load_dwordx4
;
6198 unreachable("load_global not implemented for this size.");
6200 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6201 load
->operands
[0] = Operand(addr
);
6202 load
->operands
[1] = Operand(0u);
6203 load
->definitions
[0] = Definition(dst
);
6206 load
->barrier
= barrier_buffer
;
6207 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6209 if (dst
.size() == 3) {
6211 Temp vec
= bld
.tmp(s4
);
6212 load
->definitions
[0] = Definition(vec
);
6213 ctx
->block
->instructions
.emplace_back(std::move(load
));
6214 emit_split_vector(ctx
, vec
, 4);
6216 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6217 emit_extract_vector(ctx
, vec
, 0, s1
),
6218 emit_extract_vector(ctx
, vec
, 1, s1
),
6219 emit_extract_vector(ctx
, vec
, 2, s1
));
6221 ctx
->block
->instructions
.emplace_back(std::move(load
));
6226 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6228 Builder
bld(ctx
->program
, ctx
->block
);
6229 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6231 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6232 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6234 if (ctx
->options
->chip_class
>= GFX7
)
6235 addr
= as_vgpr(ctx
, addr
);
6237 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6240 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6241 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6242 /* GFX6 doesn't support storing vec3, split it. */
6243 writemask
|= 1u << (start
+ 2);
6246 unsigned num_bytes
= count
* elem_size_bytes
;
6248 Temp write_data
= data
;
6249 if (count
!= instr
->num_components
) {
6250 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6251 for (int i
= 0; i
< count
; i
++)
6252 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6253 write_data
= bld
.tmp(RegType::vgpr
, count
);
6254 vec
->definitions
[0] = Definition(write_data
);
6255 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6258 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6259 unsigned offset
= start
* elem_size_bytes
;
6261 if (ctx
->options
->chip_class
>= GFX7
) {
6262 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6263 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6264 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6265 Temp carry
= bld
.tmp(bld
.lm
);
6266 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6268 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6269 Operand(offset
), addr0
);
6270 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6272 carry
).def(1).setHint(vcc
);
6274 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6279 bool global
= ctx
->options
->chip_class
>= GFX9
;
6281 switch (num_bytes
) {
6283 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6286 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6289 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6292 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6295 unreachable("store_global not implemented for this size.");
6298 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6299 flat
->operands
[0] = Operand(addr
);
6300 flat
->operands
[1] = Operand(s1
);
6301 flat
->operands
[2] = Operand(data
);
6304 flat
->offset
= offset
;
6305 flat
->disable_wqm
= true;
6306 flat
->barrier
= barrier_buffer
;
6307 ctx
->program
->needs_exact
= true;
6308 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6310 assert(ctx
->options
->chip_class
== GFX6
);
6313 switch (num_bytes
) {
6315 op
= aco_opcode::buffer_store_dword
;
6318 op
= aco_opcode::buffer_store_dwordx2
;
6321 op
= aco_opcode::buffer_store_dwordx4
;
6324 unreachable("store_global not implemented for this size.");
6327 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6329 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6330 mubuf
->operands
[0] = Operand(rsrc
);
6331 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6332 mubuf
->operands
[2] = Operand(0u);
6333 mubuf
->operands
[3] = Operand(write_data
);
6336 mubuf
->offset
= offset
;
6337 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6338 mubuf
->disable_wqm
= true;
6339 mubuf
->barrier
= barrier_buffer
;
6340 ctx
->program
->needs_exact
= true;
6341 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6346 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6348 /* return the previous value if dest is ever used */
6349 bool return_previous
= false;
6350 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6351 return_previous
= true;
6354 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6355 return_previous
= true;
6359 Builder
bld(ctx
->program
, ctx
->block
);
6360 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6361 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6363 if (ctx
->options
->chip_class
>= GFX7
)
6364 addr
= as_vgpr(ctx
, addr
);
6366 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6367 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6368 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6370 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6372 aco_opcode op32
, op64
;
6374 if (ctx
->options
->chip_class
>= GFX7
) {
6375 bool global
= ctx
->options
->chip_class
>= GFX9
;
6376 switch (instr
->intrinsic
) {
6377 case nir_intrinsic_global_atomic_add
:
6378 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6379 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6381 case nir_intrinsic_global_atomic_imin
:
6382 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6383 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6385 case nir_intrinsic_global_atomic_umin
:
6386 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6387 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6389 case nir_intrinsic_global_atomic_imax
:
6390 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6391 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6393 case nir_intrinsic_global_atomic_umax
:
6394 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6395 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6397 case nir_intrinsic_global_atomic_and
:
6398 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6399 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6401 case nir_intrinsic_global_atomic_or
:
6402 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6403 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6405 case nir_intrinsic_global_atomic_xor
:
6406 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6407 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6409 case nir_intrinsic_global_atomic_exchange
:
6410 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6411 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6413 case nir_intrinsic_global_atomic_comp_swap
:
6414 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6415 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6418 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6421 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6422 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6423 flat
->operands
[0] = Operand(addr
);
6424 flat
->operands
[1] = Operand(s1
);
6425 flat
->operands
[2] = Operand(data
);
6426 if (return_previous
)
6427 flat
->definitions
[0] = Definition(dst
);
6428 flat
->glc
= return_previous
;
6429 flat
->dlc
= false; /* Not needed for atomics */
6431 flat
->disable_wqm
= true;
6432 flat
->barrier
= barrier_buffer
;
6433 ctx
->program
->needs_exact
= true;
6434 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6436 assert(ctx
->options
->chip_class
== GFX6
);
6438 switch (instr
->intrinsic
) {
6439 case nir_intrinsic_global_atomic_add
:
6440 op32
= aco_opcode::buffer_atomic_add
;
6441 op64
= aco_opcode::buffer_atomic_add_x2
;
6443 case nir_intrinsic_global_atomic_imin
:
6444 op32
= aco_opcode::buffer_atomic_smin
;
6445 op64
= aco_opcode::buffer_atomic_smin_x2
;
6447 case nir_intrinsic_global_atomic_umin
:
6448 op32
= aco_opcode::buffer_atomic_umin
;
6449 op64
= aco_opcode::buffer_atomic_umin_x2
;
6451 case nir_intrinsic_global_atomic_imax
:
6452 op32
= aco_opcode::buffer_atomic_smax
;
6453 op64
= aco_opcode::buffer_atomic_smax_x2
;
6455 case nir_intrinsic_global_atomic_umax
:
6456 op32
= aco_opcode::buffer_atomic_umax
;
6457 op64
= aco_opcode::buffer_atomic_umax_x2
;
6459 case nir_intrinsic_global_atomic_and
:
6460 op32
= aco_opcode::buffer_atomic_and
;
6461 op64
= aco_opcode::buffer_atomic_and_x2
;
6463 case nir_intrinsic_global_atomic_or
:
6464 op32
= aco_opcode::buffer_atomic_or
;
6465 op64
= aco_opcode::buffer_atomic_or_x2
;
6467 case nir_intrinsic_global_atomic_xor
:
6468 op32
= aco_opcode::buffer_atomic_xor
;
6469 op64
= aco_opcode::buffer_atomic_xor_x2
;
6471 case nir_intrinsic_global_atomic_exchange
:
6472 op32
= aco_opcode::buffer_atomic_swap
;
6473 op64
= aco_opcode::buffer_atomic_swap_x2
;
6475 case nir_intrinsic_global_atomic_comp_swap
:
6476 op32
= aco_opcode::buffer_atomic_cmpswap
;
6477 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6480 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6483 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6485 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6487 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6488 mubuf
->operands
[0] = Operand(rsrc
);
6489 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6490 mubuf
->operands
[2] = Operand(0u);
6491 mubuf
->operands
[3] = Operand(data
);
6492 if (return_previous
)
6493 mubuf
->definitions
[0] = Definition(dst
);
6494 mubuf
->glc
= return_previous
;
6497 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6498 mubuf
->disable_wqm
= true;
6499 mubuf
->barrier
= barrier_buffer
;
6500 ctx
->program
->needs_exact
= true;
6501 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6505 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6506 Builder
bld(ctx
->program
, ctx
->block
);
6507 switch(instr
->intrinsic
) {
6508 case nir_intrinsic_group_memory_barrier
:
6509 case nir_intrinsic_memory_barrier
:
6510 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6512 case nir_intrinsic_memory_barrier_buffer
:
6513 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6515 case nir_intrinsic_memory_barrier_image
:
6516 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6518 case nir_intrinsic_memory_barrier_tcs_patch
:
6519 case nir_intrinsic_memory_barrier_shared
:
6520 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6523 unreachable("Unimplemented memory barrier intrinsic");
6528 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6530 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6531 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6532 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6533 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6534 Builder
bld(ctx
->program
, ctx
->block
);
6536 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6537 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6538 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6541 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6543 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6544 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6545 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6546 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6547 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6549 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6550 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6553 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6555 unsigned offset
= nir_intrinsic_base(instr
);
6556 Operand m
= load_lds_size_m0(ctx
);
6557 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6558 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6560 unsigned num_operands
= 3;
6561 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6562 switch(instr
->intrinsic
) {
6563 case nir_intrinsic_shared_atomic_add
:
6564 op32
= aco_opcode::ds_add_u32
;
6565 op64
= aco_opcode::ds_add_u64
;
6566 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6567 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6569 case nir_intrinsic_shared_atomic_imin
:
6570 op32
= aco_opcode::ds_min_i32
;
6571 op64
= aco_opcode::ds_min_i64
;
6572 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6573 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6575 case nir_intrinsic_shared_atomic_umin
:
6576 op32
= aco_opcode::ds_min_u32
;
6577 op64
= aco_opcode::ds_min_u64
;
6578 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6579 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6581 case nir_intrinsic_shared_atomic_imax
:
6582 op32
= aco_opcode::ds_max_i32
;
6583 op64
= aco_opcode::ds_max_i64
;
6584 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6585 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6587 case nir_intrinsic_shared_atomic_umax
:
6588 op32
= aco_opcode::ds_max_u32
;
6589 op64
= aco_opcode::ds_max_u64
;
6590 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6591 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6593 case nir_intrinsic_shared_atomic_and
:
6594 op32
= aco_opcode::ds_and_b32
;
6595 op64
= aco_opcode::ds_and_b64
;
6596 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6597 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6599 case nir_intrinsic_shared_atomic_or
:
6600 op32
= aco_opcode::ds_or_b32
;
6601 op64
= aco_opcode::ds_or_b64
;
6602 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6603 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6605 case nir_intrinsic_shared_atomic_xor
:
6606 op32
= aco_opcode::ds_xor_b32
;
6607 op64
= aco_opcode::ds_xor_b64
;
6608 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6609 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6611 case nir_intrinsic_shared_atomic_exchange
:
6612 op32
= aco_opcode::ds_write_b32
;
6613 op64
= aco_opcode::ds_write_b64
;
6614 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6615 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6617 case nir_intrinsic_shared_atomic_comp_swap
:
6618 op32
= aco_opcode::ds_cmpst_b32
;
6619 op64
= aco_opcode::ds_cmpst_b64
;
6620 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6621 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6625 unreachable("Unhandled shared atomic intrinsic");
6628 /* return the previous value if dest is ever used */
6629 bool return_previous
= false;
6630 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6631 return_previous
= true;
6634 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6635 return_previous
= true;
6640 if (data
.size() == 1) {
6641 assert(instr
->dest
.ssa
.bit_size
== 32);
6642 op
= return_previous
? op32_rtn
: op32
;
6644 assert(instr
->dest
.ssa
.bit_size
== 64);
6645 op
= return_previous
? op64_rtn
: op64
;
6648 if (offset
> 65535) {
6649 Builder
bld(ctx
->program
, ctx
->block
);
6650 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6654 aco_ptr
<DS_instruction
> ds
;
6655 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6656 ds
->operands
[0] = Operand(address
);
6657 ds
->operands
[1] = Operand(data
);
6658 if (num_operands
== 4)
6659 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6660 ds
->operands
[num_operands
- 1] = m
;
6661 ds
->offset0
= offset
;
6662 if (return_previous
)
6663 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6664 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6667 Temp
get_scratch_resource(isel_context
*ctx
)
6669 Builder
bld(ctx
->program
, ctx
->block
);
6670 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6671 if (ctx
->stage
!= compute_cs
)
6672 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6674 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6675 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6677 if (ctx
->program
->chip_class
>= GFX10
) {
6678 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6679 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6680 S_008F0C_RESOURCE_LEVEL(1);
6681 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6682 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6683 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6686 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6687 if (ctx
->program
->chip_class
<= GFX8
)
6688 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6690 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6693 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6694 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6695 Builder
bld(ctx
->program
, ctx
->block
);
6696 Temp rsrc
= get_scratch_resource(ctx
);
6697 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6698 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6701 switch (dst
.size()) {
6703 op
= aco_opcode::buffer_load_dword
;
6706 op
= aco_opcode::buffer_load_dwordx2
;
6709 op
= aco_opcode::buffer_load_dwordx3
;
6712 op
= aco_opcode::buffer_load_dwordx4
;
6716 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6717 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6718 bld
.def(v4
), rsrc
, offset
,
6719 ctx
->program
->scratch_offset
, 0, true);
6720 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6721 aco_opcode::buffer_load_dwordx4
,
6722 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6723 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6724 emit_split_vector(ctx
, lower
, 2);
6725 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6726 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6727 if (dst
.size() == 8) {
6728 emit_split_vector(ctx
, upper
, 2);
6729 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6730 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6735 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6736 Format::PSEUDO
, dst
.size() / 2, 1)};
6737 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6738 vec
->operands
[i
] = Operand(elems
[i
]);
6739 vec
->definitions
[0] = Definition(dst
);
6740 bld
.insert(std::move(vec
));
6741 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6745 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6748 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6749 emit_split_vector(ctx
, dst
, instr
->num_components
);
6752 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6753 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6754 Builder
bld(ctx
->program
, ctx
->block
);
6755 Temp rsrc
= get_scratch_resource(ctx
);
6756 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6757 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6759 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6760 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6764 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6765 int num_bytes
= count
* elem_size_bytes
;
6767 if (num_bytes
> 16) {
6768 assert(elem_size_bytes
== 8);
6769 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6774 // TODO: check alignment of sub-dword stores
6775 // TODO: split 3 bytes. there is no store instruction for that
6778 if (count
!= instr
->num_components
) {
6779 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6780 for (int i
= 0; i
< count
; i
++) {
6781 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6782 vec
->operands
[i
] = Operand(elem
);
6784 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6785 vec
->definitions
[0] = Definition(write_data
);
6786 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6792 switch (num_bytes
) {
6794 op
= aco_opcode::buffer_store_dword
;
6797 op
= aco_opcode::buffer_store_dwordx2
;
6800 op
= aco_opcode::buffer_store_dwordx3
;
6803 op
= aco_opcode::buffer_store_dwordx4
;
6806 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6809 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6813 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6814 uint8_t log2_ps_iter_samples
;
6815 if (ctx
->program
->info
->ps
.force_persample
) {
6816 log2_ps_iter_samples
=
6817 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6819 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6822 /* The bit pattern matches that used by fixed function fragment
6824 static const unsigned ps_iter_masks
[] = {
6825 0xffff, /* not used */
6831 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6833 Builder
bld(ctx
->program
, ctx
->block
);
6835 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6836 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6837 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6838 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6839 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6840 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6843 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6844 Builder
bld(ctx
->program
, ctx
->block
);
6846 unsigned stream
= nir_intrinsic_stream_id(instr
);
6847 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6848 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6849 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6852 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6854 unsigned num_components
=
6855 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6856 assert(num_components
);
6858 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6859 unsigned stream_offset
= 0;
6860 for (unsigned i
= 0; i
< stream
; i
++) {
6861 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6862 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6865 /* Limit on the stride field for <= GFX7. */
6866 assert(stride
< (1 << 14));
6868 Temp gsvs_dwords
[4];
6869 for (unsigned i
= 0; i
< 4; i
++)
6870 gsvs_dwords
[i
] = bld
.tmp(s1
);
6871 bld
.pseudo(aco_opcode::p_split_vector
,
6872 Definition(gsvs_dwords
[0]),
6873 Definition(gsvs_dwords
[1]),
6874 Definition(gsvs_dwords
[2]),
6875 Definition(gsvs_dwords
[3]),
6878 if (stream_offset
) {
6879 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6881 Temp carry
= bld
.tmp(s1
);
6882 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6883 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6886 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6887 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6889 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6890 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6892 unsigned offset
= 0;
6893 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6894 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6897 for (unsigned j
= 0; j
< 4; j
++) {
6898 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6901 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6902 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6903 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6904 if (const_offset
>= 4096u) {
6905 if (vaddr_offset
.isUndefined())
6906 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6908 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6909 const_offset
%= 4096u;
6912 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6913 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6914 mtbuf
->operands
[1] = vaddr_offset
;
6915 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6916 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6917 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6918 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6919 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6920 mtbuf
->offset
= const_offset
;
6923 mtbuf
->barrier
= barrier_gs_data
;
6924 mtbuf
->can_reorder
= true;
6925 bld
.insert(std::move(mtbuf
));
6928 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6931 /* outputs for the next vertex are undefined and keeping them around can
6932 * create invalid IR with control flow */
6933 ctx
->outputs
.mask
[i
] = 0;
6936 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6939 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6941 Builder
bld(ctx
->program
, ctx
->block
);
6943 if (cluster_size
== 1) {
6945 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6946 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6947 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6948 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6949 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6950 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6951 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6952 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6953 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6954 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6955 //subgroupAnd(val) -> (exec & ~val) == 0
6956 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6957 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6958 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6959 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6960 //subgroupOr(val) -> (val & exec) != 0
6961 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6962 return bool_to_vector_condition(ctx
, tmp
);
6963 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6964 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6965 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6966 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6967 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6968 return bool_to_vector_condition(ctx
, tmp
);
6970 //subgroupClustered{And,Or,Xor}(val, n) ->
6971 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6972 //cluster_offset = ~(n - 1) & lane_id
6973 //cluster_mask = ((1 << n) - 1)
6974 //subgroupClusteredAnd():
6975 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6976 //subgroupClusteredOr():
6977 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6978 //subgroupClusteredXor():
6979 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6980 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6981 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6984 if (op
== nir_op_iand
)
6985 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6987 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6989 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6991 if (ctx
->program
->chip_class
<= GFX7
)
6992 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6993 else if (ctx
->program
->wave_size
== 64)
6994 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6996 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6997 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6998 if (cluster_mask
!= 0xffffffff)
6999 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7001 Definition cmp_def
= Definition();
7002 if (op
== nir_op_iand
) {
7003 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7004 } else if (op
== nir_op_ior
) {
7005 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7006 } else if (op
== nir_op_ixor
) {
7007 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7008 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7009 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7011 cmp_def
.setHint(vcc
);
7012 return cmp_def
.getTemp();
7016 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7018 Builder
bld(ctx
->program
, ctx
->block
);
7020 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7021 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7022 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7024 if (op
== nir_op_iand
)
7025 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7027 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7029 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7030 Temp lo
= lohi
.def(0).getTemp();
7031 Temp hi
= lohi
.def(1).getTemp();
7032 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7034 Definition cmp_def
= Definition();
7035 if (op
== nir_op_iand
)
7036 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7037 else if (op
== nir_op_ior
)
7038 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7039 else if (op
== nir_op_ixor
)
7040 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7041 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7042 cmp_def
.setHint(vcc
);
7043 return cmp_def
.getTemp();
7046 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7048 Builder
bld(ctx
->program
, ctx
->block
);
7050 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7051 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7052 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7053 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7054 if (op
== nir_op_iand
)
7055 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7056 else if (op
== nir_op_ior
)
7057 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7058 else if (op
== nir_op_ixor
)
7059 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7065 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7067 Builder
bld(ctx
->program
, ctx
->block
);
7068 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7069 if (src
.regClass().type() == RegType::vgpr
) {
7070 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7071 } else if (src
.regClass() == s1
) {
7072 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7073 } else if (src
.regClass() == s2
) {
7074 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7076 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7077 nir_print_instr(&instr
->instr
, stderr
);
7078 fprintf(stderr
, "\n");
7082 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7084 Builder
bld(ctx
->program
, ctx
->block
);
7085 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7086 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7087 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7089 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7090 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7091 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7092 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7095 if (ctx
->program
->chip_class
>= GFX8
) {
7096 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7097 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7098 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7099 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7100 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7101 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7103 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7104 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7105 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7106 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7107 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7108 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7109 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7110 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7111 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7112 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7115 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7116 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7117 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7118 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7119 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7120 Temp wqm1
= bld
.tmp(v1
);
7121 emit_wqm(ctx
, tmp1
, wqm1
, true);
7122 Temp wqm2
= bld
.tmp(v1
);
7123 emit_wqm(ctx
, tmp2
, wqm2
, true);
7124 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7128 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7130 Builder
bld(ctx
->program
, ctx
->block
);
7131 switch(instr
->intrinsic
) {
7132 case nir_intrinsic_load_barycentric_sample
:
7133 case nir_intrinsic_load_barycentric_pixel
:
7134 case nir_intrinsic_load_barycentric_centroid
: {
7135 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7136 Temp bary
= Temp(0, s2
);
7138 case INTERP_MODE_SMOOTH
:
7139 case INTERP_MODE_NONE
:
7140 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7141 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7142 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7143 bary
= ctx
->persp_centroid
;
7144 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7145 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7147 case INTERP_MODE_NOPERSPECTIVE
:
7148 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7149 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7150 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7151 bary
= ctx
->linear_centroid
;
7152 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7153 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7158 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7159 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7160 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7161 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7162 Operand(p1
), Operand(p2
));
7163 emit_split_vector(ctx
, dst
, 2);
7166 case nir_intrinsic_load_barycentric_model
: {
7167 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7169 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7170 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7171 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7172 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7173 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7174 Operand(p1
), Operand(p2
), Operand(p3
));
7175 emit_split_vector(ctx
, dst
, 3);
7178 case nir_intrinsic_load_barycentric_at_sample
: {
7179 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7180 switch (ctx
->options
->key
.fs
.num_samples
) {
7181 case 2: sample_pos_offset
+= 1 << 3; break;
7182 case 4: sample_pos_offset
+= 3 << 3; break;
7183 case 8: sample_pos_offset
+= 7 << 3; break;
7187 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7188 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7189 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7190 if (addr
.type() == RegType::sgpr
) {
7193 sample_pos_offset
+= const_addr
->u32
<< 3;
7194 offset
= Operand(sample_pos_offset
);
7195 } else if (ctx
->options
->chip_class
>= GFX9
) {
7196 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7198 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7199 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7202 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7203 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7205 } else if (ctx
->options
->chip_class
>= GFX9
) {
7206 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7207 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7208 } else if (ctx
->options
->chip_class
>= GFX7
) {
7209 /* addr += private_segment_buffer + sample_pos_offset */
7210 Temp tmp0
= bld
.tmp(s1
);
7211 Temp tmp1
= bld
.tmp(s1
);
7212 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7213 Definition scc_tmp
= bld
.def(s1
, scc
);
7214 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7215 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7216 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7217 Temp pck0
= bld
.tmp(v1
);
7218 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7219 tmp1
= as_vgpr(ctx
, tmp1
);
7220 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7221 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7223 /* sample_pos = flat_load_dwordx2 addr */
7224 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7226 assert(ctx
->options
->chip_class
== GFX6
);
7228 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7229 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7230 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7232 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7233 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7235 sample_pos
= bld
.tmp(v2
);
7237 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7238 load
->definitions
[0] = Definition(sample_pos
);
7239 load
->operands
[0] = Operand(rsrc
);
7240 load
->operands
[1] = Operand(addr
);
7241 load
->operands
[2] = Operand(0u);
7242 load
->offset
= sample_pos_offset
;
7244 load
->addr64
= true;
7247 load
->disable_wqm
= false;
7248 load
->barrier
= barrier_none
;
7249 load
->can_reorder
= true;
7250 ctx
->block
->instructions
.emplace_back(std::move(load
));
7253 /* sample_pos -= 0.5 */
7254 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7255 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7256 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7257 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7258 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7260 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7263 case nir_intrinsic_load_barycentric_at_offset
: {
7264 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7265 RegClass rc
= RegClass(offset
.type(), 1);
7266 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7267 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7268 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7271 case nir_intrinsic_load_front_face
: {
7272 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7273 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7276 case nir_intrinsic_load_view_index
: {
7277 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7278 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7279 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7285 case nir_intrinsic_load_layer_id
: {
7286 unsigned idx
= nir_intrinsic_base(instr
);
7287 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7288 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7291 case nir_intrinsic_load_frag_coord
: {
7292 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7295 case nir_intrinsic_load_sample_pos
: {
7296 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7297 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7298 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7299 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7300 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7303 case nir_intrinsic_load_tess_coord
:
7304 visit_load_tess_coord(ctx
, instr
);
7306 case nir_intrinsic_load_interpolated_input
:
7307 visit_load_interpolated_input(ctx
, instr
);
7309 case nir_intrinsic_store_output
:
7310 visit_store_output(ctx
, instr
);
7312 case nir_intrinsic_load_input
:
7313 case nir_intrinsic_load_input_vertex
:
7314 visit_load_input(ctx
, instr
);
7316 case nir_intrinsic_load_output
:
7317 visit_load_output(ctx
, instr
);
7319 case nir_intrinsic_load_per_vertex_input
:
7320 visit_load_per_vertex_input(ctx
, instr
);
7322 case nir_intrinsic_load_per_vertex_output
:
7323 visit_load_per_vertex_output(ctx
, instr
);
7325 case nir_intrinsic_store_per_vertex_output
:
7326 visit_store_per_vertex_output(ctx
, instr
);
7328 case nir_intrinsic_load_ubo
:
7329 visit_load_ubo(ctx
, instr
);
7331 case nir_intrinsic_load_push_constant
:
7332 visit_load_push_constant(ctx
, instr
);
7334 case nir_intrinsic_load_constant
:
7335 visit_load_constant(ctx
, instr
);
7337 case nir_intrinsic_vulkan_resource_index
:
7338 visit_load_resource(ctx
, instr
);
7340 case nir_intrinsic_discard
:
7341 visit_discard(ctx
, instr
);
7343 case nir_intrinsic_discard_if
:
7344 visit_discard_if(ctx
, instr
);
7346 case nir_intrinsic_load_shared
:
7347 visit_load_shared(ctx
, instr
);
7349 case nir_intrinsic_store_shared
:
7350 visit_store_shared(ctx
, instr
);
7352 case nir_intrinsic_shared_atomic_add
:
7353 case nir_intrinsic_shared_atomic_imin
:
7354 case nir_intrinsic_shared_atomic_umin
:
7355 case nir_intrinsic_shared_atomic_imax
:
7356 case nir_intrinsic_shared_atomic_umax
:
7357 case nir_intrinsic_shared_atomic_and
:
7358 case nir_intrinsic_shared_atomic_or
:
7359 case nir_intrinsic_shared_atomic_xor
:
7360 case nir_intrinsic_shared_atomic_exchange
:
7361 case nir_intrinsic_shared_atomic_comp_swap
:
7362 visit_shared_atomic(ctx
, instr
);
7364 case nir_intrinsic_image_deref_load
:
7365 visit_image_load(ctx
, instr
);
7367 case nir_intrinsic_image_deref_store
:
7368 visit_image_store(ctx
, instr
);
7370 case nir_intrinsic_image_deref_atomic_add
:
7371 case nir_intrinsic_image_deref_atomic_umin
:
7372 case nir_intrinsic_image_deref_atomic_imin
:
7373 case nir_intrinsic_image_deref_atomic_umax
:
7374 case nir_intrinsic_image_deref_atomic_imax
:
7375 case nir_intrinsic_image_deref_atomic_and
:
7376 case nir_intrinsic_image_deref_atomic_or
:
7377 case nir_intrinsic_image_deref_atomic_xor
:
7378 case nir_intrinsic_image_deref_atomic_exchange
:
7379 case nir_intrinsic_image_deref_atomic_comp_swap
:
7380 visit_image_atomic(ctx
, instr
);
7382 case nir_intrinsic_image_deref_size
:
7383 visit_image_size(ctx
, instr
);
7385 case nir_intrinsic_load_ssbo
:
7386 visit_load_ssbo(ctx
, instr
);
7388 case nir_intrinsic_store_ssbo
:
7389 visit_store_ssbo(ctx
, instr
);
7391 case nir_intrinsic_load_global
:
7392 visit_load_global(ctx
, instr
);
7394 case nir_intrinsic_store_global
:
7395 visit_store_global(ctx
, instr
);
7397 case nir_intrinsic_global_atomic_add
:
7398 case nir_intrinsic_global_atomic_imin
:
7399 case nir_intrinsic_global_atomic_umin
:
7400 case nir_intrinsic_global_atomic_imax
:
7401 case nir_intrinsic_global_atomic_umax
:
7402 case nir_intrinsic_global_atomic_and
:
7403 case nir_intrinsic_global_atomic_or
:
7404 case nir_intrinsic_global_atomic_xor
:
7405 case nir_intrinsic_global_atomic_exchange
:
7406 case nir_intrinsic_global_atomic_comp_swap
:
7407 visit_global_atomic(ctx
, instr
);
7409 case nir_intrinsic_ssbo_atomic_add
:
7410 case nir_intrinsic_ssbo_atomic_imin
:
7411 case nir_intrinsic_ssbo_atomic_umin
:
7412 case nir_intrinsic_ssbo_atomic_imax
:
7413 case nir_intrinsic_ssbo_atomic_umax
:
7414 case nir_intrinsic_ssbo_atomic_and
:
7415 case nir_intrinsic_ssbo_atomic_or
:
7416 case nir_intrinsic_ssbo_atomic_xor
:
7417 case nir_intrinsic_ssbo_atomic_exchange
:
7418 case nir_intrinsic_ssbo_atomic_comp_swap
:
7419 visit_atomic_ssbo(ctx
, instr
);
7421 case nir_intrinsic_load_scratch
:
7422 visit_load_scratch(ctx
, instr
);
7424 case nir_intrinsic_store_scratch
:
7425 visit_store_scratch(ctx
, instr
);
7427 case nir_intrinsic_get_buffer_size
:
7428 visit_get_buffer_size(ctx
, instr
);
7430 case nir_intrinsic_control_barrier
: {
7431 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7432 /* GFX6 only (thanks to a hw bug workaround):
7433 * The real barrier instruction isn’t needed, because an entire patch
7434 * always fits into a single wave.
7439 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7440 bld
.sopp(aco_opcode::s_barrier
);
7444 case nir_intrinsic_memory_barrier_tcs_patch
:
7445 case nir_intrinsic_group_memory_barrier
:
7446 case nir_intrinsic_memory_barrier
:
7447 case nir_intrinsic_memory_barrier_buffer
:
7448 case nir_intrinsic_memory_barrier_image
:
7449 case nir_intrinsic_memory_barrier_shared
:
7450 emit_memory_barrier(ctx
, instr
);
7452 case nir_intrinsic_load_num_work_groups
: {
7453 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7454 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7455 emit_split_vector(ctx
, dst
, 3);
7458 case nir_intrinsic_load_local_invocation_id
: {
7459 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7460 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7461 emit_split_vector(ctx
, dst
, 3);
7464 case nir_intrinsic_load_work_group_id
: {
7465 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7466 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7467 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7468 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7469 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7470 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7471 emit_split_vector(ctx
, dst
, 3);
7474 case nir_intrinsic_load_local_invocation_index
: {
7475 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7477 /* The tg_size bits [6:11] contain the subgroup id,
7478 * we need this multiplied by the wave size, and then OR the thread id to it.
7480 if (ctx
->program
->wave_size
== 64) {
7481 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7482 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7483 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7484 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7486 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7487 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7488 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7489 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7493 case nir_intrinsic_load_subgroup_id
: {
7494 if (ctx
->stage
== compute_cs
) {
7495 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7496 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7498 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7502 case nir_intrinsic_load_subgroup_invocation
: {
7503 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7506 case nir_intrinsic_load_num_subgroups
: {
7507 if (ctx
->stage
== compute_cs
)
7508 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7509 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7511 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7514 case nir_intrinsic_ballot
: {
7515 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7516 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7517 Definition tmp
= bld
.def(dst
.regClass());
7518 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7519 if (instr
->src
[0].ssa
->bit_size
== 1) {
7520 assert(src
.regClass() == bld
.lm
);
7521 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7522 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7523 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7524 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7525 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7527 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7528 nir_print_instr(&instr
->instr
, stderr
);
7529 fprintf(stderr
, "\n");
7531 if (dst
.size() != bld
.lm
.size()) {
7532 /* Wave32 with ballot size set to 64 */
7533 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7535 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7538 case nir_intrinsic_shuffle
:
7539 case nir_intrinsic_read_invocation
: {
7540 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7541 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7542 emit_uniform_subgroup(ctx
, instr
, src
);
7544 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7545 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7546 tid
= bld
.as_uniform(tid
);
7547 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7548 if (src
.regClass() == v1
) {
7549 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7550 } else if (src
.regClass() == v2
) {
7551 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7552 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7553 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7554 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7555 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7556 emit_split_vector(ctx
, dst
, 2);
7557 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7558 assert(src
.regClass() == bld
.lm
);
7559 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7560 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7561 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7562 assert(src
.regClass() == bld
.lm
);
7564 if (ctx
->program
->chip_class
<= GFX7
)
7565 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7566 else if (ctx
->program
->wave_size
== 64)
7567 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7569 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7570 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7571 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7572 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7574 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7575 nir_print_instr(&instr
->instr
, stderr
);
7576 fprintf(stderr
, "\n");
7581 case nir_intrinsic_load_sample_id
: {
7582 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7583 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7586 case nir_intrinsic_load_sample_mask_in
: {
7587 visit_load_sample_mask_in(ctx
, instr
);
7590 case nir_intrinsic_read_first_invocation
: {
7591 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7592 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7593 if (src
.regClass() == v1
) {
7595 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7597 } else if (src
.regClass() == v2
) {
7598 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7599 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7600 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7601 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7602 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7603 emit_split_vector(ctx
, dst
, 2);
7604 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7605 assert(src
.regClass() == bld
.lm
);
7606 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7607 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7608 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7609 } else if (src
.regClass() == s1
) {
7610 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7611 } else if (src
.regClass() == s2
) {
7612 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7614 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7615 nir_print_instr(&instr
->instr
, stderr
);
7616 fprintf(stderr
, "\n");
7620 case nir_intrinsic_vote_all
: {
7621 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7622 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7623 assert(src
.regClass() == bld
.lm
);
7624 assert(dst
.regClass() == bld
.lm
);
7626 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7627 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7628 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7631 case nir_intrinsic_vote_any
: {
7632 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7633 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7634 assert(src
.regClass() == bld
.lm
);
7635 assert(dst
.regClass() == bld
.lm
);
7637 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7638 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7641 case nir_intrinsic_reduce
:
7642 case nir_intrinsic_inclusive_scan
:
7643 case nir_intrinsic_exclusive_scan
: {
7644 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7645 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7646 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7647 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7648 nir_intrinsic_cluster_size(instr
) : 0;
7649 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7651 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7652 emit_uniform_subgroup(ctx
, instr
, src
);
7653 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7654 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7656 else if (op
== nir_op_iadd
)
7658 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7660 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7662 switch (instr
->intrinsic
) {
7663 case nir_intrinsic_reduce
:
7664 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7666 case nir_intrinsic_exclusive_scan
:
7667 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7669 case nir_intrinsic_inclusive_scan
:
7670 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7675 } else if (cluster_size
== 1) {
7676 bld
.copy(Definition(dst
), src
);
7678 src
= as_vgpr(ctx
, src
);
7682 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7697 unreachable("unknown reduction op");
7702 switch (instr
->intrinsic
) {
7703 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7704 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7705 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7707 unreachable("unknown reduce intrinsic");
7710 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7711 reduce
->operands
[0] = Operand(src
);
7712 // filled in by aco_reduce_assign.cpp, used internally as part of the
7714 assert(dst
.size() == 1 || dst
.size() == 2);
7715 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7716 reduce
->operands
[2] = Operand(v1
.as_linear());
7718 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7719 reduce
->definitions
[0] = Definition(tmp_dst
);
7720 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7721 reduce
->definitions
[2] = Definition();
7722 reduce
->definitions
[3] = Definition(scc
, s1
);
7723 reduce
->definitions
[4] = Definition();
7724 reduce
->reduce_op
= reduce_op
;
7725 reduce
->cluster_size
= cluster_size
;
7726 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7728 emit_wqm(ctx
, tmp_dst
, dst
);
7732 case nir_intrinsic_quad_broadcast
: {
7733 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7734 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7735 emit_uniform_subgroup(ctx
, instr
, src
);
7737 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7738 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7739 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7741 if (instr
->dest
.ssa
.bit_size
== 1) {
7742 assert(src
.regClass() == bld
.lm
);
7743 assert(dst
.regClass() == bld
.lm
);
7744 uint32_t half_mask
= 0x11111111u
<< lane
;
7745 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7746 Temp tmp
= bld
.tmp(bld
.lm
);
7747 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7748 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7749 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7750 emit_wqm(ctx
, tmp
, dst
);
7751 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7752 if (ctx
->program
->chip_class
>= GFX8
)
7753 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7755 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7756 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7757 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7759 if (ctx
->program
->chip_class
>= GFX8
) {
7760 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7761 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7763 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7764 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7766 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7767 emit_split_vector(ctx
, dst
, 2);
7769 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7770 nir_print_instr(&instr
->instr
, stderr
);
7771 fprintf(stderr
, "\n");
7776 case nir_intrinsic_quad_swap_horizontal
:
7777 case nir_intrinsic_quad_swap_vertical
:
7778 case nir_intrinsic_quad_swap_diagonal
:
7779 case nir_intrinsic_quad_swizzle_amd
: {
7780 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7781 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7782 emit_uniform_subgroup(ctx
, instr
, src
);
7785 uint16_t dpp_ctrl
= 0;
7786 switch (instr
->intrinsic
) {
7787 case nir_intrinsic_quad_swap_horizontal
:
7788 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7790 case nir_intrinsic_quad_swap_vertical
:
7791 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7793 case nir_intrinsic_quad_swap_diagonal
:
7794 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7796 case nir_intrinsic_quad_swizzle_amd
:
7797 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7802 if (ctx
->program
->chip_class
< GFX8
)
7803 dpp_ctrl
|= (1 << 15);
7805 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7806 if (instr
->dest
.ssa
.bit_size
== 1) {
7807 assert(src
.regClass() == bld
.lm
);
7808 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7809 if (ctx
->program
->chip_class
>= GFX8
)
7810 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7812 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7813 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7814 emit_wqm(ctx
, tmp
, dst
);
7815 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7817 if (ctx
->program
->chip_class
>= GFX8
)
7818 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7820 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7821 emit_wqm(ctx
, tmp
, dst
);
7822 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7823 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7824 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7825 if (ctx
->program
->chip_class
>= GFX8
) {
7826 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7827 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7829 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7830 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7832 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7833 emit_split_vector(ctx
, dst
, 2);
7835 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7836 nir_print_instr(&instr
->instr
, stderr
);
7837 fprintf(stderr
, "\n");
7841 case nir_intrinsic_masked_swizzle_amd
: {
7842 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7843 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7844 emit_uniform_subgroup(ctx
, instr
, src
);
7847 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7848 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7849 if (dst
.regClass() == v1
) {
7851 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7853 } else if (dst
.regClass() == v2
) {
7854 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7855 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7856 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7857 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7858 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7859 emit_split_vector(ctx
, dst
, 2);
7861 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7862 nir_print_instr(&instr
->instr
, stderr
);
7863 fprintf(stderr
, "\n");
7867 case nir_intrinsic_write_invocation_amd
: {
7868 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7869 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7870 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7871 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7872 if (dst
.regClass() == v1
) {
7873 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7874 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7875 } else if (dst
.regClass() == v2
) {
7876 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7877 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7879 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7880 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7881 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7882 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7883 emit_split_vector(ctx
, dst
, 2);
7885 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7886 nir_print_instr(&instr
->instr
, stderr
);
7887 fprintf(stderr
, "\n");
7891 case nir_intrinsic_mbcnt_amd
: {
7892 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7893 RegClass rc
= RegClass(src
.type(), 1);
7894 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7895 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7896 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7897 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7898 emit_wqm(ctx
, wqm_tmp
, dst
);
7901 case nir_intrinsic_load_helper_invocation
: {
7902 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7903 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7904 ctx
->block
->kind
|= block_kind_needs_lowering
;
7905 ctx
->program
->needs_exact
= true;
7908 case nir_intrinsic_is_helper_invocation
: {
7909 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7910 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7911 ctx
->block
->kind
|= block_kind_needs_lowering
;
7912 ctx
->program
->needs_exact
= true;
7915 case nir_intrinsic_demote
:
7916 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7918 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7919 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7920 ctx
->block
->kind
|= block_kind_uses_demote
;
7921 ctx
->program
->needs_exact
= true;
7923 case nir_intrinsic_demote_if
: {
7924 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7925 assert(src
.regClass() == bld
.lm
);
7926 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7927 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7929 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7930 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7931 ctx
->block
->kind
|= block_kind_uses_demote
;
7932 ctx
->program
->needs_exact
= true;
7935 case nir_intrinsic_first_invocation
: {
7936 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7937 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7940 case nir_intrinsic_shader_clock
:
7941 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7942 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7944 case nir_intrinsic_load_vertex_id_zero_base
: {
7945 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7946 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7949 case nir_intrinsic_load_first_vertex
: {
7950 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7951 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7954 case nir_intrinsic_load_base_instance
: {
7955 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7956 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7959 case nir_intrinsic_load_instance_id
: {
7960 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7961 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7964 case nir_intrinsic_load_draw_id
: {
7965 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7966 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7969 case nir_intrinsic_load_invocation_id
: {
7970 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7972 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7973 if (ctx
->options
->chip_class
>= GFX10
)
7974 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7976 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7977 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7978 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7979 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7981 unreachable("Unsupported stage for load_invocation_id");
7986 case nir_intrinsic_load_primitive_id
: {
7987 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7989 switch (ctx
->shader
->info
.stage
) {
7990 case MESA_SHADER_GEOMETRY
:
7991 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7993 case MESA_SHADER_TESS_CTRL
:
7994 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7996 case MESA_SHADER_TESS_EVAL
:
7997 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8000 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8005 case nir_intrinsic_load_patch_vertices_in
: {
8006 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8007 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8009 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8010 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8013 case nir_intrinsic_emit_vertex_with_counter
: {
8014 visit_emit_vertex_with_counter(ctx
, instr
);
8017 case nir_intrinsic_end_primitive_with_counter
: {
8018 unsigned stream
= nir_intrinsic_stream_id(instr
);
8019 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8022 case nir_intrinsic_set_vertex_count
: {
8023 /* unused, the HW keeps track of this for us */
8027 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8028 nir_print_instr(&instr
->instr
, stderr
);
8029 fprintf(stderr
, "\n");
8037 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8038 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8039 enum glsl_base_type
*stype
)
8041 nir_deref_instr
*texture_deref_instr
= NULL
;
8042 nir_deref_instr
*sampler_deref_instr
= NULL
;
8045 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8046 switch (instr
->src
[i
].src_type
) {
8047 case nir_tex_src_texture_deref
:
8048 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8050 case nir_tex_src_sampler_deref
:
8051 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8053 case nir_tex_src_plane
:
8054 plane
= nir_src_as_int(instr
->src
[i
].src
);
8061 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8063 if (!sampler_deref_instr
)
8064 sampler_deref_instr
= texture_deref_instr
;
8067 assert(instr
->op
!= nir_texop_txf_ms
&&
8068 instr
->op
!= nir_texop_samples_identical
);
8069 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8070 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8071 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8072 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8073 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8074 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8076 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8079 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8081 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8082 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8083 Builder
bld(ctx
->program
, ctx
->block
);
8085 /* to avoid unnecessary moves, we split and recombine sampler and image */
8086 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8087 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8088 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8089 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8090 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8091 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8092 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8093 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8095 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8096 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8097 img
[0], img
[1], img
[2], img
[3],
8098 img
[4], img
[5], img
[6], img
[7]);
8099 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8100 samp
[0], samp
[1], samp
[2], samp
[3]);
8103 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8104 instr
->op
== nir_texop_samples_identical
))
8105 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8108 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8109 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8111 Builder
bld(ctx
->program
, ctx
->block
);
8113 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8114 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8115 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8117 Operand
neg_one(0xbf800000u
);
8118 Operand
one(0x3f800000u
);
8119 Operand
two(0x40000000u
);
8120 Operand
four(0x40800000u
);
8122 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8123 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8124 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8126 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8127 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8128 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8129 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8132 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8133 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8134 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8136 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8139 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8140 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8141 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8144 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8145 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8147 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8148 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8151 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8153 Builder
bld(ctx
->program
, ctx
->block
);
8154 Temp ma
, tc
, sc
, id
;
8157 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8159 // see comment in ac_prepare_cube_coords()
8160 if (ctx
->options
->chip_class
<= GFX8
)
8161 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8164 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8166 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8167 vop3a
->operands
[0] = Operand(ma
);
8168 vop3a
->abs
[0] = true;
8169 Temp invma
= bld
.tmp(v1
);
8170 vop3a
->definitions
[0] = Definition(invma
);
8171 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8173 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8175 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8177 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8179 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8181 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8184 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8185 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8187 for (unsigned i
= 0; i
< 2; i
++) {
8188 // see comment in ac_prepare_cube_coords()
8190 Temp deriv_sc
, deriv_tc
;
8191 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8192 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8194 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8196 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8197 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8198 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8199 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8200 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8201 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8202 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8205 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8206 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8210 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8217 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8219 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8221 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8222 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8225 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8226 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8227 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8231 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8233 Builder
bld(ctx
->program
, ctx
->block
);
8234 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8235 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8236 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8237 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8238 std::vector
<Temp
> coords
;
8239 std::vector
<Temp
> derivs
;
8240 nir_const_value
*sample_index_cv
= NULL
;
8241 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8242 enum glsl_base_type stype
;
8243 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8245 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8246 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8247 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8248 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8250 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8251 switch (instr
->src
[i
].src_type
) {
8252 case nir_tex_src_coord
: {
8253 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8254 for (unsigned i
= 0; i
< coord
.size(); i
++)
8255 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8258 case nir_tex_src_bias
:
8259 if (instr
->op
== nir_texop_txb
) {
8260 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8264 case nir_tex_src_lod
: {
8265 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8267 if (val
&& val
->f32
<= 0.0) {
8270 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8275 case nir_tex_src_comparator
:
8276 if (instr
->is_shadow
) {
8277 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8281 case nir_tex_src_offset
:
8282 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8283 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8286 case nir_tex_src_ddx
:
8287 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8290 case nir_tex_src_ddy
:
8291 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8294 case nir_tex_src_ms_index
:
8295 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8296 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8297 has_sample_index
= true;
8299 case nir_tex_src_texture_offset
:
8300 case nir_tex_src_sampler_offset
:
8306 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8307 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8309 if (instr
->op
== nir_texop_texture_samples
) {
8310 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8312 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8313 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8314 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8315 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8317 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8318 samples
, Operand(1u), bld
.scc(is_msaa
));
8322 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8323 aco_ptr
<Instruction
> tmp_instr
;
8324 Temp acc
, pack
= Temp();
8326 uint32_t pack_const
= 0;
8327 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8328 if (!const_offset
[i
])
8330 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8333 if (offset
.type() == RegType::sgpr
) {
8334 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8335 if (const_offset
[i
])
8338 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8339 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8342 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8345 if (pack
== Temp()) {
8348 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8352 if (pack_const
&& pack
!= Temp())
8353 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8355 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8356 if (const_offset
[i
])
8359 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8360 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8363 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8366 if (pack
== Temp()) {
8369 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8373 if (pack_const
&& pack
!= Temp())
8374 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8376 if (pack_const
&& pack
== Temp())
8377 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8378 else if (pack
== Temp())
8384 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8385 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8387 /* pack derivatives */
8388 if (has_ddx
|| has_ddy
) {
8389 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8390 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8391 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8392 derivs
= {ddx
, zero
, ddy
, zero
};
8394 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8395 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8396 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8397 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8402 if (instr
->coord_components
> 1 &&
8403 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8405 instr
->op
!= nir_texop_txf
)
8406 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8408 if (instr
->coord_components
> 2 &&
8409 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8410 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8411 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8412 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8414 instr
->op
!= nir_texop_txf
&&
8415 instr
->op
!= nir_texop_txf_ms
&&
8416 instr
->op
!= nir_texop_fragment_fetch
&&
8417 instr
->op
!= nir_texop_fragment_mask_fetch
)
8418 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8420 if (ctx
->options
->chip_class
== GFX9
&&
8421 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8422 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8423 assert(coords
.size() > 0 && coords
.size() < 3);
8425 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8426 Operand((uint32_t) 0) :
8427 Operand((uint32_t) 0x3f000000)));
8430 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8432 if (instr
->op
== nir_texop_samples_identical
)
8433 resource
= fmask_ptr
;
8435 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8436 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8437 instr
->op
!= nir_texop_txs
&&
8438 instr
->op
!= nir_texop_fragment_fetch
&&
8439 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8440 assert(has_sample_index
);
8441 Operand
op(sample_index
);
8442 if (sample_index_cv
)
8443 op
= Operand(sample_index_cv
->u32
);
8444 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8447 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8448 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8449 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8450 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8455 /* Build tex instruction */
8456 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8457 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8458 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8460 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8463 /* gather4 selects the component by dmask and always returns vec4 */
8464 if (instr
->op
== nir_texop_tg4
) {
8465 assert(instr
->dest
.ssa
.num_components
== 4);
8466 if (instr
->is_shadow
)
8469 dmask
= 1 << instr
->component
;
8470 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8471 tmp_dst
= bld
.tmp(v4
);
8472 } else if (instr
->op
== nir_texop_samples_identical
) {
8473 tmp_dst
= bld
.tmp(v1
);
8474 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8475 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8478 aco_ptr
<MIMG_instruction
> tex
;
8479 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8481 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8483 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8484 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8487 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8488 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8490 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8491 tex
->operands
[0] = Operand(resource
);
8492 tex
->operands
[1] = Operand(s4
); /* no sampler */
8493 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8494 if (ctx
->options
->chip_class
== GFX9
&&
8495 instr
->op
== nir_texop_txs
&&
8496 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8498 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8499 } else if (instr
->op
== nir_texop_query_levels
) {
8500 tex
->dmask
= 1 << 3;
8505 tex
->definitions
[0] = Definition(tmp_dst
);
8507 tex
->can_reorder
= true;
8508 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8511 /* divide 3rd value by 6 by multiplying with magic number */
8512 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8513 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8514 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8515 assert(instr
->dest
.ssa
.num_components
== 3);
8516 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8517 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8518 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8519 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8524 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8528 Temp tg4_compare_cube_wa64
= Temp();
8530 if (tg4_integer_workarounds
) {
8531 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8532 tex
->operands
[0] = Operand(resource
);
8533 tex
->operands
[1] = Operand(s4
); /* no sampler */
8534 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8538 Temp size
= bld
.tmp(v2
);
8539 tex
->definitions
[0] = Definition(size
);
8540 tex
->can_reorder
= true;
8541 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8542 emit_split_vector(ctx
, size
, size
.size());
8545 for (unsigned i
= 0; i
< 2; i
++) {
8546 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8547 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8548 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8549 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8552 Temp new_coords
[2] = {
8553 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8554 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8557 if (tg4_integer_cube_workaround
) {
8558 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8559 Temp desc
[resource
.size()];
8560 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8561 Format::PSEUDO
, 1, resource
.size())};
8562 split
->operands
[0] = Operand(resource
);
8563 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8564 desc
[i
] = bld
.tmp(s1
);
8565 split
->definitions
[i
] = Definition(desc
[i
]);
8567 ctx
->block
->instructions
.emplace_back(std::move(split
));
8569 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8570 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8571 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8574 if (stype
== GLSL_TYPE_UINT
) {
8575 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8576 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8577 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8578 bld
.scc(compare_cube_wa
));
8580 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8581 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8582 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8583 bld
.scc(compare_cube_wa
));
8585 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8586 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8588 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8590 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8591 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8592 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8594 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8595 Format::PSEUDO
, resource
.size(), 1)};
8596 for (unsigned i
= 0; i
< resource
.size(); i
++)
8597 vec
->operands
[i
] = Operand(desc
[i
]);
8598 resource
= bld
.tmp(resource
.regClass());
8599 vec
->definitions
[0] = Definition(resource
);
8600 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8602 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8603 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8604 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8605 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8607 coords
[0] = new_coords
[0];
8608 coords
[1] = new_coords
[1];
8611 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8612 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8614 assert(coords
.size() == 1);
8615 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8619 op
= aco_opcode::buffer_load_format_x
; break;
8621 op
= aco_opcode::buffer_load_format_xy
; break;
8623 op
= aco_opcode::buffer_load_format_xyz
; break;
8625 op
= aco_opcode::buffer_load_format_xyzw
; break;
8627 unreachable("Tex instruction loads more than 4 components.");
8630 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8631 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8634 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8636 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8637 mubuf
->operands
[0] = Operand(resource
);
8638 mubuf
->operands
[1] = Operand(coords
[0]);
8639 mubuf
->operands
[2] = Operand((uint32_t) 0);
8640 mubuf
->definitions
[0] = Definition(tmp_dst
);
8641 mubuf
->idxen
= true;
8642 mubuf
->can_reorder
= true;
8643 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8645 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8649 /* gather MIMG address components */
8650 std::vector
<Temp
> args
;
8652 args
.emplace_back(offset
);
8654 args
.emplace_back(bias
);
8656 args
.emplace_back(compare
);
8658 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8660 args
.insert(args
.end(), coords
.begin(), coords
.end());
8661 if (has_sample_index
)
8662 args
.emplace_back(sample_index
);
8664 args
.emplace_back(lod
);
8666 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8667 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8668 vec
->definitions
[0] = Definition(arg
);
8669 for (unsigned i
= 0; i
< args
.size(); i
++)
8670 vec
->operands
[i
] = Operand(args
[i
]);
8671 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8674 if (instr
->op
== nir_texop_txf
||
8675 instr
->op
== nir_texop_txf_ms
||
8676 instr
->op
== nir_texop_samples_identical
||
8677 instr
->op
== nir_texop_fragment_fetch
||
8678 instr
->op
== nir_texop_fragment_mask_fetch
) {
8679 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8680 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8681 tex
->operands
[0] = Operand(resource
);
8682 tex
->operands
[1] = Operand(s4
); /* no sampler */
8683 tex
->operands
[2] = Operand(arg
);
8688 tex
->definitions
[0] = Definition(tmp_dst
);
8689 tex
->can_reorder
= true;
8690 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8692 if (instr
->op
== nir_texop_samples_identical
) {
8693 assert(dmask
== 1 && dst
.regClass() == v1
);
8694 assert(dst
.id() != tmp_dst
.id());
8696 Temp tmp
= bld
.tmp(bld
.lm
);
8697 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8698 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8701 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8706 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8707 aco_opcode opcode
= aco_opcode::image_sample
;
8708 if (has_offset
) { /* image_sample_*_o */
8710 opcode
= aco_opcode::image_sample_c_o
;
8712 opcode
= aco_opcode::image_sample_c_d_o
;
8714 opcode
= aco_opcode::image_sample_c_b_o
;
8716 opcode
= aco_opcode::image_sample_c_lz_o
;
8718 opcode
= aco_opcode::image_sample_c_l_o
;
8720 opcode
= aco_opcode::image_sample_o
;
8722 opcode
= aco_opcode::image_sample_d_o
;
8724 opcode
= aco_opcode::image_sample_b_o
;
8726 opcode
= aco_opcode::image_sample_lz_o
;
8728 opcode
= aco_opcode::image_sample_l_o
;
8730 } else { /* no offset */
8732 opcode
= aco_opcode::image_sample_c
;
8734 opcode
= aco_opcode::image_sample_c_d
;
8736 opcode
= aco_opcode::image_sample_c_b
;
8738 opcode
= aco_opcode::image_sample_c_lz
;
8740 opcode
= aco_opcode::image_sample_c_l
;
8742 opcode
= aco_opcode::image_sample
;
8744 opcode
= aco_opcode::image_sample_d
;
8746 opcode
= aco_opcode::image_sample_b
;
8748 opcode
= aco_opcode::image_sample_lz
;
8750 opcode
= aco_opcode::image_sample_l
;
8754 if (instr
->op
== nir_texop_tg4
) {
8756 opcode
= aco_opcode::image_gather4_lz_o
;
8758 opcode
= aco_opcode::image_gather4_c_lz_o
;
8760 opcode
= aco_opcode::image_gather4_lz
;
8762 opcode
= aco_opcode::image_gather4_c_lz
;
8764 } else if (instr
->op
== nir_texop_lod
) {
8765 opcode
= aco_opcode::image_get_lod
;
8768 /* we don't need the bias, sample index, compare value or offset to be
8769 * computed in WQM but if the p_create_vector copies the coordinates, then it
8770 * needs to be in WQM */
8771 if (ctx
->stage
== fragment_fs
&&
8772 !has_derivs
&& !has_lod
&& !level_zero
&&
8773 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8774 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8775 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8777 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8778 tex
->operands
[0] = Operand(resource
);
8779 tex
->operands
[1] = Operand(sampler
);
8780 tex
->operands
[2] = Operand(arg
);
8784 tex
->definitions
[0] = Definition(tmp_dst
);
8785 tex
->can_reorder
= true;
8786 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8788 if (tg4_integer_cube_workaround
) {
8789 assert(tmp_dst
.id() != dst
.id());
8790 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8792 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8794 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8795 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8797 if (stype
== GLSL_TYPE_UINT
)
8798 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8800 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8801 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8803 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8804 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8805 val
[0], val
[1], val
[2], val
[3]);
8807 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8808 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8813 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8815 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8816 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8817 return Operand(tmp
.regClass());
8819 return Operand(tmp
);
8822 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8824 aco_ptr
<Pseudo_instruction
> phi
;
8825 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8826 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8828 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8829 logical
|= ctx
->block
->kind
& block_kind_merge
;
8830 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8832 /* we want a sorted list of sources, since the predecessor list is also sorted */
8833 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8834 nir_foreach_phi_src(src
, instr
)
8835 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8837 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8838 unsigned num_operands
= 0;
8839 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8840 unsigned num_defined
= 0;
8841 unsigned cur_pred_idx
= 0;
8842 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8843 if (cur_pred_idx
< preds
.size()) {
8844 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8845 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8846 unsigned skipped
= 0;
8847 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8849 if (cur_pred_idx
+ skipped
< preds
.size()) {
8850 for (unsigned i
= 0; i
< skipped
; i
++)
8851 operands
[num_operands
++] = Operand(dst
.regClass());
8852 cur_pred_idx
+= skipped
;
8857 /* Handle missing predecessors at the end. This shouldn't happen with loop
8858 * headers and we can't ignore these sources for loop header phis. */
8859 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8862 Operand op
= get_phi_operand(ctx
, src
.second
);
8863 operands
[num_operands
++] = op
;
8864 num_defined
+= !op
.isUndefined();
8866 /* handle block_kind_continue_or_break at loop exit blocks */
8867 while (cur_pred_idx
++ < preds
.size())
8868 operands
[num_operands
++] = Operand(dst
.regClass());
8870 /* If the loop ends with a break, still add a linear continue edge in case
8871 * that break is divergent or continue_or_break is used. We'll either remove
8872 * this operand later in visit_loop() if it's not necessary or replace the
8873 * undef with something correct. */
8874 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8875 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8876 nir_block
*last
= nir_loop_last_block(loop
);
8877 if (last
->successors
[0] != instr
->instr
.block
)
8878 operands
[num_operands
++] = Operand(RegClass());
8881 if (num_defined
== 0) {
8882 Builder
bld(ctx
->program
, ctx
->block
);
8883 if (dst
.regClass() == s1
) {
8884 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8885 } else if (dst
.regClass() == v1
) {
8886 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8888 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8889 for (unsigned i
= 0; i
< dst
.size(); i
++)
8890 vec
->operands
[i
] = Operand(0u);
8891 vec
->definitions
[0] = Definition(dst
);
8892 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8897 /* we can use a linear phi in some cases if one src is undef */
8898 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8899 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8901 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8902 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8903 assert(invert
->kind
& block_kind_invert
);
8905 unsigned then_block
= invert
->linear_preds
[0];
8907 Block
* insert_block
= NULL
;
8908 for (unsigned i
= 0; i
< num_operands
; i
++) {
8909 Operand op
= operands
[i
];
8910 if (op
.isUndefined())
8912 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8913 phi
->operands
[0] = op
;
8916 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8917 phi
->operands
[1] = Operand(dst
.regClass());
8918 phi
->definitions
[0] = Definition(dst
);
8919 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8923 /* try to scalarize vector phis */
8924 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8925 // TODO: scalarize linear phis on divergent ifs
8926 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8927 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8928 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8929 Operand src
= operands
[i
];
8930 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8931 can_scalarize
= false;
8933 if (can_scalarize
) {
8934 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8935 assert(dst
.size() % num_components
== 0);
8936 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8938 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8939 for (unsigned k
= 0; k
< num_components
; k
++) {
8940 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8941 for (unsigned i
= 0; i
< num_operands
; i
++) {
8942 Operand src
= operands
[i
];
8943 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8945 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8946 phi
->definitions
[0] = Definition(phi_dst
);
8947 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8948 new_vec
[k
] = phi_dst
;
8949 vec
->operands
[k
] = Operand(phi_dst
);
8951 vec
->definitions
[0] = Definition(dst
);
8952 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8953 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8958 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8959 for (unsigned i
= 0; i
< num_operands
; i
++)
8960 phi
->operands
[i
] = operands
[i
];
8961 phi
->definitions
[0] = Definition(dst
);
8962 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8966 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8968 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8970 assert(dst
.type() == RegType::sgpr
);
8972 if (dst
.size() == 1) {
8973 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8975 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8976 for (unsigned i
= 0; i
< dst
.size(); i
++)
8977 vec
->operands
[i
] = Operand(0u);
8978 vec
->definitions
[0] = Definition(dst
);
8979 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8983 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8985 Builder
bld(ctx
->program
, ctx
->block
);
8986 Block
*logical_target
;
8987 append_logical_end(ctx
->block
);
8988 unsigned idx
= ctx
->block
->index
;
8990 switch (instr
->type
) {
8991 case nir_jump_break
:
8992 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8993 add_logical_edge(idx
, logical_target
);
8994 ctx
->block
->kind
|= block_kind_break
;
8996 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8997 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8998 /* uniform break - directly jump out of the loop */
8999 ctx
->block
->kind
|= block_kind_uniform
;
9000 ctx
->cf_info
.has_branch
= true;
9001 bld
.branch(aco_opcode::p_branch
);
9002 add_linear_edge(idx
, logical_target
);
9005 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9006 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9008 case nir_jump_continue
:
9009 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9010 add_logical_edge(idx
, logical_target
);
9011 ctx
->block
->kind
|= block_kind_continue
;
9013 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9014 /* for potential uniform breaks after this continue,
9015 we must ensure that they are handled correctly */
9016 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9017 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9018 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9020 /* uniform continue - directly jump to the loop header */
9021 ctx
->block
->kind
|= block_kind_uniform
;
9022 ctx
->cf_info
.has_branch
= true;
9023 bld
.branch(aco_opcode::p_branch
);
9024 add_linear_edge(idx
, logical_target
);
9029 fprintf(stderr
, "Unknown NIR jump instr: ");
9030 nir_print_instr(&instr
->instr
, stderr
);
9031 fprintf(stderr
, "\n");
9035 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9036 ctx
->cf_info
.exec_potentially_empty_break
= true;
9037 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9040 /* remove critical edges from linear CFG */
9041 bld
.branch(aco_opcode::p_branch
);
9042 Block
* break_block
= ctx
->program
->create_and_insert_block();
9043 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9044 break_block
->kind
|= block_kind_uniform
;
9045 add_linear_edge(idx
, break_block
);
9046 /* the loop_header pointer might be invalidated by this point */
9047 if (instr
->type
== nir_jump_continue
)
9048 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9049 add_linear_edge(break_block
->index
, logical_target
);
9050 bld
.reset(break_block
);
9051 bld
.branch(aco_opcode::p_branch
);
9053 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9054 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9055 add_linear_edge(idx
, continue_block
);
9056 append_logical_start(continue_block
);
9057 ctx
->block
= continue_block
;
9061 void visit_block(isel_context
*ctx
, nir_block
*block
)
9063 nir_foreach_instr(instr
, block
) {
9064 switch (instr
->type
) {
9065 case nir_instr_type_alu
:
9066 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9068 case nir_instr_type_load_const
:
9069 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9071 case nir_instr_type_intrinsic
:
9072 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9074 case nir_instr_type_tex
:
9075 visit_tex(ctx
, nir_instr_as_tex(instr
));
9077 case nir_instr_type_phi
:
9078 visit_phi(ctx
, nir_instr_as_phi(instr
));
9080 case nir_instr_type_ssa_undef
:
9081 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9083 case nir_instr_type_deref
:
9085 case nir_instr_type_jump
:
9086 visit_jump(ctx
, nir_instr_as_jump(instr
));
9089 fprintf(stderr
, "Unknown NIR instr type: ");
9090 nir_print_instr(instr
, stderr
);
9091 fprintf(stderr
, "\n");
9096 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9097 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9102 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9103 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9105 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9106 RegClass rc
= vals
[0].regClass();
9108 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9110 unsigned next_pred
= 1;
9112 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9113 Block
& block
= ctx
->program
->blocks
[idx
];
9114 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9115 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9119 if (block
.kind
& block_kind_continue
) {
9120 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9125 bool all_same
= true;
9126 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9127 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9131 val
= vals
[block
.linear_preds
[0] - first
];
9133 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9134 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9135 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9136 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9137 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9138 phi
->definitions
[0] = Definition(val
.getTemp());
9139 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9141 vals
[idx
- first
] = val
;
9144 return vals
[last
- first
];
9147 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9149 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9150 append_logical_end(ctx
->block
);
9151 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9152 Builder
bld(ctx
->program
, ctx
->block
);
9153 bld
.branch(aco_opcode::p_branch
);
9154 unsigned loop_preheader_idx
= ctx
->block
->index
;
9156 Block loop_exit
= Block();
9157 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9158 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9160 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9161 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9162 loop_header
->kind
|= block_kind_loop_header
;
9163 add_edge(loop_preheader_idx
, loop_header
);
9164 ctx
->block
= loop_header
;
9166 /* emit loop body */
9167 unsigned loop_header_idx
= loop_header
->index
;
9168 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9169 append_logical_start(ctx
->block
);
9170 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9172 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9173 if (!ctx
->cf_info
.has_branch
) {
9174 append_logical_end(ctx
->block
);
9175 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9176 /* Discards can result in code running with an empty exec mask.
9177 * This would result in divergent breaks not ever being taken. As a
9178 * workaround, break the loop when the loop mask is empty instead of
9179 * always continuing. */
9180 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9181 unsigned block_idx
= ctx
->block
->index
;
9183 /* create helper blocks to avoid critical edges */
9184 Block
*break_block
= ctx
->program
->create_and_insert_block();
9185 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9186 break_block
->kind
= block_kind_uniform
;
9187 bld
.reset(break_block
);
9188 bld
.branch(aco_opcode::p_branch
);
9189 add_linear_edge(block_idx
, break_block
);
9190 add_linear_edge(break_block
->index
, &loop_exit
);
9192 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9193 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9194 continue_block
->kind
= block_kind_uniform
;
9195 bld
.reset(continue_block
);
9196 bld
.branch(aco_opcode::p_branch
);
9197 add_linear_edge(block_idx
, continue_block
);
9198 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9200 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9201 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9202 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9204 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9205 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9206 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9208 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9211 bld
.reset(ctx
->block
);
9212 bld
.branch(aco_opcode::p_branch
);
9215 /* Fixup phis in loop header from unreachable blocks.
9216 * has_branch/has_divergent_branch also indicates if the loop ends with a
9217 * break/continue instruction, but we don't emit those if unreachable=true */
9219 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9220 bool linear
= ctx
->cf_info
.has_branch
;
9221 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9222 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9223 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9224 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9225 /* the last operand should be the one that needs to be removed */
9226 instr
->operands
.pop_back();
9227 } else if (!is_phi(instr
)) {
9233 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9234 * and the previous one shouldn't both happen at once because a break in the
9235 * merge block would get CSE'd */
9236 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9237 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9238 Operand vals
[num_vals
];
9239 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9240 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9241 if (ctx
->cf_info
.has_branch
)
9242 instr
->operands
.pop_back();
9244 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9245 } else if (!is_phi(instr
)) {
9251 ctx
->cf_info
.has_branch
= false;
9253 // TODO: if the loop has not a single exit, we must add one °°
9254 /* emit loop successor block */
9255 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9256 append_logical_start(ctx
->block
);
9259 // TODO: check if it is beneficial to not branch on continues
9260 /* trim linear phis in loop header */
9261 for (auto&& instr
: loop_entry
->instructions
) {
9262 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9263 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9264 new_phi
->definitions
[0] = instr
->definitions
[0];
9265 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9266 new_phi
->operands
[i
] = instr
->operands
[i
];
9267 /* check that the remaining operands are all the same */
9268 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9269 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9270 instr
.swap(new_phi
);
9271 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9280 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9284 append_logical_end(ctx
->block
);
9285 ctx
->block
->kind
|= block_kind_branch
;
9287 /* branch to linear then block */
9288 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9289 aco_ptr
<Pseudo_branch_instruction
> branch
;
9290 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9291 branch
->operands
[0] = Operand(cond
);
9292 ctx
->block
->instructions
.push_back(std::move(branch
));
9294 ic
->BB_if_idx
= ctx
->block
->index
;
9295 ic
->BB_invert
= Block();
9296 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9297 /* Invert blocks are intentionally not marked as top level because they
9298 * are not part of the logical cfg. */
9299 ic
->BB_invert
.kind
|= block_kind_invert
;
9300 ic
->BB_endif
= Block();
9301 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9302 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9304 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9305 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9306 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9307 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9308 ctx
->cf_info
.parent_if
.is_divergent
= true;
9310 /* divergent branches use cbranch_execz */
9311 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9312 ctx
->cf_info
.exec_potentially_empty_break
= false;
9313 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9315 /** emit logical then block */
9316 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9317 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9318 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9319 ctx
->block
= BB_then_logical
;
9320 append_logical_start(BB_then_logical
);
9323 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9325 Block
*BB_then_logical
= ctx
->block
;
9326 append_logical_end(BB_then_logical
);
9327 /* branch from logical then block to invert block */
9328 aco_ptr
<Pseudo_branch_instruction
> branch
;
9329 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9330 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9331 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9332 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9333 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9334 BB_then_logical
->kind
|= block_kind_uniform
;
9335 assert(!ctx
->cf_info
.has_branch
);
9336 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9337 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9339 /** emit linear then block */
9340 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9341 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9342 BB_then_linear
->kind
|= block_kind_uniform
;
9343 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9344 /* branch from linear then block to invert block */
9345 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9346 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9347 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9349 /** emit invert merge block */
9350 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9351 ic
->invert_idx
= ctx
->block
->index
;
9353 /* branch to linear else block (skip else) */
9354 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9355 branch
->operands
[0] = Operand(ic
->cond
);
9356 ctx
->block
->instructions
.push_back(std::move(branch
));
9358 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9359 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9360 ic
->exec_potentially_empty_break_depth_old
=
9361 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9362 /* divergent branches use cbranch_execz */
9363 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9364 ctx
->cf_info
.exec_potentially_empty_break
= false;
9365 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9367 /** emit logical else block */
9368 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9369 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9370 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9371 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9372 ctx
->block
= BB_else_logical
;
9373 append_logical_start(BB_else_logical
);
9376 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9378 Block
*BB_else_logical
= ctx
->block
;
9379 append_logical_end(BB_else_logical
);
9381 /* branch from logical else block to endif block */
9382 aco_ptr
<Pseudo_branch_instruction
> branch
;
9383 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9384 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9385 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9386 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9387 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9388 BB_else_logical
->kind
|= block_kind_uniform
;
9390 assert(!ctx
->cf_info
.has_branch
);
9391 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9394 /** emit linear else block */
9395 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9396 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9397 BB_else_linear
->kind
|= block_kind_uniform
;
9398 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9400 /* branch from linear else block to endif block */
9401 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9402 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9403 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9406 /** emit endif merge block */
9407 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9408 append_logical_start(ctx
->block
);
9411 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9412 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9413 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9414 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9415 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9416 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9417 !ctx
->cf_info
.parent_if
.is_divergent
) {
9418 ctx
->cf_info
.exec_potentially_empty_break
= false;
9419 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9421 /* uniform control flow never has an empty exec-mask */
9422 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9423 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9424 ctx
->cf_info
.exec_potentially_empty_break
= false;
9425 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9429 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9431 assert(cond
.regClass() == s1
);
9433 append_logical_end(ctx
->block
);
9434 ctx
->block
->kind
|= block_kind_uniform
;
9436 aco_ptr
<Pseudo_branch_instruction
> branch
;
9437 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9438 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9439 branch
->operands
[0] = Operand(cond
);
9440 branch
->operands
[0].setFixed(scc
);
9441 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9443 ic
->BB_if_idx
= ctx
->block
->index
;
9444 ic
->BB_endif
= Block();
9445 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9446 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9448 ctx
->cf_info
.has_branch
= false;
9449 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9451 /** emit then block */
9452 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9453 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9454 add_edge(ic
->BB_if_idx
, BB_then
);
9455 append_logical_start(BB_then
);
9456 ctx
->block
= BB_then
;
9459 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9461 Block
*BB_then
= ctx
->block
;
9463 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9464 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9466 if (!ic
->uniform_has_then_branch
) {
9467 append_logical_end(BB_then
);
9468 /* branch from then block to endif block */
9469 aco_ptr
<Pseudo_branch_instruction
> branch
;
9470 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9471 BB_then
->instructions
.emplace_back(std::move(branch
));
9472 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9473 if (!ic
->then_branch_divergent
)
9474 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9475 BB_then
->kind
|= block_kind_uniform
;
9478 ctx
->cf_info
.has_branch
= false;
9479 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9481 /** emit else block */
9482 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9483 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9484 add_edge(ic
->BB_if_idx
, BB_else
);
9485 append_logical_start(BB_else
);
9486 ctx
->block
= BB_else
;
9489 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9491 Block
*BB_else
= ctx
->block
;
9493 if (!ctx
->cf_info
.has_branch
) {
9494 append_logical_end(BB_else
);
9495 /* branch from then block to endif block */
9496 aco_ptr
<Pseudo_branch_instruction
> branch
;
9497 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9498 BB_else
->instructions
.emplace_back(std::move(branch
));
9499 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9500 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9501 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9502 BB_else
->kind
|= block_kind_uniform
;
9505 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9506 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9508 /** emit endif merge block */
9509 if (!ctx
->cf_info
.has_branch
) {
9510 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9511 append_logical_start(ctx
->block
);
9515 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9517 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9518 Builder
bld(ctx
->program
, ctx
->block
);
9519 aco_ptr
<Pseudo_branch_instruction
> branch
;
9522 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9524 * Uniform conditionals are represented in the following way*) :
9526 * The linear and logical CFG:
9529 * BB_THEN (logical) BB_ELSE (logical)
9533 * *) Exceptions may be due to break and continue statements within loops
9534 * If a break/continue happens within uniform control flow, it branches
9535 * to the loop exit/entry block. Otherwise, it branches to the next
9539 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9540 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9541 cond
= bool_to_scalar_condition(ctx
, cond
);
9543 begin_uniform_if_then(ctx
, &ic
, cond
);
9544 visit_cf_list(ctx
, &if_stmt
->then_list
);
9546 begin_uniform_if_else(ctx
, &ic
);
9547 visit_cf_list(ctx
, &if_stmt
->else_list
);
9549 end_uniform_if(ctx
, &ic
);
9551 return !ctx
->cf_info
.has_branch
;
9552 } else { /* non-uniform condition */
9554 * To maintain a logical and linear CFG without critical edges,
9555 * non-uniform conditionals are represented in the following way*) :
9560 * BB_THEN (logical) BB_THEN (linear)
9562 * BB_INVERT (linear)
9564 * BB_ELSE (logical) BB_ELSE (linear)
9571 * BB_THEN (logical) BB_ELSE (logical)
9575 * *) Exceptions may be due to break and continue statements within loops
9578 begin_divergent_if_then(ctx
, &ic
, cond
);
9579 visit_cf_list(ctx
, &if_stmt
->then_list
);
9581 begin_divergent_if_else(ctx
, &ic
);
9582 visit_cf_list(ctx
, &if_stmt
->else_list
);
9584 end_divergent_if(ctx
, &ic
);
9590 static bool visit_cf_list(isel_context
*ctx
,
9591 struct exec_list
*list
)
9593 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9594 switch (node
->type
) {
9595 case nir_cf_node_block
:
9596 visit_block(ctx
, nir_cf_node_as_block(node
));
9598 case nir_cf_node_if
:
9599 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9602 case nir_cf_node_loop
:
9603 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9606 unreachable("unimplemented cf list type");
9612 static void create_null_export(isel_context
*ctx
)
9614 /* Some shader stages always need to have exports.
9615 * So when there is none, we need to add a null export.
9618 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9619 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9620 Builder
bld(ctx
->program
, ctx
->block
);
9621 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9622 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9625 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9627 assert(ctx
->stage
== vertex_vs
||
9628 ctx
->stage
== tess_eval_vs
||
9629 ctx
->stage
== gs_copy_vs
||
9630 ctx
->stage
== ngg_vertex_gs
||
9631 ctx
->stage
== ngg_tess_eval_gs
);
9633 int offset
= (ctx
->stage
& sw_tes
)
9634 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9635 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9636 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9637 if (!is_pos
&& !mask
)
9639 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9641 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9642 exp
->enabled_mask
= mask
;
9643 for (unsigned i
= 0; i
< 4; ++i
) {
9644 if (mask
& (1 << i
))
9645 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9647 exp
->operands
[i
] = Operand(v1
);
9649 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9650 * Setting valid_mask=1 prevents it and has no other effect.
9652 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9654 exp
->compressed
= false;
9656 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9658 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9659 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9664 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9666 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9667 exp
->enabled_mask
= 0;
9668 for (unsigned i
= 0; i
< 4; ++i
)
9669 exp
->operands
[i
] = Operand(v1
);
9670 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9671 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9672 exp
->enabled_mask
|= 0x1;
9674 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9675 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9676 exp
->enabled_mask
|= 0x4;
9678 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9679 if (ctx
->options
->chip_class
< GFX9
) {
9680 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9681 exp
->enabled_mask
|= 0x8;
9683 Builder
bld(ctx
->program
, ctx
->block
);
9685 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9686 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9687 if (exp
->operands
[2].isTemp())
9688 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9690 exp
->operands
[2] = Operand(out
);
9691 exp
->enabled_mask
|= 0x4;
9694 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9696 exp
->compressed
= false;
9697 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9698 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9701 static void create_export_phis(isel_context
*ctx
)
9703 /* Used when exports are needed, but the output temps are defined in a preceding block.
9704 * This function will set up phis in order to access the outputs in the next block.
9707 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9708 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9709 ctx
->block
->instructions
.pop_back();
9711 Builder
bld(ctx
->program
, ctx
->block
);
9713 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9714 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9715 for (unsigned i
= 0; i
< 4; ++i
) {
9716 if (!(mask
& (1 << i
)))
9719 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9720 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9721 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9725 bld
.insert(std::move(logical_start
));
9728 static void create_vs_exports(isel_context
*ctx
)
9730 assert(ctx
->stage
== vertex_vs
||
9731 ctx
->stage
== tess_eval_vs
||
9732 ctx
->stage
== gs_copy_vs
||
9733 ctx
->stage
== ngg_vertex_gs
||
9734 ctx
->stage
== ngg_tess_eval_gs
);
9736 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9737 ? &ctx
->program
->info
->tes
.outinfo
9738 : &ctx
->program
->info
->vs
.outinfo
;
9740 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9741 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9742 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9745 if (ctx
->options
->key
.has_multiview_view_index
) {
9746 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9747 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9750 /* the order these position exports are created is important */
9752 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9753 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9754 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9755 exported_pos
= true;
9757 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9758 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9759 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9760 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9762 if (ctx
->export_clip_dists
) {
9763 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9764 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9765 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9766 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9769 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9770 if (i
< VARYING_SLOT_VAR0
&&
9771 i
!= VARYING_SLOT_LAYER
&&
9772 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9773 i
!= VARYING_SLOT_VIEWPORT
)
9776 export_vs_varying(ctx
, i
, false, NULL
);
9780 create_null_export(ctx
);
9783 static bool export_fs_mrt_z(isel_context
*ctx
)
9785 Builder
bld(ctx
->program
, ctx
->block
);
9786 unsigned enabled_channels
= 0;
9790 for (unsigned i
= 0; i
< 4; ++i
) {
9791 values
[i
] = Operand(v1
);
9794 /* Both stencil and sample mask only need 16-bits. */
9795 if (!ctx
->program
->info
->ps
.writes_z
&&
9796 (ctx
->program
->info
->ps
.writes_stencil
||
9797 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9798 compr
= true; /* COMPR flag */
9800 if (ctx
->program
->info
->ps
.writes_stencil
) {
9801 /* Stencil should be in X[23:16]. */
9802 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9803 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9804 enabled_channels
|= 0x3;
9807 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9808 /* SampleMask should be in Y[15:0]. */
9809 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9810 enabled_channels
|= 0xc;
9813 if (ctx
->program
->info
->ps
.writes_z
) {
9814 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9815 enabled_channels
|= 0x1;
9818 if (ctx
->program
->info
->ps
.writes_stencil
) {
9819 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9820 enabled_channels
|= 0x2;
9823 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9824 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9825 enabled_channels
|= 0x4;
9829 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9830 * writemask component.
9832 if (ctx
->options
->chip_class
== GFX6
&&
9833 ctx
->options
->family
!= CHIP_OLAND
&&
9834 ctx
->options
->family
!= CHIP_HAINAN
) {
9835 enabled_channels
|= 0x1;
9838 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9839 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9844 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9846 Builder
bld(ctx
->program
, ctx
->block
);
9847 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9850 for (unsigned i
= 0; i
< 4; ++i
) {
9851 if (write_mask
& (1 << i
)) {
9852 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9854 values
[i
] = Operand(v1
);
9858 unsigned target
, col_format
;
9859 unsigned enabled_channels
= 0;
9860 aco_opcode compr_op
= (aco_opcode
)0;
9862 slot
-= FRAG_RESULT_DATA0
;
9863 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9864 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9866 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9867 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9871 case V_028714_SPI_SHADER_ZERO
:
9872 enabled_channels
= 0; /* writemask */
9873 target
= V_008DFC_SQ_EXP_NULL
;
9876 case V_028714_SPI_SHADER_32_R
:
9877 enabled_channels
= 1;
9880 case V_028714_SPI_SHADER_32_GR
:
9881 enabled_channels
= 0x3;
9884 case V_028714_SPI_SHADER_32_AR
:
9885 if (ctx
->options
->chip_class
>= GFX10
) {
9886 /* Special case: on GFX10, the outputs are different for 32_AR */
9887 enabled_channels
= 0x3;
9888 values
[1] = values
[3];
9889 values
[3] = Operand(v1
);
9891 enabled_channels
= 0x9;
9895 case V_028714_SPI_SHADER_FP16_ABGR
:
9896 enabled_channels
= 0x5;
9897 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9900 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9901 enabled_channels
= 0x5;
9902 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9905 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9906 enabled_channels
= 0x5;
9907 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9910 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9911 enabled_channels
= 0x5;
9912 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9913 if (is_int8
|| is_int10
) {
9915 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9916 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9918 for (unsigned i
= 0; i
< 4; i
++) {
9919 if ((write_mask
>> i
) & 1) {
9920 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9921 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9929 case V_028714_SPI_SHADER_SINT16_ABGR
:
9930 enabled_channels
= 0x5;
9931 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9932 if (is_int8
|| is_int10
) {
9934 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9935 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9936 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9937 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9939 for (unsigned i
= 0; i
< 4; i
++) {
9940 if ((write_mask
>> i
) & 1) {
9941 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9942 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9944 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9945 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9952 case V_028714_SPI_SHADER_32_ABGR
:
9953 enabled_channels
= 0xF;
9960 if (target
== V_008DFC_SQ_EXP_NULL
)
9963 if ((bool) compr_op
) {
9964 for (int i
= 0; i
< 2; i
++) {
9965 /* check if at least one of the values to be compressed is enabled */
9966 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9968 enabled_channels
|= enabled
<< (i
*2);
9969 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9970 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9971 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9973 values
[i
] = Operand(v1
);
9976 values
[2] = Operand(v1
);
9977 values
[3] = Operand(v1
);
9979 for (int i
= 0; i
< 4; i
++)
9980 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9983 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9984 enabled_channels
, target
, (bool) compr_op
);
9988 static void create_fs_exports(isel_context
*ctx
)
9990 bool exported
= false;
9992 /* Export depth, stencil and sample mask. */
9993 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9994 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9995 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9996 exported
|= export_fs_mrt_z(ctx
);
9998 /* Export all color render targets. */
9999 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10000 if (ctx
->outputs
.mask
[i
])
10001 exported
|= export_fs_mrt_color(ctx
, i
);
10004 create_null_export(ctx
);
10007 static void write_tcs_tess_factors(isel_context
*ctx
)
10009 unsigned outer_comps
;
10010 unsigned inner_comps
;
10012 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10029 Builder
bld(ctx
->program
, ctx
->block
);
10031 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10032 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10033 bld
.sopp(aco_opcode::s_barrier
);
10035 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10036 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10038 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10039 if_context ic_invocation_id_is_zero
;
10040 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10041 bld
.reset(ctx
->block
);
10043 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10045 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10046 unsigned stride
= inner_comps
+ outer_comps
;
10047 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10051 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10053 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10055 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10056 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10057 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10059 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10060 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10062 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10063 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10064 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10065 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10068 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10069 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10070 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10071 unsigned tf_const_offset
= 0;
10073 if (ctx
->program
->chip_class
<= GFX8
) {
10074 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10075 if_context ic_rel_patch_id_is_zero
;
10076 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10077 bld
.reset(ctx
->block
);
10079 /* Store the dynamic HS control word. */
10080 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10081 bld
.mubuf(aco_opcode::buffer_store_dword
,
10082 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10083 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10084 /* disable_wqm */ false, /* glc */ true);
10085 tf_const_offset
+= 4;
10087 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10088 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10089 bld
.reset(ctx
->block
);
10092 assert(stride
== 2 || stride
== 4 || stride
== 6);
10093 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10094 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10096 /* Store to offchip for TES to read - only if TES reads them */
10097 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10098 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10099 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10101 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10102 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10104 if (likely(inner_comps
)) {
10105 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10106 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10110 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10111 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10114 static void emit_stream_output(isel_context
*ctx
,
10115 Temp
const *so_buffers
,
10116 Temp
const *so_write_offset
,
10117 const struct radv_stream_output
*output
)
10119 unsigned num_comps
= util_bitcount(output
->component_mask
);
10120 unsigned writemask
= (1 << num_comps
) - 1;
10121 unsigned loc
= output
->location
;
10122 unsigned buf
= output
->buffer
;
10124 assert(num_comps
&& num_comps
<= 4);
10125 if (!num_comps
|| num_comps
> 4)
10128 unsigned start
= ffs(output
->component_mask
) - 1;
10131 bool all_undef
= true;
10132 assert(ctx
->stage
& hw_vs
);
10133 for (unsigned i
= 0; i
< num_comps
; i
++) {
10134 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10135 all_undef
= all_undef
&& !out
[i
].id();
10140 while (writemask
) {
10142 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10143 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10144 /* GFX6 doesn't support storing vec3, split it. */
10145 writemask
|= 1u << (start
+ 2);
10149 unsigned offset
= output
->offset
+ start
* 4;
10151 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10152 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10153 for (int i
= 0; i
< count
; ++i
)
10154 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10155 vec
->definitions
[0] = Definition(write_data
);
10156 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10161 opcode
= aco_opcode::buffer_store_dword
;
10164 opcode
= aco_opcode::buffer_store_dwordx2
;
10167 opcode
= aco_opcode::buffer_store_dwordx3
;
10170 opcode
= aco_opcode::buffer_store_dwordx4
;
10173 unreachable("Unsupported dword count.");
10176 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10177 store
->operands
[0] = Operand(so_buffers
[buf
]);
10178 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10179 store
->operands
[2] = Operand((uint32_t) 0);
10180 store
->operands
[3] = Operand(write_data
);
10181 if (offset
> 4095) {
10182 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10183 Builder
bld(ctx
->program
, ctx
->block
);
10184 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10186 store
->offset
= offset
;
10188 store
->offen
= true;
10190 store
->dlc
= false;
10192 store
->can_reorder
= true;
10193 ctx
->block
->instructions
.emplace_back(std::move(store
));
10197 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10199 Builder
bld(ctx
->program
, ctx
->block
);
10201 Temp so_buffers
[4];
10202 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10203 for (unsigned i
= 0; i
< 4; i
++) {
10204 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10208 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10209 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10212 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10213 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10215 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10217 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10220 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10222 bld
.reset(ctx
->block
);
10224 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10226 Temp so_write_offset
[4];
10228 for (unsigned i
= 0; i
< 4; i
++) {
10229 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10234 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10235 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10236 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10237 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10239 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10241 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10242 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10243 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10244 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10248 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10249 struct radv_stream_output
*output
=
10250 &ctx
->program
->info
->so
.outputs
[i
];
10251 if (stream
!= output
->stream
)
10254 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10257 begin_divergent_if_else(ctx
, &ic
);
10258 end_divergent_if(ctx
, &ic
);
10261 } /* end namespace */
10263 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10265 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10266 Builder
bld(ctx
->program
, ctx
->block
);
10267 constexpr unsigned hs_idx
= 1u;
10268 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10269 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10270 Operand((8u << 16) | (hs_idx
* 8u)));
10271 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10273 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10275 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10276 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10277 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10278 ls_has_nonzero_hs_threads
);
10279 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10280 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10281 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10282 ls_has_nonzero_hs_threads
);
10283 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10284 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10285 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10286 ls_has_nonzero_hs_threads
);
10288 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10289 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10290 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10293 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10295 /* Split all arguments except for the first (ring_offsets) and the last
10296 * (exec) so that the dead channels don't stay live throughout the program.
10298 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10299 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10300 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10301 startpgm
->definitions
[i
].regClass().size());
10306 void handle_bc_optimize(isel_context
*ctx
)
10308 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10309 Builder
bld(ctx
->program
, ctx
->block
);
10310 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10311 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10312 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10313 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10314 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10315 if (uses_center
&& uses_centroid
) {
10316 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10317 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10319 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10321 for (unsigned i
= 0; i
< 2; i
++) {
10322 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10323 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10324 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10325 persp_centroid
, persp_center
, sel
);
10327 ctx
->persp_centroid
= bld
.tmp(v2
);
10328 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10329 Operand(new_coord
[0]), Operand(new_coord
[1]));
10330 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10333 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10335 for (unsigned i
= 0; i
< 2; i
++) {
10336 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10337 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10338 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10339 linear_centroid
, linear_center
, sel
);
10341 ctx
->linear_centroid
= bld
.tmp(v2
);
10342 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10343 Operand(new_coord
[0]), Operand(new_coord
[1]));
10344 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10349 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10351 Program
*program
= ctx
->program
;
10353 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10355 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10356 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10357 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10358 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10359 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10361 program
->next_fp_mode
.must_flush_denorms32
=
10362 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10363 program
->next_fp_mode
.must_flush_denorms16_64
=
10364 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10365 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10367 program
->next_fp_mode
.care_about_round32
=
10368 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10370 program
->next_fp_mode
.care_about_round16_64
=
10371 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10372 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10374 /* default to preserving fp16 and fp64 denorms, since it's free */
10375 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10376 program
->next_fp_mode
.denorm16_64
= 0;
10378 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10380 /* preserving fp32 denorms is expensive, so only do it if asked */
10381 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10382 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10384 program
->next_fp_mode
.denorm32
= 0;
10386 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10387 program
->next_fp_mode
.round32
= fp_round_tz
;
10389 program
->next_fp_mode
.round32
= fp_round_ne
;
10391 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10392 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10394 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10396 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10399 void cleanup_cfg(Program
*program
)
10401 /* create linear_succs/logical_succs */
10402 for (Block
& BB
: program
->blocks
) {
10403 for (unsigned idx
: BB
.linear_preds
)
10404 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10405 for (unsigned idx
: BB
.logical_preds
)
10406 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10410 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10412 Builder
bld(ctx
->program
, ctx
->block
);
10414 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10415 Temp count
= i
== 0
10416 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10417 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10418 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10420 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10423 if (ctx
->program
->wave_size
== 64) {
10424 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10425 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10426 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10428 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10429 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10435 bool ngg_early_prim_export(isel_context
*ctx
)
10437 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10441 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10443 Builder
bld(ctx
->program
, ctx
->block
);
10445 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10446 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10448 /* Get the id of the current wave within the threadgroup (workgroup) */
10449 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10450 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10452 /* Execute the following code only on the first wave (wave id 0),
10453 * use the SCC def to tell if the wave id is zero or not.
10455 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10457 begin_uniform_if_then(ctx
, &ic
, cond
);
10458 begin_uniform_if_else(ctx
, &ic
);
10459 bld
.reset(ctx
->block
);
10461 /* Number of vertices output by VS/TES */
10462 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10463 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10464 /* Number of primitives output by VS/TES */
10465 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10466 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10468 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10469 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10470 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10472 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10473 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10475 end_uniform_if(ctx
, &ic
);
10477 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10478 bld
.reset(ctx
->block
);
10479 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10482 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10484 Builder
bld(ctx
->program
, ctx
->block
);
10486 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10487 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10490 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10493 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10494 assert(vtxindex
[i
].id());
10497 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10501 /* The initial edge flag is always false in tess eval shaders. */
10502 if (ctx
->stage
== ngg_vertex_gs
) {
10503 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10504 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10508 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10513 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10515 Builder
bld(ctx
->program
, ctx
->block
);
10516 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10518 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10519 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10520 false /* compressed */, true/* done */, false /* valid mask */);
10523 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10525 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10526 * These must always come before VS exports.
10528 * It is recommended to do these as early as possible. They can be at the beginning when
10529 * there is no SW GS and the shader doesn't write edge flags.
10533 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10534 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10536 Builder
bld(ctx
->program
, ctx
->block
);
10537 constexpr unsigned max_vertices_per_primitive
= 3;
10538 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10540 if (ctx
->stage
== ngg_vertex_gs
) {
10541 /* TODO: optimize for points & lines */
10542 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10543 if (ctx
->shader
->info
.tess
.point_mode
)
10544 num_vertices_per_primitive
= 1;
10545 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10546 num_vertices_per_primitive
= 2;
10548 unreachable("Unsupported NGG shader stage");
10551 Temp vtxindex
[max_vertices_per_primitive
];
10552 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10553 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10554 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10555 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10556 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10557 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10558 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10559 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10561 /* Export primitive data to the index buffer. */
10562 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10564 /* Export primitive ID. */
10565 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10566 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10567 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10568 Temp provoking_vtx_index
= vtxindex
[0];
10569 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10571 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10574 begin_divergent_if_else(ctx
, &ic
);
10575 end_divergent_if(ctx
, &ic
);
10578 void ngg_emit_nogs_output(isel_context
*ctx
)
10580 /* Emits NGG GS output, for stages that don't have SW GS. */
10583 Builder
bld(ctx
->program
, ctx
->block
);
10584 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10586 /* NGG streamout is currently disabled by default. */
10587 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10589 if (late_prim_export
) {
10590 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10591 create_export_phis(ctx
);
10592 /* Do what we need to do in the GS threads. */
10593 ngg_emit_nogs_gsthreads(ctx
);
10595 /* What comes next should be executed on ES threads. */
10596 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10597 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10598 bld
.reset(ctx
->block
);
10601 /* Export VS outputs */
10602 ctx
->block
->kind
|= block_kind_export_end
;
10603 create_vs_exports(ctx
);
10605 /* Export primitive ID */
10606 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10609 if (ctx
->stage
== ngg_vertex_gs
) {
10610 /* Wait for GS threads to store primitive ID in LDS. */
10611 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10612 bld
.sopp(aco_opcode::s_barrier
);
10614 /* Calculate LDS address where the GS threads stored the primitive ID. */
10615 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10616 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10617 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10618 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10619 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10620 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10622 /* Load primitive ID from LDS. */
10623 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10624 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10625 /* TES: Just use the patch ID as the primitive ID. */
10626 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10628 unreachable("unsupported NGG shader stage.");
10631 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10632 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10634 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10637 if (late_prim_export
) {
10638 begin_divergent_if_else(ctx
, &ic
);
10639 end_divergent_if(ctx
, &ic
);
10640 bld
.reset(ctx
->block
);
10644 void select_program(Program
*program
,
10645 unsigned shader_count
,
10646 struct nir_shader
*const *shaders
,
10647 ac_shader_config
* config
,
10648 struct radv_shader_args
*args
)
10650 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10651 if_context ic_merged_wave_info
;
10652 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10654 for (unsigned i
= 0; i
< shader_count
; i
++) {
10655 nir_shader
*nir
= shaders
[i
];
10656 init_context(&ctx
, nir
);
10658 setup_fp_mode(&ctx
, nir
);
10661 /* needs to be after init_context() for FS */
10662 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10663 append_logical_start(ctx
.block
);
10665 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10666 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10668 split_arguments(&ctx
, startpgm
);
10672 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10674 if (ngg_early_prim_export(&ctx
))
10675 ngg_emit_nogs_gsthreads(&ctx
);
10678 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10679 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10680 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10681 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10682 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10683 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10684 ctx
.stage
== tess_eval_geometry_gs
));
10686 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10687 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10688 if (check_merged_wave_info
) {
10689 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10690 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10694 Builder
bld(ctx
.program
, ctx
.block
);
10696 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10697 bld
.sopp(aco_opcode::s_barrier
);
10699 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10700 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10702 } else if (ctx
.stage
== geometry_gs
)
10703 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10705 if (ctx
.stage
== fragment_fs
)
10706 handle_bc_optimize(&ctx
);
10708 visit_cf_list(&ctx
, &func
->body
);
10710 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10711 emit_streamout(&ctx
, 0);
10713 if (ctx
.stage
& hw_vs
) {
10714 create_vs_exports(&ctx
);
10715 ctx
.block
->kind
|= block_kind_export_end
;
10716 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10717 ngg_emit_nogs_output(&ctx
);
10718 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10719 Builder
bld(ctx
.program
, ctx
.block
);
10720 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10721 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10722 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10723 write_tcs_tess_factors(&ctx
);
10726 if (ctx
.stage
== fragment_fs
) {
10727 create_fs_exports(&ctx
);
10728 ctx
.block
->kind
|= block_kind_export_end
;
10731 if (endif_merged_wave_info
) {
10732 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10733 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10736 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10737 ngg_emit_nogs_output(&ctx
);
10739 ralloc_free(ctx
.divergent_vals
);
10741 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10742 /* Outputs of the previous stage are inputs to the next stage */
10743 ctx
.inputs
= ctx
.outputs
;
10744 ctx
.outputs
= shader_io_state();
10748 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10750 append_logical_end(ctx
.block
);
10751 ctx
.block
->kind
|= block_kind_uniform
;
10752 Builder
bld(ctx
.program
, ctx
.block
);
10753 if (ctx
.program
->wb_smem_l1_on_end
)
10754 bld
.smem(aco_opcode::s_dcache_wb
, false);
10755 bld
.sopp(aco_opcode::s_endpgm
);
10757 cleanup_cfg(program
);
10760 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10761 ac_shader_config
* config
,
10762 struct radv_shader_args
*args
)
10764 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10766 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10767 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10768 program
->next_fp_mode
.must_flush_denorms32
= false;
10769 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10770 program
->next_fp_mode
.care_about_round32
= false;
10771 program
->next_fp_mode
.care_about_round16_64
= false;
10772 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10773 program
->next_fp_mode
.denorm32
= 0;
10774 program
->next_fp_mode
.round32
= fp_round_ne
;
10775 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10776 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10778 add_startpgm(&ctx
);
10779 append_logical_start(ctx
.block
);
10781 Builder
bld(ctx
.program
, ctx
.block
);
10783 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10785 Operand
stream_id(0u);
10786 if (args
->shader_info
->so
.num_outputs
)
10787 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10788 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10790 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10792 std::stack
<Block
> endif_blocks
;
10794 for (unsigned stream
= 0; stream
< 4; stream
++) {
10795 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10798 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10799 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10802 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10804 unsigned BB_if_idx
= ctx
.block
->index
;
10805 Block BB_endif
= Block();
10806 if (!stream_id
.isConstant()) {
10808 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10809 append_logical_end(ctx
.block
);
10810 ctx
.block
->kind
|= block_kind_uniform
;
10811 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10813 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10815 ctx
.block
= ctx
.program
->create_and_insert_block();
10816 add_edge(BB_if_idx
, ctx
.block
);
10817 bld
.reset(ctx
.block
);
10818 append_logical_start(ctx
.block
);
10821 unsigned offset
= 0;
10822 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10823 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10826 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10827 unsigned length
= util_last_bit(output_usage_mask
);
10828 for (unsigned j
= 0; j
< length
; ++j
) {
10829 if (!(output_usage_mask
& (1 << j
)))
10832 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10833 Temp voffset
= vtx_offset
;
10834 if (const_offset
>= 4096u) {
10835 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10836 const_offset
%= 4096u;
10839 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10840 mubuf
->definitions
[0] = bld
.def(v1
);
10841 mubuf
->operands
[0] = Operand(gsvs_ring
);
10842 mubuf
->operands
[1] = Operand(voffset
);
10843 mubuf
->operands
[2] = Operand(0u);
10844 mubuf
->offen
= true;
10845 mubuf
->offset
= const_offset
;
10848 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10849 mubuf
->barrier
= barrier_none
;
10850 mubuf
->can_reorder
= true;
10852 ctx
.outputs
.mask
[i
] |= 1 << j
;
10853 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10855 bld
.insert(std::move(mubuf
));
10861 if (args
->shader_info
->so
.num_outputs
) {
10862 emit_streamout(&ctx
, stream
);
10863 bld
.reset(ctx
.block
);
10867 create_vs_exports(&ctx
);
10868 ctx
.block
->kind
|= block_kind_export_end
;
10871 if (!stream_id
.isConstant()) {
10872 append_logical_end(ctx
.block
);
10874 /* branch from then block to endif block */
10875 bld
.branch(aco_opcode::p_branch
);
10876 add_edge(ctx
.block
->index
, &BB_endif
);
10877 ctx
.block
->kind
|= block_kind_uniform
;
10879 /* emit else block */
10880 ctx
.block
= ctx
.program
->create_and_insert_block();
10881 add_edge(BB_if_idx
, ctx
.block
);
10882 bld
.reset(ctx
.block
);
10883 append_logical_start(ctx
.block
);
10885 endif_blocks
.push(std::move(BB_endif
));
10889 while (!endif_blocks
.empty()) {
10890 Block BB_endif
= std::move(endif_blocks
.top());
10891 endif_blocks
.pop();
10893 Block
*BB_else
= ctx
.block
;
10895 append_logical_end(BB_else
);
10896 /* branch from else block to endif block */
10897 bld
.branch(aco_opcode::p_branch
);
10898 add_edge(BB_else
->index
, &BB_endif
);
10899 BB_else
->kind
|= block_kind_uniform
;
10901 /** emit endif merge block */
10902 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10903 bld
.reset(ctx
.block
);
10904 append_logical_start(ctx
.block
);
10907 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10909 append_logical_end(ctx
.block
);
10910 ctx
.block
->kind
|= block_kind_uniform
;
10911 bld
.sopp(aco_opcode::s_endpgm
);
10913 cleanup_cfg(program
);