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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
565 src1
= as_vgpr(ctx
, src1
);
569 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
570 assert(dst
.size() == 1);
571 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
572 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
574 bld
.vop2(op
, Definition(dst
), src0
, src1
);
578 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
579 bool flush_denorms
= false)
581 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
582 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
583 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
585 /* ensure that the instruction has at most 1 sgpr operand
586 * The optimizer will inline constants for us */
587 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
588 src0
= as_vgpr(ctx
, src0
);
589 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
590 src1
= as_vgpr(ctx
, src1
);
591 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
592 src2
= as_vgpr(ctx
, src2
);
594 Builder
bld(ctx
->program
, ctx
->block
);
595 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
596 assert(dst
.size() == 1);
597 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
598 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
600 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
604 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
606 Builder
bld(ctx
->program
, ctx
->block
);
607 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
610 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
613 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
614 assert(src0
.size() == src1
.size());
616 aco_ptr
<Instruction
> vopc
;
617 if (src1
.type() == RegType::sgpr
) {
618 if (src0
.type() == RegType::vgpr
) {
619 /* to swap the operands, we might also have to change the opcode */
621 case aco_opcode::v_cmp_lt_f16
:
622 op
= aco_opcode::v_cmp_gt_f16
;
624 case aco_opcode::v_cmp_ge_f16
:
625 op
= aco_opcode::v_cmp_le_f16
;
627 case aco_opcode::v_cmp_lt_i16
:
628 op
= aco_opcode::v_cmp_gt_i16
;
630 case aco_opcode::v_cmp_ge_i16
:
631 op
= aco_opcode::v_cmp_le_i16
;
633 case aco_opcode::v_cmp_lt_u16
:
634 op
= aco_opcode::v_cmp_gt_u16
;
636 case aco_opcode::v_cmp_ge_u16
:
637 op
= aco_opcode::v_cmp_le_u16
;
639 case aco_opcode::v_cmp_lt_f32
:
640 op
= aco_opcode::v_cmp_gt_f32
;
642 case aco_opcode::v_cmp_ge_f32
:
643 op
= aco_opcode::v_cmp_le_f32
;
645 case aco_opcode::v_cmp_lt_i32
:
646 op
= aco_opcode::v_cmp_gt_i32
;
648 case aco_opcode::v_cmp_ge_i32
:
649 op
= aco_opcode::v_cmp_le_i32
;
651 case aco_opcode::v_cmp_lt_u32
:
652 op
= aco_opcode::v_cmp_gt_u32
;
654 case aco_opcode::v_cmp_ge_u32
:
655 op
= aco_opcode::v_cmp_le_u32
;
657 case aco_opcode::v_cmp_lt_f64
:
658 op
= aco_opcode::v_cmp_gt_f64
;
660 case aco_opcode::v_cmp_ge_f64
:
661 op
= aco_opcode::v_cmp_le_f64
;
663 case aco_opcode::v_cmp_lt_i64
:
664 op
= aco_opcode::v_cmp_gt_i64
;
666 case aco_opcode::v_cmp_ge_i64
:
667 op
= aco_opcode::v_cmp_le_i64
;
669 case aco_opcode::v_cmp_lt_u64
:
670 op
= aco_opcode::v_cmp_gt_u64
;
672 case aco_opcode::v_cmp_ge_u64
:
673 op
= aco_opcode::v_cmp_le_u64
;
675 default: /* eq and ne are commutative */
682 src1
= as_vgpr(ctx
, src1
);
686 Builder
bld(ctx
->program
, ctx
->block
);
687 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
690 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
692 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
693 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
694 Builder
bld(ctx
->program
, ctx
->block
);
696 assert(dst
.regClass() == bld
.lm
);
697 assert(src0
.type() == RegType::sgpr
);
698 assert(src1
.type() == RegType::sgpr
);
699 assert(src0
.regClass() == src1
.regClass());
701 /* Emit the SALU comparison instruction */
702 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
703 /* Turn the result into a per-lane bool */
704 bool_to_vector_condition(ctx
, cmp
, dst
);
707 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
708 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
710 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
711 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
712 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
713 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
715 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
716 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
717 aco_opcode op
= use_valu
? v_op
: s_op
;
718 assert(op
!= aco_opcode::num_opcodes
);
719 assert(dst
.regClass() == ctx
->program
->lane_mask
);
722 emit_vopc_instruction(ctx
, instr
, op
, dst
);
724 emit_sopc_instruction(ctx
, instr
, op
, dst
);
727 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
729 Builder
bld(ctx
->program
, ctx
->block
);
730 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
731 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
733 assert(dst
.regClass() == bld
.lm
);
734 assert(src0
.regClass() == bld
.lm
);
735 assert(src1
.regClass() == bld
.lm
);
737 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
740 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
742 Builder
bld(ctx
->program
, ctx
->block
);
743 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
744 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
745 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
747 assert(cond
.regClass() == bld
.lm
);
749 if (dst
.type() == RegType::vgpr
) {
750 aco_ptr
<Instruction
> bcsel
;
751 if (dst
.regClass() == v2b
) {
752 then
= as_vgpr(ctx
, then
);
753 els
= as_vgpr(ctx
, els
);
755 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
756 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
757 } else if (dst
.regClass() == v1
) {
758 then
= as_vgpr(ctx
, then
);
759 els
= as_vgpr(ctx
, els
);
761 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
762 } else if (dst
.regClass() == v2
) {
763 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
765 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
766 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
768 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
769 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
771 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
773 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
774 nir_print_instr(&instr
->instr
, stderr
);
775 fprintf(stderr
, "\n");
780 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
781 assert(dst
.regClass() == bld
.lm
);
782 assert(then
.regClass() == bld
.lm
);
783 assert(els
.regClass() == bld
.lm
);
786 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
787 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
788 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
789 assert(dst
.size() == then
.size());
790 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
791 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
793 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
794 nir_print_instr(&instr
->instr
, stderr
);
795 fprintf(stderr
, "\n");
800 /* divergent boolean bcsel
801 * this implements bcsel on bools: dst = s0 ? s1 : s2
802 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
803 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
805 if (cond
.id() != then
.id())
806 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
808 if (cond
.id() == els
.id())
809 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
811 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
812 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
815 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
816 aco_opcode op
, uint32_t undo
)
818 /* multiply by 16777216 to handle denormals */
819 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
820 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
821 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
822 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
823 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
825 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
827 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
830 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
832 if (ctx
->block
->fp_mode
.denorm32
== 0) {
833 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
837 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
840 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
842 if (ctx
->block
->fp_mode
.denorm32
== 0) {
843 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
847 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
850 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
852 if (ctx
->block
->fp_mode
.denorm32
== 0) {
853 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
857 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
860 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
862 if (ctx
->block
->fp_mode
.denorm32
== 0) {
863 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
867 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
870 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
872 if (ctx
->options
->chip_class
>= GFX7
)
873 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
875 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
876 /* TODO: create more efficient code! */
877 if (val
.type() == RegType::sgpr
)
878 val
= as_vgpr(ctx
, val
);
880 /* Split the input value. */
881 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
882 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
884 /* Extract the exponent and compute the unbiased value. */
885 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
887 /* Extract the fractional part. */
888 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
889 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
891 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
892 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
894 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
895 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
896 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
897 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
898 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
900 /* Get the sign bit. */
901 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
903 /* Decide the operation to apply depending on the unbiased exponent. */
904 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
905 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
906 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
907 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
908 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
909 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
911 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
914 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
916 if (ctx
->options
->chip_class
>= GFX7
)
917 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
919 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
920 Temp src0
= as_vgpr(ctx
, val
);
922 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
923 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
925 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
926 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
927 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
929 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
931 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
934 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
935 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
937 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
939 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
940 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
942 return add
->definitions
[0].getTemp();
945 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
947 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
948 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
950 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
953 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
954 return bld
.copy(Definition(dst
), src
);
955 else if (dst
.bytes() < src
.bytes())
956 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
960 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
963 } else if (src
.regClass() == s1
) {
965 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
967 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
969 assert(src_bits
!= 8 || src
.regClass() == v1b
);
970 assert(src_bits
!= 16 || src
.regClass() == v2b
);
971 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
972 sdwa
->operands
[0] = Operand(src
);
973 sdwa
->definitions
[0] = Definition(tmp
);
975 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
977 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
978 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
979 bld
.insert(std::move(sdwa
));
982 if (dst_bits
== 64) {
983 if (is_signed
&& dst
.regClass() == s2
) {
984 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
985 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
986 } else if (is_signed
&& dst
.regClass() == v2
) {
987 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
988 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
990 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
997 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
999 if (!instr
->dest
.dest
.is_ssa
) {
1000 fprintf(stderr
, "nir alu dst not in ssa: ");
1001 nir_print_instr(&instr
->instr
, stderr
);
1002 fprintf(stderr
, "\n");
1005 Builder
bld(ctx
->program
, ctx
->block
);
1006 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1011 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1012 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1013 for (unsigned i
= 0; i
< num
; ++i
)
1014 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1016 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1017 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1018 for (unsigned i
= 0; i
< num
; ++i
)
1019 vec
->operands
[i
] = Operand
{elems
[i
]};
1020 vec
->definitions
[0] = Definition(dst
);
1021 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1022 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1024 // TODO: that is a bit suboptimal..
1025 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1026 for (unsigned i
= 0; i
< num
- 1; ++i
)
1027 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1028 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1029 for (unsigned i
= 0; i
< num
; ++i
) {
1030 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1031 if (bit
% 32 == 0) {
1032 elems
[bit
/ 32] = elems
[i
];
1034 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1035 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1036 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1039 if (dst
.size() == 1)
1040 bld
.copy(Definition(dst
), elems
[0]);
1042 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1047 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1048 aco_ptr
<Instruction
> mov
;
1049 if (dst
.type() == RegType::sgpr
) {
1050 if (src
.type() == RegType::vgpr
)
1051 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1052 else if (src
.regClass() == s1
)
1053 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1054 else if (src
.regClass() == s2
)
1055 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1057 unreachable("wrong src register class for nir_op_imov");
1058 } else if (dst
.regClass() == v1
) {
1059 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1060 } else if (dst
.regClass() == v2
) {
1061 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1063 nir_print_instr(&instr
->instr
, stderr
);
1064 unreachable("Should have been lowered to scalar.");
1069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1070 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1071 assert(src
.regClass() == bld
.lm
);
1072 assert(dst
.regClass() == bld
.lm
);
1073 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1074 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1075 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1076 } else if (dst
.regClass() == v1
) {
1077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1078 } else if (dst
.type() == RegType::sgpr
) {
1079 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1080 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1082 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1083 nir_print_instr(&instr
->instr
, stderr
);
1084 fprintf(stderr
, "\n");
1089 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1090 if (dst
.regClass() == v1
) {
1091 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1092 } else if (dst
.regClass() == s1
) {
1093 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1094 } else if (dst
.size() == 2) {
1095 Temp src0
= bld
.tmp(dst
.type(), 1);
1096 Temp src1
= bld
.tmp(dst
.type(), 1);
1097 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1099 if (dst
.regClass() == s2
) {
1100 Temp carry
= bld
.tmp(s1
);
1101 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1102 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1103 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1105 Temp lower
= bld
.tmp(v1
);
1106 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1107 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1108 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1111 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1112 nir_print_instr(&instr
->instr
, stderr
);
1113 fprintf(stderr
, "\n");
1118 if (dst
.regClass() == s1
) {
1119 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1120 } else if (dst
.regClass() == v1
) {
1121 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1122 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1124 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1125 nir_print_instr(&instr
->instr
, stderr
);
1126 fprintf(stderr
, "\n");
1130 case nir_op_isign
: {
1131 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1132 if (dst
.regClass() == s1
) {
1133 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1134 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1135 } else if (dst
.regClass() == s2
) {
1136 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1138 if (ctx
->program
->chip_class
>= GFX8
)
1139 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1141 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1142 /* SCC gets zero-extended to 64 bit */
1143 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1144 } else if (dst
.regClass() == v1
) {
1145 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1146 } else if (dst
.regClass() == v2
) {
1147 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1148 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1149 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1150 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1151 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1154 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1155 nir_print_instr(&instr
->instr
, stderr
);
1156 fprintf(stderr
, "\n");
1161 if (dst
.regClass() == v1
) {
1162 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1163 } else if (dst
.regClass() == s1
) {
1164 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1166 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1167 nir_print_instr(&instr
->instr
, stderr
);
1168 fprintf(stderr
, "\n");
1173 if (dst
.regClass() == v1
) {
1174 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1175 } else if (dst
.regClass() == s1
) {
1176 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1178 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1179 nir_print_instr(&instr
->instr
, stderr
);
1180 fprintf(stderr
, "\n");
1185 if (dst
.regClass() == v1
) {
1186 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1187 } else if (dst
.regClass() == s1
) {
1188 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1190 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1191 nir_print_instr(&instr
->instr
, stderr
);
1192 fprintf(stderr
, "\n");
1197 if (dst
.regClass() == v1
) {
1198 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1199 } else if (dst
.regClass() == s1
) {
1200 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1202 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1203 nir_print_instr(&instr
->instr
, stderr
);
1204 fprintf(stderr
, "\n");
1209 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1210 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1211 } else if (dst
.regClass() == v1
) {
1212 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1213 } else if (dst
.regClass() == s1
) {
1214 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1215 } else if (dst
.regClass() == s2
) {
1216 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1218 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1219 nir_print_instr(&instr
->instr
, stderr
);
1220 fprintf(stderr
, "\n");
1225 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1226 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1227 } else if (dst
.regClass() == v1
) {
1228 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1229 } else if (dst
.regClass() == s1
) {
1230 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1231 } else if (dst
.regClass() == s2
) {
1232 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1234 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1235 nir_print_instr(&instr
->instr
, stderr
);
1236 fprintf(stderr
, "\n");
1241 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1242 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1243 } else if (dst
.regClass() == v1
) {
1244 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1245 } else if (dst
.regClass() == s1
) {
1246 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1247 } else if (dst
.regClass() == s2
) {
1248 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1250 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1251 nir_print_instr(&instr
->instr
, stderr
);
1252 fprintf(stderr
, "\n");
1257 if (dst
.regClass() == v1
) {
1258 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1259 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1260 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1261 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1262 } else if (dst
.regClass() == v2
) {
1263 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1264 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1265 } else if (dst
.regClass() == s2
) {
1266 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1267 } else if (dst
.regClass() == s1
) {
1268 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1270 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1271 nir_print_instr(&instr
->instr
, stderr
);
1272 fprintf(stderr
, "\n");
1277 if (dst
.regClass() == v1
) {
1278 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1279 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1280 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1281 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1282 } else if (dst
.regClass() == v2
) {
1283 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1284 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1285 } else if (dst
.regClass() == s1
) {
1286 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1287 } else if (dst
.regClass() == s2
) {
1288 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1290 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1291 nir_print_instr(&instr
->instr
, stderr
);
1292 fprintf(stderr
, "\n");
1297 if (dst
.regClass() == v1
) {
1298 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1299 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1300 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1301 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1302 } else if (dst
.regClass() == v2
) {
1303 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1304 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1305 } else if (dst
.regClass() == s1
) {
1306 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1307 } else if (dst
.regClass() == s2
) {
1308 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1310 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1311 nir_print_instr(&instr
->instr
, stderr
);
1312 fprintf(stderr
, "\n");
1316 case nir_op_find_lsb
: {
1317 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1318 if (src
.regClass() == s1
) {
1319 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1320 } else if (src
.regClass() == v1
) {
1321 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1322 } else if (src
.regClass() == s2
) {
1323 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1331 case nir_op_ufind_msb
:
1332 case nir_op_ifind_msb
: {
1333 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1334 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1335 aco_opcode op
= src
.regClass() == s2
?
1336 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1337 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1338 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1340 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1341 Operand(src
.size() * 32u - 1u), msb_rev
);
1342 Temp msb
= sub
.def(0).getTemp();
1343 Temp carry
= sub
.def(1).getTemp();
1345 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1346 } else if (src
.regClass() == v1
) {
1347 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1348 Temp msb_rev
= bld
.tmp(v1
);
1349 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1350 Temp msb
= bld
.tmp(v1
);
1351 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1352 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1354 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1355 nir_print_instr(&instr
->instr
, stderr
);
1356 fprintf(stderr
, "\n");
1360 case nir_op_bitfield_reverse
: {
1361 if (dst
.regClass() == s1
) {
1362 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1363 } else if (dst
.regClass() == v1
) {
1364 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1366 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1367 nir_print_instr(&instr
->instr
, stderr
);
1368 fprintf(stderr
, "\n");
1373 if (dst
.regClass() == s1
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1378 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1379 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1380 if (dst
.regClass() == v1
) {
1381 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1385 assert(src0
.size() == 2 && src1
.size() == 2);
1386 Temp src00
= bld
.tmp(src0
.type(), 1);
1387 Temp src01
= bld
.tmp(dst
.type(), 1);
1388 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1389 Temp src10
= bld
.tmp(src1
.type(), 1);
1390 Temp src11
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1393 if (dst
.regClass() == s2
) {
1394 Temp carry
= bld
.tmp(s1
);
1395 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1396 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1397 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1398 } else if (dst
.regClass() == v2
) {
1399 Temp dst0
= bld
.tmp(v1
);
1400 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1401 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1402 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1404 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1405 nir_print_instr(&instr
->instr
, stderr
);
1406 fprintf(stderr
, "\n");
1410 case nir_op_uadd_sat
: {
1411 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1412 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1413 if (dst
.regClass() == s1
) {
1414 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1415 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1417 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1418 } else if (dst
.regClass() == v1
) {
1419 if (ctx
->options
->chip_class
>= GFX9
) {
1420 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1421 add
->operands
[0] = Operand(src0
);
1422 add
->operands
[1] = Operand(src1
);
1423 add
->definitions
[0] = Definition(dst
);
1425 ctx
->block
->instructions
.emplace_back(std::move(add
));
1427 if (src1
.regClass() != v1
)
1428 std::swap(src0
, src1
);
1429 assert(src1
.regClass() == v1
);
1430 Temp tmp
= bld
.tmp(v1
);
1431 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1432 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1435 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1436 nir_print_instr(&instr
->instr
, stderr
);
1437 fprintf(stderr
, "\n");
1441 case nir_op_uadd_carry
: {
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == s1
) {
1445 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1448 if (dst
.regClass() == v1
) {
1449 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1450 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1454 Temp src00
= bld
.tmp(src0
.type(), 1);
1455 Temp src01
= bld
.tmp(dst
.type(), 1);
1456 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1457 Temp src10
= bld
.tmp(src1
.type(), 1);
1458 Temp src11
= bld
.tmp(dst
.type(), 1);
1459 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1460 if (dst
.regClass() == s2
) {
1461 Temp carry
= bld
.tmp(s1
);
1462 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1463 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1465 } else if (dst
.regClass() == v2
) {
1466 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1467 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1468 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1469 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1471 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1472 nir_print_instr(&instr
->instr
, stderr
);
1473 fprintf(stderr
, "\n");
1478 if (dst
.regClass() == s1
) {
1479 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1483 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1484 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1485 if (dst
.regClass() == v1
) {
1486 bld
.vsub32(Definition(dst
), src0
, src1
);
1490 Temp src00
= bld
.tmp(src0
.type(), 1);
1491 Temp src01
= bld
.tmp(dst
.type(), 1);
1492 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1493 Temp src10
= bld
.tmp(src1
.type(), 1);
1494 Temp src11
= bld
.tmp(dst
.type(), 1);
1495 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1496 if (dst
.regClass() == s2
) {
1497 Temp carry
= bld
.tmp(s1
);
1498 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1499 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1500 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1501 } else if (dst
.regClass() == v2
) {
1502 Temp lower
= bld
.tmp(v1
);
1503 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1504 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1507 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1508 nir_print_instr(&instr
->instr
, stderr
);
1509 fprintf(stderr
, "\n");
1513 case nir_op_usub_borrow
: {
1514 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1515 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1516 if (dst
.regClass() == s1
) {
1517 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1519 } else if (dst
.regClass() == v1
) {
1520 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1521 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1525 Temp src00
= bld
.tmp(src0
.type(), 1);
1526 Temp src01
= bld
.tmp(dst
.type(), 1);
1527 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1528 Temp src10
= bld
.tmp(src1
.type(), 1);
1529 Temp src11
= bld
.tmp(dst
.type(), 1);
1530 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1531 if (dst
.regClass() == s2
) {
1532 Temp borrow
= bld
.tmp(s1
);
1533 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1534 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1535 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1536 } else if (dst
.regClass() == v2
) {
1537 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1538 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1539 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1540 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1542 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1543 nir_print_instr(&instr
->instr
, stderr
);
1544 fprintf(stderr
, "\n");
1549 if (dst
.regClass() == v1
) {
1550 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1551 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1552 } else if (dst
.regClass() == s1
) {
1553 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1555 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1556 nir_print_instr(&instr
->instr
, stderr
);
1557 fprintf(stderr
, "\n");
1561 case nir_op_umul_high
: {
1562 if (dst
.regClass() == v1
) {
1563 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1564 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1565 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1566 } else if (dst
.regClass() == s1
) {
1567 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1568 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1569 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1571 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1572 nir_print_instr(&instr
->instr
, stderr
);
1573 fprintf(stderr
, "\n");
1577 case nir_op_imul_high
: {
1578 if (dst
.regClass() == v1
) {
1579 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1580 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1581 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1582 } else if (dst
.regClass() == s1
) {
1583 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1584 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1585 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1587 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1588 nir_print_instr(&instr
->instr
, stderr
);
1589 fprintf(stderr
, "\n");
1594 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1595 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1596 if (dst
.regClass() == v2b
) {
1597 Temp tmp
= bld
.tmp(v1
);
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1599 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1600 } else if (dst
.regClass() == v1
) {
1601 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1602 } else if (dst
.regClass() == v2
) {
1603 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1606 nir_print_instr(&instr
->instr
, stderr
);
1607 fprintf(stderr
, "\n");
1612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1613 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1614 if (dst
.regClass() == v2b
) {
1615 Temp tmp
= bld
.tmp(v1
);
1616 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1618 } else if (dst
.regClass() == v1
) {
1619 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1620 } else if (dst
.regClass() == v2
) {
1621 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1623 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1624 nir_print_instr(&instr
->instr
, stderr
);
1625 fprintf(stderr
, "\n");
1630 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1631 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1632 if (dst
.regClass() == v2b
) {
1633 Temp tmp
= bld
.tmp(v1
);
1634 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1635 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1637 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1639 } else if (dst
.regClass() == v1
) {
1640 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1641 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1643 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1644 } else if (dst
.regClass() == v2
) {
1645 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1646 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1647 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1650 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1651 nir_print_instr(&instr
->instr
, stderr
);
1652 fprintf(stderr
, "\n");
1657 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1658 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1659 if (dst
.regClass() == v2b
) {
1660 // TODO: check fp_mode.must_flush_denorms16_64
1661 Temp tmp
= bld
.tmp(v1
);
1662 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1663 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1664 } else if (dst
.regClass() == v1
) {
1665 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1666 } else if (dst
.regClass() == v2
) {
1667 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1668 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1669 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1671 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1675 nir_print_instr(&instr
->instr
, stderr
);
1676 fprintf(stderr
, "\n");
1681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1682 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1683 if (dst
.regClass() == v2b
) {
1684 // TODO: check fp_mode.must_flush_denorms16_64
1685 Temp tmp
= bld
.tmp(v1
);
1686 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1687 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1688 } else if (dst
.regClass() == v1
) {
1689 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1690 } else if (dst
.regClass() == v2
) {
1691 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1692 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1693 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1695 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1698 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1699 nir_print_instr(&instr
->instr
, stderr
);
1700 fprintf(stderr
, "\n");
1704 case nir_op_fmax3
: {
1705 if (dst
.regClass() == v2b
) {
1706 Temp tmp
= bld
.tmp(v1
);
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1708 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1709 } else if (dst
.regClass() == v1
) {
1710 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1712 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1713 nir_print_instr(&instr
->instr
, stderr
);
1714 fprintf(stderr
, "\n");
1718 case nir_op_fmin3
: {
1719 if (dst
.regClass() == v2b
) {
1720 Temp tmp
= bld
.tmp(v1
);
1721 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1722 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1723 } else if (dst
.regClass() == v1
) {
1724 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1726 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1727 nir_print_instr(&instr
->instr
, stderr
);
1728 fprintf(stderr
, "\n");
1732 case nir_op_fmed3
: {
1733 if (dst
.regClass() == v2b
) {
1734 Temp tmp
= bld
.tmp(v1
);
1735 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1736 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1737 } else if (dst
.regClass() == v1
) {
1738 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1740 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1741 nir_print_instr(&instr
->instr
, stderr
);
1742 fprintf(stderr
, "\n");
1746 case nir_op_umax3
: {
1747 if (dst
.size() == 1) {
1748 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1751 nir_print_instr(&instr
->instr
, stderr
);
1752 fprintf(stderr
, "\n");
1756 case nir_op_umin3
: {
1757 if (dst
.size() == 1) {
1758 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1760 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1761 nir_print_instr(&instr
->instr
, stderr
);
1762 fprintf(stderr
, "\n");
1766 case nir_op_umed3
: {
1767 if (dst
.size() == 1) {
1768 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1770 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1771 nir_print_instr(&instr
->instr
, stderr
);
1772 fprintf(stderr
, "\n");
1776 case nir_op_imax3
: {
1777 if (dst
.size() == 1) {
1778 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1780 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1781 nir_print_instr(&instr
->instr
, stderr
);
1782 fprintf(stderr
, "\n");
1786 case nir_op_imin3
: {
1787 if (dst
.size() == 1) {
1788 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1791 nir_print_instr(&instr
->instr
, stderr
);
1792 fprintf(stderr
, "\n");
1796 case nir_op_imed3
: {
1797 if (dst
.size() == 1) {
1798 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1801 nir_print_instr(&instr
->instr
, stderr
);
1802 fprintf(stderr
, "\n");
1806 case nir_op_cube_face_coord
: {
1807 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1808 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1809 emit_extract_vector(ctx
, in
, 1, v1
),
1810 emit_extract_vector(ctx
, in
, 2, v1
) };
1811 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1812 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1813 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1814 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1815 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1816 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1817 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1820 case nir_op_cube_face_index
: {
1821 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1822 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1823 emit_extract_vector(ctx
, in
, 1, v1
),
1824 emit_extract_vector(ctx
, in
, 2, v1
) };
1825 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1828 case nir_op_bcsel
: {
1829 emit_bcsel(ctx
, instr
, dst
);
1833 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1834 if (dst
.regClass() == v2b
) {
1835 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1836 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1837 } else if (dst
.regClass() == v1
) {
1838 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1839 } else if (dst
.regClass() == v2
) {
1840 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1843 nir_print_instr(&instr
->instr
, stderr
);
1844 fprintf(stderr
, "\n");
1849 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1850 if (dst
.regClass() == v2b
) {
1851 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1852 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1853 } else if (dst
.regClass() == v1
) {
1854 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1855 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1856 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1857 } else if (dst
.regClass() == v2
) {
1858 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1859 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1860 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1862 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1863 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1865 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1866 nir_print_instr(&instr
->instr
, stderr
);
1867 fprintf(stderr
, "\n");
1872 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1873 if (dst
.regClass() == v2b
) {
1874 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1875 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1876 } else if (dst
.regClass() == v1
) {
1877 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1878 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1879 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1880 } else if (dst
.regClass() == v2
) {
1881 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1882 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1883 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1884 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1885 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1886 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1895 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1896 if (dst
.regClass() == v2b
) {
1897 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1898 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1899 } else if (dst
.regClass() == v1
) {
1900 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1901 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1902 // TODO: confirm that this holds under any circumstances
1903 } else if (dst
.regClass() == v2
) {
1904 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1905 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1909 nir_print_instr(&instr
->instr
, stderr
);
1910 fprintf(stderr
, "\n");
1914 case nir_op_flog2
: {
1915 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1916 if (dst
.regClass() == v2b
) {
1917 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1918 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1919 } else if (dst
.regClass() == v1
) {
1920 emit_log2(ctx
, bld
, Definition(dst
), src
);
1922 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1923 nir_print_instr(&instr
->instr
, stderr
);
1924 fprintf(stderr
, "\n");
1929 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1930 if (dst
.regClass() == v2b
) {
1931 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1933 } else if (dst
.regClass() == v1
) {
1934 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1935 } else if (dst
.regClass() == v2
) {
1936 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1938 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1939 nir_print_instr(&instr
->instr
, stderr
);
1940 fprintf(stderr
, "\n");
1944 case nir_op_fexp2
: {
1945 if (dst
.regClass() == v2b
) {
1946 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1947 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1948 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1949 } else if (dst
.regClass() == v1
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1952 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1953 nir_print_instr(&instr
->instr
, stderr
);
1954 fprintf(stderr
, "\n");
1958 case nir_op_fsqrt
: {
1959 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1960 if (dst
.regClass() == v2b
) {
1961 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1963 } else if (dst
.regClass() == v1
) {
1964 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1965 } else if (dst
.regClass() == v2
) {
1966 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1968 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1969 nir_print_instr(&instr
->instr
, stderr
);
1970 fprintf(stderr
, "\n");
1974 case nir_op_ffract
: {
1975 if (dst
.regClass() == v2b
) {
1976 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1977 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1978 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1979 } else if (dst
.regClass() == v1
) {
1980 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1981 } else if (dst
.regClass() == v2
) {
1982 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1984 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1985 nir_print_instr(&instr
->instr
, stderr
);
1986 fprintf(stderr
, "\n");
1990 case nir_op_ffloor
: {
1991 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1992 if (dst
.regClass() == v2b
) {
1993 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1995 } else if (dst
.regClass() == v1
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1997 } else if (dst
.regClass() == v2
) {
1998 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2000 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2001 nir_print_instr(&instr
->instr
, stderr
);
2002 fprintf(stderr
, "\n");
2006 case nir_op_fceil
: {
2007 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2008 if (dst
.regClass() == v2b
) {
2009 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
2010 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2011 } else if (dst
.regClass() == v1
) {
2012 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2013 } else if (dst
.regClass() == v2
) {
2014 if (ctx
->options
->chip_class
>= GFX7
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2017 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2018 /* trunc = trunc(src0)
2019 * if (src0 > 0.0 && src0 != trunc)
2022 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2023 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2024 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2025 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2026 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2027 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2028 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2031 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2032 nir_print_instr(&instr
->instr
, stderr
);
2033 fprintf(stderr
, "\n");
2037 case nir_op_ftrunc
: {
2038 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2039 if (dst
.regClass() == v2b
) {
2040 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2041 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2042 } else if (dst
.regClass() == v1
) {
2043 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2044 } else if (dst
.regClass() == v2
) {
2045 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2053 case nir_op_fround_even
: {
2054 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2055 if (dst
.regClass() == v2b
) {
2056 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2057 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2058 } else if (dst
.regClass() == v1
) {
2059 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2060 } else if (dst
.regClass() == v2
) {
2061 if (ctx
->options
->chip_class
>= GFX7
) {
2062 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2064 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2065 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2066 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2068 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2069 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2070 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2071 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2072 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2073 tmp
= sub
->definitions
[0].getTemp();
2075 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2076 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2077 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2078 Temp cond
= vop3
->definitions
[0].getTemp();
2080 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2081 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2082 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2083 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2085 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2088 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2089 nir_print_instr(&instr
->instr
, stderr
);
2090 fprintf(stderr
, "\n");
2096 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2097 aco_ptr
<Instruction
> norm
;
2098 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2101 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2102 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2103 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2104 } else if (dst
.regClass() == v1
) {
2105 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2107 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2108 if (ctx
->options
->chip_class
< GFX9
)
2109 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2111 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2112 bld
.vop1(opcode
, Definition(dst
), tmp
);
2114 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2115 nir_print_instr(&instr
->instr
, stderr
);
2116 fprintf(stderr
, "\n");
2120 case nir_op_ldexp
: {
2121 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2122 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2123 if (dst
.regClass() == v2b
) {
2124 Temp tmp
= bld
.tmp(v1
);
2125 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2127 } else if (dst
.regClass() == v1
) {
2128 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2129 } else if (dst
.regClass() == v2
) {
2130 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2133 nir_print_instr(&instr
->instr
, stderr
);
2134 fprintf(stderr
, "\n");
2138 case nir_op_frexp_sig
: {
2139 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2140 if (dst
.regClass() == v2b
) {
2141 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2143 } else if (dst
.regClass() == v1
) {
2144 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2145 } else if (dst
.regClass() == v2
) {
2146 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2154 case nir_op_frexp_exp
: {
2155 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2157 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2158 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2159 convert_int(bld
, tmp
, 8, 32, true, dst
);
2160 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2161 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2162 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2163 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2165 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2166 nir_print_instr(&instr
->instr
, stderr
);
2167 fprintf(stderr
, "\n");
2171 case nir_op_fsign
: {
2172 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2173 if (dst
.regClass() == v2b
) {
2174 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2175 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2176 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2177 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2178 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2179 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2180 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2181 } else if (dst
.regClass() == v1
) {
2182 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2183 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2184 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2185 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2186 } else if (dst
.regClass() == v2
) {
2187 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2188 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2189 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2191 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2192 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2193 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2195 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2198 nir_print_instr(&instr
->instr
, stderr
);
2199 fprintf(stderr
, "\n");
2204 case nir_op_f2f16_rtne
: {
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2207 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2208 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2209 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2212 case nir_op_f2f16_rtz
: {
2213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2214 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2215 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2216 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2217 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2220 case nir_op_f2f32
: {
2221 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2222 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2223 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2224 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2226 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2227 nir_print_instr(&instr
->instr
, stderr
);
2228 fprintf(stderr
, "\n");
2232 case nir_op_f2f64
: {
2233 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2234 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2235 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2236 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2239 case nir_op_i2f16
: {
2240 assert(dst
.regClass() == v2b
);
2241 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2242 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2243 src
= convert_int(bld
, src
, 8, 16, true);
2244 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
), src
);
2245 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2248 case nir_op_i2f32
: {
2249 assert(dst
.size() == 1);
2250 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2251 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2252 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2253 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2256 case nir_op_i2f64
: {
2257 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2258 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2259 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2260 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2261 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2262 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 RegClass rc
= RegClass(src
.type(), 1);
2265 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2266 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2267 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2268 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2269 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2270 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2273 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2274 nir_print_instr(&instr
->instr
, stderr
);
2275 fprintf(stderr
, "\n");
2279 case nir_op_u2f16
: {
2280 assert(dst
.regClass() == v2b
);
2281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2282 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2283 src
= convert_int(bld
, src
, 8, 16, false);
2284 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
), src
);
2285 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2288 case nir_op_u2f32
: {
2289 assert(dst
.size() == 1);
2290 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2291 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2292 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2293 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2295 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2296 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2297 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2301 case nir_op_u2f64
: {
2302 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2303 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2304 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2305 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2306 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2308 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2309 RegClass rc
= RegClass(src
.type(), 1);
2310 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2311 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2312 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2313 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2314 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2315 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2317 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2318 nir_print_instr(&instr
->instr
, stderr
);
2319 fprintf(stderr
, "\n");
2324 case nir_op_f2i16
: {
2325 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2326 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2327 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2328 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2329 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2331 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2333 if (dst
.type() == RegType::vgpr
)
2334 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2336 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2340 case nir_op_f2u16
: {
2341 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2342 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2343 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2344 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2345 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2347 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2349 if (dst
.type() == RegType::vgpr
)
2350 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2352 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2355 case nir_op_f2i32
: {
2356 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2357 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2358 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2359 if (dst
.type() == RegType::vgpr
) {
2360 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2362 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2363 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2365 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2366 if (dst
.type() == RegType::vgpr
)
2367 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2369 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2370 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2372 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2373 if (dst
.type() == RegType::vgpr
)
2374 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2376 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2377 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2380 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2381 nir_print_instr(&instr
->instr
, stderr
);
2382 fprintf(stderr
, "\n");
2386 case nir_op_f2u32
: {
2387 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2388 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2389 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2390 if (dst
.type() == RegType::vgpr
) {
2391 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2393 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2394 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2396 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2397 if (dst
.type() == RegType::vgpr
)
2398 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2400 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2401 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2403 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2404 if (dst
.type() == RegType::vgpr
)
2405 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2407 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2408 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2412 nir_print_instr(&instr
->instr
, stderr
);
2413 fprintf(stderr
, "\n");
2417 case nir_op_f2i64
: {
2418 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2419 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2420 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2422 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2423 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2424 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2425 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2426 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2427 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2428 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2429 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2430 Temp new_exponent
= bld
.tmp(v1
);
2431 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2432 if (ctx
->program
->chip_class
>= GFX8
)
2433 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2435 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2436 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2437 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2438 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2439 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2440 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2441 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2442 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2443 Temp new_lower
= bld
.tmp(v1
);
2444 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2445 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2446 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2448 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2449 if (src
.type() == RegType::vgpr
)
2450 src
= bld
.as_uniform(src
);
2451 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2452 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2453 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2454 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2455 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2456 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2457 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2458 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2459 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2460 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2461 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2462 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2463 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2464 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2465 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2466 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2467 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2468 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2469 Temp borrow
= bld
.tmp(s1
);
2470 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2471 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2474 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2475 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2476 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2477 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2478 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2479 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2480 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2481 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2482 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2483 if (dst
.type() == RegType::sgpr
) {
2484 lower
= bld
.as_uniform(lower
);
2485 upper
= bld
.as_uniform(upper
);
2487 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2491 nir_print_instr(&instr
->instr
, stderr
);
2492 fprintf(stderr
, "\n");
2496 case nir_op_f2u64
: {
2497 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2498 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2499 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2501 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2502 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2503 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2504 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2505 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2506 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2507 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2508 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2509 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2510 Temp new_exponent
= bld
.tmp(v1
);
2511 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2512 if (ctx
->program
->chip_class
>= GFX8
)
2513 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2515 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2516 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2517 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2518 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2519 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2520 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2521 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2522 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2524 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2525 if (src
.type() == RegType::vgpr
)
2526 src
= bld
.as_uniform(src
);
2527 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2528 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2529 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2530 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2531 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2532 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2533 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2534 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2535 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2536 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2537 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2538 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2539 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2541 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2542 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2543 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2544 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2546 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2547 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2548 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2549 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2550 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2551 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2552 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2553 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2554 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2555 if (dst
.type() == RegType::sgpr
) {
2556 lower
= bld
.as_uniform(lower
);
2557 upper
= bld
.as_uniform(upper
);
2559 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2563 nir_print_instr(&instr
->instr
, stderr
);
2564 fprintf(stderr
, "\n");
2568 case nir_op_b2f16
: {
2569 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2570 assert(src
.regClass() == bld
.lm
);
2572 if (dst
.regClass() == s1
) {
2573 src
= bool_to_scalar_condition(ctx
, src
);
2574 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2575 } else if (dst
.regClass() == v2b
) {
2576 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2577 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2578 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2580 unreachable("Wrong destination register class for nir_op_b2f16.");
2584 case nir_op_b2f32
: {
2585 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2586 assert(src
.regClass() == bld
.lm
);
2588 if (dst
.regClass() == s1
) {
2589 src
= bool_to_scalar_condition(ctx
, src
);
2590 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2591 } else if (dst
.regClass() == v1
) {
2592 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2594 unreachable("Wrong destination register class for nir_op_b2f32.");
2598 case nir_op_b2f64
: {
2599 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2600 assert(src
.regClass() == bld
.lm
);
2602 if (dst
.regClass() == s2
) {
2603 src
= bool_to_scalar_condition(ctx
, src
);
2604 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2605 } else if (dst
.regClass() == v2
) {
2606 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2607 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2608 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2610 unreachable("Wrong destination register class for nir_op_b2f64.");
2617 case nir_op_i2i64
: {
2618 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2619 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2625 case nir_op_u2u64
: {
2626 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2627 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2631 case nir_op_b2i32
: {
2632 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2633 assert(src
.regClass() == bld
.lm
);
2635 if (dst
.regClass() == s1
) {
2636 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2637 bool_to_scalar_condition(ctx
, src
, dst
);
2638 } else if (dst
.regClass() == v1
) {
2639 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2641 unreachable("Invalid register class for b2i32");
2647 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2648 assert(dst
.regClass() == bld
.lm
);
2650 if (src
.type() == RegType::vgpr
) {
2651 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2652 assert(dst
.regClass() == bld
.lm
);
2653 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2654 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2656 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2658 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2659 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2661 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2662 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2664 bool_to_vector_condition(ctx
, tmp
, dst
);
2668 case nir_op_pack_64_2x32_split
: {
2669 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2670 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2672 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2675 case nir_op_unpack_64_2x32_split_x
:
2676 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2678 case nir_op_unpack_64_2x32_split_y
:
2679 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2681 case nir_op_unpack_32_2x16_split_x
:
2682 if (dst
.type() == RegType::vgpr
) {
2683 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2685 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2688 case nir_op_unpack_32_2x16_split_y
:
2689 if (dst
.type() == RegType::vgpr
) {
2690 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2692 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2695 case nir_op_pack_32_2x16_split
: {
2696 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2697 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2698 if (dst
.regClass() == v1
) {
2699 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2700 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2701 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2703 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2704 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2705 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2709 case nir_op_pack_half_2x16
: {
2710 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2712 if (dst
.regClass() == v1
) {
2713 Temp src0
= bld
.tmp(v1
);
2714 Temp src1
= bld
.tmp(v1
);
2715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2716 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2717 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2719 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2720 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2721 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2723 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2724 nir_print_instr(&instr
->instr
, stderr
);
2725 fprintf(stderr
, "\n");
2729 case nir_op_unpack_half_2x16_split_x
: {
2730 if (dst
.regClass() == v1
) {
2731 Builder
bld(ctx
->program
, ctx
->block
);
2732 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2734 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2735 nir_print_instr(&instr
->instr
, stderr
);
2736 fprintf(stderr
, "\n");
2740 case nir_op_unpack_half_2x16_split_y
: {
2741 if (dst
.regClass() == v1
) {
2742 Builder
bld(ctx
->program
, ctx
->block
);
2743 /* TODO: use SDWA here */
2744 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2745 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2748 nir_print_instr(&instr
->instr
, stderr
);
2749 fprintf(stderr
, "\n");
2753 case nir_op_fquantize2f16
: {
2754 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2755 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2758 if (ctx
->program
->chip_class
>= GFX8
) {
2759 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2760 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2761 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2763 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2764 * so compare the result and flush to 0 if it's smaller.
2766 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2767 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2768 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2769 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2770 cmp_res
= vop3
->definitions
[0].getTemp();
2773 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2774 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2775 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2777 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2782 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2783 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2785 if (dst
.regClass() == s1
) {
2786 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2787 } else if (dst
.regClass() == v1
) {
2788 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2791 nir_print_instr(&instr
->instr
, stderr
);
2792 fprintf(stderr
, "\n");
2796 case nir_op_bitfield_select
: {
2797 /* (mask & insert) | (~mask & base) */
2798 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2799 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2800 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2802 /* dst = (insert & bitmask) | (base & ~bitmask) */
2803 if (dst
.regClass() == s1
) {
2804 aco_ptr
<Instruction
> sop2
;
2805 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2806 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2808 if (const_insert
&& const_bitmask
) {
2809 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2811 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2812 lhs
= Operand(insert
);
2816 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2817 if (const_base
&& const_bitmask
) {
2818 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2820 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2821 rhs
= Operand(base
);
2824 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2826 } else if (dst
.regClass() == v1
) {
2827 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2828 base
= as_vgpr(ctx
, base
);
2829 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2830 insert
= as_vgpr(ctx
, insert
);
2832 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2835 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2836 nir_print_instr(&instr
->instr
, stderr
);
2837 fprintf(stderr
, "\n");
2843 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2844 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2845 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2847 if (dst
.type() == RegType::sgpr
) {
2849 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2850 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2851 if (const_offset
&& const_bits
) {
2852 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2853 extract
= Operand(const_extract
);
2857 width
= Operand(const_bits
->u32
<< 16);
2859 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2861 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2865 if (dst
.regClass() == s1
) {
2866 if (instr
->op
== nir_op_ubfe
)
2867 opcode
= aco_opcode::s_bfe_u32
;
2869 opcode
= aco_opcode::s_bfe_i32
;
2870 } else if (dst
.regClass() == s2
) {
2871 if (instr
->op
== nir_op_ubfe
)
2872 opcode
= aco_opcode::s_bfe_u64
;
2874 opcode
= aco_opcode::s_bfe_i64
;
2876 unreachable("Unsupported BFE bit size");
2879 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2883 if (dst
.regClass() == v1
) {
2884 if (instr
->op
== nir_op_ubfe
)
2885 opcode
= aco_opcode::v_bfe_u32
;
2887 opcode
= aco_opcode::v_bfe_i32
;
2889 unreachable("Unsupported BFE bit size");
2892 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2896 case nir_op_bit_count
: {
2897 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2898 if (src
.regClass() == s1
) {
2899 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2900 } else if (src
.regClass() == v1
) {
2901 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2902 } else if (src
.regClass() == v2
) {
2903 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2904 emit_extract_vector(ctx
, src
, 1, v1
),
2905 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2906 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2907 } else if (src
.regClass() == s2
) {
2908 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2910 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2911 nir_print_instr(&instr
->instr
, stderr
);
2912 fprintf(stderr
, "\n");
2917 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2921 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2925 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2929 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2941 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2942 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2944 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2945 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2949 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2950 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2952 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2953 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2957 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2961 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2966 case nir_op_fddx_fine
:
2967 case nir_op_fddy_fine
:
2968 case nir_op_fddx_coarse
:
2969 case nir_op_fddy_coarse
: {
2970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2971 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2972 if (instr
->op
== nir_op_fddx_fine
) {
2973 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2974 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2975 } else if (instr
->op
== nir_op_fddy_fine
) {
2976 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2977 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2979 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2980 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2981 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2983 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2987 if (ctx
->program
->chip_class
>= GFX8
) {
2988 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2989 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2991 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2992 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2993 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2995 emit_wqm(ctx
, tmp
, dst
, true);
2999 fprintf(stderr
, "Unknown NIR ALU instr: ");
3000 nir_print_instr(&instr
->instr
, stderr
);
3001 fprintf(stderr
, "\n");
3005 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3007 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3009 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3010 // which get truncated the lsb if double and msb if int
3011 // for now, we only use s_mov_b64 with 64bit inline constants
3012 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3013 assert(dst
.type() == RegType::sgpr
);
3015 Builder
bld(ctx
->program
, ctx
->block
);
3017 if (instr
->def
.bit_size
== 1) {
3018 assert(dst
.regClass() == bld
.lm
);
3019 int val
= instr
->value
[0].b
? -1 : 0;
3020 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3021 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3022 } else if (instr
->def
.bit_size
== 8) {
3023 /* ensure that the value is correctly represented in the low byte of the register */
3024 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3025 } else if (instr
->def
.bit_size
== 16) {
3026 /* ensure that the value is correctly represented in the low half of the register */
3027 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3028 } else if (dst
.size() == 1) {
3029 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3031 assert(dst
.size() != 1);
3032 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3033 if (instr
->def
.bit_size
== 64)
3034 for (unsigned i
= 0; i
< dst
.size(); i
++)
3035 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3037 for (unsigned i
= 0; i
< dst
.size(); i
++)
3038 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3040 vec
->definitions
[0] = Definition(dst
);
3041 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3045 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3047 uint32_t new_mask
= 0;
3048 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3049 if (mask
& (1u << i
))
3050 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3054 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3056 Builder
bld(ctx
->program
, ctx
->block
);
3057 if (offset
.isTemp()) {
3058 Temp tmp
[3] = {vec
, vec
, vec
};
3060 if (vec
.size() == 3) {
3061 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3063 } else if (vec
.size() == 2) {
3064 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3065 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3067 for (unsigned i
= 0; i
< dst
.size(); i
++)
3068 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3071 if (dst
.size() == 2)
3072 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3074 offset
= Operand(0u);
3077 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3078 bld
.copy(Definition(dst
), vec
);
3080 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3083 struct LoadEmitInfo
{
3086 unsigned num_components
;
3087 unsigned component_size
;
3088 Temp resource
= Temp(0, s1
);
3089 unsigned component_stride
= 0;
3090 unsigned const_offset
= 0;
3091 unsigned align_mul
= 0;
3092 unsigned align_offset
= 0;
3095 unsigned swizzle_component_size
= 0;
3096 barrier_interaction barrier
= barrier_none
;
3097 bool can_reorder
= true;
3098 Temp soffset
= Temp(0, s1
);
3101 using LoadCallback
= Temp(*)(
3102 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3103 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3105 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3106 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3108 unsigned load_size
= info
->num_components
* info
->component_size
;
3109 unsigned component_size
= info
->component_size
;
3111 unsigned num_vals
= 0;
3112 Temp vals
[info
->dst
.bytes()];
3114 unsigned const_offset
= info
->const_offset
;
3116 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3117 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3119 unsigned bytes_read
= 0;
3120 while (bytes_read
< load_size
) {
3121 unsigned bytes_needed
= load_size
- bytes_read
;
3123 /* add buffer for unaligned loads */
3124 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3127 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3128 if (info
->component_stride
) {
3129 assert(supports_8bit_16bit_loads
&& "unimplemented");
3133 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3134 bytes_needed
= align(bytes_needed
, 4);
3141 if (info
->swizzle_component_size
)
3142 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3143 if (info
->component_stride
)
3144 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3146 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3148 /* reduce constant offset */
3149 Operand offset
= info
->offset
;
3150 unsigned reduced_const_offset
= const_offset
;
3151 bool remove_const_offset_completely
= need_to_align_offset
;
3152 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3153 unsigned to_add
= const_offset
;
3154 if (remove_const_offset_completely
) {
3155 reduced_const_offset
= 0;
3157 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3158 reduced_const_offset
%= max_const_offset_plus_one
;
3160 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3161 if (offset
.isConstant()) {
3162 offset
= Operand(offset
.constantValue() + to_add
);
3163 } else if (offset_tmp
.regClass() == s1
) {
3164 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3165 offset_tmp
, Operand(to_add
));
3166 } else if (offset_tmp
.regClass() == v1
) {
3167 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3169 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3170 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3171 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3173 if (offset_tmp
.regClass() == s2
) {
3174 Temp carry
= bld
.tmp(s1
);
3175 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3176 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3177 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3179 Temp new_lo
= bld
.tmp(v1
);
3180 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3181 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3182 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3187 /* align offset down if needed */
3188 Operand aligned_offset
= offset
;
3189 if (need_to_align_offset
) {
3190 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3191 if (offset
.isConstant()) {
3192 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3193 } else if (offset_tmp
.regClass() == s1
) {
3194 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3195 } else if (offset_tmp
.regClass() == s2
) {
3196 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3197 } else if (offset_tmp
.regClass() == v1
) {
3198 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3199 } else if (offset_tmp
.regClass() == v2
) {
3200 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3202 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3203 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3206 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3207 bld
.copy(bld
.def(s1
), aligned_offset
);
3209 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3210 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3211 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3213 /* shift result right if needed */
3215 Operand
align((uint32_t)byte_align
);
3216 if (byte_align
== -1) {
3217 if (offset
.isConstant())
3218 align
= Operand(offset
.constantValue() % 4u);
3219 else if (offset
.size() == 2)
3220 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3225 if (align
.isTemp() || align
.constantValue()) {
3226 assert(val
.bytes() >= load_size
&& "unimplemented");
3227 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3228 if (val
.type() == RegType::sgpr
)
3229 byte_align_scalar(ctx
, val
, align
, new_val
);
3231 byte_align_vector(ctx
, val
, align
, new_val
);
3236 /* add result to list and advance */
3237 if (info
->component_stride
) {
3238 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3239 const_offset
+= info
->component_stride
;
3240 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3242 const_offset
+= val
.bytes();
3243 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3245 bytes_read
+= val
.bytes();
3246 vals
[num_vals
++] = val
;
3249 /* the callback wrote directly to dst */
3250 if (vals
[0] == info
->dst
) {
3251 assert(num_vals
== 1);
3252 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3256 /* create array of components */
3257 unsigned components_split
= 0;
3258 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3259 bool has_vgprs
= false;
3260 for (unsigned i
= 0; i
< num_vals
;) {
3262 unsigned num_tmps
= 0;
3263 unsigned tmp_size
= 0;
3264 RegType reg_type
= RegType::sgpr
;
3265 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3266 if (vals
[i
].type() == RegType::vgpr
)
3267 reg_type
= RegType::vgpr
;
3268 tmp_size
+= vals
[i
].bytes();
3269 tmp
[num_tmps
++] = vals
[i
++];
3272 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3273 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3274 for (unsigned i
= 0; i
< num_vals
; i
++)
3275 vec
->operands
[i
] = Operand(tmp
[i
]);
3276 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3277 vec
->definitions
[0] = Definition(tmp
[0]);
3278 bld
.insert(std::move(vec
));
3281 if (tmp
[0].bytes() % component_size
) {
3283 assert(i
== num_vals
);
3284 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3285 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3288 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3290 unsigned start
= components_split
;
3292 if (tmp_size
== elem_rc
.bytes()) {
3293 allocated_vec
[components_split
++] = tmp
[0];
3295 assert(tmp_size
% elem_rc
.bytes() == 0);
3296 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3297 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3298 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3299 Temp component
= bld
.tmp(elem_rc
);
3300 allocated_vec
[components_split
++] = component
;
3301 split
->definitions
[i
] = Definition(component
);
3303 split
->operands
[0] = Operand(tmp
[0]);
3304 bld
.insert(std::move(split
));
3307 /* try to p_as_uniform early so we can create more optimizable code and
3308 * also update allocated_vec */
3309 for (unsigned j
= start
; j
< components_split
; j
++) {
3310 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3311 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3312 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3316 /* concatenate components and p_as_uniform() result if needed */
3317 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3318 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3320 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3322 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3323 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3324 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3325 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3327 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3328 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3329 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3330 vec
->definitions
[0] = Definition(tmp
);
3331 bld
.insert(std::move(vec
));
3332 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3334 vec
->definitions
[0] = Definition(info
->dst
);
3335 bld
.insert(std::move(vec
));
3339 Operand
load_lds_size_m0(Builder
& bld
)
3341 /* TODO: m0 does not need to be initialized on GFX9+ */
3342 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3345 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3346 Temp offset
, unsigned bytes_needed
,
3347 unsigned align
, unsigned const_offset
,
3350 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3352 Operand m
= load_lds_size_m0(bld
);
3354 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3355 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3360 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3361 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3363 op
= aco_opcode::ds_read_b128
;
3364 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3367 op
= aco_opcode::ds_read2_b64
;
3368 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3370 op
= aco_opcode::ds_read_b96
;
3371 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3373 op
= aco_opcode::ds_read_b64
;
3374 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3377 op
= aco_opcode::ds_read2_b32
;
3378 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3380 op
= aco_opcode::ds_read_b32
;
3381 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3383 op
= aco_opcode::ds_read_u16
;
3386 op
= aco_opcode::ds_read_u8
;
3389 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3390 if (const_offset
>= max_offset_plus_one
) {
3391 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3392 const_offset
%= max_offset_plus_one
;
3396 const_offset
/= (size
/ 2u);
3398 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3399 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3401 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3403 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3406 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3411 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3413 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3414 Temp address
, unsigned base_offset
, unsigned align
)
3416 assert(util_is_power_of_two_nonzero(align
));
3418 Builder
bld(ctx
->program
, ctx
->block
);
3420 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3421 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3422 info
.align_mul
= align
;
3423 info
.align_offset
= 0;
3424 info
.barrier
= barrier_shared
;
3425 info
.can_reorder
= false;
3426 info
.const_offset
= base_offset
;
3427 emit_lds_load(ctx
, bld
, &info
);
3432 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3434 if (start
== 0 && size
== data
.size())
3435 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3437 unsigned size_hint
= 1;
3438 auto it
= ctx
->allocated_vec
.find(data
.id());
3439 if (it
!= ctx
->allocated_vec
.end())
3440 size_hint
= it
->second
[0].size();
3441 if (size
% size_hint
|| start
% size_hint
)
3448 for (unsigned i
= 0; i
< size
; i
++)
3449 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3452 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3454 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3455 for (unsigned i
= 0; i
< size
; i
++)
3456 vec
->operands
[i
] = Operand(elems
[i
]);
3457 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3458 vec
->definitions
[0] = Definition(res
);
3459 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3463 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3465 Builder
bld(ctx
->program
, ctx
->block
);
3466 unsigned bytes_written
= 0;
3467 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3468 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3470 while (bytes_written
< total_size
* 4) {
3471 unsigned todo
= total_size
* 4 - bytes_written
;
3472 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3473 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3475 aco_opcode op
= aco_opcode::last_opcode
;
3476 bool write2
= false;
3478 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3479 op
= aco_opcode::ds_write_b128
;
3481 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3482 op
= aco_opcode::ds_write2_b64
;
3485 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3486 op
= aco_opcode::ds_write_b96
;
3488 } else if (todo
>= 8 && aligned8
) {
3489 op
= aco_opcode::ds_write_b64
;
3491 } else if (todo
>= 8 && usable_write2
) {
3492 op
= aco_opcode::ds_write2_b32
;
3495 } else if (todo
>= 4) {
3496 op
= aco_opcode::ds_write_b32
;
3502 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3503 unsigned max_offset
= write2
? 1020 : 65535;
3504 Temp address_offset
= address
;
3505 if (offset
> max_offset
) {
3506 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3507 offset
= offset1
+ bytes_written
;
3509 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3512 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3513 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3514 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3516 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3517 bld
.ds(op
, address_offset
, val
, m
, offset
);
3520 bytes_written
+= size
* 4;
3524 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3525 Temp address
, unsigned base_offset
, unsigned align
)
3527 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3528 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3530 Builder
bld(ctx
->program
, ctx
->block
);
3531 Operand m
= load_lds_size_m0(bld
);
3533 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3534 assert(wrmask
<= 0x0f);
3535 int start
[2], count
[2];
3536 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3537 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3538 assert(wrmask
== 0);
3540 /* one combined store is sufficient */
3541 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3542 Temp address_offset
= address
;
3543 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3544 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3548 assert(count
[0] == 1);
3549 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3551 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3552 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3553 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3554 base_offset
= base_offset
/ elem_size_bytes
;
3555 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3556 base_offset
+ start
[0], base_offset
+ start
[1]);
3560 for (unsigned i
= 0; i
< 2; i
++) {
3564 unsigned elem_size_words
= elem_size_bytes
/ 4;
3565 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3566 base_offset
, start
[i
] * elem_size_bytes
, align
);
3571 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3573 unsigned align
= 16;
3575 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3581 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3582 unsigned split_cnt
= 0u, Temp dst
= Temp())
3584 Builder
bld(ctx
->program
, ctx
->block
);
3585 unsigned dword_size
= elem_size_bytes
/ 4;
3588 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3590 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3591 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3592 instr
->definitions
[0] = Definition(dst
);
3594 for (unsigned i
= 0; i
< cnt
; ++i
) {
3596 assert(arr
[i
].size() == dword_size
);
3597 allocated_vec
[i
] = arr
[i
];
3598 instr
->operands
[i
] = Operand(arr
[i
]);
3600 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3601 allocated_vec
[i
] = zero
;
3602 instr
->operands
[i
] = Operand(zero
);
3606 bld
.insert(std::move(instr
));
3609 emit_split_vector(ctx
, dst
, split_cnt
);
3611 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3616 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3618 if (const_offset
>= 4096) {
3619 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3620 const_offset
%= 4096u;
3623 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3624 else if (unlikely(voffset
.regClass() == s1
))
3625 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3626 else if (likely(voffset
.regClass() == v1
))
3627 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3629 unreachable("Unsupported register class of voffset");
3632 return const_offset
;
3635 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3636 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3639 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3640 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3642 Builder
bld(ctx
->program
, ctx
->block
);
3643 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3644 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3646 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3647 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3648 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3649 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3650 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3652 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3655 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3656 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3657 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3659 Builder
bld(ctx
->program
, ctx
->block
);
3660 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3663 if (elem_size_bytes
== 8) {
3664 elem_size_bytes
= 4;
3665 write_mask
= widen_mask(write_mask
, 2);
3668 while (write_mask
) {
3671 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3676 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3677 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3679 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3680 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3683 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3684 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3694 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3695 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3697 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3698 assert(size_dwords
>= 1 && size_dwords
<= 4);
3700 Builder
bld(ctx
->program
, ctx
->block
);
3701 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3702 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3703 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3705 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3706 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3707 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3708 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3709 /* disable_wqm */ false, /* glc */ true,
3710 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3712 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3717 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3718 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3719 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3721 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3722 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3723 assert(!!stride
!= allow_combining
);
3725 Builder
bld(ctx
->program
, ctx
->block
);
3726 unsigned split_cnt
= num_components
;
3728 if (elem_size_bytes
== 8) {
3729 elem_size_bytes
= 4;
3730 num_components
*= 2;
3734 stride
= elem_size_bytes
;
3736 unsigned load_size
= 1;
3737 if (allow_combining
) {
3738 if ((num_components
% 4) == 0)
3740 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3742 else if ((num_components
% 2) == 0)
3746 unsigned num_loads
= num_components
/ load_size
;
3747 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3749 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3750 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3751 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3754 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3757 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3759 Builder
bld(ctx
->program
, ctx
->block
);
3760 Temp offset
= base_offset
.first
;
3761 unsigned const_offset
= base_offset
.second
;
3763 if (!nir_src_is_const(*off_src
)) {
3764 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3767 /* Calculate indirect offset with stride */
3768 if (likely(indirect_offset_arg
.regClass() == v1
))
3769 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3770 else if (indirect_offset_arg
.regClass() == s1
)
3771 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3773 unreachable("Unsupported register class of indirect offset");
3775 /* Add to the supplied base offset */
3776 if (offset
.id() == 0)
3777 offset
= with_stride
;
3778 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3779 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3780 else if (offset
.size() == 1 && with_stride
.size() == 1)
3781 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3783 unreachable("Unsupported register class of indirect offset");
3785 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3786 const_offset
+= const_offset_arg
* stride
;
3789 return std::make_pair(offset
, const_offset
);
3792 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3794 Builder
bld(ctx
->program
, ctx
->block
);
3797 if (off1
.first
.id() && off2
.first
.id()) {
3798 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3799 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3800 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3801 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3803 unreachable("Unsupported register class of indirect offset");
3805 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3808 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3811 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3813 Builder
bld(ctx
->program
, ctx
->block
);
3814 unsigned const_offset
= offs
.second
* multiplier
;
3816 if (!offs
.first
.id())
3817 return std::make_pair(offs
.first
, const_offset
);
3819 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3820 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3821 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
3823 return std::make_pair(offset
, const_offset
);
3826 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3828 Builder
bld(ctx
->program
, ctx
->block
);
3830 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3831 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3832 /* component is in bytes */
3833 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3835 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3836 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3837 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3840 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3842 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3845 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3847 Builder
bld(ctx
->program
, ctx
->block
);
3849 switch (ctx
->shader
->info
.stage
) {
3850 case MESA_SHADER_TESS_CTRL
:
3851 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3852 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3853 case MESA_SHADER_TESS_EVAL
:
3854 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3856 unreachable("Unsupported stage in get_tess_rel_patch_id");
3860 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3862 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3863 Builder
bld(ctx
->program
, ctx
->block
);
3865 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3866 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3868 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3870 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3871 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3873 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3874 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3875 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3877 return offset_mul(ctx
, offs
, 4u);
3880 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3882 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3883 Builder
bld(ctx
->program
, ctx
->block
);
3885 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3886 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3887 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3888 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3889 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3890 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3892 std::pair
<Temp
, unsigned> offs
= instr
3893 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3894 : std::make_pair(Temp(), 0u);
3896 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3897 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3902 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3903 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3905 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3906 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3908 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3909 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3915 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3917 Builder
bld(ctx
->program
, ctx
->block
);
3919 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3920 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3922 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3924 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3925 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3926 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3928 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3929 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3934 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3936 Builder
bld(ctx
->program
, ctx
->block
);
3938 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3939 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3940 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3942 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3943 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3944 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3945 unsigned attr_stride
= ctx
->tcs_num_patches
;
3947 std::pair
<Temp
, unsigned> offs
= instr
3948 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3949 : std::make_pair(Temp(), 0u);
3951 if (const_base_offset
)
3952 offs
.second
+= const_base_offset
* attr_stride
;
3954 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3955 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
3956 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3961 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3966 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3967 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3969 if (!nir_src_is_const(*off_src
)) {
3975 off
+= nir_src_as_uint(*off_src
) * 16u;
3978 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3979 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3986 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3988 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3989 unsigned component
= nir_intrinsic_component(instr
);
3990 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3992 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3993 if (off_instr
->type
!= nir_instr_type_load_const
)
3996 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3997 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3999 if (instr
->src
[0].ssa
->bit_size
== 64)
4000 write_mask
= widen_mask(write_mask
, 2);
4002 for (unsigned i
= 0; i
< 8; ++i
) {
4003 if (write_mask
& (1 << i
)) {
4004 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4005 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
4013 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4015 /* Only TCS per-vertex inputs are supported by this function.
4016 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4018 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4021 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4022 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4023 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4024 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4025 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4026 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4031 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4032 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4033 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4038 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4040 Builder
bld(ctx
->program
, ctx
->block
);
4042 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4043 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4044 bool indirect_write
;
4045 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4046 if (temp_only_input
&& !indirect_write
)
4050 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4051 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4052 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4053 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4055 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4056 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4057 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4058 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4059 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4063 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4064 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4065 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4066 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4067 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4068 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4069 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4070 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4071 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4072 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4073 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4074 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4075 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4077 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
4078 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4079 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
4081 unreachable("Invalid LS or ES stage");
4084 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4085 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4086 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4090 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4095 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4096 return off
== ctx
->tcs_tess_lvl_out_loc
||
4097 off
== ctx
->tcs_tess_lvl_in_loc
;
4101 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4103 uint64_t mask
= per_vertex
4104 ? ctx
->program
->info
->tcs
.tes_inputs_read
4105 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4107 bool indirect_write
= false;
4108 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4109 return indirect_write
|| output_read_by_tes
;
4112 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4114 uint64_t mask
= per_vertex
4115 ? ctx
->shader
->info
.outputs_read
4116 : ctx
->shader
->info
.patch_outputs_read
;
4118 bool indirect_write
= false;
4119 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4120 return indirect_write
|| output_read
;
4123 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4125 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4126 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4128 Builder
bld(ctx
->program
, ctx
->block
);
4130 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4131 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4132 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4134 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4135 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4136 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4138 if (write_to_vmem
) {
4139 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4140 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4141 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4143 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4144 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4145 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4149 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4150 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4151 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4155 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4157 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4158 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4160 Builder
bld(ctx
->program
, ctx
->block
);
4162 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4163 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4164 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4165 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4167 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4170 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4172 if (ctx
->stage
== vertex_vs
||
4173 ctx
->stage
== tess_eval_vs
||
4174 ctx
->stage
== fragment_fs
||
4175 ctx
->stage
== ngg_vertex_gs
||
4176 ctx
->stage
== ngg_tess_eval_gs
||
4177 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4178 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4179 if (!stored_to_temps
) {
4180 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4181 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4182 fprintf(stderr
, "\n");
4185 } else if (ctx
->stage
== vertex_es
||
4186 ctx
->stage
== vertex_ls
||
4187 ctx
->stage
== tess_eval_es
||
4188 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4189 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4190 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4191 visit_store_ls_or_es_output(ctx
, instr
);
4192 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4193 visit_store_tcs_output(ctx
, instr
, false);
4195 unreachable("Shader stage not implemented");
4199 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4201 visit_load_tcs_output(ctx
, instr
, false);
4204 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4206 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4207 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4209 Builder
bld(ctx
->program
, ctx
->block
);
4210 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4211 if (ctx
->program
->has_16bank_lds
)
4212 interp_p1
.instr
->operands
[0].setLateKill(true);
4213 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4216 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4218 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4219 for (unsigned i
= 0; i
< num_components
; i
++)
4220 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4221 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4222 assert(num_components
== 4);
4223 Builder
bld(ctx
->program
, ctx
->block
);
4224 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4227 for (Operand
& op
: vec
->operands
)
4228 op
= op
.isUndefined() ? Operand(0u) : op
;
4230 vec
->definitions
[0] = Definition(dst
);
4231 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4232 emit_split_vector(ctx
, dst
, num_components
);
4236 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4238 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4239 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4240 unsigned idx
= nir_intrinsic_base(instr
);
4241 unsigned component
= nir_intrinsic_component(instr
);
4242 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4244 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4246 assert(offset
->u32
== 0);
4248 /* the lower 15bit of the prim_mask contain the offset into LDS
4249 * while the upper bits contain the number of prims */
4250 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4251 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4252 Builder
bld(ctx
->program
, ctx
->block
);
4253 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4254 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4255 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4256 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4257 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4260 if (instr
->dest
.ssa
.num_components
== 1) {
4261 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4263 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4264 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4266 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4267 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4268 vec
->operands
[i
] = Operand(tmp
);
4270 vec
->definitions
[0] = Definition(dst
);
4271 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4275 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4276 unsigned offset
, unsigned stride
, unsigned channels
)
4278 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4279 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4281 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4282 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4285 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4286 unsigned offset
, unsigned stride
, unsigned *channels
)
4288 if (!vtx_info
->chan_byte_size
) {
4289 *channels
= vtx_info
->num_channels
;
4290 return vtx_info
->chan_format
;
4293 unsigned num_channels
= *channels
;
4294 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4295 unsigned new_channels
= num_channels
+ 1;
4296 /* first, assume more loads is worse and try using a larger data format */
4297 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4299 /* don't make the attribute potentially out-of-bounds */
4300 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4304 if (new_channels
== 5) {
4305 /* then try decreasing load size (at the cost of more loads) */
4306 new_channels
= *channels
;
4307 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4311 if (new_channels
< *channels
)
4312 *channels
= new_channels
;
4313 num_channels
= new_channels
;
4316 switch (vtx_info
->chan_format
) {
4317 case V_008F0C_BUF_DATA_FORMAT_8
:
4318 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4319 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4320 case V_008F0C_BUF_DATA_FORMAT_16
:
4321 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4322 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4323 case V_008F0C_BUF_DATA_FORMAT_32
:
4324 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4325 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4327 unreachable("shouldn't reach here");
4328 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4331 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4332 * so we may need to fix it up. */
4333 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4335 Builder
bld(ctx
->program
, ctx
->block
);
4337 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4338 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4340 /* For the integer-like cases, do a natural sign extension.
4342 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4343 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4346 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4347 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4349 /* Convert back to the right type. */
4350 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4351 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4352 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4353 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4354 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4355 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4361 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4363 Builder
bld(ctx
->program
, ctx
->block
);
4364 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4365 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4367 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4368 if (off_instr
->type
!= nir_instr_type_load_const
) {
4369 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4370 nir_print_instr(off_instr
, stderr
);
4371 fprintf(stderr
, "\n");
4373 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4375 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4377 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4378 unsigned component
= nir_intrinsic_component(instr
);
4379 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4380 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4381 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4382 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4384 unsigned dfmt
= attrib_format
& 0xf;
4385 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4386 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4388 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4389 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4390 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4391 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4393 num_channels
= MAX2(num_channels
, 3);
4395 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4396 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4399 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4400 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4401 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4403 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4405 Temp divided
= bld
.tmp(v1
);
4406 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4407 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4409 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4412 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4415 index
= bld
.vadd32(bld
.def(v1
),
4416 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4417 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4420 Temp channels
[num_channels
];
4421 unsigned channel_start
= 0;
4422 bool direct_fetch
= false;
4424 /* skip unused channels at the start */
4425 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4426 channel_start
= ffs(mask
) - 1;
4427 for (unsigned i
= 0; i
< channel_start
; i
++)
4428 channels
[i
] = Temp(0, s1
);
4429 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4430 num_channels
= 3 - (ffs(mask
) - 1);
4434 while (channel_start
< num_channels
) {
4435 unsigned fetch_size
= num_channels
- channel_start
;
4436 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4437 bool expanded
= false;
4439 /* use MUBUF when possible to avoid possible alignment issues */
4440 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4441 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4442 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4443 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4444 vtx_info
->chan_byte_size
== 4;
4445 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4447 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4449 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4450 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4456 Temp fetch_index
= index
;
4457 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4458 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4459 fetch_offset
= fetch_offset
% attrib_stride
;
4462 Operand
soffset(0u);
4463 if (fetch_offset
>= 4096) {
4464 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4465 fetch_offset
%= 4096;
4469 switch (fetch_size
) {
4471 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4474 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4477 assert(ctx
->options
->chip_class
>= GFX7
||
4478 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4479 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4482 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4485 unreachable("Unimplemented load_input vector size");
4489 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4490 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4491 num_channels
<= 3)) {
4492 direct_fetch
= true;
4495 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4499 Instruction
*mubuf
= bld
.mubuf(opcode
,
4500 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4501 fetch_offset
, false, true).instr
;
4502 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4504 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4505 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4506 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4507 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4510 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4512 if (fetch_size
== 1) {
4513 channels
[channel_start
] = fetch_dst
;
4515 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4516 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4519 channel_start
+= fetch_size
;
4522 if (!direct_fetch
) {
4523 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4524 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4526 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4527 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4528 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4530 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4531 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4532 unsigned num_temp
= 0;
4533 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4534 unsigned idx
= i
+ component
;
4535 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4536 Temp channel
= channels
[swizzle
[idx
]];
4537 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4538 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4539 vec
->operands
[i
] = Operand(channel
);
4543 } else if (is_float
&& idx
== 3) {
4544 vec
->operands
[i
] = Operand(0x3f800000u
);
4545 } else if (!is_float
&& idx
== 3) {
4546 vec
->operands
[i
] = Operand(1u);
4548 vec
->operands
[i
] = Operand(0u);
4551 vec
->definitions
[0] = Definition(dst
);
4552 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4553 emit_split_vector(ctx
, dst
, dst
.size());
4555 if (num_temp
== dst
.size())
4556 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4558 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4559 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4560 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4561 if (off_instr
->type
!= nir_instr_type_load_const
||
4562 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4563 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4564 nir_print_instr(off_instr
, stderr
);
4565 fprintf(stderr
, "\n");
4568 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4569 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4571 assert(offset
->u32
== 0);
4573 /* the lower 15bit of the prim_mask contain the offset into LDS
4574 * while the upper bits contain the number of prims */
4575 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4576 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4577 Builder
bld(ctx
->program
, ctx
->block
);
4578 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4579 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4580 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4581 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4582 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4585 unsigned idx
= nir_intrinsic_base(instr
);
4586 unsigned component
= nir_intrinsic_component(instr
);
4587 unsigned vertex_id
= 2; /* P0 */
4589 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4590 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4591 switch (src0
->u32
) {
4593 vertex_id
= 2; /* P0 */
4596 vertex_id
= 0; /* P10 */
4599 vertex_id
= 1; /* P20 */
4602 unreachable("invalid vertex index");
4606 if (dst
.size() == 1) {
4607 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4609 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4610 for (unsigned i
= 0; i
< dst
.size(); i
++)
4611 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4612 vec
->definitions
[0] = Definition(dst
);
4613 bld
.insert(std::move(vec
));
4616 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4617 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4618 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4619 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4620 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4622 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4624 unreachable("Shader stage not implemented");
4628 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4630 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4632 Builder
bld(ctx
->program
, ctx
->block
);
4633 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4636 if (!nir_src_is_const(*vertex_src
)) {
4637 /* better code could be created, but this case probably doesn't happen
4638 * much in practice */
4639 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4640 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4643 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4644 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4646 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4648 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4651 if (vertex_offset
.id()) {
4652 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4653 Operand(i
), indirect_vertex
);
4654 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4656 vertex_offset
= elem
;
4660 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4661 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4663 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4664 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4665 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4666 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4667 Operand((vertex
% 2u) * 16u), Operand(16u));
4669 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4672 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4673 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4674 return offset_mul(ctx
, offs
, 4u);
4677 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4679 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4681 Builder
bld(ctx
->program
, ctx
->block
);
4682 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4683 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4685 if (ctx
->stage
== geometry_gs
) {
4686 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4687 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4688 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4689 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4690 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4691 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4692 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4694 unreachable("Unsupported GS stage.");
4698 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4700 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4702 Builder
bld(ctx
->program
, ctx
->block
);
4703 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4705 if (load_input_from_temps(ctx
, instr
, dst
))
4708 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4709 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4710 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4712 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4715 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4717 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4719 Builder
bld(ctx
->program
, ctx
->block
);
4721 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4722 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4723 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4725 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4726 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4728 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4731 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4733 switch (ctx
->shader
->info
.stage
) {
4734 case MESA_SHADER_GEOMETRY
:
4735 visit_load_gs_per_vertex_input(ctx
, instr
);
4737 case MESA_SHADER_TESS_CTRL
:
4738 visit_load_tcs_per_vertex_input(ctx
, instr
);
4740 case MESA_SHADER_TESS_EVAL
:
4741 visit_load_tes_per_vertex_input(ctx
, instr
);
4744 unreachable("Unimplemented shader stage");
4748 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4750 visit_load_tcs_output(ctx
, instr
, true);
4753 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4755 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4756 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4758 visit_store_tcs_output(ctx
, instr
, true);
4761 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4763 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4765 Builder
bld(ctx
->program
, ctx
->block
);
4766 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4768 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4769 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4772 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4773 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4774 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4775 tes_w
= Operand(tmp
);
4778 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4779 emit_split_vector(ctx
, tess_coord
, 3);
4782 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4784 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4785 Builder
bld(ctx
->program
, ctx
->block
);
4786 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4787 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4788 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4791 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4795 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4797 Builder
bld(ctx
->program
, ctx
->block
);
4798 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4799 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4800 index
= bld
.as_uniform(index
);
4801 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4802 unsigned binding
= nir_intrinsic_binding(instr
);
4805 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4806 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4807 unsigned offset
= layout
->binding
[binding
].offset
;
4809 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4810 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4811 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4812 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4813 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4816 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4817 stride
= layout
->binding
[binding
].size
;
4820 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4821 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4823 if (nir_const_index
) {
4824 const_index
= const_index
* stride
;
4825 } else if (index
.type() == RegType::vgpr
) {
4826 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4827 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4829 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4833 if (nir_const_index
) {
4834 const_index
= const_index
+ offset
;
4835 } else if (index
.type() == RegType::vgpr
) {
4836 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4838 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4842 if (nir_const_index
&& const_index
== 0) {
4844 } else if (index
.type() == RegType::vgpr
) {
4845 index
= bld
.vadd32(bld
.def(v1
),
4846 nir_const_index
? Operand(const_index
) : Operand(index
),
4849 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4850 nir_const_index
? Operand(const_index
) : Operand(index
),
4854 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4857 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4858 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4859 bool glc
=false, bool readonly
=true)
4861 Builder
bld(ctx
->program
, ctx
->block
);
4862 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4863 unsigned num_bytes
= num_components
* component_size
;
4866 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4867 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4868 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4869 unsigned const_offset
= 0;
4871 /* for small bit sizes add buffer for unaligned loads */
4874 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4879 Temp lower
= Temp();
4880 if (num_bytes
> 16) {
4881 assert(num_components
== 3 || num_components
== 4);
4882 op
= aco_opcode::buffer_load_dwordx4
;
4883 lower
= bld
.tmp(v4
);
4884 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4885 mubuf
->definitions
[0] = Definition(lower
);
4886 mubuf
->operands
[0] = Operand(rsrc
);
4887 mubuf
->operands
[1] = vaddr
;
4888 mubuf
->operands
[2] = soffset
;
4889 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4892 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4893 mubuf
->can_reorder
= readonly
;
4894 bld
.insert(std::move(mubuf
));
4895 emit_split_vector(ctx
, lower
, 2);
4898 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4899 /* GFX6 doesn't support loading vec3, expand to vec4. */
4903 switch (num_bytes
) {
4905 op
= aco_opcode::buffer_load_ubyte
;
4908 op
= aco_opcode::buffer_load_ushort
;
4912 op
= aco_opcode::buffer_load_dword
;
4918 op
= aco_opcode::buffer_load_dwordx2
;
4922 assert(ctx
->options
->chip_class
> GFX6
);
4923 op
= aco_opcode::buffer_load_dwordx3
;
4926 op
= aco_opcode::buffer_load_dwordx4
;
4929 unreachable("Load SSBO not implemented for this size.");
4931 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4932 mubuf
->operands
[0] = Operand(rsrc
);
4933 mubuf
->operands
[1] = vaddr
;
4934 mubuf
->operands
[2] = soffset
;
4935 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4938 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4939 mubuf
->can_reorder
= readonly
;
4940 mubuf
->offset
= const_offset
;
4941 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4943 if (component_size
< 4) {
4944 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4945 instr
->definitions
[0] = Definition(vec
);
4946 bld
.insert(std::move(instr
));
4948 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4949 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4950 Temp tmp
[3] = {vec
, vec
, vec
};
4952 if (vec
.size() == 3) {
4953 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4954 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4955 } else if (vec
.size() == 2) {
4956 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4957 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4959 for (unsigned i
= 0; i
< dst
.size(); i
++)
4960 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4963 if (dst
.size() == 2)
4964 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4969 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4970 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4972 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4977 } else if (dst
.size() > 4) {
4978 assert(lower
!= Temp());
4979 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4980 instr
->definitions
[0] = Definition(upper
);
4981 bld
.insert(std::move(instr
));
4982 if (dst
.size() == 8)
4983 emit_split_vector(ctx
, upper
, 2);
4984 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4985 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4986 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4987 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4988 if (dst
.size() == 8)
4989 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4990 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4991 Temp vec
= bld
.tmp(v4
);
4992 instr
->definitions
[0] = Definition(vec
);
4993 bld
.insert(std::move(instr
));
4994 emit_split_vector(ctx
, vec
, 4);
4996 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4997 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4998 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4999 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
5002 if (dst
.type() == RegType::sgpr
) {
5003 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5004 instr
->definitions
[0] = Definition(vec
);
5005 bld
.insert(std::move(instr
));
5006 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
5008 instr
->definitions
[0] = Definition(dst
);
5009 bld
.insert(std::move(instr
));
5010 emit_split_vector(ctx
, dst
, num_components
);
5013 /* for small bit sizes add buffer for unaligned loads */
5015 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
5017 switch (num_bytes
) {
5022 op
= aco_opcode::s_buffer_load_dword
;
5028 op
= aco_opcode::s_buffer_load_dwordx2
;
5033 op
= aco_opcode::s_buffer_load_dwordx4
;
5037 op
= aco_opcode::s_buffer_load_dwordx8
;
5040 unreachable("Load SSBO not implemented for this size.");
5042 offset
= bld
.as_uniform(offset
);
5043 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
5044 load
->operands
[0] = Operand(rsrc
);
5045 load
->operands
[1] = Operand(offset
);
5046 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
5047 load
->definitions
[0] = Definition(dst
);
5050 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
5051 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
5052 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
5054 /* adjust misaligned small bit size loads */
5056 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
5057 load
->definitions
[0] = Definition(vec
);
5058 bld
.insert(std::move(load
));
5059 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
5060 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5063 } else if (dst
.size() == 3) {
5064 Temp vec
= bld
.tmp(s4
);
5065 load
->definitions
[0] = Definition(vec
);
5066 bld
.insert(std::move(load
));
5067 emit_split_vector(ctx
, vec
, 4);
5069 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5070 emit_extract_vector(ctx
, vec
, 0, s1
),
5071 emit_extract_vector(ctx
, vec
, 1, s1
),
5072 emit_extract_vector(ctx
, vec
, 2, s1
));
5073 } else if (dst
.size() == 6) {
5074 Temp vec
= bld
.tmp(s8
);
5075 load
->definitions
[0] = Definition(vec
);
5076 bld
.insert(std::move(load
));
5077 emit_split_vector(ctx
, vec
, 4);
5079 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5080 emit_extract_vector(ctx
, vec
, 0, s2
),
5081 emit_extract_vector(ctx
, vec
, 1, s2
),
5082 emit_extract_vector(ctx
, vec
, 2, s2
));
5084 bld
.insert(std::move(load
));
5086 emit_split_vector(ctx
, dst
, num_components
);
5090 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5092 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5093 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5095 Builder
bld(ctx
->program
, ctx
->block
);
5097 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5098 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5099 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5100 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5102 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5103 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5104 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5105 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5106 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5107 if (ctx
->options
->chip_class
>= GFX10
) {
5108 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5109 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5110 S_008F0C_RESOURCE_LEVEL(1);
5112 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5113 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5115 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5116 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5117 Operand(0xFFFFFFFFu
),
5118 Operand(desc_type
));
5119 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5120 rsrc
, upper_dwords
);
5122 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5123 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5125 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5128 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5129 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5130 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5132 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
5135 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5137 Builder
bld(ctx
->program
, ctx
->block
);
5138 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5139 unsigned offset
= nir_intrinsic_base(instr
);
5140 unsigned count
= instr
->dest
.ssa
.num_components
;
5141 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5143 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5144 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5145 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5146 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5147 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5148 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5149 for (unsigned i
= 0; i
< count
; ++i
) {
5150 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5151 vec
->operands
[i
] = Operand
{elems
[i
]};
5153 vec
->definitions
[0] = Definition(dst
);
5154 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5155 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5160 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5161 if (offset
!= 0) // TODO check if index != 0 as well
5162 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5163 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5166 bool aligned
= true;
5168 if (instr
->dest
.ssa
.bit_size
== 8) {
5169 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5170 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5172 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5173 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5174 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5176 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5181 switch (vec
.size()) {
5183 op
= aco_opcode::s_load_dword
;
5186 op
= aco_opcode::s_load_dwordx2
;
5192 op
= aco_opcode::s_load_dwordx4
;
5198 op
= aco_opcode::s_load_dwordx8
;
5201 unreachable("unimplemented or forbidden load_push_constant.");
5204 bld
.smem(op
, Definition(vec
), ptr
, index
);
5207 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5208 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5213 emit_split_vector(ctx
, vec
, 4);
5214 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5215 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5216 emit_extract_vector(ctx
, vec
, 0, rc
),
5217 emit_extract_vector(ctx
, vec
, 1, rc
),
5218 emit_extract_vector(ctx
, vec
, 2, rc
));
5221 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5224 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5226 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5228 Builder
bld(ctx
->program
, ctx
->block
);
5230 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5231 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5232 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5233 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5234 if (ctx
->options
->chip_class
>= GFX10
) {
5235 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5236 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5237 S_008F0C_RESOURCE_LEVEL(1);
5239 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5240 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5243 unsigned base
= nir_intrinsic_base(instr
);
5244 unsigned range
= nir_intrinsic_range(instr
);
5246 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5247 if (base
&& offset
.type() == RegType::sgpr
)
5248 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5249 else if (base
&& offset
.type() == RegType::vgpr
)
5250 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5252 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5253 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5254 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5255 Operand(desc_type
));
5256 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5257 // TODO: get alignment information for subdword constants
5258 unsigned byte_align
= size
< 4 ? -1 : 0;
5259 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
5262 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5264 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5265 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5267 ctx
->program
->needs_exact
= true;
5269 // TODO: optimize uniform conditions
5270 Builder
bld(ctx
->program
, ctx
->block
);
5271 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5272 assert(src
.regClass() == bld
.lm
);
5273 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5274 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5275 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5279 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5281 Builder
bld(ctx
->program
, ctx
->block
);
5283 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5284 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5286 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5287 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5289 if (ctx
->block
->loop_nest_depth
&&
5290 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5291 /* we handle discards the same way as jump instructions */
5292 append_logical_end(ctx
->block
);
5294 /* in loops, discard behaves like break */
5295 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5296 ctx
->block
->kind
|= block_kind_discard
;
5299 /* uniform discard - loop ends here */
5300 assert(nir_instr_is_last(&instr
->instr
));
5301 ctx
->block
->kind
|= block_kind_uniform
;
5302 ctx
->cf_info
.has_branch
= true;
5303 bld
.branch(aco_opcode::p_branch
);
5304 add_linear_edge(ctx
->block
->index
, linear_target
);
5308 /* we add a break right behind the discard() instructions */
5309 ctx
->block
->kind
|= block_kind_break
;
5310 unsigned idx
= ctx
->block
->index
;
5312 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5313 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5315 /* remove critical edges from linear CFG */
5316 bld
.branch(aco_opcode::p_branch
);
5317 Block
* break_block
= ctx
->program
->create_and_insert_block();
5318 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5319 break_block
->kind
|= block_kind_uniform
;
5320 add_linear_edge(idx
, break_block
);
5321 add_linear_edge(break_block
->index
, linear_target
);
5322 bld
.reset(break_block
);
5323 bld
.branch(aco_opcode::p_branch
);
5325 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5326 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5327 add_linear_edge(idx
, continue_block
);
5328 append_logical_start(continue_block
);
5329 ctx
->block
= continue_block
;
5334 /* it can currently happen that NIR doesn't remove the unreachable code */
5335 if (!nir_instr_is_last(&instr
->instr
)) {
5336 ctx
->program
->needs_exact
= true;
5337 /* save exec somewhere temporarily so that it doesn't get
5338 * overwritten before the discard from outer exec masks */
5339 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5340 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5341 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5345 /* This condition is incorrect for uniformly branched discards in a loop
5346 * predicated by a divergent condition, but the above code catches that case
5347 * and the discard would end up turning into a discard_if.
5357 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5358 /* program just ends here */
5359 ctx
->block
->kind
|= block_kind_uniform
;
5360 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5361 0 /* enabled mask */, 9 /* dest */,
5362 false /* compressed */, true/* done */, true /* valid mask */);
5363 bld
.sopp(aco_opcode::s_endpgm
);
5364 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5366 ctx
->block
->kind
|= block_kind_discard
;
5367 /* branch and linear edge is added by visit_if() */
5371 enum aco_descriptor_type
{
5382 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5383 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5385 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5386 return dim
== ac_image_cube
||
5387 dim
== ac_image_1darray
||
5388 dim
== ac_image_2darray
||
5389 dim
== ac_image_2darraymsaa
;
5392 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5393 enum aco_descriptor_type desc_type
,
5394 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5396 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5397 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5398 if (it != ctx->tex_desc.end())
5401 Temp index
= Temp();
5402 bool index_set
= false;
5403 unsigned constant_index
= 0;
5404 unsigned descriptor_set
;
5405 unsigned base_index
;
5406 Builder
bld(ctx
->program
, ctx
->block
);
5409 assert(tex_instr
&& !image
);
5411 base_index
= tex_instr
->sampler_index
;
5413 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5414 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5418 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5419 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5421 constant_index
+= array_size
* const_value
->u32
;
5423 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5424 if (indirect
.type() == RegType::vgpr
)
5425 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5427 if (array_size
!= 1)
5428 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5434 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5438 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5440 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5441 base_index
= deref_instr
->var
->data
.binding
;
5444 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5445 list
= convert_pointer_to_64_bit(ctx
, list
);
5447 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5448 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5449 unsigned offset
= binding
->offset
;
5450 unsigned stride
= binding
->size
;
5454 assert(base_index
< layout
->binding_count
);
5456 switch (desc_type
) {
5457 case ACO_DESC_IMAGE
:
5459 opcode
= aco_opcode::s_load_dwordx8
;
5461 case ACO_DESC_FMASK
:
5463 opcode
= aco_opcode::s_load_dwordx8
;
5466 case ACO_DESC_SAMPLER
:
5468 opcode
= aco_opcode::s_load_dwordx4
;
5469 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5470 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5472 case ACO_DESC_BUFFER
:
5474 opcode
= aco_opcode::s_load_dwordx4
;
5476 case ACO_DESC_PLANE_0
:
5477 case ACO_DESC_PLANE_1
:
5479 opcode
= aco_opcode::s_load_dwordx8
;
5480 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5482 case ACO_DESC_PLANE_2
:
5484 opcode
= aco_opcode::s_load_dwordx4
;
5488 unreachable("invalid desc_type\n");
5491 offset
+= constant_index
* stride
;
5493 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5494 (!index_set
|| binding
->immutable_samplers_equal
)) {
5495 if (binding
->immutable_samplers_equal
)
5498 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5499 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5500 Operand(samplers
[constant_index
* 4 + 0]),
5501 Operand(samplers
[constant_index
* 4 + 1]),
5502 Operand(samplers
[constant_index
* 4 + 2]),
5503 Operand(samplers
[constant_index
* 4 + 3]));
5508 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5510 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5511 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5514 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5516 if (desc_type
== ACO_DESC_PLANE_2
) {
5518 for (unsigned i
= 0; i
< 8; i
++)
5519 components
[i
] = bld
.tmp(s1
);
5520 bld
.pseudo(aco_opcode::p_split_vector
,
5521 Definition(components
[0]),
5522 Definition(components
[1]),
5523 Definition(components
[2]),
5524 Definition(components
[3]),
5527 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5528 bld
.pseudo(aco_opcode::p_split_vector
,
5529 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5530 Definition(components
[4]),
5531 Definition(components
[5]),
5532 Definition(components
[6]),
5533 Definition(components
[7]),
5536 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5537 components
[0], components
[1], components
[2], components
[3],
5538 components
[4], components
[5], components
[6], components
[7]);
5544 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5547 case GLSL_SAMPLER_DIM_BUF
:
5549 case GLSL_SAMPLER_DIM_1D
:
5550 return array
? 2 : 1;
5551 case GLSL_SAMPLER_DIM_2D
:
5552 return array
? 3 : 2;
5553 case GLSL_SAMPLER_DIM_MS
:
5554 return array
? 4 : 3;
5555 case GLSL_SAMPLER_DIM_3D
:
5556 case GLSL_SAMPLER_DIM_CUBE
:
5558 case GLSL_SAMPLER_DIM_RECT
:
5559 case GLSL_SAMPLER_DIM_SUBPASS
:
5561 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5570 /* Adjust the sample index according to FMASK.
5572 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5573 * which is the identity mapping. Each nibble says which physical sample
5574 * should be fetched to get that sample.
5576 * For example, 0x11111100 means there are only 2 samples stored and
5577 * the second sample covers 3/4 of the pixel. When reading samples 0
5578 * and 1, return physical sample 0 (determined by the first two 0s
5579 * in FMASK), otherwise return physical sample 1.
5581 * The sample index should be adjusted as follows:
5582 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5584 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5586 Builder
bld(ctx
->program
, ctx
->block
);
5587 Temp fmask
= bld
.tmp(v1
);
5588 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5589 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5592 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5593 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5594 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5595 load
->operands
[0] = Operand(fmask_desc_ptr
);
5596 load
->operands
[1] = Operand(s4
); /* no sampler */
5597 load
->operands
[2] = Operand(coord
);
5598 load
->definitions
[0] = Definition(fmask
);
5605 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5606 ctx
->block
->instructions
.emplace_back(std::move(load
));
5608 Operand sample_index4
;
5609 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5610 sample_index4
= Operand(sample_index
.constantValue() << 2);
5611 } else if (sample_index
.regClass() == s1
) {
5612 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5614 assert(sample_index
.regClass() == v1
);
5615 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5619 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5620 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5621 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5622 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5624 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5626 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5627 * resource descriptor is 0 (invalid),
5629 Temp compare
= bld
.tmp(bld
.lm
);
5630 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5631 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5633 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5635 /* Replace the MSAA sample index. */
5636 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5639 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5642 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5643 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5644 bool is_array
= glsl_sampler_type_is_array(type
);
5645 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5646 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5647 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5648 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5649 int count
= image_type_to_components_count(dim
, is_array
);
5650 std::vector
<Temp
> coords(count
);
5651 Builder
bld(ctx
->program
, ctx
->block
);
5655 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5656 /* get sample index */
5657 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5658 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5659 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5660 std::vector
<Temp
> fmask_load_address
;
5661 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5662 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5664 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5665 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5667 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5672 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5673 coords
.resize(coords
.size() + 1);
5674 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5676 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5678 for (int i
= 0; i
< count
; i
++)
5679 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5682 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5683 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5684 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5685 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5688 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5691 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5692 for (unsigned i
= 0; i
< coords
.size(); i
++)
5693 vec
->operands
[i
] = Operand(coords
[i
]);
5694 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5695 vec
->definitions
[0] = Definition(res
);
5696 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5701 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5703 Builder
bld(ctx
->program
, ctx
->block
);
5704 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5705 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5706 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5707 bool is_array
= glsl_sampler_type_is_array(type
);
5708 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5710 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5711 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5712 unsigned num_channels
= util_last_bit(mask
);
5713 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5714 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5717 switch (num_channels
) {
5719 opcode
= aco_opcode::buffer_load_format_x
;
5722 opcode
= aco_opcode::buffer_load_format_xy
;
5725 opcode
= aco_opcode::buffer_load_format_xyz
;
5728 opcode
= aco_opcode::buffer_load_format_xyzw
;
5731 unreachable(">4 channel buffer image load");
5733 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5734 load
->operands
[0] = Operand(rsrc
);
5735 load
->operands
[1] = Operand(vindex
);
5736 load
->operands
[2] = Operand((uint32_t) 0);
5738 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5741 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5742 load
->definitions
[0] = Definition(tmp
);
5744 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5745 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5746 load
->barrier
= barrier_image
;
5747 ctx
->block
->instructions
.emplace_back(std::move(load
));
5749 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5753 Temp coords
= get_image_coords(ctx
, instr
, type
);
5754 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5756 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5757 unsigned num_components
= util_bitcount(dmask
);
5759 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5762 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5764 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5765 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5767 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5768 load
->operands
[0] = Operand(resource
);
5769 load
->operands
[1] = Operand(s4
); /* no sampler */
5770 load
->operands
[2] = Operand(coords
);
5771 load
->definitions
[0] = Definition(tmp
);
5772 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5773 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5774 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5775 load
->dmask
= dmask
;
5777 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5778 load
->barrier
= barrier_image
;
5779 ctx
->block
->instructions
.emplace_back(std::move(load
));
5781 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5785 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5787 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5788 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5789 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5790 bool is_array
= glsl_sampler_type_is_array(type
);
5791 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5793 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5795 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5796 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5797 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5799 switch (data
.size()) {
5801 opcode
= aco_opcode::buffer_store_format_x
;
5804 opcode
= aco_opcode::buffer_store_format_xy
;
5807 opcode
= aco_opcode::buffer_store_format_xyz
;
5810 opcode
= aco_opcode::buffer_store_format_xyzw
;
5813 unreachable(">4 channel buffer image store");
5815 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5816 store
->operands
[0] = Operand(rsrc
);
5817 store
->operands
[1] = Operand(vindex
);
5818 store
->operands
[2] = Operand((uint32_t) 0);
5819 store
->operands
[3] = Operand(data
);
5820 store
->idxen
= true;
5823 store
->disable_wqm
= true;
5824 store
->barrier
= barrier_image
;
5825 ctx
->program
->needs_exact
= true;
5826 ctx
->block
->instructions
.emplace_back(std::move(store
));
5830 assert(data
.type() == RegType::vgpr
);
5831 Temp coords
= get_image_coords(ctx
, instr
, type
);
5832 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5834 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5835 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5837 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5838 store
->operands
[0] = Operand(resource
);
5839 store
->operands
[1] = Operand(data
);
5840 store
->operands
[2] = Operand(coords
);
5843 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5844 store
->dmask
= (1 << data
.size()) - 1;
5846 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5847 store
->disable_wqm
= true;
5848 store
->barrier
= barrier_image
;
5849 ctx
->program
->needs_exact
= true;
5850 ctx
->block
->instructions
.emplace_back(std::move(store
));
5854 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5856 /* return the previous value if dest is ever used */
5857 bool return_previous
= false;
5858 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5859 return_previous
= true;
5862 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5863 return_previous
= true;
5867 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5868 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5869 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5870 bool is_array
= glsl_sampler_type_is_array(type
);
5871 Builder
bld(ctx
->program
, ctx
->block
);
5873 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5874 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5876 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5877 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5879 aco_opcode buf_op
, image_op
;
5880 switch (instr
->intrinsic
) {
5881 case nir_intrinsic_image_deref_atomic_add
:
5882 buf_op
= aco_opcode::buffer_atomic_add
;
5883 image_op
= aco_opcode::image_atomic_add
;
5885 case nir_intrinsic_image_deref_atomic_umin
:
5886 buf_op
= aco_opcode::buffer_atomic_umin
;
5887 image_op
= aco_opcode::image_atomic_umin
;
5889 case nir_intrinsic_image_deref_atomic_imin
:
5890 buf_op
= aco_opcode::buffer_atomic_smin
;
5891 image_op
= aco_opcode::image_atomic_smin
;
5893 case nir_intrinsic_image_deref_atomic_umax
:
5894 buf_op
= aco_opcode::buffer_atomic_umax
;
5895 image_op
= aco_opcode::image_atomic_umax
;
5897 case nir_intrinsic_image_deref_atomic_imax
:
5898 buf_op
= aco_opcode::buffer_atomic_smax
;
5899 image_op
= aco_opcode::image_atomic_smax
;
5901 case nir_intrinsic_image_deref_atomic_and
:
5902 buf_op
= aco_opcode::buffer_atomic_and
;
5903 image_op
= aco_opcode::image_atomic_and
;
5905 case nir_intrinsic_image_deref_atomic_or
:
5906 buf_op
= aco_opcode::buffer_atomic_or
;
5907 image_op
= aco_opcode::image_atomic_or
;
5909 case nir_intrinsic_image_deref_atomic_xor
:
5910 buf_op
= aco_opcode::buffer_atomic_xor
;
5911 image_op
= aco_opcode::image_atomic_xor
;
5913 case nir_intrinsic_image_deref_atomic_exchange
:
5914 buf_op
= aco_opcode::buffer_atomic_swap
;
5915 image_op
= aco_opcode::image_atomic_swap
;
5917 case nir_intrinsic_image_deref_atomic_comp_swap
:
5918 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5919 image_op
= aco_opcode::image_atomic_cmpswap
;
5922 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5925 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5927 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5928 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5929 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5930 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5931 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5932 mubuf
->operands
[0] = Operand(resource
);
5933 mubuf
->operands
[1] = Operand(vindex
);
5934 mubuf
->operands
[2] = Operand((uint32_t)0);
5935 mubuf
->operands
[3] = Operand(data
);
5936 if (return_previous
)
5937 mubuf
->definitions
[0] = Definition(dst
);
5939 mubuf
->idxen
= true;
5940 mubuf
->glc
= return_previous
;
5941 mubuf
->dlc
= false; /* Not needed for atomics */
5942 mubuf
->disable_wqm
= true;
5943 mubuf
->barrier
= barrier_image
;
5944 ctx
->program
->needs_exact
= true;
5945 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5949 Temp coords
= get_image_coords(ctx
, instr
, type
);
5950 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5951 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5952 mimg
->operands
[0] = Operand(resource
);
5953 mimg
->operands
[1] = Operand(data
);
5954 mimg
->operands
[2] = Operand(coords
);
5955 if (return_previous
)
5956 mimg
->definitions
[0] = Definition(dst
);
5957 mimg
->glc
= return_previous
;
5958 mimg
->dlc
= false; /* Not needed for atomics */
5959 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5960 mimg
->dmask
= (1 << data
.size()) - 1;
5962 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5963 mimg
->disable_wqm
= true;
5964 mimg
->barrier
= barrier_image
;
5965 ctx
->program
->needs_exact
= true;
5966 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5970 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5972 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5973 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5974 Builder
bld(ctx
->program
, ctx
->block
);
5976 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5978 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5979 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5981 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5982 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5984 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5985 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5987 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5988 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5989 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5990 if (dst
.type() == RegType::vgpr
)
5991 bld
.copy(Definition(dst
), shr_dst
);
5993 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5995 emit_extract_vector(ctx
, desc
, 2, dst
);
5999 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6001 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6002 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6003 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6004 bool is_array
= glsl_sampler_type_is_array(type
);
6005 Builder
bld(ctx
->program
, ctx
->block
);
6007 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6008 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6009 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6013 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6016 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6018 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6020 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6021 mimg
->operands
[0] = Operand(resource
);
6022 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6023 mimg
->operands
[2] = Operand(lod
);
6024 uint8_t& dmask
= mimg
->dmask
;
6025 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6026 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6027 mimg
->da
= glsl_sampler_type_is_array(type
);
6028 mimg
->can_reorder
= true;
6029 Definition
& def
= mimg
->definitions
[0];
6030 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6032 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6033 glsl_sampler_type_is_array(type
)) {
6035 assert(instr
->dest
.ssa
.num_components
== 3);
6036 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6037 def
= Definition(tmp
);
6038 emit_split_vector(ctx
, tmp
, 3);
6040 /* divide 3rd value by 6 by multiplying with magic number */
6041 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6042 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6044 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6045 emit_extract_vector(ctx
, tmp
, 0, v1
),
6046 emit_extract_vector(ctx
, tmp
, 1, v1
),
6049 } else if (ctx
->options
->chip_class
== GFX9
&&
6050 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6051 glsl_sampler_type_is_array(type
)) {
6052 assert(instr
->dest
.ssa
.num_components
== 2);
6053 def
= Definition(dst
);
6056 def
= Definition(dst
);
6059 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6062 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6064 Builder
bld(ctx
->program
, ctx
->block
);
6065 unsigned num_components
= instr
->num_components
;
6067 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6068 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6069 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6071 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6072 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6075 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
6076 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
6077 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
6079 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
6082 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6084 Builder
bld(ctx
->program
, ctx
->block
);
6085 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6086 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6087 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6088 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6090 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6091 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6093 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
6094 ctx
->options
->chip_class
>= GFX8
&&
6095 elem_size_bytes
>= 4;
6097 offset
= bld
.as_uniform(offset
);
6098 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6102 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6103 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
6104 /* GFX6 doesn't support storing vec3, split it. */
6105 writemask
|= 1u << (start
+ 2);
6108 int num_bytes
= count
* elem_size_bytes
;
6110 /* dword or larger stores have to be dword-aligned */
6111 if (elem_size_bytes
< 4 && num_bytes
> 2) {
6112 // TODO: improve alignment check of sub-dword stores
6113 unsigned count_new
= 2 / elem_size_bytes
;
6114 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
6119 if (num_bytes
> 16) {
6120 assert(elem_size_bytes
== 8);
6121 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6127 if (elem_size_bytes
< 4) {
6128 if (data
.type() == RegType::sgpr
) {
6129 data
= as_vgpr(ctx
, data
);
6130 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
6132 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
6133 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6134 for (int i
= 0; i
< count
; i
++)
6135 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
6136 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
6137 vec
->definitions
[0] = Definition(write_data
);
6138 bld
.insert(std::move(vec
));
6139 } else if (count
!= instr
->num_components
) {
6140 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6141 for (int i
= 0; i
< count
; i
++) {
6142 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
6143 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
6145 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
6146 vec
->definitions
[0] = Definition(write_data
);
6147 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6148 } else if (!smem
&& data
.type() != RegType::vgpr
) {
6149 assert(num_bytes
% 4 == 0);
6150 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
6151 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
6152 assert(num_bytes
% 4 == 0);
6153 write_data
= bld
.as_uniform(data
);
6158 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
6159 switch (num_bytes
) {
6161 vmem_op
= aco_opcode::buffer_store_byte
;
6164 vmem_op
= aco_opcode::buffer_store_short
;
6167 vmem_op
= aco_opcode::buffer_store_dword
;
6168 smem_op
= aco_opcode::s_buffer_store_dword
;
6171 vmem_op
= aco_opcode::buffer_store_dwordx2
;
6172 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
6175 vmem_op
= aco_opcode::buffer_store_dwordx3
;
6176 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
6179 vmem_op
= aco_opcode::buffer_store_dwordx4
;
6180 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
6183 unreachable("Store SSBO not implemented for this size.");
6185 if (ctx
->stage
== fragment_fs
)
6186 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
6189 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
6190 store
->operands
[0] = Operand(rsrc
);
6192 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6193 offset
, Operand(start
* elem_size_bytes
));
6194 store
->operands
[1] = Operand(off
);
6196 store
->operands
[1] = Operand(offset
);
6198 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
6199 store
->operands
[1].setFixed(m0
);
6200 store
->operands
[2] = Operand(write_data
);
6201 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6203 store
->disable_wqm
= true;
6204 store
->barrier
= barrier_buffer
;
6205 ctx
->block
->instructions
.emplace_back(std::move(store
));
6206 ctx
->program
->wb_smem_l1_on_end
= true;
6207 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
6208 ctx
->block
->kind
|= block_kind_needs_lowering
;
6209 ctx
->program
->needs_exact
= true;
6212 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
6213 store
->operands
[0] = Operand(rsrc
);
6214 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6215 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6216 store
->operands
[3] = Operand(write_data
);
6217 store
->offset
= start
* elem_size_bytes
;
6218 store
->offen
= (offset
.type() == RegType::vgpr
);
6219 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6221 store
->disable_wqm
= true;
6222 store
->barrier
= barrier_buffer
;
6223 ctx
->program
->needs_exact
= true;
6224 ctx
->block
->instructions
.emplace_back(std::move(store
));
6229 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6231 /* return the previous value if dest is ever used */
6232 bool return_previous
= false;
6233 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6234 return_previous
= true;
6237 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6238 return_previous
= true;
6242 Builder
bld(ctx
->program
, ctx
->block
);
6243 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6245 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6246 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6247 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6249 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6250 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6251 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6253 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6255 aco_opcode op32
, op64
;
6256 switch (instr
->intrinsic
) {
6257 case nir_intrinsic_ssbo_atomic_add
:
6258 op32
= aco_opcode::buffer_atomic_add
;
6259 op64
= aco_opcode::buffer_atomic_add_x2
;
6261 case nir_intrinsic_ssbo_atomic_imin
:
6262 op32
= aco_opcode::buffer_atomic_smin
;
6263 op64
= aco_opcode::buffer_atomic_smin_x2
;
6265 case nir_intrinsic_ssbo_atomic_umin
:
6266 op32
= aco_opcode::buffer_atomic_umin
;
6267 op64
= aco_opcode::buffer_atomic_umin_x2
;
6269 case nir_intrinsic_ssbo_atomic_imax
:
6270 op32
= aco_opcode::buffer_atomic_smax
;
6271 op64
= aco_opcode::buffer_atomic_smax_x2
;
6273 case nir_intrinsic_ssbo_atomic_umax
:
6274 op32
= aco_opcode::buffer_atomic_umax
;
6275 op64
= aco_opcode::buffer_atomic_umax_x2
;
6277 case nir_intrinsic_ssbo_atomic_and
:
6278 op32
= aco_opcode::buffer_atomic_and
;
6279 op64
= aco_opcode::buffer_atomic_and_x2
;
6281 case nir_intrinsic_ssbo_atomic_or
:
6282 op32
= aco_opcode::buffer_atomic_or
;
6283 op64
= aco_opcode::buffer_atomic_or_x2
;
6285 case nir_intrinsic_ssbo_atomic_xor
:
6286 op32
= aco_opcode::buffer_atomic_xor
;
6287 op64
= aco_opcode::buffer_atomic_xor_x2
;
6289 case nir_intrinsic_ssbo_atomic_exchange
:
6290 op32
= aco_opcode::buffer_atomic_swap
;
6291 op64
= aco_opcode::buffer_atomic_swap_x2
;
6293 case nir_intrinsic_ssbo_atomic_comp_swap
:
6294 op32
= aco_opcode::buffer_atomic_cmpswap
;
6295 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6298 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6300 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6301 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6302 mubuf
->operands
[0] = Operand(rsrc
);
6303 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6304 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6305 mubuf
->operands
[3] = Operand(data
);
6306 if (return_previous
)
6307 mubuf
->definitions
[0] = Definition(dst
);
6309 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6310 mubuf
->glc
= return_previous
;
6311 mubuf
->dlc
= false; /* Not needed for atomics */
6312 mubuf
->disable_wqm
= true;
6313 mubuf
->barrier
= barrier_buffer
;
6314 ctx
->program
->needs_exact
= true;
6315 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6318 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6320 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6321 Builder
bld(ctx
->program
, ctx
->block
);
6322 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6323 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6326 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6328 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6329 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6331 if (addr
.type() == RegType::vgpr
)
6332 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6333 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6336 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6338 Builder
bld(ctx
->program
, ctx
->block
);
6339 unsigned num_components
= instr
->num_components
;
6340 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6342 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6343 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6345 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6346 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6347 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6348 * it's safe to use SMEM */
6349 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6351 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6352 bool global
= ctx
->options
->chip_class
>= GFX9
;
6354 if (ctx
->options
->chip_class
>= GFX7
) {
6355 switch (num_bytes
) {
6357 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6360 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6363 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6366 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6369 unreachable("load_global not implemented for this size.");
6372 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6373 flat
->operands
[0] = Operand(addr
);
6374 flat
->operands
[1] = Operand(s1
);
6377 flat
->barrier
= barrier_buffer
;
6379 if (dst
.type() == RegType::sgpr
) {
6380 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6381 flat
->definitions
[0] = Definition(vec
);
6382 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6383 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6385 flat
->definitions
[0] = Definition(dst
);
6386 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6388 emit_split_vector(ctx
, dst
, num_components
);
6390 assert(ctx
->options
->chip_class
== GFX6
);
6392 /* GFX6 doesn't support loading vec3, expand to vec4. */
6393 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6395 switch (num_bytes
) {
6397 op
= aco_opcode::buffer_load_dword
;
6400 op
= aco_opcode::buffer_load_dwordx2
;
6403 op
= aco_opcode::buffer_load_dwordx4
;
6406 unreachable("load_global not implemented for this size.");
6409 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6411 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6412 mubuf
->operands
[0] = Operand(rsrc
);
6413 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6414 mubuf
->operands
[2] = Operand(0u);
6418 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6419 mubuf
->disable_wqm
= false;
6420 mubuf
->barrier
= barrier_buffer
;
6421 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6424 if (dst
.size() == 3) {
6425 Temp vec
= bld
.tmp(v4
);
6426 instr
->definitions
[0] = Definition(vec
);
6427 bld
.insert(std::move(instr
));
6428 emit_split_vector(ctx
, vec
, 4);
6430 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6431 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6432 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6433 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6436 if (dst
.type() == RegType::sgpr
) {
6437 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6438 instr
->definitions
[0] = Definition(vec
);
6439 bld
.insert(std::move(instr
));
6440 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6441 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6443 instr
->definitions
[0] = Definition(dst
);
6444 bld
.insert(std::move(instr
));
6445 emit_split_vector(ctx
, dst
, num_components
);
6449 switch (num_bytes
) {
6451 op
= aco_opcode::s_load_dword
;
6454 op
= aco_opcode::s_load_dwordx2
;
6458 op
= aco_opcode::s_load_dwordx4
;
6461 unreachable("load_global not implemented for this size.");
6463 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6464 load
->operands
[0] = Operand(addr
);
6465 load
->operands
[1] = Operand(0u);
6466 load
->definitions
[0] = Definition(dst
);
6469 load
->barrier
= barrier_buffer
;
6470 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6472 if (dst
.size() == 3) {
6474 Temp vec
= bld
.tmp(s4
);
6475 load
->definitions
[0] = Definition(vec
);
6476 ctx
->block
->instructions
.emplace_back(std::move(load
));
6477 emit_split_vector(ctx
, vec
, 4);
6479 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6480 emit_extract_vector(ctx
, vec
, 0, s1
),
6481 emit_extract_vector(ctx
, vec
, 1, s1
),
6482 emit_extract_vector(ctx
, vec
, 2, s1
));
6484 ctx
->block
->instructions
.emplace_back(std::move(load
));
6489 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6491 Builder
bld(ctx
->program
, ctx
->block
);
6492 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6494 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6495 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6497 if (ctx
->options
->chip_class
>= GFX7
)
6498 addr
= as_vgpr(ctx
, addr
);
6500 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6503 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6504 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6505 /* GFX6 doesn't support storing vec3, split it. */
6506 writemask
|= 1u << (start
+ 2);
6509 unsigned num_bytes
= count
* elem_size_bytes
;
6511 Temp write_data
= data
;
6512 if (count
!= instr
->num_components
) {
6513 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6514 for (int i
= 0; i
< count
; i
++)
6515 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6516 write_data
= bld
.tmp(RegType::vgpr
, count
);
6517 vec
->definitions
[0] = Definition(write_data
);
6518 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6521 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6522 unsigned offset
= start
* elem_size_bytes
;
6524 if (ctx
->options
->chip_class
>= GFX7
) {
6525 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6526 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6527 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6528 Temp carry
= bld
.tmp(bld
.lm
);
6529 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6531 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6532 Operand(offset
), addr0
);
6533 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6535 carry
).def(1).setHint(vcc
);
6537 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6542 bool global
= ctx
->options
->chip_class
>= GFX9
;
6544 switch (num_bytes
) {
6546 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6549 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6552 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6555 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6558 unreachable("store_global not implemented for this size.");
6561 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6562 flat
->operands
[0] = Operand(addr
);
6563 flat
->operands
[1] = Operand(s1
);
6564 flat
->operands
[2] = Operand(data
);
6567 flat
->offset
= offset
;
6568 flat
->disable_wqm
= true;
6569 flat
->barrier
= barrier_buffer
;
6570 ctx
->program
->needs_exact
= true;
6571 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6573 assert(ctx
->options
->chip_class
== GFX6
);
6576 switch (num_bytes
) {
6578 op
= aco_opcode::buffer_store_dword
;
6581 op
= aco_opcode::buffer_store_dwordx2
;
6584 op
= aco_opcode::buffer_store_dwordx4
;
6587 unreachable("store_global not implemented for this size.");
6590 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6592 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6593 mubuf
->operands
[0] = Operand(rsrc
);
6594 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6595 mubuf
->operands
[2] = Operand(0u);
6596 mubuf
->operands
[3] = Operand(write_data
);
6599 mubuf
->offset
= offset
;
6600 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6601 mubuf
->disable_wqm
= true;
6602 mubuf
->barrier
= barrier_buffer
;
6603 ctx
->program
->needs_exact
= true;
6604 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6609 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6611 /* return the previous value if dest is ever used */
6612 bool return_previous
= false;
6613 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6614 return_previous
= true;
6617 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6618 return_previous
= true;
6622 Builder
bld(ctx
->program
, ctx
->block
);
6623 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6624 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6626 if (ctx
->options
->chip_class
>= GFX7
)
6627 addr
= as_vgpr(ctx
, addr
);
6629 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6630 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6631 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6633 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6635 aco_opcode op32
, op64
;
6637 if (ctx
->options
->chip_class
>= GFX7
) {
6638 bool global
= ctx
->options
->chip_class
>= GFX9
;
6639 switch (instr
->intrinsic
) {
6640 case nir_intrinsic_global_atomic_add
:
6641 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6642 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6644 case nir_intrinsic_global_atomic_imin
:
6645 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6646 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6648 case nir_intrinsic_global_atomic_umin
:
6649 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6650 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6652 case nir_intrinsic_global_atomic_imax
:
6653 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6654 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6656 case nir_intrinsic_global_atomic_umax
:
6657 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6658 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6660 case nir_intrinsic_global_atomic_and
:
6661 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6662 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6664 case nir_intrinsic_global_atomic_or
:
6665 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6666 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6668 case nir_intrinsic_global_atomic_xor
:
6669 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6670 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6672 case nir_intrinsic_global_atomic_exchange
:
6673 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6674 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6676 case nir_intrinsic_global_atomic_comp_swap
:
6677 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6678 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6681 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6684 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6685 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6686 flat
->operands
[0] = Operand(addr
);
6687 flat
->operands
[1] = Operand(s1
);
6688 flat
->operands
[2] = Operand(data
);
6689 if (return_previous
)
6690 flat
->definitions
[0] = Definition(dst
);
6691 flat
->glc
= return_previous
;
6692 flat
->dlc
= false; /* Not needed for atomics */
6694 flat
->disable_wqm
= true;
6695 flat
->barrier
= barrier_buffer
;
6696 ctx
->program
->needs_exact
= true;
6697 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6699 assert(ctx
->options
->chip_class
== GFX6
);
6701 switch (instr
->intrinsic
) {
6702 case nir_intrinsic_global_atomic_add
:
6703 op32
= aco_opcode::buffer_atomic_add
;
6704 op64
= aco_opcode::buffer_atomic_add_x2
;
6706 case nir_intrinsic_global_atomic_imin
:
6707 op32
= aco_opcode::buffer_atomic_smin
;
6708 op64
= aco_opcode::buffer_atomic_smin_x2
;
6710 case nir_intrinsic_global_atomic_umin
:
6711 op32
= aco_opcode::buffer_atomic_umin
;
6712 op64
= aco_opcode::buffer_atomic_umin_x2
;
6714 case nir_intrinsic_global_atomic_imax
:
6715 op32
= aco_opcode::buffer_atomic_smax
;
6716 op64
= aco_opcode::buffer_atomic_smax_x2
;
6718 case nir_intrinsic_global_atomic_umax
:
6719 op32
= aco_opcode::buffer_atomic_umax
;
6720 op64
= aco_opcode::buffer_atomic_umax_x2
;
6722 case nir_intrinsic_global_atomic_and
:
6723 op32
= aco_opcode::buffer_atomic_and
;
6724 op64
= aco_opcode::buffer_atomic_and_x2
;
6726 case nir_intrinsic_global_atomic_or
:
6727 op32
= aco_opcode::buffer_atomic_or
;
6728 op64
= aco_opcode::buffer_atomic_or_x2
;
6730 case nir_intrinsic_global_atomic_xor
:
6731 op32
= aco_opcode::buffer_atomic_xor
;
6732 op64
= aco_opcode::buffer_atomic_xor_x2
;
6734 case nir_intrinsic_global_atomic_exchange
:
6735 op32
= aco_opcode::buffer_atomic_swap
;
6736 op64
= aco_opcode::buffer_atomic_swap_x2
;
6738 case nir_intrinsic_global_atomic_comp_swap
:
6739 op32
= aco_opcode::buffer_atomic_cmpswap
;
6740 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6743 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6746 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6748 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6750 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6751 mubuf
->operands
[0] = Operand(rsrc
);
6752 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6753 mubuf
->operands
[2] = Operand(0u);
6754 mubuf
->operands
[3] = Operand(data
);
6755 if (return_previous
)
6756 mubuf
->definitions
[0] = Definition(dst
);
6757 mubuf
->glc
= return_previous
;
6760 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6761 mubuf
->disable_wqm
= true;
6762 mubuf
->barrier
= barrier_buffer
;
6763 ctx
->program
->needs_exact
= true;
6764 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6768 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6769 Builder
bld(ctx
->program
, ctx
->block
);
6770 switch(instr
->intrinsic
) {
6771 case nir_intrinsic_group_memory_barrier
:
6772 case nir_intrinsic_memory_barrier
:
6773 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6775 case nir_intrinsic_memory_barrier_buffer
:
6776 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6778 case nir_intrinsic_memory_barrier_image
:
6779 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6781 case nir_intrinsic_memory_barrier_tcs_patch
:
6782 case nir_intrinsic_memory_barrier_shared
:
6783 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6786 unreachable("Unimplemented memory barrier intrinsic");
6791 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6793 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6794 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6795 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6796 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6797 Builder
bld(ctx
->program
, ctx
->block
);
6799 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6800 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6801 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6804 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6806 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6807 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6808 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6809 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6810 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6812 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6813 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6816 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6818 unsigned offset
= nir_intrinsic_base(instr
);
6819 Builder
bld(ctx
->program
, ctx
->block
);
6820 Operand m
= load_lds_size_m0(bld
);
6821 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6822 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6824 unsigned num_operands
= 3;
6825 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6826 switch(instr
->intrinsic
) {
6827 case nir_intrinsic_shared_atomic_add
:
6828 op32
= aco_opcode::ds_add_u32
;
6829 op64
= aco_opcode::ds_add_u64
;
6830 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6831 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6833 case nir_intrinsic_shared_atomic_imin
:
6834 op32
= aco_opcode::ds_min_i32
;
6835 op64
= aco_opcode::ds_min_i64
;
6836 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6837 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6839 case nir_intrinsic_shared_atomic_umin
:
6840 op32
= aco_opcode::ds_min_u32
;
6841 op64
= aco_opcode::ds_min_u64
;
6842 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6843 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6845 case nir_intrinsic_shared_atomic_imax
:
6846 op32
= aco_opcode::ds_max_i32
;
6847 op64
= aco_opcode::ds_max_i64
;
6848 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6849 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6851 case nir_intrinsic_shared_atomic_umax
:
6852 op32
= aco_opcode::ds_max_u32
;
6853 op64
= aco_opcode::ds_max_u64
;
6854 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6855 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6857 case nir_intrinsic_shared_atomic_and
:
6858 op32
= aco_opcode::ds_and_b32
;
6859 op64
= aco_opcode::ds_and_b64
;
6860 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6861 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6863 case nir_intrinsic_shared_atomic_or
:
6864 op32
= aco_opcode::ds_or_b32
;
6865 op64
= aco_opcode::ds_or_b64
;
6866 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6867 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6869 case nir_intrinsic_shared_atomic_xor
:
6870 op32
= aco_opcode::ds_xor_b32
;
6871 op64
= aco_opcode::ds_xor_b64
;
6872 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6873 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6875 case nir_intrinsic_shared_atomic_exchange
:
6876 op32
= aco_opcode::ds_write_b32
;
6877 op64
= aco_opcode::ds_write_b64
;
6878 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6879 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6881 case nir_intrinsic_shared_atomic_comp_swap
:
6882 op32
= aco_opcode::ds_cmpst_b32
;
6883 op64
= aco_opcode::ds_cmpst_b64
;
6884 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6885 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6889 unreachable("Unhandled shared atomic intrinsic");
6892 /* return the previous value if dest is ever used */
6893 bool return_previous
= false;
6894 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6895 return_previous
= true;
6898 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6899 return_previous
= true;
6904 if (data
.size() == 1) {
6905 assert(instr
->dest
.ssa
.bit_size
== 32);
6906 op
= return_previous
? op32_rtn
: op32
;
6908 assert(instr
->dest
.ssa
.bit_size
== 64);
6909 op
= return_previous
? op64_rtn
: op64
;
6912 if (offset
> 65535) {
6913 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6917 aco_ptr
<DS_instruction
> ds
;
6918 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6919 ds
->operands
[0] = Operand(address
);
6920 ds
->operands
[1] = Operand(data
);
6921 if (num_operands
== 4)
6922 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6923 ds
->operands
[num_operands
- 1] = m
;
6924 ds
->offset0
= offset
;
6925 if (return_previous
)
6926 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6927 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6930 Temp
get_scratch_resource(isel_context
*ctx
)
6932 Builder
bld(ctx
->program
, ctx
->block
);
6933 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6934 if (ctx
->stage
!= compute_cs
)
6935 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6937 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6938 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6940 if (ctx
->program
->chip_class
>= GFX10
) {
6941 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6942 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6943 S_008F0C_RESOURCE_LEVEL(1);
6944 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6945 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6946 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6949 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6950 if (ctx
->program
->chip_class
<= GFX8
)
6951 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6953 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6956 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6957 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6958 Builder
bld(ctx
->program
, ctx
->block
);
6959 Temp rsrc
= get_scratch_resource(ctx
);
6960 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6961 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6964 switch (dst
.size()) {
6966 op
= aco_opcode::buffer_load_dword
;
6969 op
= aco_opcode::buffer_load_dwordx2
;
6972 op
= aco_opcode::buffer_load_dwordx3
;
6975 op
= aco_opcode::buffer_load_dwordx4
;
6979 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6980 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6981 bld
.def(v4
), rsrc
, offset
,
6982 ctx
->program
->scratch_offset
, 0, true);
6983 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6984 aco_opcode::buffer_load_dwordx4
,
6985 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6986 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6987 emit_split_vector(ctx
, lower
, 2);
6988 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6989 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6990 if (dst
.size() == 8) {
6991 emit_split_vector(ctx
, upper
, 2);
6992 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6993 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6998 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6999 Format::PSEUDO
, dst
.size() / 2, 1)};
7000 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
7001 vec
->operands
[i
] = Operand(elems
[i
]);
7002 vec
->definitions
[0] = Definition(dst
);
7003 bld
.insert(std::move(vec
));
7004 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
7008 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
7011 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
7012 emit_split_vector(ctx
, dst
, instr
->num_components
);
7015 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
7016 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
7017 Builder
bld(ctx
->program
, ctx
->block
);
7018 Temp rsrc
= get_scratch_resource(ctx
);
7019 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7020 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7022 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
7023 unsigned writemask
= nir_intrinsic_write_mask(instr
);
7027 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
7028 int num_bytes
= count
* elem_size_bytes
;
7030 if (num_bytes
> 16) {
7031 assert(elem_size_bytes
== 8);
7032 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
7037 // TODO: check alignment of sub-dword stores
7038 // TODO: split 3 bytes. there is no store instruction for that
7041 if (count
!= instr
->num_components
) {
7042 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
7043 for (int i
= 0; i
< count
; i
++) {
7044 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
7045 vec
->operands
[i
] = Operand(elem
);
7047 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
7048 vec
->definitions
[0] = Definition(write_data
);
7049 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7055 switch (num_bytes
) {
7057 op
= aco_opcode::buffer_store_dword
;
7060 op
= aco_opcode::buffer_store_dwordx2
;
7063 op
= aco_opcode::buffer_store_dwordx3
;
7066 op
= aco_opcode::buffer_store_dwordx4
;
7069 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
7072 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
7076 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
7077 uint8_t log2_ps_iter_samples
;
7078 if (ctx
->program
->info
->ps
.force_persample
) {
7079 log2_ps_iter_samples
=
7080 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
7082 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
7085 /* The bit pattern matches that used by fixed function fragment
7087 static const unsigned ps_iter_masks
[] = {
7088 0xffff, /* not used */
7094 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
7096 Builder
bld(ctx
->program
, ctx
->block
);
7098 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
7099 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7100 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
7101 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
7102 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7103 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
7106 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
7107 Builder
bld(ctx
->program
, ctx
->block
);
7109 unsigned stream
= nir_intrinsic_stream_id(instr
);
7110 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7111 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
7112 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
7115 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
7117 unsigned num_components
=
7118 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
7119 assert(num_components
);
7121 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
7122 unsigned stream_offset
= 0;
7123 for (unsigned i
= 0; i
< stream
; i
++) {
7124 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
7125 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
7128 /* Limit on the stride field for <= GFX7. */
7129 assert(stride
< (1 << 14));
7131 Temp gsvs_dwords
[4];
7132 for (unsigned i
= 0; i
< 4; i
++)
7133 gsvs_dwords
[i
] = bld
.tmp(s1
);
7134 bld
.pseudo(aco_opcode::p_split_vector
,
7135 Definition(gsvs_dwords
[0]),
7136 Definition(gsvs_dwords
[1]),
7137 Definition(gsvs_dwords
[2]),
7138 Definition(gsvs_dwords
[3]),
7141 if (stream_offset
) {
7142 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
7144 Temp carry
= bld
.tmp(s1
);
7145 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
7146 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
7149 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
7150 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
7152 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7153 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
7155 unsigned offset
= 0;
7156 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
7157 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
7160 for (unsigned j
= 0; j
< 4; j
++) {
7161 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
7164 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
7165 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
7166 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
7167 if (const_offset
>= 4096u) {
7168 if (vaddr_offset
.isUndefined())
7169 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
7171 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
7172 const_offset
%= 4096u;
7175 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
7176 mtbuf
->operands
[0] = Operand(gsvs_ring
);
7177 mtbuf
->operands
[1] = vaddr_offset
;
7178 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
7179 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7180 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7181 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7182 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7183 mtbuf
->offset
= const_offset
;
7186 mtbuf
->barrier
= barrier_gs_data
;
7187 mtbuf
->can_reorder
= true;
7188 bld
.insert(std::move(mtbuf
));
7191 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7194 /* outputs for the next vertex are undefined and keeping them around can
7195 * create invalid IR with control flow */
7196 ctx
->outputs
.mask
[i
] = 0;
7199 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7202 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7204 Builder
bld(ctx
->program
, ctx
->block
);
7206 if (cluster_size
== 1) {
7208 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7209 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7210 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7211 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7212 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7213 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7214 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7215 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7216 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7217 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7218 //subgroupAnd(val) -> (exec & ~val) == 0
7219 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7220 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7221 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7222 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7223 //subgroupOr(val) -> (val & exec) != 0
7224 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7225 return bool_to_vector_condition(ctx
, tmp
);
7226 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7227 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7228 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7229 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7230 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7231 return bool_to_vector_condition(ctx
, tmp
);
7233 //subgroupClustered{And,Or,Xor}(val, n) ->
7234 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7235 //cluster_offset = ~(n - 1) & lane_id
7236 //cluster_mask = ((1 << n) - 1)
7237 //subgroupClusteredAnd():
7238 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7239 //subgroupClusteredOr():
7240 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7241 //subgroupClusteredXor():
7242 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7243 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7244 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7247 if (op
== nir_op_iand
)
7248 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7250 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7252 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7254 if (ctx
->program
->chip_class
<= GFX7
)
7255 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7256 else if (ctx
->program
->wave_size
== 64)
7257 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7259 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7260 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7261 if (cluster_mask
!= 0xffffffff)
7262 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7264 Definition cmp_def
= Definition();
7265 if (op
== nir_op_iand
) {
7266 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7267 } else if (op
== nir_op_ior
) {
7268 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7269 } else if (op
== nir_op_ixor
) {
7270 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7271 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7272 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7274 cmp_def
.setHint(vcc
);
7275 return cmp_def
.getTemp();
7279 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7281 Builder
bld(ctx
->program
, ctx
->block
);
7283 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7284 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7285 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7287 if (op
== nir_op_iand
)
7288 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7290 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7292 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7293 Temp lo
= lohi
.def(0).getTemp();
7294 Temp hi
= lohi
.def(1).getTemp();
7295 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7297 Definition cmp_def
= Definition();
7298 if (op
== nir_op_iand
)
7299 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7300 else if (op
== nir_op_ior
)
7301 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7302 else if (op
== nir_op_ixor
)
7303 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7304 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7305 cmp_def
.setHint(vcc
);
7306 return cmp_def
.getTemp();
7309 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7311 Builder
bld(ctx
->program
, ctx
->block
);
7313 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7314 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7315 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7316 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7317 if (op
== nir_op_iand
)
7318 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7319 else if (op
== nir_op_ior
)
7320 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7321 else if (op
== nir_op_ixor
)
7322 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7328 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7330 Builder
bld(ctx
->program
, ctx
->block
);
7331 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7332 if (src
.regClass().type() == RegType::vgpr
) {
7333 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7334 } else if (src
.regClass() == s1
) {
7335 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7336 } else if (src
.regClass() == s2
) {
7337 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7340 nir_print_instr(&instr
->instr
, stderr
);
7341 fprintf(stderr
, "\n");
7345 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7347 Builder
bld(ctx
->program
, ctx
->block
);
7348 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7349 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7350 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7352 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7353 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7354 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7355 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7358 if (ctx
->program
->chip_class
>= GFX8
) {
7359 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7360 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7361 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7362 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7363 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7364 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7366 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7367 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7368 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7369 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7370 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7371 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7372 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7373 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7374 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7375 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7378 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7379 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7380 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7381 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7382 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7383 Temp wqm1
= bld
.tmp(v1
);
7384 emit_wqm(ctx
, tmp1
, wqm1
, true);
7385 Temp wqm2
= bld
.tmp(v1
);
7386 emit_wqm(ctx
, tmp2
, wqm2
, true);
7387 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7391 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7393 Builder
bld(ctx
->program
, ctx
->block
);
7394 switch(instr
->intrinsic
) {
7395 case nir_intrinsic_load_barycentric_sample
:
7396 case nir_intrinsic_load_barycentric_pixel
:
7397 case nir_intrinsic_load_barycentric_centroid
: {
7398 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7399 Temp bary
= Temp(0, s2
);
7401 case INTERP_MODE_SMOOTH
:
7402 case INTERP_MODE_NONE
:
7403 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7404 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7405 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7406 bary
= ctx
->persp_centroid
;
7407 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7408 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7410 case INTERP_MODE_NOPERSPECTIVE
:
7411 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7412 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7413 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7414 bary
= ctx
->linear_centroid
;
7415 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7416 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7421 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7422 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7423 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7424 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7425 Operand(p1
), Operand(p2
));
7426 emit_split_vector(ctx
, dst
, 2);
7429 case nir_intrinsic_load_barycentric_model
: {
7430 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7432 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7433 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7434 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7435 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7436 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7437 Operand(p1
), Operand(p2
), Operand(p3
));
7438 emit_split_vector(ctx
, dst
, 3);
7441 case nir_intrinsic_load_barycentric_at_sample
: {
7442 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7443 switch (ctx
->options
->key
.fs
.num_samples
) {
7444 case 2: sample_pos_offset
+= 1 << 3; break;
7445 case 4: sample_pos_offset
+= 3 << 3; break;
7446 case 8: sample_pos_offset
+= 7 << 3; break;
7450 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7451 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7452 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7453 if (addr
.type() == RegType::sgpr
) {
7456 sample_pos_offset
+= const_addr
->u32
<< 3;
7457 offset
= Operand(sample_pos_offset
);
7458 } else if (ctx
->options
->chip_class
>= GFX9
) {
7459 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7461 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7462 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7465 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7466 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7468 } else if (ctx
->options
->chip_class
>= GFX9
) {
7469 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7470 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7471 } else if (ctx
->options
->chip_class
>= GFX7
) {
7472 /* addr += private_segment_buffer + sample_pos_offset */
7473 Temp tmp0
= bld
.tmp(s1
);
7474 Temp tmp1
= bld
.tmp(s1
);
7475 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7476 Definition scc_tmp
= bld
.def(s1
, scc
);
7477 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7478 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7479 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7480 Temp pck0
= bld
.tmp(v1
);
7481 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7482 tmp1
= as_vgpr(ctx
, tmp1
);
7483 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7484 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7486 /* sample_pos = flat_load_dwordx2 addr */
7487 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7489 assert(ctx
->options
->chip_class
== GFX6
);
7491 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7492 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7493 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7495 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7496 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7498 sample_pos
= bld
.tmp(v2
);
7500 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7501 load
->definitions
[0] = Definition(sample_pos
);
7502 load
->operands
[0] = Operand(rsrc
);
7503 load
->operands
[1] = Operand(addr
);
7504 load
->operands
[2] = Operand(0u);
7505 load
->offset
= sample_pos_offset
;
7507 load
->addr64
= true;
7510 load
->disable_wqm
= false;
7511 load
->barrier
= barrier_none
;
7512 load
->can_reorder
= true;
7513 ctx
->block
->instructions
.emplace_back(std::move(load
));
7516 /* sample_pos -= 0.5 */
7517 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7518 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7520 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7521 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7523 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7526 case nir_intrinsic_load_barycentric_at_offset
: {
7527 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7528 RegClass rc
= RegClass(offset
.type(), 1);
7529 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7530 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7531 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7534 case nir_intrinsic_load_front_face
: {
7535 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7536 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7539 case nir_intrinsic_load_view_index
: {
7540 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7541 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7542 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7548 case nir_intrinsic_load_layer_id
: {
7549 unsigned idx
= nir_intrinsic_base(instr
);
7550 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7551 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7554 case nir_intrinsic_load_frag_coord
: {
7555 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7558 case nir_intrinsic_load_sample_pos
: {
7559 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7560 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7561 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7562 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7563 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7566 case nir_intrinsic_load_tess_coord
:
7567 visit_load_tess_coord(ctx
, instr
);
7569 case nir_intrinsic_load_interpolated_input
:
7570 visit_load_interpolated_input(ctx
, instr
);
7572 case nir_intrinsic_store_output
:
7573 visit_store_output(ctx
, instr
);
7575 case nir_intrinsic_load_input
:
7576 case nir_intrinsic_load_input_vertex
:
7577 visit_load_input(ctx
, instr
);
7579 case nir_intrinsic_load_output
:
7580 visit_load_output(ctx
, instr
);
7582 case nir_intrinsic_load_per_vertex_input
:
7583 visit_load_per_vertex_input(ctx
, instr
);
7585 case nir_intrinsic_load_per_vertex_output
:
7586 visit_load_per_vertex_output(ctx
, instr
);
7588 case nir_intrinsic_store_per_vertex_output
:
7589 visit_store_per_vertex_output(ctx
, instr
);
7591 case nir_intrinsic_load_ubo
:
7592 visit_load_ubo(ctx
, instr
);
7594 case nir_intrinsic_load_push_constant
:
7595 visit_load_push_constant(ctx
, instr
);
7597 case nir_intrinsic_load_constant
:
7598 visit_load_constant(ctx
, instr
);
7600 case nir_intrinsic_vulkan_resource_index
:
7601 visit_load_resource(ctx
, instr
);
7603 case nir_intrinsic_discard
:
7604 visit_discard(ctx
, instr
);
7606 case nir_intrinsic_discard_if
:
7607 visit_discard_if(ctx
, instr
);
7609 case nir_intrinsic_load_shared
:
7610 visit_load_shared(ctx
, instr
);
7612 case nir_intrinsic_store_shared
:
7613 visit_store_shared(ctx
, instr
);
7615 case nir_intrinsic_shared_atomic_add
:
7616 case nir_intrinsic_shared_atomic_imin
:
7617 case nir_intrinsic_shared_atomic_umin
:
7618 case nir_intrinsic_shared_atomic_imax
:
7619 case nir_intrinsic_shared_atomic_umax
:
7620 case nir_intrinsic_shared_atomic_and
:
7621 case nir_intrinsic_shared_atomic_or
:
7622 case nir_intrinsic_shared_atomic_xor
:
7623 case nir_intrinsic_shared_atomic_exchange
:
7624 case nir_intrinsic_shared_atomic_comp_swap
:
7625 visit_shared_atomic(ctx
, instr
);
7627 case nir_intrinsic_image_deref_load
:
7628 visit_image_load(ctx
, instr
);
7630 case nir_intrinsic_image_deref_store
:
7631 visit_image_store(ctx
, instr
);
7633 case nir_intrinsic_image_deref_atomic_add
:
7634 case nir_intrinsic_image_deref_atomic_umin
:
7635 case nir_intrinsic_image_deref_atomic_imin
:
7636 case nir_intrinsic_image_deref_atomic_umax
:
7637 case nir_intrinsic_image_deref_atomic_imax
:
7638 case nir_intrinsic_image_deref_atomic_and
:
7639 case nir_intrinsic_image_deref_atomic_or
:
7640 case nir_intrinsic_image_deref_atomic_xor
:
7641 case nir_intrinsic_image_deref_atomic_exchange
:
7642 case nir_intrinsic_image_deref_atomic_comp_swap
:
7643 visit_image_atomic(ctx
, instr
);
7645 case nir_intrinsic_image_deref_size
:
7646 visit_image_size(ctx
, instr
);
7648 case nir_intrinsic_load_ssbo
:
7649 visit_load_ssbo(ctx
, instr
);
7651 case nir_intrinsic_store_ssbo
:
7652 visit_store_ssbo(ctx
, instr
);
7654 case nir_intrinsic_load_global
:
7655 visit_load_global(ctx
, instr
);
7657 case nir_intrinsic_store_global
:
7658 visit_store_global(ctx
, instr
);
7660 case nir_intrinsic_global_atomic_add
:
7661 case nir_intrinsic_global_atomic_imin
:
7662 case nir_intrinsic_global_atomic_umin
:
7663 case nir_intrinsic_global_atomic_imax
:
7664 case nir_intrinsic_global_atomic_umax
:
7665 case nir_intrinsic_global_atomic_and
:
7666 case nir_intrinsic_global_atomic_or
:
7667 case nir_intrinsic_global_atomic_xor
:
7668 case nir_intrinsic_global_atomic_exchange
:
7669 case nir_intrinsic_global_atomic_comp_swap
:
7670 visit_global_atomic(ctx
, instr
);
7672 case nir_intrinsic_ssbo_atomic_add
:
7673 case nir_intrinsic_ssbo_atomic_imin
:
7674 case nir_intrinsic_ssbo_atomic_umin
:
7675 case nir_intrinsic_ssbo_atomic_imax
:
7676 case nir_intrinsic_ssbo_atomic_umax
:
7677 case nir_intrinsic_ssbo_atomic_and
:
7678 case nir_intrinsic_ssbo_atomic_or
:
7679 case nir_intrinsic_ssbo_atomic_xor
:
7680 case nir_intrinsic_ssbo_atomic_exchange
:
7681 case nir_intrinsic_ssbo_atomic_comp_swap
:
7682 visit_atomic_ssbo(ctx
, instr
);
7684 case nir_intrinsic_load_scratch
:
7685 visit_load_scratch(ctx
, instr
);
7687 case nir_intrinsic_store_scratch
:
7688 visit_store_scratch(ctx
, instr
);
7690 case nir_intrinsic_get_buffer_size
:
7691 visit_get_buffer_size(ctx
, instr
);
7693 case nir_intrinsic_control_barrier
: {
7694 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7695 /* GFX6 only (thanks to a hw bug workaround):
7696 * The real barrier instruction isn’t needed, because an entire patch
7697 * always fits into a single wave.
7702 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7703 bld
.sopp(aco_opcode::s_barrier
);
7707 case nir_intrinsic_memory_barrier_tcs_patch
:
7708 case nir_intrinsic_group_memory_barrier
:
7709 case nir_intrinsic_memory_barrier
:
7710 case nir_intrinsic_memory_barrier_buffer
:
7711 case nir_intrinsic_memory_barrier_image
:
7712 case nir_intrinsic_memory_barrier_shared
:
7713 emit_memory_barrier(ctx
, instr
);
7715 case nir_intrinsic_load_num_work_groups
: {
7716 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7717 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7718 emit_split_vector(ctx
, dst
, 3);
7721 case nir_intrinsic_load_local_invocation_id
: {
7722 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7723 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7724 emit_split_vector(ctx
, dst
, 3);
7727 case nir_intrinsic_load_work_group_id
: {
7728 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7729 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7730 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7731 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7732 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7733 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7734 emit_split_vector(ctx
, dst
, 3);
7737 case nir_intrinsic_load_local_invocation_index
: {
7738 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7740 /* The tg_size bits [6:11] contain the subgroup id,
7741 * we need this multiplied by the wave size, and then OR the thread id to it.
7743 if (ctx
->program
->wave_size
== 64) {
7744 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7745 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7746 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7747 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7749 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7750 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7751 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7752 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7756 case nir_intrinsic_load_subgroup_id
: {
7757 if (ctx
->stage
== compute_cs
) {
7758 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7759 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7761 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7765 case nir_intrinsic_load_subgroup_invocation
: {
7766 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7769 case nir_intrinsic_load_num_subgroups
: {
7770 if (ctx
->stage
== compute_cs
)
7771 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7772 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7774 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7777 case nir_intrinsic_ballot
: {
7778 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7779 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7780 Definition tmp
= bld
.def(dst
.regClass());
7781 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7782 if (instr
->src
[0].ssa
->bit_size
== 1) {
7783 assert(src
.regClass() == bld
.lm
);
7784 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7785 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7786 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7787 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7788 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7791 nir_print_instr(&instr
->instr
, stderr
);
7792 fprintf(stderr
, "\n");
7794 if (dst
.size() != bld
.lm
.size()) {
7795 /* Wave32 with ballot size set to 64 */
7796 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7798 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7801 case nir_intrinsic_shuffle
:
7802 case nir_intrinsic_read_invocation
: {
7803 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7804 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7805 emit_uniform_subgroup(ctx
, instr
, src
);
7807 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7808 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7809 tid
= bld
.as_uniform(tid
);
7810 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7811 if (src
.regClass() == v1
) {
7812 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7813 } else if (src
.regClass() == v2
) {
7814 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7815 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7816 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7817 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7818 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7819 emit_split_vector(ctx
, dst
, 2);
7820 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7821 assert(src
.regClass() == bld
.lm
);
7822 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7823 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7824 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7825 assert(src
.regClass() == bld
.lm
);
7827 if (ctx
->program
->chip_class
<= GFX7
)
7828 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7829 else if (ctx
->program
->wave_size
== 64)
7830 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7832 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7833 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7834 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7835 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7837 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7838 nir_print_instr(&instr
->instr
, stderr
);
7839 fprintf(stderr
, "\n");
7844 case nir_intrinsic_load_sample_id
: {
7845 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7846 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7849 case nir_intrinsic_load_sample_mask_in
: {
7850 visit_load_sample_mask_in(ctx
, instr
);
7853 case nir_intrinsic_read_first_invocation
: {
7854 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7855 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7856 if (src
.regClass() == v1
) {
7858 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7860 } else if (src
.regClass() == v2
) {
7861 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7863 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7864 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7865 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7866 emit_split_vector(ctx
, dst
, 2);
7867 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7868 assert(src
.regClass() == bld
.lm
);
7869 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7870 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7871 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7872 } else if (src
.regClass() == s1
) {
7873 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7874 } else if (src
.regClass() == s2
) {
7875 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7877 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7878 nir_print_instr(&instr
->instr
, stderr
);
7879 fprintf(stderr
, "\n");
7883 case nir_intrinsic_vote_all
: {
7884 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7885 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7886 assert(src
.regClass() == bld
.lm
);
7887 assert(dst
.regClass() == bld
.lm
);
7889 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7890 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7891 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7894 case nir_intrinsic_vote_any
: {
7895 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7896 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7897 assert(src
.regClass() == bld
.lm
);
7898 assert(dst
.regClass() == bld
.lm
);
7900 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7901 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7904 case nir_intrinsic_reduce
:
7905 case nir_intrinsic_inclusive_scan
:
7906 case nir_intrinsic_exclusive_scan
: {
7907 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7908 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7909 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7910 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7911 nir_intrinsic_cluster_size(instr
) : 0;
7912 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7914 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7915 emit_uniform_subgroup(ctx
, instr
, src
);
7916 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7917 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7919 else if (op
== nir_op_iadd
)
7921 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7923 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7925 switch (instr
->intrinsic
) {
7926 case nir_intrinsic_reduce
:
7927 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7929 case nir_intrinsic_exclusive_scan
:
7930 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7932 case nir_intrinsic_inclusive_scan
:
7933 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7938 } else if (cluster_size
== 1) {
7939 bld
.copy(Definition(dst
), src
);
7941 src
= as_vgpr(ctx
, src
);
7945 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7960 unreachable("unknown reduction op");
7965 switch (instr
->intrinsic
) {
7966 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7967 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7968 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7970 unreachable("unknown reduce intrinsic");
7973 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7974 reduce
->operands
[0] = Operand(src
);
7975 // filled in by aco_reduce_assign.cpp, used internally as part of the
7977 assert(dst
.size() == 1 || dst
.size() == 2);
7978 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7979 reduce
->operands
[2] = Operand(v1
.as_linear());
7981 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7982 reduce
->definitions
[0] = Definition(tmp_dst
);
7983 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7984 reduce
->definitions
[2] = Definition();
7985 reduce
->definitions
[3] = Definition(scc
, s1
);
7986 reduce
->definitions
[4] = Definition();
7987 reduce
->reduce_op
= reduce_op
;
7988 reduce
->cluster_size
= cluster_size
;
7989 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7991 emit_wqm(ctx
, tmp_dst
, dst
);
7995 case nir_intrinsic_quad_broadcast
: {
7996 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7997 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7998 emit_uniform_subgroup(ctx
, instr
, src
);
8000 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8001 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
8002 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
8004 if (instr
->dest
.ssa
.bit_size
== 1) {
8005 assert(src
.regClass() == bld
.lm
);
8006 assert(dst
.regClass() == bld
.lm
);
8007 uint32_t half_mask
= 0x11111111u
<< lane
;
8008 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
8009 Temp tmp
= bld
.tmp(bld
.lm
);
8010 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
8011 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
8012 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
8013 emit_wqm(ctx
, tmp
, dst
);
8014 } else if (instr
->dest
.ssa
.bit_size
== 32) {
8015 if (ctx
->program
->chip_class
>= GFX8
)
8016 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
8018 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
8019 } else if (instr
->dest
.ssa
.bit_size
== 64) {
8020 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8021 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8022 if (ctx
->program
->chip_class
>= GFX8
) {
8023 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8024 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8026 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
8027 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
8029 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8030 emit_split_vector(ctx
, dst
, 2);
8032 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8033 nir_print_instr(&instr
->instr
, stderr
);
8034 fprintf(stderr
, "\n");
8039 case nir_intrinsic_quad_swap_horizontal
:
8040 case nir_intrinsic_quad_swap_vertical
:
8041 case nir_intrinsic_quad_swap_diagonal
:
8042 case nir_intrinsic_quad_swizzle_amd
: {
8043 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8044 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
8045 emit_uniform_subgroup(ctx
, instr
, src
);
8048 uint16_t dpp_ctrl
= 0;
8049 switch (instr
->intrinsic
) {
8050 case nir_intrinsic_quad_swap_horizontal
:
8051 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
8053 case nir_intrinsic_quad_swap_vertical
:
8054 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
8056 case nir_intrinsic_quad_swap_diagonal
:
8057 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
8059 case nir_intrinsic_quad_swizzle_amd
:
8060 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
8065 if (ctx
->program
->chip_class
< GFX8
)
8066 dpp_ctrl
|= (1 << 15);
8068 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8069 if (instr
->dest
.ssa
.bit_size
== 1) {
8070 assert(src
.regClass() == bld
.lm
);
8071 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
8072 if (ctx
->program
->chip_class
>= GFX8
)
8073 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8075 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8076 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
8077 emit_wqm(ctx
, tmp
, dst
);
8078 } else if (instr
->dest
.ssa
.bit_size
== 32) {
8080 if (ctx
->program
->chip_class
>= GFX8
)
8081 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8083 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8084 emit_wqm(ctx
, tmp
, dst
);
8085 } else if (instr
->dest
.ssa
.bit_size
== 64) {
8086 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8088 if (ctx
->program
->chip_class
>= GFX8
) {
8089 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8090 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8092 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8093 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8095 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8096 emit_split_vector(ctx
, dst
, 2);
8098 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8099 nir_print_instr(&instr
->instr
, stderr
);
8100 fprintf(stderr
, "\n");
8104 case nir_intrinsic_masked_swizzle_amd
: {
8105 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8106 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
8107 emit_uniform_subgroup(ctx
, instr
, src
);
8110 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8111 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
8112 if (dst
.regClass() == v1
) {
8114 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
8116 } else if (dst
.regClass() == v2
) {
8117 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8118 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8119 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
8120 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
8121 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8122 emit_split_vector(ctx
, dst
, 2);
8124 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8125 nir_print_instr(&instr
->instr
, stderr
);
8126 fprintf(stderr
, "\n");
8130 case nir_intrinsic_write_invocation_amd
: {
8131 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
8132 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
8133 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
8134 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8135 if (dst
.regClass() == v1
) {
8136 /* src2 is ignored for writelane. RA assigns the same reg for dst */
8137 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
8138 } else if (dst
.regClass() == v2
) {
8139 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
8140 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
8141 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
8142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
8143 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
8144 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
8145 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8146 emit_split_vector(ctx
, dst
, 2);
8148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8149 nir_print_instr(&instr
->instr
, stderr
);
8150 fprintf(stderr
, "\n");
8154 case nir_intrinsic_mbcnt_amd
: {
8155 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8156 RegClass rc
= RegClass(src
.type(), 1);
8157 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8158 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8159 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8160 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8161 emit_wqm(ctx
, wqm_tmp
, dst
);
8164 case nir_intrinsic_load_helper_invocation
: {
8165 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8166 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8167 ctx
->block
->kind
|= block_kind_needs_lowering
;
8168 ctx
->program
->needs_exact
= true;
8171 case nir_intrinsic_is_helper_invocation
: {
8172 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8173 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8174 ctx
->block
->kind
|= block_kind_needs_lowering
;
8175 ctx
->program
->needs_exact
= true;
8178 case nir_intrinsic_demote
:
8179 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8181 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8182 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8183 ctx
->block
->kind
|= block_kind_uses_demote
;
8184 ctx
->program
->needs_exact
= true;
8186 case nir_intrinsic_demote_if
: {
8187 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8188 assert(src
.regClass() == bld
.lm
);
8189 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8190 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8192 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8193 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8194 ctx
->block
->kind
|= block_kind_uses_demote
;
8195 ctx
->program
->needs_exact
= true;
8198 case nir_intrinsic_first_invocation
: {
8199 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8200 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8203 case nir_intrinsic_shader_clock
:
8204 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8205 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8207 case nir_intrinsic_load_vertex_id_zero_base
: {
8208 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8209 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8212 case nir_intrinsic_load_first_vertex
: {
8213 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8214 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8217 case nir_intrinsic_load_base_instance
: {
8218 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8219 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8222 case nir_intrinsic_load_instance_id
: {
8223 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8224 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8227 case nir_intrinsic_load_draw_id
: {
8228 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8229 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8232 case nir_intrinsic_load_invocation_id
: {
8233 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8235 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8236 if (ctx
->options
->chip_class
>= GFX10
)
8237 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8239 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8240 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8241 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8242 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8244 unreachable("Unsupported stage for load_invocation_id");
8249 case nir_intrinsic_load_primitive_id
: {
8250 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8252 switch (ctx
->shader
->info
.stage
) {
8253 case MESA_SHADER_GEOMETRY
:
8254 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8256 case MESA_SHADER_TESS_CTRL
:
8257 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8259 case MESA_SHADER_TESS_EVAL
:
8260 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8263 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8268 case nir_intrinsic_load_patch_vertices_in
: {
8269 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8270 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8272 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8273 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8276 case nir_intrinsic_emit_vertex_with_counter
: {
8277 visit_emit_vertex_with_counter(ctx
, instr
);
8280 case nir_intrinsic_end_primitive_with_counter
: {
8281 unsigned stream
= nir_intrinsic_stream_id(instr
);
8282 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8285 case nir_intrinsic_set_vertex_count
: {
8286 /* unused, the HW keeps track of this for us */
8290 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8291 nir_print_instr(&instr
->instr
, stderr
);
8292 fprintf(stderr
, "\n");
8300 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8301 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8302 enum glsl_base_type
*stype
)
8304 nir_deref_instr
*texture_deref_instr
= NULL
;
8305 nir_deref_instr
*sampler_deref_instr
= NULL
;
8308 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8309 switch (instr
->src
[i
].src_type
) {
8310 case nir_tex_src_texture_deref
:
8311 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8313 case nir_tex_src_sampler_deref
:
8314 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8316 case nir_tex_src_plane
:
8317 plane
= nir_src_as_int(instr
->src
[i
].src
);
8324 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8326 if (!sampler_deref_instr
)
8327 sampler_deref_instr
= texture_deref_instr
;
8330 assert(instr
->op
!= nir_texop_txf_ms
&&
8331 instr
->op
!= nir_texop_samples_identical
);
8332 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8333 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8334 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8335 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8336 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8337 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8339 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8342 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8344 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8345 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8346 Builder
bld(ctx
->program
, ctx
->block
);
8348 /* to avoid unnecessary moves, we split and recombine sampler and image */
8349 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8350 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8351 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8352 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8353 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8354 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8355 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8356 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8358 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8359 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8360 img
[0], img
[1], img
[2], img
[3],
8361 img
[4], img
[5], img
[6], img
[7]);
8362 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8363 samp
[0], samp
[1], samp
[2], samp
[3]);
8366 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8367 instr
->op
== nir_texop_samples_identical
))
8368 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8371 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8372 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8374 Builder
bld(ctx
->program
, ctx
->block
);
8376 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8377 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8378 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8380 Operand
neg_one(0xbf800000u
);
8381 Operand
one(0x3f800000u
);
8382 Operand
two(0x40000000u
);
8383 Operand
four(0x40800000u
);
8385 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8386 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8387 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8389 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8390 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8391 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8392 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8395 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8396 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8397 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8399 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8402 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8403 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8404 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8407 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8408 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8410 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8411 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8414 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8416 Builder
bld(ctx
->program
, ctx
->block
);
8417 Temp ma
, tc
, sc
, id
;
8420 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8422 // see comment in ac_prepare_cube_coords()
8423 if (ctx
->options
->chip_class
<= GFX8
)
8424 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8427 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8429 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8430 vop3a
->operands
[0] = Operand(ma
);
8431 vop3a
->abs
[0] = true;
8432 Temp invma
= bld
.tmp(v1
);
8433 vop3a
->definitions
[0] = Definition(invma
);
8434 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8436 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8438 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8440 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8442 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8444 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8447 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8448 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8450 for (unsigned i
= 0; i
< 2; i
++) {
8451 // see comment in ac_prepare_cube_coords()
8453 Temp deriv_sc
, deriv_tc
;
8454 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8455 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8457 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8459 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8460 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8461 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8462 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8463 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8464 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8465 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8468 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8469 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8473 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8480 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8482 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8484 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8485 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8488 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8489 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8490 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8494 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8496 Builder
bld(ctx
->program
, ctx
->block
);
8497 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8498 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8499 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8500 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8501 std::vector
<Temp
> coords
;
8502 std::vector
<Temp
> derivs
;
8503 nir_const_value
*sample_index_cv
= NULL
;
8504 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8505 enum glsl_base_type stype
;
8506 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8508 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8509 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8510 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8511 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8513 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8514 switch (instr
->src
[i
].src_type
) {
8515 case nir_tex_src_coord
: {
8516 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8517 for (unsigned i
= 0; i
< coord
.size(); i
++)
8518 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8521 case nir_tex_src_bias
:
8522 if (instr
->op
== nir_texop_txb
) {
8523 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8527 case nir_tex_src_lod
: {
8528 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8530 if (val
&& val
->f32
<= 0.0) {
8533 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8538 case nir_tex_src_comparator
:
8539 if (instr
->is_shadow
) {
8540 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8544 case nir_tex_src_offset
:
8545 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8546 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8549 case nir_tex_src_ddx
:
8550 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8553 case nir_tex_src_ddy
:
8554 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8557 case nir_tex_src_ms_index
:
8558 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8559 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8560 has_sample_index
= true;
8562 case nir_tex_src_texture_offset
:
8563 case nir_tex_src_sampler_offset
:
8569 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8570 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8572 if (instr
->op
== nir_texop_texture_samples
) {
8573 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8575 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8576 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8577 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8578 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8580 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8581 samples
, Operand(1u), bld
.scc(is_msaa
));
8585 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8586 aco_ptr
<Instruction
> tmp_instr
;
8587 Temp acc
, pack
= Temp();
8589 uint32_t pack_const
= 0;
8590 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8591 if (!const_offset
[i
])
8593 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8596 if (offset
.type() == RegType::sgpr
) {
8597 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8598 if (const_offset
[i
])
8601 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8602 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8605 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8608 if (pack
== Temp()) {
8611 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8615 if (pack_const
&& pack
!= Temp())
8616 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8618 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8619 if (const_offset
[i
])
8622 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8623 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8626 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8629 if (pack
== Temp()) {
8632 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8636 if (pack_const
&& pack
!= Temp())
8637 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8639 if (pack_const
&& pack
== Temp())
8640 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8641 else if (pack
== Temp())
8647 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8648 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8650 /* pack derivatives */
8651 if (has_ddx
|| has_ddy
) {
8652 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8653 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8654 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8655 derivs
= {ddx
, zero
, ddy
, zero
};
8657 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8658 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8659 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8660 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8665 if (instr
->coord_components
> 1 &&
8666 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8668 instr
->op
!= nir_texop_txf
)
8669 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8671 if (instr
->coord_components
> 2 &&
8672 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8673 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8674 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8675 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8677 instr
->op
!= nir_texop_txf
&&
8678 instr
->op
!= nir_texop_txf_ms
&&
8679 instr
->op
!= nir_texop_fragment_fetch
&&
8680 instr
->op
!= nir_texop_fragment_mask_fetch
)
8681 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8683 if (ctx
->options
->chip_class
== GFX9
&&
8684 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8685 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8686 assert(coords
.size() > 0 && coords
.size() < 3);
8688 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8689 Operand((uint32_t) 0) :
8690 Operand((uint32_t) 0x3f000000)));
8693 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8695 if (instr
->op
== nir_texop_samples_identical
)
8696 resource
= fmask_ptr
;
8698 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8699 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8700 instr
->op
!= nir_texop_txs
&&
8701 instr
->op
!= nir_texop_fragment_fetch
&&
8702 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8703 assert(has_sample_index
);
8704 Operand
op(sample_index
);
8705 if (sample_index_cv
)
8706 op
= Operand(sample_index_cv
->u32
);
8707 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8710 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8711 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8712 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8713 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8718 /* Build tex instruction */
8719 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8720 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8721 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8723 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8726 /* gather4 selects the component by dmask and always returns vec4 */
8727 if (instr
->op
== nir_texop_tg4
) {
8728 assert(instr
->dest
.ssa
.num_components
== 4);
8729 if (instr
->is_shadow
)
8732 dmask
= 1 << instr
->component
;
8733 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8734 tmp_dst
= bld
.tmp(v4
);
8735 } else if (instr
->op
== nir_texop_samples_identical
) {
8736 tmp_dst
= bld
.tmp(v1
);
8737 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8738 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8741 aco_ptr
<MIMG_instruction
> tex
;
8742 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8744 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8746 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8747 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8750 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8751 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8753 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8754 tex
->operands
[0] = Operand(resource
);
8755 tex
->operands
[1] = Operand(s4
); /* no sampler */
8756 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8757 if (ctx
->options
->chip_class
== GFX9
&&
8758 instr
->op
== nir_texop_txs
&&
8759 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8761 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8762 } else if (instr
->op
== nir_texop_query_levels
) {
8763 tex
->dmask
= 1 << 3;
8768 tex
->definitions
[0] = Definition(tmp_dst
);
8770 tex
->can_reorder
= true;
8771 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8774 /* divide 3rd value by 6 by multiplying with magic number */
8775 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8776 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8777 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8778 assert(instr
->dest
.ssa
.num_components
== 3);
8779 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8780 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8781 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8782 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8787 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8791 Temp tg4_compare_cube_wa64
= Temp();
8793 if (tg4_integer_workarounds
) {
8794 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8795 tex
->operands
[0] = Operand(resource
);
8796 tex
->operands
[1] = Operand(s4
); /* no sampler */
8797 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8801 Temp size
= bld
.tmp(v2
);
8802 tex
->definitions
[0] = Definition(size
);
8803 tex
->can_reorder
= true;
8804 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8805 emit_split_vector(ctx
, size
, size
.size());
8808 for (unsigned i
= 0; i
< 2; i
++) {
8809 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8810 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8811 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8812 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8815 Temp new_coords
[2] = {
8816 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8817 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8820 if (tg4_integer_cube_workaround
) {
8821 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8822 Temp desc
[resource
.size()];
8823 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8824 Format::PSEUDO
, 1, resource
.size())};
8825 split
->operands
[0] = Operand(resource
);
8826 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8827 desc
[i
] = bld
.tmp(s1
);
8828 split
->definitions
[i
] = Definition(desc
[i
]);
8830 ctx
->block
->instructions
.emplace_back(std::move(split
));
8832 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8833 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8834 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8837 if (stype
== GLSL_TYPE_UINT
) {
8838 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8839 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8840 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8841 bld
.scc(compare_cube_wa
));
8843 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8844 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8845 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8846 bld
.scc(compare_cube_wa
));
8848 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8849 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8851 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8853 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8854 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8855 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8857 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8858 Format::PSEUDO
, resource
.size(), 1)};
8859 for (unsigned i
= 0; i
< resource
.size(); i
++)
8860 vec
->operands
[i
] = Operand(desc
[i
]);
8861 resource
= bld
.tmp(resource
.regClass());
8862 vec
->definitions
[0] = Definition(resource
);
8863 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8865 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8866 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8867 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8868 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8870 coords
[0] = new_coords
[0];
8871 coords
[1] = new_coords
[1];
8874 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8875 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8877 assert(coords
.size() == 1);
8878 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8882 op
= aco_opcode::buffer_load_format_x
; break;
8884 op
= aco_opcode::buffer_load_format_xy
; break;
8886 op
= aco_opcode::buffer_load_format_xyz
; break;
8888 op
= aco_opcode::buffer_load_format_xyzw
; break;
8890 unreachable("Tex instruction loads more than 4 components.");
8893 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8894 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8897 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8899 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8900 mubuf
->operands
[0] = Operand(resource
);
8901 mubuf
->operands
[1] = Operand(coords
[0]);
8902 mubuf
->operands
[2] = Operand((uint32_t) 0);
8903 mubuf
->definitions
[0] = Definition(tmp_dst
);
8904 mubuf
->idxen
= true;
8905 mubuf
->can_reorder
= true;
8906 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8908 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8912 /* gather MIMG address components */
8913 std::vector
<Temp
> args
;
8915 args
.emplace_back(offset
);
8917 args
.emplace_back(bias
);
8919 args
.emplace_back(compare
);
8921 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8923 args
.insert(args
.end(), coords
.begin(), coords
.end());
8924 if (has_sample_index
)
8925 args
.emplace_back(sample_index
);
8927 args
.emplace_back(lod
);
8929 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8930 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8931 vec
->definitions
[0] = Definition(arg
);
8932 for (unsigned i
= 0; i
< args
.size(); i
++)
8933 vec
->operands
[i
] = Operand(args
[i
]);
8934 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8937 if (instr
->op
== nir_texop_txf
||
8938 instr
->op
== nir_texop_txf_ms
||
8939 instr
->op
== nir_texop_samples_identical
||
8940 instr
->op
== nir_texop_fragment_fetch
||
8941 instr
->op
== nir_texop_fragment_mask_fetch
) {
8942 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8943 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8944 tex
->operands
[0] = Operand(resource
);
8945 tex
->operands
[1] = Operand(s4
); /* no sampler */
8946 tex
->operands
[2] = Operand(arg
);
8951 tex
->definitions
[0] = Definition(tmp_dst
);
8952 tex
->can_reorder
= true;
8953 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8955 if (instr
->op
== nir_texop_samples_identical
) {
8956 assert(dmask
== 1 && dst
.regClass() == v1
);
8957 assert(dst
.id() != tmp_dst
.id());
8959 Temp tmp
= bld
.tmp(bld
.lm
);
8960 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8961 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8964 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8969 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8970 aco_opcode opcode
= aco_opcode::image_sample
;
8971 if (has_offset
) { /* image_sample_*_o */
8973 opcode
= aco_opcode::image_sample_c_o
;
8975 opcode
= aco_opcode::image_sample_c_d_o
;
8977 opcode
= aco_opcode::image_sample_c_b_o
;
8979 opcode
= aco_opcode::image_sample_c_lz_o
;
8981 opcode
= aco_opcode::image_sample_c_l_o
;
8983 opcode
= aco_opcode::image_sample_o
;
8985 opcode
= aco_opcode::image_sample_d_o
;
8987 opcode
= aco_opcode::image_sample_b_o
;
8989 opcode
= aco_opcode::image_sample_lz_o
;
8991 opcode
= aco_opcode::image_sample_l_o
;
8993 } else { /* no offset */
8995 opcode
= aco_opcode::image_sample_c
;
8997 opcode
= aco_opcode::image_sample_c_d
;
8999 opcode
= aco_opcode::image_sample_c_b
;
9001 opcode
= aco_opcode::image_sample_c_lz
;
9003 opcode
= aco_opcode::image_sample_c_l
;
9005 opcode
= aco_opcode::image_sample
;
9007 opcode
= aco_opcode::image_sample_d
;
9009 opcode
= aco_opcode::image_sample_b
;
9011 opcode
= aco_opcode::image_sample_lz
;
9013 opcode
= aco_opcode::image_sample_l
;
9017 if (instr
->op
== nir_texop_tg4
) {
9019 opcode
= aco_opcode::image_gather4_lz_o
;
9021 opcode
= aco_opcode::image_gather4_c_lz_o
;
9023 opcode
= aco_opcode::image_gather4_lz
;
9025 opcode
= aco_opcode::image_gather4_c_lz
;
9027 } else if (instr
->op
== nir_texop_lod
) {
9028 opcode
= aco_opcode::image_get_lod
;
9031 /* we don't need the bias, sample index, compare value or offset to be
9032 * computed in WQM but if the p_create_vector copies the coordinates, then it
9033 * needs to be in WQM */
9034 if (ctx
->stage
== fragment_fs
&&
9035 !has_derivs
&& !has_lod
&& !level_zero
&&
9036 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
9037 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
9038 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
9040 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
9041 tex
->operands
[0] = Operand(resource
);
9042 tex
->operands
[1] = Operand(sampler
);
9043 tex
->operands
[2] = Operand(arg
);
9047 tex
->definitions
[0] = Definition(tmp_dst
);
9048 tex
->can_reorder
= true;
9049 ctx
->block
->instructions
.emplace_back(std::move(tex
));
9051 if (tg4_integer_cube_workaround
) {
9052 assert(tmp_dst
.id() != dst
.id());
9053 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
9055 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
9057 for (unsigned i
= 0; i
< dst
.size(); i
++) {
9058 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
9060 if (stype
== GLSL_TYPE_UINT
)
9061 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
9063 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
9064 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
9066 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
9067 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
9068 val
[0], val
[1], val
[2], val
[3]);
9070 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
9071 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
9076 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
9078 Temp tmp
= get_ssa_temp(ctx
, ssa
);
9079 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
9080 return Operand(tmp
.regClass());
9082 return Operand(tmp
);
9085 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
9087 aco_ptr
<Pseudo_instruction
> phi
;
9088 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
9089 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
9091 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
9092 logical
|= ctx
->block
->kind
& block_kind_merge
;
9093 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
9095 /* we want a sorted list of sources, since the predecessor list is also sorted */
9096 std::map
<unsigned, nir_ssa_def
*> phi_src
;
9097 nir_foreach_phi_src(src
, instr
)
9098 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
9100 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
9101 unsigned num_operands
= 0;
9102 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
9103 unsigned num_defined
= 0;
9104 unsigned cur_pred_idx
= 0;
9105 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
9106 if (cur_pred_idx
< preds
.size()) {
9107 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
9108 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
9109 unsigned skipped
= 0;
9110 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9112 if (cur_pred_idx
+ skipped
< preds
.size()) {
9113 for (unsigned i
= 0; i
< skipped
; i
++)
9114 operands
[num_operands
++] = Operand(dst
.regClass());
9115 cur_pred_idx
+= skipped
;
9120 /* Handle missing predecessors at the end. This shouldn't happen with loop
9121 * headers and we can't ignore these sources for loop header phis. */
9122 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9125 Operand op
= get_phi_operand(ctx
, src
.second
);
9126 operands
[num_operands
++] = op
;
9127 num_defined
+= !op
.isUndefined();
9129 /* handle block_kind_continue_or_break at loop exit blocks */
9130 while (cur_pred_idx
++ < preds
.size())
9131 operands
[num_operands
++] = Operand(dst
.regClass());
9133 /* If the loop ends with a break, still add a linear continue edge in case
9134 * that break is divergent or continue_or_break is used. We'll either remove
9135 * this operand later in visit_loop() if it's not necessary or replace the
9136 * undef with something correct. */
9137 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9138 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9139 nir_block
*last
= nir_loop_last_block(loop
);
9140 if (last
->successors
[0] != instr
->instr
.block
)
9141 operands
[num_operands
++] = Operand(RegClass());
9144 if (num_defined
== 0) {
9145 Builder
bld(ctx
->program
, ctx
->block
);
9146 if (dst
.regClass() == s1
) {
9147 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9148 } else if (dst
.regClass() == v1
) {
9149 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9151 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9152 for (unsigned i
= 0; i
< dst
.size(); i
++)
9153 vec
->operands
[i
] = Operand(0u);
9154 vec
->definitions
[0] = Definition(dst
);
9155 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9160 /* we can use a linear phi in some cases if one src is undef */
9161 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9162 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9164 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9165 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9166 assert(invert
->kind
& block_kind_invert
);
9168 unsigned then_block
= invert
->linear_preds
[0];
9170 Block
* insert_block
= NULL
;
9171 for (unsigned i
= 0; i
< num_operands
; i
++) {
9172 Operand op
= operands
[i
];
9173 if (op
.isUndefined())
9175 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9176 phi
->operands
[0] = op
;
9179 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9180 phi
->operands
[1] = Operand(dst
.regClass());
9181 phi
->definitions
[0] = Definition(dst
);
9182 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9186 /* try to scalarize vector phis */
9187 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9188 // TODO: scalarize linear phis on divergent ifs
9189 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9190 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9191 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9192 Operand src
= operands
[i
];
9193 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9194 can_scalarize
= false;
9196 if (can_scalarize
) {
9197 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9198 assert(dst
.size() % num_components
== 0);
9199 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9201 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9202 for (unsigned k
= 0; k
< num_components
; k
++) {
9203 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9204 for (unsigned i
= 0; i
< num_operands
; i
++) {
9205 Operand src
= operands
[i
];
9206 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9208 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9209 phi
->definitions
[0] = Definition(phi_dst
);
9210 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9211 new_vec
[k
] = phi_dst
;
9212 vec
->operands
[k
] = Operand(phi_dst
);
9214 vec
->definitions
[0] = Definition(dst
);
9215 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9216 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9221 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9222 for (unsigned i
= 0; i
< num_operands
; i
++)
9223 phi
->operands
[i
] = operands
[i
];
9224 phi
->definitions
[0] = Definition(dst
);
9225 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9229 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9231 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9233 assert(dst
.type() == RegType::sgpr
);
9235 if (dst
.size() == 1) {
9236 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9238 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9239 for (unsigned i
= 0; i
< dst
.size(); i
++)
9240 vec
->operands
[i
] = Operand(0u);
9241 vec
->definitions
[0] = Definition(dst
);
9242 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9246 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9248 Builder
bld(ctx
->program
, ctx
->block
);
9249 Block
*logical_target
;
9250 append_logical_end(ctx
->block
);
9251 unsigned idx
= ctx
->block
->index
;
9253 switch (instr
->type
) {
9254 case nir_jump_break
:
9255 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9256 add_logical_edge(idx
, logical_target
);
9257 ctx
->block
->kind
|= block_kind_break
;
9259 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9260 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9261 /* uniform break - directly jump out of the loop */
9262 ctx
->block
->kind
|= block_kind_uniform
;
9263 ctx
->cf_info
.has_branch
= true;
9264 bld
.branch(aco_opcode::p_branch
);
9265 add_linear_edge(idx
, logical_target
);
9268 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9269 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9271 case nir_jump_continue
:
9272 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9273 add_logical_edge(idx
, logical_target
);
9274 ctx
->block
->kind
|= block_kind_continue
;
9276 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9277 /* for potential uniform breaks after this continue,
9278 we must ensure that they are handled correctly */
9279 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9280 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9281 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9283 /* uniform continue - directly jump to the loop header */
9284 ctx
->block
->kind
|= block_kind_uniform
;
9285 ctx
->cf_info
.has_branch
= true;
9286 bld
.branch(aco_opcode::p_branch
);
9287 add_linear_edge(idx
, logical_target
);
9292 fprintf(stderr
, "Unknown NIR jump instr: ");
9293 nir_print_instr(&instr
->instr
, stderr
);
9294 fprintf(stderr
, "\n");
9298 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9299 ctx
->cf_info
.exec_potentially_empty_break
= true;
9300 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9303 /* remove critical edges from linear CFG */
9304 bld
.branch(aco_opcode::p_branch
);
9305 Block
* break_block
= ctx
->program
->create_and_insert_block();
9306 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9307 break_block
->kind
|= block_kind_uniform
;
9308 add_linear_edge(idx
, break_block
);
9309 /* the loop_header pointer might be invalidated by this point */
9310 if (instr
->type
== nir_jump_continue
)
9311 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9312 add_linear_edge(break_block
->index
, logical_target
);
9313 bld
.reset(break_block
);
9314 bld
.branch(aco_opcode::p_branch
);
9316 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9317 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9318 add_linear_edge(idx
, continue_block
);
9319 append_logical_start(continue_block
);
9320 ctx
->block
= continue_block
;
9324 void visit_block(isel_context
*ctx
, nir_block
*block
)
9326 nir_foreach_instr(instr
, block
) {
9327 switch (instr
->type
) {
9328 case nir_instr_type_alu
:
9329 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9331 case nir_instr_type_load_const
:
9332 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9334 case nir_instr_type_intrinsic
:
9335 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9337 case nir_instr_type_tex
:
9338 visit_tex(ctx
, nir_instr_as_tex(instr
));
9340 case nir_instr_type_phi
:
9341 visit_phi(ctx
, nir_instr_as_phi(instr
));
9343 case nir_instr_type_ssa_undef
:
9344 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9346 case nir_instr_type_deref
:
9348 case nir_instr_type_jump
:
9349 visit_jump(ctx
, nir_instr_as_jump(instr
));
9352 fprintf(stderr
, "Unknown NIR instr type: ");
9353 nir_print_instr(instr
, stderr
);
9354 fprintf(stderr
, "\n");
9359 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9360 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9365 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9366 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9368 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9369 RegClass rc
= vals
[0].regClass();
9371 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9373 unsigned next_pred
= 1;
9375 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9376 Block
& block
= ctx
->program
->blocks
[idx
];
9377 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9378 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9382 if (block
.kind
& block_kind_continue
) {
9383 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9388 bool all_same
= true;
9389 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9390 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9394 val
= vals
[block
.linear_preds
[0] - first
];
9396 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9397 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9398 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9399 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9400 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9401 phi
->definitions
[0] = Definition(val
.getTemp());
9402 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9404 vals
[idx
- first
] = val
;
9407 return vals
[last
- first
];
9410 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9412 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9413 append_logical_end(ctx
->block
);
9414 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9415 Builder
bld(ctx
->program
, ctx
->block
);
9416 bld
.branch(aco_opcode::p_branch
);
9417 unsigned loop_preheader_idx
= ctx
->block
->index
;
9419 Block loop_exit
= Block();
9420 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9421 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9423 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9424 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9425 loop_header
->kind
|= block_kind_loop_header
;
9426 add_edge(loop_preheader_idx
, loop_header
);
9427 ctx
->block
= loop_header
;
9429 /* emit loop body */
9430 unsigned loop_header_idx
= loop_header
->index
;
9431 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9432 append_logical_start(ctx
->block
);
9433 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9435 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9436 if (!ctx
->cf_info
.has_branch
) {
9437 append_logical_end(ctx
->block
);
9438 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9439 /* Discards can result in code running with an empty exec mask.
9440 * This would result in divergent breaks not ever being taken. As a
9441 * workaround, break the loop when the loop mask is empty instead of
9442 * always continuing. */
9443 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9444 unsigned block_idx
= ctx
->block
->index
;
9446 /* create helper blocks to avoid critical edges */
9447 Block
*break_block
= ctx
->program
->create_and_insert_block();
9448 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9449 break_block
->kind
= block_kind_uniform
;
9450 bld
.reset(break_block
);
9451 bld
.branch(aco_opcode::p_branch
);
9452 add_linear_edge(block_idx
, break_block
);
9453 add_linear_edge(break_block
->index
, &loop_exit
);
9455 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9456 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9457 continue_block
->kind
= block_kind_uniform
;
9458 bld
.reset(continue_block
);
9459 bld
.branch(aco_opcode::p_branch
);
9460 add_linear_edge(block_idx
, continue_block
);
9461 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9463 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9464 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9465 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9467 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9468 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9469 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9471 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9474 bld
.reset(ctx
->block
);
9475 bld
.branch(aco_opcode::p_branch
);
9478 /* Fixup phis in loop header from unreachable blocks.
9479 * has_branch/has_divergent_branch also indicates if the loop ends with a
9480 * break/continue instruction, but we don't emit those if unreachable=true */
9482 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9483 bool linear
= ctx
->cf_info
.has_branch
;
9484 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9485 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9486 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9487 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9488 /* the last operand should be the one that needs to be removed */
9489 instr
->operands
.pop_back();
9490 } else if (!is_phi(instr
)) {
9496 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9497 * and the previous one shouldn't both happen at once because a break in the
9498 * merge block would get CSE'd */
9499 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9500 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9501 Operand vals
[num_vals
];
9502 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9503 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9504 if (ctx
->cf_info
.has_branch
)
9505 instr
->operands
.pop_back();
9507 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9508 } else if (!is_phi(instr
)) {
9514 ctx
->cf_info
.has_branch
= false;
9516 // TODO: if the loop has not a single exit, we must add one °°
9517 /* emit loop successor block */
9518 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9519 append_logical_start(ctx
->block
);
9522 // TODO: check if it is beneficial to not branch on continues
9523 /* trim linear phis in loop header */
9524 for (auto&& instr
: loop_entry
->instructions
) {
9525 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9526 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9527 new_phi
->definitions
[0] = instr
->definitions
[0];
9528 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9529 new_phi
->operands
[i
] = instr
->operands
[i
];
9530 /* check that the remaining operands are all the same */
9531 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9532 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9533 instr
.swap(new_phi
);
9534 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9543 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9547 append_logical_end(ctx
->block
);
9548 ctx
->block
->kind
|= block_kind_branch
;
9550 /* branch to linear then block */
9551 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9552 aco_ptr
<Pseudo_branch_instruction
> branch
;
9553 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9554 branch
->operands
[0] = Operand(cond
);
9555 ctx
->block
->instructions
.push_back(std::move(branch
));
9557 ic
->BB_if_idx
= ctx
->block
->index
;
9558 ic
->BB_invert
= Block();
9559 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9560 /* Invert blocks are intentionally not marked as top level because they
9561 * are not part of the logical cfg. */
9562 ic
->BB_invert
.kind
|= block_kind_invert
;
9563 ic
->BB_endif
= Block();
9564 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9565 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9567 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9568 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9569 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9570 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9571 ctx
->cf_info
.parent_if
.is_divergent
= true;
9573 /* divergent branches use cbranch_execz */
9574 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9575 ctx
->cf_info
.exec_potentially_empty_break
= false;
9576 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9578 /** emit logical then block */
9579 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9580 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9581 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9582 ctx
->block
= BB_then_logical
;
9583 append_logical_start(BB_then_logical
);
9586 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9588 Block
*BB_then_logical
= ctx
->block
;
9589 append_logical_end(BB_then_logical
);
9590 /* branch from logical then block to invert block */
9591 aco_ptr
<Pseudo_branch_instruction
> branch
;
9592 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9593 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9594 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9595 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9596 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9597 BB_then_logical
->kind
|= block_kind_uniform
;
9598 assert(!ctx
->cf_info
.has_branch
);
9599 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9600 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9602 /** emit linear then block */
9603 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9604 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9605 BB_then_linear
->kind
|= block_kind_uniform
;
9606 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9607 /* branch from linear then block to invert block */
9608 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9609 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9610 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9612 /** emit invert merge block */
9613 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9614 ic
->invert_idx
= ctx
->block
->index
;
9616 /* branch to linear else block (skip else) */
9617 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9618 branch
->operands
[0] = Operand(ic
->cond
);
9619 ctx
->block
->instructions
.push_back(std::move(branch
));
9621 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9622 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9623 ic
->exec_potentially_empty_break_depth_old
=
9624 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9625 /* divergent branches use cbranch_execz */
9626 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9627 ctx
->cf_info
.exec_potentially_empty_break
= false;
9628 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9630 /** emit logical else block */
9631 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9632 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9633 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9634 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9635 ctx
->block
= BB_else_logical
;
9636 append_logical_start(BB_else_logical
);
9639 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9641 Block
*BB_else_logical
= ctx
->block
;
9642 append_logical_end(BB_else_logical
);
9644 /* branch from logical else block to endif block */
9645 aco_ptr
<Pseudo_branch_instruction
> branch
;
9646 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9647 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9648 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9649 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9650 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9651 BB_else_logical
->kind
|= block_kind_uniform
;
9653 assert(!ctx
->cf_info
.has_branch
);
9654 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9657 /** emit linear else block */
9658 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9659 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9660 BB_else_linear
->kind
|= block_kind_uniform
;
9661 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9663 /* branch from linear else block to endif block */
9664 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9665 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9666 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9669 /** emit endif merge block */
9670 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9671 append_logical_start(ctx
->block
);
9674 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9675 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9676 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9677 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9678 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9679 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9680 !ctx
->cf_info
.parent_if
.is_divergent
) {
9681 ctx
->cf_info
.exec_potentially_empty_break
= false;
9682 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9684 /* uniform control flow never has an empty exec-mask */
9685 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9686 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9687 ctx
->cf_info
.exec_potentially_empty_break
= false;
9688 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9692 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9694 assert(cond
.regClass() == s1
);
9696 append_logical_end(ctx
->block
);
9697 ctx
->block
->kind
|= block_kind_uniform
;
9699 aco_ptr
<Pseudo_branch_instruction
> branch
;
9700 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9701 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9702 branch
->operands
[0] = Operand(cond
);
9703 branch
->operands
[0].setFixed(scc
);
9704 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9706 ic
->BB_if_idx
= ctx
->block
->index
;
9707 ic
->BB_endif
= Block();
9708 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9709 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9711 ctx
->cf_info
.has_branch
= false;
9712 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9714 /** emit then block */
9715 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9716 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9717 add_edge(ic
->BB_if_idx
, BB_then
);
9718 append_logical_start(BB_then
);
9719 ctx
->block
= BB_then
;
9722 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9724 Block
*BB_then
= ctx
->block
;
9726 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9727 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9729 if (!ic
->uniform_has_then_branch
) {
9730 append_logical_end(BB_then
);
9731 /* branch from then block to endif block */
9732 aco_ptr
<Pseudo_branch_instruction
> branch
;
9733 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9734 BB_then
->instructions
.emplace_back(std::move(branch
));
9735 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9736 if (!ic
->then_branch_divergent
)
9737 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9738 BB_then
->kind
|= block_kind_uniform
;
9741 ctx
->cf_info
.has_branch
= false;
9742 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9744 /** emit else block */
9745 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9746 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9747 add_edge(ic
->BB_if_idx
, BB_else
);
9748 append_logical_start(BB_else
);
9749 ctx
->block
= BB_else
;
9752 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9754 Block
*BB_else
= ctx
->block
;
9756 if (!ctx
->cf_info
.has_branch
) {
9757 append_logical_end(BB_else
);
9758 /* branch from then block to endif block */
9759 aco_ptr
<Pseudo_branch_instruction
> branch
;
9760 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9761 BB_else
->instructions
.emplace_back(std::move(branch
));
9762 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9763 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9764 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9765 BB_else
->kind
|= block_kind_uniform
;
9768 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9769 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9771 /** emit endif merge block */
9772 if (!ctx
->cf_info
.has_branch
) {
9773 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9774 append_logical_start(ctx
->block
);
9778 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9780 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9781 Builder
bld(ctx
->program
, ctx
->block
);
9782 aco_ptr
<Pseudo_branch_instruction
> branch
;
9785 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9787 * Uniform conditionals are represented in the following way*) :
9789 * The linear and logical CFG:
9792 * BB_THEN (logical) BB_ELSE (logical)
9796 * *) Exceptions may be due to break and continue statements within loops
9797 * If a break/continue happens within uniform control flow, it branches
9798 * to the loop exit/entry block. Otherwise, it branches to the next
9802 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9803 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9804 cond
= bool_to_scalar_condition(ctx
, cond
);
9806 begin_uniform_if_then(ctx
, &ic
, cond
);
9807 visit_cf_list(ctx
, &if_stmt
->then_list
);
9809 begin_uniform_if_else(ctx
, &ic
);
9810 visit_cf_list(ctx
, &if_stmt
->else_list
);
9812 end_uniform_if(ctx
, &ic
);
9814 return !ctx
->cf_info
.has_branch
;
9815 } else { /* non-uniform condition */
9817 * To maintain a logical and linear CFG without critical edges,
9818 * non-uniform conditionals are represented in the following way*) :
9823 * BB_THEN (logical) BB_THEN (linear)
9825 * BB_INVERT (linear)
9827 * BB_ELSE (logical) BB_ELSE (linear)
9834 * BB_THEN (logical) BB_ELSE (logical)
9838 * *) Exceptions may be due to break and continue statements within loops
9841 begin_divergent_if_then(ctx
, &ic
, cond
);
9842 visit_cf_list(ctx
, &if_stmt
->then_list
);
9844 begin_divergent_if_else(ctx
, &ic
);
9845 visit_cf_list(ctx
, &if_stmt
->else_list
);
9847 end_divergent_if(ctx
, &ic
);
9853 static bool visit_cf_list(isel_context
*ctx
,
9854 struct exec_list
*list
)
9856 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9857 switch (node
->type
) {
9858 case nir_cf_node_block
:
9859 visit_block(ctx
, nir_cf_node_as_block(node
));
9861 case nir_cf_node_if
:
9862 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9865 case nir_cf_node_loop
:
9866 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9869 unreachable("unimplemented cf list type");
9875 static void create_null_export(isel_context
*ctx
)
9877 /* Some shader stages always need to have exports.
9878 * So when there is none, we need to add a null export.
9881 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9882 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9883 Builder
bld(ctx
->program
, ctx
->block
);
9884 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9885 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9888 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9890 assert(ctx
->stage
== vertex_vs
||
9891 ctx
->stage
== tess_eval_vs
||
9892 ctx
->stage
== gs_copy_vs
||
9893 ctx
->stage
== ngg_vertex_gs
||
9894 ctx
->stage
== ngg_tess_eval_gs
);
9896 int offset
= (ctx
->stage
& sw_tes
)
9897 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9898 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9899 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9900 if (!is_pos
&& !mask
)
9902 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9904 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9905 exp
->enabled_mask
= mask
;
9906 for (unsigned i
= 0; i
< 4; ++i
) {
9907 if (mask
& (1 << i
))
9908 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9910 exp
->operands
[i
] = Operand(v1
);
9912 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9913 * Setting valid_mask=1 prevents it and has no other effect.
9915 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9917 exp
->compressed
= false;
9919 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9921 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9922 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9927 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9929 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9930 exp
->enabled_mask
= 0;
9931 for (unsigned i
= 0; i
< 4; ++i
)
9932 exp
->operands
[i
] = Operand(v1
);
9933 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9934 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9935 exp
->enabled_mask
|= 0x1;
9937 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9938 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9939 exp
->enabled_mask
|= 0x4;
9941 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9942 if (ctx
->options
->chip_class
< GFX9
) {
9943 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9944 exp
->enabled_mask
|= 0x8;
9946 Builder
bld(ctx
->program
, ctx
->block
);
9948 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9949 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9950 if (exp
->operands
[2].isTemp())
9951 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9953 exp
->operands
[2] = Operand(out
);
9954 exp
->enabled_mask
|= 0x4;
9957 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9959 exp
->compressed
= false;
9960 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9961 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9964 static void create_export_phis(isel_context
*ctx
)
9966 /* Used when exports are needed, but the output temps are defined in a preceding block.
9967 * This function will set up phis in order to access the outputs in the next block.
9970 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9971 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9972 ctx
->block
->instructions
.pop_back();
9974 Builder
bld(ctx
->program
, ctx
->block
);
9976 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9977 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9978 for (unsigned i
= 0; i
< 4; ++i
) {
9979 if (!(mask
& (1 << i
)))
9982 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9983 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9984 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9988 bld
.insert(std::move(logical_start
));
9991 static void create_vs_exports(isel_context
*ctx
)
9993 assert(ctx
->stage
== vertex_vs
||
9994 ctx
->stage
== tess_eval_vs
||
9995 ctx
->stage
== gs_copy_vs
||
9996 ctx
->stage
== ngg_vertex_gs
||
9997 ctx
->stage
== ngg_tess_eval_gs
);
9999 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
10000 ? &ctx
->program
->info
->tes
.outinfo
10001 : &ctx
->program
->info
->vs
.outinfo
;
10003 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
10004 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10005 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
10008 if (ctx
->options
->key
.has_multiview_view_index
) {
10009 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
10010 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
10013 /* the order these position exports are created is important */
10015 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
10016 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
10017 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
10018 exported_pos
= true;
10020 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10021 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
10022 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10023 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
10025 if (ctx
->export_clip_dists
) {
10026 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10027 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
10028 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10029 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
10032 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10033 if (i
< VARYING_SLOT_VAR0
&&
10034 i
!= VARYING_SLOT_LAYER
&&
10035 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
10036 i
!= VARYING_SLOT_VIEWPORT
)
10039 export_vs_varying(ctx
, i
, false, NULL
);
10043 create_null_export(ctx
);
10046 static bool export_fs_mrt_z(isel_context
*ctx
)
10048 Builder
bld(ctx
->program
, ctx
->block
);
10049 unsigned enabled_channels
= 0;
10050 bool compr
= false;
10053 for (unsigned i
= 0; i
< 4; ++i
) {
10054 values
[i
] = Operand(v1
);
10057 /* Both stencil and sample mask only need 16-bits. */
10058 if (!ctx
->program
->info
->ps
.writes_z
&&
10059 (ctx
->program
->info
->ps
.writes_stencil
||
10060 ctx
->program
->info
->ps
.writes_sample_mask
)) {
10061 compr
= true; /* COMPR flag */
10063 if (ctx
->program
->info
->ps
.writes_stencil
) {
10064 /* Stencil should be in X[23:16]. */
10065 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10066 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
10067 enabled_channels
|= 0x3;
10070 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10071 /* SampleMask should be in Y[15:0]. */
10072 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10073 enabled_channels
|= 0xc;
10076 if (ctx
->program
->info
->ps
.writes_z
) {
10077 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
10078 enabled_channels
|= 0x1;
10081 if (ctx
->program
->info
->ps
.writes_stencil
) {
10082 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10083 enabled_channels
|= 0x2;
10086 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10087 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10088 enabled_channels
|= 0x4;
10092 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
10093 * writemask component.
10095 if (ctx
->options
->chip_class
== GFX6
&&
10096 ctx
->options
->family
!= CHIP_OLAND
&&
10097 ctx
->options
->family
!= CHIP_HAINAN
) {
10098 enabled_channels
|= 0x1;
10101 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10102 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
10107 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
10109 Builder
bld(ctx
->program
, ctx
->block
);
10110 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10113 for (unsigned i
= 0; i
< 4; ++i
) {
10114 if (write_mask
& (1 << i
)) {
10115 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10117 values
[i
] = Operand(v1
);
10121 unsigned target
, col_format
;
10122 unsigned enabled_channels
= 0;
10123 aco_opcode compr_op
= (aco_opcode
)0;
10125 slot
-= FRAG_RESULT_DATA0
;
10126 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10127 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10129 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10130 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10132 switch (col_format
)
10134 case V_028714_SPI_SHADER_ZERO
:
10135 enabled_channels
= 0; /* writemask */
10136 target
= V_008DFC_SQ_EXP_NULL
;
10139 case V_028714_SPI_SHADER_32_R
:
10140 enabled_channels
= 1;
10143 case V_028714_SPI_SHADER_32_GR
:
10144 enabled_channels
= 0x3;
10147 case V_028714_SPI_SHADER_32_AR
:
10148 if (ctx
->options
->chip_class
>= GFX10
) {
10149 /* Special case: on GFX10, the outputs are different for 32_AR */
10150 enabled_channels
= 0x3;
10151 values
[1] = values
[3];
10152 values
[3] = Operand(v1
);
10154 enabled_channels
= 0x9;
10158 case V_028714_SPI_SHADER_FP16_ABGR
:
10159 enabled_channels
= 0x5;
10160 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10163 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10164 enabled_channels
= 0x5;
10165 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10168 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10169 enabled_channels
= 0x5;
10170 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10173 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10174 enabled_channels
= 0x5;
10175 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10176 if (is_int8
|| is_int10
) {
10178 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10179 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10181 for (unsigned i
= 0; i
< 4; i
++) {
10182 if ((write_mask
>> i
) & 1) {
10183 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10184 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10192 case V_028714_SPI_SHADER_SINT16_ABGR
:
10193 enabled_channels
= 0x5;
10194 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10195 if (is_int8
|| is_int10
) {
10197 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10198 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10199 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10200 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10202 for (unsigned i
= 0; i
< 4; i
++) {
10203 if ((write_mask
>> i
) & 1) {
10204 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10205 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10207 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10208 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10215 case V_028714_SPI_SHADER_32_ABGR
:
10216 enabled_channels
= 0xF;
10223 if (target
== V_008DFC_SQ_EXP_NULL
)
10226 if ((bool) compr_op
) {
10227 for (int i
= 0; i
< 2; i
++) {
10228 /* check if at least one of the values to be compressed is enabled */
10229 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10231 enabled_channels
|= enabled
<< (i
*2);
10232 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10233 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10234 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10236 values
[i
] = Operand(v1
);
10239 values
[2] = Operand(v1
);
10240 values
[3] = Operand(v1
);
10242 for (int i
= 0; i
< 4; i
++)
10243 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10246 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10247 enabled_channels
, target
, (bool) compr_op
);
10251 static void create_fs_exports(isel_context
*ctx
)
10253 bool exported
= false;
10255 /* Export depth, stencil and sample mask. */
10256 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10257 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10258 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10259 exported
|= export_fs_mrt_z(ctx
);
10261 /* Export all color render targets. */
10262 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10263 if (ctx
->outputs
.mask
[i
])
10264 exported
|= export_fs_mrt_color(ctx
, i
);
10267 create_null_export(ctx
);
10270 static void write_tcs_tess_factors(isel_context
*ctx
)
10272 unsigned outer_comps
;
10273 unsigned inner_comps
;
10275 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10292 Builder
bld(ctx
->program
, ctx
->block
);
10294 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10295 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10296 bld
.sopp(aco_opcode::s_barrier
);
10298 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10299 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10301 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10302 if_context ic_invocation_id_is_zero
;
10303 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10304 bld
.reset(ctx
->block
);
10306 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10308 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10309 unsigned stride
= inner_comps
+ outer_comps
;
10310 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10314 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10316 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10318 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10319 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10320 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10322 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10323 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10325 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10326 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10327 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10328 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10331 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10332 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10333 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10334 unsigned tf_const_offset
= 0;
10336 if (ctx
->program
->chip_class
<= GFX8
) {
10337 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10338 if_context ic_rel_patch_id_is_zero
;
10339 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10340 bld
.reset(ctx
->block
);
10342 /* Store the dynamic HS control word. */
10343 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10344 bld
.mubuf(aco_opcode::buffer_store_dword
,
10345 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10346 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10347 /* disable_wqm */ false, /* glc */ true);
10348 tf_const_offset
+= 4;
10350 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10351 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10352 bld
.reset(ctx
->block
);
10355 assert(stride
== 2 || stride
== 4 || stride
== 6);
10356 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10357 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10359 /* Store to offchip for TES to read - only if TES reads them */
10360 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10361 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10362 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10364 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10365 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10367 if (likely(inner_comps
)) {
10368 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10369 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10373 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10374 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10377 static void emit_stream_output(isel_context
*ctx
,
10378 Temp
const *so_buffers
,
10379 Temp
const *so_write_offset
,
10380 const struct radv_stream_output
*output
)
10382 unsigned num_comps
= util_bitcount(output
->component_mask
);
10383 unsigned writemask
= (1 << num_comps
) - 1;
10384 unsigned loc
= output
->location
;
10385 unsigned buf
= output
->buffer
;
10387 assert(num_comps
&& num_comps
<= 4);
10388 if (!num_comps
|| num_comps
> 4)
10391 unsigned start
= ffs(output
->component_mask
) - 1;
10394 bool all_undef
= true;
10395 assert(ctx
->stage
& hw_vs
);
10396 for (unsigned i
= 0; i
< num_comps
; i
++) {
10397 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10398 all_undef
= all_undef
&& !out
[i
].id();
10403 while (writemask
) {
10405 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10406 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10407 /* GFX6 doesn't support storing vec3, split it. */
10408 writemask
|= 1u << (start
+ 2);
10412 unsigned offset
= output
->offset
+ start
* 4;
10414 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10415 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10416 for (int i
= 0; i
< count
; ++i
)
10417 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10418 vec
->definitions
[0] = Definition(write_data
);
10419 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10424 opcode
= aco_opcode::buffer_store_dword
;
10427 opcode
= aco_opcode::buffer_store_dwordx2
;
10430 opcode
= aco_opcode::buffer_store_dwordx3
;
10433 opcode
= aco_opcode::buffer_store_dwordx4
;
10436 unreachable("Unsupported dword count.");
10439 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10440 store
->operands
[0] = Operand(so_buffers
[buf
]);
10441 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10442 store
->operands
[2] = Operand((uint32_t) 0);
10443 store
->operands
[3] = Operand(write_data
);
10444 if (offset
> 4095) {
10445 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10446 Builder
bld(ctx
->program
, ctx
->block
);
10447 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10449 store
->offset
= offset
;
10451 store
->offen
= true;
10453 store
->dlc
= false;
10455 store
->can_reorder
= true;
10456 ctx
->block
->instructions
.emplace_back(std::move(store
));
10460 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10462 Builder
bld(ctx
->program
, ctx
->block
);
10464 Temp so_buffers
[4];
10465 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10466 for (unsigned i
= 0; i
< 4; i
++) {
10467 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10471 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10472 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10475 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10476 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10478 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10480 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10483 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10485 bld
.reset(ctx
->block
);
10487 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10489 Temp so_write_offset
[4];
10491 for (unsigned i
= 0; i
< 4; i
++) {
10492 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10497 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10498 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10499 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10500 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10502 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10504 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10505 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10506 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10507 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10511 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10512 struct radv_stream_output
*output
=
10513 &ctx
->program
->info
->so
.outputs
[i
];
10514 if (stream
!= output
->stream
)
10517 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10520 begin_divergent_if_else(ctx
, &ic
);
10521 end_divergent_if(ctx
, &ic
);
10524 } /* end namespace */
10526 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10528 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10529 Builder
bld(ctx
->program
, ctx
->block
);
10530 constexpr unsigned hs_idx
= 1u;
10531 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10532 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10533 Operand((8u << 16) | (hs_idx
* 8u)));
10534 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10536 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10538 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10539 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10540 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10541 ls_has_nonzero_hs_threads
);
10542 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10543 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10544 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10545 ls_has_nonzero_hs_threads
);
10546 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10547 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10548 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10549 ls_has_nonzero_hs_threads
);
10551 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10552 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10553 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10556 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10558 /* Split all arguments except for the first (ring_offsets) and the last
10559 * (exec) so that the dead channels don't stay live throughout the program.
10561 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10562 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10563 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10564 startpgm
->definitions
[i
].regClass().size());
10569 void handle_bc_optimize(isel_context
*ctx
)
10571 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10572 Builder
bld(ctx
->program
, ctx
->block
);
10573 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10574 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10575 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10576 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10577 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10578 if (uses_center
&& uses_centroid
) {
10579 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10580 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10582 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10584 for (unsigned i
= 0; i
< 2; i
++) {
10585 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10586 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10587 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10588 persp_centroid
, persp_center
, sel
);
10590 ctx
->persp_centroid
= bld
.tmp(v2
);
10591 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10592 Operand(new_coord
[0]), Operand(new_coord
[1]));
10593 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10596 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10598 for (unsigned i
= 0; i
< 2; i
++) {
10599 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10600 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10601 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10602 linear_centroid
, linear_center
, sel
);
10604 ctx
->linear_centroid
= bld
.tmp(v2
);
10605 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10606 Operand(new_coord
[0]), Operand(new_coord
[1]));
10607 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10612 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10614 Program
*program
= ctx
->program
;
10616 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10618 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10619 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10620 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10621 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10622 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10624 program
->next_fp_mode
.must_flush_denorms32
=
10625 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10626 program
->next_fp_mode
.must_flush_denorms16_64
=
10627 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10628 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10630 program
->next_fp_mode
.care_about_round32
=
10631 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10633 program
->next_fp_mode
.care_about_round16_64
=
10634 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10635 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10637 /* default to preserving fp16 and fp64 denorms, since it's free */
10638 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10639 program
->next_fp_mode
.denorm16_64
= 0;
10641 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10643 /* preserving fp32 denorms is expensive, so only do it if asked */
10644 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10645 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10647 program
->next_fp_mode
.denorm32
= 0;
10649 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10650 program
->next_fp_mode
.round32
= fp_round_tz
;
10652 program
->next_fp_mode
.round32
= fp_round_ne
;
10654 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10655 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10657 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10659 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10662 void cleanup_cfg(Program
*program
)
10664 /* create linear_succs/logical_succs */
10665 for (Block
& BB
: program
->blocks
) {
10666 for (unsigned idx
: BB
.linear_preds
)
10667 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10668 for (unsigned idx
: BB
.logical_preds
)
10669 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10673 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10675 Builder
bld(ctx
->program
, ctx
->block
);
10677 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10678 Temp count
= i
== 0
10679 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10680 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10681 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10683 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10686 if (ctx
->program
->wave_size
== 64) {
10687 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10688 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10689 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10691 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10692 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10698 bool ngg_early_prim_export(isel_context
*ctx
)
10700 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10704 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10706 Builder
bld(ctx
->program
, ctx
->block
);
10708 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10709 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10711 /* Get the id of the current wave within the threadgroup (workgroup) */
10712 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10713 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10715 /* Execute the following code only on the first wave (wave id 0),
10716 * use the SCC def to tell if the wave id is zero or not.
10718 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10720 begin_uniform_if_then(ctx
, &ic
, cond
);
10721 begin_uniform_if_else(ctx
, &ic
);
10722 bld
.reset(ctx
->block
);
10724 /* Number of vertices output by VS/TES */
10725 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10726 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10727 /* Number of primitives output by VS/TES */
10728 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10729 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10731 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10732 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10733 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10735 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10736 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10738 end_uniform_if(ctx
, &ic
);
10740 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10741 bld
.reset(ctx
->block
);
10742 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10745 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10747 Builder
bld(ctx
->program
, ctx
->block
);
10749 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10750 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10753 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10756 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10757 assert(vtxindex
[i
].id());
10760 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10764 /* The initial edge flag is always false in tess eval shaders. */
10765 if (ctx
->stage
== ngg_vertex_gs
) {
10766 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10767 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10771 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10776 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10778 Builder
bld(ctx
->program
, ctx
->block
);
10779 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10781 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10782 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10783 false /* compressed */, true/* done */, false /* valid mask */);
10786 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10788 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10789 * These must always come before VS exports.
10791 * It is recommended to do these as early as possible. They can be at the beginning when
10792 * there is no SW GS and the shader doesn't write edge flags.
10796 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10797 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10799 Builder
bld(ctx
->program
, ctx
->block
);
10800 constexpr unsigned max_vertices_per_primitive
= 3;
10801 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10803 if (ctx
->stage
== ngg_vertex_gs
) {
10804 /* TODO: optimize for points & lines */
10805 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10806 if (ctx
->shader
->info
.tess
.point_mode
)
10807 num_vertices_per_primitive
= 1;
10808 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10809 num_vertices_per_primitive
= 2;
10811 unreachable("Unsupported NGG shader stage");
10814 Temp vtxindex
[max_vertices_per_primitive
];
10815 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10816 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10817 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10818 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10819 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10820 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10821 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10822 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10824 /* Export primitive data to the index buffer. */
10825 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10827 /* Export primitive ID. */
10828 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10829 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10830 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10831 Temp provoking_vtx_index
= vtxindex
[0];
10832 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10834 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10837 begin_divergent_if_else(ctx
, &ic
);
10838 end_divergent_if(ctx
, &ic
);
10841 void ngg_emit_nogs_output(isel_context
*ctx
)
10843 /* Emits NGG GS output, for stages that don't have SW GS. */
10846 Builder
bld(ctx
->program
, ctx
->block
);
10847 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10849 /* NGG streamout is currently disabled by default. */
10850 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10852 if (late_prim_export
) {
10853 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10854 create_export_phis(ctx
);
10855 /* Do what we need to do in the GS threads. */
10856 ngg_emit_nogs_gsthreads(ctx
);
10858 /* What comes next should be executed on ES threads. */
10859 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10860 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10861 bld
.reset(ctx
->block
);
10864 /* Export VS outputs */
10865 ctx
->block
->kind
|= block_kind_export_end
;
10866 create_vs_exports(ctx
);
10868 /* Export primitive ID */
10869 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10872 if (ctx
->stage
== ngg_vertex_gs
) {
10873 /* Wait for GS threads to store primitive ID in LDS. */
10874 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10875 bld
.sopp(aco_opcode::s_barrier
);
10877 /* Calculate LDS address where the GS threads stored the primitive ID. */
10878 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10879 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10880 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10881 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10882 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10883 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10885 /* Load primitive ID from LDS. */
10886 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10887 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10888 /* TES: Just use the patch ID as the primitive ID. */
10889 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10891 unreachable("unsupported NGG shader stage.");
10894 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10895 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10897 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10900 if (late_prim_export
) {
10901 begin_divergent_if_else(ctx
, &ic
);
10902 end_divergent_if(ctx
, &ic
);
10903 bld
.reset(ctx
->block
);
10907 void select_program(Program
*program
,
10908 unsigned shader_count
,
10909 struct nir_shader
*const *shaders
,
10910 ac_shader_config
* config
,
10911 struct radv_shader_args
*args
)
10913 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10914 if_context ic_merged_wave_info
;
10915 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10917 for (unsigned i
= 0; i
< shader_count
; i
++) {
10918 nir_shader
*nir
= shaders
[i
];
10919 init_context(&ctx
, nir
);
10921 setup_fp_mode(&ctx
, nir
);
10924 /* needs to be after init_context() for FS */
10925 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10926 append_logical_start(ctx
.block
);
10928 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10929 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10931 split_arguments(&ctx
, startpgm
);
10935 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10937 if (ngg_early_prim_export(&ctx
))
10938 ngg_emit_nogs_gsthreads(&ctx
);
10941 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10942 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10943 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10944 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10945 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10946 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10947 ctx
.stage
== tess_eval_geometry_gs
));
10949 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10950 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10951 if (check_merged_wave_info
) {
10952 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10953 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10957 Builder
bld(ctx
.program
, ctx
.block
);
10959 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10960 bld
.sopp(aco_opcode::s_barrier
);
10962 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10963 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10965 } else if (ctx
.stage
== geometry_gs
)
10966 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10968 if (ctx
.stage
== fragment_fs
)
10969 handle_bc_optimize(&ctx
);
10971 visit_cf_list(&ctx
, &func
->body
);
10973 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10974 emit_streamout(&ctx
, 0);
10976 if (ctx
.stage
& hw_vs
) {
10977 create_vs_exports(&ctx
);
10978 ctx
.block
->kind
|= block_kind_export_end
;
10979 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10980 ngg_emit_nogs_output(&ctx
);
10981 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10982 Builder
bld(ctx
.program
, ctx
.block
);
10983 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10984 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10985 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10986 write_tcs_tess_factors(&ctx
);
10989 if (ctx
.stage
== fragment_fs
) {
10990 create_fs_exports(&ctx
);
10991 ctx
.block
->kind
|= block_kind_export_end
;
10994 if (endif_merged_wave_info
) {
10995 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10996 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10999 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
11000 ngg_emit_nogs_output(&ctx
);
11002 ralloc_free(ctx
.divergent_vals
);
11004 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
11005 /* Outputs of the previous stage are inputs to the next stage */
11006 ctx
.inputs
= ctx
.outputs
;
11007 ctx
.outputs
= shader_io_state();
11011 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11013 append_logical_end(ctx
.block
);
11014 ctx
.block
->kind
|= block_kind_uniform
;
11015 Builder
bld(ctx
.program
, ctx
.block
);
11016 if (ctx
.program
->wb_smem_l1_on_end
)
11017 bld
.smem(aco_opcode::s_dcache_wb
, false);
11018 bld
.sopp(aco_opcode::s_endpgm
);
11020 cleanup_cfg(program
);
11023 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
11024 ac_shader_config
* config
,
11025 struct radv_shader_args
*args
)
11027 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
11029 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
11030 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
11031 program
->next_fp_mode
.must_flush_denorms32
= false;
11032 program
->next_fp_mode
.must_flush_denorms16_64
= false;
11033 program
->next_fp_mode
.care_about_round32
= false;
11034 program
->next_fp_mode
.care_about_round16_64
= false;
11035 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
11036 program
->next_fp_mode
.denorm32
= 0;
11037 program
->next_fp_mode
.round32
= fp_round_ne
;
11038 program
->next_fp_mode
.round16_64
= fp_round_ne
;
11039 ctx
.block
->fp_mode
= program
->next_fp_mode
;
11041 add_startpgm(&ctx
);
11042 append_logical_start(ctx
.block
);
11044 Builder
bld(ctx
.program
, ctx
.block
);
11046 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
11048 Operand
stream_id(0u);
11049 if (args
->shader_info
->so
.num_outputs
)
11050 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
11051 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
11053 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
11055 std::stack
<Block
> endif_blocks
;
11057 for (unsigned stream
= 0; stream
< 4; stream
++) {
11058 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
11061 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
11062 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
11065 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
11067 unsigned BB_if_idx
= ctx
.block
->index
;
11068 Block BB_endif
= Block();
11069 if (!stream_id
.isConstant()) {
11071 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11072 append_logical_end(ctx
.block
);
11073 ctx
.block
->kind
|= block_kind_uniform
;
11074 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11076 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11078 ctx
.block
= ctx
.program
->create_and_insert_block();
11079 add_edge(BB_if_idx
, ctx
.block
);
11080 bld
.reset(ctx
.block
);
11081 append_logical_start(ctx
.block
);
11084 unsigned offset
= 0;
11085 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11086 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11089 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11090 unsigned length
= util_last_bit(output_usage_mask
);
11091 for (unsigned j
= 0; j
< length
; ++j
) {
11092 if (!(output_usage_mask
& (1 << j
)))
11095 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11096 Temp voffset
= vtx_offset
;
11097 if (const_offset
>= 4096u) {
11098 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11099 const_offset
%= 4096u;
11102 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11103 mubuf
->definitions
[0] = bld
.def(v1
);
11104 mubuf
->operands
[0] = Operand(gsvs_ring
);
11105 mubuf
->operands
[1] = Operand(voffset
);
11106 mubuf
->operands
[2] = Operand(0u);
11107 mubuf
->offen
= true;
11108 mubuf
->offset
= const_offset
;
11111 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11112 mubuf
->barrier
= barrier_none
;
11113 mubuf
->can_reorder
= true;
11115 ctx
.outputs
.mask
[i
] |= 1 << j
;
11116 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11118 bld
.insert(std::move(mubuf
));
11124 if (args
->shader_info
->so
.num_outputs
) {
11125 emit_streamout(&ctx
, stream
);
11126 bld
.reset(ctx
.block
);
11130 create_vs_exports(&ctx
);
11131 ctx
.block
->kind
|= block_kind_export_end
;
11134 if (!stream_id
.isConstant()) {
11135 append_logical_end(ctx
.block
);
11137 /* branch from then block to endif block */
11138 bld
.branch(aco_opcode::p_branch
);
11139 add_edge(ctx
.block
->index
, &BB_endif
);
11140 ctx
.block
->kind
|= block_kind_uniform
;
11142 /* emit else block */
11143 ctx
.block
= ctx
.program
->create_and_insert_block();
11144 add_edge(BB_if_idx
, ctx
.block
);
11145 bld
.reset(ctx
.block
);
11146 append_logical_start(ctx
.block
);
11148 endif_blocks
.push(std::move(BB_endif
));
11152 while (!endif_blocks
.empty()) {
11153 Block BB_endif
= std::move(endif_blocks
.top());
11154 endif_blocks
.pop();
11156 Block
*BB_else
= ctx
.block
;
11158 append_logical_end(BB_else
);
11159 /* branch from else block to endif block */
11160 bld
.branch(aco_opcode::p_branch
);
11161 add_edge(BB_else
->index
, &BB_endif
);
11162 BB_else
->kind
|= block_kind_uniform
;
11164 /** emit endif merge block */
11165 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11166 bld
.reset(ctx
.block
);
11167 append_logical_start(ctx
.block
);
11170 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11172 append_logical_end(ctx
.block
);
11173 ctx
.block
->kind
|= block_kind_uniform
;
11174 bld
.sopp(aco_opcode::s_endpgm
);
11176 cleanup_cfg(program
);