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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f16
:
630 op
= aco_opcode::v_cmp_gt_f16
;
632 case aco_opcode::v_cmp_ge_f16
:
633 op
= aco_opcode::v_cmp_le_f16
;
635 case aco_opcode::v_cmp_lt_i16
:
636 op
= aco_opcode::v_cmp_gt_i16
;
638 case aco_opcode::v_cmp_ge_i16
:
639 op
= aco_opcode::v_cmp_le_i16
;
641 case aco_opcode::v_cmp_lt_u16
:
642 op
= aco_opcode::v_cmp_gt_u16
;
644 case aco_opcode::v_cmp_ge_u16
:
645 op
= aco_opcode::v_cmp_le_u16
;
647 case aco_opcode::v_cmp_lt_f32
:
648 op
= aco_opcode::v_cmp_gt_f32
;
650 case aco_opcode::v_cmp_ge_f32
:
651 op
= aco_opcode::v_cmp_le_f32
;
653 case aco_opcode::v_cmp_lt_i32
:
654 op
= aco_opcode::v_cmp_gt_i32
;
656 case aco_opcode::v_cmp_ge_i32
:
657 op
= aco_opcode::v_cmp_le_i32
;
659 case aco_opcode::v_cmp_lt_u32
:
660 op
= aco_opcode::v_cmp_gt_u32
;
662 case aco_opcode::v_cmp_ge_u32
:
663 op
= aco_opcode::v_cmp_le_u32
;
665 case aco_opcode::v_cmp_lt_f64
:
666 op
= aco_opcode::v_cmp_gt_f64
;
668 case aco_opcode::v_cmp_ge_f64
:
669 op
= aco_opcode::v_cmp_le_f64
;
671 case aco_opcode::v_cmp_lt_i64
:
672 op
= aco_opcode::v_cmp_gt_i64
;
674 case aco_opcode::v_cmp_ge_i64
:
675 op
= aco_opcode::v_cmp_le_i64
;
677 case aco_opcode::v_cmp_lt_u64
:
678 op
= aco_opcode::v_cmp_gt_u64
;
680 case aco_opcode::v_cmp_ge_u64
:
681 op
= aco_opcode::v_cmp_le_u64
;
683 default: /* eq and ne are commutative */
690 src1
= as_vgpr(ctx
, src1
);
694 Builder
bld(ctx
->program
, ctx
->block
);
695 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
698 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
700 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
701 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
702 Builder
bld(ctx
->program
, ctx
->block
);
704 assert(dst
.regClass() == bld
.lm
);
705 assert(src0
.type() == RegType::sgpr
);
706 assert(src1
.type() == RegType::sgpr
);
707 assert(src0
.regClass() == src1
.regClass());
709 /* Emit the SALU comparison instruction */
710 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
711 /* Turn the result into a per-lane bool */
712 bool_to_vector_condition(ctx
, cmp
, dst
);
715 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
716 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
718 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
719 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
720 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
721 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
723 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
724 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
725 aco_opcode op
= use_valu
? v_op
: s_op
;
726 assert(op
!= aco_opcode::num_opcodes
);
727 assert(dst
.regClass() == ctx
->program
->lane_mask
);
730 emit_vopc_instruction(ctx
, instr
, op
, dst
);
732 emit_sopc_instruction(ctx
, instr
, op
, dst
);
735 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
737 Builder
bld(ctx
->program
, ctx
->block
);
738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
739 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
741 assert(dst
.regClass() == bld
.lm
);
742 assert(src0
.regClass() == bld
.lm
);
743 assert(src1
.regClass() == bld
.lm
);
745 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
748 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
750 Builder
bld(ctx
->program
, ctx
->block
);
751 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
752 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
753 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
755 assert(cond
.regClass() == bld
.lm
);
757 if (dst
.type() == RegType::vgpr
) {
758 aco_ptr
<Instruction
> bcsel
;
759 if (dst
.regClass() == v2b
) {
760 then
= as_vgpr(ctx
, then
);
761 els
= as_vgpr(ctx
, els
);
763 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
765 } else if (dst
.regClass() == v1
) {
766 then
= as_vgpr(ctx
, then
);
767 els
= as_vgpr(ctx
, els
);
769 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
770 } else if (dst
.regClass() == v2
) {
771 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
772 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
773 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
774 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
776 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
777 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
779 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
781 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
782 nir_print_instr(&instr
->instr
, stderr
);
783 fprintf(stderr
, "\n");
788 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
789 assert(dst
.regClass() == bld
.lm
);
790 assert(then
.regClass() == bld
.lm
);
791 assert(els
.regClass() == bld
.lm
);
794 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
795 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
796 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
797 assert(dst
.size() == then
.size());
798 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
799 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
801 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
802 nir_print_instr(&instr
->instr
, stderr
);
803 fprintf(stderr
, "\n");
808 /* divergent boolean bcsel
809 * this implements bcsel on bools: dst = s0 ? s1 : s2
810 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
811 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
813 if (cond
.id() != then
.id())
814 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
816 if (cond
.id() == els
.id())
817 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
819 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
820 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
823 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
824 aco_opcode op
, uint32_t undo
)
826 /* multiply by 16777216 to handle denormals */
827 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
828 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
829 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
830 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
831 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
833 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
835 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
838 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
840 if (ctx
->block
->fp_mode
.denorm32
== 0) {
841 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
845 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
848 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
850 if (ctx
->block
->fp_mode
.denorm32
== 0) {
851 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
855 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
858 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
860 if (ctx
->block
->fp_mode
.denorm32
== 0) {
861 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
865 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
868 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
870 if (ctx
->block
->fp_mode
.denorm32
== 0) {
871 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
875 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
878 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
880 if (ctx
->options
->chip_class
>= GFX7
)
881 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
883 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
884 /* TODO: create more efficient code! */
885 if (val
.type() == RegType::sgpr
)
886 val
= as_vgpr(ctx
, val
);
888 /* Split the input value. */
889 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
890 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
892 /* Extract the exponent and compute the unbiased value. */
893 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
895 /* Extract the fractional part. */
896 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
897 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
899 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
900 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
902 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
903 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
904 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
905 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
906 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
908 /* Get the sign bit. */
909 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
911 /* Decide the operation to apply depending on the unbiased exponent. */
912 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
913 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
914 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
915 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
916 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
917 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
919 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
922 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
924 if (ctx
->options
->chip_class
>= GFX7
)
925 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
927 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
928 Temp src0
= as_vgpr(ctx
, val
);
930 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
931 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
933 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
934 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
935 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
937 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
938 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
939 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
942 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
943 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
945 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
947 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
948 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
950 return add
->definitions
[0].getTemp();
953 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
955 if (!instr
->dest
.dest
.is_ssa
) {
956 fprintf(stderr
, "nir alu dst not in ssa: ");
957 nir_print_instr(&instr
->instr
, stderr
);
958 fprintf(stderr
, "\n");
961 Builder
bld(ctx
->program
, ctx
->block
);
962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
967 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
968 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
969 for (unsigned i
= 0; i
< num
; ++i
)
970 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
972 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
973 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
974 for (unsigned i
= 0; i
< num
; ++i
)
975 vec
->operands
[i
] = Operand
{elems
[i
]};
976 vec
->definitions
[0] = Definition(dst
);
977 ctx
->block
->instructions
.emplace_back(std::move(vec
));
978 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
980 // TODO: that is a bit suboptimal..
981 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
982 for (unsigned i
= 0; i
< num
- 1; ++i
)
983 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
984 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
985 for (unsigned i
= 0; i
< num
; ++i
) {
986 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
988 elems
[bit
/ 32] = elems
[i
];
990 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
991 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
992 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
996 bld
.copy(Definition(dst
), elems
[0]);
998 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1003 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1004 aco_ptr
<Instruction
> mov
;
1005 if (dst
.type() == RegType::sgpr
) {
1006 if (src
.type() == RegType::vgpr
)
1007 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1008 else if (src
.regClass() == s1
)
1009 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1010 else if (src
.regClass() == s2
)
1011 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1013 unreachable("wrong src register class for nir_op_imov");
1014 } else if (dst
.regClass() == v1
) {
1015 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1016 } else if (dst
.regClass() == v2
) {
1017 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1019 nir_print_instr(&instr
->instr
, stderr
);
1020 unreachable("Should have been lowered to scalar.");
1025 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1026 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1027 assert(src
.regClass() == bld
.lm
);
1028 assert(dst
.regClass() == bld
.lm
);
1029 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1030 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1031 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1032 } else if (dst
.regClass() == v1
) {
1033 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1034 } else if (dst
.type() == RegType::sgpr
) {
1035 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1036 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1039 nir_print_instr(&instr
->instr
, stderr
);
1040 fprintf(stderr
, "\n");
1045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1046 if (dst
.regClass() == v1
) {
1047 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1048 } else if (dst
.regClass() == s1
) {
1049 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1050 } else if (dst
.size() == 2) {
1051 Temp src0
= bld
.tmp(dst
.type(), 1);
1052 Temp src1
= bld
.tmp(dst
.type(), 1);
1053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1055 if (dst
.regClass() == s2
) {
1056 Temp carry
= bld
.tmp(s1
);
1057 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1058 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1059 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1061 Temp lower
= bld
.tmp(v1
);
1062 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1063 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1064 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1068 nir_print_instr(&instr
->instr
, stderr
);
1069 fprintf(stderr
, "\n");
1074 if (dst
.regClass() == s1
) {
1075 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1076 } else if (dst
.regClass() == v1
) {
1077 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1078 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1080 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1081 nir_print_instr(&instr
->instr
, stderr
);
1082 fprintf(stderr
, "\n");
1086 case nir_op_isign
: {
1087 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1088 if (dst
.regClass() == s1
) {
1089 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1090 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1091 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1092 } else if (dst
.regClass() == s2
) {
1093 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1095 if (ctx
->program
->chip_class
>= GFX8
)
1096 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1098 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1099 /* SCC gets zero-extended to 64 bit */
1100 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1101 } else if (dst
.regClass() == v1
) {
1102 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1103 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1104 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1105 } else if (dst
.regClass() == v2
) {
1106 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1107 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1108 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1109 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1110 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1111 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (dst
.regClass() == v1
) {
1145 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1146 } else if (dst
.regClass() == s1
) {
1147 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1149 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1150 nir_print_instr(&instr
->instr
, stderr
);
1151 fprintf(stderr
, "\n");
1156 if (dst
.regClass() == v1
) {
1157 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1158 } else if (dst
.regClass() == s1
) {
1159 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1169 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1170 } else if (dst
.regClass() == v1
) {
1171 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1172 } else if (dst
.regClass() == s1
) {
1173 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1174 } else if (dst
.regClass() == s2
) {
1175 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1177 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1178 nir_print_instr(&instr
->instr
, stderr
);
1179 fprintf(stderr
, "\n");
1184 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1185 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1186 } else if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1190 } else if (dst
.regClass() == s2
) {
1191 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1193 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1194 nir_print_instr(&instr
->instr
, stderr
);
1195 fprintf(stderr
, "\n");
1200 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1201 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1202 } else if (dst
.regClass() == v1
) {
1203 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1204 } else if (dst
.regClass() == s1
) {
1205 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1206 } else if (dst
.regClass() == s2
) {
1207 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1209 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1210 nir_print_instr(&instr
->instr
, stderr
);
1211 fprintf(stderr
, "\n");
1216 if (dst
.regClass() == v1
) {
1217 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1218 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1219 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1220 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1221 } else if (dst
.regClass() == v2
) {
1222 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1223 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1224 } else if (dst
.regClass() == s2
) {
1225 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1226 } else if (dst
.regClass() == s1
) {
1227 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1236 if (dst
.regClass() == v1
) {
1237 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1238 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1239 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1240 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1241 } else if (dst
.regClass() == v2
) {
1242 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1243 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1244 } else if (dst
.regClass() == s1
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1246 } else if (dst
.regClass() == s2
) {
1247 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1249 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1250 nir_print_instr(&instr
->instr
, stderr
);
1251 fprintf(stderr
, "\n");
1256 if (dst
.regClass() == v1
) {
1257 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1258 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1259 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1260 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1261 } else if (dst
.regClass() == v2
) {
1262 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1263 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1264 } else if (dst
.regClass() == s1
) {
1265 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1266 } else if (dst
.regClass() == s2
) {
1267 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1275 case nir_op_find_lsb
: {
1276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1277 if (src
.regClass() == s1
) {
1278 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1279 } else if (src
.regClass() == v1
) {
1280 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1281 } else if (src
.regClass() == s2
) {
1282 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1290 case nir_op_ufind_msb
:
1291 case nir_op_ifind_msb
: {
1292 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1293 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1294 aco_opcode op
= src
.regClass() == s2
?
1295 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1296 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1297 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1299 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1300 Operand(src
.size() * 32u - 1u), msb_rev
);
1301 Temp msb
= sub
.def(0).getTemp();
1302 Temp carry
= sub
.def(1).getTemp();
1304 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1305 } else if (src
.regClass() == v1
) {
1306 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1307 Temp msb_rev
= bld
.tmp(v1
);
1308 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1309 Temp msb
= bld
.tmp(v1
);
1310 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1311 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1313 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1314 nir_print_instr(&instr
->instr
, stderr
);
1315 fprintf(stderr
, "\n");
1319 case nir_op_bitfield_reverse
: {
1320 if (dst
.regClass() == s1
) {
1321 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1322 } else if (dst
.regClass() == v1
) {
1323 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1332 if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1337 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1338 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1339 if (dst
.regClass() == v1
) {
1340 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1344 assert(src0
.size() == 2 && src1
.size() == 2);
1345 Temp src00
= bld
.tmp(src0
.type(), 1);
1346 Temp src01
= bld
.tmp(dst
.type(), 1);
1347 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1348 Temp src10
= bld
.tmp(src1
.type(), 1);
1349 Temp src11
= bld
.tmp(dst
.type(), 1);
1350 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1352 if (dst
.regClass() == s2
) {
1353 Temp carry
= bld
.tmp(s1
);
1354 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1355 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1356 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1357 } else if (dst
.regClass() == v2
) {
1358 Temp dst0
= bld
.tmp(v1
);
1359 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1360 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1363 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1364 nir_print_instr(&instr
->instr
, stderr
);
1365 fprintf(stderr
, "\n");
1369 case nir_op_uadd_sat
: {
1370 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1371 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1372 if (dst
.regClass() == s1
) {
1373 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1374 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1376 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1377 } else if (dst
.regClass() == v1
) {
1378 if (ctx
->options
->chip_class
>= GFX9
) {
1379 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1380 add
->operands
[0] = Operand(src0
);
1381 add
->operands
[1] = Operand(src1
);
1382 add
->definitions
[0] = Definition(dst
);
1384 ctx
->block
->instructions
.emplace_back(std::move(add
));
1386 if (src1
.regClass() != v1
)
1387 std::swap(src0
, src1
);
1388 assert(src1
.regClass() == v1
);
1389 Temp tmp
= bld
.tmp(v1
);
1390 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1391 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1394 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1395 nir_print_instr(&instr
->instr
, stderr
);
1396 fprintf(stderr
, "\n");
1400 case nir_op_uadd_carry
: {
1401 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1402 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1403 if (dst
.regClass() == s1
) {
1404 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1407 if (dst
.regClass() == v1
) {
1408 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1409 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1413 Temp src00
= bld
.tmp(src0
.type(), 1);
1414 Temp src01
= bld
.tmp(dst
.type(), 1);
1415 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1416 Temp src10
= bld
.tmp(src1
.type(), 1);
1417 Temp src11
= bld
.tmp(dst
.type(), 1);
1418 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1419 if (dst
.regClass() == s2
) {
1420 Temp carry
= bld
.tmp(s1
);
1421 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1422 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1423 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1424 } else if (dst
.regClass() == v2
) {
1425 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1426 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1427 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1430 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1431 nir_print_instr(&instr
->instr
, stderr
);
1432 fprintf(stderr
, "\n");
1437 if (dst
.regClass() == s1
) {
1438 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == v1
) {
1445 bld
.vsub32(Definition(dst
), src0
, src1
);
1449 Temp src00
= bld
.tmp(src0
.type(), 1);
1450 Temp src01
= bld
.tmp(dst
.type(), 1);
1451 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1452 Temp src10
= bld
.tmp(src1
.type(), 1);
1453 Temp src11
= bld
.tmp(dst
.type(), 1);
1454 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1455 if (dst
.regClass() == s2
) {
1456 Temp carry
= bld
.tmp(s1
);
1457 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1458 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1459 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1460 } else if (dst
.regClass() == v2
) {
1461 Temp lower
= bld
.tmp(v1
);
1462 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1463 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1466 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1467 nir_print_instr(&instr
->instr
, stderr
);
1468 fprintf(stderr
, "\n");
1472 case nir_op_usub_borrow
: {
1473 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1474 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1475 if (dst
.regClass() == s1
) {
1476 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1478 } else if (dst
.regClass() == v1
) {
1479 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1480 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1484 Temp src00
= bld
.tmp(src0
.type(), 1);
1485 Temp src01
= bld
.tmp(dst
.type(), 1);
1486 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1487 Temp src10
= bld
.tmp(src1
.type(), 1);
1488 Temp src11
= bld
.tmp(dst
.type(), 1);
1489 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1490 if (dst
.regClass() == s2
) {
1491 Temp borrow
= bld
.tmp(s1
);
1492 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1493 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1495 } else if (dst
.regClass() == v2
) {
1496 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1497 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1498 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1499 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1501 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1502 nir_print_instr(&instr
->instr
, stderr
);
1503 fprintf(stderr
, "\n");
1508 if (dst
.regClass() == v1
) {
1509 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1510 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1511 } else if (dst
.regClass() == s1
) {
1512 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1515 nir_print_instr(&instr
->instr
, stderr
);
1516 fprintf(stderr
, "\n");
1520 case nir_op_umul_high
: {
1521 if (dst
.regClass() == v1
) {
1522 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1523 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1524 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1525 } else if (dst
.regClass() == s1
) {
1526 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1527 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1528 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1530 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1531 nir_print_instr(&instr
->instr
, stderr
);
1532 fprintf(stderr
, "\n");
1536 case nir_op_imul_high
: {
1537 if (dst
.regClass() == v1
) {
1538 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1539 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1540 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1541 } else if (dst
.regClass() == s1
) {
1542 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1543 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1544 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1546 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1547 nir_print_instr(&instr
->instr
, stderr
);
1548 fprintf(stderr
, "\n");
1553 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1554 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1555 if (dst
.regClass() == v2b
) {
1556 Temp tmp
= bld
.tmp(v1
);
1557 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1558 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1559 } else if (dst
.regClass() == v1
) {
1560 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1561 } else if (dst
.regClass() == v2
) {
1562 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1564 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1565 nir_print_instr(&instr
->instr
, stderr
);
1566 fprintf(stderr
, "\n");
1571 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1572 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1573 if (dst
.regClass() == v2b
) {
1574 Temp tmp
= bld
.tmp(v1
);
1575 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1576 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1577 } else if (dst
.regClass() == v1
) {
1578 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1579 } else if (dst
.regClass() == v2
) {
1580 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1582 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1583 nir_print_instr(&instr
->instr
, stderr
);
1584 fprintf(stderr
, "\n");
1589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1590 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1591 if (dst
.regClass() == v2b
) {
1592 Temp tmp
= bld
.tmp(v1
);
1593 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1594 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1596 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1597 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1598 } else if (dst
.regClass() == v1
) {
1599 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1600 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1602 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1603 } else if (dst
.regClass() == v2
) {
1604 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1606 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1609 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1610 nir_print_instr(&instr
->instr
, stderr
);
1611 fprintf(stderr
, "\n");
1616 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1617 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1618 if (dst
.regClass() == v2b
) {
1619 // TODO: check fp_mode.must_flush_denorms16_64
1620 Temp tmp
= bld
.tmp(v1
);
1621 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1622 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1623 } else if (dst
.regClass() == v1
) {
1624 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1625 } else if (dst
.regClass() == v2
) {
1626 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1627 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1628 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1630 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1634 nir_print_instr(&instr
->instr
, stderr
);
1635 fprintf(stderr
, "\n");
1640 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1641 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1642 if (dst
.regClass() == v2b
) {
1643 // TODO: check fp_mode.must_flush_denorms16_64
1644 Temp tmp
= bld
.tmp(v1
);
1645 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1647 } else if (dst
.regClass() == v1
) {
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1649 } else if (dst
.regClass() == v2
) {
1650 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1651 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1652 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1654 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1663 case nir_op_fmax3
: {
1664 if (dst
.regClass() == v2b
) {
1665 Temp tmp
= bld
.tmp(v1
);
1666 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1667 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1668 } else if (dst
.regClass() == v1
) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_fmin3
: {
1678 if (dst
.regClass() == v2b
) {
1679 Temp tmp
= bld
.tmp(v1
);
1680 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1681 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1682 } else if (dst
.regClass() == v1
) {
1683 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1686 nir_print_instr(&instr
->instr
, stderr
);
1687 fprintf(stderr
, "\n");
1691 case nir_op_fmed3
: {
1692 if (dst
.regClass() == v2b
) {
1693 Temp tmp
= bld
.tmp(v1
);
1694 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1695 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1696 } else if (dst
.regClass() == v1
) {
1697 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1700 nir_print_instr(&instr
->instr
, stderr
);
1701 fprintf(stderr
, "\n");
1705 case nir_op_umax3
: {
1706 if (dst
.size() == 1) {
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1710 nir_print_instr(&instr
->instr
, stderr
);
1711 fprintf(stderr
, "\n");
1715 case nir_op_umin3
: {
1716 if (dst
.size() == 1) {
1717 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1725 case nir_op_umed3
: {
1726 if (dst
.size() == 1) {
1727 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1729 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1730 nir_print_instr(&instr
->instr
, stderr
);
1731 fprintf(stderr
, "\n");
1735 case nir_op_imax3
: {
1736 if (dst
.size() == 1) {
1737 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1745 case nir_op_imin3
: {
1746 if (dst
.size() == 1) {
1747 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1749 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1750 nir_print_instr(&instr
->instr
, stderr
);
1751 fprintf(stderr
, "\n");
1755 case nir_op_imed3
: {
1756 if (dst
.size() == 1) {
1757 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1765 case nir_op_cube_face_coord
: {
1766 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1767 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1768 emit_extract_vector(ctx
, in
, 1, v1
),
1769 emit_extract_vector(ctx
, in
, 2, v1
) };
1770 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1771 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1772 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1773 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1774 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1775 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1776 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1779 case nir_op_cube_face_index
: {
1780 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1781 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1782 emit_extract_vector(ctx
, in
, 1, v1
),
1783 emit_extract_vector(ctx
, in
, 2, v1
) };
1784 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1787 case nir_op_bcsel
: {
1788 emit_bcsel(ctx
, instr
, dst
);
1792 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1793 if (dst
.regClass() == v2b
) {
1794 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1796 } else if (dst
.regClass() == v1
) {
1797 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1798 } else if (dst
.regClass() == v2
) {
1799 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1802 nir_print_instr(&instr
->instr
, stderr
);
1803 fprintf(stderr
, "\n");
1808 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1809 if (dst
.regClass() == v2b
) {
1810 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1811 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1812 } else if (dst
.regClass() == v1
) {
1813 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1814 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1815 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1816 } else if (dst
.regClass() == v2
) {
1817 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1818 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1819 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1820 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1821 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1822 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1831 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1832 if (dst
.regClass() == v2b
) {
1833 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1834 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1835 } else if (dst
.regClass() == v1
) {
1836 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1837 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1838 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1839 } else if (dst
.regClass() == v2
) {
1840 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1841 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1842 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1844 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1845 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1847 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1848 nir_print_instr(&instr
->instr
, stderr
);
1849 fprintf(stderr
, "\n");
1854 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1855 if (dst
.regClass() == v2b
) {
1856 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1857 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1858 } else if (dst
.regClass() == v1
) {
1859 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1860 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1861 // TODO: confirm that this holds under any circumstances
1862 } else if (dst
.regClass() == v2
) {
1863 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1864 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1867 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1868 nir_print_instr(&instr
->instr
, stderr
);
1869 fprintf(stderr
, "\n");
1873 case nir_op_flog2
: {
1874 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1875 if (dst
.regClass() == v2b
) {
1876 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1878 } else if (dst
.regClass() == v1
) {
1879 emit_log2(ctx
, bld
, Definition(dst
), src
);
1881 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1882 nir_print_instr(&instr
->instr
, stderr
);
1883 fprintf(stderr
, "\n");
1888 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1889 if (dst
.regClass() == v2b
) {
1890 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1892 } else if (dst
.regClass() == v1
) {
1893 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1894 } else if (dst
.regClass() == v2
) {
1895 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1898 nir_print_instr(&instr
->instr
, stderr
);
1899 fprintf(stderr
, "\n");
1903 case nir_op_fexp2
: {
1904 if (dst
.regClass() == v2b
) {
1905 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1906 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1907 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1908 } else if (dst
.regClass() == v1
) {
1909 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1911 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1912 nir_print_instr(&instr
->instr
, stderr
);
1913 fprintf(stderr
, "\n");
1917 case nir_op_fsqrt
: {
1918 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1919 if (dst
.regClass() == v2b
) {
1920 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1921 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1922 } else if (dst
.regClass() == v1
) {
1923 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1924 } else if (dst
.regClass() == v2
) {
1925 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1927 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1928 nir_print_instr(&instr
->instr
, stderr
);
1929 fprintf(stderr
, "\n");
1933 case nir_op_ffract
: {
1934 if (dst
.regClass() == v2b
) {
1935 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1936 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1940 } else if (dst
.regClass() == v2
) {
1941 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1943 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1944 nir_print_instr(&instr
->instr
, stderr
);
1945 fprintf(stderr
, "\n");
1949 case nir_op_ffloor
: {
1950 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1951 if (dst
.regClass() == v2b
) {
1952 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1953 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1954 } else if (dst
.regClass() == v1
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1956 } else if (dst
.regClass() == v2
) {
1957 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1960 nir_print_instr(&instr
->instr
, stderr
);
1961 fprintf(stderr
, "\n");
1965 case nir_op_fceil
: {
1966 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1967 if (dst
.regClass() == v2b
) {
1968 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
1969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1972 } else if (dst
.regClass() == v2
) {
1973 if (ctx
->options
->chip_class
>= GFX7
) {
1974 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1976 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1977 /* trunc = trunc(src0)
1978 * if (src0 > 0.0 && src0 != trunc)
1981 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1982 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1983 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1984 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1985 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1986 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1987 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1990 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1991 nir_print_instr(&instr
->instr
, stderr
);
1992 fprintf(stderr
, "\n");
1996 case nir_op_ftrunc
: {
1997 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1998 if (dst
.regClass() == v2b
) {
1999 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2000 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2001 } else if (dst
.regClass() == v1
) {
2002 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2003 } else if (dst
.regClass() == v2
) {
2004 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2006 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2007 nir_print_instr(&instr
->instr
, stderr
);
2008 fprintf(stderr
, "\n");
2012 case nir_op_fround_even
: {
2013 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2014 if (dst
.regClass() == v2b
) {
2015 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2016 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2017 } else if (dst
.regClass() == v1
) {
2018 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2019 } else if (dst
.regClass() == v2
) {
2020 if (ctx
->options
->chip_class
>= GFX7
) {
2021 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2023 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2024 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2027 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2028 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2029 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2030 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2031 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2032 tmp
= sub
->definitions
[0].getTemp();
2034 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2035 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2036 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2037 Temp cond
= vop3
->definitions
[0].getTemp();
2039 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2040 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2041 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2042 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2044 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2055 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2056 aco_ptr
<Instruction
> norm
;
2057 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2058 if (dst
.regClass() == v2b
) {
2059 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2060 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2061 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2063 } else if (dst
.regClass() == v1
) {
2064 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2066 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2067 if (ctx
->options
->chip_class
< GFX9
)
2068 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2070 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2071 bld
.vop1(opcode
, Definition(dst
), tmp
);
2073 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2074 nir_print_instr(&instr
->instr
, stderr
);
2075 fprintf(stderr
, "\n");
2079 case nir_op_ldexp
: {
2080 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2081 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2082 if (dst
.regClass() == v2b
) {
2083 Temp tmp
= bld
.tmp(v1
);
2084 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2085 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2086 } else if (dst
.regClass() == v1
) {
2087 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2088 } else if (dst
.regClass() == v2
) {
2089 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2091 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2092 nir_print_instr(&instr
->instr
, stderr
);
2093 fprintf(stderr
, "\n");
2097 case nir_op_frexp_sig
: {
2098 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2101 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2102 } else if (dst
.regClass() == v1
) {
2103 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2104 } else if (dst
.regClass() == v2
) {
2105 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2108 nir_print_instr(&instr
->instr
, stderr
);
2109 fprintf(stderr
, "\n");
2113 case nir_op_frexp_exp
: {
2114 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2115 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2116 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2117 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), tmp
, Operand(0u));
2118 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2119 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2120 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2121 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2124 nir_print_instr(&instr
->instr
, stderr
);
2125 fprintf(stderr
, "\n");
2129 case nir_op_fsign
: {
2130 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2131 if (dst
.regClass() == v2b
) {
2132 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2133 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2134 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2135 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2136 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2137 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2139 } else if (dst
.regClass() == v1
) {
2140 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2141 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2142 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2143 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2144 } else if (dst
.regClass() == v2
) {
2145 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2146 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2147 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2149 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2150 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2151 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2156 nir_print_instr(&instr
->instr
, stderr
);
2157 fprintf(stderr
, "\n");
2162 case nir_op_f2f16_rtne
: {
2163 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2164 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2165 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2166 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2167 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2170 case nir_op_f2f16_rtz
: {
2171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2172 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2173 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2174 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2175 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2178 case nir_op_f2f32
: {
2179 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2180 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2181 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2182 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2184 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2185 nir_print_instr(&instr
->instr
, stderr
);
2186 fprintf(stderr
, "\n");
2190 case nir_op_f2f64
: {
2191 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2192 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2193 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2194 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2197 case nir_op_i2f16
: {
2198 assert(dst
.regClass() == v2b
);
2199 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
),
2200 get_alu_src(ctx
, instr
->src
[0]));
2201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2204 case nir_op_i2f32
: {
2205 assert(dst
.size() == 1);
2206 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2209 case nir_op_i2f64
: {
2210 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2211 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2212 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2214 RegClass rc
= RegClass(src
.type(), 1);
2215 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2217 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2218 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2219 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2220 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2223 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2224 nir_print_instr(&instr
->instr
, stderr
);
2225 fprintf(stderr
, "\n");
2229 case nir_op_u2f16
: {
2230 assert(dst
.regClass() == v2b
);
2231 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
),
2232 get_alu_src(ctx
, instr
->src
[0]));
2233 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2236 case nir_op_u2f32
: {
2237 assert(dst
.size() == 1);
2238 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2241 case nir_op_u2f64
: {
2242 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2243 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2244 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2245 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2246 RegClass rc
= RegClass(src
.type(), 1);
2247 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2248 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2249 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2250 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2251 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2252 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2254 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2255 nir_print_instr(&instr
->instr
, stderr
);
2256 fprintf(stderr
, "\n");
2260 case nir_op_f2i16
: {
2261 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2262 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2263 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2264 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2265 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2267 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2269 if (dst
.type() == RegType::vgpr
)
2270 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2272 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2275 case nir_op_f2u16
: {
2276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2277 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2278 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2279 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2280 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2282 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2284 if (dst
.type() == RegType::vgpr
)
2285 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2287 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2290 case nir_op_f2i32
: {
2291 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2292 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2293 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2294 if (dst
.type() == RegType::vgpr
) {
2295 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2297 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2298 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2300 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2301 if (dst
.type() == RegType::vgpr
)
2302 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2304 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2305 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2308 if (dst
.type() == RegType::vgpr
)
2309 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2311 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2312 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2315 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2316 nir_print_instr(&instr
->instr
, stderr
);
2317 fprintf(stderr
, "\n");
2321 case nir_op_f2u32
: {
2322 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2323 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2324 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2325 if (dst
.type() == RegType::vgpr
) {
2326 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2328 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2329 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2331 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2332 if (dst
.type() == RegType::vgpr
)
2333 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2335 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2336 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2338 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2339 if (dst
.type() == RegType::vgpr
)
2340 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2343 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2346 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2347 nir_print_instr(&instr
->instr
, stderr
);
2348 fprintf(stderr
, "\n");
2352 case nir_op_f2i64
: {
2353 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2354 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2355 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2357 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2358 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2359 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2360 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2361 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2362 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2363 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2364 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2365 Temp new_exponent
= bld
.tmp(v1
);
2366 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2367 if (ctx
->program
->chip_class
>= GFX8
)
2368 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2370 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2371 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2372 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2373 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2374 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2375 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2376 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2377 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2378 Temp new_lower
= bld
.tmp(v1
);
2379 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2380 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2381 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2383 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2384 if (src
.type() == RegType::vgpr
)
2385 src
= bld
.as_uniform(src
);
2386 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2387 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2388 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2389 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2390 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2391 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2392 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2393 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2394 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2395 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2396 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2397 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2398 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2399 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2400 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2401 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2402 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2403 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2404 Temp borrow
= bld
.tmp(s1
);
2405 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2406 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2407 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2409 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2410 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2411 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2412 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2413 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2414 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2415 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2416 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2417 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2418 if (dst
.type() == RegType::sgpr
) {
2419 lower
= bld
.as_uniform(lower
);
2420 upper
= bld
.as_uniform(upper
);
2422 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2425 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2426 nir_print_instr(&instr
->instr
, stderr
);
2427 fprintf(stderr
, "\n");
2431 case nir_op_f2u64
: {
2432 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2433 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2434 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2436 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2437 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2438 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2439 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2440 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2441 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2442 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2443 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2444 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2445 Temp new_exponent
= bld
.tmp(v1
);
2446 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2447 if (ctx
->program
->chip_class
>= GFX8
)
2448 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2450 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2451 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2452 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2453 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2454 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2455 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2456 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2457 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2459 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2460 if (src
.type() == RegType::vgpr
)
2461 src
= bld
.as_uniform(src
);
2462 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2463 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2464 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2465 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2466 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2467 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2468 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2469 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2470 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2471 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2472 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2473 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2474 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2475 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2476 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2477 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2478 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2479 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2481 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2482 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2483 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2484 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2485 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2486 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2487 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2488 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2489 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2490 if (dst
.type() == RegType::sgpr
) {
2491 lower
= bld
.as_uniform(lower
);
2492 upper
= bld
.as_uniform(upper
);
2494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2497 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2498 nir_print_instr(&instr
->instr
, stderr
);
2499 fprintf(stderr
, "\n");
2503 case nir_op_b2f16
: {
2504 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2505 assert(src
.regClass() == bld
.lm
);
2507 if (dst
.regClass() == s1
) {
2508 src
= bool_to_scalar_condition(ctx
, src
);
2509 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2510 } else if (dst
.regClass() == v2b
) {
2511 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2512 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2513 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2515 unreachable("Wrong destination register class for nir_op_b2f16.");
2519 case nir_op_b2f32
: {
2520 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2521 assert(src
.regClass() == bld
.lm
);
2523 if (dst
.regClass() == s1
) {
2524 src
= bool_to_scalar_condition(ctx
, src
);
2525 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2526 } else if (dst
.regClass() == v1
) {
2527 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2529 unreachable("Wrong destination register class for nir_op_b2f32.");
2533 case nir_op_b2f64
: {
2534 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2535 assert(src
.regClass() == bld
.lm
);
2537 if (dst
.regClass() == s2
) {
2538 src
= bool_to_scalar_condition(ctx
, src
);
2539 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2540 } else if (dst
.regClass() == v2
) {
2541 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2542 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2543 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2545 unreachable("Wrong destination register class for nir_op_b2f64.");
2551 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2552 /* we can actually just say dst = src */
2553 if (src
.regClass() == s1
)
2554 bld
.copy(Definition(dst
), src
);
2556 emit_extract_vector(ctx
, src
, 0, dst
);
2559 case nir_op_i2i16
: {
2560 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2561 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2562 if (dst
.regClass() == s1
) {
2563 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2565 assert(src
.regClass() == v1b
);
2566 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2567 sdwa
->operands
[0] = Operand(src
);
2568 sdwa
->definitions
[0] = Definition(dst
);
2569 sdwa
->sel
[0] = sdwa_sbyte
;
2570 sdwa
->dst_sel
= sdwa_sword
;
2571 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2574 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2575 /* we can actually just say dst = src */
2576 if (src
.regClass() == s1
)
2577 bld
.copy(Definition(dst
), src
);
2579 emit_extract_vector(ctx
, src
, 0, dst
);
2583 case nir_op_u2u16
: {
2584 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2585 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2586 if (dst
.regClass() == s1
)
2587 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2589 assert(src
.regClass() == v1b
);
2590 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2591 sdwa
->operands
[0] = Operand(src
);
2592 sdwa
->definitions
[0] = Definition(dst
);
2593 sdwa
->sel
[0] = sdwa_ubyte
;
2594 sdwa
->dst_sel
= sdwa_uword
;
2595 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2598 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2599 /* we can actually just say dst = src */
2600 if (src
.regClass() == s1
)
2601 bld
.copy(Definition(dst
), src
);
2603 emit_extract_vector(ctx
, src
, 0, dst
);
2607 case nir_op_i2i32
: {
2608 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2609 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2610 if (dst
.regClass() == s1
) {
2611 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2613 assert(src
.regClass() == v1b
);
2614 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2615 sdwa
->operands
[0] = Operand(src
);
2616 sdwa
->definitions
[0] = Definition(dst
);
2617 sdwa
->sel
[0] = sdwa_sbyte
;
2618 sdwa
->dst_sel
= sdwa_sdword
;
2619 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2621 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2622 if (dst
.regClass() == s1
) {
2623 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2625 assert(src
.regClass() == v2b
);
2626 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2627 sdwa
->operands
[0] = Operand(src
);
2628 sdwa
->definitions
[0] = Definition(dst
);
2629 sdwa
->sel
[0] = sdwa_sword
;
2630 sdwa
->dst_sel
= sdwa_udword
;
2631 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2633 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2634 /* we can actually just say dst = src, as it would map the lower register */
2635 emit_extract_vector(ctx
, src
, 0, dst
);
2637 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2638 nir_print_instr(&instr
->instr
, stderr
);
2639 fprintf(stderr
, "\n");
2643 case nir_op_u2u32
: {
2644 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2645 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2646 if (dst
.regClass() == s1
)
2647 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2649 assert(src
.regClass() == v1b
);
2650 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2651 sdwa
->operands
[0] = Operand(src
);
2652 sdwa
->definitions
[0] = Definition(dst
);
2653 sdwa
->sel
[0] = sdwa_ubyte
;
2654 sdwa
->dst_sel
= sdwa_udword
;
2655 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2657 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2658 if (dst
.regClass() == s1
) {
2659 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2661 assert(src
.regClass() == v2b
);
2662 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2663 sdwa
->operands
[0] = Operand(src
);
2664 sdwa
->definitions
[0] = Definition(dst
);
2665 sdwa
->sel
[0] = sdwa_uword
;
2666 sdwa
->dst_sel
= sdwa_udword
;
2667 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2669 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2670 /* we can actually just say dst = src, as it would map the lower register */
2671 emit_extract_vector(ctx
, src
, 0, dst
);
2673 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2674 nir_print_instr(&instr
->instr
, stderr
);
2675 fprintf(stderr
, "\n");
2679 case nir_op_i2i64
: {
2680 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2681 if (src
.regClass() == s1
) {
2682 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2683 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2684 } else if (src
.regClass() == v1
) {
2685 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2686 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2688 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2689 nir_print_instr(&instr
->instr
, stderr
);
2690 fprintf(stderr
, "\n");
2694 case nir_op_u2u64
: {
2695 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2696 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2697 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2700 nir_print_instr(&instr
->instr
, stderr
);
2701 fprintf(stderr
, "\n");
2706 case nir_op_b2i32
: {
2707 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2708 assert(src
.regClass() == bld
.lm
);
2710 if (dst
.regClass() == s1
) {
2711 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2712 bool_to_scalar_condition(ctx
, src
, dst
);
2713 } else if (dst
.regClass() == v1
) {
2714 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2716 unreachable("Invalid register class for b2i32");
2722 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2723 assert(dst
.regClass() == bld
.lm
);
2725 if (src
.type() == RegType::vgpr
) {
2726 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2727 assert(dst
.regClass() == bld
.lm
);
2728 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2729 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2731 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2733 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2734 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2736 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2737 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2739 bool_to_vector_condition(ctx
, tmp
, dst
);
2743 case nir_op_pack_64_2x32_split
: {
2744 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2745 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2747 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2750 case nir_op_unpack_64_2x32_split_x
:
2751 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2753 case nir_op_unpack_64_2x32_split_y
:
2754 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2756 case nir_op_unpack_32_2x16_split_x
:
2757 if (dst
.type() == RegType::vgpr
) {
2758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2760 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2763 case nir_op_unpack_32_2x16_split_y
:
2764 if (dst
.type() == RegType::vgpr
) {
2765 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2767 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2770 case nir_op_pack_32_2x16_split
: {
2771 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2772 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2773 if (dst
.regClass() == v1
) {
2774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2776 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2777 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2778 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2782 case nir_op_pack_half_2x16
: {
2783 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2785 if (dst
.regClass() == v1
) {
2786 Temp src0
= bld
.tmp(v1
);
2787 Temp src1
= bld
.tmp(v1
);
2788 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2789 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2790 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2792 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2793 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2794 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2796 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2797 nir_print_instr(&instr
->instr
, stderr
);
2798 fprintf(stderr
, "\n");
2802 case nir_op_unpack_half_2x16_split_x
: {
2803 if (dst
.regClass() == v1
) {
2804 Builder
bld(ctx
->program
, ctx
->block
);
2805 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2807 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2808 nir_print_instr(&instr
->instr
, stderr
);
2809 fprintf(stderr
, "\n");
2813 case nir_op_unpack_half_2x16_split_y
: {
2814 if (dst
.regClass() == v1
) {
2815 Builder
bld(ctx
->program
, ctx
->block
);
2816 /* TODO: use SDWA here */
2817 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2818 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2820 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2821 nir_print_instr(&instr
->instr
, stderr
);
2822 fprintf(stderr
, "\n");
2826 case nir_op_fquantize2f16
: {
2827 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2828 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2831 if (ctx
->program
->chip_class
>= GFX8
) {
2832 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2833 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2834 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2836 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2837 * so compare the result and flush to 0 if it's smaller.
2839 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2840 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2841 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2842 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2843 cmp_res
= vop3
->definitions
[0].getTemp();
2846 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2847 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2848 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2850 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2855 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2856 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2858 if (dst
.regClass() == s1
) {
2859 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2860 } else if (dst
.regClass() == v1
) {
2861 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2863 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2864 nir_print_instr(&instr
->instr
, stderr
);
2865 fprintf(stderr
, "\n");
2869 case nir_op_bitfield_select
: {
2870 /* (mask & insert) | (~mask & base) */
2871 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2872 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2873 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2875 /* dst = (insert & bitmask) | (base & ~bitmask) */
2876 if (dst
.regClass() == s1
) {
2877 aco_ptr
<Instruction
> sop2
;
2878 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2879 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2881 if (const_insert
&& const_bitmask
) {
2882 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2884 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2885 lhs
= Operand(insert
);
2889 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2890 if (const_base
&& const_bitmask
) {
2891 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2893 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2894 rhs
= Operand(base
);
2897 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2899 } else if (dst
.regClass() == v1
) {
2900 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2901 base
= as_vgpr(ctx
, base
);
2902 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2903 insert
= as_vgpr(ctx
, insert
);
2905 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2909 nir_print_instr(&instr
->instr
, stderr
);
2910 fprintf(stderr
, "\n");
2916 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2917 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2918 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2920 if (dst
.type() == RegType::sgpr
) {
2922 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2923 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2924 if (const_offset
&& const_bits
) {
2925 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2926 extract
= Operand(const_extract
);
2930 width
= Operand(const_bits
->u32
<< 16);
2932 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2934 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2938 if (dst
.regClass() == s1
) {
2939 if (instr
->op
== nir_op_ubfe
)
2940 opcode
= aco_opcode::s_bfe_u32
;
2942 opcode
= aco_opcode::s_bfe_i32
;
2943 } else if (dst
.regClass() == s2
) {
2944 if (instr
->op
== nir_op_ubfe
)
2945 opcode
= aco_opcode::s_bfe_u64
;
2947 opcode
= aco_opcode::s_bfe_i64
;
2949 unreachable("Unsupported BFE bit size");
2952 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2956 if (dst
.regClass() == v1
) {
2957 if (instr
->op
== nir_op_ubfe
)
2958 opcode
= aco_opcode::v_bfe_u32
;
2960 opcode
= aco_opcode::v_bfe_i32
;
2962 unreachable("Unsupported BFE bit size");
2965 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2969 case nir_op_bit_count
: {
2970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2971 if (src
.regClass() == s1
) {
2972 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2973 } else if (src
.regClass() == v1
) {
2974 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2975 } else if (src
.regClass() == v2
) {
2976 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2977 emit_extract_vector(ctx
, src
, 1, v1
),
2978 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2979 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2980 } else if (src
.regClass() == s2
) {
2981 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2983 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2984 nir_print_instr(&instr
->instr
, stderr
);
2985 fprintf(stderr
, "\n");
2990 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2994 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2998 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
3002 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3006 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3010 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3014 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3015 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3017 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3018 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3022 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3023 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3025 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3026 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3030 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3034 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3039 case nir_op_fddx_fine
:
3040 case nir_op_fddy_fine
:
3041 case nir_op_fddx_coarse
:
3042 case nir_op_fddy_coarse
: {
3043 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3044 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3045 if (instr
->op
== nir_op_fddx_fine
) {
3046 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3047 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3048 } else if (instr
->op
== nir_op_fddy_fine
) {
3049 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3050 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3052 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3053 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3054 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3056 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3060 if (ctx
->program
->chip_class
>= GFX8
) {
3061 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3062 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3064 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3065 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3066 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3068 emit_wqm(ctx
, tmp
, dst
, true);
3072 fprintf(stderr
, "Unknown NIR ALU instr: ");
3073 nir_print_instr(&instr
->instr
, stderr
);
3074 fprintf(stderr
, "\n");
3078 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3080 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3082 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3083 // which get truncated the lsb if double and msb if int
3084 // for now, we only use s_mov_b64 with 64bit inline constants
3085 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3086 assert(dst
.type() == RegType::sgpr
);
3088 Builder
bld(ctx
->program
, ctx
->block
);
3090 if (instr
->def
.bit_size
== 1) {
3091 assert(dst
.regClass() == bld
.lm
);
3092 int val
= instr
->value
[0].b
? -1 : 0;
3093 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3094 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3095 } else if (instr
->def
.bit_size
== 8) {
3096 /* ensure that the value is correctly represented in the low byte of the register */
3097 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3098 } else if (instr
->def
.bit_size
== 16) {
3099 /* ensure that the value is correctly represented in the low half of the register */
3100 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3101 } else if (dst
.size() == 1) {
3102 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3104 assert(dst
.size() != 1);
3105 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3106 if (instr
->def
.bit_size
== 64)
3107 for (unsigned i
= 0; i
< dst
.size(); i
++)
3108 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3110 for (unsigned i
= 0; i
< dst
.size(); i
++)
3111 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3113 vec
->definitions
[0] = Definition(dst
);
3114 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3118 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3120 uint32_t new_mask
= 0;
3121 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3122 if (mask
& (1u << i
))
3123 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3127 Operand
load_lds_size_m0(isel_context
*ctx
)
3129 /* TODO: m0 does not need to be initialized on GFX9+ */
3130 Builder
bld(ctx
->program
, ctx
->block
);
3131 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3134 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3135 Temp address
, unsigned base_offset
, unsigned align
)
3137 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3139 Builder
bld(ctx
->program
, ctx
->block
);
3141 Operand m
= load_lds_size_m0(ctx
);
3143 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3144 unsigned bytes_read
= 0;
3145 unsigned result_size
= 0;
3146 unsigned total_bytes
= num_components
* elem_size_bytes
;
3147 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3148 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3149 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3151 while (bytes_read
< total_bytes
) {
3152 unsigned todo
= total_bytes
- bytes_read
;
3153 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3154 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3156 aco_opcode op
= aco_opcode::last_opcode
;
3158 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3159 op
= aco_opcode::ds_read_b128
;
3161 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3162 op
= aco_opcode::ds_read2_b64
;
3165 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3166 op
= aco_opcode::ds_read_b96
;
3168 } else if (todo
>= 8 && aligned8
) {
3169 op
= aco_opcode::ds_read_b64
;
3171 } else if (todo
>= 8 && usable_read2
) {
3172 op
= aco_opcode::ds_read2_b32
;
3175 } else if (todo
>= 4) {
3176 op
= aco_opcode::ds_read_b32
;
3181 assert(todo
% elem_size_bytes
== 0);
3182 unsigned num_elements
= todo
/ elem_size_bytes
;
3183 unsigned offset
= base_offset
+ bytes_read
;
3184 unsigned max_offset
= read2
? 1019 : 65535;
3186 Temp address_offset
= address
;
3187 if (offset
> max_offset
) {
3188 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3189 offset
= bytes_read
;
3191 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3194 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3197 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3200 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3202 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3204 if (num_components
== 1) {
3205 assert(todo
== total_bytes
);
3206 if (dst
.type() == RegType::sgpr
)
3207 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3211 if (dst
.type() == RegType::sgpr
) {
3212 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3213 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3217 if (num_elements
== 1) {
3218 result
[result_size
++] = res
;
3220 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3221 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3222 split
->operands
[0] = Operand(res
);
3223 for (unsigned i
= 0; i
< num_elements
; i
++)
3224 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3225 ctx
->block
->instructions
.emplace_back(std::move(split
));
3231 assert(result_size
== num_components
&& result_size
> 1);
3232 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3233 for (unsigned i
= 0; i
< result_size
; i
++)
3234 vec
->operands
[i
] = Operand(result
[i
]);
3235 vec
->definitions
[0] = Definition(dst
);
3236 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3237 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3242 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3244 if (start
== 0 && size
== data
.size())
3245 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3247 unsigned size_hint
= 1;
3248 auto it
= ctx
->allocated_vec
.find(data
.id());
3249 if (it
!= ctx
->allocated_vec
.end())
3250 size_hint
= it
->second
[0].size();
3251 if (size
% size_hint
|| start
% size_hint
)
3258 for (unsigned i
= 0; i
< size
; i
++)
3259 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3262 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3264 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3265 for (unsigned i
= 0; i
< size
; i
++)
3266 vec
->operands
[i
] = Operand(elems
[i
]);
3267 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3268 vec
->definitions
[0] = Definition(res
);
3269 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3273 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3275 Builder
bld(ctx
->program
, ctx
->block
);
3276 unsigned bytes_written
= 0;
3277 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3278 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3280 while (bytes_written
< total_size
* 4) {
3281 unsigned todo
= total_size
* 4 - bytes_written
;
3282 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3283 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3285 aco_opcode op
= aco_opcode::last_opcode
;
3286 bool write2
= false;
3288 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3289 op
= aco_opcode::ds_write_b128
;
3291 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3292 op
= aco_opcode::ds_write2_b64
;
3295 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3296 op
= aco_opcode::ds_write_b96
;
3298 } else if (todo
>= 8 && aligned8
) {
3299 op
= aco_opcode::ds_write_b64
;
3301 } else if (todo
>= 8 && usable_write2
) {
3302 op
= aco_opcode::ds_write2_b32
;
3305 } else if (todo
>= 4) {
3306 op
= aco_opcode::ds_write_b32
;
3312 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3313 unsigned max_offset
= write2
? 1020 : 65535;
3314 Temp address_offset
= address
;
3315 if (offset
> max_offset
) {
3316 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3317 offset
= offset1
+ bytes_written
;
3319 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3322 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3323 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3324 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3326 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3327 bld
.ds(op
, address_offset
, val
, m
, offset
);
3330 bytes_written
+= size
* 4;
3334 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3335 Temp address
, unsigned base_offset
, unsigned align
)
3337 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3338 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3340 Operand m
= load_lds_size_m0(ctx
);
3342 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3343 assert(wrmask
<= 0x0f);
3344 int start
[2], count
[2];
3345 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3346 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3347 assert(wrmask
== 0);
3349 /* one combined store is sufficient */
3350 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3351 Builder
bld(ctx
->program
, ctx
->block
);
3353 Temp address_offset
= address
;
3354 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3355 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3359 assert(count
[0] == 1);
3360 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3362 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3363 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3364 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3365 base_offset
= base_offset
/ elem_size_bytes
;
3366 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3367 base_offset
+ start
[0], base_offset
+ start
[1]);
3371 for (unsigned i
= 0; i
< 2; i
++) {
3375 unsigned elem_size_words
= elem_size_bytes
/ 4;
3376 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3377 base_offset
, start
[i
] * elem_size_bytes
, align
);
3382 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3384 unsigned align
= 16;
3386 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3392 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3393 unsigned split_cnt
= 0u, Temp dst
= Temp())
3395 Builder
bld(ctx
->program
, ctx
->block
);
3396 unsigned dword_size
= elem_size_bytes
/ 4;
3399 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3401 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3402 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3403 instr
->definitions
[0] = Definition(dst
);
3405 for (unsigned i
= 0; i
< cnt
; ++i
) {
3407 assert(arr
[i
].size() == dword_size
);
3408 allocated_vec
[i
] = arr
[i
];
3409 instr
->operands
[i
] = Operand(arr
[i
]);
3411 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3412 allocated_vec
[i
] = zero
;
3413 instr
->operands
[i
] = Operand(zero
);
3417 bld
.insert(std::move(instr
));
3420 emit_split_vector(ctx
, dst
, split_cnt
);
3422 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3427 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3429 if (const_offset
>= 4096) {
3430 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3431 const_offset
%= 4096u;
3434 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3435 else if (unlikely(voffset
.regClass() == s1
))
3436 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3437 else if (likely(voffset
.regClass() == v1
))
3438 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3440 unreachable("Unsupported register class of voffset");
3443 return const_offset
;
3446 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3447 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3450 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3451 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3453 Builder
bld(ctx
->program
, ctx
->block
);
3454 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3455 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3457 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3458 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3459 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3460 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3461 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3463 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3466 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3467 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3468 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3470 Builder
bld(ctx
->program
, ctx
->block
);
3471 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3474 if (elem_size_bytes
== 8) {
3475 elem_size_bytes
= 4;
3476 write_mask
= widen_mask(write_mask
, 2);
3479 while (write_mask
) {
3482 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3487 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3488 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3490 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3491 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3494 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3495 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3505 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3506 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3508 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3509 assert(size_dwords
>= 1 && size_dwords
<= 4);
3511 Builder
bld(ctx
->program
, ctx
->block
);
3512 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3513 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3514 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3516 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3517 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3518 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3519 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3520 /* disable_wqm */ false, /* glc */ true,
3521 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3523 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3528 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3529 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3530 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3532 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3533 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3534 assert(!!stride
!= allow_combining
);
3536 Builder
bld(ctx
->program
, ctx
->block
);
3537 unsigned split_cnt
= num_components
;
3539 if (elem_size_bytes
== 8) {
3540 elem_size_bytes
= 4;
3541 num_components
*= 2;
3545 stride
= elem_size_bytes
;
3547 unsigned load_size
= 1;
3548 if (allow_combining
) {
3549 if ((num_components
% 4) == 0)
3551 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3553 else if ((num_components
% 2) == 0)
3557 unsigned num_loads
= num_components
/ load_size
;
3558 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3560 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3561 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3562 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3565 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3568 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3570 Builder
bld(ctx
->program
, ctx
->block
);
3571 Temp offset
= base_offset
.first
;
3572 unsigned const_offset
= base_offset
.second
;
3574 if (!nir_src_is_const(*off_src
)) {
3575 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3578 /* Calculate indirect offset with stride */
3579 if (likely(indirect_offset_arg
.regClass() == v1
))
3580 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3581 else if (indirect_offset_arg
.regClass() == s1
)
3582 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3584 unreachable("Unsupported register class of indirect offset");
3586 /* Add to the supplied base offset */
3587 if (offset
.id() == 0)
3588 offset
= with_stride
;
3589 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3590 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3591 else if (offset
.size() == 1 && with_stride
.size() == 1)
3592 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3594 unreachable("Unsupported register class of indirect offset");
3596 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3597 const_offset
+= const_offset_arg
* stride
;
3600 return std::make_pair(offset
, const_offset
);
3603 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3605 Builder
bld(ctx
->program
, ctx
->block
);
3608 if (off1
.first
.id() && off2
.first
.id()) {
3609 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3610 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3611 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3612 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3614 unreachable("Unsupported register class of indirect offset");
3616 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3619 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3622 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3624 Builder
bld(ctx
->program
, ctx
->block
);
3625 unsigned const_offset
= offs
.second
* multiplier
;
3627 if (!offs
.first
.id())
3628 return std::make_pair(offs
.first
, const_offset
);
3630 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3631 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3632 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3634 return std::make_pair(offset
, const_offset
);
3637 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3639 Builder
bld(ctx
->program
, ctx
->block
);
3641 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3642 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3643 /* component is in bytes */
3644 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3646 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3647 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3648 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3651 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3653 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3656 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3658 Builder
bld(ctx
->program
, ctx
->block
);
3660 switch (ctx
->shader
->info
.stage
) {
3661 case MESA_SHADER_TESS_CTRL
:
3662 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3663 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3664 case MESA_SHADER_TESS_EVAL
:
3665 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3667 unreachable("Unsupported stage in get_tess_rel_patch_id");
3671 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3673 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3674 Builder
bld(ctx
->program
, ctx
->block
);
3676 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3677 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3679 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3681 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3682 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3684 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3685 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3686 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3688 return offset_mul(ctx
, offs
, 4u);
3691 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3693 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3694 Builder
bld(ctx
->program
, ctx
->block
);
3696 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3697 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3698 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3699 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3700 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3701 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3703 std::pair
<Temp
, unsigned> offs
= instr
3704 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3705 : std::make_pair(Temp(), 0u);
3707 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3708 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3713 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3714 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3716 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3717 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3719 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3720 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3726 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3728 Builder
bld(ctx
->program
, ctx
->block
);
3730 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3731 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3733 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3735 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3736 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3737 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3739 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3740 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3745 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3747 Builder
bld(ctx
->program
, ctx
->block
);
3749 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3750 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3751 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3753 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3754 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3755 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3756 unsigned attr_stride
= ctx
->tcs_num_patches
;
3758 std::pair
<Temp
, unsigned> offs
= instr
3759 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3760 : std::make_pair(Temp(), 0u);
3762 if (const_base_offset
)
3763 offs
.second
+= const_base_offset
* attr_stride
;
3765 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3766 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3767 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3772 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3774 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3775 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3777 if (!nir_src_is_const(*off_src
)) {
3783 off
+= nir_src_as_uint(*off_src
) * 16u;
3786 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3787 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3794 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3796 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3797 unsigned component
= nir_intrinsic_component(instr
);
3798 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3800 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3801 if (off_instr
->type
!= nir_instr_type_load_const
)
3804 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3805 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3807 if (instr
->src
[0].ssa
->bit_size
== 64)
3808 write_mask
= widen_mask(write_mask
, 2);
3810 for (unsigned i
= 0; i
< 8; ++i
) {
3811 if (write_mask
& (1 << i
)) {
3812 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3813 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3821 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3823 /* Only TCS per-vertex inputs are supported by this function.
3824 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3826 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3829 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3830 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3831 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3832 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3833 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3834 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3839 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3840 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3841 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3842 assert(vec
.size() == dst
.size());
3844 Builder
bld(ctx
->program
, ctx
->block
);
3845 bld
.copy(Definition(dst
), vec
);
3849 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3851 Builder
bld(ctx
->program
, ctx
->block
);
3853 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3854 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3855 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3856 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3858 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3859 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3860 bool indirect_write
;
3861 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3862 if (temp_only_input
&& !indirect_write
)
3866 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3867 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3868 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3869 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3870 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3874 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3875 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3876 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3877 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3878 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3879 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3880 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3881 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3882 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3883 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3884 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3885 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3886 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3888 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3889 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3890 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3892 unreachable("Invalid LS or ES stage");
3895 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3896 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3897 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3901 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3903 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3904 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3905 off
!= ctx
->tcs_tess_lvl_in_loc
;
3908 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3910 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3911 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3914 uint64_t mask
= per_vertex
3915 ? ctx
->shader
->info
.outputs_read
3916 : ctx
->shader
->info
.patch_outputs_read
;
3917 bool indirect_write
;
3918 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3919 return indirect_write
|| output_read
;
3922 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3924 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3925 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3927 Builder
bld(ctx
->program
, ctx
->block
);
3929 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3930 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3931 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3933 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3934 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3935 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3936 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3938 if (write_to_vmem
) {
3939 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3940 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3941 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3943 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3944 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3945 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3949 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3950 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3951 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3955 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3957 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3958 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3960 Builder
bld(ctx
->program
, ctx
->block
);
3962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3963 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3964 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3965 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3967 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3970 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3972 if (ctx
->stage
== vertex_vs
||
3973 ctx
->stage
== tess_eval_vs
||
3974 ctx
->stage
== fragment_fs
||
3975 ctx
->stage
== ngg_vertex_gs
||
3976 ctx
->stage
== ngg_tess_eval_gs
||
3977 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3978 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3979 if (!stored_to_temps
) {
3980 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3981 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3982 fprintf(stderr
, "\n");
3985 } else if (ctx
->stage
== vertex_es
||
3986 ctx
->stage
== vertex_ls
||
3987 ctx
->stage
== tess_eval_es
||
3988 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3989 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3990 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3991 visit_store_ls_or_es_output(ctx
, instr
);
3992 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3993 visit_store_tcs_output(ctx
, instr
, false);
3995 unreachable("Shader stage not implemented");
3999 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4001 visit_load_tcs_output(ctx
, instr
, false);
4004 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4006 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4007 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4009 Builder
bld(ctx
->program
, ctx
->block
);
4010 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4011 if (ctx
->program
->has_16bank_lds
)
4012 interp_p1
.instr
->operands
[0].setLateKill(true);
4013 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4016 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4018 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4019 for (unsigned i
= 0; i
< num_components
; i
++)
4020 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4021 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4022 assert(num_components
== 4);
4023 Builder
bld(ctx
->program
, ctx
->block
);
4024 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4027 for (Operand
& op
: vec
->operands
)
4028 op
= op
.isUndefined() ? Operand(0u) : op
;
4030 vec
->definitions
[0] = Definition(dst
);
4031 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4032 emit_split_vector(ctx
, dst
, num_components
);
4036 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4038 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4039 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4040 unsigned idx
= nir_intrinsic_base(instr
);
4041 unsigned component
= nir_intrinsic_component(instr
);
4042 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4044 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4046 assert(offset
->u32
== 0);
4048 /* the lower 15bit of the prim_mask contain the offset into LDS
4049 * while the upper bits contain the number of prims */
4050 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4051 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4052 Builder
bld(ctx
->program
, ctx
->block
);
4053 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4054 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4055 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4056 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4057 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4060 if (instr
->dest
.ssa
.num_components
== 1) {
4061 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4063 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4064 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4066 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4067 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4068 vec
->operands
[i
] = Operand(tmp
);
4070 vec
->definitions
[0] = Definition(dst
);
4071 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4075 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4076 unsigned offset
, unsigned stride
, unsigned channels
)
4078 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4079 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4081 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4082 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4085 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4086 unsigned offset
, unsigned stride
, unsigned *channels
)
4088 if (!vtx_info
->chan_byte_size
) {
4089 *channels
= vtx_info
->num_channels
;
4090 return vtx_info
->chan_format
;
4093 unsigned num_channels
= *channels
;
4094 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4095 unsigned new_channels
= num_channels
+ 1;
4096 /* first, assume more loads is worse and try using a larger data format */
4097 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4099 /* don't make the attribute potentially out-of-bounds */
4100 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4104 if (new_channels
== 5) {
4105 /* then try decreasing load size (at the cost of more loads) */
4106 new_channels
= *channels
;
4107 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4111 if (new_channels
< *channels
)
4112 *channels
= new_channels
;
4113 num_channels
= new_channels
;
4116 switch (vtx_info
->chan_format
) {
4117 case V_008F0C_BUF_DATA_FORMAT_8
:
4118 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4119 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4120 case V_008F0C_BUF_DATA_FORMAT_16
:
4121 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4122 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4123 case V_008F0C_BUF_DATA_FORMAT_32
:
4124 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4125 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4127 unreachable("shouldn't reach here");
4128 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4131 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4132 * so we may need to fix it up. */
4133 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4135 Builder
bld(ctx
->program
, ctx
->block
);
4137 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4138 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4140 /* For the integer-like cases, do a natural sign extension.
4142 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4143 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4146 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4147 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4149 /* Convert back to the right type. */
4150 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4151 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4152 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4153 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4154 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4155 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4161 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4163 Builder
bld(ctx
->program
, ctx
->block
);
4164 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4165 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4167 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4168 if (off_instr
->type
!= nir_instr_type_load_const
) {
4169 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4170 nir_print_instr(off_instr
, stderr
);
4171 fprintf(stderr
, "\n");
4173 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4175 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4177 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4178 unsigned component
= nir_intrinsic_component(instr
);
4179 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4180 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4181 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4182 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4184 unsigned dfmt
= attrib_format
& 0xf;
4185 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4186 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4188 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4189 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4190 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4191 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4193 num_channels
= MAX2(num_channels
, 3);
4195 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4196 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4199 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4200 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4201 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4203 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4205 Temp divided
= bld
.tmp(v1
);
4206 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4207 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4209 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4212 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4215 index
= bld
.vadd32(bld
.def(v1
),
4216 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4217 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4220 Temp channels
[num_channels
];
4221 unsigned channel_start
= 0;
4222 bool direct_fetch
= false;
4224 /* skip unused channels at the start */
4225 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4226 channel_start
= ffs(mask
) - 1;
4227 for (unsigned i
= 0; i
< channel_start
; i
++)
4228 channels
[i
] = Temp(0, s1
);
4229 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4230 num_channels
= 3 - (ffs(mask
) - 1);
4234 while (channel_start
< num_channels
) {
4235 unsigned fetch_size
= num_channels
- channel_start
;
4236 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4237 bool expanded
= false;
4239 /* use MUBUF when possible to avoid possible alignment issues */
4240 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4241 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4242 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4243 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4244 vtx_info
->chan_byte_size
== 4;
4245 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4247 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4249 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4250 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4256 Temp fetch_index
= index
;
4257 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4258 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4259 fetch_offset
= fetch_offset
% attrib_stride
;
4262 Operand
soffset(0u);
4263 if (fetch_offset
>= 4096) {
4264 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4265 fetch_offset
%= 4096;
4269 switch (fetch_size
) {
4271 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4274 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4277 assert(ctx
->options
->chip_class
>= GFX7
||
4278 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4279 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4282 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4285 unreachable("Unimplemented load_input vector size");
4289 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4290 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4291 num_channels
<= 3)) {
4292 direct_fetch
= true;
4295 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4299 Instruction
*mubuf
= bld
.mubuf(opcode
,
4300 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4301 fetch_offset
, false, true).instr
;
4302 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4304 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4305 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4306 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4307 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4310 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4312 if (fetch_size
== 1) {
4313 channels
[channel_start
] = fetch_dst
;
4315 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4316 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4319 channel_start
+= fetch_size
;
4322 if (!direct_fetch
) {
4323 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4324 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4326 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4327 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4328 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4330 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4331 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4332 unsigned num_temp
= 0;
4333 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4334 unsigned idx
= i
+ component
;
4335 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4336 Temp channel
= channels
[swizzle
[idx
]];
4337 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4338 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4339 vec
->operands
[i
] = Operand(channel
);
4343 } else if (is_float
&& idx
== 3) {
4344 vec
->operands
[i
] = Operand(0x3f800000u
);
4345 } else if (!is_float
&& idx
== 3) {
4346 vec
->operands
[i
] = Operand(1u);
4348 vec
->operands
[i
] = Operand(0u);
4351 vec
->definitions
[0] = Definition(dst
);
4352 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4353 emit_split_vector(ctx
, dst
, dst
.size());
4355 if (num_temp
== dst
.size())
4356 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4358 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4359 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4360 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4361 if (off_instr
->type
!= nir_instr_type_load_const
||
4362 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4363 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4364 nir_print_instr(off_instr
, stderr
);
4365 fprintf(stderr
, "\n");
4368 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4369 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4371 assert(offset
->u32
== 0);
4373 /* the lower 15bit of the prim_mask contain the offset into LDS
4374 * while the upper bits contain the number of prims */
4375 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4376 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4377 Builder
bld(ctx
->program
, ctx
->block
);
4378 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4379 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4380 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4381 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4382 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4385 unsigned idx
= nir_intrinsic_base(instr
);
4386 unsigned component
= nir_intrinsic_component(instr
);
4387 unsigned vertex_id
= 2; /* P0 */
4389 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4390 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4391 switch (src0
->u32
) {
4393 vertex_id
= 2; /* P0 */
4396 vertex_id
= 0; /* P10 */
4399 vertex_id
= 1; /* P20 */
4402 unreachable("invalid vertex index");
4406 if (dst
.size() == 1) {
4407 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4409 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4410 for (unsigned i
= 0; i
< dst
.size(); i
++)
4411 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4412 vec
->definitions
[0] = Definition(dst
);
4413 bld
.insert(std::move(vec
));
4416 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4417 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4418 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4419 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4420 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4422 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4424 unreachable("Shader stage not implemented");
4428 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4430 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4432 Builder
bld(ctx
->program
, ctx
->block
);
4433 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4436 if (!nir_src_is_const(*vertex_src
)) {
4437 /* better code could be created, but this case probably doesn't happen
4438 * much in practice */
4439 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4440 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4443 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4444 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4446 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4448 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4451 if (vertex_offset
.id()) {
4452 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4453 Operand(i
), indirect_vertex
);
4454 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4456 vertex_offset
= elem
;
4460 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4461 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4463 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4464 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4465 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4466 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4467 Operand((vertex
% 2u) * 16u), Operand(16u));
4469 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4472 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4473 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4474 return offset_mul(ctx
, offs
, 4u);
4477 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4479 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4481 Builder
bld(ctx
->program
, ctx
->block
);
4482 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4483 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4485 if (ctx
->stage
== geometry_gs
) {
4486 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4487 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4488 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4489 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4490 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4491 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4492 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4494 unreachable("Unsupported GS stage.");
4498 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4500 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4502 Builder
bld(ctx
->program
, ctx
->block
);
4503 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4505 if (load_input_from_temps(ctx
, instr
, dst
))
4508 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4509 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4510 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4512 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4515 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4517 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4519 Builder
bld(ctx
->program
, ctx
->block
);
4521 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4522 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4523 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4525 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4526 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4528 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4531 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4533 switch (ctx
->shader
->info
.stage
) {
4534 case MESA_SHADER_GEOMETRY
:
4535 visit_load_gs_per_vertex_input(ctx
, instr
);
4537 case MESA_SHADER_TESS_CTRL
:
4538 visit_load_tcs_per_vertex_input(ctx
, instr
);
4540 case MESA_SHADER_TESS_EVAL
:
4541 visit_load_tes_per_vertex_input(ctx
, instr
);
4544 unreachable("Unimplemented shader stage");
4548 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4550 visit_load_tcs_output(ctx
, instr
, true);
4553 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4555 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4556 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4558 visit_store_tcs_output(ctx
, instr
, true);
4561 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4563 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4565 Builder
bld(ctx
->program
, ctx
->block
);
4566 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4568 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4569 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4572 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4573 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4574 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4575 tes_w
= Operand(tmp
);
4578 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4579 emit_split_vector(ctx
, tess_coord
, 3);
4582 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4584 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4585 Builder
bld(ctx
->program
, ctx
->block
);
4586 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4587 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4588 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4591 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4595 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4597 Builder
bld(ctx
->program
, ctx
->block
);
4598 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4599 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4600 index
= bld
.as_uniform(index
);
4601 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4602 unsigned binding
= nir_intrinsic_binding(instr
);
4605 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4606 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4607 unsigned offset
= layout
->binding
[binding
].offset
;
4609 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4610 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4611 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4612 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4613 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4616 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4617 stride
= layout
->binding
[binding
].size
;
4620 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4621 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4623 if (nir_const_index
) {
4624 const_index
= const_index
* stride
;
4625 } else if (index
.type() == RegType::vgpr
) {
4626 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4627 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4629 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4633 if (nir_const_index
) {
4634 const_index
= const_index
+ offset
;
4635 } else if (index
.type() == RegType::vgpr
) {
4636 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4638 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4642 if (nir_const_index
&& const_index
== 0) {
4644 } else if (index
.type() == RegType::vgpr
) {
4645 index
= bld
.vadd32(bld
.def(v1
),
4646 nir_const_index
? Operand(const_index
) : Operand(index
),
4649 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4650 nir_const_index
? Operand(const_index
) : Operand(index
),
4654 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4657 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4658 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4659 bool glc
=false, bool readonly
=true)
4661 Builder
bld(ctx
->program
, ctx
->block
);
4662 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4663 unsigned num_bytes
= num_components
* component_size
;
4666 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4667 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4668 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4669 unsigned const_offset
= 0;
4671 /* for small bit sizes add buffer for unaligned loads */
4674 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4679 Temp lower
= Temp();
4680 if (num_bytes
> 16) {
4681 assert(num_components
== 3 || num_components
== 4);
4682 op
= aco_opcode::buffer_load_dwordx4
;
4683 lower
= bld
.tmp(v4
);
4684 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4685 mubuf
->definitions
[0] = Definition(lower
);
4686 mubuf
->operands
[0] = Operand(rsrc
);
4687 mubuf
->operands
[1] = vaddr
;
4688 mubuf
->operands
[2] = soffset
;
4689 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4692 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4693 mubuf
->can_reorder
= readonly
;
4694 bld
.insert(std::move(mubuf
));
4695 emit_split_vector(ctx
, lower
, 2);
4698 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4699 /* GFX6 doesn't support loading vec3, expand to vec4. */
4703 switch (num_bytes
) {
4705 op
= aco_opcode::buffer_load_ubyte
;
4708 op
= aco_opcode::buffer_load_ushort
;
4712 op
= aco_opcode::buffer_load_dword
;
4718 op
= aco_opcode::buffer_load_dwordx2
;
4722 assert(ctx
->options
->chip_class
> GFX6
);
4723 op
= aco_opcode::buffer_load_dwordx3
;
4726 op
= aco_opcode::buffer_load_dwordx4
;
4729 unreachable("Load SSBO not implemented for this size.");
4731 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4732 mubuf
->operands
[0] = Operand(rsrc
);
4733 mubuf
->operands
[1] = vaddr
;
4734 mubuf
->operands
[2] = soffset
;
4735 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4738 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4739 mubuf
->can_reorder
= readonly
;
4740 mubuf
->offset
= const_offset
;
4741 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4743 if (component_size
< 4) {
4744 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4745 instr
->definitions
[0] = Definition(vec
);
4746 bld
.insert(std::move(instr
));
4748 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4749 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4750 Temp tmp
[3] = {vec
, vec
, vec
};
4752 if (vec
.size() == 3) {
4753 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4754 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4755 } else if (vec
.size() == 2) {
4756 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4757 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4759 for (unsigned i
= 0; i
< dst
.size(); i
++)
4760 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4763 if (dst
.size() == 2)
4764 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4769 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4770 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4772 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4777 } else if (dst
.size() > 4) {
4778 assert(lower
!= Temp());
4779 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4780 instr
->definitions
[0] = Definition(upper
);
4781 bld
.insert(std::move(instr
));
4782 if (dst
.size() == 8)
4783 emit_split_vector(ctx
, upper
, 2);
4784 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4785 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4786 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4787 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4788 if (dst
.size() == 8)
4789 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4790 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4791 Temp vec
= bld
.tmp(v4
);
4792 instr
->definitions
[0] = Definition(vec
);
4793 bld
.insert(std::move(instr
));
4794 emit_split_vector(ctx
, vec
, 4);
4796 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4797 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4798 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4799 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4802 if (dst
.type() == RegType::sgpr
) {
4803 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4804 instr
->definitions
[0] = Definition(vec
);
4805 bld
.insert(std::move(instr
));
4806 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4808 instr
->definitions
[0] = Definition(dst
);
4809 bld
.insert(std::move(instr
));
4810 emit_split_vector(ctx
, dst
, num_components
);
4813 /* for small bit sizes add buffer for unaligned loads */
4815 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4817 switch (num_bytes
) {
4822 op
= aco_opcode::s_buffer_load_dword
;
4828 op
= aco_opcode::s_buffer_load_dwordx2
;
4833 op
= aco_opcode::s_buffer_load_dwordx4
;
4837 op
= aco_opcode::s_buffer_load_dwordx8
;
4840 unreachable("Load SSBO not implemented for this size.");
4842 offset
= bld
.as_uniform(offset
);
4843 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4844 load
->operands
[0] = Operand(rsrc
);
4845 load
->operands
[1] = Operand(offset
);
4846 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4847 load
->definitions
[0] = Definition(dst
);
4850 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4851 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4852 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4854 /* adjust misaligned small bit size loads */
4856 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4857 load
->definitions
[0] = Definition(vec
);
4858 bld
.insert(std::move(load
));
4859 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4860 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4863 } else if (dst
.size() == 3) {
4864 Temp vec
= bld
.tmp(s4
);
4865 load
->definitions
[0] = Definition(vec
);
4866 bld
.insert(std::move(load
));
4867 emit_split_vector(ctx
, vec
, 4);
4869 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4870 emit_extract_vector(ctx
, vec
, 0, s1
),
4871 emit_extract_vector(ctx
, vec
, 1, s1
),
4872 emit_extract_vector(ctx
, vec
, 2, s1
));
4873 } else if (dst
.size() == 6) {
4874 Temp vec
= bld
.tmp(s8
);
4875 load
->definitions
[0] = Definition(vec
);
4876 bld
.insert(std::move(load
));
4877 emit_split_vector(ctx
, vec
, 4);
4879 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4880 emit_extract_vector(ctx
, vec
, 0, s2
),
4881 emit_extract_vector(ctx
, vec
, 1, s2
),
4882 emit_extract_vector(ctx
, vec
, 2, s2
));
4884 bld
.insert(std::move(load
));
4886 emit_split_vector(ctx
, dst
, num_components
);
4890 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4892 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4893 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4895 Builder
bld(ctx
->program
, ctx
->block
);
4897 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4898 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4899 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4900 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4902 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4903 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4904 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4905 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4906 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4907 if (ctx
->options
->chip_class
>= GFX10
) {
4908 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4909 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4910 S_008F0C_RESOURCE_LEVEL(1);
4912 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4913 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4915 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4916 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4917 Operand(0xFFFFFFFFu
),
4918 Operand(desc_type
));
4919 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4920 rsrc
, upper_dwords
);
4922 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4923 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4925 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4928 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4929 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4930 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4932 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4935 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4937 Builder
bld(ctx
->program
, ctx
->block
);
4938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4939 unsigned offset
= nir_intrinsic_base(instr
);
4940 unsigned count
= instr
->dest
.ssa
.num_components
;
4941 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4943 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4944 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4945 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4946 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4947 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4948 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4949 for (unsigned i
= 0; i
< count
; ++i
) {
4950 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4951 vec
->operands
[i
] = Operand
{elems
[i
]};
4953 vec
->definitions
[0] = Definition(dst
);
4954 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4955 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4960 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4961 if (offset
!= 0) // TODO check if index != 0 as well
4962 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4963 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4966 bool aligned
= true;
4968 if (instr
->dest
.ssa
.bit_size
== 8) {
4969 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4970 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4972 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4973 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4974 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4976 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4981 switch (vec
.size()) {
4983 op
= aco_opcode::s_load_dword
;
4986 op
= aco_opcode::s_load_dwordx2
;
4992 op
= aco_opcode::s_load_dwordx4
;
4998 op
= aco_opcode::s_load_dwordx8
;
5001 unreachable("unimplemented or forbidden load_push_constant.");
5004 bld
.smem(op
, Definition(vec
), ptr
, index
);
5007 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5008 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5013 emit_split_vector(ctx
, vec
, 4);
5014 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5015 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5016 emit_extract_vector(ctx
, vec
, 0, rc
),
5017 emit_extract_vector(ctx
, vec
, 1, rc
),
5018 emit_extract_vector(ctx
, vec
, 2, rc
));
5021 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5024 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5026 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5028 Builder
bld(ctx
->program
, ctx
->block
);
5030 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5031 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5032 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5033 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5034 if (ctx
->options
->chip_class
>= GFX10
) {
5035 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5036 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5037 S_008F0C_RESOURCE_LEVEL(1);
5039 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5040 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5043 unsigned base
= nir_intrinsic_base(instr
);
5044 unsigned range
= nir_intrinsic_range(instr
);
5046 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5047 if (base
&& offset
.type() == RegType::sgpr
)
5048 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5049 else if (base
&& offset
.type() == RegType::vgpr
)
5050 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5052 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5053 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5054 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5055 Operand(desc_type
));
5056 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5057 // TODO: get alignment information for subdword constants
5058 unsigned byte_align
= size
< 4 ? -1 : 0;
5059 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
5062 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5064 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5065 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5067 ctx
->program
->needs_exact
= true;
5069 // TODO: optimize uniform conditions
5070 Builder
bld(ctx
->program
, ctx
->block
);
5071 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5072 assert(src
.regClass() == bld
.lm
);
5073 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5074 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5075 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5079 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5081 Builder
bld(ctx
->program
, ctx
->block
);
5083 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5084 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5086 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5087 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5089 if (ctx
->block
->loop_nest_depth
&&
5090 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5091 /* we handle discards the same way as jump instructions */
5092 append_logical_end(ctx
->block
);
5094 /* in loops, discard behaves like break */
5095 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5096 ctx
->block
->kind
|= block_kind_discard
;
5099 /* uniform discard - loop ends here */
5100 assert(nir_instr_is_last(&instr
->instr
));
5101 ctx
->block
->kind
|= block_kind_uniform
;
5102 ctx
->cf_info
.has_branch
= true;
5103 bld
.branch(aco_opcode::p_branch
);
5104 add_linear_edge(ctx
->block
->index
, linear_target
);
5108 /* we add a break right behind the discard() instructions */
5109 ctx
->block
->kind
|= block_kind_break
;
5110 unsigned idx
= ctx
->block
->index
;
5112 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5113 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5115 /* remove critical edges from linear CFG */
5116 bld
.branch(aco_opcode::p_branch
);
5117 Block
* break_block
= ctx
->program
->create_and_insert_block();
5118 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5119 break_block
->kind
|= block_kind_uniform
;
5120 add_linear_edge(idx
, break_block
);
5121 add_linear_edge(break_block
->index
, linear_target
);
5122 bld
.reset(break_block
);
5123 bld
.branch(aco_opcode::p_branch
);
5125 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5126 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5127 add_linear_edge(idx
, continue_block
);
5128 append_logical_start(continue_block
);
5129 ctx
->block
= continue_block
;
5134 /* it can currently happen that NIR doesn't remove the unreachable code */
5135 if (!nir_instr_is_last(&instr
->instr
)) {
5136 ctx
->program
->needs_exact
= true;
5137 /* save exec somewhere temporarily so that it doesn't get
5138 * overwritten before the discard from outer exec masks */
5139 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5140 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5141 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5145 /* This condition is incorrect for uniformly branched discards in a loop
5146 * predicated by a divergent condition, but the above code catches that case
5147 * and the discard would end up turning into a discard_if.
5157 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5158 /* program just ends here */
5159 ctx
->block
->kind
|= block_kind_uniform
;
5160 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5161 0 /* enabled mask */, 9 /* dest */,
5162 false /* compressed */, true/* done */, true /* valid mask */);
5163 bld
.sopp(aco_opcode::s_endpgm
);
5164 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5166 ctx
->block
->kind
|= block_kind_discard
;
5167 /* branch and linear edge is added by visit_if() */
5171 enum aco_descriptor_type
{
5182 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5183 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5185 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5186 return dim
== ac_image_cube
||
5187 dim
== ac_image_1darray
||
5188 dim
== ac_image_2darray
||
5189 dim
== ac_image_2darraymsaa
;
5192 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5193 enum aco_descriptor_type desc_type
,
5194 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5196 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5197 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5198 if (it != ctx->tex_desc.end())
5201 Temp index
= Temp();
5202 bool index_set
= false;
5203 unsigned constant_index
= 0;
5204 unsigned descriptor_set
;
5205 unsigned base_index
;
5206 Builder
bld(ctx
->program
, ctx
->block
);
5209 assert(tex_instr
&& !image
);
5211 base_index
= tex_instr
->sampler_index
;
5213 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5214 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5218 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5219 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5221 constant_index
+= array_size
* const_value
->u32
;
5223 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5224 if (indirect
.type() == RegType::vgpr
)
5225 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5227 if (array_size
!= 1)
5228 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5234 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5238 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5240 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5241 base_index
= deref_instr
->var
->data
.binding
;
5244 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5245 list
= convert_pointer_to_64_bit(ctx
, list
);
5247 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5248 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5249 unsigned offset
= binding
->offset
;
5250 unsigned stride
= binding
->size
;
5254 assert(base_index
< layout
->binding_count
);
5256 switch (desc_type
) {
5257 case ACO_DESC_IMAGE
:
5259 opcode
= aco_opcode::s_load_dwordx8
;
5261 case ACO_DESC_FMASK
:
5263 opcode
= aco_opcode::s_load_dwordx8
;
5266 case ACO_DESC_SAMPLER
:
5268 opcode
= aco_opcode::s_load_dwordx4
;
5269 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5270 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5272 case ACO_DESC_BUFFER
:
5274 opcode
= aco_opcode::s_load_dwordx4
;
5276 case ACO_DESC_PLANE_0
:
5277 case ACO_DESC_PLANE_1
:
5279 opcode
= aco_opcode::s_load_dwordx8
;
5280 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5282 case ACO_DESC_PLANE_2
:
5284 opcode
= aco_opcode::s_load_dwordx4
;
5288 unreachable("invalid desc_type\n");
5291 offset
+= constant_index
* stride
;
5293 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5294 (!index_set
|| binding
->immutable_samplers_equal
)) {
5295 if (binding
->immutable_samplers_equal
)
5298 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5299 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5300 Operand(samplers
[constant_index
* 4 + 0]),
5301 Operand(samplers
[constant_index
* 4 + 1]),
5302 Operand(samplers
[constant_index
* 4 + 2]),
5303 Operand(samplers
[constant_index
* 4 + 3]));
5308 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5310 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5311 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5314 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5316 if (desc_type
== ACO_DESC_PLANE_2
) {
5318 for (unsigned i
= 0; i
< 8; i
++)
5319 components
[i
] = bld
.tmp(s1
);
5320 bld
.pseudo(aco_opcode::p_split_vector
,
5321 Definition(components
[0]),
5322 Definition(components
[1]),
5323 Definition(components
[2]),
5324 Definition(components
[3]),
5327 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5328 bld
.pseudo(aco_opcode::p_split_vector
,
5329 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5330 Definition(components
[4]),
5331 Definition(components
[5]),
5332 Definition(components
[6]),
5333 Definition(components
[7]),
5336 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5337 components
[0], components
[1], components
[2], components
[3],
5338 components
[4], components
[5], components
[6], components
[7]);
5344 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5347 case GLSL_SAMPLER_DIM_BUF
:
5349 case GLSL_SAMPLER_DIM_1D
:
5350 return array
? 2 : 1;
5351 case GLSL_SAMPLER_DIM_2D
:
5352 return array
? 3 : 2;
5353 case GLSL_SAMPLER_DIM_MS
:
5354 return array
? 4 : 3;
5355 case GLSL_SAMPLER_DIM_3D
:
5356 case GLSL_SAMPLER_DIM_CUBE
:
5358 case GLSL_SAMPLER_DIM_RECT
:
5359 case GLSL_SAMPLER_DIM_SUBPASS
:
5361 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5370 /* Adjust the sample index according to FMASK.
5372 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5373 * which is the identity mapping. Each nibble says which physical sample
5374 * should be fetched to get that sample.
5376 * For example, 0x11111100 means there are only 2 samples stored and
5377 * the second sample covers 3/4 of the pixel. When reading samples 0
5378 * and 1, return physical sample 0 (determined by the first two 0s
5379 * in FMASK), otherwise return physical sample 1.
5381 * The sample index should be adjusted as follows:
5382 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5384 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5386 Builder
bld(ctx
->program
, ctx
->block
);
5387 Temp fmask
= bld
.tmp(v1
);
5388 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5389 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5392 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5393 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5394 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5395 load
->operands
[0] = Operand(fmask_desc_ptr
);
5396 load
->operands
[1] = Operand(s4
); /* no sampler */
5397 load
->operands
[2] = Operand(coord
);
5398 load
->definitions
[0] = Definition(fmask
);
5405 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5406 ctx
->block
->instructions
.emplace_back(std::move(load
));
5408 Operand sample_index4
;
5409 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5410 sample_index4
= Operand(sample_index
.constantValue() << 2);
5411 } else if (sample_index
.regClass() == s1
) {
5412 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5414 assert(sample_index
.regClass() == v1
);
5415 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5419 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5420 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5421 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5422 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5424 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5426 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5427 * resource descriptor is 0 (invalid),
5429 Temp compare
= bld
.tmp(bld
.lm
);
5430 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5431 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5433 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5435 /* Replace the MSAA sample index. */
5436 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5439 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5442 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5443 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5444 bool is_array
= glsl_sampler_type_is_array(type
);
5445 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5446 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5447 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5448 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5449 int count
= image_type_to_components_count(dim
, is_array
);
5450 std::vector
<Temp
> coords(count
);
5451 Builder
bld(ctx
->program
, ctx
->block
);
5455 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5456 /* get sample index */
5457 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5458 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5459 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5460 std::vector
<Temp
> fmask_load_address
;
5461 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5462 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5464 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5465 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5467 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5472 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5473 coords
.resize(coords
.size() + 1);
5474 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5476 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5478 for (int i
= 0; i
< count
; i
++)
5479 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5482 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5483 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5484 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5485 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5488 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5491 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5492 for (unsigned i
= 0; i
< coords
.size(); i
++)
5493 vec
->operands
[i
] = Operand(coords
[i
]);
5494 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5495 vec
->definitions
[0] = Definition(res
);
5496 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5501 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5503 Builder
bld(ctx
->program
, ctx
->block
);
5504 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5505 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5506 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5507 bool is_array
= glsl_sampler_type_is_array(type
);
5508 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5510 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5511 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5512 unsigned num_channels
= util_last_bit(mask
);
5513 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5514 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5517 switch (num_channels
) {
5519 opcode
= aco_opcode::buffer_load_format_x
;
5522 opcode
= aco_opcode::buffer_load_format_xy
;
5525 opcode
= aco_opcode::buffer_load_format_xyz
;
5528 opcode
= aco_opcode::buffer_load_format_xyzw
;
5531 unreachable(">4 channel buffer image load");
5533 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5534 load
->operands
[0] = Operand(rsrc
);
5535 load
->operands
[1] = Operand(vindex
);
5536 load
->operands
[2] = Operand((uint32_t) 0);
5538 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5541 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5542 load
->definitions
[0] = Definition(tmp
);
5544 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5545 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5546 load
->barrier
= barrier_image
;
5547 ctx
->block
->instructions
.emplace_back(std::move(load
));
5549 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5553 Temp coords
= get_image_coords(ctx
, instr
, type
);
5554 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5556 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5557 unsigned num_components
= util_bitcount(dmask
);
5559 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5562 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5564 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5565 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5567 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5568 load
->operands
[0] = Operand(resource
);
5569 load
->operands
[1] = Operand(s4
); /* no sampler */
5570 load
->operands
[2] = Operand(coords
);
5571 load
->definitions
[0] = Definition(tmp
);
5572 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5573 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5574 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5575 load
->dmask
= dmask
;
5577 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5578 load
->barrier
= barrier_image
;
5579 ctx
->block
->instructions
.emplace_back(std::move(load
));
5581 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5585 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5587 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5588 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5589 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5590 bool is_array
= glsl_sampler_type_is_array(type
);
5591 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5593 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5595 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5596 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5597 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5599 switch (data
.size()) {
5601 opcode
= aco_opcode::buffer_store_format_x
;
5604 opcode
= aco_opcode::buffer_store_format_xy
;
5607 opcode
= aco_opcode::buffer_store_format_xyz
;
5610 opcode
= aco_opcode::buffer_store_format_xyzw
;
5613 unreachable(">4 channel buffer image store");
5615 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5616 store
->operands
[0] = Operand(rsrc
);
5617 store
->operands
[1] = Operand(vindex
);
5618 store
->operands
[2] = Operand((uint32_t) 0);
5619 store
->operands
[3] = Operand(data
);
5620 store
->idxen
= true;
5623 store
->disable_wqm
= true;
5624 store
->barrier
= barrier_image
;
5625 ctx
->program
->needs_exact
= true;
5626 ctx
->block
->instructions
.emplace_back(std::move(store
));
5630 assert(data
.type() == RegType::vgpr
);
5631 Temp coords
= get_image_coords(ctx
, instr
, type
);
5632 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5634 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5635 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5637 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5638 store
->operands
[0] = Operand(resource
);
5639 store
->operands
[1] = Operand(data
);
5640 store
->operands
[2] = Operand(coords
);
5643 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5644 store
->dmask
= (1 << data
.size()) - 1;
5646 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5647 store
->disable_wqm
= true;
5648 store
->barrier
= barrier_image
;
5649 ctx
->program
->needs_exact
= true;
5650 ctx
->block
->instructions
.emplace_back(std::move(store
));
5654 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5656 /* return the previous value if dest is ever used */
5657 bool return_previous
= false;
5658 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5659 return_previous
= true;
5662 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5663 return_previous
= true;
5667 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5668 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5669 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5670 bool is_array
= glsl_sampler_type_is_array(type
);
5671 Builder
bld(ctx
->program
, ctx
->block
);
5673 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5674 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5676 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5677 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5679 aco_opcode buf_op
, image_op
;
5680 switch (instr
->intrinsic
) {
5681 case nir_intrinsic_image_deref_atomic_add
:
5682 buf_op
= aco_opcode::buffer_atomic_add
;
5683 image_op
= aco_opcode::image_atomic_add
;
5685 case nir_intrinsic_image_deref_atomic_umin
:
5686 buf_op
= aco_opcode::buffer_atomic_umin
;
5687 image_op
= aco_opcode::image_atomic_umin
;
5689 case nir_intrinsic_image_deref_atomic_imin
:
5690 buf_op
= aco_opcode::buffer_atomic_smin
;
5691 image_op
= aco_opcode::image_atomic_smin
;
5693 case nir_intrinsic_image_deref_atomic_umax
:
5694 buf_op
= aco_opcode::buffer_atomic_umax
;
5695 image_op
= aco_opcode::image_atomic_umax
;
5697 case nir_intrinsic_image_deref_atomic_imax
:
5698 buf_op
= aco_opcode::buffer_atomic_smax
;
5699 image_op
= aco_opcode::image_atomic_smax
;
5701 case nir_intrinsic_image_deref_atomic_and
:
5702 buf_op
= aco_opcode::buffer_atomic_and
;
5703 image_op
= aco_opcode::image_atomic_and
;
5705 case nir_intrinsic_image_deref_atomic_or
:
5706 buf_op
= aco_opcode::buffer_atomic_or
;
5707 image_op
= aco_opcode::image_atomic_or
;
5709 case nir_intrinsic_image_deref_atomic_xor
:
5710 buf_op
= aco_opcode::buffer_atomic_xor
;
5711 image_op
= aco_opcode::image_atomic_xor
;
5713 case nir_intrinsic_image_deref_atomic_exchange
:
5714 buf_op
= aco_opcode::buffer_atomic_swap
;
5715 image_op
= aco_opcode::image_atomic_swap
;
5717 case nir_intrinsic_image_deref_atomic_comp_swap
:
5718 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5719 image_op
= aco_opcode::image_atomic_cmpswap
;
5722 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5725 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5727 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5728 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5729 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5730 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5731 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5732 mubuf
->operands
[0] = Operand(resource
);
5733 mubuf
->operands
[1] = Operand(vindex
);
5734 mubuf
->operands
[2] = Operand((uint32_t)0);
5735 mubuf
->operands
[3] = Operand(data
);
5736 if (return_previous
)
5737 mubuf
->definitions
[0] = Definition(dst
);
5739 mubuf
->idxen
= true;
5740 mubuf
->glc
= return_previous
;
5741 mubuf
->dlc
= false; /* Not needed for atomics */
5742 mubuf
->disable_wqm
= true;
5743 mubuf
->barrier
= barrier_image
;
5744 ctx
->program
->needs_exact
= true;
5745 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5749 Temp coords
= get_image_coords(ctx
, instr
, type
);
5750 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5751 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5752 mimg
->operands
[0] = Operand(resource
);
5753 mimg
->operands
[1] = Operand(data
);
5754 mimg
->operands
[2] = Operand(coords
);
5755 if (return_previous
)
5756 mimg
->definitions
[0] = Definition(dst
);
5757 mimg
->glc
= return_previous
;
5758 mimg
->dlc
= false; /* Not needed for atomics */
5759 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5760 mimg
->dmask
= (1 << data
.size()) - 1;
5762 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5763 mimg
->disable_wqm
= true;
5764 mimg
->barrier
= barrier_image
;
5765 ctx
->program
->needs_exact
= true;
5766 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5770 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5772 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5773 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5774 Builder
bld(ctx
->program
, ctx
->block
);
5776 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5778 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5779 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5781 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5782 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5784 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5785 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5787 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5788 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5789 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5790 if (dst
.type() == RegType::vgpr
)
5791 bld
.copy(Definition(dst
), shr_dst
);
5793 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5795 emit_extract_vector(ctx
, desc
, 2, dst
);
5799 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5801 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5802 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5803 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5804 bool is_array
= glsl_sampler_type_is_array(type
);
5805 Builder
bld(ctx
->program
, ctx
->block
);
5807 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5808 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5809 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5813 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5816 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5818 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5820 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5821 mimg
->operands
[0] = Operand(resource
);
5822 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5823 mimg
->operands
[2] = Operand(lod
);
5824 uint8_t& dmask
= mimg
->dmask
;
5825 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5826 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5827 mimg
->da
= glsl_sampler_type_is_array(type
);
5828 mimg
->can_reorder
= true;
5829 Definition
& def
= mimg
->definitions
[0];
5830 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5832 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5833 glsl_sampler_type_is_array(type
)) {
5835 assert(instr
->dest
.ssa
.num_components
== 3);
5836 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5837 def
= Definition(tmp
);
5838 emit_split_vector(ctx
, tmp
, 3);
5840 /* divide 3rd value by 6 by multiplying with magic number */
5841 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5842 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5844 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5845 emit_extract_vector(ctx
, tmp
, 0, v1
),
5846 emit_extract_vector(ctx
, tmp
, 1, v1
),
5849 } else if (ctx
->options
->chip_class
== GFX9
&&
5850 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5851 glsl_sampler_type_is_array(type
)) {
5852 assert(instr
->dest
.ssa
.num_components
== 2);
5853 def
= Definition(dst
);
5856 def
= Definition(dst
);
5859 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5862 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5864 Builder
bld(ctx
->program
, ctx
->block
);
5865 unsigned num_components
= instr
->num_components
;
5867 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5868 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5869 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5871 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5872 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5875 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5876 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5877 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5879 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5882 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5884 Builder
bld(ctx
->program
, ctx
->block
);
5885 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5886 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5887 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5888 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5890 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5891 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5893 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5894 ctx
->options
->chip_class
>= GFX8
&&
5895 elem_size_bytes
>= 4;
5897 offset
= bld
.as_uniform(offset
);
5898 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5902 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5903 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5904 /* GFX6 doesn't support storing vec3, split it. */
5905 writemask
|= 1u << (start
+ 2);
5908 int num_bytes
= count
* elem_size_bytes
;
5910 /* dword or larger stores have to be dword-aligned */
5911 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5912 // TODO: improve alignment check of sub-dword stores
5913 unsigned count_new
= 2 / elem_size_bytes
;
5914 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5919 if (num_bytes
> 16) {
5920 assert(elem_size_bytes
== 8);
5921 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5927 if (elem_size_bytes
< 4) {
5928 if (data
.type() == RegType::sgpr
) {
5929 data
= as_vgpr(ctx
, data
);
5930 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5932 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5933 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5934 for (int i
= 0; i
< count
; i
++)
5935 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5936 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5937 vec
->definitions
[0] = Definition(write_data
);
5938 bld
.insert(std::move(vec
));
5939 } else if (count
!= instr
->num_components
) {
5940 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5941 for (int i
= 0; i
< count
; i
++) {
5942 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5943 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5945 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5946 vec
->definitions
[0] = Definition(write_data
);
5947 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5948 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5949 assert(num_bytes
% 4 == 0);
5950 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5951 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5952 assert(num_bytes
% 4 == 0);
5953 write_data
= bld
.as_uniform(data
);
5958 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5959 switch (num_bytes
) {
5961 vmem_op
= aco_opcode::buffer_store_byte
;
5964 vmem_op
= aco_opcode::buffer_store_short
;
5967 vmem_op
= aco_opcode::buffer_store_dword
;
5968 smem_op
= aco_opcode::s_buffer_store_dword
;
5971 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5972 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5975 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5976 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5979 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5980 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5983 unreachable("Store SSBO not implemented for this size.");
5985 if (ctx
->stage
== fragment_fs
)
5986 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5989 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5990 store
->operands
[0] = Operand(rsrc
);
5992 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5993 offset
, Operand(start
* elem_size_bytes
));
5994 store
->operands
[1] = Operand(off
);
5996 store
->operands
[1] = Operand(offset
);
5998 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5999 store
->operands
[1].setFixed(m0
);
6000 store
->operands
[2] = Operand(write_data
);
6001 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6003 store
->disable_wqm
= true;
6004 store
->barrier
= barrier_buffer
;
6005 ctx
->block
->instructions
.emplace_back(std::move(store
));
6006 ctx
->program
->wb_smem_l1_on_end
= true;
6007 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
6008 ctx
->block
->kind
|= block_kind_needs_lowering
;
6009 ctx
->program
->needs_exact
= true;
6012 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
6013 store
->operands
[0] = Operand(rsrc
);
6014 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6015 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6016 store
->operands
[3] = Operand(write_data
);
6017 store
->offset
= start
* elem_size_bytes
;
6018 store
->offen
= (offset
.type() == RegType::vgpr
);
6019 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6021 store
->disable_wqm
= true;
6022 store
->barrier
= barrier_buffer
;
6023 ctx
->program
->needs_exact
= true;
6024 ctx
->block
->instructions
.emplace_back(std::move(store
));
6029 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6031 /* return the previous value if dest is ever used */
6032 bool return_previous
= false;
6033 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6034 return_previous
= true;
6037 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6038 return_previous
= true;
6042 Builder
bld(ctx
->program
, ctx
->block
);
6043 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6045 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6046 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6047 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6049 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6050 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6051 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6053 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6055 aco_opcode op32
, op64
;
6056 switch (instr
->intrinsic
) {
6057 case nir_intrinsic_ssbo_atomic_add
:
6058 op32
= aco_opcode::buffer_atomic_add
;
6059 op64
= aco_opcode::buffer_atomic_add_x2
;
6061 case nir_intrinsic_ssbo_atomic_imin
:
6062 op32
= aco_opcode::buffer_atomic_smin
;
6063 op64
= aco_opcode::buffer_atomic_smin_x2
;
6065 case nir_intrinsic_ssbo_atomic_umin
:
6066 op32
= aco_opcode::buffer_atomic_umin
;
6067 op64
= aco_opcode::buffer_atomic_umin_x2
;
6069 case nir_intrinsic_ssbo_atomic_imax
:
6070 op32
= aco_opcode::buffer_atomic_smax
;
6071 op64
= aco_opcode::buffer_atomic_smax_x2
;
6073 case nir_intrinsic_ssbo_atomic_umax
:
6074 op32
= aco_opcode::buffer_atomic_umax
;
6075 op64
= aco_opcode::buffer_atomic_umax_x2
;
6077 case nir_intrinsic_ssbo_atomic_and
:
6078 op32
= aco_opcode::buffer_atomic_and
;
6079 op64
= aco_opcode::buffer_atomic_and_x2
;
6081 case nir_intrinsic_ssbo_atomic_or
:
6082 op32
= aco_opcode::buffer_atomic_or
;
6083 op64
= aco_opcode::buffer_atomic_or_x2
;
6085 case nir_intrinsic_ssbo_atomic_xor
:
6086 op32
= aco_opcode::buffer_atomic_xor
;
6087 op64
= aco_opcode::buffer_atomic_xor_x2
;
6089 case nir_intrinsic_ssbo_atomic_exchange
:
6090 op32
= aco_opcode::buffer_atomic_swap
;
6091 op64
= aco_opcode::buffer_atomic_swap_x2
;
6093 case nir_intrinsic_ssbo_atomic_comp_swap
:
6094 op32
= aco_opcode::buffer_atomic_cmpswap
;
6095 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6098 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6100 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6101 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6102 mubuf
->operands
[0] = Operand(rsrc
);
6103 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6104 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6105 mubuf
->operands
[3] = Operand(data
);
6106 if (return_previous
)
6107 mubuf
->definitions
[0] = Definition(dst
);
6109 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6110 mubuf
->glc
= return_previous
;
6111 mubuf
->dlc
= false; /* Not needed for atomics */
6112 mubuf
->disable_wqm
= true;
6113 mubuf
->barrier
= barrier_buffer
;
6114 ctx
->program
->needs_exact
= true;
6115 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6118 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6120 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6121 Builder
bld(ctx
->program
, ctx
->block
);
6122 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6123 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6126 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6128 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6129 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6131 if (addr
.type() == RegType::vgpr
)
6132 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6133 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6136 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6138 Builder
bld(ctx
->program
, ctx
->block
);
6139 unsigned num_components
= instr
->num_components
;
6140 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6142 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6143 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6145 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6146 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6148 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6149 bool global
= ctx
->options
->chip_class
>= GFX9
;
6151 if (ctx
->options
->chip_class
>= GFX7
) {
6153 switch (num_bytes
) {
6155 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6158 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6161 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6164 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6167 unreachable("load_global not implemented for this size.");
6170 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6171 flat
->operands
[0] = Operand(addr
);
6172 flat
->operands
[1] = Operand(s1
);
6175 flat
->barrier
= barrier_buffer
;
6177 if (dst
.type() == RegType::sgpr
) {
6178 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6179 flat
->definitions
[0] = Definition(vec
);
6180 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6181 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6183 flat
->definitions
[0] = Definition(dst
);
6184 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6186 emit_split_vector(ctx
, dst
, num_components
);
6188 assert(ctx
->options
->chip_class
== GFX6
);
6190 /* GFX6 doesn't support loading vec3, expand to vec4. */
6191 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6194 switch (num_bytes
) {
6196 op
= aco_opcode::buffer_load_dword
;
6199 op
= aco_opcode::buffer_load_dwordx2
;
6202 op
= aco_opcode::buffer_load_dwordx4
;
6205 unreachable("load_global not implemented for this size.");
6208 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6210 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6211 mubuf
->operands
[0] = Operand(rsrc
);
6212 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6213 mubuf
->operands
[2] = Operand(0u);
6217 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6218 mubuf
->disable_wqm
= false;
6219 mubuf
->barrier
= barrier_buffer
;
6220 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6223 if (dst
.size() == 3) {
6224 Temp vec
= bld
.tmp(v4
);
6225 instr
->definitions
[0] = Definition(vec
);
6226 bld
.insert(std::move(instr
));
6227 emit_split_vector(ctx
, vec
, 4);
6229 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6230 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6231 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6232 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6235 if (dst
.type() == RegType::sgpr
) {
6236 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6237 instr
->definitions
[0] = Definition(vec
);
6238 bld
.insert(std::move(instr
));
6239 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6240 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6242 instr
->definitions
[0] = Definition(dst
);
6243 bld
.insert(std::move(instr
));
6244 emit_split_vector(ctx
, dst
, num_components
);
6248 switch (num_bytes
) {
6250 op
= aco_opcode::s_load_dword
;
6253 op
= aco_opcode::s_load_dwordx2
;
6257 op
= aco_opcode::s_load_dwordx4
;
6260 unreachable("load_global not implemented for this size.");
6262 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6263 load
->operands
[0] = Operand(addr
);
6264 load
->operands
[1] = Operand(0u);
6265 load
->definitions
[0] = Definition(dst
);
6268 load
->barrier
= barrier_buffer
;
6269 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6271 if (dst
.size() == 3) {
6273 Temp vec
= bld
.tmp(s4
);
6274 load
->definitions
[0] = Definition(vec
);
6275 ctx
->block
->instructions
.emplace_back(std::move(load
));
6276 emit_split_vector(ctx
, vec
, 4);
6278 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6279 emit_extract_vector(ctx
, vec
, 0, s1
),
6280 emit_extract_vector(ctx
, vec
, 1, s1
),
6281 emit_extract_vector(ctx
, vec
, 2, s1
));
6283 ctx
->block
->instructions
.emplace_back(std::move(load
));
6288 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6290 Builder
bld(ctx
->program
, ctx
->block
);
6291 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6293 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6294 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6296 if (ctx
->options
->chip_class
>= GFX7
)
6297 addr
= as_vgpr(ctx
, addr
);
6299 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6302 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6303 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6304 /* GFX6 doesn't support storing vec3, split it. */
6305 writemask
|= 1u << (start
+ 2);
6308 unsigned num_bytes
= count
* elem_size_bytes
;
6310 Temp write_data
= data
;
6311 if (count
!= instr
->num_components
) {
6312 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6313 for (int i
= 0; i
< count
; i
++)
6314 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6315 write_data
= bld
.tmp(RegType::vgpr
, count
);
6316 vec
->definitions
[0] = Definition(write_data
);
6317 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6320 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6321 unsigned offset
= start
* elem_size_bytes
;
6323 if (ctx
->options
->chip_class
>= GFX7
) {
6324 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6325 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6326 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6327 Temp carry
= bld
.tmp(bld
.lm
);
6328 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6330 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6331 Operand(offset
), addr0
);
6332 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6334 carry
).def(1).setHint(vcc
);
6336 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6341 bool global
= ctx
->options
->chip_class
>= GFX9
;
6343 switch (num_bytes
) {
6345 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6348 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6351 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6354 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6357 unreachable("store_global not implemented for this size.");
6360 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6361 flat
->operands
[0] = Operand(addr
);
6362 flat
->operands
[1] = Operand(s1
);
6363 flat
->operands
[2] = Operand(data
);
6366 flat
->offset
= offset
;
6367 flat
->disable_wqm
= true;
6368 flat
->barrier
= barrier_buffer
;
6369 ctx
->program
->needs_exact
= true;
6370 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6372 assert(ctx
->options
->chip_class
== GFX6
);
6375 switch (num_bytes
) {
6377 op
= aco_opcode::buffer_store_dword
;
6380 op
= aco_opcode::buffer_store_dwordx2
;
6383 op
= aco_opcode::buffer_store_dwordx4
;
6386 unreachable("store_global not implemented for this size.");
6389 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6391 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6392 mubuf
->operands
[0] = Operand(rsrc
);
6393 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6394 mubuf
->operands
[2] = Operand(0u);
6395 mubuf
->operands
[3] = Operand(write_data
);
6398 mubuf
->offset
= offset
;
6399 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6400 mubuf
->disable_wqm
= true;
6401 mubuf
->barrier
= barrier_buffer
;
6402 ctx
->program
->needs_exact
= true;
6403 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6408 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6410 /* return the previous value if dest is ever used */
6411 bool return_previous
= false;
6412 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6413 return_previous
= true;
6416 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6417 return_previous
= true;
6421 Builder
bld(ctx
->program
, ctx
->block
);
6422 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6423 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6425 if (ctx
->options
->chip_class
>= GFX7
)
6426 addr
= as_vgpr(ctx
, addr
);
6428 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6429 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6430 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6432 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6434 aco_opcode op32
, op64
;
6436 if (ctx
->options
->chip_class
>= GFX7
) {
6437 bool global
= ctx
->options
->chip_class
>= GFX9
;
6438 switch (instr
->intrinsic
) {
6439 case nir_intrinsic_global_atomic_add
:
6440 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6441 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6443 case nir_intrinsic_global_atomic_imin
:
6444 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6445 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6447 case nir_intrinsic_global_atomic_umin
:
6448 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6449 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6451 case nir_intrinsic_global_atomic_imax
:
6452 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6453 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6455 case nir_intrinsic_global_atomic_umax
:
6456 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6457 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6459 case nir_intrinsic_global_atomic_and
:
6460 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6461 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6463 case nir_intrinsic_global_atomic_or
:
6464 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6465 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6467 case nir_intrinsic_global_atomic_xor
:
6468 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6469 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6471 case nir_intrinsic_global_atomic_exchange
:
6472 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6473 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6475 case nir_intrinsic_global_atomic_comp_swap
:
6476 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6477 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6480 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6483 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6484 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6485 flat
->operands
[0] = Operand(addr
);
6486 flat
->operands
[1] = Operand(s1
);
6487 flat
->operands
[2] = Operand(data
);
6488 if (return_previous
)
6489 flat
->definitions
[0] = Definition(dst
);
6490 flat
->glc
= return_previous
;
6491 flat
->dlc
= false; /* Not needed for atomics */
6493 flat
->disable_wqm
= true;
6494 flat
->barrier
= barrier_buffer
;
6495 ctx
->program
->needs_exact
= true;
6496 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6498 assert(ctx
->options
->chip_class
== GFX6
);
6500 switch (instr
->intrinsic
) {
6501 case nir_intrinsic_global_atomic_add
:
6502 op32
= aco_opcode::buffer_atomic_add
;
6503 op64
= aco_opcode::buffer_atomic_add_x2
;
6505 case nir_intrinsic_global_atomic_imin
:
6506 op32
= aco_opcode::buffer_atomic_smin
;
6507 op64
= aco_opcode::buffer_atomic_smin_x2
;
6509 case nir_intrinsic_global_atomic_umin
:
6510 op32
= aco_opcode::buffer_atomic_umin
;
6511 op64
= aco_opcode::buffer_atomic_umin_x2
;
6513 case nir_intrinsic_global_atomic_imax
:
6514 op32
= aco_opcode::buffer_atomic_smax
;
6515 op64
= aco_opcode::buffer_atomic_smax_x2
;
6517 case nir_intrinsic_global_atomic_umax
:
6518 op32
= aco_opcode::buffer_atomic_umax
;
6519 op64
= aco_opcode::buffer_atomic_umax_x2
;
6521 case nir_intrinsic_global_atomic_and
:
6522 op32
= aco_opcode::buffer_atomic_and
;
6523 op64
= aco_opcode::buffer_atomic_and_x2
;
6525 case nir_intrinsic_global_atomic_or
:
6526 op32
= aco_opcode::buffer_atomic_or
;
6527 op64
= aco_opcode::buffer_atomic_or_x2
;
6529 case nir_intrinsic_global_atomic_xor
:
6530 op32
= aco_opcode::buffer_atomic_xor
;
6531 op64
= aco_opcode::buffer_atomic_xor_x2
;
6533 case nir_intrinsic_global_atomic_exchange
:
6534 op32
= aco_opcode::buffer_atomic_swap
;
6535 op64
= aco_opcode::buffer_atomic_swap_x2
;
6537 case nir_intrinsic_global_atomic_comp_swap
:
6538 op32
= aco_opcode::buffer_atomic_cmpswap
;
6539 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6542 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6545 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6547 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6549 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6550 mubuf
->operands
[0] = Operand(rsrc
);
6551 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6552 mubuf
->operands
[2] = Operand(0u);
6553 mubuf
->operands
[3] = Operand(data
);
6554 if (return_previous
)
6555 mubuf
->definitions
[0] = Definition(dst
);
6556 mubuf
->glc
= return_previous
;
6559 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6560 mubuf
->disable_wqm
= true;
6561 mubuf
->barrier
= barrier_buffer
;
6562 ctx
->program
->needs_exact
= true;
6563 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6567 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6568 Builder
bld(ctx
->program
, ctx
->block
);
6569 switch(instr
->intrinsic
) {
6570 case nir_intrinsic_group_memory_barrier
:
6571 case nir_intrinsic_memory_barrier
:
6572 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6574 case nir_intrinsic_memory_barrier_buffer
:
6575 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6577 case nir_intrinsic_memory_barrier_image
:
6578 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6580 case nir_intrinsic_memory_barrier_tcs_patch
:
6581 case nir_intrinsic_memory_barrier_shared
:
6582 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6585 unreachable("Unimplemented memory barrier intrinsic");
6590 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6592 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6593 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6594 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6595 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6596 Builder
bld(ctx
->program
, ctx
->block
);
6598 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6599 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6600 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6603 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6605 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6606 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6607 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6608 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6609 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6611 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6612 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6615 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6617 unsigned offset
= nir_intrinsic_base(instr
);
6618 Operand m
= load_lds_size_m0(ctx
);
6619 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6620 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6622 unsigned num_operands
= 3;
6623 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6624 switch(instr
->intrinsic
) {
6625 case nir_intrinsic_shared_atomic_add
:
6626 op32
= aco_opcode::ds_add_u32
;
6627 op64
= aco_opcode::ds_add_u64
;
6628 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6629 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6631 case nir_intrinsic_shared_atomic_imin
:
6632 op32
= aco_opcode::ds_min_i32
;
6633 op64
= aco_opcode::ds_min_i64
;
6634 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6635 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6637 case nir_intrinsic_shared_atomic_umin
:
6638 op32
= aco_opcode::ds_min_u32
;
6639 op64
= aco_opcode::ds_min_u64
;
6640 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6641 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6643 case nir_intrinsic_shared_atomic_imax
:
6644 op32
= aco_opcode::ds_max_i32
;
6645 op64
= aco_opcode::ds_max_i64
;
6646 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6647 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6649 case nir_intrinsic_shared_atomic_umax
:
6650 op32
= aco_opcode::ds_max_u32
;
6651 op64
= aco_opcode::ds_max_u64
;
6652 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6653 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6655 case nir_intrinsic_shared_atomic_and
:
6656 op32
= aco_opcode::ds_and_b32
;
6657 op64
= aco_opcode::ds_and_b64
;
6658 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6659 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6661 case nir_intrinsic_shared_atomic_or
:
6662 op32
= aco_opcode::ds_or_b32
;
6663 op64
= aco_opcode::ds_or_b64
;
6664 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6665 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6667 case nir_intrinsic_shared_atomic_xor
:
6668 op32
= aco_opcode::ds_xor_b32
;
6669 op64
= aco_opcode::ds_xor_b64
;
6670 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6671 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6673 case nir_intrinsic_shared_atomic_exchange
:
6674 op32
= aco_opcode::ds_write_b32
;
6675 op64
= aco_opcode::ds_write_b64
;
6676 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6677 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6679 case nir_intrinsic_shared_atomic_comp_swap
:
6680 op32
= aco_opcode::ds_cmpst_b32
;
6681 op64
= aco_opcode::ds_cmpst_b64
;
6682 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6683 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6687 unreachable("Unhandled shared atomic intrinsic");
6690 /* return the previous value if dest is ever used */
6691 bool return_previous
= false;
6692 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6693 return_previous
= true;
6696 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6697 return_previous
= true;
6702 if (data
.size() == 1) {
6703 assert(instr
->dest
.ssa
.bit_size
== 32);
6704 op
= return_previous
? op32_rtn
: op32
;
6706 assert(instr
->dest
.ssa
.bit_size
== 64);
6707 op
= return_previous
? op64_rtn
: op64
;
6710 if (offset
> 65535) {
6711 Builder
bld(ctx
->program
, ctx
->block
);
6712 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6716 aco_ptr
<DS_instruction
> ds
;
6717 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6718 ds
->operands
[0] = Operand(address
);
6719 ds
->operands
[1] = Operand(data
);
6720 if (num_operands
== 4)
6721 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6722 ds
->operands
[num_operands
- 1] = m
;
6723 ds
->offset0
= offset
;
6724 if (return_previous
)
6725 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6726 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6729 Temp
get_scratch_resource(isel_context
*ctx
)
6731 Builder
bld(ctx
->program
, ctx
->block
);
6732 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6733 if (ctx
->stage
!= compute_cs
)
6734 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6736 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6737 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6739 if (ctx
->program
->chip_class
>= GFX10
) {
6740 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6741 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6742 S_008F0C_RESOURCE_LEVEL(1);
6743 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6744 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6745 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6748 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6749 if (ctx
->program
->chip_class
<= GFX8
)
6750 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6752 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6755 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6756 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6757 Builder
bld(ctx
->program
, ctx
->block
);
6758 Temp rsrc
= get_scratch_resource(ctx
);
6759 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6760 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6763 switch (dst
.size()) {
6765 op
= aco_opcode::buffer_load_dword
;
6768 op
= aco_opcode::buffer_load_dwordx2
;
6771 op
= aco_opcode::buffer_load_dwordx3
;
6774 op
= aco_opcode::buffer_load_dwordx4
;
6778 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6779 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6780 bld
.def(v4
), rsrc
, offset
,
6781 ctx
->program
->scratch_offset
, 0, true);
6782 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6783 aco_opcode::buffer_load_dwordx4
,
6784 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6785 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6786 emit_split_vector(ctx
, lower
, 2);
6787 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6788 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6789 if (dst
.size() == 8) {
6790 emit_split_vector(ctx
, upper
, 2);
6791 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6792 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6797 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6798 Format::PSEUDO
, dst
.size() / 2, 1)};
6799 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6800 vec
->operands
[i
] = Operand(elems
[i
]);
6801 vec
->definitions
[0] = Definition(dst
);
6802 bld
.insert(std::move(vec
));
6803 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6807 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6810 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6811 emit_split_vector(ctx
, dst
, instr
->num_components
);
6814 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6815 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6816 Builder
bld(ctx
->program
, ctx
->block
);
6817 Temp rsrc
= get_scratch_resource(ctx
);
6818 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6819 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6821 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6822 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6826 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6827 int num_bytes
= count
* elem_size_bytes
;
6829 if (num_bytes
> 16) {
6830 assert(elem_size_bytes
== 8);
6831 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6836 // TODO: check alignment of sub-dword stores
6837 // TODO: split 3 bytes. there is no store instruction for that
6840 if (count
!= instr
->num_components
) {
6841 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6842 for (int i
= 0; i
< count
; i
++) {
6843 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6844 vec
->operands
[i
] = Operand(elem
);
6846 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6847 vec
->definitions
[0] = Definition(write_data
);
6848 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6854 switch (num_bytes
) {
6856 op
= aco_opcode::buffer_store_dword
;
6859 op
= aco_opcode::buffer_store_dwordx2
;
6862 op
= aco_opcode::buffer_store_dwordx3
;
6865 op
= aco_opcode::buffer_store_dwordx4
;
6868 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6871 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6875 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6876 uint8_t log2_ps_iter_samples
;
6877 if (ctx
->program
->info
->ps
.force_persample
) {
6878 log2_ps_iter_samples
=
6879 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6881 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6884 /* The bit pattern matches that used by fixed function fragment
6886 static const unsigned ps_iter_masks
[] = {
6887 0xffff, /* not used */
6893 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6895 Builder
bld(ctx
->program
, ctx
->block
);
6897 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6898 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6899 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6900 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6901 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6902 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6905 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6906 Builder
bld(ctx
->program
, ctx
->block
);
6908 unsigned stream
= nir_intrinsic_stream_id(instr
);
6909 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6910 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6911 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6914 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6916 unsigned num_components
=
6917 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6918 assert(num_components
);
6920 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6921 unsigned stream_offset
= 0;
6922 for (unsigned i
= 0; i
< stream
; i
++) {
6923 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6924 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6927 /* Limit on the stride field for <= GFX7. */
6928 assert(stride
< (1 << 14));
6930 Temp gsvs_dwords
[4];
6931 for (unsigned i
= 0; i
< 4; i
++)
6932 gsvs_dwords
[i
] = bld
.tmp(s1
);
6933 bld
.pseudo(aco_opcode::p_split_vector
,
6934 Definition(gsvs_dwords
[0]),
6935 Definition(gsvs_dwords
[1]),
6936 Definition(gsvs_dwords
[2]),
6937 Definition(gsvs_dwords
[3]),
6940 if (stream_offset
) {
6941 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6943 Temp carry
= bld
.tmp(s1
);
6944 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6945 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6948 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6949 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6951 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6952 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6954 unsigned offset
= 0;
6955 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6956 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6959 for (unsigned j
= 0; j
< 4; j
++) {
6960 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6963 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6964 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6965 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6966 if (const_offset
>= 4096u) {
6967 if (vaddr_offset
.isUndefined())
6968 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6970 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6971 const_offset
%= 4096u;
6974 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6975 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6976 mtbuf
->operands
[1] = vaddr_offset
;
6977 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6978 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6979 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6980 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6981 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6982 mtbuf
->offset
= const_offset
;
6985 mtbuf
->barrier
= barrier_gs_data
;
6986 mtbuf
->can_reorder
= true;
6987 bld
.insert(std::move(mtbuf
));
6990 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6993 /* outputs for the next vertex are undefined and keeping them around can
6994 * create invalid IR with control flow */
6995 ctx
->outputs
.mask
[i
] = 0;
6998 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7001 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7003 Builder
bld(ctx
->program
, ctx
->block
);
7005 if (cluster_size
== 1) {
7007 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7008 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7009 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7010 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7011 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7012 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7013 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7014 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7015 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7016 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7017 //subgroupAnd(val) -> (exec & ~val) == 0
7018 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7019 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7020 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7021 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7022 //subgroupOr(val) -> (val & exec) != 0
7023 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7024 return bool_to_vector_condition(ctx
, tmp
);
7025 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7026 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7027 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7028 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7029 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7030 return bool_to_vector_condition(ctx
, tmp
);
7032 //subgroupClustered{And,Or,Xor}(val, n) ->
7033 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7034 //cluster_offset = ~(n - 1) & lane_id
7035 //cluster_mask = ((1 << n) - 1)
7036 //subgroupClusteredAnd():
7037 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7038 //subgroupClusteredOr():
7039 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7040 //subgroupClusteredXor():
7041 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7042 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7043 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7046 if (op
== nir_op_iand
)
7047 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7049 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7051 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7053 if (ctx
->program
->chip_class
<= GFX7
)
7054 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7055 else if (ctx
->program
->wave_size
== 64)
7056 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7058 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7059 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7060 if (cluster_mask
!= 0xffffffff)
7061 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7063 Definition cmp_def
= Definition();
7064 if (op
== nir_op_iand
) {
7065 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7066 } else if (op
== nir_op_ior
) {
7067 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7068 } else if (op
== nir_op_ixor
) {
7069 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7070 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7071 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7073 cmp_def
.setHint(vcc
);
7074 return cmp_def
.getTemp();
7078 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7080 Builder
bld(ctx
->program
, ctx
->block
);
7082 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7083 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7084 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7086 if (op
== nir_op_iand
)
7087 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7089 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7091 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7092 Temp lo
= lohi
.def(0).getTemp();
7093 Temp hi
= lohi
.def(1).getTemp();
7094 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7096 Definition cmp_def
= Definition();
7097 if (op
== nir_op_iand
)
7098 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7099 else if (op
== nir_op_ior
)
7100 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7101 else if (op
== nir_op_ixor
)
7102 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7103 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7104 cmp_def
.setHint(vcc
);
7105 return cmp_def
.getTemp();
7108 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7110 Builder
bld(ctx
->program
, ctx
->block
);
7112 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7113 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7114 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7115 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7116 if (op
== nir_op_iand
)
7117 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7118 else if (op
== nir_op_ior
)
7119 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7120 else if (op
== nir_op_ixor
)
7121 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7127 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7129 Builder
bld(ctx
->program
, ctx
->block
);
7130 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7131 if (src
.regClass().type() == RegType::vgpr
) {
7132 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7133 } else if (src
.regClass() == s1
) {
7134 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7135 } else if (src
.regClass() == s2
) {
7136 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7138 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7139 nir_print_instr(&instr
->instr
, stderr
);
7140 fprintf(stderr
, "\n");
7144 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7146 Builder
bld(ctx
->program
, ctx
->block
);
7147 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7148 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7149 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7151 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7152 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7153 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7154 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7157 if (ctx
->program
->chip_class
>= GFX8
) {
7158 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7159 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7160 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7161 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7162 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7163 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7165 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7166 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7167 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7168 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7169 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7170 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7171 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7172 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7173 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7174 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7177 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7178 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7179 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7180 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7181 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7182 Temp wqm1
= bld
.tmp(v1
);
7183 emit_wqm(ctx
, tmp1
, wqm1
, true);
7184 Temp wqm2
= bld
.tmp(v1
);
7185 emit_wqm(ctx
, tmp2
, wqm2
, true);
7186 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7190 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7192 Builder
bld(ctx
->program
, ctx
->block
);
7193 switch(instr
->intrinsic
) {
7194 case nir_intrinsic_load_barycentric_sample
:
7195 case nir_intrinsic_load_barycentric_pixel
:
7196 case nir_intrinsic_load_barycentric_centroid
: {
7197 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7198 Temp bary
= Temp(0, s2
);
7200 case INTERP_MODE_SMOOTH
:
7201 case INTERP_MODE_NONE
:
7202 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7203 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7204 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7205 bary
= ctx
->persp_centroid
;
7206 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7207 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7209 case INTERP_MODE_NOPERSPECTIVE
:
7210 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7211 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7212 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7213 bary
= ctx
->linear_centroid
;
7214 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7215 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7220 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7221 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7222 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7223 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7224 Operand(p1
), Operand(p2
));
7225 emit_split_vector(ctx
, dst
, 2);
7228 case nir_intrinsic_load_barycentric_model
: {
7229 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7231 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7232 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7233 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7234 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7235 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7236 Operand(p1
), Operand(p2
), Operand(p3
));
7237 emit_split_vector(ctx
, dst
, 3);
7240 case nir_intrinsic_load_barycentric_at_sample
: {
7241 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7242 switch (ctx
->options
->key
.fs
.num_samples
) {
7243 case 2: sample_pos_offset
+= 1 << 3; break;
7244 case 4: sample_pos_offset
+= 3 << 3; break;
7245 case 8: sample_pos_offset
+= 7 << 3; break;
7249 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7250 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7251 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7252 if (addr
.type() == RegType::sgpr
) {
7255 sample_pos_offset
+= const_addr
->u32
<< 3;
7256 offset
= Operand(sample_pos_offset
);
7257 } else if (ctx
->options
->chip_class
>= GFX9
) {
7258 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7260 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7261 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7264 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7265 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7267 } else if (ctx
->options
->chip_class
>= GFX9
) {
7268 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7269 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7270 } else if (ctx
->options
->chip_class
>= GFX7
) {
7271 /* addr += private_segment_buffer + sample_pos_offset */
7272 Temp tmp0
= bld
.tmp(s1
);
7273 Temp tmp1
= bld
.tmp(s1
);
7274 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7275 Definition scc_tmp
= bld
.def(s1
, scc
);
7276 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7277 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7278 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7279 Temp pck0
= bld
.tmp(v1
);
7280 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7281 tmp1
= as_vgpr(ctx
, tmp1
);
7282 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7283 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7285 /* sample_pos = flat_load_dwordx2 addr */
7286 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7288 assert(ctx
->options
->chip_class
== GFX6
);
7290 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7291 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7292 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7294 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7295 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7297 sample_pos
= bld
.tmp(v2
);
7299 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7300 load
->definitions
[0] = Definition(sample_pos
);
7301 load
->operands
[0] = Operand(rsrc
);
7302 load
->operands
[1] = Operand(addr
);
7303 load
->operands
[2] = Operand(0u);
7304 load
->offset
= sample_pos_offset
;
7306 load
->addr64
= true;
7309 load
->disable_wqm
= false;
7310 load
->barrier
= barrier_none
;
7311 load
->can_reorder
= true;
7312 ctx
->block
->instructions
.emplace_back(std::move(load
));
7315 /* sample_pos -= 0.5 */
7316 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7317 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7318 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7319 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7320 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7322 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7325 case nir_intrinsic_load_barycentric_at_offset
: {
7326 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7327 RegClass rc
= RegClass(offset
.type(), 1);
7328 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7329 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7330 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7333 case nir_intrinsic_load_front_face
: {
7334 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7335 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7338 case nir_intrinsic_load_view_index
: {
7339 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7340 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7341 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7347 case nir_intrinsic_load_layer_id
: {
7348 unsigned idx
= nir_intrinsic_base(instr
);
7349 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7350 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7353 case nir_intrinsic_load_frag_coord
: {
7354 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7357 case nir_intrinsic_load_sample_pos
: {
7358 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7359 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7360 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7361 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7362 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7365 case nir_intrinsic_load_tess_coord
:
7366 visit_load_tess_coord(ctx
, instr
);
7368 case nir_intrinsic_load_interpolated_input
:
7369 visit_load_interpolated_input(ctx
, instr
);
7371 case nir_intrinsic_store_output
:
7372 visit_store_output(ctx
, instr
);
7374 case nir_intrinsic_load_input
:
7375 case nir_intrinsic_load_input_vertex
:
7376 visit_load_input(ctx
, instr
);
7378 case nir_intrinsic_load_output
:
7379 visit_load_output(ctx
, instr
);
7381 case nir_intrinsic_load_per_vertex_input
:
7382 visit_load_per_vertex_input(ctx
, instr
);
7384 case nir_intrinsic_load_per_vertex_output
:
7385 visit_load_per_vertex_output(ctx
, instr
);
7387 case nir_intrinsic_store_per_vertex_output
:
7388 visit_store_per_vertex_output(ctx
, instr
);
7390 case nir_intrinsic_load_ubo
:
7391 visit_load_ubo(ctx
, instr
);
7393 case nir_intrinsic_load_push_constant
:
7394 visit_load_push_constant(ctx
, instr
);
7396 case nir_intrinsic_load_constant
:
7397 visit_load_constant(ctx
, instr
);
7399 case nir_intrinsic_vulkan_resource_index
:
7400 visit_load_resource(ctx
, instr
);
7402 case nir_intrinsic_discard
:
7403 visit_discard(ctx
, instr
);
7405 case nir_intrinsic_discard_if
:
7406 visit_discard_if(ctx
, instr
);
7408 case nir_intrinsic_load_shared
:
7409 visit_load_shared(ctx
, instr
);
7411 case nir_intrinsic_store_shared
:
7412 visit_store_shared(ctx
, instr
);
7414 case nir_intrinsic_shared_atomic_add
:
7415 case nir_intrinsic_shared_atomic_imin
:
7416 case nir_intrinsic_shared_atomic_umin
:
7417 case nir_intrinsic_shared_atomic_imax
:
7418 case nir_intrinsic_shared_atomic_umax
:
7419 case nir_intrinsic_shared_atomic_and
:
7420 case nir_intrinsic_shared_atomic_or
:
7421 case nir_intrinsic_shared_atomic_xor
:
7422 case nir_intrinsic_shared_atomic_exchange
:
7423 case nir_intrinsic_shared_atomic_comp_swap
:
7424 visit_shared_atomic(ctx
, instr
);
7426 case nir_intrinsic_image_deref_load
:
7427 visit_image_load(ctx
, instr
);
7429 case nir_intrinsic_image_deref_store
:
7430 visit_image_store(ctx
, instr
);
7432 case nir_intrinsic_image_deref_atomic_add
:
7433 case nir_intrinsic_image_deref_atomic_umin
:
7434 case nir_intrinsic_image_deref_atomic_imin
:
7435 case nir_intrinsic_image_deref_atomic_umax
:
7436 case nir_intrinsic_image_deref_atomic_imax
:
7437 case nir_intrinsic_image_deref_atomic_and
:
7438 case nir_intrinsic_image_deref_atomic_or
:
7439 case nir_intrinsic_image_deref_atomic_xor
:
7440 case nir_intrinsic_image_deref_atomic_exchange
:
7441 case nir_intrinsic_image_deref_atomic_comp_swap
:
7442 visit_image_atomic(ctx
, instr
);
7444 case nir_intrinsic_image_deref_size
:
7445 visit_image_size(ctx
, instr
);
7447 case nir_intrinsic_load_ssbo
:
7448 visit_load_ssbo(ctx
, instr
);
7450 case nir_intrinsic_store_ssbo
:
7451 visit_store_ssbo(ctx
, instr
);
7453 case nir_intrinsic_load_global
:
7454 visit_load_global(ctx
, instr
);
7456 case nir_intrinsic_store_global
:
7457 visit_store_global(ctx
, instr
);
7459 case nir_intrinsic_global_atomic_add
:
7460 case nir_intrinsic_global_atomic_imin
:
7461 case nir_intrinsic_global_atomic_umin
:
7462 case nir_intrinsic_global_atomic_imax
:
7463 case nir_intrinsic_global_atomic_umax
:
7464 case nir_intrinsic_global_atomic_and
:
7465 case nir_intrinsic_global_atomic_or
:
7466 case nir_intrinsic_global_atomic_xor
:
7467 case nir_intrinsic_global_atomic_exchange
:
7468 case nir_intrinsic_global_atomic_comp_swap
:
7469 visit_global_atomic(ctx
, instr
);
7471 case nir_intrinsic_ssbo_atomic_add
:
7472 case nir_intrinsic_ssbo_atomic_imin
:
7473 case nir_intrinsic_ssbo_atomic_umin
:
7474 case nir_intrinsic_ssbo_atomic_imax
:
7475 case nir_intrinsic_ssbo_atomic_umax
:
7476 case nir_intrinsic_ssbo_atomic_and
:
7477 case nir_intrinsic_ssbo_atomic_or
:
7478 case nir_intrinsic_ssbo_atomic_xor
:
7479 case nir_intrinsic_ssbo_atomic_exchange
:
7480 case nir_intrinsic_ssbo_atomic_comp_swap
:
7481 visit_atomic_ssbo(ctx
, instr
);
7483 case nir_intrinsic_load_scratch
:
7484 visit_load_scratch(ctx
, instr
);
7486 case nir_intrinsic_store_scratch
:
7487 visit_store_scratch(ctx
, instr
);
7489 case nir_intrinsic_get_buffer_size
:
7490 visit_get_buffer_size(ctx
, instr
);
7492 case nir_intrinsic_control_barrier
: {
7493 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7494 /* GFX6 only (thanks to a hw bug workaround):
7495 * The real barrier instruction isn’t needed, because an entire patch
7496 * always fits into a single wave.
7501 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7502 bld
.sopp(aco_opcode::s_barrier
);
7506 case nir_intrinsic_memory_barrier_tcs_patch
:
7507 case nir_intrinsic_group_memory_barrier
:
7508 case nir_intrinsic_memory_barrier
:
7509 case nir_intrinsic_memory_barrier_buffer
:
7510 case nir_intrinsic_memory_barrier_image
:
7511 case nir_intrinsic_memory_barrier_shared
:
7512 emit_memory_barrier(ctx
, instr
);
7514 case nir_intrinsic_load_num_work_groups
: {
7515 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7516 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7517 emit_split_vector(ctx
, dst
, 3);
7520 case nir_intrinsic_load_local_invocation_id
: {
7521 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7522 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7523 emit_split_vector(ctx
, dst
, 3);
7526 case nir_intrinsic_load_work_group_id
: {
7527 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7528 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7529 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7530 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7531 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7532 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7533 emit_split_vector(ctx
, dst
, 3);
7536 case nir_intrinsic_load_local_invocation_index
: {
7537 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7539 /* The tg_size bits [6:11] contain the subgroup id,
7540 * we need this multiplied by the wave size, and then OR the thread id to it.
7542 if (ctx
->program
->wave_size
== 64) {
7543 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7544 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7545 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7546 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7548 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7549 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7550 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7551 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7555 case nir_intrinsic_load_subgroup_id
: {
7556 if (ctx
->stage
== compute_cs
) {
7557 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7558 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7560 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7564 case nir_intrinsic_load_subgroup_invocation
: {
7565 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7568 case nir_intrinsic_load_num_subgroups
: {
7569 if (ctx
->stage
== compute_cs
)
7570 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7571 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7573 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7576 case nir_intrinsic_ballot
: {
7577 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7578 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7579 Definition tmp
= bld
.def(dst
.regClass());
7580 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7581 if (instr
->src
[0].ssa
->bit_size
== 1) {
7582 assert(src
.regClass() == bld
.lm
);
7583 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7584 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7585 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7586 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7587 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7589 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7590 nir_print_instr(&instr
->instr
, stderr
);
7591 fprintf(stderr
, "\n");
7593 if (dst
.size() != bld
.lm
.size()) {
7594 /* Wave32 with ballot size set to 64 */
7595 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7597 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7600 case nir_intrinsic_shuffle
:
7601 case nir_intrinsic_read_invocation
: {
7602 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7603 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7604 emit_uniform_subgroup(ctx
, instr
, src
);
7606 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7607 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7608 tid
= bld
.as_uniform(tid
);
7609 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7610 if (src
.regClass() == v1
) {
7611 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7612 } else if (src
.regClass() == v2
) {
7613 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7615 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7616 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7617 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7618 emit_split_vector(ctx
, dst
, 2);
7619 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7620 assert(src
.regClass() == bld
.lm
);
7621 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7622 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7623 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7624 assert(src
.regClass() == bld
.lm
);
7626 if (ctx
->program
->chip_class
<= GFX7
)
7627 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7628 else if (ctx
->program
->wave_size
== 64)
7629 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7631 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7632 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7633 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7634 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7636 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7637 nir_print_instr(&instr
->instr
, stderr
);
7638 fprintf(stderr
, "\n");
7643 case nir_intrinsic_load_sample_id
: {
7644 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7645 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7648 case nir_intrinsic_load_sample_mask_in
: {
7649 visit_load_sample_mask_in(ctx
, instr
);
7652 case nir_intrinsic_read_first_invocation
: {
7653 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7654 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7655 if (src
.regClass() == v1
) {
7657 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7659 } else if (src
.regClass() == v2
) {
7660 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7661 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7662 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7663 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7664 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7665 emit_split_vector(ctx
, dst
, 2);
7666 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7667 assert(src
.regClass() == bld
.lm
);
7668 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7669 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7670 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7671 } else if (src
.regClass() == s1
) {
7672 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7673 } else if (src
.regClass() == s2
) {
7674 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7676 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7677 nir_print_instr(&instr
->instr
, stderr
);
7678 fprintf(stderr
, "\n");
7682 case nir_intrinsic_vote_all
: {
7683 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7684 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7685 assert(src
.regClass() == bld
.lm
);
7686 assert(dst
.regClass() == bld
.lm
);
7688 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7689 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7690 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7693 case nir_intrinsic_vote_any
: {
7694 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7695 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7696 assert(src
.regClass() == bld
.lm
);
7697 assert(dst
.regClass() == bld
.lm
);
7699 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7700 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7703 case nir_intrinsic_reduce
:
7704 case nir_intrinsic_inclusive_scan
:
7705 case nir_intrinsic_exclusive_scan
: {
7706 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7707 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7708 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7709 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7710 nir_intrinsic_cluster_size(instr
) : 0;
7711 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7713 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7714 emit_uniform_subgroup(ctx
, instr
, src
);
7715 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7716 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7718 else if (op
== nir_op_iadd
)
7720 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7722 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7724 switch (instr
->intrinsic
) {
7725 case nir_intrinsic_reduce
:
7726 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7728 case nir_intrinsic_exclusive_scan
:
7729 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7731 case nir_intrinsic_inclusive_scan
:
7732 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7737 } else if (cluster_size
== 1) {
7738 bld
.copy(Definition(dst
), src
);
7740 src
= as_vgpr(ctx
, src
);
7744 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7759 unreachable("unknown reduction op");
7764 switch (instr
->intrinsic
) {
7765 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7766 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7767 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7769 unreachable("unknown reduce intrinsic");
7772 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7773 reduce
->operands
[0] = Operand(src
);
7774 // filled in by aco_reduce_assign.cpp, used internally as part of the
7776 assert(dst
.size() == 1 || dst
.size() == 2);
7777 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7778 reduce
->operands
[2] = Operand(v1
.as_linear());
7780 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7781 reduce
->definitions
[0] = Definition(tmp_dst
);
7782 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7783 reduce
->definitions
[2] = Definition();
7784 reduce
->definitions
[3] = Definition(scc
, s1
);
7785 reduce
->definitions
[4] = Definition();
7786 reduce
->reduce_op
= reduce_op
;
7787 reduce
->cluster_size
= cluster_size
;
7788 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7790 emit_wqm(ctx
, tmp_dst
, dst
);
7794 case nir_intrinsic_quad_broadcast
: {
7795 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7796 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7797 emit_uniform_subgroup(ctx
, instr
, src
);
7799 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7800 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7801 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7803 if (instr
->dest
.ssa
.bit_size
== 1) {
7804 assert(src
.regClass() == bld
.lm
);
7805 assert(dst
.regClass() == bld
.lm
);
7806 uint32_t half_mask
= 0x11111111u
<< lane
;
7807 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7808 Temp tmp
= bld
.tmp(bld
.lm
);
7809 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7810 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7811 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7812 emit_wqm(ctx
, tmp
, dst
);
7813 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7814 if (ctx
->program
->chip_class
>= GFX8
)
7815 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7817 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7818 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7819 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7820 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7821 if (ctx
->program
->chip_class
>= GFX8
) {
7822 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7823 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7825 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7826 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7828 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7829 emit_split_vector(ctx
, dst
, 2);
7831 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7832 nir_print_instr(&instr
->instr
, stderr
);
7833 fprintf(stderr
, "\n");
7838 case nir_intrinsic_quad_swap_horizontal
:
7839 case nir_intrinsic_quad_swap_vertical
:
7840 case nir_intrinsic_quad_swap_diagonal
:
7841 case nir_intrinsic_quad_swizzle_amd
: {
7842 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7843 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7844 emit_uniform_subgroup(ctx
, instr
, src
);
7847 uint16_t dpp_ctrl
= 0;
7848 switch (instr
->intrinsic
) {
7849 case nir_intrinsic_quad_swap_horizontal
:
7850 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7852 case nir_intrinsic_quad_swap_vertical
:
7853 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7855 case nir_intrinsic_quad_swap_diagonal
:
7856 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7858 case nir_intrinsic_quad_swizzle_amd
:
7859 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7864 if (ctx
->program
->chip_class
< GFX8
)
7865 dpp_ctrl
|= (1 << 15);
7867 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7868 if (instr
->dest
.ssa
.bit_size
== 1) {
7869 assert(src
.regClass() == bld
.lm
);
7870 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7871 if (ctx
->program
->chip_class
>= GFX8
)
7872 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7874 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7875 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7876 emit_wqm(ctx
, tmp
, dst
);
7877 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7879 if (ctx
->program
->chip_class
>= GFX8
)
7880 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7882 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7883 emit_wqm(ctx
, tmp
, dst
);
7884 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7885 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7886 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7887 if (ctx
->program
->chip_class
>= GFX8
) {
7888 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7889 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7891 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7892 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7894 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7895 emit_split_vector(ctx
, dst
, 2);
7897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7898 nir_print_instr(&instr
->instr
, stderr
);
7899 fprintf(stderr
, "\n");
7903 case nir_intrinsic_masked_swizzle_amd
: {
7904 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7905 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7906 emit_uniform_subgroup(ctx
, instr
, src
);
7909 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7910 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7911 if (dst
.regClass() == v1
) {
7913 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7915 } else if (dst
.regClass() == v2
) {
7916 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7917 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7918 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7919 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7920 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7921 emit_split_vector(ctx
, dst
, 2);
7923 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7924 nir_print_instr(&instr
->instr
, stderr
);
7925 fprintf(stderr
, "\n");
7929 case nir_intrinsic_write_invocation_amd
: {
7930 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7931 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7932 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7933 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7934 if (dst
.regClass() == v1
) {
7935 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7936 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7937 } else if (dst
.regClass() == v2
) {
7938 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7939 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7941 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7942 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7943 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7944 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7945 emit_split_vector(ctx
, dst
, 2);
7947 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7948 nir_print_instr(&instr
->instr
, stderr
);
7949 fprintf(stderr
, "\n");
7953 case nir_intrinsic_mbcnt_amd
: {
7954 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7955 RegClass rc
= RegClass(src
.type(), 1);
7956 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7957 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7958 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7959 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7960 emit_wqm(ctx
, wqm_tmp
, dst
);
7963 case nir_intrinsic_load_helper_invocation
: {
7964 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7965 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7966 ctx
->block
->kind
|= block_kind_needs_lowering
;
7967 ctx
->program
->needs_exact
= true;
7970 case nir_intrinsic_is_helper_invocation
: {
7971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7972 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7973 ctx
->block
->kind
|= block_kind_needs_lowering
;
7974 ctx
->program
->needs_exact
= true;
7977 case nir_intrinsic_demote
:
7978 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7980 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7981 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7982 ctx
->block
->kind
|= block_kind_uses_demote
;
7983 ctx
->program
->needs_exact
= true;
7985 case nir_intrinsic_demote_if
: {
7986 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7987 assert(src
.regClass() == bld
.lm
);
7988 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7989 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7991 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7992 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7993 ctx
->block
->kind
|= block_kind_uses_demote
;
7994 ctx
->program
->needs_exact
= true;
7997 case nir_intrinsic_first_invocation
: {
7998 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7999 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8002 case nir_intrinsic_shader_clock
:
8003 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8004 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8006 case nir_intrinsic_load_vertex_id_zero_base
: {
8007 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8008 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8011 case nir_intrinsic_load_first_vertex
: {
8012 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8013 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8016 case nir_intrinsic_load_base_instance
: {
8017 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8018 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8021 case nir_intrinsic_load_instance_id
: {
8022 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8023 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8026 case nir_intrinsic_load_draw_id
: {
8027 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8028 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8031 case nir_intrinsic_load_invocation_id
: {
8032 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8034 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8035 if (ctx
->options
->chip_class
>= GFX10
)
8036 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8038 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8039 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8040 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8041 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8043 unreachable("Unsupported stage for load_invocation_id");
8048 case nir_intrinsic_load_primitive_id
: {
8049 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8051 switch (ctx
->shader
->info
.stage
) {
8052 case MESA_SHADER_GEOMETRY
:
8053 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8055 case MESA_SHADER_TESS_CTRL
:
8056 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8058 case MESA_SHADER_TESS_EVAL
:
8059 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8062 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8067 case nir_intrinsic_load_patch_vertices_in
: {
8068 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8069 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8071 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8072 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8075 case nir_intrinsic_emit_vertex_with_counter
: {
8076 visit_emit_vertex_with_counter(ctx
, instr
);
8079 case nir_intrinsic_end_primitive_with_counter
: {
8080 unsigned stream
= nir_intrinsic_stream_id(instr
);
8081 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8084 case nir_intrinsic_set_vertex_count
: {
8085 /* unused, the HW keeps track of this for us */
8089 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8090 nir_print_instr(&instr
->instr
, stderr
);
8091 fprintf(stderr
, "\n");
8099 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8100 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8101 enum glsl_base_type
*stype
)
8103 nir_deref_instr
*texture_deref_instr
= NULL
;
8104 nir_deref_instr
*sampler_deref_instr
= NULL
;
8107 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8108 switch (instr
->src
[i
].src_type
) {
8109 case nir_tex_src_texture_deref
:
8110 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8112 case nir_tex_src_sampler_deref
:
8113 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8115 case nir_tex_src_plane
:
8116 plane
= nir_src_as_int(instr
->src
[i
].src
);
8123 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8125 if (!sampler_deref_instr
)
8126 sampler_deref_instr
= texture_deref_instr
;
8129 assert(instr
->op
!= nir_texop_txf_ms
&&
8130 instr
->op
!= nir_texop_samples_identical
);
8131 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8132 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8133 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8134 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8135 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8136 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8138 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8141 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8143 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8144 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8145 Builder
bld(ctx
->program
, ctx
->block
);
8147 /* to avoid unnecessary moves, we split and recombine sampler and image */
8148 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8149 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8150 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8151 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8152 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8153 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8154 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8155 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8157 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8158 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8159 img
[0], img
[1], img
[2], img
[3],
8160 img
[4], img
[5], img
[6], img
[7]);
8161 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8162 samp
[0], samp
[1], samp
[2], samp
[3]);
8165 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8166 instr
->op
== nir_texop_samples_identical
))
8167 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8170 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8171 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8173 Builder
bld(ctx
->program
, ctx
->block
);
8175 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8176 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8177 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8179 Operand
neg_one(0xbf800000u
);
8180 Operand
one(0x3f800000u
);
8181 Operand
two(0x40000000u
);
8182 Operand
four(0x40800000u
);
8184 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8185 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8186 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8188 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8189 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8190 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8191 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8194 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8195 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8196 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8198 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8201 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8202 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8203 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8206 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8207 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8209 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8210 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8213 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8215 Builder
bld(ctx
->program
, ctx
->block
);
8216 Temp ma
, tc
, sc
, id
;
8219 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8221 // see comment in ac_prepare_cube_coords()
8222 if (ctx
->options
->chip_class
<= GFX8
)
8223 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8226 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8228 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8229 vop3a
->operands
[0] = Operand(ma
);
8230 vop3a
->abs
[0] = true;
8231 Temp invma
= bld
.tmp(v1
);
8232 vop3a
->definitions
[0] = Definition(invma
);
8233 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8235 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8237 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8239 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8241 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8243 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8246 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8247 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8249 for (unsigned i
= 0; i
< 2; i
++) {
8250 // see comment in ac_prepare_cube_coords()
8252 Temp deriv_sc
, deriv_tc
;
8253 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8254 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8256 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8258 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8259 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8260 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8261 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8262 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8263 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8264 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8267 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8268 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8272 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8279 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8281 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8283 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8284 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8287 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8288 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8289 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8293 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8295 Builder
bld(ctx
->program
, ctx
->block
);
8296 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8297 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8298 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8299 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8300 std::vector
<Temp
> coords
;
8301 std::vector
<Temp
> derivs
;
8302 nir_const_value
*sample_index_cv
= NULL
;
8303 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8304 enum glsl_base_type stype
;
8305 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8307 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8308 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8309 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8310 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8312 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8313 switch (instr
->src
[i
].src_type
) {
8314 case nir_tex_src_coord
: {
8315 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8316 for (unsigned i
= 0; i
< coord
.size(); i
++)
8317 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8320 case nir_tex_src_bias
:
8321 if (instr
->op
== nir_texop_txb
) {
8322 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8326 case nir_tex_src_lod
: {
8327 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8329 if (val
&& val
->f32
<= 0.0) {
8332 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8337 case nir_tex_src_comparator
:
8338 if (instr
->is_shadow
) {
8339 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8343 case nir_tex_src_offset
:
8344 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8345 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8348 case nir_tex_src_ddx
:
8349 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8352 case nir_tex_src_ddy
:
8353 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8356 case nir_tex_src_ms_index
:
8357 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8358 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8359 has_sample_index
= true;
8361 case nir_tex_src_texture_offset
:
8362 case nir_tex_src_sampler_offset
:
8368 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8369 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8371 if (instr
->op
== nir_texop_texture_samples
) {
8372 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8374 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8375 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8376 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8377 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8379 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8380 samples
, Operand(1u), bld
.scc(is_msaa
));
8384 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8385 aco_ptr
<Instruction
> tmp_instr
;
8386 Temp acc
, pack
= Temp();
8388 uint32_t pack_const
= 0;
8389 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8390 if (!const_offset
[i
])
8392 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8395 if (offset
.type() == RegType::sgpr
) {
8396 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8397 if (const_offset
[i
])
8400 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8401 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8404 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8407 if (pack
== Temp()) {
8410 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8414 if (pack_const
&& pack
!= Temp())
8415 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8417 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8418 if (const_offset
[i
])
8421 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8422 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8425 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8428 if (pack
== Temp()) {
8431 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8435 if (pack_const
&& pack
!= Temp())
8436 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8438 if (pack_const
&& pack
== Temp())
8439 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8440 else if (pack
== Temp())
8446 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8447 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8449 /* pack derivatives */
8450 if (has_ddx
|| has_ddy
) {
8451 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8452 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8453 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8454 derivs
= {ddy
, zero
, ddy
, zero
};
8456 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8457 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8458 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8459 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8464 if (instr
->coord_components
> 1 &&
8465 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8467 instr
->op
!= nir_texop_txf
)
8468 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8470 if (instr
->coord_components
> 2 &&
8471 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8472 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8473 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8474 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8476 instr
->op
!= nir_texop_txf
&&
8477 instr
->op
!= nir_texop_txf_ms
&&
8478 instr
->op
!= nir_texop_fragment_fetch
&&
8479 instr
->op
!= nir_texop_fragment_mask_fetch
)
8480 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8482 if (ctx
->options
->chip_class
== GFX9
&&
8483 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8484 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8485 assert(coords
.size() > 0 && coords
.size() < 3);
8487 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8488 Operand((uint32_t) 0) :
8489 Operand((uint32_t) 0x3f000000)));
8492 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8494 if (instr
->op
== nir_texop_samples_identical
)
8495 resource
= fmask_ptr
;
8497 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8498 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8499 instr
->op
!= nir_texop_txs
&&
8500 instr
->op
!= nir_texop_fragment_fetch
&&
8501 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8502 assert(has_sample_index
);
8503 Operand
op(sample_index
);
8504 if (sample_index_cv
)
8505 op
= Operand(sample_index_cv
->u32
);
8506 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8509 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8510 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8511 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8512 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8517 /* Build tex instruction */
8518 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8519 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8520 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8522 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8525 /* gather4 selects the component by dmask and always returns vec4 */
8526 if (instr
->op
== nir_texop_tg4
) {
8527 assert(instr
->dest
.ssa
.num_components
== 4);
8528 if (instr
->is_shadow
)
8531 dmask
= 1 << instr
->component
;
8532 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8533 tmp_dst
= bld
.tmp(v4
);
8534 } else if (instr
->op
== nir_texop_samples_identical
) {
8535 tmp_dst
= bld
.tmp(v1
);
8536 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8537 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8540 aco_ptr
<MIMG_instruction
> tex
;
8541 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8543 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8545 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8546 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8549 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8550 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8552 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8553 tex
->operands
[0] = Operand(resource
);
8554 tex
->operands
[1] = Operand(s4
); /* no sampler */
8555 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8556 if (ctx
->options
->chip_class
== GFX9
&&
8557 instr
->op
== nir_texop_txs
&&
8558 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8560 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8561 } else if (instr
->op
== nir_texop_query_levels
) {
8562 tex
->dmask
= 1 << 3;
8567 tex
->definitions
[0] = Definition(tmp_dst
);
8569 tex
->can_reorder
= true;
8570 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8573 /* divide 3rd value by 6 by multiplying with magic number */
8574 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8575 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8576 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8577 assert(instr
->dest
.ssa
.num_components
== 3);
8578 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8579 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8580 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8581 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8586 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8590 Temp tg4_compare_cube_wa64
= Temp();
8592 if (tg4_integer_workarounds
) {
8593 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8594 tex
->operands
[0] = Operand(resource
);
8595 tex
->operands
[1] = Operand(s4
); /* no sampler */
8596 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8600 Temp size
= bld
.tmp(v2
);
8601 tex
->definitions
[0] = Definition(size
);
8602 tex
->can_reorder
= true;
8603 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8604 emit_split_vector(ctx
, size
, size
.size());
8607 for (unsigned i
= 0; i
< 2; i
++) {
8608 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8609 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8610 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8611 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8614 Temp new_coords
[2] = {
8615 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8616 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8619 if (tg4_integer_cube_workaround
) {
8620 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8621 Temp desc
[resource
.size()];
8622 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8623 Format::PSEUDO
, 1, resource
.size())};
8624 split
->operands
[0] = Operand(resource
);
8625 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8626 desc
[i
] = bld
.tmp(s1
);
8627 split
->definitions
[i
] = Definition(desc
[i
]);
8629 ctx
->block
->instructions
.emplace_back(std::move(split
));
8631 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8632 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8633 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8636 if (stype
== GLSL_TYPE_UINT
) {
8637 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8638 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8639 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8640 bld
.scc(compare_cube_wa
));
8642 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8643 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8644 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8645 bld
.scc(compare_cube_wa
));
8647 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8648 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8650 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8652 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8653 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8654 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8656 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8657 Format::PSEUDO
, resource
.size(), 1)};
8658 for (unsigned i
= 0; i
< resource
.size(); i
++)
8659 vec
->operands
[i
] = Operand(desc
[i
]);
8660 resource
= bld
.tmp(resource
.regClass());
8661 vec
->definitions
[0] = Definition(resource
);
8662 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8664 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8665 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8666 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8667 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8669 coords
[0] = new_coords
[0];
8670 coords
[1] = new_coords
[1];
8673 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8674 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8676 assert(coords
.size() == 1);
8677 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8681 op
= aco_opcode::buffer_load_format_x
; break;
8683 op
= aco_opcode::buffer_load_format_xy
; break;
8685 op
= aco_opcode::buffer_load_format_xyz
; break;
8687 op
= aco_opcode::buffer_load_format_xyzw
; break;
8689 unreachable("Tex instruction loads more than 4 components.");
8692 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8693 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8696 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8698 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8699 mubuf
->operands
[0] = Operand(resource
);
8700 mubuf
->operands
[1] = Operand(coords
[0]);
8701 mubuf
->operands
[2] = Operand((uint32_t) 0);
8702 mubuf
->definitions
[0] = Definition(tmp_dst
);
8703 mubuf
->idxen
= true;
8704 mubuf
->can_reorder
= true;
8705 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8707 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8711 /* gather MIMG address components */
8712 std::vector
<Temp
> args
;
8714 args
.emplace_back(offset
);
8716 args
.emplace_back(bias
);
8718 args
.emplace_back(compare
);
8720 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8722 args
.insert(args
.end(), coords
.begin(), coords
.end());
8723 if (has_sample_index
)
8724 args
.emplace_back(sample_index
);
8726 args
.emplace_back(lod
);
8728 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8729 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8730 vec
->definitions
[0] = Definition(arg
);
8731 for (unsigned i
= 0; i
< args
.size(); i
++)
8732 vec
->operands
[i
] = Operand(args
[i
]);
8733 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8736 if (instr
->op
== nir_texop_txf
||
8737 instr
->op
== nir_texop_txf_ms
||
8738 instr
->op
== nir_texop_samples_identical
||
8739 instr
->op
== nir_texop_fragment_fetch
||
8740 instr
->op
== nir_texop_fragment_mask_fetch
) {
8741 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8742 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8743 tex
->operands
[0] = Operand(resource
);
8744 tex
->operands
[1] = Operand(s4
); /* no sampler */
8745 tex
->operands
[2] = Operand(arg
);
8750 tex
->definitions
[0] = Definition(tmp_dst
);
8751 tex
->can_reorder
= true;
8752 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8754 if (instr
->op
== nir_texop_samples_identical
) {
8755 assert(dmask
== 1 && dst
.regClass() == v1
);
8756 assert(dst
.id() != tmp_dst
.id());
8758 Temp tmp
= bld
.tmp(bld
.lm
);
8759 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8760 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8763 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8768 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8769 aco_opcode opcode
= aco_opcode::image_sample
;
8770 if (has_offset
) { /* image_sample_*_o */
8772 opcode
= aco_opcode::image_sample_c_o
;
8774 opcode
= aco_opcode::image_sample_c_d_o
;
8776 opcode
= aco_opcode::image_sample_c_b_o
;
8778 opcode
= aco_opcode::image_sample_c_lz_o
;
8780 opcode
= aco_opcode::image_sample_c_l_o
;
8782 opcode
= aco_opcode::image_sample_o
;
8784 opcode
= aco_opcode::image_sample_d_o
;
8786 opcode
= aco_opcode::image_sample_b_o
;
8788 opcode
= aco_opcode::image_sample_lz_o
;
8790 opcode
= aco_opcode::image_sample_l_o
;
8792 } else { /* no offset */
8794 opcode
= aco_opcode::image_sample_c
;
8796 opcode
= aco_opcode::image_sample_c_d
;
8798 opcode
= aco_opcode::image_sample_c_b
;
8800 opcode
= aco_opcode::image_sample_c_lz
;
8802 opcode
= aco_opcode::image_sample_c_l
;
8804 opcode
= aco_opcode::image_sample
;
8806 opcode
= aco_opcode::image_sample_d
;
8808 opcode
= aco_opcode::image_sample_b
;
8810 opcode
= aco_opcode::image_sample_lz
;
8812 opcode
= aco_opcode::image_sample_l
;
8816 if (instr
->op
== nir_texop_tg4
) {
8818 opcode
= aco_opcode::image_gather4_lz_o
;
8820 opcode
= aco_opcode::image_gather4_c_lz_o
;
8822 opcode
= aco_opcode::image_gather4_lz
;
8824 opcode
= aco_opcode::image_gather4_c_lz
;
8826 } else if (instr
->op
== nir_texop_lod
) {
8827 opcode
= aco_opcode::image_get_lod
;
8830 /* we don't need the bias, sample index, compare value or offset to be
8831 * computed in WQM but if the p_create_vector copies the coordinates, then it
8832 * needs to be in WQM */
8833 if (ctx
->stage
== fragment_fs
&&
8834 !has_derivs
&& !has_lod
&& !level_zero
&&
8835 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8836 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8837 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8839 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8840 tex
->operands
[0] = Operand(resource
);
8841 tex
->operands
[1] = Operand(sampler
);
8842 tex
->operands
[2] = Operand(arg
);
8846 tex
->definitions
[0] = Definition(tmp_dst
);
8847 tex
->can_reorder
= true;
8848 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8850 if (tg4_integer_cube_workaround
) {
8851 assert(tmp_dst
.id() != dst
.id());
8852 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8854 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8856 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8857 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8859 if (stype
== GLSL_TYPE_UINT
)
8860 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8862 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8863 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8865 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8866 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8867 val
[0], val
[1], val
[2], val
[3]);
8869 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8870 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8875 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8877 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8878 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8879 return Operand(tmp
.regClass());
8881 return Operand(tmp
);
8884 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8886 aco_ptr
<Pseudo_instruction
> phi
;
8887 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8888 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8890 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8891 logical
|= ctx
->block
->kind
& block_kind_merge
;
8892 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8894 /* we want a sorted list of sources, since the predecessor list is also sorted */
8895 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8896 nir_foreach_phi_src(src
, instr
)
8897 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8899 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8900 unsigned num_operands
= 0;
8901 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8902 unsigned num_defined
= 0;
8903 unsigned cur_pred_idx
= 0;
8904 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8905 if (cur_pred_idx
< preds
.size()) {
8906 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8907 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8908 unsigned skipped
= 0;
8909 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8911 if (cur_pred_idx
+ skipped
< preds
.size()) {
8912 for (unsigned i
= 0; i
< skipped
; i
++)
8913 operands
[num_operands
++] = Operand(dst
.regClass());
8914 cur_pred_idx
+= skipped
;
8919 /* Handle missing predecessors at the end. This shouldn't happen with loop
8920 * headers and we can't ignore these sources for loop header phis. */
8921 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8924 Operand op
= get_phi_operand(ctx
, src
.second
);
8925 operands
[num_operands
++] = op
;
8926 num_defined
+= !op
.isUndefined();
8928 /* handle block_kind_continue_or_break at loop exit blocks */
8929 while (cur_pred_idx
++ < preds
.size())
8930 operands
[num_operands
++] = Operand(dst
.regClass());
8932 /* If the loop ends with a break, still add a linear continue edge in case
8933 * that break is divergent or continue_or_break is used. We'll either remove
8934 * this operand later in visit_loop() if it's not necessary or replace the
8935 * undef with something correct. */
8936 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8937 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8938 nir_block
*last
= nir_loop_last_block(loop
);
8939 if (last
->successors
[0] != instr
->instr
.block
)
8940 operands
[num_operands
++] = Operand(RegClass());
8943 if (num_defined
== 0) {
8944 Builder
bld(ctx
->program
, ctx
->block
);
8945 if (dst
.regClass() == s1
) {
8946 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8947 } else if (dst
.regClass() == v1
) {
8948 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8950 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8951 for (unsigned i
= 0; i
< dst
.size(); i
++)
8952 vec
->operands
[i
] = Operand(0u);
8953 vec
->definitions
[0] = Definition(dst
);
8954 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8959 /* we can use a linear phi in some cases if one src is undef */
8960 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8961 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8963 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8964 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8965 assert(invert
->kind
& block_kind_invert
);
8967 unsigned then_block
= invert
->linear_preds
[0];
8969 Block
* insert_block
= NULL
;
8970 for (unsigned i
= 0; i
< num_operands
; i
++) {
8971 Operand op
= operands
[i
];
8972 if (op
.isUndefined())
8974 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8975 phi
->operands
[0] = op
;
8978 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8979 phi
->operands
[1] = Operand(dst
.regClass());
8980 phi
->definitions
[0] = Definition(dst
);
8981 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8985 /* try to scalarize vector phis */
8986 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8987 // TODO: scalarize linear phis on divergent ifs
8988 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8989 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8990 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8991 Operand src
= operands
[i
];
8992 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8993 can_scalarize
= false;
8995 if (can_scalarize
) {
8996 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8997 assert(dst
.size() % num_components
== 0);
8998 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9000 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9001 for (unsigned k
= 0; k
< num_components
; k
++) {
9002 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9003 for (unsigned i
= 0; i
< num_operands
; i
++) {
9004 Operand src
= operands
[i
];
9005 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9007 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9008 phi
->definitions
[0] = Definition(phi_dst
);
9009 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9010 new_vec
[k
] = phi_dst
;
9011 vec
->operands
[k
] = Operand(phi_dst
);
9013 vec
->definitions
[0] = Definition(dst
);
9014 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9015 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9020 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9021 for (unsigned i
= 0; i
< num_operands
; i
++)
9022 phi
->operands
[i
] = operands
[i
];
9023 phi
->definitions
[0] = Definition(dst
);
9024 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9028 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9030 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9032 assert(dst
.type() == RegType::sgpr
);
9034 if (dst
.size() == 1) {
9035 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9037 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9038 for (unsigned i
= 0; i
< dst
.size(); i
++)
9039 vec
->operands
[i
] = Operand(0u);
9040 vec
->definitions
[0] = Definition(dst
);
9041 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9045 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9047 Builder
bld(ctx
->program
, ctx
->block
);
9048 Block
*logical_target
;
9049 append_logical_end(ctx
->block
);
9050 unsigned idx
= ctx
->block
->index
;
9052 switch (instr
->type
) {
9053 case nir_jump_break
:
9054 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9055 add_logical_edge(idx
, logical_target
);
9056 ctx
->block
->kind
|= block_kind_break
;
9058 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9059 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9060 /* uniform break - directly jump out of the loop */
9061 ctx
->block
->kind
|= block_kind_uniform
;
9062 ctx
->cf_info
.has_branch
= true;
9063 bld
.branch(aco_opcode::p_branch
);
9064 add_linear_edge(idx
, logical_target
);
9067 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9068 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9070 case nir_jump_continue
:
9071 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9072 add_logical_edge(idx
, logical_target
);
9073 ctx
->block
->kind
|= block_kind_continue
;
9075 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9076 /* for potential uniform breaks after this continue,
9077 we must ensure that they are handled correctly */
9078 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9079 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9080 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9082 /* uniform continue - directly jump to the loop header */
9083 ctx
->block
->kind
|= block_kind_uniform
;
9084 ctx
->cf_info
.has_branch
= true;
9085 bld
.branch(aco_opcode::p_branch
);
9086 add_linear_edge(idx
, logical_target
);
9091 fprintf(stderr
, "Unknown NIR jump instr: ");
9092 nir_print_instr(&instr
->instr
, stderr
);
9093 fprintf(stderr
, "\n");
9097 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9098 ctx
->cf_info
.exec_potentially_empty_break
= true;
9099 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9102 /* remove critical edges from linear CFG */
9103 bld
.branch(aco_opcode::p_branch
);
9104 Block
* break_block
= ctx
->program
->create_and_insert_block();
9105 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9106 break_block
->kind
|= block_kind_uniform
;
9107 add_linear_edge(idx
, break_block
);
9108 /* the loop_header pointer might be invalidated by this point */
9109 if (instr
->type
== nir_jump_continue
)
9110 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9111 add_linear_edge(break_block
->index
, logical_target
);
9112 bld
.reset(break_block
);
9113 bld
.branch(aco_opcode::p_branch
);
9115 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9116 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9117 add_linear_edge(idx
, continue_block
);
9118 append_logical_start(continue_block
);
9119 ctx
->block
= continue_block
;
9123 void visit_block(isel_context
*ctx
, nir_block
*block
)
9125 nir_foreach_instr(instr
, block
) {
9126 switch (instr
->type
) {
9127 case nir_instr_type_alu
:
9128 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9130 case nir_instr_type_load_const
:
9131 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9133 case nir_instr_type_intrinsic
:
9134 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9136 case nir_instr_type_tex
:
9137 visit_tex(ctx
, nir_instr_as_tex(instr
));
9139 case nir_instr_type_phi
:
9140 visit_phi(ctx
, nir_instr_as_phi(instr
));
9142 case nir_instr_type_ssa_undef
:
9143 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9145 case nir_instr_type_deref
:
9147 case nir_instr_type_jump
:
9148 visit_jump(ctx
, nir_instr_as_jump(instr
));
9151 fprintf(stderr
, "Unknown NIR instr type: ");
9152 nir_print_instr(instr
, stderr
);
9153 fprintf(stderr
, "\n");
9158 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9159 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9164 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9165 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9167 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9168 RegClass rc
= vals
[0].regClass();
9170 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9172 unsigned next_pred
= 1;
9174 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9175 Block
& block
= ctx
->program
->blocks
[idx
];
9176 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9177 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9181 if (block
.kind
& block_kind_continue
) {
9182 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9187 bool all_same
= true;
9188 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9189 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9193 val
= vals
[block
.linear_preds
[0] - first
];
9195 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9196 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9197 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9198 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9199 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9200 phi
->definitions
[0] = Definition(val
.getTemp());
9201 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9203 vals
[idx
- first
] = val
;
9206 return vals
[last
- first
];
9209 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9211 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9212 append_logical_end(ctx
->block
);
9213 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9214 Builder
bld(ctx
->program
, ctx
->block
);
9215 bld
.branch(aco_opcode::p_branch
);
9216 unsigned loop_preheader_idx
= ctx
->block
->index
;
9218 Block loop_exit
= Block();
9219 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9220 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9222 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9223 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9224 loop_header
->kind
|= block_kind_loop_header
;
9225 add_edge(loop_preheader_idx
, loop_header
);
9226 ctx
->block
= loop_header
;
9228 /* emit loop body */
9229 unsigned loop_header_idx
= loop_header
->index
;
9230 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9231 append_logical_start(ctx
->block
);
9232 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9234 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9235 if (!ctx
->cf_info
.has_branch
) {
9236 append_logical_end(ctx
->block
);
9237 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9238 /* Discards can result in code running with an empty exec mask.
9239 * This would result in divergent breaks not ever being taken. As a
9240 * workaround, break the loop when the loop mask is empty instead of
9241 * always continuing. */
9242 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9243 unsigned block_idx
= ctx
->block
->index
;
9245 /* create helper blocks to avoid critical edges */
9246 Block
*break_block
= ctx
->program
->create_and_insert_block();
9247 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9248 break_block
->kind
= block_kind_uniform
;
9249 bld
.reset(break_block
);
9250 bld
.branch(aco_opcode::p_branch
);
9251 add_linear_edge(block_idx
, break_block
);
9252 add_linear_edge(break_block
->index
, &loop_exit
);
9254 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9255 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9256 continue_block
->kind
= block_kind_uniform
;
9257 bld
.reset(continue_block
);
9258 bld
.branch(aco_opcode::p_branch
);
9259 add_linear_edge(block_idx
, continue_block
);
9260 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9262 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9263 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9264 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9266 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9267 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9268 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9270 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9273 bld
.reset(ctx
->block
);
9274 bld
.branch(aco_opcode::p_branch
);
9277 /* Fixup phis in loop header from unreachable blocks.
9278 * has_branch/has_divergent_branch also indicates if the loop ends with a
9279 * break/continue instruction, but we don't emit those if unreachable=true */
9281 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9282 bool linear
= ctx
->cf_info
.has_branch
;
9283 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9284 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9285 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9286 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9287 /* the last operand should be the one that needs to be removed */
9288 instr
->operands
.pop_back();
9289 } else if (!is_phi(instr
)) {
9295 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9296 * and the previous one shouldn't both happen at once because a break in the
9297 * merge block would get CSE'd */
9298 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9299 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9300 Operand vals
[num_vals
];
9301 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9302 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9303 if (ctx
->cf_info
.has_branch
)
9304 instr
->operands
.pop_back();
9306 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9307 } else if (!is_phi(instr
)) {
9313 ctx
->cf_info
.has_branch
= false;
9315 // TODO: if the loop has not a single exit, we must add one °°
9316 /* emit loop successor block */
9317 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9318 append_logical_start(ctx
->block
);
9321 // TODO: check if it is beneficial to not branch on continues
9322 /* trim linear phis in loop header */
9323 for (auto&& instr
: loop_entry
->instructions
) {
9324 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9325 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9326 new_phi
->definitions
[0] = instr
->definitions
[0];
9327 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9328 new_phi
->operands
[i
] = instr
->operands
[i
];
9329 /* check that the remaining operands are all the same */
9330 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9331 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9332 instr
.swap(new_phi
);
9333 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9342 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9346 append_logical_end(ctx
->block
);
9347 ctx
->block
->kind
|= block_kind_branch
;
9349 /* branch to linear then block */
9350 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9351 aco_ptr
<Pseudo_branch_instruction
> branch
;
9352 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9353 branch
->operands
[0] = Operand(cond
);
9354 ctx
->block
->instructions
.push_back(std::move(branch
));
9356 ic
->BB_if_idx
= ctx
->block
->index
;
9357 ic
->BB_invert
= Block();
9358 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9359 /* Invert blocks are intentionally not marked as top level because they
9360 * are not part of the logical cfg. */
9361 ic
->BB_invert
.kind
|= block_kind_invert
;
9362 ic
->BB_endif
= Block();
9363 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9364 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9366 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9367 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9368 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9369 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9370 ctx
->cf_info
.parent_if
.is_divergent
= true;
9372 /* divergent branches use cbranch_execz */
9373 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9374 ctx
->cf_info
.exec_potentially_empty_break
= false;
9375 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9377 /** emit logical then block */
9378 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9379 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9380 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9381 ctx
->block
= BB_then_logical
;
9382 append_logical_start(BB_then_logical
);
9385 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9387 Block
*BB_then_logical
= ctx
->block
;
9388 append_logical_end(BB_then_logical
);
9389 /* branch from logical then block to invert block */
9390 aco_ptr
<Pseudo_branch_instruction
> branch
;
9391 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9392 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9393 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9394 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9395 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9396 BB_then_logical
->kind
|= block_kind_uniform
;
9397 assert(!ctx
->cf_info
.has_branch
);
9398 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9399 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9401 /** emit linear then block */
9402 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9403 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9404 BB_then_linear
->kind
|= block_kind_uniform
;
9405 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9406 /* branch from linear then block to invert block */
9407 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9408 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9409 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9411 /** emit invert merge block */
9412 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9413 ic
->invert_idx
= ctx
->block
->index
;
9415 /* branch to linear else block (skip else) */
9416 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9417 branch
->operands
[0] = Operand(ic
->cond
);
9418 ctx
->block
->instructions
.push_back(std::move(branch
));
9420 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9421 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9422 ic
->exec_potentially_empty_break_depth_old
=
9423 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9424 /* divergent branches use cbranch_execz */
9425 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9426 ctx
->cf_info
.exec_potentially_empty_break
= false;
9427 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9429 /** emit logical else block */
9430 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9431 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9432 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9433 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9434 ctx
->block
= BB_else_logical
;
9435 append_logical_start(BB_else_logical
);
9438 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9440 Block
*BB_else_logical
= ctx
->block
;
9441 append_logical_end(BB_else_logical
);
9443 /* branch from logical else block to endif block */
9444 aco_ptr
<Pseudo_branch_instruction
> branch
;
9445 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9446 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9447 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9448 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9449 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9450 BB_else_logical
->kind
|= block_kind_uniform
;
9452 assert(!ctx
->cf_info
.has_branch
);
9453 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9456 /** emit linear else block */
9457 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9458 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9459 BB_else_linear
->kind
|= block_kind_uniform
;
9460 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9462 /* branch from linear else block to endif block */
9463 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9464 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9465 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9468 /** emit endif merge block */
9469 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9470 append_logical_start(ctx
->block
);
9473 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9474 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9475 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9476 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9477 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9478 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9479 !ctx
->cf_info
.parent_if
.is_divergent
) {
9480 ctx
->cf_info
.exec_potentially_empty_break
= false;
9481 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9483 /* uniform control flow never has an empty exec-mask */
9484 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9485 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9486 ctx
->cf_info
.exec_potentially_empty_break
= false;
9487 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9491 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9493 assert(cond
.regClass() == s1
);
9495 append_logical_end(ctx
->block
);
9496 ctx
->block
->kind
|= block_kind_uniform
;
9498 aco_ptr
<Pseudo_branch_instruction
> branch
;
9499 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9500 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9501 branch
->operands
[0] = Operand(cond
);
9502 branch
->operands
[0].setFixed(scc
);
9503 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9505 ic
->BB_if_idx
= ctx
->block
->index
;
9506 ic
->BB_endif
= Block();
9507 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9508 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9510 ctx
->cf_info
.has_branch
= false;
9511 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9513 /** emit then block */
9514 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9515 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9516 add_edge(ic
->BB_if_idx
, BB_then
);
9517 append_logical_start(BB_then
);
9518 ctx
->block
= BB_then
;
9521 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9523 Block
*BB_then
= ctx
->block
;
9525 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9526 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9528 if (!ic
->uniform_has_then_branch
) {
9529 append_logical_end(BB_then
);
9530 /* branch from then block to endif block */
9531 aco_ptr
<Pseudo_branch_instruction
> branch
;
9532 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9533 BB_then
->instructions
.emplace_back(std::move(branch
));
9534 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9535 if (!ic
->then_branch_divergent
)
9536 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9537 BB_then
->kind
|= block_kind_uniform
;
9540 ctx
->cf_info
.has_branch
= false;
9541 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9543 /** emit else block */
9544 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9545 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9546 add_edge(ic
->BB_if_idx
, BB_else
);
9547 append_logical_start(BB_else
);
9548 ctx
->block
= BB_else
;
9551 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9553 Block
*BB_else
= ctx
->block
;
9555 if (!ctx
->cf_info
.has_branch
) {
9556 append_logical_end(BB_else
);
9557 /* branch from then block to endif block */
9558 aco_ptr
<Pseudo_branch_instruction
> branch
;
9559 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9560 BB_else
->instructions
.emplace_back(std::move(branch
));
9561 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9562 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9563 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9564 BB_else
->kind
|= block_kind_uniform
;
9567 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9568 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9570 /** emit endif merge block */
9571 if (!ctx
->cf_info
.has_branch
) {
9572 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9573 append_logical_start(ctx
->block
);
9577 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9579 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9580 Builder
bld(ctx
->program
, ctx
->block
);
9581 aco_ptr
<Pseudo_branch_instruction
> branch
;
9584 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9586 * Uniform conditionals are represented in the following way*) :
9588 * The linear and logical CFG:
9591 * BB_THEN (logical) BB_ELSE (logical)
9595 * *) Exceptions may be due to break and continue statements within loops
9596 * If a break/continue happens within uniform control flow, it branches
9597 * to the loop exit/entry block. Otherwise, it branches to the next
9601 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9602 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9603 cond
= bool_to_scalar_condition(ctx
, cond
);
9605 begin_uniform_if_then(ctx
, &ic
, cond
);
9606 visit_cf_list(ctx
, &if_stmt
->then_list
);
9608 begin_uniform_if_else(ctx
, &ic
);
9609 visit_cf_list(ctx
, &if_stmt
->else_list
);
9611 end_uniform_if(ctx
, &ic
);
9613 return !ctx
->cf_info
.has_branch
;
9614 } else { /* non-uniform condition */
9616 * To maintain a logical and linear CFG without critical edges,
9617 * non-uniform conditionals are represented in the following way*) :
9622 * BB_THEN (logical) BB_THEN (linear)
9624 * BB_INVERT (linear)
9626 * BB_ELSE (logical) BB_ELSE (linear)
9633 * BB_THEN (logical) BB_ELSE (logical)
9637 * *) Exceptions may be due to break and continue statements within loops
9640 begin_divergent_if_then(ctx
, &ic
, cond
);
9641 visit_cf_list(ctx
, &if_stmt
->then_list
);
9643 begin_divergent_if_else(ctx
, &ic
);
9644 visit_cf_list(ctx
, &if_stmt
->else_list
);
9646 end_divergent_if(ctx
, &ic
);
9652 static bool visit_cf_list(isel_context
*ctx
,
9653 struct exec_list
*list
)
9655 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9656 switch (node
->type
) {
9657 case nir_cf_node_block
:
9658 visit_block(ctx
, nir_cf_node_as_block(node
));
9660 case nir_cf_node_if
:
9661 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9664 case nir_cf_node_loop
:
9665 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9668 unreachable("unimplemented cf list type");
9674 static void create_null_export(isel_context
*ctx
)
9676 /* Some shader stages always need to have exports.
9677 * So when there is none, we need to add a null export.
9680 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9681 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9682 Builder
bld(ctx
->program
, ctx
->block
);
9683 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9684 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9687 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9689 assert(ctx
->stage
== vertex_vs
||
9690 ctx
->stage
== tess_eval_vs
||
9691 ctx
->stage
== gs_copy_vs
||
9692 ctx
->stage
== ngg_vertex_gs
||
9693 ctx
->stage
== ngg_tess_eval_gs
);
9695 int offset
= (ctx
->stage
& sw_tes
)
9696 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9697 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9698 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9699 if (!is_pos
&& !mask
)
9701 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9703 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9704 exp
->enabled_mask
= mask
;
9705 for (unsigned i
= 0; i
< 4; ++i
) {
9706 if (mask
& (1 << i
))
9707 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9709 exp
->operands
[i
] = Operand(v1
);
9711 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9712 * Setting valid_mask=1 prevents it and has no other effect.
9714 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9716 exp
->compressed
= false;
9718 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9720 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9721 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9726 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9728 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9729 exp
->enabled_mask
= 0;
9730 for (unsigned i
= 0; i
< 4; ++i
)
9731 exp
->operands
[i
] = Operand(v1
);
9732 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9733 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9734 exp
->enabled_mask
|= 0x1;
9736 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9737 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9738 exp
->enabled_mask
|= 0x4;
9740 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9741 if (ctx
->options
->chip_class
< GFX9
) {
9742 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9743 exp
->enabled_mask
|= 0x8;
9745 Builder
bld(ctx
->program
, ctx
->block
);
9747 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9748 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9749 if (exp
->operands
[2].isTemp())
9750 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9752 exp
->operands
[2] = Operand(out
);
9753 exp
->enabled_mask
|= 0x4;
9756 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9758 exp
->compressed
= false;
9759 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9760 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9763 static void create_export_phis(isel_context
*ctx
)
9765 /* Used when exports are needed, but the output temps are defined in a preceding block.
9766 * This function will set up phis in order to access the outputs in the next block.
9769 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9770 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9771 ctx
->block
->instructions
.pop_back();
9773 Builder
bld(ctx
->program
, ctx
->block
);
9775 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9776 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9777 for (unsigned i
= 0; i
< 4; ++i
) {
9778 if (!(mask
& (1 << i
)))
9781 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9782 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9783 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9787 bld
.insert(std::move(logical_start
));
9790 static void create_vs_exports(isel_context
*ctx
)
9792 assert(ctx
->stage
== vertex_vs
||
9793 ctx
->stage
== tess_eval_vs
||
9794 ctx
->stage
== gs_copy_vs
||
9795 ctx
->stage
== ngg_vertex_gs
||
9796 ctx
->stage
== ngg_tess_eval_gs
);
9798 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9799 ? &ctx
->program
->info
->tes
.outinfo
9800 : &ctx
->program
->info
->vs
.outinfo
;
9802 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9803 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9804 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9807 if (ctx
->options
->key
.has_multiview_view_index
) {
9808 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9809 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9812 /* the order these position exports are created is important */
9814 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9815 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9816 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9817 exported_pos
= true;
9819 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9820 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9821 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9822 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9824 if (ctx
->export_clip_dists
) {
9825 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9826 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9827 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9828 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9831 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9832 if (i
< VARYING_SLOT_VAR0
&&
9833 i
!= VARYING_SLOT_LAYER
&&
9834 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9837 export_vs_varying(ctx
, i
, false, NULL
);
9841 create_null_export(ctx
);
9844 static bool export_fs_mrt_z(isel_context
*ctx
)
9846 Builder
bld(ctx
->program
, ctx
->block
);
9847 unsigned enabled_channels
= 0;
9851 for (unsigned i
= 0; i
< 4; ++i
) {
9852 values
[i
] = Operand(v1
);
9855 /* Both stencil and sample mask only need 16-bits. */
9856 if (!ctx
->program
->info
->ps
.writes_z
&&
9857 (ctx
->program
->info
->ps
.writes_stencil
||
9858 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9859 compr
= true; /* COMPR flag */
9861 if (ctx
->program
->info
->ps
.writes_stencil
) {
9862 /* Stencil should be in X[23:16]. */
9863 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9864 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9865 enabled_channels
|= 0x3;
9868 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9869 /* SampleMask should be in Y[15:0]. */
9870 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9871 enabled_channels
|= 0xc;
9874 if (ctx
->program
->info
->ps
.writes_z
) {
9875 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9876 enabled_channels
|= 0x1;
9879 if (ctx
->program
->info
->ps
.writes_stencil
) {
9880 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9881 enabled_channels
|= 0x2;
9884 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9885 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9886 enabled_channels
|= 0x4;
9890 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9891 * writemask component.
9893 if (ctx
->options
->chip_class
== GFX6
&&
9894 ctx
->options
->family
!= CHIP_OLAND
&&
9895 ctx
->options
->family
!= CHIP_HAINAN
) {
9896 enabled_channels
|= 0x1;
9899 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9900 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9905 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9907 Builder
bld(ctx
->program
, ctx
->block
);
9908 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9911 for (unsigned i
= 0; i
< 4; ++i
) {
9912 if (write_mask
& (1 << i
)) {
9913 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9915 values
[i
] = Operand(v1
);
9919 unsigned target
, col_format
;
9920 unsigned enabled_channels
= 0;
9921 aco_opcode compr_op
= (aco_opcode
)0;
9923 slot
-= FRAG_RESULT_DATA0
;
9924 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9925 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9927 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9928 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9932 case V_028714_SPI_SHADER_ZERO
:
9933 enabled_channels
= 0; /* writemask */
9934 target
= V_008DFC_SQ_EXP_NULL
;
9937 case V_028714_SPI_SHADER_32_R
:
9938 enabled_channels
= 1;
9941 case V_028714_SPI_SHADER_32_GR
:
9942 enabled_channels
= 0x3;
9945 case V_028714_SPI_SHADER_32_AR
:
9946 if (ctx
->options
->chip_class
>= GFX10
) {
9947 /* Special case: on GFX10, the outputs are different for 32_AR */
9948 enabled_channels
= 0x3;
9949 values
[1] = values
[3];
9950 values
[3] = Operand(v1
);
9952 enabled_channels
= 0x9;
9956 case V_028714_SPI_SHADER_FP16_ABGR
:
9957 enabled_channels
= 0x5;
9958 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9961 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9962 enabled_channels
= 0x5;
9963 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9966 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9967 enabled_channels
= 0x5;
9968 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9971 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9972 enabled_channels
= 0x5;
9973 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9974 if (is_int8
|| is_int10
) {
9976 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9977 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9979 for (unsigned i
= 0; i
< 4; i
++) {
9980 if ((write_mask
>> i
) & 1) {
9981 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9982 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9990 case V_028714_SPI_SHADER_SINT16_ABGR
:
9991 enabled_channels
= 0x5;
9992 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9993 if (is_int8
|| is_int10
) {
9995 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9996 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9997 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9998 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10000 for (unsigned i
= 0; i
< 4; i
++) {
10001 if ((write_mask
>> i
) & 1) {
10002 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10003 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10005 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10006 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10013 case V_028714_SPI_SHADER_32_ABGR
:
10014 enabled_channels
= 0xF;
10021 if (target
== V_008DFC_SQ_EXP_NULL
)
10024 if ((bool) compr_op
) {
10025 for (int i
= 0; i
< 2; i
++) {
10026 /* check if at least one of the values to be compressed is enabled */
10027 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10029 enabled_channels
|= enabled
<< (i
*2);
10030 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10031 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10032 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10034 values
[i
] = Operand(v1
);
10037 values
[2] = Operand(v1
);
10038 values
[3] = Operand(v1
);
10040 for (int i
= 0; i
< 4; i
++)
10041 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10044 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10045 enabled_channels
, target
, (bool) compr_op
);
10049 static void create_fs_exports(isel_context
*ctx
)
10051 bool exported
= false;
10053 /* Export depth, stencil and sample mask. */
10054 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10055 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10056 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10057 exported
|= export_fs_mrt_z(ctx
);
10059 /* Export all color render targets. */
10060 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10061 if (ctx
->outputs
.mask
[i
])
10062 exported
|= export_fs_mrt_color(ctx
, i
);
10065 create_null_export(ctx
);
10068 static void write_tcs_tess_factors(isel_context
*ctx
)
10070 unsigned outer_comps
;
10071 unsigned inner_comps
;
10073 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10090 Builder
bld(ctx
->program
, ctx
->block
);
10092 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10093 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10094 bld
.sopp(aco_opcode::s_barrier
);
10096 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10097 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10099 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10100 if_context ic_invocation_id_is_zero
;
10101 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10102 bld
.reset(ctx
->block
);
10104 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10106 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10107 unsigned stride
= inner_comps
+ outer_comps
;
10108 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10112 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10114 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10116 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10117 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10118 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10120 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10121 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10123 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10124 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10125 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10126 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10129 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10130 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10131 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10132 unsigned tf_const_offset
= 0;
10134 if (ctx
->program
->chip_class
<= GFX8
) {
10135 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10136 if_context ic_rel_patch_id_is_zero
;
10137 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10138 bld
.reset(ctx
->block
);
10140 /* Store the dynamic HS control word. */
10141 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10142 bld
.mubuf(aco_opcode::buffer_store_dword
,
10143 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10144 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10145 /* disable_wqm */ false, /* glc */ true);
10146 tf_const_offset
+= 4;
10148 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10149 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10150 bld
.reset(ctx
->block
);
10153 assert(stride
== 2 || stride
== 4 || stride
== 6);
10154 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10155 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10157 /* Store to offchip for TES to read - only if TES reads them */
10158 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10159 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10160 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10162 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10163 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10165 if (likely(inner_comps
)) {
10166 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10167 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10171 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10172 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10175 static void emit_stream_output(isel_context
*ctx
,
10176 Temp
const *so_buffers
,
10177 Temp
const *so_write_offset
,
10178 const struct radv_stream_output
*output
)
10180 unsigned num_comps
= util_bitcount(output
->component_mask
);
10181 unsigned writemask
= (1 << num_comps
) - 1;
10182 unsigned loc
= output
->location
;
10183 unsigned buf
= output
->buffer
;
10185 assert(num_comps
&& num_comps
<= 4);
10186 if (!num_comps
|| num_comps
> 4)
10189 unsigned start
= ffs(output
->component_mask
) - 1;
10192 bool all_undef
= true;
10193 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10194 for (unsigned i
= 0; i
< num_comps
; i
++) {
10195 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10196 all_undef
= all_undef
&& !out
[i
].id();
10201 while (writemask
) {
10203 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10204 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10205 /* GFX6 doesn't support storing vec3, split it. */
10206 writemask
|= 1u << (start
+ 2);
10210 unsigned offset
= output
->offset
+ start
* 4;
10212 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10213 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10214 for (int i
= 0; i
< count
; ++i
)
10215 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10216 vec
->definitions
[0] = Definition(write_data
);
10217 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10222 opcode
= aco_opcode::buffer_store_dword
;
10225 opcode
= aco_opcode::buffer_store_dwordx2
;
10228 opcode
= aco_opcode::buffer_store_dwordx3
;
10231 opcode
= aco_opcode::buffer_store_dwordx4
;
10234 unreachable("Unsupported dword count.");
10237 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10238 store
->operands
[0] = Operand(so_buffers
[buf
]);
10239 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10240 store
->operands
[2] = Operand((uint32_t) 0);
10241 store
->operands
[3] = Operand(write_data
);
10242 if (offset
> 4095) {
10243 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10244 Builder
bld(ctx
->program
, ctx
->block
);
10245 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10247 store
->offset
= offset
;
10249 store
->offen
= true;
10251 store
->dlc
= false;
10253 store
->can_reorder
= true;
10254 ctx
->block
->instructions
.emplace_back(std::move(store
));
10258 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10260 Builder
bld(ctx
->program
, ctx
->block
);
10262 Temp so_buffers
[4];
10263 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10264 for (unsigned i
= 0; i
< 4; i
++) {
10265 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10269 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10270 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10273 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10274 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10276 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10278 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10281 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10283 bld
.reset(ctx
->block
);
10285 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10287 Temp so_write_offset
[4];
10289 for (unsigned i
= 0; i
< 4; i
++) {
10290 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10295 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10296 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10297 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10298 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10300 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10302 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10303 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10304 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10305 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10309 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10310 struct radv_stream_output
*output
=
10311 &ctx
->program
->info
->so
.outputs
[i
];
10312 if (stream
!= output
->stream
)
10315 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10318 begin_divergent_if_else(ctx
, &ic
);
10319 end_divergent_if(ctx
, &ic
);
10322 } /* end namespace */
10324 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10326 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10327 Builder
bld(ctx
->program
, ctx
->block
);
10328 constexpr unsigned hs_idx
= 1u;
10329 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10330 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10331 Operand((8u << 16) | (hs_idx
* 8u)));
10332 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10334 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10336 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10337 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10338 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10339 ls_has_nonzero_hs_threads
);
10340 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10341 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10342 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10343 ls_has_nonzero_hs_threads
);
10344 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10345 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10346 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10347 ls_has_nonzero_hs_threads
);
10349 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10350 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10351 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10354 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10356 /* Split all arguments except for the first (ring_offsets) and the last
10357 * (exec) so that the dead channels don't stay live throughout the program.
10359 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10360 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10361 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10362 startpgm
->definitions
[i
].regClass().size());
10367 void handle_bc_optimize(isel_context
*ctx
)
10369 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10370 Builder
bld(ctx
->program
, ctx
->block
);
10371 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10372 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10373 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10374 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10375 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10376 if (uses_center
&& uses_centroid
) {
10377 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10378 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10380 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10382 for (unsigned i
= 0; i
< 2; i
++) {
10383 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10384 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10385 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10386 persp_centroid
, persp_center
, sel
);
10388 ctx
->persp_centroid
= bld
.tmp(v2
);
10389 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10390 Operand(new_coord
[0]), Operand(new_coord
[1]));
10391 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10394 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10396 for (unsigned i
= 0; i
< 2; i
++) {
10397 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10398 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10399 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10400 linear_centroid
, linear_center
, sel
);
10402 ctx
->linear_centroid
= bld
.tmp(v2
);
10403 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10404 Operand(new_coord
[0]), Operand(new_coord
[1]));
10405 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10410 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10412 Program
*program
= ctx
->program
;
10414 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10416 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10417 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10418 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10419 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10420 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10422 program
->next_fp_mode
.must_flush_denorms32
=
10423 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10424 program
->next_fp_mode
.must_flush_denorms16_64
=
10425 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10426 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10428 program
->next_fp_mode
.care_about_round32
=
10429 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10431 program
->next_fp_mode
.care_about_round16_64
=
10432 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10433 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10435 /* default to preserving fp16 and fp64 denorms, since it's free */
10436 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10437 program
->next_fp_mode
.denorm16_64
= 0;
10439 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10441 /* preserving fp32 denorms is expensive, so only do it if asked */
10442 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10443 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10445 program
->next_fp_mode
.denorm32
= 0;
10447 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10448 program
->next_fp_mode
.round32
= fp_round_tz
;
10450 program
->next_fp_mode
.round32
= fp_round_ne
;
10452 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10453 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10455 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10457 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10460 void cleanup_cfg(Program
*program
)
10462 /* create linear_succs/logical_succs */
10463 for (Block
& BB
: program
->blocks
) {
10464 for (unsigned idx
: BB
.linear_preds
)
10465 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10466 for (unsigned idx
: BB
.logical_preds
)
10467 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10471 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10473 Builder
bld(ctx
->program
, ctx
->block
);
10475 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10476 Temp count
= i
== 0
10477 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10478 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10479 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10481 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10484 if (ctx
->program
->wave_size
== 64) {
10485 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10486 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10487 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10489 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10490 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10496 bool ngg_early_prim_export(isel_context
*ctx
)
10498 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10502 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10504 Builder
bld(ctx
->program
, ctx
->block
);
10506 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10507 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10509 /* Get the id of the current wave within the threadgroup (workgroup) */
10510 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10511 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10513 /* Execute the following code only on the first wave (wave id 0),
10514 * use the SCC def to tell if the wave id is zero or not.
10516 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10518 begin_uniform_if_then(ctx
, &ic
, cond
);
10519 begin_uniform_if_else(ctx
, &ic
);
10520 bld
.reset(ctx
->block
);
10522 /* Number of vertices output by VS/TES */
10523 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10524 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10525 /* Number of primitives output by VS/TES */
10526 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10527 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10529 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10530 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10531 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10533 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10534 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10536 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10537 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10539 end_uniform_if(ctx
, &ic
);
10542 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10544 Builder
bld(ctx
->program
, ctx
->block
);
10546 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10547 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10550 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10553 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10554 assert(vtxindex
[i
].id());
10557 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10561 /* The initial edge flag is always false in tess eval shaders. */
10562 if (ctx
->stage
== ngg_vertex_gs
) {
10563 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10564 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10568 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10573 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10575 Builder
bld(ctx
->program
, ctx
->block
);
10576 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10578 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10579 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10580 false /* compressed */, true/* done */, false /* valid mask */);
10583 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10585 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10586 * These must always come before VS exports.
10588 * It is recommended to do these as early as possible. They can be at the beginning when
10589 * there is no SW GS and the shader doesn't write edge flags.
10593 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10594 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10596 Builder
bld(ctx
->program
, ctx
->block
);
10597 constexpr unsigned max_vertices_per_primitive
= 3;
10598 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10600 if (ctx
->stage
== ngg_vertex_gs
) {
10601 /* TODO: optimize for points & lines */
10602 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10603 if (ctx
->shader
->info
.tess
.point_mode
)
10604 num_vertices_per_primitive
= 1;
10605 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10606 num_vertices_per_primitive
= 2;
10608 unreachable("Unsupported NGG shader stage");
10611 Temp vtxindex
[max_vertices_per_primitive
];
10612 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10613 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10614 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10615 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10616 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10617 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10618 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10619 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10621 /* Export primitive data to the index buffer. */
10622 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10624 /* Export primitive ID. */
10625 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10626 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10627 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10628 Temp provoking_vtx_index
= vtxindex
[0];
10629 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10631 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10634 begin_divergent_if_else(ctx
, &ic
);
10635 end_divergent_if(ctx
, &ic
);
10638 void ngg_emit_nogs_output(isel_context
*ctx
)
10640 /* Emits NGG GS output, for stages that don't have SW GS. */
10643 Builder
bld(ctx
->program
, ctx
->block
);
10644 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10646 /* NGG streamout is currently disabled by default. */
10647 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10649 if (late_prim_export
) {
10650 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10651 create_export_phis(ctx
);
10652 /* Do what we need to do in the GS threads. */
10653 ngg_emit_nogs_gsthreads(ctx
);
10655 /* What comes next should be executed on ES threads. */
10656 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10657 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10658 bld
.reset(ctx
->block
);
10661 /* Export VS outputs */
10662 ctx
->block
->kind
|= block_kind_export_end
;
10663 create_vs_exports(ctx
);
10665 /* Export primitive ID */
10666 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10669 if (ctx
->stage
== ngg_vertex_gs
) {
10670 /* Wait for GS threads to store primitive ID in LDS. */
10671 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10672 bld
.sopp(aco_opcode::s_barrier
);
10674 /* Calculate LDS address where the GS threads stored the primitive ID. */
10675 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10676 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10677 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10678 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10679 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10680 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10682 /* Load primitive ID from LDS. */
10683 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10684 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10685 /* TES: Just use the patch ID as the primitive ID. */
10686 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10688 unreachable("unsupported NGG shader stage.");
10691 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10692 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10694 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10697 if (late_prim_export
) {
10698 begin_divergent_if_else(ctx
, &ic
);
10699 end_divergent_if(ctx
, &ic
);
10700 bld
.reset(ctx
->block
);
10704 void select_program(Program
*program
,
10705 unsigned shader_count
,
10706 struct nir_shader
*const *shaders
,
10707 ac_shader_config
* config
,
10708 struct radv_shader_args
*args
)
10710 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10711 if_context ic_merged_wave_info
;
10712 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10714 for (unsigned i
= 0; i
< shader_count
; i
++) {
10715 nir_shader
*nir
= shaders
[i
];
10716 init_context(&ctx
, nir
);
10718 setup_fp_mode(&ctx
, nir
);
10721 /* needs to be after init_context() for FS */
10722 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10723 append_logical_start(ctx
.block
);
10725 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10726 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10728 split_arguments(&ctx
, startpgm
);
10732 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10734 if (ngg_early_prim_export(&ctx
))
10735 ngg_emit_nogs_gsthreads(&ctx
);
10738 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10739 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10740 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10741 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10742 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10743 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10744 ctx
.stage
== tess_eval_geometry_gs
));
10746 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10747 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10748 if (check_merged_wave_info
) {
10749 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10750 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10754 Builder
bld(ctx
.program
, ctx
.block
);
10756 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10757 bld
.sopp(aco_opcode::s_barrier
);
10759 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10760 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10762 } else if (ctx
.stage
== geometry_gs
)
10763 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10765 if (ctx
.stage
== fragment_fs
)
10766 handle_bc_optimize(&ctx
);
10768 visit_cf_list(&ctx
, &func
->body
);
10770 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10771 emit_streamout(&ctx
, 0);
10773 if (ctx
.stage
& hw_vs
) {
10774 create_vs_exports(&ctx
);
10775 ctx
.block
->kind
|= block_kind_export_end
;
10776 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10777 ngg_emit_nogs_output(&ctx
);
10778 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10779 Builder
bld(ctx
.program
, ctx
.block
);
10780 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10781 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10782 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10783 write_tcs_tess_factors(&ctx
);
10786 if (ctx
.stage
== fragment_fs
) {
10787 create_fs_exports(&ctx
);
10788 ctx
.block
->kind
|= block_kind_export_end
;
10791 if (endif_merged_wave_info
) {
10792 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10793 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10796 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10797 ngg_emit_nogs_output(&ctx
);
10799 ralloc_free(ctx
.divergent_vals
);
10801 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10802 /* Outputs of the previous stage are inputs to the next stage */
10803 ctx
.inputs
= ctx
.outputs
;
10804 ctx
.outputs
= shader_io_state();
10808 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10810 append_logical_end(ctx
.block
);
10811 ctx
.block
->kind
|= block_kind_uniform
;
10812 Builder
bld(ctx
.program
, ctx
.block
);
10813 if (ctx
.program
->wb_smem_l1_on_end
)
10814 bld
.smem(aco_opcode::s_dcache_wb
, false);
10815 bld
.sopp(aco_opcode::s_endpgm
);
10817 cleanup_cfg(program
);
10820 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10821 ac_shader_config
* config
,
10822 struct radv_shader_args
*args
)
10824 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10826 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10827 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10828 program
->next_fp_mode
.must_flush_denorms32
= false;
10829 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10830 program
->next_fp_mode
.care_about_round32
= false;
10831 program
->next_fp_mode
.care_about_round16_64
= false;
10832 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10833 program
->next_fp_mode
.denorm32
= 0;
10834 program
->next_fp_mode
.round32
= fp_round_ne
;
10835 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10836 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10838 add_startpgm(&ctx
);
10839 append_logical_start(ctx
.block
);
10841 Builder
bld(ctx
.program
, ctx
.block
);
10843 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10845 Operand
stream_id(0u);
10846 if (args
->shader_info
->so
.num_outputs
)
10847 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10848 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10850 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10852 std::stack
<Block
> endif_blocks
;
10854 for (unsigned stream
= 0; stream
< 4; stream
++) {
10855 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10858 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10859 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10862 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10864 unsigned BB_if_idx
= ctx
.block
->index
;
10865 Block BB_endif
= Block();
10866 if (!stream_id
.isConstant()) {
10868 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10869 append_logical_end(ctx
.block
);
10870 ctx
.block
->kind
|= block_kind_uniform
;
10871 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10873 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10875 ctx
.block
= ctx
.program
->create_and_insert_block();
10876 add_edge(BB_if_idx
, ctx
.block
);
10877 bld
.reset(ctx
.block
);
10878 append_logical_start(ctx
.block
);
10881 unsigned offset
= 0;
10882 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10883 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10886 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10887 unsigned length
= util_last_bit(output_usage_mask
);
10888 for (unsigned j
= 0; j
< length
; ++j
) {
10889 if (!(output_usage_mask
& (1 << j
)))
10892 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10893 Temp voffset
= vtx_offset
;
10894 if (const_offset
>= 4096u) {
10895 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10896 const_offset
%= 4096u;
10899 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10900 mubuf
->definitions
[0] = bld
.def(v1
);
10901 mubuf
->operands
[0] = Operand(gsvs_ring
);
10902 mubuf
->operands
[1] = Operand(voffset
);
10903 mubuf
->operands
[2] = Operand(0u);
10904 mubuf
->offen
= true;
10905 mubuf
->offset
= const_offset
;
10908 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10909 mubuf
->barrier
= barrier_none
;
10910 mubuf
->can_reorder
= true;
10912 ctx
.outputs
.mask
[i
] |= 1 << j
;
10913 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10915 bld
.insert(std::move(mubuf
));
10921 if (args
->shader_info
->so
.num_outputs
) {
10922 emit_streamout(&ctx
, stream
);
10923 bld
.reset(ctx
.block
);
10927 create_vs_exports(&ctx
);
10928 ctx
.block
->kind
|= block_kind_export_end
;
10931 if (!stream_id
.isConstant()) {
10932 append_logical_end(ctx
.block
);
10934 /* branch from then block to endif block */
10935 bld
.branch(aco_opcode::p_branch
);
10936 add_edge(ctx
.block
->index
, &BB_endif
);
10937 ctx
.block
->kind
|= block_kind_uniform
;
10939 /* emit else block */
10940 ctx
.block
= ctx
.program
->create_and_insert_block();
10941 add_edge(BB_if_idx
, ctx
.block
);
10942 bld
.reset(ctx
.block
);
10943 append_logical_start(ctx
.block
);
10945 endif_blocks
.push(std::move(BB_endif
));
10949 while (!endif_blocks
.empty()) {
10950 Block BB_endif
= std::move(endif_blocks
.top());
10951 endif_blocks
.pop();
10953 Block
*BB_else
= ctx
.block
;
10955 append_logical_end(BB_else
);
10956 /* branch from else block to endif block */
10957 bld
.branch(aco_opcode::p_branch
);
10958 add_edge(BB_else
->index
, &BB_endif
);
10959 BB_else
->kind
|= block_kind_uniform
;
10961 /** emit endif merge block */
10962 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10963 bld
.reset(ctx
.block
);
10964 append_logical_start(ctx
.block
);
10967 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10969 append_logical_end(ctx
.block
);
10970 ctx
.block
->kind
|= block_kind_uniform
;
10971 bld
.sopp(aco_opcode::s_endpgm
);
10973 cleanup_cfg(program
);