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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
418 Builder
bld(ctx
->program
, ctx
->block
);
419 if (offset
.isTemp()) {
420 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
422 if (vec
.size() == 4) {
423 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
425 } else if (vec
.size() == 3) {
426 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
428 } else if (vec
.size() == 2) {
429 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
432 for (unsigned i
= 0; i
< dst
.size(); i
++)
433 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
437 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
439 offset
= Operand(0u);
442 unsigned num_components
= dst
.bytes() / component_size
;
443 if (vec
.regClass() == dst
.regClass()) {
444 assert(offset
.constantValue() == 0);
445 bld
.copy(Definition(dst
), vec
);
446 emit_split_vector(ctx
, dst
, num_components
);
450 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
451 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
452 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
454 assert(offset
.constantValue() % component_size
== 0);
455 unsigned skip
= offset
.constantValue() / component_size
;
456 for (unsigned i
= 0; i
< num_components
; i
++)
457 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
459 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
460 if (dst
.type() == RegType::vgpr
) {
461 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
462 for (unsigned i
= 0; i
< num_components
; i
++)
463 create_vec
->operands
[i
] = Operand(elems
[i
]);
464 create_vec
->definitions
[0] = Definition(dst
);
465 bld
.insert(std::move(create_vec
));
467 /* if dst is sgpr - split the src, but move the original to sgpr. */
469 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
470 byte_align_scalar(ctx
, vec
, offset
, dst
);
472 assert(dst
.size() == vec
.size());
473 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
476 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
479 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
481 Builder
bld(ctx
->program
, ctx
->block
);
483 dst
= bld
.tmp(bld
.lm
);
485 assert(val
.regClass() == s1
);
486 assert(dst
.regClass() == bld
.lm
);
488 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
491 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
493 Builder
bld(ctx
->program
, ctx
->block
);
497 assert(val
.regClass() == bld
.lm
);
498 assert(dst
.regClass() == s1
);
500 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
501 Temp tmp
= bld
.tmp(s1
);
502 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
503 return emit_wqm(ctx
, tmp
, dst
);
506 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
508 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
509 return get_ssa_temp(ctx
, src
.src
.ssa
);
511 if (src
.src
.ssa
->num_components
== size
) {
512 bool identity_swizzle
= true;
513 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
514 if (src
.swizzle
[i
] != i
)
515 identity_swizzle
= false;
517 if (identity_swizzle
)
518 return get_ssa_temp(ctx
, src
.src
.ssa
);
521 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
522 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
523 assert(elem_size
> 0);
524 assert(vec
.bytes() % elem_size
== 0);
526 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
527 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
529 unsigned swizzle
= src
.swizzle
[0];
530 if (vec
.size() > 1) {
531 assert(src
.src
.ssa
->bit_size
== 16);
532 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
533 swizzle
= swizzle
& 1;
538 Temp dst
{ctx
->program
->allocateId(), s1
};
539 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
540 bfe
->operands
[0] = Operand(vec
);
541 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
542 bfe
->definitions
[0] = Definition(dst
);
543 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
544 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
548 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
550 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
553 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
554 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
555 for (unsigned i
= 0; i
< size
; ++i
) {
556 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
557 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
559 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
560 vec_instr
->definitions
[0] = Definition(dst
);
561 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
562 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
567 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
571 Builder
bld(ctx
->program
, ctx
->block
);
572 if (ptr
.type() == RegType::vgpr
)
573 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
574 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
575 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
578 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
580 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
581 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
582 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
583 sop2
->definitions
[0] = Definition(dst
);
585 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
586 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
589 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
590 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
592 Builder
bld(ctx
->program
, ctx
->block
);
593 bld
.is_precise
= instr
->exact
;
595 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
596 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
597 if (src1
.type() == RegType::sgpr
) {
598 if (commutative
&& src0
.type() == RegType::vgpr
) {
603 src1
= as_vgpr(ctx
, src1
);
607 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
608 assert(dst
.size() == 1);
609 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
610 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
612 bld
.vop2(op
, Definition(dst
), src0
, src1
);
616 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
617 aco_opcode op
, Temp dst
)
619 Builder
bld(ctx
->program
, ctx
->block
);
620 bld
.is_precise
= instr
->exact
;
622 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
623 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
625 if (src1
.type() == RegType::sgpr
) {
626 assert(src0
.type() == RegType::vgpr
);
627 std::swap(src0
, src1
);
630 Temp src00
= bld
.tmp(src0
.type(), 1);
631 Temp src01
= bld
.tmp(src0
.type(), 1);
632 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
633 Temp src10
= bld
.tmp(v1
);
634 Temp src11
= bld
.tmp(v1
);
635 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
636 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
637 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
638 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
641 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
642 bool flush_denorms
= false)
644 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
645 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
646 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
648 /* ensure that the instruction has at most 1 sgpr operand
649 * The optimizer will inline constants for us */
650 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
651 src0
= as_vgpr(ctx
, src0
);
652 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
653 src1
= as_vgpr(ctx
, src1
);
654 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
655 src2
= as_vgpr(ctx
, src2
);
657 Builder
bld(ctx
->program
, ctx
->block
);
658 bld
.is_precise
= instr
->exact
;
659 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
660 assert(dst
.size() == 1);
661 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
662 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
664 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
668 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
670 Builder
bld(ctx
->program
, ctx
->block
);
671 bld
.is_precise
= instr
->exact
;
672 if (dst
.type() == RegType::sgpr
)
673 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
674 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
676 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
679 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
682 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
683 assert(src0
.size() == src1
.size());
685 aco_ptr
<Instruction
> vopc
;
686 if (src1
.type() == RegType::sgpr
) {
687 if (src0
.type() == RegType::vgpr
) {
688 /* to swap the operands, we might also have to change the opcode */
690 case aco_opcode::v_cmp_lt_f16
:
691 op
= aco_opcode::v_cmp_gt_f16
;
693 case aco_opcode::v_cmp_ge_f16
:
694 op
= aco_opcode::v_cmp_le_f16
;
696 case aco_opcode::v_cmp_lt_i16
:
697 op
= aco_opcode::v_cmp_gt_i16
;
699 case aco_opcode::v_cmp_ge_i16
:
700 op
= aco_opcode::v_cmp_le_i16
;
702 case aco_opcode::v_cmp_lt_u16
:
703 op
= aco_opcode::v_cmp_gt_u16
;
705 case aco_opcode::v_cmp_ge_u16
:
706 op
= aco_opcode::v_cmp_le_u16
;
708 case aco_opcode::v_cmp_lt_f32
:
709 op
= aco_opcode::v_cmp_gt_f32
;
711 case aco_opcode::v_cmp_ge_f32
:
712 op
= aco_opcode::v_cmp_le_f32
;
714 case aco_opcode::v_cmp_lt_i32
:
715 op
= aco_opcode::v_cmp_gt_i32
;
717 case aco_opcode::v_cmp_ge_i32
:
718 op
= aco_opcode::v_cmp_le_i32
;
720 case aco_opcode::v_cmp_lt_u32
:
721 op
= aco_opcode::v_cmp_gt_u32
;
723 case aco_opcode::v_cmp_ge_u32
:
724 op
= aco_opcode::v_cmp_le_u32
;
726 case aco_opcode::v_cmp_lt_f64
:
727 op
= aco_opcode::v_cmp_gt_f64
;
729 case aco_opcode::v_cmp_ge_f64
:
730 op
= aco_opcode::v_cmp_le_f64
;
732 case aco_opcode::v_cmp_lt_i64
:
733 op
= aco_opcode::v_cmp_gt_i64
;
735 case aco_opcode::v_cmp_ge_i64
:
736 op
= aco_opcode::v_cmp_le_i64
;
738 case aco_opcode::v_cmp_lt_u64
:
739 op
= aco_opcode::v_cmp_gt_u64
;
741 case aco_opcode::v_cmp_ge_u64
:
742 op
= aco_opcode::v_cmp_le_u64
;
744 default: /* eq and ne are commutative */
751 src1
= as_vgpr(ctx
, src1
);
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
759 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
761 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
762 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
763 Builder
bld(ctx
->program
, ctx
->block
);
765 assert(dst
.regClass() == bld
.lm
);
766 assert(src0
.type() == RegType::sgpr
);
767 assert(src1
.type() == RegType::sgpr
);
768 assert(src0
.regClass() == src1
.regClass());
770 /* Emit the SALU comparison instruction */
771 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
772 /* Turn the result into a per-lane bool */
773 bool_to_vector_condition(ctx
, cmp
, dst
);
776 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
777 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
779 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
780 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
781 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
782 nir_dest_is_divergent(instr
->dest
.dest
) ||
783 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
784 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
785 aco_opcode op
= use_valu
? v_op
: s_op
;
786 assert(op
!= aco_opcode::num_opcodes
);
787 assert(dst
.regClass() == ctx
->program
->lane_mask
);
790 emit_vopc_instruction(ctx
, instr
, op
, dst
);
792 emit_sopc_instruction(ctx
, instr
, op
, dst
);
795 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
797 Builder
bld(ctx
->program
, ctx
->block
);
798 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
799 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
801 assert(dst
.regClass() == bld
.lm
);
802 assert(src0
.regClass() == bld
.lm
);
803 assert(src1
.regClass() == bld
.lm
);
805 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
808 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
810 Builder
bld(ctx
->program
, ctx
->block
);
811 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
812 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
813 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
815 assert(cond
.regClass() == bld
.lm
);
817 if (dst
.type() == RegType::vgpr
) {
818 aco_ptr
<Instruction
> bcsel
;
819 if (dst
.size() == 1) {
820 then
= as_vgpr(ctx
, then
);
821 els
= as_vgpr(ctx
, els
);
823 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
824 } else if (dst
.size() == 2) {
825 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
826 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
827 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
828 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
830 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
831 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
833 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
835 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
836 nir_print_instr(&instr
->instr
, stderr
);
837 fprintf(stderr
, "\n");
842 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
843 assert(dst
.regClass() == bld
.lm
);
844 assert(then
.regClass() == bld
.lm
);
845 assert(els
.regClass() == bld
.lm
);
848 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
849 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
850 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
851 assert(dst
.size() == then
.size());
852 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
853 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
855 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
856 nir_print_instr(&instr
->instr
, stderr
);
857 fprintf(stderr
, "\n");
862 /* divergent boolean bcsel
863 * this implements bcsel on bools: dst = s0 ? s1 : s2
864 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
865 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
867 if (cond
.id() != then
.id())
868 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
870 if (cond
.id() == els
.id())
871 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
873 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
874 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
877 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
878 aco_opcode op
, uint32_t undo
)
880 /* multiply by 16777216 to handle denormals */
881 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
882 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
883 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
884 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
885 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
887 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
889 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
892 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
894 if (ctx
->block
->fp_mode
.denorm32
== 0) {
895 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
899 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
902 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
904 if (ctx
->block
->fp_mode
.denorm32
== 0) {
905 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
909 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
912 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
914 if (ctx
->block
->fp_mode
.denorm32
== 0) {
915 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
919 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
922 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
924 if (ctx
->block
->fp_mode
.denorm32
== 0) {
925 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
929 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
932 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
934 if (ctx
->options
->chip_class
>= GFX7
)
935 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
937 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
938 /* TODO: create more efficient code! */
939 if (val
.type() == RegType::sgpr
)
940 val
= as_vgpr(ctx
, val
);
942 /* Split the input value. */
943 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
944 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
946 /* Extract the exponent and compute the unbiased value. */
947 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
948 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
950 /* Extract the fractional part. */
951 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
952 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
954 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
955 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
957 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
958 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
959 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
960 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
961 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
963 /* Get the sign bit. */
964 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
966 /* Decide the operation to apply depending on the unbiased exponent. */
967 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
968 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
969 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
970 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
971 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
972 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
974 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
977 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
979 if (ctx
->options
->chip_class
>= GFX7
)
980 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
982 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
983 Temp src0
= as_vgpr(ctx
, val
);
985 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
986 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
988 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
989 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
990 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
992 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
993 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
994 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
995 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
997 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
998 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1000 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1002 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1003 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1005 return add
->definitions
[0].getTemp();
1008 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
1010 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
1011 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
1013 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
1016 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
1017 return bld
.copy(Definition(dst
), src
);
1018 else if (dst
.bytes() < src
.bytes())
1019 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
1023 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1026 } else if (src
.regClass() == s1
) {
1028 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1030 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1031 } else if (ctx
->options
->chip_class
>= GFX8
) {
1032 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1033 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1034 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1035 sdwa
->operands
[0] = Operand(src
);
1036 sdwa
->definitions
[0] = Definition(tmp
);
1038 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1040 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1041 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1042 bld
.insert(std::move(sdwa
));
1044 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1045 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1046 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1049 if (dst_bits
== 64) {
1050 if (is_signed
&& dst
.regClass() == s2
) {
1051 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1052 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1053 } else if (is_signed
&& dst
.regClass() == v2
) {
1054 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1055 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1057 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1064 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1066 if (!instr
->dest
.dest
.is_ssa
) {
1067 fprintf(stderr
, "nir alu dst not in ssa: ");
1068 nir_print_instr(&instr
->instr
, stderr
);
1069 fprintf(stderr
, "\n");
1072 Builder
bld(ctx
->program
, ctx
->block
);
1073 bld
.is_precise
= instr
->exact
;
1074 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1079 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1080 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1081 for (unsigned i
= 0; i
< num
; ++i
)
1082 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1084 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1085 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1086 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1087 for (unsigned i
= 0; i
< num
; ++i
) {
1088 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1089 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1091 vec
->operands
[i
] = Operand
{elems
[i
]};
1093 vec
->definitions
[0] = Definition(dst
);
1094 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1095 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1097 // TODO: that is a bit suboptimal..
1098 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1099 for (unsigned i
= 0; i
< num
- 1; ++i
)
1100 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1101 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1102 for (unsigned i
= 0; i
< num
; ++i
) {
1103 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1104 if (bit
% 32 == 0) {
1105 elems
[bit
/ 32] = elems
[i
];
1107 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1108 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1109 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1112 if (dst
.size() == 1)
1113 bld
.copy(Definition(dst
), elems
[0]);
1115 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1120 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1121 aco_ptr
<Instruction
> mov
;
1122 if (dst
.type() == RegType::sgpr
) {
1123 if (src
.type() == RegType::vgpr
)
1124 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1125 else if (src
.regClass() == s1
)
1126 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1127 else if (src
.regClass() == s2
)
1128 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1130 unreachable("wrong src register class for nir_op_imov");
1132 if (dst
.regClass() == v1
)
1133 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1134 else if (dst
.regClass() == v1b
||
1135 dst
.regClass() == v2b
||
1136 dst
.regClass() == v2
)
1137 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1139 unreachable("wrong src register class for nir_op_imov");
1144 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1145 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1146 assert(src
.regClass() == bld
.lm
);
1147 assert(dst
.regClass() == bld
.lm
);
1148 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1149 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1150 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1151 } else if (dst
.regClass() == v1
) {
1152 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1153 } else if (dst
.regClass() == v2
) {
1154 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1155 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1156 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1157 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1159 } else if (dst
.type() == RegType::sgpr
) {
1160 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1161 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1163 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1164 nir_print_instr(&instr
->instr
, stderr
);
1165 fprintf(stderr
, "\n");
1170 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1171 if (dst
.regClass() == v1
) {
1172 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1173 } else if (dst
.regClass() == s1
) {
1174 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1175 } else if (dst
.size() == 2) {
1176 Temp src0
= bld
.tmp(dst
.type(), 1);
1177 Temp src1
= bld
.tmp(dst
.type(), 1);
1178 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1180 if (dst
.regClass() == s2
) {
1181 Temp carry
= bld
.tmp(s1
);
1182 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1183 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1184 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1186 Temp lower
= bld
.tmp(v1
);
1187 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1188 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1189 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1192 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1193 nir_print_instr(&instr
->instr
, stderr
);
1194 fprintf(stderr
, "\n");
1199 if (dst
.regClass() == s1
) {
1200 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1201 } else if (dst
.regClass() == v1
) {
1202 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1203 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1211 case nir_op_isign
: {
1212 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1213 if (dst
.regClass() == s1
) {
1214 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1215 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1216 } else if (dst
.regClass() == s2
) {
1217 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1219 if (ctx
->program
->chip_class
>= GFX8
)
1220 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1222 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1223 /* SCC gets zero-extended to 64 bit */
1224 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1225 } else if (dst
.regClass() == v1
) {
1226 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1227 } else if (dst
.regClass() == v2
) {
1228 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1229 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1230 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1231 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1232 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1233 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1235 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1236 nir_print_instr(&instr
->instr
, stderr
);
1237 fprintf(stderr
, "\n");
1242 if (dst
.regClass() == v1
) {
1243 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1244 } else if (dst
.regClass() == s1
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1247 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1248 nir_print_instr(&instr
->instr
, stderr
);
1249 fprintf(stderr
, "\n");
1254 if (dst
.regClass() == v1
) {
1255 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1256 } else if (dst
.regClass() == s1
) {
1257 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1259 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1260 nir_print_instr(&instr
->instr
, stderr
);
1261 fprintf(stderr
, "\n");
1266 if (dst
.regClass() == v1
) {
1267 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1268 } else if (dst
.regClass() == s1
) {
1269 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1271 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1272 nir_print_instr(&instr
->instr
, stderr
);
1273 fprintf(stderr
, "\n");
1278 if (dst
.regClass() == v1
) {
1279 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1280 } else if (dst
.regClass() == s1
) {
1281 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1283 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1284 nir_print_instr(&instr
->instr
, stderr
);
1285 fprintf(stderr
, "\n");
1290 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1291 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1292 } else if (dst
.regClass() == v1
) {
1293 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1294 } else if (dst
.regClass() == v2
) {
1295 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1296 } else if (dst
.regClass() == s1
) {
1297 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1298 } else if (dst
.regClass() == s2
) {
1299 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1302 nir_print_instr(&instr
->instr
, stderr
);
1303 fprintf(stderr
, "\n");
1308 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1309 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1310 } else if (dst
.regClass() == v1
) {
1311 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1312 } else if (dst
.regClass() == v2
) {
1313 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1314 } else if (dst
.regClass() == s1
) {
1315 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1316 } else if (dst
.regClass() == s2
) {
1317 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1319 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1320 nir_print_instr(&instr
->instr
, stderr
);
1321 fprintf(stderr
, "\n");
1326 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1327 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1328 } else if (dst
.regClass() == v1
) {
1329 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1330 } else if (dst
.regClass() == v2
) {
1331 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1332 } else if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1334 } else if (dst
.regClass() == s2
) {
1335 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1337 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1338 nir_print_instr(&instr
->instr
, stderr
);
1339 fprintf(stderr
, "\n");
1344 if (dst
.regClass() == v1
) {
1345 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1346 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1347 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1348 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1349 } else if (dst
.regClass() == v2
) {
1350 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1351 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1352 } else if (dst
.regClass() == s2
) {
1353 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1354 } else if (dst
.regClass() == s1
) {
1355 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1357 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1358 nir_print_instr(&instr
->instr
, stderr
);
1359 fprintf(stderr
, "\n");
1364 if (dst
.regClass() == v1
) {
1365 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1366 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1367 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1368 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1369 } else if (dst
.regClass() == v2
) {
1370 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1371 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1372 } else if (dst
.regClass() == s1
) {
1373 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1374 } else if (dst
.regClass() == s2
) {
1375 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1377 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1378 nir_print_instr(&instr
->instr
, stderr
);
1379 fprintf(stderr
, "\n");
1384 if (dst
.regClass() == v1
) {
1385 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1386 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1387 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1388 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1389 } else if (dst
.regClass() == v2
) {
1390 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1391 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1392 } else if (dst
.regClass() == s1
) {
1393 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1394 } else if (dst
.regClass() == s2
) {
1395 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1397 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1398 nir_print_instr(&instr
->instr
, stderr
);
1399 fprintf(stderr
, "\n");
1403 case nir_op_find_lsb
: {
1404 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1405 if (src
.regClass() == s1
) {
1406 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1407 } else if (src
.regClass() == v1
) {
1408 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1409 } else if (src
.regClass() == s2
) {
1410 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1412 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1413 nir_print_instr(&instr
->instr
, stderr
);
1414 fprintf(stderr
, "\n");
1418 case nir_op_ufind_msb
:
1419 case nir_op_ifind_msb
: {
1420 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1421 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1422 aco_opcode op
= src
.regClass() == s2
?
1423 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1424 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1425 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1427 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1428 Operand(src
.size() * 32u - 1u), msb_rev
);
1429 Temp msb
= sub
.def(0).getTemp();
1430 Temp carry
= sub
.def(1).getTemp();
1432 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1433 } else if (src
.regClass() == v1
) {
1434 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1435 Temp msb_rev
= bld
.tmp(v1
);
1436 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1437 Temp msb
= bld
.tmp(v1
);
1438 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1439 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1441 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1442 nir_print_instr(&instr
->instr
, stderr
);
1443 fprintf(stderr
, "\n");
1447 case nir_op_bitfield_reverse
: {
1448 if (dst
.regClass() == s1
) {
1449 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1450 } else if (dst
.regClass() == v1
) {
1451 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1453 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1454 nir_print_instr(&instr
->instr
, stderr
);
1455 fprintf(stderr
, "\n");
1460 if (dst
.regClass() == s1
) {
1461 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1465 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1466 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1467 if (dst
.regClass() == v1
) {
1468 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1472 assert(src0
.size() == 2 && src1
.size() == 2);
1473 Temp src00
= bld
.tmp(src0
.type(), 1);
1474 Temp src01
= bld
.tmp(dst
.type(), 1);
1475 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1476 Temp src10
= bld
.tmp(src1
.type(), 1);
1477 Temp src11
= bld
.tmp(dst
.type(), 1);
1478 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1480 if (dst
.regClass() == s2
) {
1481 Temp carry
= bld
.tmp(s1
);
1482 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1483 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1484 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1485 } else if (dst
.regClass() == v2
) {
1486 Temp dst0
= bld
.tmp(v1
);
1487 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1488 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1489 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1491 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1492 nir_print_instr(&instr
->instr
, stderr
);
1493 fprintf(stderr
, "\n");
1497 case nir_op_uadd_sat
: {
1498 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1499 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1500 if (dst
.regClass() == s1
) {
1501 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1502 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1504 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1505 } else if (dst
.regClass() == v1
) {
1506 if (ctx
->options
->chip_class
>= GFX9
) {
1507 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1508 add
->operands
[0] = Operand(src0
);
1509 add
->operands
[1] = Operand(src1
);
1510 add
->definitions
[0] = Definition(dst
);
1512 ctx
->block
->instructions
.emplace_back(std::move(add
));
1514 if (src1
.regClass() != v1
)
1515 std::swap(src0
, src1
);
1516 assert(src1
.regClass() == v1
);
1517 Temp tmp
= bld
.tmp(v1
);
1518 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1519 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1523 nir_print_instr(&instr
->instr
, stderr
);
1524 fprintf(stderr
, "\n");
1528 case nir_op_uadd_carry
: {
1529 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1530 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1531 if (dst
.regClass() == s1
) {
1532 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1535 if (dst
.regClass() == v1
) {
1536 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1537 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1541 Temp src00
= bld
.tmp(src0
.type(), 1);
1542 Temp src01
= bld
.tmp(dst
.type(), 1);
1543 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1544 Temp src10
= bld
.tmp(src1
.type(), 1);
1545 Temp src11
= bld
.tmp(dst
.type(), 1);
1546 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1547 if (dst
.regClass() == s2
) {
1548 Temp carry
= bld
.tmp(s1
);
1549 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1550 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1551 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1552 } else if (dst
.regClass() == v2
) {
1553 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1554 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1555 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1556 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1558 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1559 nir_print_instr(&instr
->instr
, stderr
);
1560 fprintf(stderr
, "\n");
1565 if (dst
.regClass() == s1
) {
1566 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1570 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1571 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1572 if (dst
.regClass() == v1
) {
1573 bld
.vsub32(Definition(dst
), src0
, src1
);
1577 Temp src00
= bld
.tmp(src0
.type(), 1);
1578 Temp src01
= bld
.tmp(dst
.type(), 1);
1579 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1580 Temp src10
= bld
.tmp(src1
.type(), 1);
1581 Temp src11
= bld
.tmp(dst
.type(), 1);
1582 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1583 if (dst
.regClass() == s2
) {
1584 Temp carry
= bld
.tmp(s1
);
1585 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1586 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1587 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1588 } else if (dst
.regClass() == v2
) {
1589 Temp lower
= bld
.tmp(v1
);
1590 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1591 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1592 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1594 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1595 nir_print_instr(&instr
->instr
, stderr
);
1596 fprintf(stderr
, "\n");
1600 case nir_op_usub_borrow
: {
1601 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1602 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1603 if (dst
.regClass() == s1
) {
1604 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1606 } else if (dst
.regClass() == v1
) {
1607 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1608 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1612 Temp src00
= bld
.tmp(src0
.type(), 1);
1613 Temp src01
= bld
.tmp(dst
.type(), 1);
1614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1615 Temp src10
= bld
.tmp(src1
.type(), 1);
1616 Temp src11
= bld
.tmp(dst
.type(), 1);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1618 if (dst
.regClass() == s2
) {
1619 Temp borrow
= bld
.tmp(s1
);
1620 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1621 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1623 } else if (dst
.regClass() == v2
) {
1624 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1625 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1626 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1629 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1630 nir_print_instr(&instr
->instr
, stderr
);
1631 fprintf(stderr
, "\n");
1636 if (dst
.regClass() == v1
) {
1637 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1638 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1639 } else if (dst
.regClass() == s1
) {
1640 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1642 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1643 nir_print_instr(&instr
->instr
, stderr
);
1644 fprintf(stderr
, "\n");
1648 case nir_op_umul_high
: {
1649 if (dst
.regClass() == v1
) {
1650 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1651 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1652 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1653 } else if (dst
.regClass() == s1
) {
1654 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1655 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1656 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1658 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1659 nir_print_instr(&instr
->instr
, stderr
);
1660 fprintf(stderr
, "\n");
1664 case nir_op_imul_high
: {
1665 if (dst
.regClass() == v1
) {
1666 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1667 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1668 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1669 } else if (dst
.regClass() == s1
) {
1670 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1671 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1672 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1675 nir_print_instr(&instr
->instr
, stderr
);
1676 fprintf(stderr
, "\n");
1681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1682 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1683 if (dst
.regClass() == v2b
) {
1684 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1685 } else if (dst
.regClass() == v1
) {
1686 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1687 } else if (dst
.regClass() == v2
) {
1688 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1690 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1691 nir_print_instr(&instr
->instr
, stderr
);
1692 fprintf(stderr
, "\n");
1697 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1698 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1699 if (dst
.regClass() == v2b
) {
1700 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1701 } else if (dst
.regClass() == v1
) {
1702 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1703 } else if (dst
.regClass() == v2
) {
1704 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1706 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1707 nir_print_instr(&instr
->instr
, stderr
);
1708 fprintf(stderr
, "\n");
1713 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1714 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1715 if (dst
.regClass() == v2b
) {
1716 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1717 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1719 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1720 } else if (dst
.regClass() == v1
) {
1721 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1722 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1724 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1725 } else if (dst
.regClass() == v2
) {
1726 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1727 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1728 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1731 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1732 nir_print_instr(&instr
->instr
, stderr
);
1733 fprintf(stderr
, "\n");
1738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1739 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1740 if (dst
.regClass() == v2b
) {
1741 // TODO: check fp_mode.must_flush_denorms16_64
1742 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1743 } else if (dst
.regClass() == v1
) {
1744 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1745 } else if (dst
.regClass() == v2
) {
1746 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1747 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1748 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1750 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1753 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1754 nir_print_instr(&instr
->instr
, stderr
);
1755 fprintf(stderr
, "\n");
1760 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1761 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1762 if (dst
.regClass() == v2b
) {
1763 // TODO: check fp_mode.must_flush_denorms16_64
1764 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1765 } else if (dst
.regClass() == v1
) {
1766 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1767 } else if (dst
.regClass() == v2
) {
1768 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1769 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1770 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1772 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1776 nir_print_instr(&instr
->instr
, stderr
);
1777 fprintf(stderr
, "\n");
1781 case nir_op_fmax3
: {
1782 if (dst
.regClass() == v2b
) {
1783 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1784 } else if (dst
.regClass() == v1
) {
1785 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1793 case nir_op_fmin3
: {
1794 if (dst
.regClass() == v2b
) {
1795 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1796 } else if (dst
.regClass() == v1
) {
1797 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1799 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1800 nir_print_instr(&instr
->instr
, stderr
);
1801 fprintf(stderr
, "\n");
1805 case nir_op_fmed3
: {
1806 if (dst
.regClass() == v2b
) {
1807 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1808 } else if (dst
.regClass() == v1
) {
1809 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1811 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1812 nir_print_instr(&instr
->instr
, stderr
);
1813 fprintf(stderr
, "\n");
1817 case nir_op_umax3
: {
1818 if (dst
.size() == 1) {
1819 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1821 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1822 nir_print_instr(&instr
->instr
, stderr
);
1823 fprintf(stderr
, "\n");
1827 case nir_op_umin3
: {
1828 if (dst
.size() == 1) {
1829 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1831 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1832 nir_print_instr(&instr
->instr
, stderr
);
1833 fprintf(stderr
, "\n");
1837 case nir_op_umed3
: {
1838 if (dst
.size() == 1) {
1839 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1841 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1842 nir_print_instr(&instr
->instr
, stderr
);
1843 fprintf(stderr
, "\n");
1847 case nir_op_imax3
: {
1848 if (dst
.size() == 1) {
1849 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1851 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1852 nir_print_instr(&instr
->instr
, stderr
);
1853 fprintf(stderr
, "\n");
1857 case nir_op_imin3
: {
1858 if (dst
.size() == 1) {
1859 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1861 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1862 nir_print_instr(&instr
->instr
, stderr
);
1863 fprintf(stderr
, "\n");
1867 case nir_op_imed3
: {
1868 if (dst
.size() == 1) {
1869 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1872 nir_print_instr(&instr
->instr
, stderr
);
1873 fprintf(stderr
, "\n");
1877 case nir_op_cube_face_coord
: {
1878 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1879 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1880 emit_extract_vector(ctx
, in
, 1, v1
),
1881 emit_extract_vector(ctx
, in
, 2, v1
) };
1882 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1883 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1884 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1885 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1886 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1887 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1888 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1891 case nir_op_cube_face_index
: {
1892 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1893 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1894 emit_extract_vector(ctx
, in
, 1, v1
),
1895 emit_extract_vector(ctx
, in
, 2, v1
) };
1896 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1899 case nir_op_bcsel
: {
1900 emit_bcsel(ctx
, instr
, dst
);
1904 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1905 if (dst
.regClass() == v2b
) {
1906 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1907 } else if (dst
.regClass() == v1
) {
1908 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1909 } else if (dst
.regClass() == v2
) {
1910 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1912 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1913 nir_print_instr(&instr
->instr
, stderr
);
1914 fprintf(stderr
, "\n");
1919 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1920 if (dst
.regClass() == v2b
) {
1921 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1922 } else if (dst
.regClass() == v1
) {
1923 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1924 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1925 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1926 } else if (dst
.regClass() == v2
) {
1927 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1928 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1929 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1931 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1932 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1934 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1935 nir_print_instr(&instr
->instr
, stderr
);
1936 fprintf(stderr
, "\n");
1941 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1942 if (dst
.regClass() == v2b
) {
1943 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1944 } else if (dst
.regClass() == v1
) {
1945 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1946 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1947 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1948 } else if (dst
.regClass() == v2
) {
1949 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1950 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1951 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1952 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1953 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1954 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1956 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1957 nir_print_instr(&instr
->instr
, stderr
);
1958 fprintf(stderr
, "\n");
1963 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1964 if (dst
.regClass() == v2b
) {
1965 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1966 } else if (dst
.regClass() == v1
) {
1967 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1968 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1969 // TODO: confirm that this holds under any circumstances
1970 } else if (dst
.regClass() == v2
) {
1971 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1972 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1975 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1976 nir_print_instr(&instr
->instr
, stderr
);
1977 fprintf(stderr
, "\n");
1981 case nir_op_flog2
: {
1982 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1983 if (dst
.regClass() == v2b
) {
1984 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1985 } else if (dst
.regClass() == v1
) {
1986 emit_log2(ctx
, bld
, Definition(dst
), src
);
1988 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1989 nir_print_instr(&instr
->instr
, stderr
);
1990 fprintf(stderr
, "\n");
1995 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1996 if (dst
.regClass() == v2b
) {
1997 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1998 } else if (dst
.regClass() == v1
) {
1999 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2000 } else if (dst
.regClass() == v2
) {
2001 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2003 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2004 nir_print_instr(&instr
->instr
, stderr
);
2005 fprintf(stderr
, "\n");
2009 case nir_op_fexp2
: {
2010 if (dst
.regClass() == v2b
) {
2011 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2012 } else if (dst
.regClass() == v1
) {
2013 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2015 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2016 nir_print_instr(&instr
->instr
, stderr
);
2017 fprintf(stderr
, "\n");
2021 case nir_op_fsqrt
: {
2022 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2023 if (dst
.regClass() == v2b
) {
2024 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2025 } else if (dst
.regClass() == v1
) {
2026 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2027 } else if (dst
.regClass() == v2
) {
2028 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2030 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2031 nir_print_instr(&instr
->instr
, stderr
);
2032 fprintf(stderr
, "\n");
2036 case nir_op_ffract
: {
2037 if (dst
.regClass() == v2b
) {
2038 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2039 } else if (dst
.regClass() == v1
) {
2040 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2041 } else if (dst
.regClass() == v2
) {
2042 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2044 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2045 nir_print_instr(&instr
->instr
, stderr
);
2046 fprintf(stderr
, "\n");
2050 case nir_op_ffloor
: {
2051 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2052 if (dst
.regClass() == v2b
) {
2053 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2054 } else if (dst
.regClass() == v1
) {
2055 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2056 } else if (dst
.regClass() == v2
) {
2057 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2059 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2060 nir_print_instr(&instr
->instr
, stderr
);
2061 fprintf(stderr
, "\n");
2065 case nir_op_fceil
: {
2066 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2067 if (dst
.regClass() == v2b
) {
2068 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2069 } else if (dst
.regClass() == v1
) {
2070 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2071 } else if (dst
.regClass() == v2
) {
2072 if (ctx
->options
->chip_class
>= GFX7
) {
2073 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2075 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2076 /* trunc = trunc(src0)
2077 * if (src0 > 0.0 && src0 != trunc)
2080 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2081 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2082 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2083 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2084 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2085 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2086 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2090 nir_print_instr(&instr
->instr
, stderr
);
2091 fprintf(stderr
, "\n");
2095 case nir_op_ftrunc
: {
2096 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2097 if (dst
.regClass() == v2b
) {
2098 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2099 } else if (dst
.regClass() == v1
) {
2100 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2101 } else if (dst
.regClass() == v2
) {
2102 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2104 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2105 nir_print_instr(&instr
->instr
, stderr
);
2106 fprintf(stderr
, "\n");
2110 case nir_op_fround_even
: {
2111 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2112 if (dst
.regClass() == v2b
) {
2113 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2114 } else if (dst
.regClass() == v1
) {
2115 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2116 } else if (dst
.regClass() == v2
) {
2117 if (ctx
->options
->chip_class
>= GFX7
) {
2118 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2120 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2121 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2122 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2124 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2125 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2126 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2127 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2128 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2129 tmp
= sub
->definitions
[0].getTemp();
2131 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2132 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2133 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2134 Temp cond
= vop3
->definitions
[0].getTemp();
2136 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2137 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2138 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2139 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2141 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2144 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2145 nir_print_instr(&instr
->instr
, stderr
);
2146 fprintf(stderr
, "\n");
2152 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2153 aco_ptr
<Instruction
> norm
;
2154 if (dst
.regClass() == v2b
) {
2155 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2156 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2157 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2158 bld
.vop1(opcode
, Definition(dst
), tmp
);
2159 } else if (dst
.regClass() == v1
) {
2160 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2161 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2163 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2164 if (ctx
->options
->chip_class
< GFX9
)
2165 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2167 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2168 bld
.vop1(opcode
, Definition(dst
), tmp
);
2170 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2171 nir_print_instr(&instr
->instr
, stderr
);
2172 fprintf(stderr
, "\n");
2176 case nir_op_ldexp
: {
2177 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2178 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2179 if (dst
.regClass() == v2b
) {
2180 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2181 } else if (dst
.regClass() == v1
) {
2182 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2183 } else if (dst
.regClass() == v2
) {
2184 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2186 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2187 nir_print_instr(&instr
->instr
, stderr
);
2188 fprintf(stderr
, "\n");
2192 case nir_op_frexp_sig
: {
2193 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2194 if (dst
.regClass() == v2b
) {
2195 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2196 } else if (dst
.regClass() == v1
) {
2197 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2198 } else if (dst
.regClass() == v2
) {
2199 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2201 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2202 nir_print_instr(&instr
->instr
, stderr
);
2203 fprintf(stderr
, "\n");
2207 case nir_op_frexp_exp
: {
2208 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2209 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2210 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2211 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2212 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2213 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2214 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2215 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2216 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2218 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2219 nir_print_instr(&instr
->instr
, stderr
);
2220 fprintf(stderr
, "\n");
2224 case nir_op_fsign
: {
2225 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2226 if (dst
.regClass() == v2b
) {
2227 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2228 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2229 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2230 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2231 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2232 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2233 } else if (dst
.regClass() == v1
) {
2234 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2235 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2236 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2237 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2238 } else if (dst
.regClass() == v2
) {
2239 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2240 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2241 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2243 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2244 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2245 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2247 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2249 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2250 nir_print_instr(&instr
->instr
, stderr
);
2251 fprintf(stderr
, "\n");
2256 case nir_op_f2f16_rtne
: {
2257 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2258 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2259 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2260 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2263 case nir_op_f2f16_rtz
: {
2264 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2265 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2266 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2267 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2270 case nir_op_f2f32
: {
2271 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2272 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2273 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2274 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2276 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2277 nir_print_instr(&instr
->instr
, stderr
);
2278 fprintf(stderr
, "\n");
2282 case nir_op_f2f64
: {
2283 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2284 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2285 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2286 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2289 case nir_op_i2f16
: {
2290 assert(dst
.regClass() == v2b
);
2291 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2292 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2293 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2294 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2295 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2296 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2299 case nir_op_i2f32
: {
2300 assert(dst
.size() == 1);
2301 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2302 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2303 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2304 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2307 case nir_op_i2f64
: {
2308 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2309 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2310 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2311 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2312 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2313 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2314 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2315 RegClass rc
= RegClass(src
.type(), 1);
2316 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2317 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2318 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2319 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2320 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2321 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2324 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2325 nir_print_instr(&instr
->instr
, stderr
);
2326 fprintf(stderr
, "\n");
2330 case nir_op_u2f16
: {
2331 assert(dst
.regClass() == v2b
);
2332 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2333 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2334 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2335 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2336 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2337 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2340 case nir_op_u2f32
: {
2341 assert(dst
.size() == 1);
2342 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2343 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2344 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2346 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2347 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2348 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2352 case nir_op_u2f64
: {
2353 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2354 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2355 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2356 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2357 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2358 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2359 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2360 RegClass rc
= RegClass(src
.type(), 1);
2361 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2362 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2363 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2364 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2365 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2366 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2368 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2369 nir_print_instr(&instr
->instr
, stderr
);
2370 fprintf(stderr
, "\n");
2375 case nir_op_f2i16
: {
2376 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2377 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2378 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2379 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2381 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2385 case nir_op_f2u16
: {
2386 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2387 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2388 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2389 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2391 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2394 case nir_op_f2i32
: {
2395 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2396 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2397 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2398 if (dst
.type() == RegType::vgpr
) {
2399 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2401 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2402 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2404 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2405 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2406 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2407 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2409 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2410 nir_print_instr(&instr
->instr
, stderr
);
2411 fprintf(stderr
, "\n");
2415 case nir_op_f2u32
: {
2416 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2417 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2418 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2419 if (dst
.type() == RegType::vgpr
) {
2420 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2422 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2423 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2425 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2426 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2427 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2428 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2430 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2431 nir_print_instr(&instr
->instr
, stderr
);
2432 fprintf(stderr
, "\n");
2436 case nir_op_f2i64
: {
2437 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2438 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2439 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2441 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2442 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2443 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2444 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2445 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2446 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2447 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2448 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2449 Temp new_exponent
= bld
.tmp(v1
);
2450 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2451 if (ctx
->program
->chip_class
>= GFX8
)
2452 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2454 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2455 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2456 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2458 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2459 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2460 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2461 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2462 Temp new_lower
= bld
.tmp(v1
);
2463 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2464 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2465 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2467 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2468 if (src
.type() == RegType::vgpr
)
2469 src
= bld
.as_uniform(src
);
2470 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2471 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2472 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2473 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2474 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2475 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2476 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2477 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2478 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2479 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2480 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2481 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2482 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2483 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2484 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2485 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2486 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2487 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2488 Temp borrow
= bld
.tmp(s1
);
2489 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2490 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2491 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2493 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2494 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2495 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2496 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2497 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2498 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2499 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2500 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2501 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2502 if (dst
.type() == RegType::sgpr
) {
2503 lower
= bld
.as_uniform(lower
);
2504 upper
= bld
.as_uniform(upper
);
2506 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2509 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2510 nir_print_instr(&instr
->instr
, stderr
);
2511 fprintf(stderr
, "\n");
2515 case nir_op_f2u64
: {
2516 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2517 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2518 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2520 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2521 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2522 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2523 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2524 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2525 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2526 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2527 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2528 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2529 Temp new_exponent
= bld
.tmp(v1
);
2530 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2531 if (ctx
->program
->chip_class
>= GFX8
)
2532 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2534 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2535 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2536 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2537 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2538 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2539 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2540 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2543 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2544 if (src
.type() == RegType::vgpr
)
2545 src
= bld
.as_uniform(src
);
2546 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2547 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2548 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2549 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2550 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2551 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2552 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2553 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2554 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2555 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2556 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2557 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2558 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2559 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2560 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2561 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2562 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2563 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2565 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2566 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2567 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2568 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2569 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2570 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2571 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2572 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2573 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2574 if (dst
.type() == RegType::sgpr
) {
2575 lower
= bld
.as_uniform(lower
);
2576 upper
= bld
.as_uniform(upper
);
2578 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2581 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2582 nir_print_instr(&instr
->instr
, stderr
);
2583 fprintf(stderr
, "\n");
2587 case nir_op_b2f16
: {
2588 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2589 assert(src
.regClass() == bld
.lm
);
2591 if (dst
.regClass() == s1
) {
2592 src
= bool_to_scalar_condition(ctx
, src
);
2593 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2594 } else if (dst
.regClass() == v2b
) {
2595 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2596 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2598 unreachable("Wrong destination register class for nir_op_b2f16.");
2602 case nir_op_b2f32
: {
2603 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2604 assert(src
.regClass() == bld
.lm
);
2606 if (dst
.regClass() == s1
) {
2607 src
= bool_to_scalar_condition(ctx
, src
);
2608 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2609 } else if (dst
.regClass() == v1
) {
2610 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2612 unreachable("Wrong destination register class for nir_op_b2f32.");
2616 case nir_op_b2f64
: {
2617 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2618 assert(src
.regClass() == bld
.lm
);
2620 if (dst
.regClass() == s2
) {
2621 src
= bool_to_scalar_condition(ctx
, src
);
2622 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2623 } else if (dst
.regClass() == v2
) {
2624 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2625 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2626 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2628 unreachable("Wrong destination register class for nir_op_b2f64.");
2635 case nir_op_i2i64
: {
2636 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2637 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2643 case nir_op_u2u64
: {
2644 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2645 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2649 case nir_op_b2i32
: {
2650 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2651 assert(src
.regClass() == bld
.lm
);
2653 if (dst
.regClass() == s1
) {
2654 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2655 bool_to_scalar_condition(ctx
, src
, dst
);
2656 } else if (dst
.regClass() == v1
) {
2657 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2659 unreachable("Invalid register class for b2i32");
2665 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2666 assert(dst
.regClass() == bld
.lm
);
2668 if (src
.type() == RegType::vgpr
) {
2669 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2670 assert(dst
.regClass() == bld
.lm
);
2671 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2672 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2674 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2676 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2677 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2679 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2680 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2682 bool_to_vector_condition(ctx
, tmp
, dst
);
2686 case nir_op_pack_64_2x32_split
: {
2687 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2688 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2690 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2693 case nir_op_unpack_64_2x32_split_x
:
2694 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2696 case nir_op_unpack_64_2x32_split_y
:
2697 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2699 case nir_op_unpack_32_2x16_split_x
:
2700 if (dst
.type() == RegType::vgpr
) {
2701 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2703 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2706 case nir_op_unpack_32_2x16_split_y
:
2707 if (dst
.type() == RegType::vgpr
) {
2708 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2710 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2713 case nir_op_pack_32_2x16_split
: {
2714 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2715 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2716 if (dst
.regClass() == v1
) {
2717 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2718 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2719 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2721 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2722 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2723 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2727 case nir_op_pack_half_2x16
: {
2728 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2730 if (dst
.regClass() == v1
) {
2731 Temp src0
= bld
.tmp(v1
);
2732 Temp src1
= bld
.tmp(v1
);
2733 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2734 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2735 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2737 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2738 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2739 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2741 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2742 nir_print_instr(&instr
->instr
, stderr
);
2743 fprintf(stderr
, "\n");
2747 case nir_op_unpack_half_2x16_split_x
: {
2748 if (dst
.regClass() == v1
) {
2749 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2751 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2752 nir_print_instr(&instr
->instr
, stderr
);
2753 fprintf(stderr
, "\n");
2757 case nir_op_unpack_half_2x16_split_y
: {
2758 if (dst
.regClass() == v1
) {
2759 /* TODO: use SDWA here */
2760 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2761 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2763 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2764 nir_print_instr(&instr
->instr
, stderr
);
2765 fprintf(stderr
, "\n");
2769 case nir_op_fquantize2f16
: {
2770 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2771 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2774 if (ctx
->program
->chip_class
>= GFX8
) {
2775 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2776 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2777 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2779 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2780 * so compare the result and flush to 0 if it's smaller.
2782 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2783 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2784 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2785 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2786 cmp_res
= vop3
->definitions
[0].getTemp();
2789 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2790 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2791 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2793 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2798 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2799 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2801 if (dst
.regClass() == s1
) {
2802 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2803 } else if (dst
.regClass() == v1
) {
2804 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2806 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2807 nir_print_instr(&instr
->instr
, stderr
);
2808 fprintf(stderr
, "\n");
2812 case nir_op_bitfield_select
: {
2813 /* (mask & insert) | (~mask & base) */
2814 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2815 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2816 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2818 /* dst = (insert & bitmask) | (base & ~bitmask) */
2819 if (dst
.regClass() == s1
) {
2820 aco_ptr
<Instruction
> sop2
;
2821 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2822 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2824 if (const_insert
&& const_bitmask
) {
2825 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2827 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2828 lhs
= Operand(insert
);
2832 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2833 if (const_base
&& const_bitmask
) {
2834 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2836 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2837 rhs
= Operand(base
);
2840 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2842 } else if (dst
.regClass() == v1
) {
2843 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2844 base
= as_vgpr(ctx
, base
);
2845 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2846 insert
= as_vgpr(ctx
, insert
);
2848 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2851 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2852 nir_print_instr(&instr
->instr
, stderr
);
2853 fprintf(stderr
, "\n");
2859 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2860 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2861 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2863 if (dst
.type() == RegType::sgpr
) {
2865 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2866 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2867 if (const_offset
&& const_bits
) {
2868 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2869 extract
= Operand(const_extract
);
2873 width
= Operand(const_bits
->u32
<< 16);
2875 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2877 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2881 if (dst
.regClass() == s1
) {
2882 if (instr
->op
== nir_op_ubfe
)
2883 opcode
= aco_opcode::s_bfe_u32
;
2885 opcode
= aco_opcode::s_bfe_i32
;
2886 } else if (dst
.regClass() == s2
) {
2887 if (instr
->op
== nir_op_ubfe
)
2888 opcode
= aco_opcode::s_bfe_u64
;
2890 opcode
= aco_opcode::s_bfe_i64
;
2892 unreachable("Unsupported BFE bit size");
2895 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2899 if (dst
.regClass() == v1
) {
2900 if (instr
->op
== nir_op_ubfe
)
2901 opcode
= aco_opcode::v_bfe_u32
;
2903 opcode
= aco_opcode::v_bfe_i32
;
2905 unreachable("Unsupported BFE bit size");
2908 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2912 case nir_op_bit_count
: {
2913 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2914 if (src
.regClass() == s1
) {
2915 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2916 } else if (src
.regClass() == v1
) {
2917 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2918 } else if (src
.regClass() == v2
) {
2919 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2920 emit_extract_vector(ctx
, src
, 1, v1
),
2921 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2922 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2923 } else if (src
.regClass() == s2
) {
2924 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2926 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2927 nir_print_instr(&instr
->instr
, stderr
);
2928 fprintf(stderr
, "\n");
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2941 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2945 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2949 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2953 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2957 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2958 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2960 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2961 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2965 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2966 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2968 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2969 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2973 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2977 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2982 case nir_op_fddx_fine
:
2983 case nir_op_fddy_fine
:
2984 case nir_op_fddx_coarse
:
2985 case nir_op_fddy_coarse
: {
2986 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2987 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2988 if (instr
->op
== nir_op_fddx_fine
) {
2989 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2990 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2991 } else if (instr
->op
== nir_op_fddy_fine
) {
2992 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2993 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2995 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2996 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2997 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2999 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3003 if (ctx
->program
->chip_class
>= GFX8
) {
3004 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3005 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3007 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3008 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3009 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3011 emit_wqm(ctx
, tmp
, dst
, true);
3015 fprintf(stderr
, "Unknown NIR ALU instr: ");
3016 nir_print_instr(&instr
->instr
, stderr
);
3017 fprintf(stderr
, "\n");
3021 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3023 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3025 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3026 // which get truncated the lsb if double and msb if int
3027 // for now, we only use s_mov_b64 with 64bit inline constants
3028 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3029 assert(dst
.type() == RegType::sgpr
);
3031 Builder
bld(ctx
->program
, ctx
->block
);
3033 if (instr
->def
.bit_size
== 1) {
3034 assert(dst
.regClass() == bld
.lm
);
3035 int val
= instr
->value
[0].b
? -1 : 0;
3036 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3037 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3038 } else if (instr
->def
.bit_size
== 8) {
3039 /* ensure that the value is correctly represented in the low byte of the register */
3040 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3041 } else if (instr
->def
.bit_size
== 16) {
3042 /* ensure that the value is correctly represented in the low half of the register */
3043 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3044 } else if (dst
.size() == 1) {
3045 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3047 assert(dst
.size() != 1);
3048 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3049 if (instr
->def
.bit_size
== 64)
3050 for (unsigned i
= 0; i
< dst
.size(); i
++)
3051 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3053 for (unsigned i
= 0; i
< dst
.size(); i
++)
3054 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3056 vec
->definitions
[0] = Definition(dst
);
3057 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3061 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3063 uint32_t new_mask
= 0;
3064 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3065 if (mask
& (1u << i
))
3066 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3070 struct LoadEmitInfo
{
3073 unsigned num_components
;
3074 unsigned component_size
;
3075 Temp resource
= Temp(0, s1
);
3076 unsigned component_stride
= 0;
3077 unsigned const_offset
= 0;
3078 unsigned align_mul
= 0;
3079 unsigned align_offset
= 0;
3082 unsigned swizzle_component_size
= 0;
3083 barrier_interaction barrier
= barrier_none
;
3084 bool can_reorder
= true;
3085 Temp soffset
= Temp(0, s1
);
3088 using LoadCallback
= Temp(*)(
3089 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3090 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3092 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3093 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3095 unsigned load_size
= info
->num_components
* info
->component_size
;
3096 unsigned component_size
= info
->component_size
;
3098 unsigned num_vals
= 0;
3099 Temp vals
[info
->dst
.bytes()];
3101 unsigned const_offset
= info
->const_offset
;
3103 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3104 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3106 unsigned bytes_read
= 0;
3107 while (bytes_read
< load_size
) {
3108 unsigned bytes_needed
= load_size
- bytes_read
;
3110 /* add buffer for unaligned loads */
3111 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3114 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3115 if (info
->component_stride
) {
3116 assert(supports_8bit_16bit_loads
&& "unimplemented");
3120 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3121 bytes_needed
= align(bytes_needed
, 4);
3128 if (info
->swizzle_component_size
)
3129 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3130 if (info
->component_stride
)
3131 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3133 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3135 /* reduce constant offset */
3136 Operand offset
= info
->offset
;
3137 unsigned reduced_const_offset
= const_offset
;
3138 bool remove_const_offset_completely
= need_to_align_offset
;
3139 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3140 unsigned to_add
= const_offset
;
3141 if (remove_const_offset_completely
) {
3142 reduced_const_offset
= 0;
3144 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3145 reduced_const_offset
%= max_const_offset_plus_one
;
3147 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3148 if (offset
.isConstant()) {
3149 offset
= Operand(offset
.constantValue() + to_add
);
3150 } else if (offset_tmp
.regClass() == s1
) {
3151 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3152 offset_tmp
, Operand(to_add
));
3153 } else if (offset_tmp
.regClass() == v1
) {
3154 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3156 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3157 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3158 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3160 if (offset_tmp
.regClass() == s2
) {
3161 Temp carry
= bld
.tmp(s1
);
3162 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3163 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3164 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3166 Temp new_lo
= bld
.tmp(v1
);
3167 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3168 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3169 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3174 /* align offset down if needed */
3175 Operand aligned_offset
= offset
;
3176 if (need_to_align_offset
) {
3177 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3178 if (offset
.isConstant()) {
3179 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3180 } else if (offset_tmp
.regClass() == s1
) {
3181 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3182 } else if (offset_tmp
.regClass() == s2
) {
3183 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3184 } else if (offset_tmp
.regClass() == v1
) {
3185 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3186 } else if (offset_tmp
.regClass() == v2
) {
3187 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3188 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3189 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3190 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3193 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3194 bld
.copy(bld
.def(s1
), aligned_offset
);
3196 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3197 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3198 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3200 /* the callback wrote directly to dst */
3201 if (val
== info
->dst
) {
3202 assert(num_vals
== 0);
3203 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3207 /* shift result right if needed */
3208 if (info
->component_size
< 4 && byte_align_loads
) {
3209 Operand
align((uint32_t)byte_align
);
3210 if (byte_align
== -1) {
3211 if (offset
.isConstant())
3212 align
= Operand(offset
.constantValue() % 4u);
3213 else if (offset
.size() == 2)
3214 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3219 assert(val
.bytes() >= load_size
&& "unimplemented");
3220 if (val
.type() == RegType::sgpr
)
3221 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3223 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3227 /* add result to list and advance */
3228 if (info
->component_stride
) {
3229 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3230 const_offset
+= info
->component_stride
;
3231 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3233 const_offset
+= val
.bytes();
3234 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3236 bytes_read
+= val
.bytes();
3237 vals
[num_vals
++] = val
;
3240 /* create array of components */
3241 unsigned components_split
= 0;
3242 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3243 bool has_vgprs
= false;
3244 for (unsigned i
= 0; i
< num_vals
;) {
3246 unsigned num_tmps
= 0;
3247 unsigned tmp_size
= 0;
3248 RegType reg_type
= RegType::sgpr
;
3249 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3250 if (vals
[i
].type() == RegType::vgpr
)
3251 reg_type
= RegType::vgpr
;
3252 tmp_size
+= vals
[i
].bytes();
3253 tmp
[num_tmps
++] = vals
[i
++];
3256 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3257 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3258 for (unsigned i
= 0; i
< num_vals
; i
++)
3259 vec
->operands
[i
] = Operand(tmp
[i
]);
3260 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3261 vec
->definitions
[0] = Definition(tmp
[0]);
3262 bld
.insert(std::move(vec
));
3265 if (tmp
[0].bytes() % component_size
) {
3267 assert(i
== num_vals
);
3268 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3269 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3272 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3274 unsigned start
= components_split
;
3276 if (tmp_size
== elem_rc
.bytes()) {
3277 allocated_vec
[components_split
++] = tmp
[0];
3279 assert(tmp_size
% elem_rc
.bytes() == 0);
3280 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3281 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3282 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3283 Temp component
= bld
.tmp(elem_rc
);
3284 allocated_vec
[components_split
++] = component
;
3285 split
->definitions
[i
] = Definition(component
);
3287 split
->operands
[0] = Operand(tmp
[0]);
3288 bld
.insert(std::move(split
));
3291 /* try to p_as_uniform early so we can create more optimizable code and
3292 * also update allocated_vec */
3293 for (unsigned j
= start
; j
< components_split
; j
++) {
3294 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3295 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3296 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3300 /* concatenate components and p_as_uniform() result if needed */
3301 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3302 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3304 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3306 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3307 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3308 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3309 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3311 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3312 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3313 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3314 vec
->definitions
[0] = Definition(tmp
);
3315 bld
.insert(std::move(vec
));
3316 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3318 vec
->definitions
[0] = Definition(info
->dst
);
3319 bld
.insert(std::move(vec
));
3323 Operand
load_lds_size_m0(Builder
& bld
)
3325 /* TODO: m0 does not need to be initialized on GFX9+ */
3326 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3329 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3330 Temp offset
, unsigned bytes_needed
,
3331 unsigned align
, unsigned const_offset
,
3334 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3336 Operand m
= load_lds_size_m0(bld
);
3338 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3339 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3344 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3345 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3347 op
= aco_opcode::ds_read_b128
;
3348 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3351 op
= aco_opcode::ds_read2_b64
;
3352 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3354 op
= aco_opcode::ds_read_b96
;
3355 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3357 op
= aco_opcode::ds_read_b64
;
3358 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3361 op
= aco_opcode::ds_read2_b32
;
3362 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3364 op
= aco_opcode::ds_read_b32
;
3365 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3367 op
= aco_opcode::ds_read_u16
;
3370 op
= aco_opcode::ds_read_u8
;
3373 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3374 if (const_offset
>= max_offset_plus_one
) {
3375 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3376 const_offset
%= max_offset_plus_one
;
3380 const_offset
/= (size
/ 2u);
3382 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3383 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3385 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3387 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3390 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3395 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3397 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3398 Temp offset
, unsigned bytes_needed
,
3399 unsigned align
, unsigned const_offset
,
3404 if (bytes_needed
<= 4) {
3406 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3407 } else if (bytes_needed
<= 8) {
3409 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3410 } else if (bytes_needed
<= 16) {
3412 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3413 } else if (bytes_needed
<= 32) {
3415 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3418 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3420 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3421 if (info
->resource
.id()) {
3422 load
->operands
[0] = Operand(info
->resource
);
3423 load
->operands
[1] = Operand(offset
);
3425 load
->operands
[0] = Operand(offset
);
3426 load
->operands
[1] = Operand(0u);
3428 RegClass
rc(RegType::sgpr
, size
);
3429 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3430 load
->definitions
[0] = Definition(val
);
3431 load
->glc
= info
->glc
;
3432 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3433 load
->barrier
= info
->barrier
;
3434 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3435 bld
.insert(std::move(load
));
3439 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3441 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3442 Temp offset
, unsigned bytes_needed
,
3443 unsigned align_
, unsigned const_offset
,
3446 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3447 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3449 if (info
->soffset
.id()) {
3450 if (soffset
.isTemp())
3451 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3452 soffset
= Operand(info
->soffset
);
3455 unsigned bytes_size
= 0;
3457 if (bytes_needed
== 1) {
3459 op
= aco_opcode::buffer_load_ubyte
;
3460 } else if (bytes_needed
== 2) {
3462 op
= aco_opcode::buffer_load_ushort
;
3463 } else if (bytes_needed
<= 4) {
3465 op
= aco_opcode::buffer_load_dword
;
3466 } else if (bytes_needed
<= 8) {
3468 op
= aco_opcode::buffer_load_dwordx2
;
3469 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3471 op
= aco_opcode::buffer_load_dwordx3
;
3474 op
= aco_opcode::buffer_load_dwordx4
;
3476 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3477 mubuf
->operands
[0] = Operand(info
->resource
);
3478 mubuf
->operands
[1] = vaddr
;
3479 mubuf
->operands
[2] = soffset
;
3480 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3481 mubuf
->glc
= info
->glc
;
3482 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3483 mubuf
->barrier
= info
->barrier
;
3484 mubuf
->can_reorder
= info
->can_reorder
;
3485 mubuf
->offset
= const_offset
;
3486 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3487 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3488 mubuf
->definitions
[0] = Definition(val
);
3489 bld
.insert(std::move(mubuf
));
3494 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3496 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3498 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3499 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3501 if (addr
.type() == RegType::vgpr
)
3502 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3503 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3506 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3507 Temp offset
, unsigned bytes_needed
,
3508 unsigned align_
, unsigned const_offset
,
3511 unsigned bytes_size
= 0;
3512 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3513 bool global
= bld
.program
->chip_class
>= GFX9
;
3515 if (bytes_needed
== 1) {
3517 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3518 } else if (bytes_needed
== 2) {
3520 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3521 } else if (bytes_needed
<= 4) {
3523 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3524 } else if (bytes_needed
<= 8) {
3526 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3527 } else if (bytes_needed
<= 12 && !mubuf
) {
3529 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3532 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3534 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3535 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3537 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3538 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3539 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3540 mubuf
->operands
[2] = Operand(0u);
3541 mubuf
->glc
= info
->glc
;
3544 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3545 mubuf
->disable_wqm
= false;
3546 mubuf
->barrier
= info
->barrier
;
3547 mubuf
->definitions
[0] = Definition(val
);
3548 bld
.insert(std::move(mubuf
));
3550 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3552 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3553 flat
->operands
[0] = Operand(offset
);
3554 flat
->operands
[1] = Operand(s1
);
3555 flat
->glc
= info
->glc
;
3556 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3557 flat
->barrier
= info
->barrier
;
3559 flat
->definitions
[0] = Definition(val
);
3560 bld
.insert(std::move(flat
));
3566 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3568 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3569 Temp address
, unsigned base_offset
, unsigned align
)
3571 assert(util_is_power_of_two_nonzero(align
));
3573 Builder
bld(ctx
->program
, ctx
->block
);
3575 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3576 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3577 info
.align_mul
= align
;
3578 info
.align_offset
= 0;
3579 info
.barrier
= barrier_shared
;
3580 info
.can_reorder
= false;
3581 info
.const_offset
= base_offset
;
3582 emit_lds_load(ctx
, bld
, &info
);
3587 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3592 Builder
bld(ctx
->program
, ctx
->block
);
3594 ASSERTED
bool is_subdword
= false;
3595 for (unsigned i
= 0; i
< count
; i
++)
3596 is_subdword
|= offsets
[i
] % 4;
3597 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3598 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3600 /* count == 1 fast path */
3602 if (dst_type
== RegType::sgpr
)
3603 dst
[0] = bld
.as_uniform(src
);
3605 dst
[0] = as_vgpr(ctx
, src
);
3609 for (unsigned i
= 0; i
< count
- 1; i
++)
3610 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3611 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3613 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3614 src
= as_vgpr(ctx
, src
);
3616 /* use allocated_vec if possible */
3617 auto it
= ctx
->allocated_vec
.find(src
.id());
3618 if (it
!= ctx
->allocated_vec
.end()) {
3619 unsigned total_size
= 0;
3620 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3621 total_size
+= it
->second
[i
].bytes();
3622 if (total_size
!= src
.bytes())
3625 unsigned elem_size
= it
->second
[0].bytes();
3627 for (unsigned i
= 0; i
< count
; i
++) {
3628 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3632 for (unsigned i
= 0; i
< count
; i
++) {
3633 unsigned start_idx
= offsets
[i
] / elem_size
;
3634 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3635 if (op_count
== 1) {
3636 if (dst_type
== RegType::sgpr
)
3637 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3639 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3643 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3644 for (unsigned j
= 0; j
< op_count
; j
++) {
3645 Temp tmp
= it
->second
[start_idx
+ j
];
3646 if (dst_type
== RegType::sgpr
)
3647 tmp
= bld
.as_uniform(tmp
);
3648 vec
->operands
[j
] = Operand(tmp
);
3650 vec
->definitions
[0] = Definition(dst
[i
]);
3651 bld
.insert(std::move(vec
));
3657 if (dst_type
== RegType::sgpr
)
3658 src
= bld
.as_uniform(src
);
3662 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3663 split
->operands
[0] = Operand(src
);
3664 for (unsigned i
= 0; i
< count
; i
++)
3665 split
->definitions
[i
] = Definition(dst
[i
]);
3666 bld
.insert(std::move(split
));
3669 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3670 int *start
, int *count
)
3672 unsigned start_elem
= ffs(todo_mask
) - 1;
3673 bool skip
= !(mask
& (1 << start_elem
));
3675 mask
= ~mask
& todo_mask
;
3679 u_bit_scan_consecutive_range(&mask
, start
, count
);
3684 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3686 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3689 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3690 Temp address
, unsigned base_offset
, unsigned align
)
3692 assert(util_is_power_of_two_nonzero(align
));
3693 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3695 Builder
bld(ctx
->program
, ctx
->block
);
3696 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3697 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3699 unsigned write_count
= 0;
3700 Temp write_datas
[32];
3701 unsigned offsets
[32];
3702 aco_opcode opcodes
[32];
3704 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3706 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3709 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3710 offsets
[write_count
] = offset
;
3711 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3713 advance_write_mask(&todo
, offset
, bytes
);
3717 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3718 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3719 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3720 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3722 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3723 aco_opcode op
= aco_opcode::num_opcodes
;
3724 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3725 op
= aco_opcode::ds_write_b128
;
3727 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3728 op
= aco_opcode::ds_write_b96
;
3730 } else if (bytes
>= 8 && aligned8
) {
3731 op
= aco_opcode::ds_write_b64
;
3733 } else if (bytes
>= 4 && aligned4
) {
3734 op
= aco_opcode::ds_write_b32
;
3736 } else if (bytes
>= 2 && aligned2
) {
3737 op
= aco_opcode::ds_write_b16
;
3739 } else if (bytes
>= 1) {
3740 op
= aco_opcode::ds_write_b8
;
3746 offsets
[write_count
] = offset
;
3747 opcodes
[write_count
] = op
;
3749 advance_write_mask(&todo
, offset
, bytes
);
3752 Operand m
= load_lds_size_m0(bld
);
3754 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3756 for (unsigned i
= 0; i
< write_count
; i
++) {
3757 aco_opcode op
= opcodes
[i
];
3758 if (op
== aco_opcode::num_opcodes
)
3761 Temp data
= write_datas
[i
];
3763 unsigned second
= write_count
;
3764 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3765 for (second
= i
+ 1; second
< write_count
; second
++) {
3766 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3767 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3768 opcodes
[second
] = aco_opcode::num_opcodes
;
3774 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3775 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3777 unsigned inline_offset
= base_offset
+ offsets
[i
];
3778 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3779 Temp address_offset
= address
;
3780 if (inline_offset
> max_offset
) {
3781 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3782 inline_offset
= offsets
[i
];
3784 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3787 Temp second_data
= write_datas
[second
];
3788 inline_offset
/= data
.bytes();
3789 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3791 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3796 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3798 unsigned align
= 16;
3800 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3806 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3811 return aco_opcode::buffer_store_byte
;
3814 return aco_opcode::buffer_store_short
;
3816 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3818 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3821 return aco_opcode::buffer_store_dwordx3
;
3823 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3825 unreachable("Unexpected store size");
3826 return aco_opcode::num_opcodes
;
3829 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3830 Temp data
, unsigned writemask
, int swizzle_element_size
,
3831 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3833 unsigned write_count_with_skips
= 0;
3836 /* determine how to split the data */
3837 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3840 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3841 offsets
[write_count_with_skips
] = offset
;
3842 if (skips
[write_count_with_skips
]) {
3843 advance_write_mask(&todo
, offset
, bytes
);
3844 write_count_with_skips
++;
3848 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3849 * larger than swizzle_element_size */
3850 bytes
= MIN2(bytes
, swizzle_element_size
);
3852 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3854 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3855 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3858 /* dword or larger stores have to be dword-aligned */
3859 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3860 unsigned align_offset
= instr
? nir_intrinsic_align_offset(instr
) : 0;
3861 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3862 if (bytes
>= 4 && !dword_aligned
)
3863 bytes
= MIN2(bytes
, 2);
3865 advance_write_mask(&todo
, offset
, bytes
);
3866 write_count_with_skips
++;
3869 /* actually split data */
3870 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3873 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3876 write_datas
[*write_count
] = write_datas
[i
];
3877 offsets
[*write_count
] = offsets
[i
];
3882 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3883 unsigned split_cnt
= 0u, Temp dst
= Temp())
3885 Builder
bld(ctx
->program
, ctx
->block
);
3886 unsigned dword_size
= elem_size_bytes
/ 4;
3889 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3891 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3892 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3893 instr
->definitions
[0] = Definition(dst
);
3895 for (unsigned i
= 0; i
< cnt
; ++i
) {
3897 assert(arr
[i
].size() == dword_size
);
3898 allocated_vec
[i
] = arr
[i
];
3899 instr
->operands
[i
] = Operand(arr
[i
]);
3901 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3902 allocated_vec
[i
] = zero
;
3903 instr
->operands
[i
] = Operand(zero
);
3907 bld
.insert(std::move(instr
));
3910 emit_split_vector(ctx
, dst
, split_cnt
);
3912 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3917 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3919 if (const_offset
>= 4096) {
3920 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3921 const_offset
%= 4096u;
3924 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3925 else if (unlikely(voffset
.regClass() == s1
))
3926 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3927 else if (likely(voffset
.regClass() == v1
))
3928 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3930 unreachable("Unsupported register class of voffset");
3933 return const_offset
;
3936 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3937 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3940 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3941 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3943 Builder
bld(ctx
->program
, ctx
->block
);
3944 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3945 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3947 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3948 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3949 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3950 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3951 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3953 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3956 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3957 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3958 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3960 Builder
bld(ctx
->program
, ctx
->block
);
3961 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3963 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3965 unsigned write_count
= 0;
3966 Temp write_datas
[32];
3967 unsigned offsets
[32];
3968 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3969 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3971 for (unsigned i
= 0; i
< write_count
; i
++) {
3972 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3973 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3977 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3978 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3979 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3981 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3982 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3983 assert(!!stride
!= allow_combining
);
3985 Builder
bld(ctx
->program
, ctx
->block
);
3987 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3988 info
.component_stride
= allow_combining
? 0 : stride
;
3990 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3991 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3992 info
.align_offset
= 0;
3993 info
.soffset
= soffset
;
3994 info
.const_offset
= base_const_offset
;
3995 emit_mubuf_load(ctx
, bld
, &info
);
3998 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4000 Builder
bld(ctx
->program
, ctx
->block
);
4001 Temp offset
= base_offset
.first
;
4002 unsigned const_offset
= base_offset
.second
;
4004 if (!nir_src_is_const(*off_src
)) {
4005 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4008 /* Calculate indirect offset with stride */
4009 if (likely(indirect_offset_arg
.regClass() == v1
))
4010 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4011 else if (indirect_offset_arg
.regClass() == s1
)
4012 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4014 unreachable("Unsupported register class of indirect offset");
4016 /* Add to the supplied base offset */
4017 if (offset
.id() == 0)
4018 offset
= with_stride
;
4019 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4020 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4021 else if (offset
.size() == 1 && with_stride
.size() == 1)
4022 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4024 unreachable("Unsupported register class of indirect offset");
4026 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4027 const_offset
+= const_offset_arg
* stride
;
4030 return std::make_pair(offset
, const_offset
);
4033 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4035 Builder
bld(ctx
->program
, ctx
->block
);
4038 if (off1
.first
.id() && off2
.first
.id()) {
4039 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4040 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4041 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4042 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4044 unreachable("Unsupported register class of indirect offset");
4046 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4049 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4052 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4054 Builder
bld(ctx
->program
, ctx
->block
);
4055 unsigned const_offset
= offs
.second
* multiplier
;
4057 if (!offs
.first
.id())
4058 return std::make_pair(offs
.first
, const_offset
);
4060 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4061 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4062 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4064 return std::make_pair(offset
, const_offset
);
4067 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4069 Builder
bld(ctx
->program
, ctx
->block
);
4071 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4072 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4073 /* component is in bytes */
4074 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4076 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4077 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4078 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4081 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4083 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4086 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4088 Builder
bld(ctx
->program
, ctx
->block
);
4090 switch (ctx
->shader
->info
.stage
) {
4091 case MESA_SHADER_TESS_CTRL
:
4092 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4093 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4094 case MESA_SHADER_TESS_EVAL
:
4095 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4097 unreachable("Unsupported stage in get_tess_rel_patch_id");
4101 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4103 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4104 Builder
bld(ctx
->program
, ctx
->block
);
4106 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4107 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4109 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4111 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4112 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4114 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4115 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4116 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4118 return offset_mul(ctx
, offs
, 4u);
4121 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4123 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4124 Builder
bld(ctx
->program
, ctx
->block
);
4126 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4127 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4128 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4129 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4131 std::pair
<Temp
, unsigned> offs
= instr
4132 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4133 : std::make_pair(Temp(), 0u);
4135 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4136 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4141 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4142 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4144 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4145 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4147 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4148 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4154 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4156 Builder
bld(ctx
->program
, ctx
->block
);
4158 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4159 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4161 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4163 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4164 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4165 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4167 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4168 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4173 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4175 Builder
bld(ctx
->program
, ctx
->block
);
4177 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4178 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4179 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4180 unsigned attr_stride
= ctx
->tcs_num_patches
;
4182 std::pair
<Temp
, unsigned> offs
= instr
4183 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4184 : std::make_pair(Temp(), 0u);
4186 if (const_base_offset
)
4187 offs
.second
+= const_base_offset
* attr_stride
;
4189 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4190 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4191 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4196 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4198 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4203 unsigned drv_loc
= nir_intrinsic_base(instr
);
4204 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4206 if (!nir_src_is_const(*off_src
)) {
4212 uint64_t slot
= per_vertex
4213 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4214 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4215 return (((uint64_t) 1) << slot
) & mask
;
4218 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4220 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4221 unsigned component
= nir_intrinsic_component(instr
);
4222 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4224 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4225 if (off_instr
->type
!= nir_instr_type_load_const
)
4228 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4229 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4231 if (instr
->src
[0].ssa
->bit_size
== 64)
4232 write_mask
= widen_mask(write_mask
, 2);
4234 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4236 for (unsigned i
= 0; i
< 8; ++i
) {
4237 if (write_mask
& (1 << i
)) {
4238 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4239 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4247 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4249 /* Only TCS per-vertex inputs are supported by this function.
4250 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4252 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4255 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4256 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4257 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4258 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4259 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4260 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4265 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4266 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4267 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4272 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4274 Builder
bld(ctx
->program
, ctx
->block
);
4276 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4277 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4278 bool indirect_write
;
4279 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4280 if (temp_only_input
&& !indirect_write
)
4284 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4285 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4286 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4287 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4289 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4290 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4291 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4292 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4293 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4297 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4298 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4299 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4300 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4301 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4302 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4303 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4304 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4305 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4306 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4307 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4308 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4309 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4311 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4312 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4314 unreachable("Invalid LS or ES stage");
4317 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4318 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4319 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4323 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4328 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4329 return off
== ctx
->tcs_tess_lvl_out_loc
||
4330 off
== ctx
->tcs_tess_lvl_in_loc
;
4334 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4336 uint64_t mask
= per_vertex
4337 ? ctx
->program
->info
->tcs
.tes_inputs_read
4338 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4340 bool indirect_write
= false;
4341 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4342 return indirect_write
|| output_read_by_tes
;
4345 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4347 uint64_t mask
= per_vertex
4348 ? ctx
->shader
->info
.outputs_read
4349 : ctx
->shader
->info
.patch_outputs_read
;
4351 bool indirect_write
= false;
4352 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4353 return indirect_write
|| output_read
;
4356 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4358 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4359 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4361 Builder
bld(ctx
->program
, ctx
->block
);
4363 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4364 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4365 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4367 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4368 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4369 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4371 if (write_to_vmem
) {
4372 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4373 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4374 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4376 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4377 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4378 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4382 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4383 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4384 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4388 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4390 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4391 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4393 Builder
bld(ctx
->program
, ctx
->block
);
4395 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4396 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4397 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4398 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4400 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4403 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4405 if (ctx
->stage
== vertex_vs
||
4406 ctx
->stage
== tess_eval_vs
||
4407 ctx
->stage
== fragment_fs
||
4408 ctx
->stage
== ngg_vertex_gs
||
4409 ctx
->stage
== ngg_tess_eval_gs
||
4410 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4411 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4412 if (!stored_to_temps
) {
4413 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4414 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4415 fprintf(stderr
, "\n");
4418 } else if (ctx
->stage
== vertex_es
||
4419 ctx
->stage
== vertex_ls
||
4420 ctx
->stage
== tess_eval_es
||
4421 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4422 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4423 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4424 visit_store_ls_or_es_output(ctx
, instr
);
4425 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4426 visit_store_tcs_output(ctx
, instr
, false);
4428 unreachable("Shader stage not implemented");
4432 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4434 visit_load_tcs_output(ctx
, instr
, false);
4437 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4439 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4440 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4442 Builder
bld(ctx
->program
, ctx
->block
);
4444 if (dst
.regClass() == v2b
) {
4445 if (ctx
->program
->has_16bank_lds
) {
4446 assert(ctx
->options
->chip_class
<= GFX8
);
4447 Builder::Result interp_p1
=
4448 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4449 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4450 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4451 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4452 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4453 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4455 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4457 if (ctx
->options
->chip_class
== GFX8
)
4458 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4460 Builder::Result interp_p1
=
4461 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4462 coord1
, bld
.m0(prim_mask
), idx
, component
);
4463 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4464 interp_p1
, idx
, component
);
4467 Builder::Result interp_p1
=
4468 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4469 bld
.m0(prim_mask
), idx
, component
);
4471 if (ctx
->program
->has_16bank_lds
)
4472 interp_p1
.instr
->operands
[0].setLateKill(true);
4474 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4475 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4479 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4481 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4482 for (unsigned i
= 0; i
< num_components
; i
++)
4483 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4484 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4485 assert(num_components
== 4);
4486 Builder
bld(ctx
->program
, ctx
->block
);
4487 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4490 for (Operand
& op
: vec
->operands
)
4491 op
= op
.isUndefined() ? Operand(0u) : op
;
4493 vec
->definitions
[0] = Definition(dst
);
4494 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4495 emit_split_vector(ctx
, dst
, num_components
);
4499 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4501 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4502 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4503 unsigned idx
= nir_intrinsic_base(instr
);
4504 unsigned component
= nir_intrinsic_component(instr
);
4505 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4507 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4509 assert(offset
->u32
== 0);
4511 /* the lower 15bit of the prim_mask contain the offset into LDS
4512 * while the upper bits contain the number of prims */
4513 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4514 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4515 Builder
bld(ctx
->program
, ctx
->block
);
4516 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4517 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4518 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4519 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4520 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4523 if (instr
->dest
.ssa
.num_components
== 1) {
4524 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4526 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4527 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4529 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4530 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4531 vec
->operands
[i
] = Operand(tmp
);
4533 vec
->definitions
[0] = Definition(dst
);
4534 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4538 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4539 unsigned offset
, unsigned stride
, unsigned channels
)
4541 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4542 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4544 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4545 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4548 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4549 unsigned offset
, unsigned stride
, unsigned *channels
)
4551 if (!vtx_info
->chan_byte_size
) {
4552 *channels
= vtx_info
->num_channels
;
4553 return vtx_info
->chan_format
;
4556 unsigned num_channels
= *channels
;
4557 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4558 unsigned new_channels
= num_channels
+ 1;
4559 /* first, assume more loads is worse and try using a larger data format */
4560 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4562 /* don't make the attribute potentially out-of-bounds */
4563 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4567 if (new_channels
== 5) {
4568 /* then try decreasing load size (at the cost of more loads) */
4569 new_channels
= *channels
;
4570 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4574 if (new_channels
< *channels
)
4575 *channels
= new_channels
;
4576 num_channels
= new_channels
;
4579 switch (vtx_info
->chan_format
) {
4580 case V_008F0C_BUF_DATA_FORMAT_8
:
4581 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4582 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4583 case V_008F0C_BUF_DATA_FORMAT_16
:
4584 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4585 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4586 case V_008F0C_BUF_DATA_FORMAT_32
:
4587 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4588 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4590 unreachable("shouldn't reach here");
4591 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4594 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4595 * so we may need to fix it up. */
4596 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4598 Builder
bld(ctx
->program
, ctx
->block
);
4600 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4601 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4603 /* For the integer-like cases, do a natural sign extension.
4605 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4606 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4609 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4610 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4612 /* Convert back to the right type. */
4613 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4614 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4615 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4616 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4617 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4618 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4624 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4626 Builder
bld(ctx
->program
, ctx
->block
);
4627 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4628 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4630 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4631 if (off_instr
->type
!= nir_instr_type_load_const
) {
4632 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4633 nir_print_instr(off_instr
, stderr
);
4634 fprintf(stderr
, "\n");
4636 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4638 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4640 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4641 unsigned component
= nir_intrinsic_component(instr
);
4642 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4643 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4644 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4645 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4646 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4648 unsigned dfmt
= attrib_format
& 0xf;
4649 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4650 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4652 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4653 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4654 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4655 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4657 num_channels
= MAX2(num_channels
, 3);
4659 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4660 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4663 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4664 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4665 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4667 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4669 Temp divided
= bld
.tmp(v1
);
4670 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4671 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4673 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4676 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4679 index
= bld
.vadd32(bld
.def(v1
),
4680 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4681 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4684 Temp channels
[num_channels
];
4685 unsigned channel_start
= 0;
4686 bool direct_fetch
= false;
4688 /* skip unused channels at the start */
4689 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4690 channel_start
= ffs(mask
) - 1;
4691 for (unsigned i
= 0; i
< channel_start
; i
++)
4692 channels
[i
] = Temp(0, s1
);
4693 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4694 num_channels
= 3 - (ffs(mask
) - 1);
4698 while (channel_start
< num_channels
) {
4699 unsigned fetch_component
= num_channels
- channel_start
;
4700 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4701 bool expanded
= false;
4703 /* use MUBUF when possible to avoid possible alignment issues */
4704 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4705 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4706 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4707 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4708 vtx_info
->chan_byte_size
== 4;
4709 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4711 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4713 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4714 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4715 fetch_component
= 4;
4720 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4722 Temp fetch_index
= index
;
4723 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4724 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4725 fetch_offset
= fetch_offset
% attrib_stride
;
4728 Operand
soffset(0u);
4729 if (fetch_offset
>= 4096) {
4730 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4731 fetch_offset
%= 4096;
4735 switch (fetch_bytes
) {
4737 assert(!use_mubuf
&& bitsize
== 16);
4738 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4741 if (bitsize
== 16) {
4743 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4745 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4749 assert(!use_mubuf
&& bitsize
== 16);
4750 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4753 if (bitsize
== 16) {
4755 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4757 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4761 assert(ctx
->options
->chip_class
>= GFX7
||
4762 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4763 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4766 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4769 unreachable("Unimplemented load_input vector size");
4773 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4774 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4775 num_channels
<= 3)) {
4776 direct_fetch
= true;
4779 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4783 Instruction
*mubuf
= bld
.mubuf(opcode
,
4784 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4785 fetch_offset
, false, true).instr
;
4786 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4788 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4789 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4790 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4791 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4794 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4796 if (fetch_component
== 1) {
4797 channels
[channel_start
] = fetch_dst
;
4799 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4800 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4801 bitsize
== 16 ? v2b
: v1
);
4804 channel_start
+= fetch_component
;
4807 if (!direct_fetch
) {
4808 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4809 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4811 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4812 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4813 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4815 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4816 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4817 unsigned num_temp
= 0;
4818 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4819 unsigned idx
= i
+ component
;
4820 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4821 Temp channel
= channels
[swizzle
[idx
]];
4822 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4823 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4824 vec
->operands
[i
] = Operand(channel
);
4828 } else if (is_float
&& idx
== 3) {
4829 vec
->operands
[i
] = Operand(0x3f800000u
);
4830 } else if (!is_float
&& idx
== 3) {
4831 vec
->operands
[i
] = Operand(1u);
4833 vec
->operands
[i
] = Operand(0u);
4836 vec
->definitions
[0] = Definition(dst
);
4837 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4838 emit_split_vector(ctx
, dst
, dst
.size());
4840 if (num_temp
== dst
.size())
4841 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4843 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4844 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4845 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4846 if (off_instr
->type
!= nir_instr_type_load_const
||
4847 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4848 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4849 nir_print_instr(off_instr
, stderr
);
4850 fprintf(stderr
, "\n");
4853 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4854 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4856 assert(offset
->u32
== 0);
4858 /* the lower 15bit of the prim_mask contain the offset into LDS
4859 * while the upper bits contain the number of prims */
4860 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4861 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4862 Builder
bld(ctx
->program
, ctx
->block
);
4863 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4864 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4865 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4866 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4867 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4870 unsigned idx
= nir_intrinsic_base(instr
);
4871 unsigned component
= nir_intrinsic_component(instr
);
4872 unsigned vertex_id
= 2; /* P0 */
4874 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4875 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4876 switch (src0
->u32
) {
4878 vertex_id
= 2; /* P0 */
4881 vertex_id
= 0; /* P10 */
4884 vertex_id
= 1; /* P20 */
4887 unreachable("invalid vertex index");
4891 if (dst
.size() == 1) {
4892 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4894 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4895 for (unsigned i
= 0; i
< dst
.size(); i
++)
4896 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4897 vec
->definitions
[0] = Definition(dst
);
4898 bld
.insert(std::move(vec
));
4901 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4902 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4903 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4904 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4905 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4907 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4909 unreachable("Shader stage not implemented");
4913 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4915 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4917 Builder
bld(ctx
->program
, ctx
->block
);
4918 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4921 if (!nir_src_is_const(*vertex_src
)) {
4922 /* better code could be created, but this case probably doesn't happen
4923 * much in practice */
4924 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4925 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4928 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4929 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4931 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4933 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4936 if (vertex_offset
.id()) {
4937 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4938 Operand(i
), indirect_vertex
);
4939 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4941 vertex_offset
= elem
;
4945 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4946 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4948 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4949 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4950 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4951 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4952 Operand((vertex
% 2u) * 16u), Operand(16u));
4954 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4957 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4958 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4959 return offset_mul(ctx
, offs
, 4u);
4962 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4964 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4966 Builder
bld(ctx
->program
, ctx
->block
);
4967 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4968 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4970 if (ctx
->stage
== geometry_gs
) {
4971 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4972 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4973 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4974 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4975 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4976 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4977 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4979 unreachable("Unsupported GS stage.");
4983 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4985 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4987 Builder
bld(ctx
->program
, ctx
->block
);
4988 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4990 if (load_input_from_temps(ctx
, instr
, dst
))
4993 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4994 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4995 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4997 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5000 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5002 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5004 Builder
bld(ctx
->program
, ctx
->block
);
5006 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5007 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5008 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5010 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5011 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5013 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5016 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5018 switch (ctx
->shader
->info
.stage
) {
5019 case MESA_SHADER_GEOMETRY
:
5020 visit_load_gs_per_vertex_input(ctx
, instr
);
5022 case MESA_SHADER_TESS_CTRL
:
5023 visit_load_tcs_per_vertex_input(ctx
, instr
);
5025 case MESA_SHADER_TESS_EVAL
:
5026 visit_load_tes_per_vertex_input(ctx
, instr
);
5029 unreachable("Unimplemented shader stage");
5033 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5035 visit_load_tcs_output(ctx
, instr
, true);
5038 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5040 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5041 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5043 visit_store_tcs_output(ctx
, instr
, true);
5046 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5048 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5050 Builder
bld(ctx
->program
, ctx
->block
);
5051 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5053 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5054 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5057 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5058 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5059 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5060 tes_w
= Operand(tmp
);
5063 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5064 emit_split_vector(ctx
, tess_coord
, 3);
5067 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5069 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5070 Builder
bld(ctx
->program
, ctx
->block
);
5071 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5072 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5073 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5076 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5080 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5082 Builder
bld(ctx
->program
, ctx
->block
);
5083 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5084 if (!nir_dest_is_divergent(instr
->dest
))
5085 index
= bld
.as_uniform(index
);
5086 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5087 unsigned binding
= nir_intrinsic_binding(instr
);
5090 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5091 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5092 unsigned offset
= layout
->binding
[binding
].offset
;
5094 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5095 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5096 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5097 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5098 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5101 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5102 stride
= layout
->binding
[binding
].size
;
5105 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5106 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5108 if (nir_const_index
) {
5109 const_index
= const_index
* stride
;
5110 } else if (index
.type() == RegType::vgpr
) {
5111 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5112 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5114 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5118 if (nir_const_index
) {
5119 const_index
= const_index
+ offset
;
5120 } else if (index
.type() == RegType::vgpr
) {
5121 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5123 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5127 if (nir_const_index
&& const_index
== 0) {
5129 } else if (index
.type() == RegType::vgpr
) {
5130 index
= bld
.vadd32(bld
.def(v1
),
5131 nir_const_index
? Operand(const_index
) : Operand(index
),
5134 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5135 nir_const_index
? Operand(const_index
) : Operand(index
),
5139 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5142 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5143 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5144 bool glc
=false, bool readonly
=true, bool allow_smem
=true)
5146 Builder
bld(ctx
->program
, ctx
->block
);
5148 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5150 offset
= bld
.as_uniform(offset
);
5152 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5154 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5155 info
.can_reorder
= readonly
;
5156 info
.align_mul
= align_mul
;
5157 info
.align_offset
= align_offset
;
5159 emit_smem_load(ctx
, bld
, &info
);
5161 emit_mubuf_load(ctx
, bld
, &info
);
5164 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5166 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5167 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5169 Builder
bld(ctx
->program
, ctx
->block
);
5171 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5172 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5173 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5174 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5176 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5177 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5178 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5179 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5180 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5181 if (ctx
->options
->chip_class
>= GFX10
) {
5182 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5183 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5184 S_008F0C_RESOURCE_LEVEL(1);
5186 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5187 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5189 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5190 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5191 Operand(0xFFFFFFFFu
),
5192 Operand(desc_type
));
5193 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5194 rsrc
, upper_dwords
);
5196 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5197 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5199 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5200 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5201 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5204 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5206 Builder
bld(ctx
->program
, ctx
->block
);
5207 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5208 unsigned offset
= nir_intrinsic_base(instr
);
5209 unsigned count
= instr
->dest
.ssa
.num_components
;
5210 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5212 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5213 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5214 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5215 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5216 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5217 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5218 for (unsigned i
= 0; i
< count
; ++i
) {
5219 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5220 vec
->operands
[i
] = Operand
{elems
[i
]};
5222 vec
->definitions
[0] = Definition(dst
);
5223 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5224 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5229 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5230 if (offset
!= 0) // TODO check if index != 0 as well
5231 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5232 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5235 bool aligned
= true;
5237 if (instr
->dest
.ssa
.bit_size
== 8) {
5238 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5239 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5241 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5242 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5243 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5245 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5250 switch (vec
.size()) {
5252 op
= aco_opcode::s_load_dword
;
5255 op
= aco_opcode::s_load_dwordx2
;
5261 op
= aco_opcode::s_load_dwordx4
;
5267 op
= aco_opcode::s_load_dwordx8
;
5270 unreachable("unimplemented or forbidden load_push_constant.");
5273 bld
.smem(op
, Definition(vec
), ptr
, index
);
5276 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5277 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5282 emit_split_vector(ctx
, vec
, 4);
5283 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5284 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5285 emit_extract_vector(ctx
, vec
, 0, rc
),
5286 emit_extract_vector(ctx
, vec
, 1, rc
),
5287 emit_extract_vector(ctx
, vec
, 2, rc
));
5290 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5293 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5295 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5297 Builder
bld(ctx
->program
, ctx
->block
);
5299 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5300 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5301 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5302 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5303 if (ctx
->options
->chip_class
>= GFX10
) {
5304 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5305 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5306 S_008F0C_RESOURCE_LEVEL(1);
5308 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5309 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5312 unsigned base
= nir_intrinsic_base(instr
);
5313 unsigned range
= nir_intrinsic_range(instr
);
5315 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5316 if (base
&& offset
.type() == RegType::sgpr
)
5317 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5318 else if (base
&& offset
.type() == RegType::vgpr
)
5319 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5321 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5322 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5323 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5324 Operand(desc_type
));
5325 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5326 // TODO: get alignment information for subdword constants
5327 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5330 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5332 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5333 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5335 ctx
->program
->needs_exact
= true;
5337 // TODO: optimize uniform conditions
5338 Builder
bld(ctx
->program
, ctx
->block
);
5339 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5340 assert(src
.regClass() == bld
.lm
);
5341 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5342 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5343 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5347 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5349 Builder
bld(ctx
->program
, ctx
->block
);
5351 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5352 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5354 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5355 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5357 if (ctx
->block
->loop_nest_depth
&&
5358 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5359 /* we handle discards the same way as jump instructions */
5360 append_logical_end(ctx
->block
);
5362 /* in loops, discard behaves like break */
5363 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5364 ctx
->block
->kind
|= block_kind_discard
;
5367 /* uniform discard - loop ends here */
5368 assert(nir_instr_is_last(&instr
->instr
));
5369 ctx
->block
->kind
|= block_kind_uniform
;
5370 ctx
->cf_info
.has_branch
= true;
5371 bld
.branch(aco_opcode::p_branch
);
5372 add_linear_edge(ctx
->block
->index
, linear_target
);
5376 /* we add a break right behind the discard() instructions */
5377 ctx
->block
->kind
|= block_kind_break
;
5378 unsigned idx
= ctx
->block
->index
;
5380 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5381 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5383 /* remove critical edges from linear CFG */
5384 bld
.branch(aco_opcode::p_branch
);
5385 Block
* break_block
= ctx
->program
->create_and_insert_block();
5386 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5387 break_block
->kind
|= block_kind_uniform
;
5388 add_linear_edge(idx
, break_block
);
5389 add_linear_edge(break_block
->index
, linear_target
);
5390 bld
.reset(break_block
);
5391 bld
.branch(aco_opcode::p_branch
);
5393 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5394 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5395 add_linear_edge(idx
, continue_block
);
5396 append_logical_start(continue_block
);
5397 ctx
->block
= continue_block
;
5402 /* it can currently happen that NIR doesn't remove the unreachable code */
5403 if (!nir_instr_is_last(&instr
->instr
)) {
5404 ctx
->program
->needs_exact
= true;
5405 /* save exec somewhere temporarily so that it doesn't get
5406 * overwritten before the discard from outer exec masks */
5407 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5408 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5409 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5413 /* This condition is incorrect for uniformly branched discards in a loop
5414 * predicated by a divergent condition, but the above code catches that case
5415 * and the discard would end up turning into a discard_if.
5425 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5426 /* program just ends here */
5427 ctx
->block
->kind
|= block_kind_uniform
;
5428 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5429 0 /* enabled mask */, 9 /* dest */,
5430 false /* compressed */, true/* done */, true /* valid mask */);
5431 bld
.sopp(aco_opcode::s_endpgm
);
5432 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5434 ctx
->block
->kind
|= block_kind_discard
;
5435 /* branch and linear edge is added by visit_if() */
5439 enum aco_descriptor_type
{
5450 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5451 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5453 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5454 return dim
== ac_image_cube
||
5455 dim
== ac_image_1darray
||
5456 dim
== ac_image_2darray
||
5457 dim
== ac_image_2darraymsaa
;
5460 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5461 enum aco_descriptor_type desc_type
,
5462 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5464 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5465 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5466 if (it != ctx->tex_desc.end())
5469 Temp index
= Temp();
5470 bool index_set
= false;
5471 unsigned constant_index
= 0;
5472 unsigned descriptor_set
;
5473 unsigned base_index
;
5474 Builder
bld(ctx
->program
, ctx
->block
);
5477 assert(tex_instr
&& !image
);
5479 base_index
= tex_instr
->sampler_index
;
5481 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5482 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5486 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5487 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5489 constant_index
+= array_size
* const_value
->u32
;
5491 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5492 if (indirect
.type() == RegType::vgpr
)
5493 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5495 if (array_size
!= 1)
5496 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5502 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5506 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5508 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5509 base_index
= deref_instr
->var
->data
.binding
;
5512 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5513 list
= convert_pointer_to_64_bit(ctx
, list
);
5515 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5516 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5517 unsigned offset
= binding
->offset
;
5518 unsigned stride
= binding
->size
;
5522 assert(base_index
< layout
->binding_count
);
5524 switch (desc_type
) {
5525 case ACO_DESC_IMAGE
:
5527 opcode
= aco_opcode::s_load_dwordx8
;
5529 case ACO_DESC_FMASK
:
5531 opcode
= aco_opcode::s_load_dwordx8
;
5534 case ACO_DESC_SAMPLER
:
5536 opcode
= aco_opcode::s_load_dwordx4
;
5537 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5538 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5540 case ACO_DESC_BUFFER
:
5542 opcode
= aco_opcode::s_load_dwordx4
;
5544 case ACO_DESC_PLANE_0
:
5545 case ACO_DESC_PLANE_1
:
5547 opcode
= aco_opcode::s_load_dwordx8
;
5548 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5550 case ACO_DESC_PLANE_2
:
5552 opcode
= aco_opcode::s_load_dwordx4
;
5556 unreachable("invalid desc_type\n");
5559 offset
+= constant_index
* stride
;
5561 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5562 (!index_set
|| binding
->immutable_samplers_equal
)) {
5563 if (binding
->immutable_samplers_equal
)
5566 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5567 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5568 Operand(samplers
[constant_index
* 4 + 0]),
5569 Operand(samplers
[constant_index
* 4 + 1]),
5570 Operand(samplers
[constant_index
* 4 + 2]),
5571 Operand(samplers
[constant_index
* 4 + 3]));
5576 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5578 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5579 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5582 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5584 if (desc_type
== ACO_DESC_PLANE_2
) {
5586 for (unsigned i
= 0; i
< 8; i
++)
5587 components
[i
] = bld
.tmp(s1
);
5588 bld
.pseudo(aco_opcode::p_split_vector
,
5589 Definition(components
[0]),
5590 Definition(components
[1]),
5591 Definition(components
[2]),
5592 Definition(components
[3]),
5595 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5596 bld
.pseudo(aco_opcode::p_split_vector
,
5597 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5598 Definition(components
[4]),
5599 Definition(components
[5]),
5600 Definition(components
[6]),
5601 Definition(components
[7]),
5604 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5605 components
[0], components
[1], components
[2], components
[3],
5606 components
[4], components
[5], components
[6], components
[7]);
5612 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5615 case GLSL_SAMPLER_DIM_BUF
:
5617 case GLSL_SAMPLER_DIM_1D
:
5618 return array
? 2 : 1;
5619 case GLSL_SAMPLER_DIM_2D
:
5620 return array
? 3 : 2;
5621 case GLSL_SAMPLER_DIM_MS
:
5622 return array
? 4 : 3;
5623 case GLSL_SAMPLER_DIM_3D
:
5624 case GLSL_SAMPLER_DIM_CUBE
:
5626 case GLSL_SAMPLER_DIM_RECT
:
5627 case GLSL_SAMPLER_DIM_SUBPASS
:
5629 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5638 /* Adjust the sample index according to FMASK.
5640 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5641 * which is the identity mapping. Each nibble says which physical sample
5642 * should be fetched to get that sample.
5644 * For example, 0x11111100 means there are only 2 samples stored and
5645 * the second sample covers 3/4 of the pixel. When reading samples 0
5646 * and 1, return physical sample 0 (determined by the first two 0s
5647 * in FMASK), otherwise return physical sample 1.
5649 * The sample index should be adjusted as follows:
5650 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5652 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5654 Builder
bld(ctx
->program
, ctx
->block
);
5655 Temp fmask
= bld
.tmp(v1
);
5656 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5657 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5660 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5661 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5662 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5663 load
->operands
[0] = Operand(fmask_desc_ptr
);
5664 load
->operands
[1] = Operand(s4
); /* no sampler */
5665 load
->operands
[2] = Operand(coord
);
5666 load
->definitions
[0] = Definition(fmask
);
5673 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5674 ctx
->block
->instructions
.emplace_back(std::move(load
));
5676 Operand sample_index4
;
5677 if (sample_index
.isConstant()) {
5678 if (sample_index
.constantValue() < 16) {
5679 sample_index4
= Operand(sample_index
.constantValue() << 2);
5681 sample_index4
= Operand(0u);
5683 } else if (sample_index
.regClass() == s1
) {
5684 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5686 assert(sample_index
.regClass() == v1
);
5687 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5691 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5692 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5693 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5694 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5696 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5698 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5699 * resource descriptor is 0 (invalid),
5701 Temp compare
= bld
.tmp(bld
.lm
);
5702 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5703 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5705 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5707 /* Replace the MSAA sample index. */
5708 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5711 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5714 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5715 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5716 bool is_array
= glsl_sampler_type_is_array(type
);
5717 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5718 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5719 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5720 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5721 int count
= image_type_to_components_count(dim
, is_array
);
5722 std::vector
<Temp
> coords(count
);
5723 Builder
bld(ctx
->program
, ctx
->block
);
5727 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5728 /* get sample index */
5729 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5730 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5731 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5732 std::vector
<Temp
> fmask_load_address
;
5733 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5734 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5736 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5737 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5739 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5744 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5745 coords
.resize(coords
.size() + 1);
5746 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5748 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5750 for (int i
= 0; i
< count
; i
++)
5751 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5754 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5755 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5756 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5757 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5760 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5763 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5764 for (unsigned i
= 0; i
< coords
.size(); i
++)
5765 vec
->operands
[i
] = Operand(coords
[i
]);
5766 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5767 vec
->definitions
[0] = Definition(res
);
5768 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5773 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5775 Builder
bld(ctx
->program
, ctx
->block
);
5776 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5777 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5778 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5779 bool is_array
= glsl_sampler_type_is_array(type
);
5780 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5782 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5783 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5784 unsigned num_channels
= util_last_bit(mask
);
5785 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5786 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5789 switch (num_channels
) {
5791 opcode
= aco_opcode::buffer_load_format_x
;
5794 opcode
= aco_opcode::buffer_load_format_xy
;
5797 opcode
= aco_opcode::buffer_load_format_xyz
;
5800 opcode
= aco_opcode::buffer_load_format_xyzw
;
5803 unreachable(">4 channel buffer image load");
5805 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5806 load
->operands
[0] = Operand(rsrc
);
5807 load
->operands
[1] = Operand(vindex
);
5808 load
->operands
[2] = Operand((uint32_t) 0);
5810 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5813 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5814 load
->definitions
[0] = Definition(tmp
);
5816 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5817 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5818 load
->barrier
= barrier_image
;
5819 ctx
->block
->instructions
.emplace_back(std::move(load
));
5821 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5825 Temp coords
= get_image_coords(ctx
, instr
, type
);
5826 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5828 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5829 unsigned num_components
= util_bitcount(dmask
);
5831 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5834 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5836 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5837 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5839 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5840 load
->operands
[0] = Operand(resource
);
5841 load
->operands
[1] = Operand(s4
); /* no sampler */
5842 load
->operands
[2] = Operand(coords
);
5843 load
->definitions
[0] = Definition(tmp
);
5844 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5845 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5846 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5847 load
->dmask
= dmask
;
5849 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5850 load
->barrier
= barrier_image
;
5851 ctx
->block
->instructions
.emplace_back(std::move(load
));
5853 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5857 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5859 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5860 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5861 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5862 bool is_array
= glsl_sampler_type_is_array(type
);
5863 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5865 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5867 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5868 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5869 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5871 switch (data
.size()) {
5873 opcode
= aco_opcode::buffer_store_format_x
;
5876 opcode
= aco_opcode::buffer_store_format_xy
;
5879 opcode
= aco_opcode::buffer_store_format_xyz
;
5882 opcode
= aco_opcode::buffer_store_format_xyzw
;
5885 unreachable(">4 channel buffer image store");
5887 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5888 store
->operands
[0] = Operand(rsrc
);
5889 store
->operands
[1] = Operand(vindex
);
5890 store
->operands
[2] = Operand((uint32_t) 0);
5891 store
->operands
[3] = Operand(data
);
5892 store
->idxen
= true;
5895 store
->disable_wqm
= true;
5896 store
->barrier
= barrier_image
;
5897 ctx
->program
->needs_exact
= true;
5898 ctx
->block
->instructions
.emplace_back(std::move(store
));
5902 assert(data
.type() == RegType::vgpr
);
5903 Temp coords
= get_image_coords(ctx
, instr
, type
);
5904 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5906 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5907 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5909 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5910 store
->operands
[0] = Operand(resource
);
5911 store
->operands
[1] = Operand(data
);
5912 store
->operands
[2] = Operand(coords
);
5915 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5916 store
->dmask
= (1 << data
.size()) - 1;
5918 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5919 store
->disable_wqm
= true;
5920 store
->barrier
= barrier_image
;
5921 ctx
->program
->needs_exact
= true;
5922 ctx
->block
->instructions
.emplace_back(std::move(store
));
5926 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5928 /* return the previous value if dest is ever used */
5929 bool return_previous
= false;
5930 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5931 return_previous
= true;
5934 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5935 return_previous
= true;
5939 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5940 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5941 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5942 bool is_array
= glsl_sampler_type_is_array(type
);
5943 Builder
bld(ctx
->program
, ctx
->block
);
5945 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5946 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5948 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5949 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5951 aco_opcode buf_op
, image_op
;
5952 switch (instr
->intrinsic
) {
5953 case nir_intrinsic_image_deref_atomic_add
:
5954 buf_op
= aco_opcode::buffer_atomic_add
;
5955 image_op
= aco_opcode::image_atomic_add
;
5957 case nir_intrinsic_image_deref_atomic_umin
:
5958 buf_op
= aco_opcode::buffer_atomic_umin
;
5959 image_op
= aco_opcode::image_atomic_umin
;
5961 case nir_intrinsic_image_deref_atomic_imin
:
5962 buf_op
= aco_opcode::buffer_atomic_smin
;
5963 image_op
= aco_opcode::image_atomic_smin
;
5965 case nir_intrinsic_image_deref_atomic_umax
:
5966 buf_op
= aco_opcode::buffer_atomic_umax
;
5967 image_op
= aco_opcode::image_atomic_umax
;
5969 case nir_intrinsic_image_deref_atomic_imax
:
5970 buf_op
= aco_opcode::buffer_atomic_smax
;
5971 image_op
= aco_opcode::image_atomic_smax
;
5973 case nir_intrinsic_image_deref_atomic_and
:
5974 buf_op
= aco_opcode::buffer_atomic_and
;
5975 image_op
= aco_opcode::image_atomic_and
;
5977 case nir_intrinsic_image_deref_atomic_or
:
5978 buf_op
= aco_opcode::buffer_atomic_or
;
5979 image_op
= aco_opcode::image_atomic_or
;
5981 case nir_intrinsic_image_deref_atomic_xor
:
5982 buf_op
= aco_opcode::buffer_atomic_xor
;
5983 image_op
= aco_opcode::image_atomic_xor
;
5985 case nir_intrinsic_image_deref_atomic_exchange
:
5986 buf_op
= aco_opcode::buffer_atomic_swap
;
5987 image_op
= aco_opcode::image_atomic_swap
;
5989 case nir_intrinsic_image_deref_atomic_comp_swap
:
5990 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5991 image_op
= aco_opcode::image_atomic_cmpswap
;
5994 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5997 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5999 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6000 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6001 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6002 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6003 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6004 mubuf
->operands
[0] = Operand(resource
);
6005 mubuf
->operands
[1] = Operand(vindex
);
6006 mubuf
->operands
[2] = Operand((uint32_t)0);
6007 mubuf
->operands
[3] = Operand(data
);
6008 if (return_previous
)
6009 mubuf
->definitions
[0] = Definition(dst
);
6011 mubuf
->idxen
= true;
6012 mubuf
->glc
= return_previous
;
6013 mubuf
->dlc
= false; /* Not needed for atomics */
6014 mubuf
->disable_wqm
= true;
6015 mubuf
->barrier
= barrier_image
;
6016 ctx
->program
->needs_exact
= true;
6017 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6021 Temp coords
= get_image_coords(ctx
, instr
, type
);
6022 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6023 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6024 mimg
->operands
[0] = Operand(resource
);
6025 mimg
->operands
[1] = Operand(data
);
6026 mimg
->operands
[2] = Operand(coords
);
6027 if (return_previous
)
6028 mimg
->definitions
[0] = Definition(dst
);
6029 mimg
->glc
= return_previous
;
6030 mimg
->dlc
= false; /* Not needed for atomics */
6031 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6032 mimg
->dmask
= (1 << data
.size()) - 1;
6034 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6035 mimg
->disable_wqm
= true;
6036 mimg
->barrier
= barrier_image
;
6037 ctx
->program
->needs_exact
= true;
6038 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6042 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6044 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6045 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6046 Builder
bld(ctx
->program
, ctx
->block
);
6048 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6050 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6051 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6053 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6054 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6056 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6057 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6059 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6060 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6061 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6062 if (dst
.type() == RegType::vgpr
)
6063 bld
.copy(Definition(dst
), shr_dst
);
6065 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6067 emit_extract_vector(ctx
, desc
, 2, dst
);
6071 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6073 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6074 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6075 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6076 bool is_array
= glsl_sampler_type_is_array(type
);
6077 Builder
bld(ctx
->program
, ctx
->block
);
6079 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6080 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6081 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6085 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6088 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6090 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6092 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6093 mimg
->operands
[0] = Operand(resource
);
6094 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6095 mimg
->operands
[2] = Operand(lod
);
6096 uint8_t& dmask
= mimg
->dmask
;
6097 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6098 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6099 mimg
->da
= glsl_sampler_type_is_array(type
);
6100 mimg
->can_reorder
= true;
6101 Definition
& def
= mimg
->definitions
[0];
6102 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6104 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6105 glsl_sampler_type_is_array(type
)) {
6107 assert(instr
->dest
.ssa
.num_components
== 3);
6108 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6109 def
= Definition(tmp
);
6110 emit_split_vector(ctx
, tmp
, 3);
6112 /* divide 3rd value by 6 by multiplying with magic number */
6113 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6114 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6116 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6117 emit_extract_vector(ctx
, tmp
, 0, v1
),
6118 emit_extract_vector(ctx
, tmp
, 1, v1
),
6121 } else if (ctx
->options
->chip_class
== GFX9
&&
6122 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6123 glsl_sampler_type_is_array(type
)) {
6124 assert(instr
->dest
.ssa
.num_components
== 2);
6125 def
= Definition(dst
);
6128 def
= Definition(dst
);
6131 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6134 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6136 Builder
bld(ctx
->program
, ctx
->block
);
6137 unsigned num_components
= instr
->num_components
;
6139 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6140 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6141 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6143 unsigned access
= nir_intrinsic_access(instr
);
6144 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6145 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6147 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6148 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6149 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6151 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6152 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6154 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6155 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false, allow_smem
);
6158 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6160 Builder
bld(ctx
->program
, ctx
->block
);
6161 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6162 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6163 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6164 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6166 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6167 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6169 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6170 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6171 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6172 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6174 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6176 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6177 ctx
->options
->chip_class
>= GFX8
&&
6178 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6181 offset
= bld
.as_uniform(offset
);
6182 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6184 unsigned write_count
= 0;
6185 Temp write_datas
[32];
6186 unsigned offsets
[32];
6187 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6188 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6190 for (unsigned i
= 0; i
< write_count
; i
++) {
6191 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6192 if (smem
&& ctx
->stage
== fragment_fs
)
6193 op
= aco_opcode::p_fs_buffer_store_smem
;
6196 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6197 store
->operands
[0] = Operand(rsrc
);
6199 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6200 offset
, Operand(offsets
[i
]));
6201 store
->operands
[1] = Operand(off
);
6203 store
->operands
[1] = Operand(offset
);
6205 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6206 store
->operands
[1].setFixed(m0
);
6207 store
->operands
[2] = Operand(write_datas
[i
]);
6210 store
->disable_wqm
= true;
6211 store
->barrier
= barrier_buffer
;
6212 ctx
->block
->instructions
.emplace_back(std::move(store
));
6213 ctx
->program
->wb_smem_l1_on_end
= true;
6214 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6215 ctx
->block
->kind
|= block_kind_needs_lowering
;
6216 ctx
->program
->needs_exact
= true;
6219 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6220 store
->operands
[0] = Operand(rsrc
);
6221 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6222 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6223 store
->operands
[3] = Operand(write_datas
[i
]);
6224 store
->offset
= offsets
[i
];
6225 store
->offen
= (offset
.type() == RegType::vgpr
);
6228 store
->disable_wqm
= true;
6229 store
->barrier
= barrier_buffer
;
6230 ctx
->program
->needs_exact
= true;
6231 ctx
->block
->instructions
.emplace_back(std::move(store
));
6236 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6238 /* return the previous value if dest is ever used */
6239 bool return_previous
= false;
6240 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6241 return_previous
= true;
6244 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6245 return_previous
= true;
6249 Builder
bld(ctx
->program
, ctx
->block
);
6250 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6252 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6253 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6254 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6256 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6257 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6258 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6260 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6262 aco_opcode op32
, op64
;
6263 switch (instr
->intrinsic
) {
6264 case nir_intrinsic_ssbo_atomic_add
:
6265 op32
= aco_opcode::buffer_atomic_add
;
6266 op64
= aco_opcode::buffer_atomic_add_x2
;
6268 case nir_intrinsic_ssbo_atomic_imin
:
6269 op32
= aco_opcode::buffer_atomic_smin
;
6270 op64
= aco_opcode::buffer_atomic_smin_x2
;
6272 case nir_intrinsic_ssbo_atomic_umin
:
6273 op32
= aco_opcode::buffer_atomic_umin
;
6274 op64
= aco_opcode::buffer_atomic_umin_x2
;
6276 case nir_intrinsic_ssbo_atomic_imax
:
6277 op32
= aco_opcode::buffer_atomic_smax
;
6278 op64
= aco_opcode::buffer_atomic_smax_x2
;
6280 case nir_intrinsic_ssbo_atomic_umax
:
6281 op32
= aco_opcode::buffer_atomic_umax
;
6282 op64
= aco_opcode::buffer_atomic_umax_x2
;
6284 case nir_intrinsic_ssbo_atomic_and
:
6285 op32
= aco_opcode::buffer_atomic_and
;
6286 op64
= aco_opcode::buffer_atomic_and_x2
;
6288 case nir_intrinsic_ssbo_atomic_or
:
6289 op32
= aco_opcode::buffer_atomic_or
;
6290 op64
= aco_opcode::buffer_atomic_or_x2
;
6292 case nir_intrinsic_ssbo_atomic_xor
:
6293 op32
= aco_opcode::buffer_atomic_xor
;
6294 op64
= aco_opcode::buffer_atomic_xor_x2
;
6296 case nir_intrinsic_ssbo_atomic_exchange
:
6297 op32
= aco_opcode::buffer_atomic_swap
;
6298 op64
= aco_opcode::buffer_atomic_swap_x2
;
6300 case nir_intrinsic_ssbo_atomic_comp_swap
:
6301 op32
= aco_opcode::buffer_atomic_cmpswap
;
6302 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6305 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6307 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6308 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6309 mubuf
->operands
[0] = Operand(rsrc
);
6310 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6311 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6312 mubuf
->operands
[3] = Operand(data
);
6313 if (return_previous
)
6314 mubuf
->definitions
[0] = Definition(dst
);
6316 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6317 mubuf
->glc
= return_previous
;
6318 mubuf
->dlc
= false; /* Not needed for atomics */
6319 mubuf
->disable_wqm
= true;
6320 mubuf
->barrier
= barrier_buffer
;
6321 ctx
->program
->needs_exact
= true;
6322 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6325 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6327 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6328 Builder
bld(ctx
->program
, ctx
->block
);
6329 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6330 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6333 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6335 Builder
bld(ctx
->program
, ctx
->block
);
6336 unsigned num_components
= instr
->num_components
;
6337 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6339 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6340 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6341 num_components
, component_size
};
6342 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6343 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6344 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6345 info
.barrier
= barrier_buffer
;
6346 info
.can_reorder
= false;
6347 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6348 * it's safe to use SMEM */
6349 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6350 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6351 emit_global_load(ctx
, bld
, &info
);
6353 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6354 emit_smem_load(ctx
, bld
, &info
);
6358 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6360 Builder
bld(ctx
->program
, ctx
->block
);
6361 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6362 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6364 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6365 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6366 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6368 if (ctx
->options
->chip_class
>= GFX7
)
6369 addr
= as_vgpr(ctx
, addr
);
6371 unsigned write_count
= 0;
6372 Temp write_datas
[32];
6373 unsigned offsets
[32];
6374 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6375 16, &write_count
, write_datas
, offsets
);
6377 for (unsigned i
= 0; i
< write_count
; i
++) {
6378 if (ctx
->options
->chip_class
>= GFX7
) {
6379 unsigned offset
= offsets
[i
];
6380 Temp store_addr
= addr
;
6381 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6382 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6383 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6384 Temp carry
= bld
.tmp(bld
.lm
);
6385 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6387 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6388 Operand(offset
), addr0
);
6389 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6391 carry
).def(1).setHint(vcc
);
6393 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6398 bool global
= ctx
->options
->chip_class
>= GFX9
;
6400 switch (write_datas
[i
].bytes()) {
6402 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6405 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6408 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6411 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6414 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6417 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6420 unreachable("store_global not implemented for this size.");
6423 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6424 flat
->operands
[0] = Operand(store_addr
);
6425 flat
->operands
[1] = Operand(s1
);
6426 flat
->operands
[2] = Operand(write_datas
[i
]);
6429 flat
->offset
= offset
;
6430 flat
->disable_wqm
= true;
6431 flat
->barrier
= barrier_buffer
;
6432 ctx
->program
->needs_exact
= true;
6433 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6435 assert(ctx
->options
->chip_class
== GFX6
);
6437 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6439 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6441 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6442 mubuf
->operands
[0] = Operand(rsrc
);
6443 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6444 mubuf
->operands
[2] = Operand(0u);
6445 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6448 mubuf
->offset
= offsets
[i
];
6449 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6450 mubuf
->disable_wqm
= true;
6451 mubuf
->barrier
= barrier_buffer
;
6452 ctx
->program
->needs_exact
= true;
6453 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6458 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6460 /* return the previous value if dest is ever used */
6461 bool return_previous
= false;
6462 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6463 return_previous
= true;
6466 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6467 return_previous
= true;
6471 Builder
bld(ctx
->program
, ctx
->block
);
6472 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6473 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6475 if (ctx
->options
->chip_class
>= GFX7
)
6476 addr
= as_vgpr(ctx
, addr
);
6478 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6479 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6480 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6482 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6484 aco_opcode op32
, op64
;
6486 if (ctx
->options
->chip_class
>= GFX7
) {
6487 bool global
= ctx
->options
->chip_class
>= GFX9
;
6488 switch (instr
->intrinsic
) {
6489 case nir_intrinsic_global_atomic_add
:
6490 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6491 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6493 case nir_intrinsic_global_atomic_imin
:
6494 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6495 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6497 case nir_intrinsic_global_atomic_umin
:
6498 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6499 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6501 case nir_intrinsic_global_atomic_imax
:
6502 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6503 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6505 case nir_intrinsic_global_atomic_umax
:
6506 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6507 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6509 case nir_intrinsic_global_atomic_and
:
6510 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6511 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6513 case nir_intrinsic_global_atomic_or
:
6514 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6515 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6517 case nir_intrinsic_global_atomic_xor
:
6518 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6519 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6521 case nir_intrinsic_global_atomic_exchange
:
6522 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6523 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6525 case nir_intrinsic_global_atomic_comp_swap
:
6526 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6527 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6530 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6533 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6534 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6535 flat
->operands
[0] = Operand(addr
);
6536 flat
->operands
[1] = Operand(s1
);
6537 flat
->operands
[2] = Operand(data
);
6538 if (return_previous
)
6539 flat
->definitions
[0] = Definition(dst
);
6540 flat
->glc
= return_previous
;
6541 flat
->dlc
= false; /* Not needed for atomics */
6543 flat
->disable_wqm
= true;
6544 flat
->barrier
= barrier_buffer
;
6545 ctx
->program
->needs_exact
= true;
6546 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6548 assert(ctx
->options
->chip_class
== GFX6
);
6550 switch (instr
->intrinsic
) {
6551 case nir_intrinsic_global_atomic_add
:
6552 op32
= aco_opcode::buffer_atomic_add
;
6553 op64
= aco_opcode::buffer_atomic_add_x2
;
6555 case nir_intrinsic_global_atomic_imin
:
6556 op32
= aco_opcode::buffer_atomic_smin
;
6557 op64
= aco_opcode::buffer_atomic_smin_x2
;
6559 case nir_intrinsic_global_atomic_umin
:
6560 op32
= aco_opcode::buffer_atomic_umin
;
6561 op64
= aco_opcode::buffer_atomic_umin_x2
;
6563 case nir_intrinsic_global_atomic_imax
:
6564 op32
= aco_opcode::buffer_atomic_smax
;
6565 op64
= aco_opcode::buffer_atomic_smax_x2
;
6567 case nir_intrinsic_global_atomic_umax
:
6568 op32
= aco_opcode::buffer_atomic_umax
;
6569 op64
= aco_opcode::buffer_atomic_umax_x2
;
6571 case nir_intrinsic_global_atomic_and
:
6572 op32
= aco_opcode::buffer_atomic_and
;
6573 op64
= aco_opcode::buffer_atomic_and_x2
;
6575 case nir_intrinsic_global_atomic_or
:
6576 op32
= aco_opcode::buffer_atomic_or
;
6577 op64
= aco_opcode::buffer_atomic_or_x2
;
6579 case nir_intrinsic_global_atomic_xor
:
6580 op32
= aco_opcode::buffer_atomic_xor
;
6581 op64
= aco_opcode::buffer_atomic_xor_x2
;
6583 case nir_intrinsic_global_atomic_exchange
:
6584 op32
= aco_opcode::buffer_atomic_swap
;
6585 op64
= aco_opcode::buffer_atomic_swap_x2
;
6587 case nir_intrinsic_global_atomic_comp_swap
:
6588 op32
= aco_opcode::buffer_atomic_cmpswap
;
6589 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6592 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6595 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6597 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6599 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6600 mubuf
->operands
[0] = Operand(rsrc
);
6601 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6602 mubuf
->operands
[2] = Operand(0u);
6603 mubuf
->operands
[3] = Operand(data
);
6604 if (return_previous
)
6605 mubuf
->definitions
[0] = Definition(dst
);
6606 mubuf
->glc
= return_previous
;
6609 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6610 mubuf
->disable_wqm
= true;
6611 mubuf
->barrier
= barrier_buffer
;
6612 ctx
->program
->needs_exact
= true;
6613 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6617 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6618 Builder
bld(ctx
->program
, ctx
->block
);
6619 switch(instr
->intrinsic
) {
6620 case nir_intrinsic_group_memory_barrier
:
6621 case nir_intrinsic_memory_barrier
:
6622 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6624 case nir_intrinsic_memory_barrier_buffer
:
6625 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6627 case nir_intrinsic_memory_barrier_image
:
6628 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6630 case nir_intrinsic_memory_barrier_tcs_patch
:
6631 case nir_intrinsic_memory_barrier_shared
:
6632 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6635 unreachable("Unimplemented memory barrier intrinsic");
6640 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6642 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6643 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6644 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6645 Builder
bld(ctx
->program
, ctx
->block
);
6647 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6648 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6649 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6652 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6654 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6655 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6656 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6657 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6659 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6660 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6663 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6665 unsigned offset
= nir_intrinsic_base(instr
);
6666 Builder
bld(ctx
->program
, ctx
->block
);
6667 Operand m
= load_lds_size_m0(bld
);
6668 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6669 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6671 unsigned num_operands
= 3;
6672 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6673 switch(instr
->intrinsic
) {
6674 case nir_intrinsic_shared_atomic_add
:
6675 op32
= aco_opcode::ds_add_u32
;
6676 op64
= aco_opcode::ds_add_u64
;
6677 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6678 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6680 case nir_intrinsic_shared_atomic_imin
:
6681 op32
= aco_opcode::ds_min_i32
;
6682 op64
= aco_opcode::ds_min_i64
;
6683 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6684 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6686 case nir_intrinsic_shared_atomic_umin
:
6687 op32
= aco_opcode::ds_min_u32
;
6688 op64
= aco_opcode::ds_min_u64
;
6689 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6690 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6692 case nir_intrinsic_shared_atomic_imax
:
6693 op32
= aco_opcode::ds_max_i32
;
6694 op64
= aco_opcode::ds_max_i64
;
6695 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6696 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6698 case nir_intrinsic_shared_atomic_umax
:
6699 op32
= aco_opcode::ds_max_u32
;
6700 op64
= aco_opcode::ds_max_u64
;
6701 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6702 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6704 case nir_intrinsic_shared_atomic_and
:
6705 op32
= aco_opcode::ds_and_b32
;
6706 op64
= aco_opcode::ds_and_b64
;
6707 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6708 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6710 case nir_intrinsic_shared_atomic_or
:
6711 op32
= aco_opcode::ds_or_b32
;
6712 op64
= aco_opcode::ds_or_b64
;
6713 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6714 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6716 case nir_intrinsic_shared_atomic_xor
:
6717 op32
= aco_opcode::ds_xor_b32
;
6718 op64
= aco_opcode::ds_xor_b64
;
6719 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6720 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6722 case nir_intrinsic_shared_atomic_exchange
:
6723 op32
= aco_opcode::ds_write_b32
;
6724 op64
= aco_opcode::ds_write_b64
;
6725 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6726 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6728 case nir_intrinsic_shared_atomic_comp_swap
:
6729 op32
= aco_opcode::ds_cmpst_b32
;
6730 op64
= aco_opcode::ds_cmpst_b64
;
6731 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6732 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6736 unreachable("Unhandled shared atomic intrinsic");
6739 /* return the previous value if dest is ever used */
6740 bool return_previous
= false;
6741 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6742 return_previous
= true;
6745 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6746 return_previous
= true;
6751 if (data
.size() == 1) {
6752 assert(instr
->dest
.ssa
.bit_size
== 32);
6753 op
= return_previous
? op32_rtn
: op32
;
6755 assert(instr
->dest
.ssa
.bit_size
== 64);
6756 op
= return_previous
? op64_rtn
: op64
;
6759 if (offset
> 65535) {
6760 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6764 aco_ptr
<DS_instruction
> ds
;
6765 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6766 ds
->operands
[0] = Operand(address
);
6767 ds
->operands
[1] = Operand(data
);
6768 if (num_operands
== 4)
6769 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6770 ds
->operands
[num_operands
- 1] = m
;
6771 ds
->offset0
= offset
;
6772 if (return_previous
)
6773 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6774 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6777 Temp
get_scratch_resource(isel_context
*ctx
)
6779 Builder
bld(ctx
->program
, ctx
->block
);
6780 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6781 if (ctx
->stage
!= compute_cs
)
6782 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6784 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6785 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6787 if (ctx
->program
->chip_class
>= GFX10
) {
6788 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6789 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6790 S_008F0C_RESOURCE_LEVEL(1);
6791 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6792 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6793 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6796 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6797 if (ctx
->program
->chip_class
<= GFX8
)
6798 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6800 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6803 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6804 Builder
bld(ctx
->program
, ctx
->block
);
6805 Temp rsrc
= get_scratch_resource(ctx
);
6806 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6807 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6809 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6810 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6811 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6812 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6813 info
.swizzle_component_size
= 16;
6814 info
.can_reorder
= false;
6815 info
.soffset
= ctx
->program
->scratch_offset
;
6816 emit_mubuf_load(ctx
, bld
, &info
);
6819 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6820 Builder
bld(ctx
->program
, ctx
->block
);
6821 Temp rsrc
= get_scratch_resource(ctx
);
6822 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6823 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6825 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6826 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6828 unsigned write_count
= 0;
6829 Temp write_datas
[32];
6830 unsigned offsets
[32];
6831 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6832 16, &write_count
, write_datas
, offsets
);
6834 for (unsigned i
= 0; i
< write_count
; i
++) {
6835 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6836 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6840 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6841 uint8_t log2_ps_iter_samples
;
6842 if (ctx
->program
->info
->ps
.force_persample
) {
6843 log2_ps_iter_samples
=
6844 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6846 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6849 /* The bit pattern matches that used by fixed function fragment
6851 static const unsigned ps_iter_masks
[] = {
6852 0xffff, /* not used */
6858 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6860 Builder
bld(ctx
->program
, ctx
->block
);
6862 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6863 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6864 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6865 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6866 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6867 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6870 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6871 Builder
bld(ctx
->program
, ctx
->block
);
6873 unsigned stream
= nir_intrinsic_stream_id(instr
);
6874 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6875 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6876 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6879 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6881 unsigned num_components
=
6882 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6883 assert(num_components
);
6885 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6886 unsigned stream_offset
= 0;
6887 for (unsigned i
= 0; i
< stream
; i
++) {
6888 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6889 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6892 /* Limit on the stride field for <= GFX7. */
6893 assert(stride
< (1 << 14));
6895 Temp gsvs_dwords
[4];
6896 for (unsigned i
= 0; i
< 4; i
++)
6897 gsvs_dwords
[i
] = bld
.tmp(s1
);
6898 bld
.pseudo(aco_opcode::p_split_vector
,
6899 Definition(gsvs_dwords
[0]),
6900 Definition(gsvs_dwords
[1]),
6901 Definition(gsvs_dwords
[2]),
6902 Definition(gsvs_dwords
[3]),
6905 if (stream_offset
) {
6906 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6908 Temp carry
= bld
.tmp(s1
);
6909 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6910 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6913 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6914 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6916 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6917 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6919 unsigned offset
= 0;
6920 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6921 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6924 for (unsigned j
= 0; j
< 4; j
++) {
6925 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6928 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6929 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6930 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6931 if (const_offset
>= 4096u) {
6932 if (vaddr_offset
.isUndefined())
6933 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6935 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6936 const_offset
%= 4096u;
6939 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6940 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6941 mtbuf
->operands
[1] = vaddr_offset
;
6942 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6943 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6944 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6945 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6946 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6947 mtbuf
->offset
= const_offset
;
6950 mtbuf
->barrier
= barrier_gs_data
;
6951 mtbuf
->can_reorder
= true;
6952 bld
.insert(std::move(mtbuf
));
6955 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6958 /* outputs for the next vertex are undefined and keeping them around can
6959 * create invalid IR with control flow */
6960 ctx
->outputs
.mask
[i
] = 0;
6963 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6966 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6968 Builder
bld(ctx
->program
, ctx
->block
);
6970 if (cluster_size
== 1) {
6972 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6973 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6974 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6975 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6976 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6977 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6978 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6979 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6980 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6981 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6982 //subgroupAnd(val) -> (exec & ~val) == 0
6983 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6984 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6985 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6986 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6987 //subgroupOr(val) -> (val & exec) != 0
6988 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6989 return bool_to_vector_condition(ctx
, tmp
);
6990 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6991 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6992 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6993 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6994 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6995 return bool_to_vector_condition(ctx
, tmp
);
6997 //subgroupClustered{And,Or,Xor}(val, n) ->
6998 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6999 //cluster_offset = ~(n - 1) & lane_id
7000 //cluster_mask = ((1 << n) - 1)
7001 //subgroupClusteredAnd():
7002 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7003 //subgroupClusteredOr():
7004 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7005 //subgroupClusteredXor():
7006 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7007 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7008 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7011 if (op
== nir_op_iand
)
7012 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7014 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7016 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7018 if (ctx
->program
->chip_class
<= GFX7
)
7019 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7020 else if (ctx
->program
->wave_size
== 64)
7021 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7023 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7024 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7025 if (cluster_mask
!= 0xffffffff)
7026 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7028 Definition cmp_def
= Definition();
7029 if (op
== nir_op_iand
) {
7030 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7031 } else if (op
== nir_op_ior
) {
7032 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7033 } else if (op
== nir_op_ixor
) {
7034 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7035 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7036 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7038 cmp_def
.setHint(vcc
);
7039 return cmp_def
.getTemp();
7043 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7045 Builder
bld(ctx
->program
, ctx
->block
);
7047 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7048 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7049 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7051 if (op
== nir_op_iand
)
7052 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7054 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7056 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7057 Temp lo
= lohi
.def(0).getTemp();
7058 Temp hi
= lohi
.def(1).getTemp();
7059 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7061 Definition cmp_def
= Definition();
7062 if (op
== nir_op_iand
)
7063 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7064 else if (op
== nir_op_ior
)
7065 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7066 else if (op
== nir_op_ixor
)
7067 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7068 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7069 cmp_def
.setHint(vcc
);
7070 return cmp_def
.getTemp();
7073 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7075 Builder
bld(ctx
->program
, ctx
->block
);
7077 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7078 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7079 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7080 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7081 if (op
== nir_op_iand
)
7082 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7083 else if (op
== nir_op_ior
)
7084 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7085 else if (op
== nir_op_ixor
)
7086 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7092 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7094 Builder
bld(ctx
->program
, ctx
->block
);
7095 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7096 if (src
.regClass().type() == RegType::vgpr
) {
7097 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7098 } else if (src
.regClass() == s1
) {
7099 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7100 } else if (src
.regClass() == s2
) {
7101 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7103 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7104 nir_print_instr(&instr
->instr
, stderr
);
7105 fprintf(stderr
, "\n");
7109 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7111 Builder
bld(ctx
->program
, ctx
->block
);
7112 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7113 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7114 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7116 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7117 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7118 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7119 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7122 if (ctx
->program
->chip_class
>= GFX8
) {
7123 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7124 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7125 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7126 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7127 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7128 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7130 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7131 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7132 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7133 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7134 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7135 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7136 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7137 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7138 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7139 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7142 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7143 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7144 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7145 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7146 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7147 Temp wqm1
= bld
.tmp(v1
);
7148 emit_wqm(ctx
, tmp1
, wqm1
, true);
7149 Temp wqm2
= bld
.tmp(v1
);
7150 emit_wqm(ctx
, tmp2
, wqm2
, true);
7151 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7155 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7157 Builder
bld(ctx
->program
, ctx
->block
);
7158 switch(instr
->intrinsic
) {
7159 case nir_intrinsic_load_barycentric_sample
:
7160 case nir_intrinsic_load_barycentric_pixel
:
7161 case nir_intrinsic_load_barycentric_centroid
: {
7162 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7163 Temp bary
= Temp(0, s2
);
7165 case INTERP_MODE_SMOOTH
:
7166 case INTERP_MODE_NONE
:
7167 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7168 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7169 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7170 bary
= ctx
->persp_centroid
;
7171 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7172 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7174 case INTERP_MODE_NOPERSPECTIVE
:
7175 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7176 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7177 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7178 bary
= ctx
->linear_centroid
;
7179 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7180 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7185 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7186 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7187 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7188 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7189 Operand(p1
), Operand(p2
));
7190 emit_split_vector(ctx
, dst
, 2);
7193 case nir_intrinsic_load_barycentric_model
: {
7194 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7196 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7197 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7198 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7199 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7200 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7201 Operand(p1
), Operand(p2
), Operand(p3
));
7202 emit_split_vector(ctx
, dst
, 3);
7205 case nir_intrinsic_load_barycentric_at_sample
: {
7206 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7207 switch (ctx
->options
->key
.fs
.num_samples
) {
7208 case 2: sample_pos_offset
+= 1 << 3; break;
7209 case 4: sample_pos_offset
+= 3 << 3; break;
7210 case 8: sample_pos_offset
+= 7 << 3; break;
7214 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7215 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7216 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7217 if (addr
.type() == RegType::sgpr
) {
7220 sample_pos_offset
+= const_addr
->u32
<< 3;
7221 offset
= Operand(sample_pos_offset
);
7222 } else if (ctx
->options
->chip_class
>= GFX9
) {
7223 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7225 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7226 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7229 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7230 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7232 } else if (ctx
->options
->chip_class
>= GFX9
) {
7233 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7234 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7235 } else if (ctx
->options
->chip_class
>= GFX7
) {
7236 /* addr += private_segment_buffer + sample_pos_offset */
7237 Temp tmp0
= bld
.tmp(s1
);
7238 Temp tmp1
= bld
.tmp(s1
);
7239 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7240 Definition scc_tmp
= bld
.def(s1
, scc
);
7241 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7242 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7243 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7244 Temp pck0
= bld
.tmp(v1
);
7245 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7246 tmp1
= as_vgpr(ctx
, tmp1
);
7247 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7248 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7250 /* sample_pos = flat_load_dwordx2 addr */
7251 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7253 assert(ctx
->options
->chip_class
== GFX6
);
7255 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7256 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7257 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7259 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7260 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7262 sample_pos
= bld
.tmp(v2
);
7264 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7265 load
->definitions
[0] = Definition(sample_pos
);
7266 load
->operands
[0] = Operand(rsrc
);
7267 load
->operands
[1] = Operand(addr
);
7268 load
->operands
[2] = Operand(0u);
7269 load
->offset
= sample_pos_offset
;
7271 load
->addr64
= true;
7274 load
->disable_wqm
= false;
7275 load
->barrier
= barrier_none
;
7276 load
->can_reorder
= true;
7277 ctx
->block
->instructions
.emplace_back(std::move(load
));
7280 /* sample_pos -= 0.5 */
7281 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7282 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7283 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7284 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7285 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7287 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7290 case nir_intrinsic_load_barycentric_at_offset
: {
7291 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7292 RegClass rc
= RegClass(offset
.type(), 1);
7293 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7294 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7295 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7298 case nir_intrinsic_load_front_face
: {
7299 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7300 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7303 case nir_intrinsic_load_view_index
: {
7304 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7305 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7306 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7312 case nir_intrinsic_load_layer_id
: {
7313 unsigned idx
= nir_intrinsic_base(instr
);
7314 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7315 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7318 case nir_intrinsic_load_frag_coord
: {
7319 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7322 case nir_intrinsic_load_sample_pos
: {
7323 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7324 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7325 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7326 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7327 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7330 case nir_intrinsic_load_tess_coord
:
7331 visit_load_tess_coord(ctx
, instr
);
7333 case nir_intrinsic_load_interpolated_input
:
7334 visit_load_interpolated_input(ctx
, instr
);
7336 case nir_intrinsic_store_output
:
7337 visit_store_output(ctx
, instr
);
7339 case nir_intrinsic_load_input
:
7340 case nir_intrinsic_load_input_vertex
:
7341 visit_load_input(ctx
, instr
);
7343 case nir_intrinsic_load_output
:
7344 visit_load_output(ctx
, instr
);
7346 case nir_intrinsic_load_per_vertex_input
:
7347 visit_load_per_vertex_input(ctx
, instr
);
7349 case nir_intrinsic_load_per_vertex_output
:
7350 visit_load_per_vertex_output(ctx
, instr
);
7352 case nir_intrinsic_store_per_vertex_output
:
7353 visit_store_per_vertex_output(ctx
, instr
);
7355 case nir_intrinsic_load_ubo
:
7356 visit_load_ubo(ctx
, instr
);
7358 case nir_intrinsic_load_push_constant
:
7359 visit_load_push_constant(ctx
, instr
);
7361 case nir_intrinsic_load_constant
:
7362 visit_load_constant(ctx
, instr
);
7364 case nir_intrinsic_vulkan_resource_index
:
7365 visit_load_resource(ctx
, instr
);
7367 case nir_intrinsic_discard
:
7368 visit_discard(ctx
, instr
);
7370 case nir_intrinsic_discard_if
:
7371 visit_discard_if(ctx
, instr
);
7373 case nir_intrinsic_load_shared
:
7374 visit_load_shared(ctx
, instr
);
7376 case nir_intrinsic_store_shared
:
7377 visit_store_shared(ctx
, instr
);
7379 case nir_intrinsic_shared_atomic_add
:
7380 case nir_intrinsic_shared_atomic_imin
:
7381 case nir_intrinsic_shared_atomic_umin
:
7382 case nir_intrinsic_shared_atomic_imax
:
7383 case nir_intrinsic_shared_atomic_umax
:
7384 case nir_intrinsic_shared_atomic_and
:
7385 case nir_intrinsic_shared_atomic_or
:
7386 case nir_intrinsic_shared_atomic_xor
:
7387 case nir_intrinsic_shared_atomic_exchange
:
7388 case nir_intrinsic_shared_atomic_comp_swap
:
7389 visit_shared_atomic(ctx
, instr
);
7391 case nir_intrinsic_image_deref_load
:
7392 visit_image_load(ctx
, instr
);
7394 case nir_intrinsic_image_deref_store
:
7395 visit_image_store(ctx
, instr
);
7397 case nir_intrinsic_image_deref_atomic_add
:
7398 case nir_intrinsic_image_deref_atomic_umin
:
7399 case nir_intrinsic_image_deref_atomic_imin
:
7400 case nir_intrinsic_image_deref_atomic_umax
:
7401 case nir_intrinsic_image_deref_atomic_imax
:
7402 case nir_intrinsic_image_deref_atomic_and
:
7403 case nir_intrinsic_image_deref_atomic_or
:
7404 case nir_intrinsic_image_deref_atomic_xor
:
7405 case nir_intrinsic_image_deref_atomic_exchange
:
7406 case nir_intrinsic_image_deref_atomic_comp_swap
:
7407 visit_image_atomic(ctx
, instr
);
7409 case nir_intrinsic_image_deref_size
:
7410 visit_image_size(ctx
, instr
);
7412 case nir_intrinsic_load_ssbo
:
7413 visit_load_ssbo(ctx
, instr
);
7415 case nir_intrinsic_store_ssbo
:
7416 visit_store_ssbo(ctx
, instr
);
7418 case nir_intrinsic_load_global
:
7419 visit_load_global(ctx
, instr
);
7421 case nir_intrinsic_store_global
:
7422 visit_store_global(ctx
, instr
);
7424 case nir_intrinsic_global_atomic_add
:
7425 case nir_intrinsic_global_atomic_imin
:
7426 case nir_intrinsic_global_atomic_umin
:
7427 case nir_intrinsic_global_atomic_imax
:
7428 case nir_intrinsic_global_atomic_umax
:
7429 case nir_intrinsic_global_atomic_and
:
7430 case nir_intrinsic_global_atomic_or
:
7431 case nir_intrinsic_global_atomic_xor
:
7432 case nir_intrinsic_global_atomic_exchange
:
7433 case nir_intrinsic_global_atomic_comp_swap
:
7434 visit_global_atomic(ctx
, instr
);
7436 case nir_intrinsic_ssbo_atomic_add
:
7437 case nir_intrinsic_ssbo_atomic_imin
:
7438 case nir_intrinsic_ssbo_atomic_umin
:
7439 case nir_intrinsic_ssbo_atomic_imax
:
7440 case nir_intrinsic_ssbo_atomic_umax
:
7441 case nir_intrinsic_ssbo_atomic_and
:
7442 case nir_intrinsic_ssbo_atomic_or
:
7443 case nir_intrinsic_ssbo_atomic_xor
:
7444 case nir_intrinsic_ssbo_atomic_exchange
:
7445 case nir_intrinsic_ssbo_atomic_comp_swap
:
7446 visit_atomic_ssbo(ctx
, instr
);
7448 case nir_intrinsic_load_scratch
:
7449 visit_load_scratch(ctx
, instr
);
7451 case nir_intrinsic_store_scratch
:
7452 visit_store_scratch(ctx
, instr
);
7454 case nir_intrinsic_get_buffer_size
:
7455 visit_get_buffer_size(ctx
, instr
);
7457 case nir_intrinsic_control_barrier
: {
7458 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7459 /* GFX6 only (thanks to a hw bug workaround):
7460 * The real barrier instruction isn’t needed, because an entire patch
7461 * always fits into a single wave.
7466 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7467 bld
.sopp(aco_opcode::s_barrier
);
7471 case nir_intrinsic_memory_barrier_tcs_patch
:
7472 case nir_intrinsic_group_memory_barrier
:
7473 case nir_intrinsic_memory_barrier
:
7474 case nir_intrinsic_memory_barrier_buffer
:
7475 case nir_intrinsic_memory_barrier_image
:
7476 case nir_intrinsic_memory_barrier_shared
:
7477 emit_memory_barrier(ctx
, instr
);
7479 case nir_intrinsic_load_num_work_groups
: {
7480 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7481 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7482 emit_split_vector(ctx
, dst
, 3);
7485 case nir_intrinsic_load_local_invocation_id
: {
7486 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7487 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7488 emit_split_vector(ctx
, dst
, 3);
7491 case nir_intrinsic_load_work_group_id
: {
7492 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7493 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7495 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7496 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7497 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7498 emit_split_vector(ctx
, dst
, 3);
7501 case nir_intrinsic_load_local_invocation_index
: {
7502 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7504 /* The tg_size bits [6:11] contain the subgroup id,
7505 * we need this multiplied by the wave size, and then OR the thread id to it.
7507 if (ctx
->program
->wave_size
== 64) {
7508 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7509 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7510 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7511 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7513 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7514 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7515 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7516 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7520 case nir_intrinsic_load_subgroup_id
: {
7521 if (ctx
->stage
== compute_cs
) {
7522 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7523 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7525 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7529 case nir_intrinsic_load_subgroup_invocation
: {
7530 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7533 case nir_intrinsic_load_num_subgroups
: {
7534 if (ctx
->stage
== compute_cs
)
7535 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7536 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7538 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7541 case nir_intrinsic_ballot
: {
7542 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7543 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7544 Definition tmp
= bld
.def(dst
.regClass());
7545 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7546 if (instr
->src
[0].ssa
->bit_size
== 1) {
7547 assert(src
.regClass() == bld
.lm
);
7548 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7549 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7550 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7551 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7552 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7554 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7555 nir_print_instr(&instr
->instr
, stderr
);
7556 fprintf(stderr
, "\n");
7558 if (dst
.size() != bld
.lm
.size()) {
7559 /* Wave32 with ballot size set to 64 */
7560 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7562 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7565 case nir_intrinsic_shuffle
:
7566 case nir_intrinsic_read_invocation
: {
7567 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7568 if (!nir_src_is_divergent(instr
->src
[0])) {
7569 emit_uniform_subgroup(ctx
, instr
, src
);
7571 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7572 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7573 tid
= bld
.as_uniform(tid
);
7574 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7575 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7576 Temp tmp
= bld
.tmp(v1
);
7577 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7578 if (dst
.type() == RegType::vgpr
)
7579 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7581 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7582 } else if (src
.regClass() == v1
) {
7583 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7584 } else if (src
.regClass() == v2
) {
7585 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7586 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7587 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7588 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7589 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7590 emit_split_vector(ctx
, dst
, 2);
7591 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7592 assert(src
.regClass() == bld
.lm
);
7593 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7594 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7595 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7596 assert(src
.regClass() == bld
.lm
);
7598 if (ctx
->program
->chip_class
<= GFX7
)
7599 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7600 else if (ctx
->program
->wave_size
== 64)
7601 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7603 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7604 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7605 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7606 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7608 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7609 nir_print_instr(&instr
->instr
, stderr
);
7610 fprintf(stderr
, "\n");
7615 case nir_intrinsic_load_sample_id
: {
7616 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7617 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7620 case nir_intrinsic_load_sample_mask_in
: {
7621 visit_load_sample_mask_in(ctx
, instr
);
7624 case nir_intrinsic_read_first_invocation
: {
7625 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7626 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7627 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7629 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7631 } else if (src
.regClass() == v2
) {
7632 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7633 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7634 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7635 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7636 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7637 emit_split_vector(ctx
, dst
, 2);
7638 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7639 assert(src
.regClass() == bld
.lm
);
7640 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7641 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7642 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7643 } else if (src
.regClass() == s1
) {
7644 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7645 } else if (src
.regClass() == s2
) {
7646 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7648 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7649 nir_print_instr(&instr
->instr
, stderr
);
7650 fprintf(stderr
, "\n");
7654 case nir_intrinsic_vote_all
: {
7655 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7656 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7657 assert(src
.regClass() == bld
.lm
);
7658 assert(dst
.regClass() == bld
.lm
);
7660 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7661 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7662 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7665 case nir_intrinsic_vote_any
: {
7666 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7667 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7668 assert(src
.regClass() == bld
.lm
);
7669 assert(dst
.regClass() == bld
.lm
);
7671 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7672 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7675 case nir_intrinsic_reduce
:
7676 case nir_intrinsic_inclusive_scan
:
7677 case nir_intrinsic_exclusive_scan
: {
7678 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7679 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7680 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7681 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7682 nir_intrinsic_cluster_size(instr
) : 0;
7683 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7685 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7686 emit_uniform_subgroup(ctx
, instr
, src
);
7687 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7688 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7690 else if (op
== nir_op_iadd
)
7692 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7694 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7696 switch (instr
->intrinsic
) {
7697 case nir_intrinsic_reduce
:
7698 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7700 case nir_intrinsic_exclusive_scan
:
7701 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7703 case nir_intrinsic_inclusive_scan
:
7704 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7709 } else if (cluster_size
== 1) {
7710 bld
.copy(Definition(dst
), src
);
7712 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7714 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7718 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7719 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7734 unreachable("unknown reduction op");
7740 switch (instr
->intrinsic
) {
7741 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7742 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7743 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7745 unreachable("unknown reduce intrinsic");
7748 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7749 reduce
->operands
[0] = Operand(src
);
7750 // filled in by aco_reduce_assign.cpp, used internally as part of the
7752 assert(dst
.size() == 1 || dst
.size() == 2);
7753 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7754 reduce
->operands
[2] = Operand(v1
.as_linear());
7756 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7757 reduce
->definitions
[0] = Definition(tmp_dst
);
7758 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7759 reduce
->definitions
[2] = Definition();
7760 reduce
->definitions
[3] = Definition(scc
, s1
);
7761 reduce
->definitions
[4] = Definition();
7762 reduce
->reduce_op
= reduce_op
;
7763 reduce
->cluster_size
= cluster_size
;
7764 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7766 emit_wqm(ctx
, tmp_dst
, dst
);
7770 case nir_intrinsic_quad_broadcast
: {
7771 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7772 if (!nir_dest_is_divergent(instr
->dest
)) {
7773 emit_uniform_subgroup(ctx
, instr
, src
);
7775 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7776 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7777 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7779 if (instr
->dest
.ssa
.bit_size
== 1) {
7780 assert(src
.regClass() == bld
.lm
);
7781 assert(dst
.regClass() == bld
.lm
);
7782 uint32_t half_mask
= 0x11111111u
<< lane
;
7783 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7784 Temp tmp
= bld
.tmp(bld
.lm
);
7785 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7786 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7787 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7788 emit_wqm(ctx
, tmp
, dst
);
7789 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7790 Temp tmp
= bld
.tmp(v1
);
7791 if (ctx
->program
->chip_class
>= GFX8
)
7792 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7794 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7796 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7797 Temp tmp
= bld
.tmp(v1
);
7798 if (ctx
->program
->chip_class
>= GFX8
)
7799 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7801 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7802 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7803 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7804 if (ctx
->program
->chip_class
>= GFX8
)
7805 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7807 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7808 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7809 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7810 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7811 if (ctx
->program
->chip_class
>= GFX8
) {
7812 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7813 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7815 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7816 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7818 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7819 emit_split_vector(ctx
, dst
, 2);
7821 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7822 nir_print_instr(&instr
->instr
, stderr
);
7823 fprintf(stderr
, "\n");
7828 case nir_intrinsic_quad_swap_horizontal
:
7829 case nir_intrinsic_quad_swap_vertical
:
7830 case nir_intrinsic_quad_swap_diagonal
:
7831 case nir_intrinsic_quad_swizzle_amd
: {
7832 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7833 if (!nir_dest_is_divergent(instr
->dest
)) {
7834 emit_uniform_subgroup(ctx
, instr
, src
);
7837 uint16_t dpp_ctrl
= 0;
7838 switch (instr
->intrinsic
) {
7839 case nir_intrinsic_quad_swap_horizontal
:
7840 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7842 case nir_intrinsic_quad_swap_vertical
:
7843 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7845 case nir_intrinsic_quad_swap_diagonal
:
7846 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7848 case nir_intrinsic_quad_swizzle_amd
:
7849 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7854 if (ctx
->program
->chip_class
< GFX8
)
7855 dpp_ctrl
|= (1 << 15);
7857 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7858 if (instr
->dest
.ssa
.bit_size
== 1) {
7859 assert(src
.regClass() == bld
.lm
);
7860 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7861 if (ctx
->program
->chip_class
>= GFX8
)
7862 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7864 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7865 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7866 emit_wqm(ctx
, tmp
, dst
);
7867 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7868 Temp tmp
= bld
.tmp(v1
);
7869 if (ctx
->program
->chip_class
>= GFX8
)
7870 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7872 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7873 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7874 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7875 Temp tmp
= bld
.tmp(v1
);
7876 if (ctx
->program
->chip_class
>= GFX8
)
7877 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7879 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7880 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7881 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7883 if (ctx
->program
->chip_class
>= GFX8
)
7884 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7886 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7887 emit_wqm(ctx
, tmp
, dst
);
7888 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7889 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7890 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7891 if (ctx
->program
->chip_class
>= GFX8
) {
7892 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7893 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7895 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7896 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7898 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7899 emit_split_vector(ctx
, dst
, 2);
7901 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7902 nir_print_instr(&instr
->instr
, stderr
);
7903 fprintf(stderr
, "\n");
7907 case nir_intrinsic_masked_swizzle_amd
: {
7908 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7909 if (!nir_dest_is_divergent(instr
->dest
)) {
7910 emit_uniform_subgroup(ctx
, instr
, src
);
7913 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7914 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7915 if (dst
.regClass() == v1
) {
7917 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7919 } else if (dst
.regClass() == v2
) {
7920 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7921 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7922 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7923 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7924 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7925 emit_split_vector(ctx
, dst
, 2);
7927 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7928 nir_print_instr(&instr
->instr
, stderr
);
7929 fprintf(stderr
, "\n");
7933 case nir_intrinsic_write_invocation_amd
: {
7934 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7935 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7936 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7937 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7938 if (dst
.regClass() == v1
) {
7939 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7940 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7941 } else if (dst
.regClass() == v2
) {
7942 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7943 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7944 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7945 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7946 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7947 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7948 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7949 emit_split_vector(ctx
, dst
, 2);
7951 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7952 nir_print_instr(&instr
->instr
, stderr
);
7953 fprintf(stderr
, "\n");
7957 case nir_intrinsic_mbcnt_amd
: {
7958 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7959 RegClass rc
= RegClass(src
.type(), 1);
7960 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7961 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7963 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7964 emit_wqm(ctx
, wqm_tmp
, dst
);
7967 case nir_intrinsic_load_helper_invocation
: {
7968 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7969 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7970 ctx
->block
->kind
|= block_kind_needs_lowering
;
7971 ctx
->program
->needs_exact
= true;
7974 case nir_intrinsic_is_helper_invocation
: {
7975 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7976 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7977 ctx
->block
->kind
|= block_kind_needs_lowering
;
7978 ctx
->program
->needs_exact
= true;
7981 case nir_intrinsic_demote
:
7982 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7984 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7985 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7986 ctx
->block
->kind
|= block_kind_uses_demote
;
7987 ctx
->program
->needs_exact
= true;
7989 case nir_intrinsic_demote_if
: {
7990 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7991 assert(src
.regClass() == bld
.lm
);
7992 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7993 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7995 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7996 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7997 ctx
->block
->kind
|= block_kind_uses_demote
;
7998 ctx
->program
->needs_exact
= true;
8001 case nir_intrinsic_first_invocation
: {
8002 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8003 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8006 case nir_intrinsic_shader_clock
: {
8008 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8009 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8010 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8011 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8014 case nir_intrinsic_load_vertex_id_zero_base
: {
8015 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8016 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8019 case nir_intrinsic_load_first_vertex
: {
8020 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8021 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8024 case nir_intrinsic_load_base_instance
: {
8025 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8026 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8029 case nir_intrinsic_load_instance_id
: {
8030 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8031 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8034 case nir_intrinsic_load_draw_id
: {
8035 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8036 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8039 case nir_intrinsic_load_invocation_id
: {
8040 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8042 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8043 if (ctx
->options
->chip_class
>= GFX10
)
8044 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8046 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8047 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8048 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8049 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8051 unreachable("Unsupported stage for load_invocation_id");
8056 case nir_intrinsic_load_primitive_id
: {
8057 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8059 switch (ctx
->shader
->info
.stage
) {
8060 case MESA_SHADER_GEOMETRY
:
8061 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8063 case MESA_SHADER_TESS_CTRL
:
8064 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8066 case MESA_SHADER_TESS_EVAL
:
8067 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8070 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8075 case nir_intrinsic_load_patch_vertices_in
: {
8076 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8077 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8079 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8080 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8083 case nir_intrinsic_emit_vertex_with_counter
: {
8084 visit_emit_vertex_with_counter(ctx
, instr
);
8087 case nir_intrinsic_end_primitive_with_counter
: {
8088 unsigned stream
= nir_intrinsic_stream_id(instr
);
8089 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8092 case nir_intrinsic_set_vertex_count
: {
8093 /* unused, the HW keeps track of this for us */
8097 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8098 nir_print_instr(&instr
->instr
, stderr
);
8099 fprintf(stderr
, "\n");
8107 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8108 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8109 enum glsl_base_type
*stype
)
8111 nir_deref_instr
*texture_deref_instr
= NULL
;
8112 nir_deref_instr
*sampler_deref_instr
= NULL
;
8115 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8116 switch (instr
->src
[i
].src_type
) {
8117 case nir_tex_src_texture_deref
:
8118 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8120 case nir_tex_src_sampler_deref
:
8121 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8123 case nir_tex_src_plane
:
8124 plane
= nir_src_as_int(instr
->src
[i
].src
);
8131 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8133 if (!sampler_deref_instr
)
8134 sampler_deref_instr
= texture_deref_instr
;
8137 assert(instr
->op
!= nir_texop_txf_ms
&&
8138 instr
->op
!= nir_texop_samples_identical
);
8139 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8140 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8141 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8142 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8143 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8144 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8146 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8149 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8151 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8152 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8153 Builder
bld(ctx
->program
, ctx
->block
);
8155 /* to avoid unnecessary moves, we split and recombine sampler and image */
8156 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8157 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8158 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8159 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8160 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8161 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8162 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8163 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8165 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8166 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8167 img
[0], img
[1], img
[2], img
[3],
8168 img
[4], img
[5], img
[6], img
[7]);
8169 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8170 samp
[0], samp
[1], samp
[2], samp
[3]);
8173 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8174 instr
->op
== nir_texop_samples_identical
))
8175 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8178 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8179 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8181 Builder
bld(ctx
->program
, ctx
->block
);
8183 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8184 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8185 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8187 Operand
neg_one(0xbf800000u
);
8188 Operand
one(0x3f800000u
);
8189 Operand
two(0x40000000u
);
8190 Operand
four(0x40800000u
);
8192 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8193 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8194 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8196 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8197 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8198 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8199 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8202 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8203 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8204 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8206 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8209 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8210 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8211 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8214 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8215 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8217 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8218 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8221 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8223 Builder
bld(ctx
->program
, ctx
->block
);
8224 Temp ma
, tc
, sc
, id
;
8227 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8229 // see comment in ac_prepare_cube_coords()
8230 if (ctx
->options
->chip_class
<= GFX8
)
8231 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8234 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8236 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8237 vop3a
->operands
[0] = Operand(ma
);
8238 vop3a
->abs
[0] = true;
8239 Temp invma
= bld
.tmp(v1
);
8240 vop3a
->definitions
[0] = Definition(invma
);
8241 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8243 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8245 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8247 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8249 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8251 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8254 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8255 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8257 for (unsigned i
= 0; i
< 2; i
++) {
8258 // see comment in ac_prepare_cube_coords()
8260 Temp deriv_sc
, deriv_tc
;
8261 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8262 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8264 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8266 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8267 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8268 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8269 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8270 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8271 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8272 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8275 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8276 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8280 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8287 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8289 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8291 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8292 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8295 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8296 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8297 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8301 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8303 Builder
bld(ctx
->program
, ctx
->block
);
8304 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8305 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8306 has_clamped_lod
= false;
8307 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8308 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8309 clamped_lod
= Temp();
8310 std::vector
<Temp
> coords
;
8311 std::vector
<Temp
> derivs
;
8312 nir_const_value
*sample_index_cv
= NULL
;
8313 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8314 enum glsl_base_type stype
;
8315 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8317 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8318 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8319 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8320 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8322 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8323 switch (instr
->src
[i
].src_type
) {
8324 case nir_tex_src_coord
: {
8325 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8326 for (unsigned i
= 0; i
< coord
.size(); i
++)
8327 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8330 case nir_tex_src_bias
:
8331 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8334 case nir_tex_src_lod
: {
8335 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8337 if (val
&& val
->f32
<= 0.0) {
8340 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8345 case nir_tex_src_min_lod
:
8346 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8347 has_clamped_lod
= true;
8349 case nir_tex_src_comparator
:
8350 if (instr
->is_shadow
) {
8351 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8355 case nir_tex_src_offset
:
8356 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8357 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8360 case nir_tex_src_ddx
:
8361 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8364 case nir_tex_src_ddy
:
8365 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8368 case nir_tex_src_ms_index
:
8369 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8370 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8371 has_sample_index
= true;
8373 case nir_tex_src_texture_offset
:
8374 case nir_tex_src_sampler_offset
:
8380 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8381 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8383 if (instr
->op
== nir_texop_texture_samples
) {
8384 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8386 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8387 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8388 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8390 Operand default_sample
= Operand(1u);
8391 if (ctx
->options
->robust_buffer_access
) {
8392 /* Extract the second dword of the descriptor, if it's
8393 * all zero, then it's a null descriptor.
8395 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8396 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8397 default_sample
= Operand(is_non_null_descriptor
);
8400 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8401 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8402 samples
, default_sample
, bld
.scc(is_msaa
));
8406 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8407 aco_ptr
<Instruction
> tmp_instr
;
8408 Temp acc
, pack
= Temp();
8410 uint32_t pack_const
= 0;
8411 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8412 if (!const_offset
[i
])
8414 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8417 if (offset
.type() == RegType::sgpr
) {
8418 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8419 if (const_offset
[i
])
8422 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8423 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8426 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8429 if (pack
== Temp()) {
8432 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8436 if (pack_const
&& pack
!= Temp())
8437 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8439 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8440 if (const_offset
[i
])
8443 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8444 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8447 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8450 if (pack
== Temp()) {
8453 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8457 if (pack_const
&& pack
!= Temp())
8458 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8460 if (pack_const
&& pack
== Temp())
8461 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8462 else if (pack
== Temp())
8468 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8469 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8471 /* pack derivatives */
8472 if (has_ddx
|| has_ddy
) {
8473 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8474 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8475 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8476 derivs
= {ddx
, zero
, ddy
, zero
};
8478 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8479 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8480 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8481 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8486 if (instr
->coord_components
> 1 &&
8487 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8489 instr
->op
!= nir_texop_txf
)
8490 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8492 if (instr
->coord_components
> 2 &&
8493 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8494 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8495 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8496 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8498 instr
->op
!= nir_texop_txf
&&
8499 instr
->op
!= nir_texop_txf_ms
&&
8500 instr
->op
!= nir_texop_fragment_fetch
&&
8501 instr
->op
!= nir_texop_fragment_mask_fetch
)
8502 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8504 if (ctx
->options
->chip_class
== GFX9
&&
8505 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8506 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8507 assert(coords
.size() > 0 && coords
.size() < 3);
8509 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8510 Operand((uint32_t) 0) :
8511 Operand((uint32_t) 0x3f000000)));
8514 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8516 if (instr
->op
== nir_texop_samples_identical
)
8517 resource
= fmask_ptr
;
8519 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8520 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8521 instr
->op
!= nir_texop_txs
&&
8522 instr
->op
!= nir_texop_fragment_fetch
&&
8523 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8524 assert(has_sample_index
);
8525 Operand
op(sample_index
);
8526 if (sample_index_cv
)
8527 op
= Operand(sample_index_cv
->u32
);
8528 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8531 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8532 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8533 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8534 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8539 /* Build tex instruction */
8540 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8541 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8542 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8544 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8547 /* gather4 selects the component by dmask and always returns vec4 */
8548 if (instr
->op
== nir_texop_tg4
) {
8549 assert(instr
->dest
.ssa
.num_components
== 4);
8550 if (instr
->is_shadow
)
8553 dmask
= 1 << instr
->component
;
8554 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8555 tmp_dst
= bld
.tmp(v4
);
8556 } else if (instr
->op
== nir_texop_samples_identical
) {
8557 tmp_dst
= bld
.tmp(v1
);
8558 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8559 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8562 aco_ptr
<MIMG_instruction
> tex
;
8563 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8565 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8567 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8568 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8571 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8572 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8574 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8575 tex
->operands
[0] = Operand(resource
);
8576 tex
->operands
[1] = Operand(s4
); /* no sampler */
8577 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8578 if (ctx
->options
->chip_class
== GFX9
&&
8579 instr
->op
== nir_texop_txs
&&
8580 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8582 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8583 } else if (instr
->op
== nir_texop_query_levels
) {
8584 tex
->dmask
= 1 << 3;
8589 tex
->definitions
[0] = Definition(tmp_dst
);
8591 tex
->can_reorder
= true;
8592 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8595 /* divide 3rd value by 6 by multiplying with magic number */
8596 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8597 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8598 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8599 assert(instr
->dest
.ssa
.num_components
== 3);
8600 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8601 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8602 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8603 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8608 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8612 Temp tg4_compare_cube_wa64
= Temp();
8614 if (tg4_integer_workarounds
) {
8615 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8616 tex
->operands
[0] = Operand(resource
);
8617 tex
->operands
[1] = Operand(s4
); /* no sampler */
8618 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8622 Temp size
= bld
.tmp(v2
);
8623 tex
->definitions
[0] = Definition(size
);
8624 tex
->can_reorder
= true;
8625 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8626 emit_split_vector(ctx
, size
, size
.size());
8629 for (unsigned i
= 0; i
< 2; i
++) {
8630 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8631 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8632 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8633 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8636 Temp new_coords
[2] = {
8637 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8638 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8641 if (tg4_integer_cube_workaround
) {
8642 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8643 Temp desc
[resource
.size()];
8644 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8645 Format::PSEUDO
, 1, resource
.size())};
8646 split
->operands
[0] = Operand(resource
);
8647 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8648 desc
[i
] = bld
.tmp(s1
);
8649 split
->definitions
[i
] = Definition(desc
[i
]);
8651 ctx
->block
->instructions
.emplace_back(std::move(split
));
8653 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8654 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8655 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8658 if (stype
== GLSL_TYPE_UINT
) {
8659 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8660 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8661 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8662 bld
.scc(compare_cube_wa
));
8664 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8665 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8666 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8667 bld
.scc(compare_cube_wa
));
8669 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8670 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8672 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8674 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8675 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8676 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8678 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8679 Format::PSEUDO
, resource
.size(), 1)};
8680 for (unsigned i
= 0; i
< resource
.size(); i
++)
8681 vec
->operands
[i
] = Operand(desc
[i
]);
8682 resource
= bld
.tmp(resource
.regClass());
8683 vec
->definitions
[0] = Definition(resource
);
8684 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8686 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8687 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8688 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8689 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8691 coords
[0] = new_coords
[0];
8692 coords
[1] = new_coords
[1];
8695 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8696 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8698 assert(coords
.size() == 1);
8699 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8703 op
= aco_opcode::buffer_load_format_x
; break;
8705 op
= aco_opcode::buffer_load_format_xy
; break;
8707 op
= aco_opcode::buffer_load_format_xyz
; break;
8709 op
= aco_opcode::buffer_load_format_xyzw
; break;
8711 unreachable("Tex instruction loads more than 4 components.");
8714 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8715 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8718 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8720 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8721 mubuf
->operands
[0] = Operand(resource
);
8722 mubuf
->operands
[1] = Operand(coords
[0]);
8723 mubuf
->operands
[2] = Operand((uint32_t) 0);
8724 mubuf
->definitions
[0] = Definition(tmp_dst
);
8725 mubuf
->idxen
= true;
8726 mubuf
->can_reorder
= true;
8727 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8729 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8733 /* gather MIMG address components */
8734 std::vector
<Temp
> args
;
8736 args
.emplace_back(offset
);
8738 args
.emplace_back(bias
);
8740 args
.emplace_back(compare
);
8742 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8744 args
.insert(args
.end(), coords
.begin(), coords
.end());
8745 if (has_sample_index
)
8746 args
.emplace_back(sample_index
);
8748 args
.emplace_back(lod
);
8749 if (has_clamped_lod
)
8750 args
.emplace_back(clamped_lod
);
8752 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8753 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8754 vec
->definitions
[0] = Definition(arg
);
8755 for (unsigned i
= 0; i
< args
.size(); i
++)
8756 vec
->operands
[i
] = Operand(args
[i
]);
8757 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8760 if (instr
->op
== nir_texop_txf
||
8761 instr
->op
== nir_texop_txf_ms
||
8762 instr
->op
== nir_texop_samples_identical
||
8763 instr
->op
== nir_texop_fragment_fetch
||
8764 instr
->op
== nir_texop_fragment_mask_fetch
) {
8765 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8766 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8767 tex
->operands
[0] = Operand(resource
);
8768 tex
->operands
[1] = Operand(s4
); /* no sampler */
8769 tex
->operands
[2] = Operand(arg
);
8774 tex
->definitions
[0] = Definition(tmp_dst
);
8775 tex
->can_reorder
= true;
8776 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8778 if (instr
->op
== nir_texop_samples_identical
) {
8779 assert(dmask
== 1 && dst
.regClass() == v1
);
8780 assert(dst
.id() != tmp_dst
.id());
8782 Temp tmp
= bld
.tmp(bld
.lm
);
8783 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8784 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8787 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8792 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8793 aco_opcode opcode
= aco_opcode::image_sample
;
8794 if (has_offset
) { /* image_sample_*_o */
8795 if (has_clamped_lod
) {
8797 opcode
= aco_opcode::image_sample_c_cl_o
;
8799 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8801 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8803 opcode
= aco_opcode::image_sample_cl_o
;
8805 opcode
= aco_opcode::image_sample_d_cl_o
;
8807 opcode
= aco_opcode::image_sample_b_cl_o
;
8809 } else if (has_compare
) {
8810 opcode
= aco_opcode::image_sample_c_o
;
8812 opcode
= aco_opcode::image_sample_c_d_o
;
8814 opcode
= aco_opcode::image_sample_c_b_o
;
8816 opcode
= aco_opcode::image_sample_c_lz_o
;
8818 opcode
= aco_opcode::image_sample_c_l_o
;
8820 opcode
= aco_opcode::image_sample_o
;
8822 opcode
= aco_opcode::image_sample_d_o
;
8824 opcode
= aco_opcode::image_sample_b_o
;
8826 opcode
= aco_opcode::image_sample_lz_o
;
8828 opcode
= aco_opcode::image_sample_l_o
;
8830 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8832 opcode
= aco_opcode::image_sample_c_cl
;
8834 opcode
= aco_opcode::image_sample_c_d_cl
;
8836 opcode
= aco_opcode::image_sample_c_b_cl
;
8838 opcode
= aco_opcode::image_sample_cl
;
8840 opcode
= aco_opcode::image_sample_d_cl
;
8842 opcode
= aco_opcode::image_sample_b_cl
;
8844 } else { /* no offset */
8846 opcode
= aco_opcode::image_sample_c
;
8848 opcode
= aco_opcode::image_sample_c_d
;
8850 opcode
= aco_opcode::image_sample_c_b
;
8852 opcode
= aco_opcode::image_sample_c_lz
;
8854 opcode
= aco_opcode::image_sample_c_l
;
8856 opcode
= aco_opcode::image_sample
;
8858 opcode
= aco_opcode::image_sample_d
;
8860 opcode
= aco_opcode::image_sample_b
;
8862 opcode
= aco_opcode::image_sample_lz
;
8864 opcode
= aco_opcode::image_sample_l
;
8868 if (instr
->op
== nir_texop_tg4
) {
8869 if (has_offset
) { /* image_gather4_*_o */
8871 opcode
= aco_opcode::image_gather4_c_lz_o
;
8873 opcode
= aco_opcode::image_gather4_c_l_o
;
8875 opcode
= aco_opcode::image_gather4_c_b_o
;
8877 opcode
= aco_opcode::image_gather4_lz_o
;
8879 opcode
= aco_opcode::image_gather4_l_o
;
8881 opcode
= aco_opcode::image_gather4_b_o
;
8885 opcode
= aco_opcode::image_gather4_c_lz
;
8887 opcode
= aco_opcode::image_gather4_c_l
;
8889 opcode
= aco_opcode::image_gather4_c_b
;
8891 opcode
= aco_opcode::image_gather4_lz
;
8893 opcode
= aco_opcode::image_gather4_l
;
8895 opcode
= aco_opcode::image_gather4_b
;
8898 } else if (instr
->op
== nir_texop_lod
) {
8899 opcode
= aco_opcode::image_get_lod
;
8902 /* we don't need the bias, sample index, compare value or offset to be
8903 * computed in WQM but if the p_create_vector copies the coordinates, then it
8904 * needs to be in WQM */
8905 if (ctx
->stage
== fragment_fs
&&
8906 !has_derivs
&& !has_lod
&& !level_zero
&&
8907 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8908 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8909 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8911 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8912 tex
->operands
[0] = Operand(resource
);
8913 tex
->operands
[1] = Operand(sampler
);
8914 tex
->operands
[2] = Operand(arg
);
8918 tex
->definitions
[0] = Definition(tmp_dst
);
8919 tex
->can_reorder
= true;
8920 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8922 if (tg4_integer_cube_workaround
) {
8923 assert(tmp_dst
.id() != dst
.id());
8924 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8926 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8928 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8929 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8931 if (stype
== GLSL_TYPE_UINT
)
8932 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8934 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8935 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8937 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8938 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8939 val
[0], val
[1], val
[2], val
[3]);
8941 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8942 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8947 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
)
8949 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8950 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8953 return Operand(tmp
);
8956 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8958 aco_ptr
<Pseudo_instruction
> phi
;
8959 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8960 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8962 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8963 logical
|= ctx
->block
->kind
& block_kind_merge
;
8964 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8966 /* we want a sorted list of sources, since the predecessor list is also sorted */
8967 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8968 nir_foreach_phi_src(src
, instr
)
8969 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8971 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8972 unsigned num_operands
= 0;
8973 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8974 unsigned num_defined
= 0;
8975 unsigned cur_pred_idx
= 0;
8976 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8977 if (cur_pred_idx
< preds
.size()) {
8978 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8979 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8980 unsigned skipped
= 0;
8981 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8983 if (cur_pred_idx
+ skipped
< preds
.size()) {
8984 for (unsigned i
= 0; i
< skipped
; i
++)
8985 operands
[num_operands
++] = Operand(dst
.regClass());
8986 cur_pred_idx
+= skipped
;
8991 /* Handle missing predecessors at the end. This shouldn't happen with loop
8992 * headers and we can't ignore these sources for loop header phis. */
8993 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8996 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass());
8997 operands
[num_operands
++] = op
;
8998 num_defined
+= !op
.isUndefined();
9000 /* handle block_kind_continue_or_break at loop exit blocks */
9001 while (cur_pred_idx
++ < preds
.size())
9002 operands
[num_operands
++] = Operand(dst
.regClass());
9004 /* If the loop ends with a break, still add a linear continue edge in case
9005 * that break is divergent or continue_or_break is used. We'll either remove
9006 * this operand later in visit_loop() if it's not necessary or replace the
9007 * undef with something correct. */
9008 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9009 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9010 nir_block
*last
= nir_loop_last_block(loop
);
9011 if (last
->successors
[0] != instr
->instr
.block
)
9012 operands
[num_operands
++] = Operand(RegClass());
9015 if (num_defined
== 0) {
9016 Builder
bld(ctx
->program
, ctx
->block
);
9017 if (dst
.regClass() == s1
) {
9018 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9019 } else if (dst
.regClass() == v1
) {
9020 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9022 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9023 for (unsigned i
= 0; i
< dst
.size(); i
++)
9024 vec
->operands
[i
] = Operand(0u);
9025 vec
->definitions
[0] = Definition(dst
);
9026 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9031 /* we can use a linear phi in some cases if one src is undef */
9032 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9033 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9035 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9036 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9037 assert(invert
->kind
& block_kind_invert
);
9039 unsigned then_block
= invert
->linear_preds
[0];
9041 Block
* insert_block
= NULL
;
9042 for (unsigned i
= 0; i
< num_operands
; i
++) {
9043 Operand op
= operands
[i
];
9044 if (op
.isUndefined())
9046 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9047 phi
->operands
[0] = op
;
9050 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9051 phi
->operands
[1] = Operand(dst
.regClass());
9052 phi
->definitions
[0] = Definition(dst
);
9053 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9057 /* try to scalarize vector phis */
9058 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9059 // TODO: scalarize linear phis on divergent ifs
9060 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9061 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9062 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9063 Operand src
= operands
[i
];
9064 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9065 can_scalarize
= false;
9067 if (can_scalarize
) {
9068 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9069 assert(dst
.size() % num_components
== 0);
9070 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9072 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9073 for (unsigned k
= 0; k
< num_components
; k
++) {
9074 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9075 for (unsigned i
= 0; i
< num_operands
; i
++) {
9076 Operand src
= operands
[i
];
9077 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9079 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9080 phi
->definitions
[0] = Definition(phi_dst
);
9081 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9082 new_vec
[k
] = phi_dst
;
9083 vec
->operands
[k
] = Operand(phi_dst
);
9085 vec
->definitions
[0] = Definition(dst
);
9086 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9087 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9092 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9093 for (unsigned i
= 0; i
< num_operands
; i
++)
9094 phi
->operands
[i
] = operands
[i
];
9095 phi
->definitions
[0] = Definition(dst
);
9096 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9100 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9102 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9104 assert(dst
.type() == RegType::sgpr
);
9106 if (dst
.size() == 1) {
9107 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9109 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9110 for (unsigned i
= 0; i
< dst
.size(); i
++)
9111 vec
->operands
[i
] = Operand(0u);
9112 vec
->definitions
[0] = Definition(dst
);
9113 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9117 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9119 Builder
bld(ctx
->program
, ctx
->block
);
9120 Block
*logical_target
;
9121 append_logical_end(ctx
->block
);
9122 unsigned idx
= ctx
->block
->index
;
9124 switch (instr
->type
) {
9125 case nir_jump_break
:
9126 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9127 add_logical_edge(idx
, logical_target
);
9128 ctx
->block
->kind
|= block_kind_break
;
9130 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9131 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9132 /* uniform break - directly jump out of the loop */
9133 ctx
->block
->kind
|= block_kind_uniform
;
9134 ctx
->cf_info
.has_branch
= true;
9135 bld
.branch(aco_opcode::p_branch
);
9136 add_linear_edge(idx
, logical_target
);
9139 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9140 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9142 case nir_jump_continue
:
9143 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9144 add_logical_edge(idx
, logical_target
);
9145 ctx
->block
->kind
|= block_kind_continue
;
9147 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9148 /* for potential uniform breaks after this continue,
9149 we must ensure that they are handled correctly */
9150 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9151 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9152 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9154 /* uniform continue - directly jump to the loop header */
9155 ctx
->block
->kind
|= block_kind_uniform
;
9156 ctx
->cf_info
.has_branch
= true;
9157 bld
.branch(aco_opcode::p_branch
);
9158 add_linear_edge(idx
, logical_target
);
9163 fprintf(stderr
, "Unknown NIR jump instr: ");
9164 nir_print_instr(&instr
->instr
, stderr
);
9165 fprintf(stderr
, "\n");
9169 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9170 ctx
->cf_info
.exec_potentially_empty_break
= true;
9171 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9174 /* remove critical edges from linear CFG */
9175 bld
.branch(aco_opcode::p_branch
);
9176 Block
* break_block
= ctx
->program
->create_and_insert_block();
9177 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9178 break_block
->kind
|= block_kind_uniform
;
9179 add_linear_edge(idx
, break_block
);
9180 /* the loop_header pointer might be invalidated by this point */
9181 if (instr
->type
== nir_jump_continue
)
9182 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9183 add_linear_edge(break_block
->index
, logical_target
);
9184 bld
.reset(break_block
);
9185 bld
.branch(aco_opcode::p_branch
);
9187 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9188 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9189 add_linear_edge(idx
, continue_block
);
9190 append_logical_start(continue_block
);
9191 ctx
->block
= continue_block
;
9195 void visit_block(isel_context
*ctx
, nir_block
*block
)
9197 nir_foreach_instr(instr
, block
) {
9198 switch (instr
->type
) {
9199 case nir_instr_type_alu
:
9200 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9202 case nir_instr_type_load_const
:
9203 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9205 case nir_instr_type_intrinsic
:
9206 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9208 case nir_instr_type_tex
:
9209 visit_tex(ctx
, nir_instr_as_tex(instr
));
9211 case nir_instr_type_phi
:
9212 visit_phi(ctx
, nir_instr_as_phi(instr
));
9214 case nir_instr_type_ssa_undef
:
9215 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9217 case nir_instr_type_deref
:
9219 case nir_instr_type_jump
:
9220 visit_jump(ctx
, nir_instr_as_jump(instr
));
9223 fprintf(stderr
, "Unknown NIR instr type: ");
9224 nir_print_instr(instr
, stderr
);
9225 fprintf(stderr
, "\n");
9230 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9231 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9236 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9237 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9239 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9240 RegClass rc
= vals
[0].regClass();
9242 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9244 unsigned next_pred
= 1;
9246 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9247 Block
& block
= ctx
->program
->blocks
[idx
];
9248 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9249 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9253 if (block
.kind
& block_kind_continue
) {
9254 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9259 bool all_same
= true;
9260 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9261 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9265 val
= vals
[block
.linear_preds
[0] - first
];
9267 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9268 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9269 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9270 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9271 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9272 phi
->definitions
[0] = Definition(val
.getTemp());
9273 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9275 vals
[idx
- first
] = val
;
9278 return vals
[last
- first
];
9281 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9283 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9284 append_logical_end(ctx
->block
);
9285 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9286 Builder
bld(ctx
->program
, ctx
->block
);
9287 bld
.branch(aco_opcode::p_branch
);
9288 unsigned loop_preheader_idx
= ctx
->block
->index
;
9290 Block loop_exit
= Block();
9291 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9292 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9294 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9295 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9296 loop_header
->kind
|= block_kind_loop_header
;
9297 add_edge(loop_preheader_idx
, loop_header
);
9298 ctx
->block
= loop_header
;
9300 /* emit loop body */
9301 unsigned loop_header_idx
= loop_header
->index
;
9302 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9303 append_logical_start(ctx
->block
);
9304 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9306 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9307 if (!ctx
->cf_info
.has_branch
) {
9308 append_logical_end(ctx
->block
);
9309 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9310 /* Discards can result in code running with an empty exec mask.
9311 * This would result in divergent breaks not ever being taken. As a
9312 * workaround, break the loop when the loop mask is empty instead of
9313 * always continuing. */
9314 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9315 unsigned block_idx
= ctx
->block
->index
;
9317 /* create helper blocks to avoid critical edges */
9318 Block
*break_block
= ctx
->program
->create_and_insert_block();
9319 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9320 break_block
->kind
= block_kind_uniform
;
9321 bld
.reset(break_block
);
9322 bld
.branch(aco_opcode::p_branch
);
9323 add_linear_edge(block_idx
, break_block
);
9324 add_linear_edge(break_block
->index
, &loop_exit
);
9326 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9327 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9328 continue_block
->kind
= block_kind_uniform
;
9329 bld
.reset(continue_block
);
9330 bld
.branch(aco_opcode::p_branch
);
9331 add_linear_edge(block_idx
, continue_block
);
9332 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9334 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9335 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9336 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9338 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9339 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9340 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9342 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9345 bld
.reset(ctx
->block
);
9346 bld
.branch(aco_opcode::p_branch
);
9349 /* Fixup phis in loop header from unreachable blocks.
9350 * has_branch/has_divergent_branch also indicates if the loop ends with a
9351 * break/continue instruction, but we don't emit those if unreachable=true */
9353 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9354 bool linear
= ctx
->cf_info
.has_branch
;
9355 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9356 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9357 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9358 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9359 /* the last operand should be the one that needs to be removed */
9360 instr
->operands
.pop_back();
9361 } else if (!is_phi(instr
)) {
9367 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9368 * and the previous one shouldn't both happen at once because a break in the
9369 * merge block would get CSE'd */
9370 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9371 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9372 Operand vals
[num_vals
];
9373 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9374 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9375 if (ctx
->cf_info
.has_branch
)
9376 instr
->operands
.pop_back();
9378 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9379 } else if (!is_phi(instr
)) {
9385 ctx
->cf_info
.has_branch
= false;
9387 // TODO: if the loop has not a single exit, we must add one °°
9388 /* emit loop successor block */
9389 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9390 append_logical_start(ctx
->block
);
9393 // TODO: check if it is beneficial to not branch on continues
9394 /* trim linear phis in loop header */
9395 for (auto&& instr
: loop_entry
->instructions
) {
9396 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9397 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9398 new_phi
->definitions
[0] = instr
->definitions
[0];
9399 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9400 new_phi
->operands
[i
] = instr
->operands
[i
];
9401 /* check that the remaining operands are all the same */
9402 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9403 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9404 instr
.swap(new_phi
);
9405 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9414 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9418 append_logical_end(ctx
->block
);
9419 ctx
->block
->kind
|= block_kind_branch
;
9421 /* branch to linear then block */
9422 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9423 aco_ptr
<Pseudo_branch_instruction
> branch
;
9424 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9425 branch
->operands
[0] = Operand(cond
);
9426 ctx
->block
->instructions
.push_back(std::move(branch
));
9428 ic
->BB_if_idx
= ctx
->block
->index
;
9429 ic
->BB_invert
= Block();
9430 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9431 /* Invert blocks are intentionally not marked as top level because they
9432 * are not part of the logical cfg. */
9433 ic
->BB_invert
.kind
|= block_kind_invert
;
9434 ic
->BB_endif
= Block();
9435 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9436 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9438 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9439 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9440 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9441 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9442 ctx
->cf_info
.parent_if
.is_divergent
= true;
9444 /* divergent branches use cbranch_execz */
9445 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9446 ctx
->cf_info
.exec_potentially_empty_break
= false;
9447 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9449 /** emit logical then block */
9450 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9451 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9452 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9453 ctx
->block
= BB_then_logical
;
9454 append_logical_start(BB_then_logical
);
9457 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9459 Block
*BB_then_logical
= ctx
->block
;
9460 append_logical_end(BB_then_logical
);
9461 /* branch from logical then block to invert block */
9462 aco_ptr
<Pseudo_branch_instruction
> branch
;
9463 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9464 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9465 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9466 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9467 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9468 BB_then_logical
->kind
|= block_kind_uniform
;
9469 assert(!ctx
->cf_info
.has_branch
);
9470 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9471 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9473 /** emit linear then block */
9474 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9475 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9476 BB_then_linear
->kind
|= block_kind_uniform
;
9477 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9478 /* branch from linear then block to invert block */
9479 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9480 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9481 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9483 /** emit invert merge block */
9484 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9485 ic
->invert_idx
= ctx
->block
->index
;
9487 /* branch to linear else block (skip else) */
9488 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9489 branch
->operands
[0] = Operand(ic
->cond
);
9490 ctx
->block
->instructions
.push_back(std::move(branch
));
9492 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9493 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9494 ic
->exec_potentially_empty_break_depth_old
=
9495 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9496 /* divergent branches use cbranch_execz */
9497 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9498 ctx
->cf_info
.exec_potentially_empty_break
= false;
9499 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9501 /** emit logical else block */
9502 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9503 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9504 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9505 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9506 ctx
->block
= BB_else_logical
;
9507 append_logical_start(BB_else_logical
);
9510 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9512 Block
*BB_else_logical
= ctx
->block
;
9513 append_logical_end(BB_else_logical
);
9515 /* branch from logical else block to endif block */
9516 aco_ptr
<Pseudo_branch_instruction
> branch
;
9517 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9518 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9519 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9520 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9521 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9522 BB_else_logical
->kind
|= block_kind_uniform
;
9524 assert(!ctx
->cf_info
.has_branch
);
9525 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9528 /** emit linear else block */
9529 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9530 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9531 BB_else_linear
->kind
|= block_kind_uniform
;
9532 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9534 /* branch from linear else block to endif block */
9535 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9536 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9537 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9540 /** emit endif merge block */
9541 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9542 append_logical_start(ctx
->block
);
9545 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9546 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9547 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9548 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9549 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9550 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9551 !ctx
->cf_info
.parent_if
.is_divergent
) {
9552 ctx
->cf_info
.exec_potentially_empty_break
= false;
9553 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9555 /* uniform control flow never has an empty exec-mask */
9556 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9557 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9558 ctx
->cf_info
.exec_potentially_empty_break
= false;
9559 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9563 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9565 assert(cond
.regClass() == s1
);
9567 append_logical_end(ctx
->block
);
9568 ctx
->block
->kind
|= block_kind_uniform
;
9570 aco_ptr
<Pseudo_branch_instruction
> branch
;
9571 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9572 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9573 branch
->operands
[0] = Operand(cond
);
9574 branch
->operands
[0].setFixed(scc
);
9575 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9577 ic
->BB_if_idx
= ctx
->block
->index
;
9578 ic
->BB_endif
= Block();
9579 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9580 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9582 ctx
->cf_info
.has_branch
= false;
9583 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9585 /** emit then block */
9586 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9587 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9588 add_edge(ic
->BB_if_idx
, BB_then
);
9589 append_logical_start(BB_then
);
9590 ctx
->block
= BB_then
;
9593 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9595 Block
*BB_then
= ctx
->block
;
9597 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9598 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9600 if (!ic
->uniform_has_then_branch
) {
9601 append_logical_end(BB_then
);
9602 /* branch from then block to endif block */
9603 aco_ptr
<Pseudo_branch_instruction
> branch
;
9604 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9605 BB_then
->instructions
.emplace_back(std::move(branch
));
9606 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9607 if (!ic
->then_branch_divergent
)
9608 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9609 BB_then
->kind
|= block_kind_uniform
;
9612 ctx
->cf_info
.has_branch
= false;
9613 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9615 /** emit else block */
9616 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9617 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9618 add_edge(ic
->BB_if_idx
, BB_else
);
9619 append_logical_start(BB_else
);
9620 ctx
->block
= BB_else
;
9623 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9625 Block
*BB_else
= ctx
->block
;
9627 if (!ctx
->cf_info
.has_branch
) {
9628 append_logical_end(BB_else
);
9629 /* branch from then block to endif block */
9630 aco_ptr
<Pseudo_branch_instruction
> branch
;
9631 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9632 BB_else
->instructions
.emplace_back(std::move(branch
));
9633 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9634 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9635 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9636 BB_else
->kind
|= block_kind_uniform
;
9639 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9640 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9642 /** emit endif merge block */
9643 if (!ctx
->cf_info
.has_branch
) {
9644 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9645 append_logical_start(ctx
->block
);
9649 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9651 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9652 Builder
bld(ctx
->program
, ctx
->block
);
9653 aco_ptr
<Pseudo_branch_instruction
> branch
;
9656 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9658 * Uniform conditionals are represented in the following way*) :
9660 * The linear and logical CFG:
9663 * BB_THEN (logical) BB_ELSE (logical)
9667 * *) Exceptions may be due to break and continue statements within loops
9668 * If a break/continue happens within uniform control flow, it branches
9669 * to the loop exit/entry block. Otherwise, it branches to the next
9673 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9674 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9675 cond
= bool_to_scalar_condition(ctx
, cond
);
9677 begin_uniform_if_then(ctx
, &ic
, cond
);
9678 visit_cf_list(ctx
, &if_stmt
->then_list
);
9680 begin_uniform_if_else(ctx
, &ic
);
9681 visit_cf_list(ctx
, &if_stmt
->else_list
);
9683 end_uniform_if(ctx
, &ic
);
9684 } else { /* non-uniform condition */
9686 * To maintain a logical and linear CFG without critical edges,
9687 * non-uniform conditionals are represented in the following way*) :
9692 * BB_THEN (logical) BB_THEN (linear)
9694 * BB_INVERT (linear)
9696 * BB_ELSE (logical) BB_ELSE (linear)
9703 * BB_THEN (logical) BB_ELSE (logical)
9707 * *) Exceptions may be due to break and continue statements within loops
9710 begin_divergent_if_then(ctx
, &ic
, cond
);
9711 visit_cf_list(ctx
, &if_stmt
->then_list
);
9713 begin_divergent_if_else(ctx
, &ic
);
9714 visit_cf_list(ctx
, &if_stmt
->else_list
);
9716 end_divergent_if(ctx
, &ic
);
9719 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9722 static bool visit_cf_list(isel_context
*ctx
,
9723 struct exec_list
*list
)
9725 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9726 switch (node
->type
) {
9727 case nir_cf_node_block
:
9728 visit_block(ctx
, nir_cf_node_as_block(node
));
9730 case nir_cf_node_if
:
9731 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9734 case nir_cf_node_loop
:
9735 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9738 unreachable("unimplemented cf list type");
9744 static void create_null_export(isel_context
*ctx
)
9746 /* Some shader stages always need to have exports.
9747 * So when there is none, we need to add a null export.
9750 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9751 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9752 Builder
bld(ctx
->program
, ctx
->block
);
9753 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9754 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9757 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9759 assert(ctx
->stage
== vertex_vs
||
9760 ctx
->stage
== tess_eval_vs
||
9761 ctx
->stage
== gs_copy_vs
||
9762 ctx
->stage
== ngg_vertex_gs
||
9763 ctx
->stage
== ngg_tess_eval_gs
);
9765 int offset
= (ctx
->stage
& sw_tes
)
9766 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9767 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9768 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9769 if (!is_pos
&& !mask
)
9771 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9773 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9774 exp
->enabled_mask
= mask
;
9775 for (unsigned i
= 0; i
< 4; ++i
) {
9776 if (mask
& (1 << i
))
9777 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9779 exp
->operands
[i
] = Operand(v1
);
9781 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9782 * Setting valid_mask=1 prevents it and has no other effect.
9784 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9786 exp
->compressed
= false;
9788 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9790 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9791 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9796 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9798 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9799 exp
->enabled_mask
= 0;
9800 for (unsigned i
= 0; i
< 4; ++i
)
9801 exp
->operands
[i
] = Operand(v1
);
9802 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9803 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9804 exp
->enabled_mask
|= 0x1;
9806 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9807 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9808 exp
->enabled_mask
|= 0x4;
9810 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9811 if (ctx
->options
->chip_class
< GFX9
) {
9812 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9813 exp
->enabled_mask
|= 0x8;
9815 Builder
bld(ctx
->program
, ctx
->block
);
9817 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9818 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9819 if (exp
->operands
[2].isTemp())
9820 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9822 exp
->operands
[2] = Operand(out
);
9823 exp
->enabled_mask
|= 0x4;
9826 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9828 exp
->compressed
= false;
9829 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9830 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9833 static void create_export_phis(isel_context
*ctx
)
9835 /* Used when exports are needed, but the output temps are defined in a preceding block.
9836 * This function will set up phis in order to access the outputs in the next block.
9839 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9840 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9841 ctx
->block
->instructions
.pop_back();
9843 Builder
bld(ctx
->program
, ctx
->block
);
9845 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9846 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9847 for (unsigned i
= 0; i
< 4; ++i
) {
9848 if (!(mask
& (1 << i
)))
9851 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9852 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9853 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9857 bld
.insert(std::move(logical_start
));
9860 static void create_vs_exports(isel_context
*ctx
)
9862 assert(ctx
->stage
== vertex_vs
||
9863 ctx
->stage
== tess_eval_vs
||
9864 ctx
->stage
== gs_copy_vs
||
9865 ctx
->stage
== ngg_vertex_gs
||
9866 ctx
->stage
== ngg_tess_eval_gs
);
9868 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9869 ? &ctx
->program
->info
->tes
.outinfo
9870 : &ctx
->program
->info
->vs
.outinfo
;
9872 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9873 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9874 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9877 if (ctx
->options
->key
.has_multiview_view_index
) {
9878 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9879 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9882 /* the order these position exports are created is important */
9884 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9885 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9886 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9887 exported_pos
= true;
9889 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9890 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9891 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9892 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9894 if (ctx
->export_clip_dists
) {
9895 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9896 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9897 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9898 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9901 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9902 if (i
< VARYING_SLOT_VAR0
&&
9903 i
!= VARYING_SLOT_LAYER
&&
9904 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9905 i
!= VARYING_SLOT_VIEWPORT
)
9908 export_vs_varying(ctx
, i
, false, NULL
);
9912 create_null_export(ctx
);
9915 static bool export_fs_mrt_z(isel_context
*ctx
)
9917 Builder
bld(ctx
->program
, ctx
->block
);
9918 unsigned enabled_channels
= 0;
9922 for (unsigned i
= 0; i
< 4; ++i
) {
9923 values
[i
] = Operand(v1
);
9926 /* Both stencil and sample mask only need 16-bits. */
9927 if (!ctx
->program
->info
->ps
.writes_z
&&
9928 (ctx
->program
->info
->ps
.writes_stencil
||
9929 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9930 compr
= true; /* COMPR flag */
9932 if (ctx
->program
->info
->ps
.writes_stencil
) {
9933 /* Stencil should be in X[23:16]. */
9934 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9935 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9936 enabled_channels
|= 0x3;
9939 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9940 /* SampleMask should be in Y[15:0]. */
9941 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9942 enabled_channels
|= 0xc;
9945 if (ctx
->program
->info
->ps
.writes_z
) {
9946 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9947 enabled_channels
|= 0x1;
9950 if (ctx
->program
->info
->ps
.writes_stencil
) {
9951 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9952 enabled_channels
|= 0x2;
9955 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9956 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9957 enabled_channels
|= 0x4;
9961 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9962 * writemask component.
9964 if (ctx
->options
->chip_class
== GFX6
&&
9965 ctx
->options
->family
!= CHIP_OLAND
&&
9966 ctx
->options
->family
!= CHIP_HAINAN
) {
9967 enabled_channels
|= 0x1;
9970 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9971 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9976 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9978 Builder
bld(ctx
->program
, ctx
->block
);
9979 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9982 for (unsigned i
= 0; i
< 4; ++i
) {
9983 if (write_mask
& (1 << i
)) {
9984 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9986 values
[i
] = Operand(v1
);
9990 unsigned target
, col_format
;
9991 unsigned enabled_channels
= 0;
9992 aco_opcode compr_op
= (aco_opcode
)0;
9994 slot
-= FRAG_RESULT_DATA0
;
9995 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9996 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9998 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9999 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10000 bool is_16bit
= values
[0].regClass() == v2b
;
10002 switch (col_format
)
10004 case V_028714_SPI_SHADER_ZERO
:
10005 enabled_channels
= 0; /* writemask */
10006 target
= V_008DFC_SQ_EXP_NULL
;
10009 case V_028714_SPI_SHADER_32_R
:
10010 enabled_channels
= 1;
10013 case V_028714_SPI_SHADER_32_GR
:
10014 enabled_channels
= 0x3;
10017 case V_028714_SPI_SHADER_32_AR
:
10018 if (ctx
->options
->chip_class
>= GFX10
) {
10019 /* Special case: on GFX10, the outputs are different for 32_AR */
10020 enabled_channels
= 0x3;
10021 values
[1] = values
[3];
10022 values
[3] = Operand(v1
);
10024 enabled_channels
= 0x9;
10028 case V_028714_SPI_SHADER_FP16_ABGR
:
10029 enabled_channels
= 0x5;
10030 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10032 if (ctx
->options
->chip_class
>= GFX9
) {
10033 /* Pack the FP16 values together instead of converting them to
10034 * FP32 and back to FP16.
10035 * TODO: use p_create_vector and let the compiler optimizes.
10037 compr_op
= aco_opcode::v_pack_b32_f16
;
10039 for (unsigned i
= 0; i
< 4; i
++) {
10040 if ((write_mask
>> i
) & 1)
10041 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10047 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10048 enabled_channels
= 0x5;
10049 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10050 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10052 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10056 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10057 enabled_channels
= 0x5;
10058 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10059 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10061 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10065 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10066 enabled_channels
= 0x5;
10067 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10068 if (is_int8
|| is_int10
) {
10070 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10071 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10073 for (unsigned i
= 0; i
< 4; i
++) {
10074 if ((write_mask
>> i
) & 1) {
10075 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10076 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10080 } else if (is_16bit
) {
10081 for (unsigned i
= 0; i
< 4; i
++) {
10082 if ((write_mask
>> i
) & 1) {
10083 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10084 values
[i
] = Operand(tmp
);
10091 case V_028714_SPI_SHADER_SINT16_ABGR
:
10092 enabled_channels
= 0x5;
10093 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10094 if (is_int8
|| is_int10
) {
10096 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10097 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10098 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10099 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10101 for (unsigned i
= 0; i
< 4; i
++) {
10102 if ((write_mask
>> i
) & 1) {
10103 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10104 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10106 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10107 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10111 } else if (is_16bit
) {
10112 for (unsigned i
= 0; i
< 4; i
++) {
10113 if ((write_mask
>> i
) & 1) {
10114 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10115 values
[i
] = Operand(tmp
);
10121 case V_028714_SPI_SHADER_32_ABGR
:
10122 enabled_channels
= 0xF;
10129 if (target
== V_008DFC_SQ_EXP_NULL
)
10132 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10133 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10135 (col_format
== V_028714_SPI_SHADER_32_R
||
10136 col_format
== V_028714_SPI_SHADER_32_GR
||
10137 col_format
== V_028714_SPI_SHADER_32_AR
||
10138 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10139 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10140 for (int i
= 0; i
< 4; i
++) {
10141 if (!(write_mask
& (1 << i
)))
10144 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10145 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10146 bld
.copy(bld
.def(v1
), Operand(3u)));
10147 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10148 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10152 if ((bool) compr_op
) {
10153 for (int i
= 0; i
< 2; i
++) {
10154 /* check if at least one of the values to be compressed is enabled */
10155 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10157 enabled_channels
|= enabled
<< (i
*2);
10158 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10159 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10160 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10162 values
[i
] = Operand(v1
);
10165 values
[2] = Operand(v1
);
10166 values
[3] = Operand(v1
);
10168 for (int i
= 0; i
< 4; i
++)
10169 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10172 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10173 enabled_channels
, target
, (bool) compr_op
);
10177 static void create_fs_exports(isel_context
*ctx
)
10179 bool exported
= false;
10181 /* Export depth, stencil and sample mask. */
10182 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10183 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10184 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10185 exported
|= export_fs_mrt_z(ctx
);
10187 /* Export all color render targets. */
10188 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10189 if (ctx
->outputs
.mask
[i
])
10190 exported
|= export_fs_mrt_color(ctx
, i
);
10193 create_null_export(ctx
);
10196 static void write_tcs_tess_factors(isel_context
*ctx
)
10198 unsigned outer_comps
;
10199 unsigned inner_comps
;
10201 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10218 Builder
bld(ctx
->program
, ctx
->block
);
10220 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10221 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10222 bld
.sopp(aco_opcode::s_barrier
);
10224 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10225 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10227 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10228 if_context ic_invocation_id_is_zero
;
10229 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10230 bld
.reset(ctx
->block
);
10232 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10234 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10235 unsigned stride
= inner_comps
+ outer_comps
;
10236 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10240 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10242 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10244 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10245 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10246 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10248 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10249 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10251 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10252 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10253 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10254 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10257 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10258 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10259 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10260 unsigned tf_const_offset
= 0;
10262 if (ctx
->program
->chip_class
<= GFX8
) {
10263 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10264 if_context ic_rel_patch_id_is_zero
;
10265 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10266 bld
.reset(ctx
->block
);
10268 /* Store the dynamic HS control word. */
10269 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10270 bld
.mubuf(aco_opcode::buffer_store_dword
,
10271 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10272 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10273 /* disable_wqm */ false, /* glc */ true);
10274 tf_const_offset
+= 4;
10276 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10277 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10278 bld
.reset(ctx
->block
);
10281 assert(stride
== 2 || stride
== 4 || stride
== 6);
10282 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10283 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10285 /* Store to offchip for TES to read - only if TES reads them */
10286 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10287 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10288 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10290 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10291 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10293 if (likely(inner_comps
)) {
10294 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10295 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10299 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10300 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10303 static void emit_stream_output(isel_context
*ctx
,
10304 Temp
const *so_buffers
,
10305 Temp
const *so_write_offset
,
10306 const struct radv_stream_output
*output
)
10308 unsigned num_comps
= util_bitcount(output
->component_mask
);
10309 unsigned writemask
= (1 << num_comps
) - 1;
10310 unsigned loc
= output
->location
;
10311 unsigned buf
= output
->buffer
;
10313 assert(num_comps
&& num_comps
<= 4);
10314 if (!num_comps
|| num_comps
> 4)
10317 unsigned start
= ffs(output
->component_mask
) - 1;
10320 bool all_undef
= true;
10321 assert(ctx
->stage
& hw_vs
);
10322 for (unsigned i
= 0; i
< num_comps
; i
++) {
10323 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10324 all_undef
= all_undef
&& !out
[i
].id();
10329 while (writemask
) {
10331 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10332 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10333 /* GFX6 doesn't support storing vec3, split it. */
10334 writemask
|= 1u << (start
+ 2);
10338 unsigned offset
= output
->offset
+ start
* 4;
10340 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10341 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10342 for (int i
= 0; i
< count
; ++i
)
10343 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10344 vec
->definitions
[0] = Definition(write_data
);
10345 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10350 opcode
= aco_opcode::buffer_store_dword
;
10353 opcode
= aco_opcode::buffer_store_dwordx2
;
10356 opcode
= aco_opcode::buffer_store_dwordx3
;
10359 opcode
= aco_opcode::buffer_store_dwordx4
;
10362 unreachable("Unsupported dword count.");
10365 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10366 store
->operands
[0] = Operand(so_buffers
[buf
]);
10367 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10368 store
->operands
[2] = Operand((uint32_t) 0);
10369 store
->operands
[3] = Operand(write_data
);
10370 if (offset
> 4095) {
10371 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10372 Builder
bld(ctx
->program
, ctx
->block
);
10373 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10375 store
->offset
= offset
;
10377 store
->offen
= true;
10379 store
->dlc
= false;
10381 store
->can_reorder
= true;
10382 ctx
->block
->instructions
.emplace_back(std::move(store
));
10386 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10388 Builder
bld(ctx
->program
, ctx
->block
);
10390 Temp so_buffers
[4];
10391 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10392 for (unsigned i
= 0; i
< 4; i
++) {
10393 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10397 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10398 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10401 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10402 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10404 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10406 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10409 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10411 bld
.reset(ctx
->block
);
10413 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10415 Temp so_write_offset
[4];
10417 for (unsigned i
= 0; i
< 4; i
++) {
10418 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10423 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10424 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10425 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10426 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10428 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10430 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10431 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10432 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10433 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10437 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10438 struct radv_stream_output
*output
=
10439 &ctx
->program
->info
->so
.outputs
[i
];
10440 if (stream
!= output
->stream
)
10443 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10446 begin_divergent_if_else(ctx
, &ic
);
10447 end_divergent_if(ctx
, &ic
);
10450 } /* end namespace */
10452 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10454 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10455 Builder
bld(ctx
->program
, ctx
->block
);
10456 constexpr unsigned hs_idx
= 1u;
10457 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10458 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10459 Operand((8u << 16) | (hs_idx
* 8u)));
10460 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10462 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10464 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10465 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10466 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10467 ls_has_nonzero_hs_threads
);
10468 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10469 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10470 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10471 ls_has_nonzero_hs_threads
);
10472 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10473 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10474 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10475 ls_has_nonzero_hs_threads
);
10477 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10478 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10479 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10482 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10484 /* Split all arguments except for the first (ring_offsets) and the last
10485 * (exec) so that the dead channels don't stay live throughout the program.
10487 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10488 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10489 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10490 startpgm
->definitions
[i
].regClass().size());
10495 void handle_bc_optimize(isel_context
*ctx
)
10497 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10498 Builder
bld(ctx
->program
, ctx
->block
);
10499 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10500 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10501 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10502 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10503 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10504 if (uses_center
&& uses_centroid
) {
10505 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10506 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10508 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10510 for (unsigned i
= 0; i
< 2; i
++) {
10511 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10512 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10513 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10514 persp_centroid
, persp_center
, sel
);
10516 ctx
->persp_centroid
= bld
.tmp(v2
);
10517 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10518 Operand(new_coord
[0]), Operand(new_coord
[1]));
10519 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10522 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10524 for (unsigned i
= 0; i
< 2; i
++) {
10525 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10526 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10527 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10528 linear_centroid
, linear_center
, sel
);
10530 ctx
->linear_centroid
= bld
.tmp(v2
);
10531 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10532 Operand(new_coord
[0]), Operand(new_coord
[1]));
10533 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10538 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10540 Program
*program
= ctx
->program
;
10542 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10544 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10545 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10546 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10547 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10548 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10550 program
->next_fp_mode
.must_flush_denorms32
=
10551 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10552 program
->next_fp_mode
.must_flush_denorms16_64
=
10553 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10554 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10556 program
->next_fp_mode
.care_about_round32
=
10557 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10559 program
->next_fp_mode
.care_about_round16_64
=
10560 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10561 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10563 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10564 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10565 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10566 program
->next_fp_mode
.denorm16_64
= 0;
10568 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10570 /* preserving fp32 denorms is expensive, so only do it if asked */
10571 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10572 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10574 program
->next_fp_mode
.denorm32
= 0;
10576 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10577 program
->next_fp_mode
.round32
= fp_round_tz
;
10579 program
->next_fp_mode
.round32
= fp_round_ne
;
10581 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10582 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10584 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10586 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10589 void cleanup_cfg(Program
*program
)
10591 /* create linear_succs/logical_succs */
10592 for (Block
& BB
: program
->blocks
) {
10593 for (unsigned idx
: BB
.linear_preds
)
10594 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10595 for (unsigned idx
: BB
.logical_preds
)
10596 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10600 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10602 Builder
bld(ctx
->program
, ctx
->block
);
10604 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10605 Temp count
= i
== 0
10606 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10607 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10608 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10610 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10613 if (ctx
->program
->wave_size
== 64) {
10614 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10615 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10616 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10618 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10619 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10625 bool ngg_early_prim_export(isel_context
*ctx
)
10627 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10631 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10633 Builder
bld(ctx
->program
, ctx
->block
);
10635 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10636 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10638 /* Get the id of the current wave within the threadgroup (workgroup) */
10639 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10640 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10642 /* Execute the following code only on the first wave (wave id 0),
10643 * use the SCC def to tell if the wave id is zero or not.
10645 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10647 begin_uniform_if_then(ctx
, &ic
, cond
);
10648 begin_uniform_if_else(ctx
, &ic
);
10649 bld
.reset(ctx
->block
);
10651 /* Number of vertices output by VS/TES */
10652 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10653 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10654 /* Number of primitives output by VS/TES */
10655 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10656 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10658 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10659 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10660 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10662 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10663 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10665 end_uniform_if(ctx
, &ic
);
10667 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10668 bld
.reset(ctx
->block
);
10669 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10672 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10674 Builder
bld(ctx
->program
, ctx
->block
);
10676 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10677 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10680 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10683 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10684 assert(vtxindex
[i
].id());
10687 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10691 /* The initial edge flag is always false in tess eval shaders. */
10692 if (ctx
->stage
== ngg_vertex_gs
) {
10693 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10694 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10698 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10703 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10705 Builder
bld(ctx
->program
, ctx
->block
);
10706 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10708 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10709 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10710 false /* compressed */, true/* done */, false /* valid mask */);
10713 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10715 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10716 * These must always come before VS exports.
10718 * It is recommended to do these as early as possible. They can be at the beginning when
10719 * there is no SW GS and the shader doesn't write edge flags.
10723 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10724 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10726 Builder
bld(ctx
->program
, ctx
->block
);
10727 constexpr unsigned max_vertices_per_primitive
= 3;
10728 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10730 if (ctx
->stage
== ngg_vertex_gs
) {
10731 /* TODO: optimize for points & lines */
10732 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10733 if (ctx
->shader
->info
.tess
.point_mode
)
10734 num_vertices_per_primitive
= 1;
10735 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10736 num_vertices_per_primitive
= 2;
10738 unreachable("Unsupported NGG shader stage");
10741 Temp vtxindex
[max_vertices_per_primitive
];
10742 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10743 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10744 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10745 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10746 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10747 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10748 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10749 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10751 /* Export primitive data to the index buffer. */
10752 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10754 /* Export primitive ID. */
10755 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10756 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10757 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10758 Temp provoking_vtx_index
= vtxindex
[0];
10759 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10761 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10764 begin_divergent_if_else(ctx
, &ic
);
10765 end_divergent_if(ctx
, &ic
);
10768 void ngg_emit_nogs_output(isel_context
*ctx
)
10770 /* Emits NGG GS output, for stages that don't have SW GS. */
10773 Builder
bld(ctx
->program
, ctx
->block
);
10774 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10776 /* NGG streamout is currently disabled by default. */
10777 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10779 if (late_prim_export
) {
10780 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10781 create_export_phis(ctx
);
10782 /* Do what we need to do in the GS threads. */
10783 ngg_emit_nogs_gsthreads(ctx
);
10785 /* What comes next should be executed on ES threads. */
10786 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10787 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10788 bld
.reset(ctx
->block
);
10791 /* Export VS outputs */
10792 ctx
->block
->kind
|= block_kind_export_end
;
10793 create_vs_exports(ctx
);
10795 /* Export primitive ID */
10796 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10799 if (ctx
->stage
== ngg_vertex_gs
) {
10800 /* Wait for GS threads to store primitive ID in LDS. */
10801 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10802 bld
.sopp(aco_opcode::s_barrier
);
10804 /* Calculate LDS address where the GS threads stored the primitive ID. */
10805 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10806 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10807 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10808 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10809 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10810 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10812 /* Load primitive ID from LDS. */
10813 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10814 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10815 /* TES: Just use the patch ID as the primitive ID. */
10816 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10818 unreachable("unsupported NGG shader stage.");
10821 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10822 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10824 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10827 if (late_prim_export
) {
10828 begin_divergent_if_else(ctx
, &ic
);
10829 end_divergent_if(ctx
, &ic
);
10830 bld
.reset(ctx
->block
);
10834 void select_program(Program
*program
,
10835 unsigned shader_count
,
10836 struct nir_shader
*const *shaders
,
10837 ac_shader_config
* config
,
10838 struct radv_shader_args
*args
)
10840 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10841 if_context ic_merged_wave_info
;
10842 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10844 for (unsigned i
= 0; i
< shader_count
; i
++) {
10845 nir_shader
*nir
= shaders
[i
];
10846 init_context(&ctx
, nir
);
10848 setup_fp_mode(&ctx
, nir
);
10851 /* needs to be after init_context() for FS */
10852 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10853 append_logical_start(ctx
.block
);
10855 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10856 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10858 split_arguments(&ctx
, startpgm
);
10862 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10864 if (ngg_early_prim_export(&ctx
))
10865 ngg_emit_nogs_gsthreads(&ctx
);
10868 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10869 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10870 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10871 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10872 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10873 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10874 ctx
.stage
== tess_eval_geometry_gs
));
10876 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10877 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10878 if (check_merged_wave_info
) {
10879 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10880 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10884 Builder
bld(ctx
.program
, ctx
.block
);
10886 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10887 bld
.sopp(aco_opcode::s_barrier
);
10889 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10890 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10892 } else if (ctx
.stage
== geometry_gs
)
10893 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10895 if (ctx
.stage
== fragment_fs
)
10896 handle_bc_optimize(&ctx
);
10898 visit_cf_list(&ctx
, &func
->body
);
10900 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10901 emit_streamout(&ctx
, 0);
10903 if (ctx
.stage
& hw_vs
) {
10904 create_vs_exports(&ctx
);
10905 ctx
.block
->kind
|= block_kind_export_end
;
10906 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10907 ngg_emit_nogs_output(&ctx
);
10908 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10909 Builder
bld(ctx
.program
, ctx
.block
);
10910 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10911 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10912 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10913 write_tcs_tess_factors(&ctx
);
10916 if (ctx
.stage
== fragment_fs
) {
10917 create_fs_exports(&ctx
);
10918 ctx
.block
->kind
|= block_kind_export_end
;
10921 if (endif_merged_wave_info
) {
10922 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10923 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10926 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10927 ngg_emit_nogs_output(&ctx
);
10929 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10930 /* Outputs of the previous stage are inputs to the next stage */
10931 ctx
.inputs
= ctx
.outputs
;
10932 ctx
.outputs
= shader_io_state();
10936 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10938 append_logical_end(ctx
.block
);
10939 ctx
.block
->kind
|= block_kind_uniform
;
10940 Builder
bld(ctx
.program
, ctx
.block
);
10941 if (ctx
.program
->wb_smem_l1_on_end
)
10942 bld
.smem(aco_opcode::s_dcache_wb
, false);
10943 bld
.sopp(aco_opcode::s_endpgm
);
10945 cleanup_cfg(program
);
10948 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10949 ac_shader_config
* config
,
10950 struct radv_shader_args
*args
)
10952 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10954 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10955 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10956 program
->next_fp_mode
.must_flush_denorms32
= false;
10957 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10958 program
->next_fp_mode
.care_about_round32
= false;
10959 program
->next_fp_mode
.care_about_round16_64
= false;
10960 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10961 program
->next_fp_mode
.denorm32
= 0;
10962 program
->next_fp_mode
.round32
= fp_round_ne
;
10963 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10964 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10966 add_startpgm(&ctx
);
10967 append_logical_start(ctx
.block
);
10969 Builder
bld(ctx
.program
, ctx
.block
);
10971 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10973 Operand
stream_id(0u);
10974 if (args
->shader_info
->so
.num_outputs
)
10975 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10976 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10978 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10980 std::stack
<Block
> endif_blocks
;
10982 for (unsigned stream
= 0; stream
< 4; stream
++) {
10983 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10986 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10987 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10990 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10992 unsigned BB_if_idx
= ctx
.block
->index
;
10993 Block BB_endif
= Block();
10994 if (!stream_id
.isConstant()) {
10996 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10997 append_logical_end(ctx
.block
);
10998 ctx
.block
->kind
|= block_kind_uniform
;
10999 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11001 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11003 ctx
.block
= ctx
.program
->create_and_insert_block();
11004 add_edge(BB_if_idx
, ctx
.block
);
11005 bld
.reset(ctx
.block
);
11006 append_logical_start(ctx
.block
);
11009 unsigned offset
= 0;
11010 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11011 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11014 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11015 unsigned length
= util_last_bit(output_usage_mask
);
11016 for (unsigned j
= 0; j
< length
; ++j
) {
11017 if (!(output_usage_mask
& (1 << j
)))
11020 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11021 Temp voffset
= vtx_offset
;
11022 if (const_offset
>= 4096u) {
11023 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11024 const_offset
%= 4096u;
11027 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11028 mubuf
->definitions
[0] = bld
.def(v1
);
11029 mubuf
->operands
[0] = Operand(gsvs_ring
);
11030 mubuf
->operands
[1] = Operand(voffset
);
11031 mubuf
->operands
[2] = Operand(0u);
11032 mubuf
->offen
= true;
11033 mubuf
->offset
= const_offset
;
11036 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11037 mubuf
->barrier
= barrier_none
;
11038 mubuf
->can_reorder
= true;
11040 ctx
.outputs
.mask
[i
] |= 1 << j
;
11041 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11043 bld
.insert(std::move(mubuf
));
11049 if (args
->shader_info
->so
.num_outputs
) {
11050 emit_streamout(&ctx
, stream
);
11051 bld
.reset(ctx
.block
);
11055 create_vs_exports(&ctx
);
11056 ctx
.block
->kind
|= block_kind_export_end
;
11059 if (!stream_id
.isConstant()) {
11060 append_logical_end(ctx
.block
);
11062 /* branch from then block to endif block */
11063 bld
.branch(aco_opcode::p_branch
);
11064 add_edge(ctx
.block
->index
, &BB_endif
);
11065 ctx
.block
->kind
|= block_kind_uniform
;
11067 /* emit else block */
11068 ctx
.block
= ctx
.program
->create_and_insert_block();
11069 add_edge(BB_if_idx
, ctx
.block
);
11070 bld
.reset(ctx
.block
);
11071 append_logical_start(ctx
.block
);
11073 endif_blocks
.push(std::move(BB_endif
));
11077 while (!endif_blocks
.empty()) {
11078 Block BB_endif
= std::move(endif_blocks
.top());
11079 endif_blocks
.pop();
11081 Block
*BB_else
= ctx
.block
;
11083 append_logical_end(BB_else
);
11084 /* branch from else block to endif block */
11085 bld
.branch(aco_opcode::p_branch
);
11086 add_edge(BB_else
->index
, &BB_endif
);
11087 BB_else
->kind
|= block_kind_uniform
;
11089 /** emit endif merge block */
11090 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11091 bld
.reset(ctx
.block
);
11092 append_logical_start(ctx
.block
);
11095 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11097 append_logical_end(ctx
.block
);
11098 ctx
.block
->kind
|= block_kind_uniform
;
11099 bld
.sopp(aco_opcode::s_endpgm
);
11101 cleanup_cfg(program
);