2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <unordered_map>
29 #include "vulkan/radv_shader.h"
30 #include "vulkan/radv_descriptor_set.h"
31 #include "vulkan/radv_shader_args.h"
33 #include "ac_exp_param.h"
34 #include "ac_shader_util.h"
36 #include "util/u_math.h"
38 #define MAX_INLINE_PUSH_CONSTS 8
43 uint8_t mask
[VARYING_SLOT_VAR31
+ 1];
44 Temp outputs
[VARYING_SLOT_VAR31
+ 1][4];
48 const struct radv_nir_compiler_options
*options
;
49 struct radv_shader_args
*args
;
52 uint32_t constant_data_offset
;
55 std::unique_ptr
<Temp
[]> allocated
;
56 std::unordered_map
<unsigned, std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
>> allocated_vec
;
57 Stage stage
; /* Stage */
58 bool has_gfx10_wave64_bpermute
= false;
61 uint16_t loop_nest_depth
= 0;
65 bool has_divergent_continue
= false;
66 bool has_divergent_branch
= false;
69 bool is_divergent
= false;
71 bool exec_potentially_empty_discard
= false; /* set to false when loop_nest_depth==0 && parent_if.is_divergent==false */
72 uint16_t exec_potentially_empty_break_depth
= UINT16_MAX
;
73 /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth
74 * and parent_if.is_divergent==false. Called _break but it's also used for
76 bool exec_potentially_empty_break
= false;
77 std::unique_ptr
<unsigned[]> nir_to_aco
; /* NIR block index to ACO block index */
80 Temp arg_temps
[AC_MAX_ARGS
];
83 Temp persp_centroid
, linear_centroid
;
88 /* gathered information */
89 uint64_t input_masks
[MESA_SHADER_COMPUTE
];
90 uint64_t output_masks
[MESA_SHADER_COMPUTE
];
92 /* VS output information */
93 bool export_clip_dists
;
94 unsigned num_clip_distances
;
95 unsigned num_cull_distances
;
97 /* tessellation information */
98 uint32_t tcs_num_inputs
;
99 uint32_t tcs_num_patches
;
101 /* VS, FS or GS output information */
102 output_state outputs
;
105 Temp
get_arg(isel_context
*ctx
, struct ac_arg arg
)
108 return ctx
->arg_temps
[arg
.arg_index
];
111 unsigned get_interp_input(nir_intrinsic_op intrin
, enum glsl_interp_mode interp
)
114 case INTERP_MODE_SMOOTH
:
115 case INTERP_MODE_NONE
:
116 if (intrin
== nir_intrinsic_load_barycentric_pixel
||
117 intrin
== nir_intrinsic_load_barycentric_at_sample
||
118 intrin
== nir_intrinsic_load_barycentric_at_offset
)
119 return S_0286CC_PERSP_CENTER_ENA(1);
120 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
121 return S_0286CC_PERSP_CENTROID_ENA(1);
122 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
123 return S_0286CC_PERSP_SAMPLE_ENA(1);
125 case INTERP_MODE_NOPERSPECTIVE
:
126 if (intrin
== nir_intrinsic_load_barycentric_pixel
)
127 return S_0286CC_LINEAR_CENTER_ENA(1);
128 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
129 return S_0286CC_LINEAR_CENTROID_ENA(1);
130 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
131 return S_0286CC_LINEAR_SAMPLE_ENA(1);
139 void init_context(isel_context
*ctx
, nir_shader
*shader
)
141 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
142 unsigned lane_mask_size
= ctx
->program
->lane_mask
.size();
144 ctx
->shader
= shader
;
145 ctx
->divergent_vals
= nir_divergence_analysis(shader
, nir_divergence_view_index_uniform
);
147 std::unique_ptr
<Temp
[]> allocated
{new Temp
[impl
->ssa_alloc
]()};
149 unsigned spi_ps_inputs
= 0;
151 std::unique_ptr
<unsigned[]> nir_to_aco
{new unsigned[impl
->num_blocks
]()};
156 nir_foreach_block(block
, impl
) {
157 nir_foreach_instr(instr
, block
) {
158 switch(instr
->type
) {
159 case nir_instr_type_alu
: {
160 nir_alu_instr
*alu_instr
= nir_instr_as_alu(instr
);
161 unsigned size
= alu_instr
->dest
.dest
.ssa
.num_components
;
162 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 64)
164 RegType type
= RegType::sgpr
;
165 switch(alu_instr
->op
) {
187 case nir_op_fround_even
:
196 case nir_op_pack_half_2x16
:
197 case nir_op_unpack_half_2x16_split_x
:
198 case nir_op_unpack_half_2x16_split_y
:
201 case nir_op_fddx_fine
:
202 case nir_op_fddy_fine
:
203 case nir_op_fddx_coarse
:
204 case nir_op_fddy_coarse
:
205 case nir_op_fquantize2f16
:
207 case nir_op_frexp_sig
:
208 case nir_op_frexp_exp
:
209 case nir_op_cube_face_index
:
210 case nir_op_cube_face_coord
:
211 type
= RegType::vgpr
;
224 size
= lane_mask_size
;
232 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
235 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
236 size
= lane_mask_size
;
238 if (ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
]) {
239 type
= RegType::vgpr
;
241 if (allocated
[alu_instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
||
242 allocated
[alu_instr
->src
[2].src
.ssa
->index
].type() == RegType::vgpr
) {
243 type
= RegType::vgpr
;
246 if (alu_instr
->src
[1].src
.ssa
->num_components
== 1 && alu_instr
->src
[2].src
.ssa
->num_components
== 1) {
247 assert(allocated
[alu_instr
->src
[1].src
.ssa
->index
].size() == allocated
[alu_instr
->src
[2].src
.ssa
->index
].size());
248 size
= allocated
[alu_instr
->src
[1].src
.ssa
->index
].size();
253 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
254 size
= lane_mask_size
;
256 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
260 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
261 size
= lane_mask_size
;
263 for (unsigned i
= 0; i
< nir_op_infos
[alu_instr
->op
].num_inputs
; i
++) {
264 if (allocated
[alu_instr
->src
[i
].src
.ssa
->index
].type() == RegType::vgpr
)
265 type
= RegType::vgpr
;
270 allocated
[alu_instr
->dest
.dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
273 case nir_instr_type_load_const
: {
274 unsigned size
= nir_instr_as_load_const(instr
)->def
.num_components
;
275 if (nir_instr_as_load_const(instr
)->def
.bit_size
== 64)
277 else if (nir_instr_as_load_const(instr
)->def
.bit_size
== 1)
278 size
*= lane_mask_size
;
279 allocated
[nir_instr_as_load_const(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
282 case nir_instr_type_intrinsic
: {
283 nir_intrinsic_instr
*intrinsic
= nir_instr_as_intrinsic(instr
);
284 if (!nir_intrinsic_infos
[intrinsic
->intrinsic
].has_dest
)
286 unsigned size
= intrinsic
->dest
.ssa
.num_components
;
287 if (intrinsic
->dest
.ssa
.bit_size
== 64)
289 RegType type
= RegType::sgpr
;
290 switch(intrinsic
->intrinsic
) {
291 case nir_intrinsic_load_push_constant
:
292 case nir_intrinsic_load_work_group_id
:
293 case nir_intrinsic_load_num_work_groups
:
294 case nir_intrinsic_load_subgroup_id
:
295 case nir_intrinsic_load_num_subgroups
:
296 case nir_intrinsic_load_first_vertex
:
297 case nir_intrinsic_load_base_instance
:
298 case nir_intrinsic_get_buffer_size
:
299 case nir_intrinsic_vote_all
:
300 case nir_intrinsic_vote_any
:
301 case nir_intrinsic_read_first_invocation
:
302 case nir_intrinsic_read_invocation
:
303 case nir_intrinsic_first_invocation
:
304 type
= RegType::sgpr
;
305 if (intrinsic
->dest
.ssa
.bit_size
== 1)
306 size
= lane_mask_size
;
308 case nir_intrinsic_ballot
:
309 type
= RegType::sgpr
;
311 case nir_intrinsic_load_sample_id
:
312 case nir_intrinsic_load_sample_mask_in
:
313 case nir_intrinsic_load_input
:
314 case nir_intrinsic_load_input_vertex
:
315 case nir_intrinsic_load_per_vertex_input
:
316 case nir_intrinsic_load_vertex_id
:
317 case nir_intrinsic_load_vertex_id_zero_base
:
318 case nir_intrinsic_load_barycentric_sample
:
319 case nir_intrinsic_load_barycentric_pixel
:
320 case nir_intrinsic_load_barycentric_model
:
321 case nir_intrinsic_load_barycentric_centroid
:
322 case nir_intrinsic_load_barycentric_at_sample
:
323 case nir_intrinsic_load_barycentric_at_offset
:
324 case nir_intrinsic_load_interpolated_input
:
325 case nir_intrinsic_load_frag_coord
:
326 case nir_intrinsic_load_sample_pos
:
327 case nir_intrinsic_load_layer_id
:
328 case nir_intrinsic_load_local_invocation_id
:
329 case nir_intrinsic_load_local_invocation_index
:
330 case nir_intrinsic_load_subgroup_invocation
:
331 case nir_intrinsic_load_tess_coord
:
332 case nir_intrinsic_write_invocation_amd
:
333 case nir_intrinsic_mbcnt_amd
:
334 case nir_intrinsic_load_instance_id
:
335 case nir_intrinsic_ssbo_atomic_add
:
336 case nir_intrinsic_ssbo_atomic_imin
:
337 case nir_intrinsic_ssbo_atomic_umin
:
338 case nir_intrinsic_ssbo_atomic_imax
:
339 case nir_intrinsic_ssbo_atomic_umax
:
340 case nir_intrinsic_ssbo_atomic_and
:
341 case nir_intrinsic_ssbo_atomic_or
:
342 case nir_intrinsic_ssbo_atomic_xor
:
343 case nir_intrinsic_ssbo_atomic_exchange
:
344 case nir_intrinsic_ssbo_atomic_comp_swap
:
345 case nir_intrinsic_global_atomic_add
:
346 case nir_intrinsic_global_atomic_imin
:
347 case nir_intrinsic_global_atomic_umin
:
348 case nir_intrinsic_global_atomic_imax
:
349 case nir_intrinsic_global_atomic_umax
:
350 case nir_intrinsic_global_atomic_and
:
351 case nir_intrinsic_global_atomic_or
:
352 case nir_intrinsic_global_atomic_xor
:
353 case nir_intrinsic_global_atomic_exchange
:
354 case nir_intrinsic_global_atomic_comp_swap
:
355 case nir_intrinsic_image_deref_atomic_add
:
356 case nir_intrinsic_image_deref_atomic_umin
:
357 case nir_intrinsic_image_deref_atomic_imin
:
358 case nir_intrinsic_image_deref_atomic_umax
:
359 case nir_intrinsic_image_deref_atomic_imax
:
360 case nir_intrinsic_image_deref_atomic_and
:
361 case nir_intrinsic_image_deref_atomic_or
:
362 case nir_intrinsic_image_deref_atomic_xor
:
363 case nir_intrinsic_image_deref_atomic_exchange
:
364 case nir_intrinsic_image_deref_atomic_comp_swap
:
365 case nir_intrinsic_image_deref_size
:
366 case nir_intrinsic_shared_atomic_add
:
367 case nir_intrinsic_shared_atomic_imin
:
368 case nir_intrinsic_shared_atomic_umin
:
369 case nir_intrinsic_shared_atomic_imax
:
370 case nir_intrinsic_shared_atomic_umax
:
371 case nir_intrinsic_shared_atomic_and
:
372 case nir_intrinsic_shared_atomic_or
:
373 case nir_intrinsic_shared_atomic_xor
:
374 case nir_intrinsic_shared_atomic_exchange
:
375 case nir_intrinsic_shared_atomic_comp_swap
:
376 case nir_intrinsic_load_scratch
:
377 case nir_intrinsic_load_invocation_id
:
378 case nir_intrinsic_load_primitive_id
:
379 type
= RegType::vgpr
;
381 case nir_intrinsic_shuffle
:
382 case nir_intrinsic_quad_broadcast
:
383 case nir_intrinsic_quad_swap_horizontal
:
384 case nir_intrinsic_quad_swap_vertical
:
385 case nir_intrinsic_quad_swap_diagonal
:
386 case nir_intrinsic_quad_swizzle_amd
:
387 case nir_intrinsic_masked_swizzle_amd
:
388 case nir_intrinsic_inclusive_scan
:
389 case nir_intrinsic_exclusive_scan
:
390 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
391 size
= lane_mask_size
;
392 type
= RegType::sgpr
;
393 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
394 type
= RegType::sgpr
;
396 type
= RegType::vgpr
;
399 case nir_intrinsic_load_view_index
:
400 type
= ctx
->stage
== fragment_fs
? RegType::vgpr
: RegType::sgpr
;
402 case nir_intrinsic_load_front_face
:
403 case nir_intrinsic_load_helper_invocation
:
404 case nir_intrinsic_is_helper_invocation
:
405 type
= RegType::sgpr
;
406 size
= lane_mask_size
;
408 case nir_intrinsic_reduce
:
409 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
410 size
= lane_mask_size
;
411 type
= RegType::sgpr
;
412 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
413 type
= RegType::sgpr
;
415 type
= RegType::vgpr
;
418 case nir_intrinsic_load_ubo
:
419 case nir_intrinsic_load_ssbo
:
420 case nir_intrinsic_load_global
:
421 case nir_intrinsic_vulkan_resource_index
:
422 type
= ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
424 /* due to copy propagation, the swizzled imov is removed if num dest components == 1 */
425 case nir_intrinsic_load_shared
:
426 if (ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
])
427 type
= RegType::vgpr
;
429 type
= RegType::sgpr
;
432 for (unsigned i
= 0; i
< nir_intrinsic_infos
[intrinsic
->intrinsic
].num_srcs
; i
++) {
433 if (allocated
[intrinsic
->src
[i
].ssa
->index
].type() == RegType::vgpr
)
434 type
= RegType::vgpr
;
438 allocated
[intrinsic
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
440 switch(intrinsic
->intrinsic
) {
441 case nir_intrinsic_load_barycentric_sample
:
442 case nir_intrinsic_load_barycentric_pixel
:
443 case nir_intrinsic_load_barycentric_centroid
:
444 case nir_intrinsic_load_barycentric_at_sample
:
445 case nir_intrinsic_load_barycentric_at_offset
: {
446 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(intrinsic
);
447 spi_ps_inputs
|= get_interp_input(intrinsic
->intrinsic
, mode
);
450 case nir_intrinsic_load_barycentric_model
:
451 spi_ps_inputs
|= S_0286CC_PERSP_PULL_MODEL_ENA(1);
453 case nir_intrinsic_load_front_face
:
454 spi_ps_inputs
|= S_0286CC_FRONT_FACE_ENA(1);
456 case nir_intrinsic_load_frag_coord
:
457 case nir_intrinsic_load_sample_pos
: {
458 uint8_t mask
= nir_ssa_def_components_read(&intrinsic
->dest
.ssa
);
459 for (unsigned i
= 0; i
< 4; i
++) {
461 spi_ps_inputs
|= S_0286CC_POS_X_FLOAT_ENA(1) << i
;
466 case nir_intrinsic_load_sample_id
:
467 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
469 case nir_intrinsic_load_sample_mask_in
:
470 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
471 spi_ps_inputs
|= S_0286CC_SAMPLE_COVERAGE_ENA(1);
478 case nir_instr_type_tex
: {
479 nir_tex_instr
* tex
= nir_instr_as_tex(instr
);
480 unsigned size
= tex
->dest
.ssa
.num_components
;
482 if (tex
->dest
.ssa
.bit_size
== 64)
484 if (tex
->op
== nir_texop_texture_samples
)
485 assert(!ctx
->divergent_vals
[tex
->dest
.ssa
.index
]);
486 if (ctx
->divergent_vals
[tex
->dest
.ssa
.index
])
487 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::vgpr
, size
));
489 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
492 case nir_instr_type_parallel_copy
: {
493 nir_foreach_parallel_copy_entry(entry
, nir_instr_as_parallel_copy(instr
)) {
494 allocated
[entry
->dest
.ssa
.index
] = allocated
[entry
->src
.ssa
->index
];
498 case nir_instr_type_ssa_undef
: {
499 unsigned size
= nir_instr_as_ssa_undef(instr
)->def
.num_components
;
500 if (nir_instr_as_ssa_undef(instr
)->def
.bit_size
== 64)
502 allocated
[nir_instr_as_ssa_undef(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
505 case nir_instr_type_phi
: {
506 nir_phi_instr
* phi
= nir_instr_as_phi(instr
);
508 unsigned size
= phi
->dest
.ssa
.num_components
;
510 if (phi
->dest
.ssa
.bit_size
== 1) {
511 assert(size
== 1 && "multiple components not yet supported on boolean phis.");
512 type
= RegType::sgpr
;
513 size
*= lane_mask_size
;
514 allocated
[phi
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
518 if (ctx
->divergent_vals
[phi
->dest
.ssa
.index
]) {
519 type
= RegType::vgpr
;
521 type
= RegType::sgpr
;
522 nir_foreach_phi_src (src
, phi
) {
523 if (allocated
[src
->src
.ssa
->index
].type() == RegType::vgpr
)
524 type
= RegType::vgpr
;
525 if (allocated
[src
->src
.ssa
->index
].type() == RegType::none
)
530 size
*= phi
->dest
.ssa
.bit_size
== 64 ? 2 : 1;
531 RegClass rc
= RegClass(type
, size
);
532 if (rc
!= allocated
[phi
->dest
.ssa
.index
].regClass()) {
535 nir_foreach_phi_src(src
, phi
)
536 assert(allocated
[src
->src
.ssa
->index
].size() == rc
.size());
538 allocated
[phi
->dest
.ssa
.index
] = Temp(0, rc
);
548 if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_inputs
)) {
549 /* If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be enabled too */
550 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
553 if (!(spi_ps_inputs
& 0x7F)) {
554 /* At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled */
555 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
558 ctx
->program
->config
->spi_ps_input_ena
= spi_ps_inputs
;
559 ctx
->program
->config
->spi_ps_input_addr
= spi_ps_inputs
;
561 for (unsigned i
= 0; i
< impl
->ssa_alloc
; i
++)
562 allocated
[i
] = Temp(ctx
->program
->allocateId(), allocated
[i
].regClass());
564 ctx
->allocated
.reset(allocated
.release());
565 ctx
->cf_info
.nir_to_aco
.reset(nir_to_aco
.release());
568 Pseudo_instruction
*add_startpgm(struct isel_context
*ctx
)
570 unsigned arg_count
= ctx
->args
->ac
.arg_count
;
571 if (ctx
->stage
== fragment_fs
) {
572 /* LLVM optimizes away unused FS inputs and computes spi_ps_input_addr
573 * itself and then communicates the results back via the ELF binary.
574 * Mirror what LLVM does by re-mapping the VGPR arguments here.
576 * TODO: If we made the FS input scanning code into a separate pass that
577 * could run before argument setup, then this wouldn't be necessary
580 struct ac_shader_args
*args
= &ctx
->args
->ac
;
582 for (unsigned i
= 0, vgpr_arg
= 0, vgpr_reg
= 0; i
< args
->arg_count
; i
++) {
583 if (args
->args
[i
].file
!= AC_ARG_VGPR
) {
588 if (!(ctx
->program
->config
->spi_ps_input_addr
& (1 << vgpr_arg
))) {
589 args
->args
[i
].skip
= true;
591 args
->args
[i
].offset
= vgpr_reg
;
592 vgpr_reg
+= args
->args
[i
].size
;
599 aco_ptr
<Pseudo_instruction
> startpgm
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_startpgm
, Format::PSEUDO
, 0, arg_count
+ 1)};
600 for (unsigned i
= 0, arg
= 0; i
< ctx
->args
->ac
.arg_count
; i
++) {
601 if (ctx
->args
->ac
.args
[i
].skip
)
604 enum ac_arg_regfile file
= ctx
->args
->ac
.args
[i
].file
;
605 unsigned size
= ctx
->args
->ac
.args
[i
].size
;
606 unsigned reg
= ctx
->args
->ac
.args
[i
].offset
;
607 RegClass type
= RegClass(file
== AC_ARG_SGPR
? RegType::sgpr
: RegType::vgpr
, size
);
608 Temp dst
= Temp
{ctx
->program
->allocateId(), type
};
609 ctx
->arg_temps
[i
] = dst
;
610 startpgm
->definitions
[arg
] = Definition(dst
);
611 startpgm
->definitions
[arg
].setFixed(PhysReg
{file
== AC_ARG_SGPR
? reg
: reg
+ 256});
614 startpgm
->definitions
[arg_count
] = Definition
{ctx
->program
->allocateId(), exec
, ctx
->program
->lane_mask
};
615 Pseudo_instruction
*instr
= startpgm
.get();
616 ctx
->block
->instructions
.push_back(std::move(startpgm
));
618 /* Stash these in the program so that they can be accessed later when
621 ctx
->program
->private_segment_buffer
= get_arg(ctx
, ctx
->args
->ring_offsets
);
622 ctx
->program
->scratch_offset
= get_arg(ctx
, ctx
->args
->scratch_offset
);
628 type_size(const struct glsl_type
*type
, bool bindless
)
630 // TODO: don't we need type->std430_base_alignment() here?
631 return glsl_count_attribute_slots(type
, false);
635 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
637 assert(glsl_type_is_vector_or_scalar(type
));
639 uint32_t comp_size
= glsl_type_is_boolean(type
)
640 ? 4 : glsl_get_bit_size(type
) / 8;
641 unsigned length
= glsl_get_vector_elements(type
);
642 *size
= comp_size
* length
,
647 mem_vectorize_callback(unsigned align
, unsigned bit_size
,
648 unsigned num_components
, unsigned high_offset
,
649 nir_intrinsic_instr
*low
, nir_intrinsic_instr
*high
)
651 if ((bit_size
!= 32 && bit_size
!= 64) || num_components
> 4)
654 /* >128 bit loads are split except with SMEM */
655 if (bit_size
* num_components
> 128)
658 switch (low
->intrinsic
) {
659 case nir_intrinsic_load_ubo
:
660 case nir_intrinsic_load_ssbo
:
661 case nir_intrinsic_store_ssbo
:
662 case nir_intrinsic_load_push_constant
:
663 return align
% 4 == 0;
664 case nir_intrinsic_load_deref
:
665 case nir_intrinsic_store_deref
:
666 assert(nir_src_as_deref(low
->src
[0])->mode
== nir_var_mem_shared
);
668 case nir_intrinsic_load_shared
:
669 case nir_intrinsic_store_shared
:
670 if (bit_size
* num_components
> 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
671 return align
% 16 == 0;
673 return align
% 4 == 0;
681 setup_vs_output_info(isel_context
*ctx
, nir_shader
*nir
,
682 bool export_prim_id
, bool export_clip_dists
,
683 radv_vs_output_info
*outinfo
)
685 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
686 sizeof(outinfo
->vs_output_param_offset
));
688 outinfo
->param_exports
= 0;
689 int pos_written
= 0x1;
690 if (outinfo
->writes_pointsize
|| outinfo
->writes_viewport_index
|| outinfo
->writes_layer
)
691 pos_written
|= 1 << 1;
693 uint64_t mask
= ctx
->output_masks
[nir
->info
.stage
];
695 int idx
= u_bit_scan64(&mask
);
696 if (idx
>= VARYING_SLOT_VAR0
|| idx
== VARYING_SLOT_LAYER
|| idx
== VARYING_SLOT_PRIMITIVE_ID
||
697 ((idx
== VARYING_SLOT_CLIP_DIST0
|| idx
== VARYING_SLOT_CLIP_DIST1
) && export_clip_dists
)) {
698 if (outinfo
->vs_output_param_offset
[idx
] == AC_EXP_PARAM_UNDEFINED
)
699 outinfo
->vs_output_param_offset
[idx
] = outinfo
->param_exports
++;
702 if (outinfo
->writes_layer
&&
703 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] == AC_EXP_PARAM_UNDEFINED
) {
704 /* when ctx->options->key.has_multiview_view_index = true, the layer
705 * variable isn't declared in NIR and it's isel's job to get the layer */
706 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = outinfo
->param_exports
++;
709 if (export_prim_id
) {
710 assert(outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] == AC_EXP_PARAM_UNDEFINED
);
711 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = outinfo
->param_exports
++;
714 ctx
->export_clip_dists
= export_clip_dists
;
715 ctx
->num_clip_distances
= util_bitcount(outinfo
->clip_dist_mask
);
716 ctx
->num_cull_distances
= util_bitcount(outinfo
->cull_dist_mask
);
718 assert(ctx
->num_clip_distances
+ ctx
->num_cull_distances
<= 8);
720 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
721 pos_written
|= 1 << 2;
722 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
723 pos_written
|= 1 << 3;
725 outinfo
->pos_exports
= util_bitcount(pos_written
);
729 setup_vs_variables(isel_context
*ctx
, nir_shader
*nir
)
731 nir_foreach_variable(variable
, &nir
->inputs
)
733 variable
->data
.driver_location
= variable
->data
.location
* 4;
735 nir_foreach_variable(variable
, &nir
->outputs
)
737 if (ctx
->stage
== vertex_geometry_gs
)
738 variable
->data
.driver_location
= util_bitcount64(ctx
->output_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
739 else if (ctx
->stage
== vertex_es
||
740 ctx
->stage
== vertex_ls
||
741 ctx
->stage
== vertex_tess_control_hs
)
742 // TODO: make this more compact
743 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
744 else if (ctx
->stage
== vertex_vs
)
745 variable
->data
.driver_location
= variable
->data
.location
* 4;
747 unreachable("Unsupported VS stage");
750 if (ctx
->stage
== vertex_vs
) {
751 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
752 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
753 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
754 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== vertex_es
) {
755 /* TODO: radv_nir_shader_info_pass() already sets this but it's larger
756 * than it needs to be in order to set it better, we have to improve
757 * radv_nir_shader_info_pass() because gfx9_get_gs_info() uses
758 * esgs_itemsize and has to be done before compilation
760 /* radv_es_output_info *outinfo = &ctx->program->info->vs.es_info;
761 outinfo->esgs_itemsize = util_bitcount64(ctx->output_masks[nir->info.stage]) * 16u; */
765 void setup_gs_variables(isel_context
*ctx
, nir_shader
*nir
)
767 assert(ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== geometry_gs
);
768 if (ctx
->stage
== vertex_geometry_gs
) {
769 nir_foreach_variable(variable
, &nir
->inputs
) {
770 variable
->data
.driver_location
= util_bitcount64(ctx
->input_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
773 //TODO: make this more compact
774 nir_foreach_variable(variable
, &nir
->inputs
) {
775 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
)variable
->data
.location
) * 4;
778 nir_foreach_variable(variable
, &nir
->outputs
) {
779 variable
->data
.driver_location
= variable
->data
.location
* 4;
782 if (ctx
->stage
== vertex_geometry_gs
)
783 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_VERTEX
; /* tesselation shaders are not yet supported */
787 setup_tcs_variables(isel_context
*ctx
, nir_shader
*nir
)
789 switch (ctx
->stage
) {
790 case tess_control_hs
:
791 ctx
->tcs_num_inputs
= ctx
->args
->options
->key
.tcs
.num_inputs
;
793 case vertex_tess_control_hs
:
794 ctx
->tcs_num_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
797 unreachable("Unsupported TCS shader stage");
800 ctx
->tcs_num_patches
= get_tcs_num_patches(
801 ctx
->args
->options
->key
.tcs
.input_vertices
,
802 nir
->info
.tess
.tcs_vertices_out
,
804 ctx
->args
->shader_info
->tcs
.outputs_written
,
805 ctx
->args
->shader_info
->tcs
.patch_outputs_written
,
806 ctx
->args
->options
->tess_offchip_block_dw_size
,
807 ctx
->args
->options
->chip_class
,
808 ctx
->args
->options
->family
);
809 unsigned lds_size
= calculate_tess_lds_size(
810 ctx
->args
->options
->key
.tcs
.input_vertices
,
811 nir
->info
.tess
.tcs_vertices_out
,
813 ctx
->tcs_num_patches
,
814 ctx
->args
->shader_info
->tcs
.outputs_written
,
815 ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
817 ctx
->args
->shader_info
->tcs
.num_patches
= ctx
->tcs_num_patches
;
818 ctx
->args
->shader_info
->tcs
.lds_size
= lds_size
;
819 ctx
->program
->config
->lds_size
= (lds_size
+ ctx
->program
->lds_alloc_granule
- 1) /
820 ctx
->program
->lds_alloc_granule
;
822 nir_foreach_variable(variable
, &nir
->inputs
) {
823 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
826 nir_foreach_variable(variable
, &nir
->outputs
) {
827 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
832 setup_variables(isel_context
*ctx
, nir_shader
*nir
)
834 switch (nir
->info
.stage
) {
835 case MESA_SHADER_FRAGMENT
: {
836 nir_foreach_variable(variable
, &nir
->outputs
)
838 int idx
= variable
->data
.location
+ variable
->data
.index
;
839 variable
->data
.driver_location
= idx
* 4;
843 case MESA_SHADER_COMPUTE
: {
844 ctx
->program
->config
->lds_size
= (nir
->info
.cs
.shared_size
+ ctx
->program
->lds_alloc_granule
- 1) /
845 ctx
->program
->lds_alloc_granule
;
848 case MESA_SHADER_VERTEX
: {
849 setup_vs_variables(ctx
, nir
);
852 case MESA_SHADER_GEOMETRY
: {
853 setup_gs_variables(ctx
, nir
);
856 case MESA_SHADER_TESS_CTRL
: {
857 setup_tcs_variables(ctx
, nir
);
861 unreachable("Unhandled shader stage.");
866 get_io_masks(isel_context
*ctx
, unsigned shader_count
, struct nir_shader
*const *shaders
)
868 for (unsigned i
= 0; i
< shader_count
; i
++) {
869 nir_shader
*nir
= shaders
[i
];
870 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
873 uint64_t output_mask
= 0;
874 nir_foreach_variable(variable
, &nir
->outputs
) {
875 const glsl_type
*type
= variable
->type
;
876 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
877 type
= type
->fields
.array
;
878 unsigned slots
= type
->count_attribute_slots(false);
879 if (variable
->data
.compact
) {
880 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
881 slots
= (component_count
+ 3) / 4;
883 output_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
886 uint64_t input_mask
= 0;
887 nir_foreach_variable(variable
, &nir
->inputs
) {
888 const glsl_type
*type
= variable
->type
;
889 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
890 type
= type
->fields
.array
;
891 unsigned slots
= type
->count_attribute_slots(false);
892 if (variable
->data
.compact
) {
893 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
894 slots
= (component_count
+ 3) / 4;
896 input_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
899 ctx
->output_masks
[nir
->info
.stage
] |= output_mask
;
900 if (i
+ 1 < shader_count
)
901 ctx
->input_masks
[shaders
[i
+ 1]->info
.stage
] |= output_mask
;
903 ctx
->input_masks
[nir
->info
.stage
] |= input_mask
;
905 ctx
->output_masks
[shaders
[i
- 1]->info
.stage
] |= input_mask
;
910 setup_nir(isel_context
*ctx
, nir_shader
*nir
)
912 Program
*program
= ctx
->program
;
914 /* align and copy constant data */
915 while (program
->constant_data
.size() % 4u)
916 program
->constant_data
.push_back(0);
917 ctx
->constant_data_offset
= program
->constant_data
.size();
918 program
->constant_data
.insert(program
->constant_data
.end(),
919 (uint8_t*)nir
->constant_data
,
920 (uint8_t*)nir
->constant_data
+ nir
->constant_data_size
);
922 /* the variable setup has to be done before lower_io / CSE */
923 setup_variables(ctx
, nir
);
925 /* optimize and lower memory operations */
926 bool lower_to_scalar
= false;
927 bool lower_pack
= false;
928 if (nir_opt_load_store_vectorize(nir
,
929 (nir_variable_mode
)(nir_var_mem_ssbo
| nir_var_mem_ubo
|
930 nir_var_mem_push_const
| nir_var_mem_shared
),
931 mem_vectorize_callback
)) {
932 lower_to_scalar
= true;
935 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
936 nir_lower_io(nir
, (nir_variable_mode
)(nir_var_shader_in
| nir_var_shader_out
), type_size
, (nir_lower_io_options
)0);
937 nir_lower_explicit_io(nir
, nir_var_mem_global
, nir_address_format_64bit_global
);
940 nir_lower_alu_to_scalar(nir
, NULL
, NULL
);
944 /* lower ALU operations */
945 // TODO: implement logic64 in aco, it's more effective for sgprs
946 nir_lower_int64(nir
, nir
->options
->lower_int64_options
);
948 nir_opt_idiv_const(nir
, 32);
949 nir_lower_idiv(nir
, nir_lower_idiv_precise
);
951 /* optimize the lowered ALU operations */
952 bool more_algebraic
= true;
953 while (more_algebraic
) {
954 more_algebraic
= false;
955 NIR_PASS_V(nir
, nir_copy_prop
);
956 NIR_PASS_V(nir
, nir_opt_dce
);
957 NIR_PASS_V(nir
, nir_opt_constant_folding
);
958 NIR_PASS(more_algebraic
, nir
, nir_opt_algebraic
);
961 /* Do late algebraic optimization to turn add(a, neg(b)) back into
962 * subs, then the mandatory cleanup after algebraic. Note that it may
963 * produce fnegs, and if so then we need to keep running to squash
966 bool more_late_algebraic
= true;
967 while (more_late_algebraic
) {
968 more_late_algebraic
= false;
969 NIR_PASS(more_late_algebraic
, nir
, nir_opt_algebraic_late
);
970 NIR_PASS_V(nir
, nir_opt_constant_folding
);
971 NIR_PASS_V(nir
, nir_copy_prop
);
972 NIR_PASS_V(nir
, nir_opt_dce
);
973 NIR_PASS_V(nir
, nir_opt_cse
);
977 nir_lower_load_const_to_scalar(nir
);
978 nir_opt_shrink_load(nir
);
979 nir_move_options move_opts
= (nir_move_options
)(
980 nir_move_const_undef
| nir_move_load_ubo
| nir_move_load_input
|
981 nir_move_comparisons
| nir_move_copies
);
982 nir_opt_sink(nir
, move_opts
);
983 nir_opt_move(nir
, move_opts
);
984 nir_convert_to_lcssa(nir
, true, false);
985 nir_lower_phis_to_scalar(nir
);
987 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
988 nir_index_ssa_defs(func
);
989 nir_metadata_require(func
, nir_metadata_block_index
);
993 setup_isel_context(Program
* program
,
994 unsigned shader_count
,
995 struct nir_shader
*const *shaders
,
996 ac_shader_config
* config
,
997 struct radv_shader_args
*args
,
998 bool is_gs_copy_shader
)
1001 for (unsigned i
= 0; i
< shader_count
; i
++) {
1002 switch (shaders
[i
]->info
.stage
) {
1003 case MESA_SHADER_VERTEX
:
1004 program
->stage
|= sw_vs
;
1006 case MESA_SHADER_TESS_CTRL
:
1007 program
->stage
|= sw_tcs
;
1009 case MESA_SHADER_TESS_EVAL
:
1010 program
->stage
|= sw_tes
;
1012 case MESA_SHADER_GEOMETRY
:
1013 program
->stage
|= is_gs_copy_shader
? sw_gs_copy
: sw_gs
;
1015 case MESA_SHADER_FRAGMENT
:
1016 program
->stage
|= sw_fs
;
1018 case MESA_SHADER_COMPUTE
:
1019 program
->stage
|= sw_cs
;
1022 unreachable("Shader stage not implemented");
1025 bool gfx9_plus
= args
->options
->chip_class
>= GFX9
;
1026 bool ngg
= args
->shader_info
->is_ngg
&& args
->options
->chip_class
>= GFX10
;
1027 if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_es
)
1028 program
->stage
|= hw_es
;
1029 else if (program
->stage
== sw_vs
&& !args
->shader_info
->vs
.as_ls
)
1030 program
->stage
|= hw_vs
;
1031 else if (program
->stage
== sw_gs
)
1032 program
->stage
|= hw_gs
;
1033 else if (program
->stage
== sw_fs
)
1034 program
->stage
|= hw_fs
;
1035 else if (program
->stage
== sw_cs
)
1036 program
->stage
|= hw_cs
;
1037 else if (program
->stage
== sw_gs_copy
)
1038 program
->stage
|= hw_vs
;
1039 else if (program
->stage
== (sw_vs
| sw_gs
) && gfx9_plus
&& !ngg
)
1040 program
->stage
|= hw_gs
;
1041 else if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_ls
)
1042 program
->stage
|= hw_ls
; /* GFX6-8: VS is a Local Shader, when tessellation is used */
1043 else if (program
->stage
== sw_tcs
)
1044 program
->stage
|= hw_hs
; /* GFX6-8: TCS is a Hull Shader */
1045 else if (program
->stage
== (sw_vs
| sw_tcs
))
1046 program
->stage
|= hw_hs
; /* GFX9-10: VS+TCS merged into a Hull Shader */
1047 else if (program
->stage
== sw_tes
&& !args
->shader_info
->tes
.as_es
&& !ngg
)
1048 program
->stage
|= hw_vs
; /* GFX6-9: TES without GS uses the HW VS stage (and GFX10/legacy) */
1049 else if (program
->stage
== sw_tes
&& args
->shader_info
->tes
.as_es
&& !ngg
)
1050 program
->stage
|= hw_es
; /* GFX6-8: TES is an Export Shader */
1051 else if (program
->stage
== (sw_tes
| sw_gs
) && gfx9_plus
&& !ngg
)
1052 program
->stage
|= hw_gs
; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */
1054 unreachable("Shader stage not implemented");
1056 program
->config
= config
;
1057 program
->info
= args
->shader_info
;
1058 program
->chip_class
= args
->options
->chip_class
;
1059 program
->family
= args
->options
->family
;
1060 program
->wave_size
= args
->shader_info
->wave_size
;
1061 program
->lane_mask
= program
->wave_size
== 32 ? s1
: s2
;
1063 program
->lds_alloc_granule
= args
->options
->chip_class
>= GFX7
? 512 : 256;
1064 program
->lds_limit
= args
->options
->chip_class
>= GFX7
? 65536 : 32768;
1065 program
->vgpr_limit
= 256;
1066 program
->vgpr_alloc_granule
= 3;
1068 if (args
->options
->chip_class
>= GFX10
) {
1069 program
->physical_sgprs
= 2560; /* doesn't matter as long as it's at least 128 * 20 */
1070 program
->sgpr_alloc_granule
= 127;
1071 program
->sgpr_limit
= 106;
1072 program
->vgpr_alloc_granule
= program
->wave_size
== 32 ? 7 : 3;
1073 } else if (program
->chip_class
>= GFX8
) {
1074 program
->physical_sgprs
= 800;
1075 program
->sgpr_alloc_granule
= 15;
1076 if (args
->options
->family
== CHIP_TONGA
|| args
->options
->family
== CHIP_ICELAND
)
1077 program
->sgpr_limit
= 94; /* workaround hardware bug */
1079 program
->sgpr_limit
= 102;
1081 program
->physical_sgprs
= 512;
1082 program
->sgpr_alloc_granule
= 7;
1083 program
->sgpr_limit
= 104;
1086 calc_min_waves(program
);
1087 program
->vgpr_limit
= get_addr_vgpr_from_waves(program
, program
->min_waves
);
1088 program
->sgpr_limit
= get_addr_sgpr_from_waves(program
, program
->min_waves
);
1090 isel_context ctx
= {};
1091 ctx
.program
= program
;
1093 ctx
.options
= args
->options
;
1094 ctx
.stage
= program
->stage
;
1096 get_io_masks(&ctx
, shader_count
, shaders
);
1098 unsigned scratch_size
= 0;
1099 if (program
->stage
== gs_copy_vs
) {
1100 assert(shader_count
== 1);
1101 setup_vs_output_info(&ctx
, shaders
[0], false, true, &args
->shader_info
->vs
.outinfo
);
1103 for (unsigned i
= 0; i
< shader_count
; i
++) {
1104 nir_shader
*nir
= shaders
[i
];
1105 setup_nir(&ctx
, nir
);
1107 if (args
->options
->dump_preoptir
) {
1108 fprintf(stderr
, "NIR shader before instruction selection:\n");
1109 nir_print_shader(nir
, stderr
);
1113 for (unsigned i
= 0; i
< shader_count
; i
++)
1114 scratch_size
= std::max(scratch_size
, shaders
[i
]->scratch_size
);
1117 ctx
.program
->config
->scratch_bytes_per_wave
= align(scratch_size
* ctx
.program
->wave_size
, 1024);
1119 ctx
.block
= ctx
.program
->create_and_insert_block();
1120 ctx
.block
->loop_nest_depth
= 0;
1121 ctx
.block
->kind
= block_kind_top_level
;