2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <unordered_map>
29 #include "nir_control_flow.h"
30 #include "vulkan/radv_shader.h"
31 #include "vulkan/radv_descriptor_set.h"
32 #include "vulkan/radv_shader_args.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
37 #include "util/u_math.h"
39 #define MAX_INLINE_PUSH_CONSTS 8
43 struct shader_io_state
{
44 uint8_t mask
[VARYING_SLOT_MAX
];
45 Temp temps
[VARYING_SLOT_MAX
* 4u];
48 memset(mask
, 0, sizeof(mask
));
49 std::fill_n(temps
, VARYING_SLOT_MAX
* 4u, Temp(0, RegClass::v1
));
54 const struct radv_nir_compiler_options
*options
;
55 struct radv_shader_args
*args
;
58 uint32_t constant_data_offset
;
60 std::unique_ptr
<Temp
[]> allocated
;
61 std::unordered_map
<unsigned, std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
>> allocated_vec
;
62 Stage stage
; /* Stage */
63 bool has_gfx10_wave64_bpermute
= false;
66 uint16_t loop_nest_depth
= 0;
70 bool has_divergent_continue
= false;
71 bool has_divergent_branch
= false;
74 bool is_divergent
= false;
76 bool exec_potentially_empty_discard
= false; /* set to false when loop_nest_depth==0 && parent_if.is_divergent==false */
77 uint16_t exec_potentially_empty_break_depth
= UINT16_MAX
;
78 /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth
79 * and parent_if.is_divergent==false. Called _break but it's also used for
81 bool exec_potentially_empty_break
= false;
82 std::unique_ptr
<unsigned[]> nir_to_aco
; /* NIR block index to ACO block index */
85 Temp arg_temps
[AC_MAX_ARGS
];
88 Temp persp_centroid
, linear_centroid
;
93 /* VS output information */
94 bool export_clip_dists
;
95 unsigned num_clip_distances
;
96 unsigned num_cull_distances
;
98 /* tessellation information */
99 unsigned tcs_tess_lvl_out_loc
;
100 unsigned tcs_tess_lvl_in_loc
;
101 uint64_t tcs_temp_only_inputs
;
102 uint32_t tcs_num_inputs
;
103 uint32_t tcs_num_outputs
;
104 uint32_t tcs_num_patch_outputs
;
105 uint32_t tcs_num_patches
;
106 bool tcs_in_out_eq
= false;
108 /* I/O information */
109 shader_io_state inputs
;
110 shader_io_state outputs
;
111 uint8_t output_drv_loc_to_var_slot
[MESA_SHADER_COMPUTE
][VARYING_SLOT_MAX
];
112 uint8_t output_tcs_patch_drv_loc_to_var_slot
[VARYING_SLOT_MAX
];
115 Temp
get_arg(isel_context
*ctx
, struct ac_arg arg
)
118 return ctx
->arg_temps
[arg
.arg_index
];
121 unsigned get_interp_input(nir_intrinsic_op intrin
, enum glsl_interp_mode interp
)
124 case INTERP_MODE_SMOOTH
:
125 case INTERP_MODE_NONE
:
126 if (intrin
== nir_intrinsic_load_barycentric_pixel
||
127 intrin
== nir_intrinsic_load_barycentric_at_sample
||
128 intrin
== nir_intrinsic_load_barycentric_at_offset
)
129 return S_0286CC_PERSP_CENTER_ENA(1);
130 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
131 return S_0286CC_PERSP_CENTROID_ENA(1);
132 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
133 return S_0286CC_PERSP_SAMPLE_ENA(1);
135 case INTERP_MODE_NOPERSPECTIVE
:
136 if (intrin
== nir_intrinsic_load_barycentric_pixel
)
137 return S_0286CC_LINEAR_CENTER_ENA(1);
138 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
139 return S_0286CC_LINEAR_CENTROID_ENA(1);
140 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
141 return S_0286CC_LINEAR_SAMPLE_ENA(1);
149 /* If one side of a divergent IF ends in a branch and the other doesn't, we
150 * might have to emit the contents of the side without the branch at the merge
151 * block instead. This is so that we can use any SGPR live-out of the side
152 * without the branch without creating a linear phi in the invert or merge block. */
154 sanitize_if(nir_function_impl
*impl
, nir_if
*nif
)
156 //TODO: skip this if the condition is uniform and there are no divergent breaks/continues?
158 nir_block
*then_block
= nir_if_last_then_block(nif
);
159 nir_block
*else_block
= nir_if_last_else_block(nif
);
160 bool then_jump
= nir_block_ends_in_jump(then_block
) || nir_block_is_unreachable(then_block
);
161 bool else_jump
= nir_block_ends_in_jump(else_block
) || nir_block_is_unreachable(else_block
);
162 if (then_jump
== else_jump
)
165 /* If the continue from block is empty then return as there is nothing to
168 if (nir_cf_list_is_empty_block(else_jump
? &nif
->then_list
: &nif
->else_list
))
171 /* Even though this if statement has a jump on one side, we may still have
172 * phis afterwards. Single-source phis can be produced by loop unrolling
173 * or dead control-flow passes and are perfectly legal. Run a quick phi
174 * removal on the block after the if to clean up any such phis.
176 nir_opt_remove_phis_block(nir_cf_node_as_block(nir_cf_node_next(&nif
->cf_node
)));
178 /* Finally, move the continue from branch after the if-statement. */
179 nir_block
*last_continue_from_blk
= else_jump
? then_block
: else_block
;
180 nir_block
*first_continue_from_blk
= else_jump
?
181 nir_if_first_then_block(nif
) : nir_if_first_else_block(nif
);
184 nir_cf_extract(&tmp
, nir_before_block(first_continue_from_blk
),
185 nir_after_block(last_continue_from_blk
));
186 nir_cf_reinsert(&tmp
, nir_after_cf_node(&nif
->cf_node
));
188 /* nir_cf_extract() invalidates dominance metadata, but it should still be
189 * correct because of the specific type of transformation we did. Block
190 * indices are not valid except for block_0's, which is all we care about for
191 * nir_block_is_unreachable(). */
192 impl
->valid_metadata
=
193 (nir_metadata
)(impl
->valid_metadata
| nir_metadata_dominance
| nir_metadata_block_index
);
199 sanitize_cf_list(nir_function_impl
*impl
, struct exec_list
*cf_list
)
201 bool progress
= false;
202 foreach_list_typed(nir_cf_node
, cf_node
, node
, cf_list
) {
203 switch (cf_node
->type
) {
204 case nir_cf_node_block
:
206 case nir_cf_node_if
: {
207 nir_if
*nif
= nir_cf_node_as_if(cf_node
);
208 progress
|= sanitize_cf_list(impl
, &nif
->then_list
);
209 progress
|= sanitize_cf_list(impl
, &nif
->else_list
);
210 progress
|= sanitize_if(impl
, nif
);
213 case nir_cf_node_loop
: {
214 nir_loop
*loop
= nir_cf_node_as_loop(cf_node
);
215 progress
|= sanitize_cf_list(impl
, &loop
->body
);
218 case nir_cf_node_function
:
219 unreachable("Invalid cf type");
226 RegClass
get_reg_class(isel_context
*ctx
, RegType type
, unsigned components
, unsigned bitsize
)
229 return RegClass(RegType::sgpr
, ctx
->program
->lane_mask
.size() * components
);
231 return RegClass::get(type
, components
* bitsize
/ 8u);
234 void init_context(isel_context
*ctx
, nir_shader
*shader
)
236 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
237 unsigned lane_mask_size
= ctx
->program
->lane_mask
.size();
239 ctx
->shader
= shader
;
240 nir_divergence_analysis(shader
, nir_divergence_view_index_uniform
);
242 /* sanitize control flow */
243 nir_metadata_require(impl
, nir_metadata_dominance
);
244 sanitize_cf_list(impl
, &impl
->body
);
245 nir_metadata_preserve(impl
, (nir_metadata
)~nir_metadata_block_index
);
247 /* we'll need this for isel */
248 nir_metadata_require(impl
, nir_metadata_block_index
);
250 if (!(ctx
->stage
& sw_gs_copy
) && ctx
->options
->dump_preoptir
) {
251 fprintf(stderr
, "NIR shader before instruction selection:\n");
252 nir_print_shader(shader
, stderr
);
255 std::unique_ptr
<Temp
[]> allocated
{new Temp
[impl
->ssa_alloc
]()};
257 unsigned spi_ps_inputs
= 0;
259 std::unique_ptr
<unsigned[]> nir_to_aco
{new unsigned[impl
->num_blocks
]()};
264 nir_foreach_block(block
, impl
) {
265 nir_foreach_instr(instr
, block
) {
266 switch(instr
->type
) {
267 case nir_instr_type_alu
: {
268 nir_alu_instr
*alu_instr
= nir_instr_as_alu(instr
);
269 RegType type
= RegType::sgpr
;
270 switch(alu_instr
->op
) {
292 case nir_op_fround_even
:
296 case nir_op_f2f16_rtz
:
297 case nir_op_f2f16_rtne
:
306 case nir_op_pack_half_2x16
:
307 case nir_op_unpack_half_2x16_split_x
:
308 case nir_op_unpack_half_2x16_split_y
:
311 case nir_op_fddx_fine
:
312 case nir_op_fddy_fine
:
313 case nir_op_fddx_coarse
:
314 case nir_op_fddy_coarse
:
315 case nir_op_fquantize2f16
:
317 case nir_op_frexp_sig
:
318 case nir_op_frexp_exp
:
319 case nir_op_cube_face_index
:
320 case nir_op_cube_face_coord
:
321 type
= RegType::vgpr
;
334 type
= nir_dest_is_divergent(alu_instr
->dest
.dest
) ? RegType::vgpr
: RegType::sgpr
;
337 type
= nir_dest_is_divergent(alu_instr
->dest
.dest
) ? RegType::vgpr
: RegType::sgpr
;
340 for (unsigned i
= 0; i
< nir_op_infos
[alu_instr
->op
].num_inputs
; i
++) {
341 if (allocated
[alu_instr
->src
[i
].src
.ssa
->index
].type() == RegType::vgpr
)
342 type
= RegType::vgpr
;
347 RegClass rc
= get_reg_class(ctx
, type
, alu_instr
->dest
.dest
.ssa
.num_components
, alu_instr
->dest
.dest
.ssa
.bit_size
);
348 allocated
[alu_instr
->dest
.dest
.ssa
.index
] = Temp(0, rc
);
351 case nir_instr_type_load_const
: {
352 unsigned num_components
= nir_instr_as_load_const(instr
)->def
.num_components
;
353 unsigned bit_size
= nir_instr_as_load_const(instr
)->def
.bit_size
;
354 RegClass rc
= get_reg_class(ctx
, RegType::sgpr
, num_components
, bit_size
);
355 allocated
[nir_instr_as_load_const(instr
)->def
.index
] = Temp(0, rc
);
358 case nir_instr_type_intrinsic
: {
359 nir_intrinsic_instr
*intrinsic
= nir_instr_as_intrinsic(instr
);
360 if (!nir_intrinsic_infos
[intrinsic
->intrinsic
].has_dest
)
362 RegType type
= RegType::sgpr
;
363 switch(intrinsic
->intrinsic
) {
364 case nir_intrinsic_load_push_constant
:
365 case nir_intrinsic_load_work_group_id
:
366 case nir_intrinsic_load_num_work_groups
:
367 case nir_intrinsic_load_subgroup_id
:
368 case nir_intrinsic_load_num_subgroups
:
369 case nir_intrinsic_load_first_vertex
:
370 case nir_intrinsic_load_base_instance
:
371 case nir_intrinsic_get_buffer_size
:
372 case nir_intrinsic_vote_all
:
373 case nir_intrinsic_vote_any
:
374 case nir_intrinsic_read_first_invocation
:
375 case nir_intrinsic_read_invocation
:
376 case nir_intrinsic_first_invocation
:
377 case nir_intrinsic_ballot
:
378 type
= RegType::sgpr
;
380 case nir_intrinsic_load_sample_id
:
381 case nir_intrinsic_load_sample_mask_in
:
382 case nir_intrinsic_load_input
:
383 case nir_intrinsic_load_output
:
384 case nir_intrinsic_load_input_vertex
:
385 case nir_intrinsic_load_per_vertex_input
:
386 case nir_intrinsic_load_per_vertex_output
:
387 case nir_intrinsic_load_vertex_id
:
388 case nir_intrinsic_load_vertex_id_zero_base
:
389 case nir_intrinsic_load_barycentric_sample
:
390 case nir_intrinsic_load_barycentric_pixel
:
391 case nir_intrinsic_load_barycentric_model
:
392 case nir_intrinsic_load_barycentric_centroid
:
393 case nir_intrinsic_load_barycentric_at_sample
:
394 case nir_intrinsic_load_barycentric_at_offset
:
395 case nir_intrinsic_load_interpolated_input
:
396 case nir_intrinsic_load_frag_coord
:
397 case nir_intrinsic_load_sample_pos
:
398 case nir_intrinsic_load_layer_id
:
399 case nir_intrinsic_load_local_invocation_id
:
400 case nir_intrinsic_load_local_invocation_index
:
401 case nir_intrinsic_load_subgroup_invocation
:
402 case nir_intrinsic_load_tess_coord
:
403 case nir_intrinsic_write_invocation_amd
:
404 case nir_intrinsic_mbcnt_amd
:
405 case nir_intrinsic_load_instance_id
:
406 case nir_intrinsic_ssbo_atomic_add
:
407 case nir_intrinsic_ssbo_atomic_imin
:
408 case nir_intrinsic_ssbo_atomic_umin
:
409 case nir_intrinsic_ssbo_atomic_imax
:
410 case nir_intrinsic_ssbo_atomic_umax
:
411 case nir_intrinsic_ssbo_atomic_and
:
412 case nir_intrinsic_ssbo_atomic_or
:
413 case nir_intrinsic_ssbo_atomic_xor
:
414 case nir_intrinsic_ssbo_atomic_exchange
:
415 case nir_intrinsic_ssbo_atomic_comp_swap
:
416 case nir_intrinsic_global_atomic_add
:
417 case nir_intrinsic_global_atomic_imin
:
418 case nir_intrinsic_global_atomic_umin
:
419 case nir_intrinsic_global_atomic_imax
:
420 case nir_intrinsic_global_atomic_umax
:
421 case nir_intrinsic_global_atomic_and
:
422 case nir_intrinsic_global_atomic_or
:
423 case nir_intrinsic_global_atomic_xor
:
424 case nir_intrinsic_global_atomic_exchange
:
425 case nir_intrinsic_global_atomic_comp_swap
:
426 case nir_intrinsic_image_deref_atomic_add
:
427 case nir_intrinsic_image_deref_atomic_umin
:
428 case nir_intrinsic_image_deref_atomic_imin
:
429 case nir_intrinsic_image_deref_atomic_umax
:
430 case nir_intrinsic_image_deref_atomic_imax
:
431 case nir_intrinsic_image_deref_atomic_and
:
432 case nir_intrinsic_image_deref_atomic_or
:
433 case nir_intrinsic_image_deref_atomic_xor
:
434 case nir_intrinsic_image_deref_atomic_exchange
:
435 case nir_intrinsic_image_deref_atomic_comp_swap
:
436 case nir_intrinsic_image_deref_size
:
437 case nir_intrinsic_shared_atomic_add
:
438 case nir_intrinsic_shared_atomic_imin
:
439 case nir_intrinsic_shared_atomic_umin
:
440 case nir_intrinsic_shared_atomic_imax
:
441 case nir_intrinsic_shared_atomic_umax
:
442 case nir_intrinsic_shared_atomic_and
:
443 case nir_intrinsic_shared_atomic_or
:
444 case nir_intrinsic_shared_atomic_xor
:
445 case nir_intrinsic_shared_atomic_exchange
:
446 case nir_intrinsic_shared_atomic_comp_swap
:
447 case nir_intrinsic_load_scratch
:
448 case nir_intrinsic_load_invocation_id
:
449 case nir_intrinsic_load_primitive_id
:
450 type
= RegType::vgpr
;
452 case nir_intrinsic_shuffle
:
453 case nir_intrinsic_quad_broadcast
:
454 case nir_intrinsic_quad_swap_horizontal
:
455 case nir_intrinsic_quad_swap_vertical
:
456 case nir_intrinsic_quad_swap_diagonal
:
457 case nir_intrinsic_quad_swizzle_amd
:
458 case nir_intrinsic_masked_swizzle_amd
:
459 case nir_intrinsic_inclusive_scan
:
460 case nir_intrinsic_exclusive_scan
:
461 case nir_intrinsic_reduce
:
462 case nir_intrinsic_load_ubo
:
463 case nir_intrinsic_load_ssbo
:
464 case nir_intrinsic_load_global
:
465 case nir_intrinsic_vulkan_resource_index
:
466 case nir_intrinsic_load_shared
:
467 type
= nir_dest_is_divergent(intrinsic
->dest
) ? RegType::vgpr
: RegType::sgpr
;
469 case nir_intrinsic_load_view_index
:
470 type
= ctx
->stage
== fragment_fs
? RegType::vgpr
: RegType::sgpr
;
473 for (unsigned i
= 0; i
< nir_intrinsic_infos
[intrinsic
->intrinsic
].num_srcs
; i
++) {
474 if (allocated
[intrinsic
->src
[i
].ssa
->index
].type() == RegType::vgpr
)
475 type
= RegType::vgpr
;
479 RegClass rc
= get_reg_class(ctx
, type
, intrinsic
->dest
.ssa
.num_components
, intrinsic
->dest
.ssa
.bit_size
);
480 allocated
[intrinsic
->dest
.ssa
.index
] = Temp(0, rc
);
482 switch(intrinsic
->intrinsic
) {
483 case nir_intrinsic_load_barycentric_sample
:
484 case nir_intrinsic_load_barycentric_pixel
:
485 case nir_intrinsic_load_barycentric_centroid
:
486 case nir_intrinsic_load_barycentric_at_sample
:
487 case nir_intrinsic_load_barycentric_at_offset
: {
488 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(intrinsic
);
489 spi_ps_inputs
|= get_interp_input(intrinsic
->intrinsic
, mode
);
492 case nir_intrinsic_load_barycentric_model
:
493 spi_ps_inputs
|= S_0286CC_PERSP_PULL_MODEL_ENA(1);
495 case nir_intrinsic_load_front_face
:
496 spi_ps_inputs
|= S_0286CC_FRONT_FACE_ENA(1);
498 case nir_intrinsic_load_frag_coord
:
499 case nir_intrinsic_load_sample_pos
: {
500 uint8_t mask
= nir_ssa_def_components_read(&intrinsic
->dest
.ssa
);
501 for (unsigned i
= 0; i
< 4; i
++) {
503 spi_ps_inputs
|= S_0286CC_POS_X_FLOAT_ENA(1) << i
;
508 case nir_intrinsic_load_sample_id
:
509 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
511 case nir_intrinsic_load_sample_mask_in
:
512 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
513 spi_ps_inputs
|= S_0286CC_SAMPLE_COVERAGE_ENA(1);
520 case nir_instr_type_tex
: {
521 nir_tex_instr
* tex
= nir_instr_as_tex(instr
);
522 unsigned size
= tex
->dest
.ssa
.num_components
;
524 if (tex
->dest
.ssa
.bit_size
== 64)
526 if (tex
->op
== nir_texop_texture_samples
) {
527 assert(!tex
->dest
.ssa
.divergent
);
529 if (nir_dest_is_divergent(tex
->dest
))
530 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::vgpr
, size
));
532 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
535 case nir_instr_type_parallel_copy
: {
536 nir_foreach_parallel_copy_entry(entry
, nir_instr_as_parallel_copy(instr
)) {
537 allocated
[entry
->dest
.ssa
.index
] = allocated
[entry
->src
.ssa
->index
];
541 case nir_instr_type_ssa_undef
: {
542 unsigned num_components
= nir_instr_as_ssa_undef(instr
)->def
.num_components
;
543 unsigned bit_size
= nir_instr_as_ssa_undef(instr
)->def
.bit_size
;
544 RegClass rc
= get_reg_class(ctx
, RegType::sgpr
, num_components
, bit_size
);
545 allocated
[nir_instr_as_ssa_undef(instr
)->def
.index
] = Temp(0, rc
);
548 case nir_instr_type_phi
: {
549 nir_phi_instr
* phi
= nir_instr_as_phi(instr
);
551 unsigned size
= phi
->dest
.ssa
.num_components
;
553 if (phi
->dest
.ssa
.bit_size
== 1) {
554 assert(size
== 1 && "multiple components not yet supported on boolean phis.");
555 type
= RegType::sgpr
;
556 size
*= lane_mask_size
;
557 allocated
[phi
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
561 if (nir_dest_is_divergent(phi
->dest
)) {
562 type
= RegType::vgpr
;
564 type
= RegType::sgpr
;
565 nir_foreach_phi_src (src
, phi
) {
566 if (allocated
[src
->src
.ssa
->index
].type() == RegType::vgpr
)
567 type
= RegType::vgpr
;
568 if (allocated
[src
->src
.ssa
->index
].type() == RegType::none
)
573 RegClass rc
= get_reg_class(ctx
, type
, phi
->dest
.ssa
.num_components
, phi
->dest
.ssa
.bit_size
);
574 if (rc
!= allocated
[phi
->dest
.ssa
.index
].regClass()) {
577 nir_foreach_phi_src(src
, phi
)
578 assert(allocated
[src
->src
.ssa
->index
].size() == rc
.size());
580 allocated
[phi
->dest
.ssa
.index
] = Temp(0, rc
);
590 if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_inputs
)) {
591 /* If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be enabled too */
592 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
595 if (!(spi_ps_inputs
& 0x7F)) {
596 /* At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled */
597 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
600 ctx
->program
->config
->spi_ps_input_ena
= spi_ps_inputs
;
601 ctx
->program
->config
->spi_ps_input_addr
= spi_ps_inputs
;
603 for (unsigned i
= 0; i
< impl
->ssa_alloc
; i
++)
604 allocated
[i
] = Temp(ctx
->program
->allocateId(), allocated
[i
].regClass());
606 ctx
->allocated
.reset(allocated
.release());
607 ctx
->cf_info
.nir_to_aco
.reset(nir_to_aco
.release());
610 Pseudo_instruction
*add_startpgm(struct isel_context
*ctx
)
612 unsigned arg_count
= ctx
->args
->ac
.arg_count
;
613 if (ctx
->stage
== fragment_fs
) {
614 /* LLVM optimizes away unused FS inputs and computes spi_ps_input_addr
615 * itself and then communicates the results back via the ELF binary.
616 * Mirror what LLVM does by re-mapping the VGPR arguments here.
618 * TODO: If we made the FS input scanning code into a separate pass that
619 * could run before argument setup, then this wouldn't be necessary
622 struct ac_shader_args
*args
= &ctx
->args
->ac
;
624 for (unsigned i
= 0, vgpr_arg
= 0, vgpr_reg
= 0; i
< args
->arg_count
; i
++) {
625 if (args
->args
[i
].file
!= AC_ARG_VGPR
) {
630 if (!(ctx
->program
->config
->spi_ps_input_addr
& (1 << vgpr_arg
))) {
631 args
->args
[i
].skip
= true;
633 args
->args
[i
].offset
= vgpr_reg
;
634 vgpr_reg
+= args
->args
[i
].size
;
641 aco_ptr
<Pseudo_instruction
> startpgm
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_startpgm
, Format::PSEUDO
, 0, arg_count
+ 1)};
642 for (unsigned i
= 0, arg
= 0; i
< ctx
->args
->ac
.arg_count
; i
++) {
643 if (ctx
->args
->ac
.args
[i
].skip
)
646 enum ac_arg_regfile file
= ctx
->args
->ac
.args
[i
].file
;
647 unsigned size
= ctx
->args
->ac
.args
[i
].size
;
648 unsigned reg
= ctx
->args
->ac
.args
[i
].offset
;
649 RegClass type
= RegClass(file
== AC_ARG_SGPR
? RegType::sgpr
: RegType::vgpr
, size
);
650 Temp dst
= Temp
{ctx
->program
->allocateId(), type
};
651 ctx
->arg_temps
[i
] = dst
;
652 startpgm
->definitions
[arg
] = Definition(dst
);
653 startpgm
->definitions
[arg
].setFixed(PhysReg
{file
== AC_ARG_SGPR
? reg
: reg
+ 256});
656 startpgm
->definitions
[arg_count
] = Definition
{ctx
->program
->allocateId(), exec
, ctx
->program
->lane_mask
};
657 Pseudo_instruction
*instr
= startpgm
.get();
658 ctx
->block
->instructions
.push_back(std::move(startpgm
));
660 /* Stash these in the program so that they can be accessed later when
663 ctx
->program
->private_segment_buffer
= get_arg(ctx
, ctx
->args
->ring_offsets
);
664 ctx
->program
->scratch_offset
= get_arg(ctx
, ctx
->args
->scratch_offset
);
670 type_size(const struct glsl_type
*type
, bool bindless
)
672 // TODO: don't we need type->std430_base_alignment() here?
673 return glsl_count_attribute_slots(type
, false);
677 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
679 assert(glsl_type_is_vector_or_scalar(type
));
681 uint32_t comp_size
= glsl_type_is_boolean(type
)
682 ? 4 : glsl_get_bit_size(type
) / 8;
683 unsigned length
= glsl_get_vector_elements(type
);
684 *size
= comp_size
* length
,
689 mem_vectorize_callback(unsigned align
, unsigned bit_size
,
690 unsigned num_components
, unsigned high_offset
,
691 nir_intrinsic_instr
*low
, nir_intrinsic_instr
*high
)
693 if ((bit_size
!= 32 && bit_size
!= 64) || num_components
> 4)
696 /* >128 bit loads are split except with SMEM */
697 if (bit_size
* num_components
> 128)
700 switch (low
->intrinsic
) {
701 case nir_intrinsic_load_global
:
702 case nir_intrinsic_store_global
:
703 return align
% 4 == 0;
704 case nir_intrinsic_store_ssbo
:
705 if (low
->src
[0].ssa
->bit_size
< 32 || high
->src
[0].ssa
->bit_size
< 32)
707 return align
% 4 == 0;
708 case nir_intrinsic_load_ssbo
:
709 if (low
->dest
.ssa
.bit_size
< 32 || high
->dest
.ssa
.bit_size
< 32)
711 case nir_intrinsic_load_ubo
:
712 case nir_intrinsic_load_push_constant
:
713 return align
% 4 == 0;
714 case nir_intrinsic_load_deref
:
715 case nir_intrinsic_store_deref
:
716 assert(nir_src_as_deref(low
->src
[0])->mode
== nir_var_mem_shared
);
718 case nir_intrinsic_load_shared
:
719 case nir_intrinsic_store_shared
:
720 if (bit_size
* num_components
> 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
721 return align
% 16 == 0;
723 return align
% 4 == 0;
731 setup_vs_output_info(isel_context
*ctx
, nir_shader
*nir
,
732 bool export_prim_id
, bool export_clip_dists
,
733 radv_vs_output_info
*outinfo
)
735 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
736 sizeof(outinfo
->vs_output_param_offset
));
738 outinfo
->param_exports
= 0;
739 int pos_written
= 0x1;
740 if (outinfo
->writes_pointsize
|| outinfo
->writes_viewport_index
|| outinfo
->writes_layer
)
741 pos_written
|= 1 << 1;
743 uint64_t mask
= nir
->info
.outputs_written
;
745 int idx
= u_bit_scan64(&mask
);
746 if (idx
>= VARYING_SLOT_VAR0
|| idx
== VARYING_SLOT_LAYER
||
747 idx
== VARYING_SLOT_PRIMITIVE_ID
|| idx
== VARYING_SLOT_VIEWPORT
||
748 ((idx
== VARYING_SLOT_CLIP_DIST0
|| idx
== VARYING_SLOT_CLIP_DIST1
) && export_clip_dists
)) {
749 if (outinfo
->vs_output_param_offset
[idx
] == AC_EXP_PARAM_UNDEFINED
)
750 outinfo
->vs_output_param_offset
[idx
] = outinfo
->param_exports
++;
753 if (outinfo
->writes_layer
&&
754 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] == AC_EXP_PARAM_UNDEFINED
) {
755 /* when ctx->options->key.has_multiview_view_index = true, the layer
756 * variable isn't declared in NIR and it's isel's job to get the layer */
757 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = outinfo
->param_exports
++;
760 if (export_prim_id
) {
761 assert(outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] == AC_EXP_PARAM_UNDEFINED
);
762 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = outinfo
->param_exports
++;
765 ctx
->export_clip_dists
= export_clip_dists
;
766 ctx
->num_clip_distances
= util_bitcount(outinfo
->clip_dist_mask
);
767 ctx
->num_cull_distances
= util_bitcount(outinfo
->cull_dist_mask
);
769 assert(ctx
->num_clip_distances
+ ctx
->num_cull_distances
<= 8);
771 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
772 pos_written
|= 1 << 2;
773 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
774 pos_written
|= 1 << 3;
776 outinfo
->pos_exports
= util_bitcount(pos_written
);
780 setup_vs_variables(isel_context
*ctx
, nir_shader
*nir
)
782 nir_foreach_variable(variable
, &nir
->inputs
)
784 variable
->data
.driver_location
= variable
->data
.location
* 4;
786 nir_foreach_variable(variable
, &nir
->outputs
)
788 if (ctx
->stage
== vertex_vs
|| ctx
->stage
== ngg_vertex_gs
)
789 variable
->data
.driver_location
= variable
->data
.location
* 4;
791 assert(variable
->data
.location
>= 0 && variable
->data
.location
<= UINT8_MAX
);
792 ctx
->output_drv_loc_to_var_slot
[MESA_SHADER_VERTEX
][variable
->data
.driver_location
/ 4] = variable
->data
.location
;
795 if (ctx
->stage
== vertex_vs
|| ctx
->stage
== ngg_vertex_gs
) {
796 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
797 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
798 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
799 } else if (ctx
->stage
== vertex_ls
) {
800 ctx
->tcs_num_inputs
= ctx
->program
->info
->vs
.num_linked_outputs
;
803 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
804 /* We need to store the primitive IDs in LDS */
805 unsigned lds_size
= ctx
->program
->info
->ngg_info
.esgs_ring_size
;
806 ctx
->program
->config
->lds_size
= (lds_size
+ ctx
->program
->lds_alloc_granule
- 1) /
807 ctx
->program
->lds_alloc_granule
;
811 void setup_gs_variables(isel_context
*ctx
, nir_shader
*nir
)
813 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
814 ctx
->program
->config
->lds_size
= ctx
->program
->info
->gs_ring_info
.lds_size
; /* Already in units of the alloc granularity */
816 nir_foreach_variable(variable
, &nir
->outputs
) {
817 variable
->data
.driver_location
= variable
->data
.location
* 4;
820 if (ctx
->stage
== vertex_geometry_gs
)
821 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_VERTEX
;
822 else if (ctx
->stage
== tess_eval_geometry_gs
)
823 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_TESS_EVAL
;
827 setup_tcs_info(isel_context
*ctx
, nir_shader
*nir
)
829 /* When the number of TCS input and output vertices are the same (typically 3):
830 * - There is an equal amount of LS and HS invocations
831 * - In case of merged LSHS shaders, the LS and HS halves of the shader
832 * always process the exact same vertex. We can use this knowledge to optimize them.
835 ctx
->stage
== vertex_tess_control_hs
&&
836 ctx
->args
->options
->key
.tcs
.input_vertices
== nir
->info
.tess
.tcs_vertices_out
;
838 if (ctx
->tcs_in_out_eq
) {
839 ctx
->tcs_temp_only_inputs
= ~nir
->info
.tess
.tcs_cross_invocation_inputs_read
&
840 ~nir
->info
.inputs_read_indirectly
&
841 nir
->info
.inputs_read
;
844 ctx
->tcs_num_inputs
= ctx
->program
->info
->tcs
.num_linked_inputs
;
845 ctx
->tcs_num_outputs
= ctx
->program
->info
->tcs
.num_linked_outputs
;
846 ctx
->tcs_num_patch_outputs
= ctx
->program
->info
->tcs
.num_linked_patch_outputs
;
848 ctx
->tcs_num_patches
= get_tcs_num_patches(
849 ctx
->args
->options
->key
.tcs
.input_vertices
,
850 nir
->info
.tess
.tcs_vertices_out
,
852 ctx
->tcs_num_outputs
,
853 ctx
->tcs_num_patch_outputs
,
854 ctx
->args
->options
->tess_offchip_block_dw_size
,
855 ctx
->args
->options
->chip_class
,
856 ctx
->args
->options
->family
);
857 unsigned lds_size
= calculate_tess_lds_size(
858 ctx
->args
->options
->key
.tcs
.input_vertices
,
859 nir
->info
.tess
.tcs_vertices_out
,
861 ctx
->tcs_num_patches
,
862 ctx
->tcs_num_outputs
,
863 ctx
->tcs_num_patch_outputs
);
865 ctx
->args
->shader_info
->tcs
.num_patches
= ctx
->tcs_num_patches
;
866 ctx
->args
->shader_info
->tcs
.lds_size
= lds_size
;
867 ctx
->program
->config
->lds_size
= (lds_size
+ ctx
->program
->lds_alloc_granule
- 1) /
868 ctx
->program
->lds_alloc_granule
;
872 setup_tcs_variables(isel_context
*ctx
, nir_shader
*nir
)
874 nir_foreach_variable(variable
, &nir
->outputs
) {
875 assert(variable
->data
.location
>= 0 && variable
->data
.location
<= UINT8_MAX
);
877 if (variable
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
878 ctx
->tcs_tess_lvl_out_loc
= variable
->data
.driver_location
* 4u;
879 else if (variable
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
)
880 ctx
->tcs_tess_lvl_in_loc
= variable
->data
.driver_location
* 4u;
882 if (variable
->data
.patch
)
883 ctx
->output_tcs_patch_drv_loc_to_var_slot
[variable
->data
.driver_location
/ 4] = variable
->data
.location
;
885 ctx
->output_drv_loc_to_var_slot
[MESA_SHADER_TESS_CTRL
][variable
->data
.driver_location
/ 4] = variable
->data
.location
;
890 setup_tes_variables(isel_context
*ctx
, nir_shader
*nir
)
892 ctx
->tcs_num_patches
= ctx
->args
->options
->key
.tes
.num_patches
;
893 ctx
->tcs_num_outputs
= ctx
->program
->info
->tes
.num_linked_inputs
;
895 nir_foreach_variable(variable
, &nir
->outputs
) {
896 if (ctx
->stage
== tess_eval_vs
|| ctx
->stage
== ngg_tess_eval_gs
)
897 variable
->data
.driver_location
= variable
->data
.location
* 4;
900 if (ctx
->stage
== tess_eval_vs
|| ctx
->stage
== ngg_tess_eval_gs
) {
901 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->tes
.outinfo
;
902 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
903 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
908 setup_variables(isel_context
*ctx
, nir_shader
*nir
)
910 switch (nir
->info
.stage
) {
911 case MESA_SHADER_FRAGMENT
: {
912 nir_foreach_variable(variable
, &nir
->outputs
)
914 int idx
= variable
->data
.location
+ variable
->data
.index
;
915 variable
->data
.driver_location
= idx
* 4;
919 case MESA_SHADER_COMPUTE
: {
920 ctx
->program
->config
->lds_size
= (nir
->info
.cs
.shared_size
+ ctx
->program
->lds_alloc_granule
- 1) /
921 ctx
->program
->lds_alloc_granule
;
924 case MESA_SHADER_VERTEX
: {
925 setup_vs_variables(ctx
, nir
);
928 case MESA_SHADER_GEOMETRY
: {
929 setup_gs_variables(ctx
, nir
);
932 case MESA_SHADER_TESS_CTRL
: {
933 setup_tcs_variables(ctx
, nir
);
936 case MESA_SHADER_TESS_EVAL
: {
937 setup_tes_variables(ctx
, nir
);
941 unreachable("Unhandled shader stage.");
946 lower_bit_size_callback(const nir_alu_instr
*alu
, void *_
)
948 if (nir_op_is_vec(alu
->op
))
951 unsigned bit_size
= alu
->dest
.dest
.ssa
.bit_size
;
952 if (nir_alu_instr_is_comparison(alu
))
953 bit_size
= nir_src_bit_size(alu
->src
[0].src
);
955 if (bit_size
>= 32 || bit_size
== 1)
958 if (alu
->op
== nir_op_bcsel
)
961 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
963 if (info
->is_conversion
)
966 bool is_integer
= info
->output_type
& (nir_type_uint
| nir_type_int
);
967 for (unsigned i
= 0; is_integer
&& (i
< info
->num_inputs
); i
++)
968 is_integer
= info
->input_types
[i
] & (nir_type_uint
| nir_type_int
);
970 return is_integer
? 32 : 0;
974 setup_nir(isel_context
*ctx
, nir_shader
*nir
)
976 Program
*program
= ctx
->program
;
978 /* align and copy constant data */
979 while (program
->constant_data
.size() % 4u)
980 program
->constant_data
.push_back(0);
981 ctx
->constant_data_offset
= program
->constant_data
.size();
982 program
->constant_data
.insert(program
->constant_data
.end(),
983 (uint8_t*)nir
->constant_data
,
984 (uint8_t*)nir
->constant_data
+ nir
->constant_data_size
);
986 /* the variable setup has to be done before lower_io / CSE */
987 setup_variables(ctx
, nir
);
989 /* optimize and lower memory operations */
990 if (nir_lower_explicit_io(nir
, nir_var_mem_global
, nir_address_format_64bit_global
)) {
991 nir_opt_constant_folding(nir
);
995 bool lower_to_scalar
= false;
996 bool lower_pack
= false;
997 nir_variable_mode robust_modes
= (nir_variable_mode
)0;
999 if (ctx
->options
->robust_buffer_access
) {
1000 robust_modes
= (nir_variable_mode
)(nir_var_mem_ubo
|
1002 nir_var_mem_global
|
1003 nir_var_mem_push_const
);
1006 if (nir_opt_load_store_vectorize(nir
,
1007 (nir_variable_mode
)(nir_var_mem_ssbo
| nir_var_mem_ubo
|
1008 nir_var_mem_push_const
| nir_var_mem_shared
|
1009 nir_var_mem_global
),
1010 mem_vectorize_callback
, robust_modes
)) {
1011 lower_to_scalar
= true;
1014 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
1015 nir_lower_io(nir
, (nir_variable_mode
)(nir_var_shader_in
| nir_var_shader_out
), type_size
, (nir_lower_io_options
)0);
1017 if (lower_to_scalar
)
1018 nir_lower_alu_to_scalar(nir
, NULL
, NULL
);
1020 nir_lower_pack(nir
);
1022 /* lower ALU operations */
1023 // TODO: implement logic64 in aco, it's more effective for sgprs
1024 nir_lower_int64(nir
, nir
->options
->lower_int64_options
);
1026 if (nir_lower_bit_size(nir
, lower_bit_size_callback
, NULL
))
1027 nir_copy_prop(nir
); /* allow nir_opt_idiv_const() to optimize lowered divisions */
1029 nir_opt_idiv_const(nir
, 32);
1030 nir_lower_idiv(nir
, nir_lower_idiv_precise
);
1032 /* optimize the lowered ALU operations */
1033 bool more_algebraic
= true;
1034 while (more_algebraic
) {
1035 more_algebraic
= false;
1036 NIR_PASS_V(nir
, nir_copy_prop
);
1037 NIR_PASS_V(nir
, nir_opt_dce
);
1038 NIR_PASS_V(nir
, nir_opt_constant_folding
);
1039 NIR_PASS(more_algebraic
, nir
, nir_opt_algebraic
);
1042 /* Do late algebraic optimization to turn add(a, neg(b)) back into
1043 * subs, then the mandatory cleanup after algebraic. Note that it may
1044 * produce fnegs, and if so then we need to keep running to squash
1047 bool more_late_algebraic
= true;
1048 while (more_late_algebraic
) {
1049 more_late_algebraic
= false;
1050 NIR_PASS(more_late_algebraic
, nir
, nir_opt_algebraic_late
);
1051 NIR_PASS_V(nir
, nir_opt_constant_folding
);
1052 NIR_PASS_V(nir
, nir_copy_prop
);
1053 NIR_PASS_V(nir
, nir_opt_dce
);
1054 NIR_PASS_V(nir
, nir_opt_cse
);
1057 /* cleanup passes */
1058 nir_lower_load_const_to_scalar(nir
);
1059 nir_opt_shrink_load(nir
);
1060 nir_move_options move_opts
= (nir_move_options
)(
1061 nir_move_const_undef
| nir_move_load_ubo
| nir_move_load_input
|
1062 nir_move_comparisons
| nir_move_copies
);
1063 nir_opt_sink(nir
, move_opts
);
1064 nir_opt_move(nir
, move_opts
);
1065 nir_convert_to_lcssa(nir
, true, false);
1066 nir_lower_phis_to_scalar(nir
);
1068 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
1069 nir_index_ssa_defs(func
);
1073 setup_xnack(Program
*program
)
1075 switch (program
->family
) {
1083 program
->xnack_enabled
= true;
1091 setup_isel_context(Program
* program
,
1092 unsigned shader_count
,
1093 struct nir_shader
*const *shaders
,
1094 ac_shader_config
* config
,
1095 struct radv_shader_args
*args
,
1096 bool is_gs_copy_shader
)
1099 for (unsigned i
= 0; i
< shader_count
; i
++) {
1100 switch (shaders
[i
]->info
.stage
) {
1101 case MESA_SHADER_VERTEX
:
1102 program
->stage
|= sw_vs
;
1104 case MESA_SHADER_TESS_CTRL
:
1105 program
->stage
|= sw_tcs
;
1107 case MESA_SHADER_TESS_EVAL
:
1108 program
->stage
|= sw_tes
;
1110 case MESA_SHADER_GEOMETRY
:
1111 program
->stage
|= is_gs_copy_shader
? sw_gs_copy
: sw_gs
;
1113 case MESA_SHADER_FRAGMENT
:
1114 program
->stage
|= sw_fs
;
1116 case MESA_SHADER_COMPUTE
:
1117 program
->stage
|= sw_cs
;
1120 unreachable("Shader stage not implemented");
1123 bool gfx9_plus
= args
->options
->chip_class
>= GFX9
;
1124 bool ngg
= args
->shader_info
->is_ngg
&& args
->options
->chip_class
>= GFX10
;
1125 if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_es
&& !ngg
)
1126 program
->stage
|= hw_es
;
1127 else if (program
->stage
== sw_vs
&& !args
->shader_info
->vs
.as_ls
&& !ngg
)
1128 program
->stage
|= hw_vs
;
1129 else if (program
->stage
== sw_vs
&& ngg
)
1130 program
->stage
|= hw_ngg_gs
; /* GFX10/NGG: VS without GS uses the HW GS stage */
1131 else if (program
->stage
== sw_gs
)
1132 program
->stage
|= hw_gs
;
1133 else if (program
->stage
== sw_fs
)
1134 program
->stage
|= hw_fs
;
1135 else if (program
->stage
== sw_cs
)
1136 program
->stage
|= hw_cs
;
1137 else if (program
->stage
== sw_gs_copy
)
1138 program
->stage
|= hw_vs
;
1139 else if (program
->stage
== (sw_vs
| sw_gs
) && gfx9_plus
&& !ngg
)
1140 program
->stage
|= hw_gs
;
1141 else if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_ls
)
1142 program
->stage
|= hw_ls
; /* GFX6-8: VS is a Local Shader, when tessellation is used */
1143 else if (program
->stage
== sw_tcs
)
1144 program
->stage
|= hw_hs
; /* GFX6-8: TCS is a Hull Shader */
1145 else if (program
->stage
== (sw_vs
| sw_tcs
))
1146 program
->stage
|= hw_hs
; /* GFX9-10: VS+TCS merged into a Hull Shader */
1147 else if (program
->stage
== sw_tes
&& !args
->shader_info
->tes
.as_es
&& !ngg
)
1148 program
->stage
|= hw_vs
; /* GFX6-9: TES without GS uses the HW VS stage (and GFX10/legacy) */
1149 else if (program
->stage
== sw_tes
&& !args
->shader_info
->tes
.as_es
&& ngg
)
1150 program
->stage
|= hw_ngg_gs
; /* GFX10/NGG: TES without GS uses the HW GS stage */
1151 else if (program
->stage
== sw_tes
&& args
->shader_info
->tes
.as_es
&& !ngg
)
1152 program
->stage
|= hw_es
; /* GFX6-8: TES is an Export Shader */
1153 else if (program
->stage
== (sw_tes
| sw_gs
) && gfx9_plus
&& !ngg
)
1154 program
->stage
|= hw_gs
; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */
1156 unreachable("Shader stage not implemented");
1158 program
->config
= config
;
1159 program
->info
= args
->shader_info
;
1160 program
->chip_class
= args
->options
->chip_class
;
1161 program
->family
= args
->options
->family
;
1162 program
->wave_size
= args
->shader_info
->wave_size
;
1163 program
->lane_mask
= program
->wave_size
== 32 ? s1
: s2
;
1165 program
->lds_alloc_granule
= args
->options
->chip_class
>= GFX7
? 512 : 256;
1166 program
->lds_limit
= args
->options
->chip_class
>= GFX7
? 65536 : 32768;
1167 /* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
1168 program
->has_16bank_lds
= args
->options
->family
== CHIP_KABINI
|| args
->options
->family
== CHIP_STONEY
;
1170 program
->vgpr_limit
= 256;
1171 program
->vgpr_alloc_granule
= 3;
1173 if (args
->options
->chip_class
>= GFX10
) {
1174 program
->physical_sgprs
= 2560; /* doesn't matter as long as it's at least 128 * 20 */
1175 program
->sgpr_alloc_granule
= 127;
1176 program
->sgpr_limit
= 106;
1177 program
->vgpr_alloc_granule
= program
->wave_size
== 32 ? 7 : 3;
1178 } else if (program
->chip_class
>= GFX8
) {
1179 program
->physical_sgprs
= 800;
1180 program
->sgpr_alloc_granule
= 15;
1181 if (args
->options
->family
== CHIP_TONGA
|| args
->options
->family
== CHIP_ICELAND
)
1182 program
->sgpr_limit
= 94; /* workaround hardware bug */
1184 program
->sgpr_limit
= 102;
1186 program
->physical_sgprs
= 512;
1187 program
->sgpr_alloc_granule
= 7;
1188 program
->sgpr_limit
= 104;
1191 isel_context ctx
= {};
1192 ctx
.program
= program
;
1194 ctx
.options
= args
->options
;
1195 ctx
.stage
= program
->stage
;
1197 /* TODO: Check if we need to adjust min_waves for unknown workgroup sizes. */
1198 if (program
->stage
& (hw_vs
| hw_fs
)) {
1199 /* PS and legacy VS have separate waves, no workgroups */
1200 program
->workgroup_size
= program
->wave_size
;
1201 } else if (program
->stage
== compute_cs
) {
1202 /* CS sets the workgroup size explicitly */
1203 unsigned* bsize
= program
->info
->cs
.block_size
;
1204 program
->workgroup_size
= bsize
[0] * bsize
[1] * bsize
[2];
1205 } else if ((program
->stage
& hw_es
) || program
->stage
== geometry_gs
) {
1206 /* Unmerged ESGS operate in workgroups if on-chip GS (LDS rings) are enabled on GFX7-8 (not implemented in Mesa) */
1207 program
->workgroup_size
= program
->wave_size
;
1208 } else if (program
->stage
& hw_gs
) {
1209 /* If on-chip GS (LDS rings) are enabled on GFX9 or later, merged GS operates in workgroups */
1210 assert(program
->chip_class
>= GFX9
);
1211 uint32_t es_verts_per_subgrp
= G_028A44_ES_VERTS_PER_SUBGRP(program
->info
->gs_ring_info
.vgt_gs_onchip_cntl
);
1212 uint32_t gs_instr_prims_in_subgrp
= G_028A44_GS_INST_PRIMS_IN_SUBGRP(program
->info
->gs_ring_info
.vgt_gs_onchip_cntl
);
1213 uint32_t workgroup_size
= MAX2(es_verts_per_subgrp
, gs_instr_prims_in_subgrp
);
1214 program
->workgroup_size
= MAX2(MIN2(workgroup_size
, 256), 1);
1215 } else if (program
->stage
== vertex_ls
) {
1216 /* Unmerged LS operates in workgroups */
1217 program
->workgroup_size
= UINT_MAX
; /* TODO: probably tcs_num_patches * tcs_vertices_in, but those are not plumbed to ACO for LS */
1218 } else if (program
->stage
== tess_control_hs
) {
1219 /* Unmerged HS operates in workgroups, size is determined by the output vertices */
1220 setup_tcs_info(&ctx
, shaders
[0]);
1221 program
->workgroup_size
= ctx
.tcs_num_patches
* shaders
[0]->info
.tess
.tcs_vertices_out
;
1222 } else if (program
->stage
== vertex_tess_control_hs
) {
1223 /* Merged LSHS operates in workgroups, but can still have a different number of LS and HS invocations */
1224 setup_tcs_info(&ctx
, shaders
[1]);
1225 program
->workgroup_size
= ctx
.tcs_num_patches
* MAX2(shaders
[1]->info
.tess
.tcs_vertices_out
, ctx
.args
->options
->key
.tcs
.input_vertices
);
1226 } else if (program
->stage
& hw_ngg_gs
) {
1227 /* TODO: Calculate workgroup size of NGG shaders. */
1228 program
->workgroup_size
= UINT_MAX
;
1230 unreachable("Unsupported shader stage.");
1233 calc_min_waves(program
);
1234 program
->vgpr_limit
= get_addr_vgpr_from_waves(program
, program
->min_waves
);
1235 program
->sgpr_limit
= get_addr_sgpr_from_waves(program
, program
->min_waves
);
1237 unsigned scratch_size
= 0;
1238 if (program
->stage
== gs_copy_vs
) {
1239 assert(shader_count
== 1);
1240 setup_vs_output_info(&ctx
, shaders
[0], false, true, &args
->shader_info
->vs
.outinfo
);
1242 for (unsigned i
= 0; i
< shader_count
; i
++) {
1243 nir_shader
*nir
= shaders
[i
];
1244 setup_nir(&ctx
, nir
);
1247 for (unsigned i
= 0; i
< shader_count
; i
++)
1248 scratch_size
= std::max(scratch_size
, shaders
[i
]->scratch_size
);
1251 ctx
.program
->config
->scratch_bytes_per_wave
= align(scratch_size
* ctx
.program
->wave_size
, 1024);
1253 ctx
.block
= ctx
.program
->create_and_insert_block();
1254 ctx
.block
->loop_nest_depth
= 0;
1255 ctx
.block
->kind
= block_kind_top_level
;
1257 setup_xnack(program
);
1258 program
->sram_ecc_enabled
= args
->options
->family
== CHIP_ARCTURUS
;
1259 /* apparently gfx702 also has fast v_fma_f32 but I can't find a family for that */
1260 program
->has_fast_fma32
= program
->chip_class
>= GFX9
;
1261 if (args
->options
->family
== CHIP_TAHITI
|| args
->options
->family
== CHIP_CARRIZO
|| args
->options
->family
== CHIP_HAWAII
)
1262 program
->has_fast_fma32
= true;