2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <unordered_map>
29 #include "vulkan/radv_shader.h"
30 #include "vulkan/radv_descriptor_set.h"
31 #include "vulkan/radv_shader_args.h"
33 #include "ac_exp_param.h"
34 #include "ac_shader_util.h"
36 #include "util/u_math.h"
38 #define MAX_INLINE_PUSH_CONSTS 8
42 struct vs_output_state
{
43 uint8_t mask
[VARYING_SLOT_VAR31
+ 1];
44 Temp outputs
[VARYING_SLOT_VAR31
+ 1][4];
48 const struct radv_nir_compiler_options
*options
;
49 struct radv_shader_args
*args
;
52 uint32_t constant_data_offset
;
55 std::unique_ptr
<Temp
[]> allocated
;
56 std::unordered_map
<unsigned, std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
>> allocated_vec
;
57 Stage stage
; /* Stage */
58 bool has_gfx10_wave64_bpermute
= false;
61 uint16_t loop_nest_depth
= 0;
65 bool has_divergent_continue
= false;
66 bool has_divergent_branch
= false;
69 bool is_divergent
= false;
71 bool exec_potentially_empty
= false;
72 std::unique_ptr
<unsigned[]> nir_to_aco
; /* NIR block index to ACO block index */
75 Temp arg_temps
[AC_MAX_ARGS
];
77 /* inputs common for merged stages */
78 Temp merged_wave_info
= Temp(0, s1
);
81 Temp persp_centroid
, linear_centroid
;
84 bool needs_instance_id
;
86 /* VS output information */
87 unsigned num_clip_distances
;
88 unsigned num_cull_distances
;
89 vs_output_state vs_output
;
92 Temp
get_arg(isel_context
*ctx
, struct ac_arg arg
)
95 return ctx
->arg_temps
[arg
.arg_index
];
98 unsigned get_interp_input(nir_intrinsic_op intrin
, enum glsl_interp_mode interp
)
101 case INTERP_MODE_SMOOTH
:
102 case INTERP_MODE_NONE
:
103 if (intrin
== nir_intrinsic_load_barycentric_pixel
||
104 intrin
== nir_intrinsic_load_barycentric_at_sample
||
105 intrin
== nir_intrinsic_load_barycentric_at_offset
)
106 return S_0286CC_PERSP_CENTER_ENA(1);
107 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
108 return S_0286CC_PERSP_CENTROID_ENA(1);
109 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
110 return S_0286CC_PERSP_SAMPLE_ENA(1);
112 case INTERP_MODE_NOPERSPECTIVE
:
113 if (intrin
== nir_intrinsic_load_barycentric_pixel
)
114 return S_0286CC_LINEAR_CENTER_ENA(1);
115 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
116 return S_0286CC_LINEAR_CENTROID_ENA(1);
117 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
118 return S_0286CC_LINEAR_SAMPLE_ENA(1);
126 void init_context(isel_context
*ctx
, nir_shader
*shader
)
128 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
129 unsigned lane_mask_size
= ctx
->program
->lane_mask
.size();
131 ctx
->shader
= shader
;
132 ctx
->divergent_vals
= nir_divergence_analysis(shader
, nir_divergence_view_index_uniform
);
134 std::unique_ptr
<Temp
[]> allocated
{new Temp
[impl
->ssa_alloc
]()};
136 unsigned spi_ps_inputs
= 0;
138 std::unique_ptr
<unsigned[]> nir_to_aco
{new unsigned[impl
->num_blocks
]()};
143 nir_foreach_block(block
, impl
) {
144 nir_foreach_instr(instr
, block
) {
145 switch(instr
->type
) {
146 case nir_instr_type_alu
: {
147 nir_alu_instr
*alu_instr
= nir_instr_as_alu(instr
);
148 unsigned size
= alu_instr
->dest
.dest
.ssa
.num_components
;
149 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 64)
151 RegType type
= RegType::sgpr
;
152 switch(alu_instr
->op
) {
174 case nir_op_fround_even
:
183 case nir_op_pack_half_2x16
:
184 case nir_op_unpack_half_2x16_split_x
:
185 case nir_op_unpack_half_2x16_split_y
:
188 case nir_op_fddx_fine
:
189 case nir_op_fddy_fine
:
190 case nir_op_fddx_coarse
:
191 case nir_op_fddy_coarse
:
192 case nir_op_fquantize2f16
:
194 case nir_op_frexp_sig
:
195 case nir_op_frexp_exp
:
196 case nir_op_cube_face_index
:
197 case nir_op_cube_face_coord
:
198 type
= RegType::vgpr
;
211 size
= lane_mask_size
;
219 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
222 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
223 size
= lane_mask_size
;
225 if (ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
]) {
226 type
= RegType::vgpr
;
228 if (allocated
[alu_instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
||
229 allocated
[alu_instr
->src
[2].src
.ssa
->index
].type() == RegType::vgpr
) {
230 type
= RegType::vgpr
;
233 if (alu_instr
->src
[1].src
.ssa
->num_components
== 1 && alu_instr
->src
[2].src
.ssa
->num_components
== 1) {
234 assert(allocated
[alu_instr
->src
[1].src
.ssa
->index
].size() == allocated
[alu_instr
->src
[2].src
.ssa
->index
].size());
235 size
= allocated
[alu_instr
->src
[1].src
.ssa
->index
].size();
240 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
241 size
= lane_mask_size
;
243 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
247 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
248 size
= lane_mask_size
;
250 for (unsigned i
= 0; i
< nir_op_infos
[alu_instr
->op
].num_inputs
; i
++) {
251 if (allocated
[alu_instr
->src
[i
].src
.ssa
->index
].type() == RegType::vgpr
)
252 type
= RegType::vgpr
;
257 allocated
[alu_instr
->dest
.dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
260 case nir_instr_type_load_const
: {
261 unsigned size
= nir_instr_as_load_const(instr
)->def
.num_components
;
262 if (nir_instr_as_load_const(instr
)->def
.bit_size
== 64)
264 else if (nir_instr_as_load_const(instr
)->def
.bit_size
== 1)
265 size
*= lane_mask_size
;
266 allocated
[nir_instr_as_load_const(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
269 case nir_instr_type_intrinsic
: {
270 nir_intrinsic_instr
*intrinsic
= nir_instr_as_intrinsic(instr
);
271 if (!nir_intrinsic_infos
[intrinsic
->intrinsic
].has_dest
)
273 unsigned size
= intrinsic
->dest
.ssa
.num_components
;
274 if (intrinsic
->dest
.ssa
.bit_size
== 64)
276 RegType type
= RegType::sgpr
;
277 switch(intrinsic
->intrinsic
) {
278 case nir_intrinsic_load_push_constant
:
279 case nir_intrinsic_load_work_group_id
:
280 case nir_intrinsic_load_num_work_groups
:
281 case nir_intrinsic_load_subgroup_id
:
282 case nir_intrinsic_load_num_subgroups
:
283 case nir_intrinsic_load_first_vertex
:
284 case nir_intrinsic_load_base_instance
:
285 case nir_intrinsic_get_buffer_size
:
286 case nir_intrinsic_vote_all
:
287 case nir_intrinsic_vote_any
:
288 case nir_intrinsic_read_first_invocation
:
289 case nir_intrinsic_read_invocation
:
290 case nir_intrinsic_first_invocation
:
291 type
= RegType::sgpr
;
292 if (intrinsic
->dest
.ssa
.bit_size
== 1)
293 size
= lane_mask_size
;
295 case nir_intrinsic_ballot
:
296 type
= RegType::sgpr
;
298 case nir_intrinsic_load_sample_id
:
299 case nir_intrinsic_load_sample_mask_in
:
300 case nir_intrinsic_load_input
:
301 case nir_intrinsic_load_vertex_id
:
302 case nir_intrinsic_load_vertex_id_zero_base
:
303 case nir_intrinsic_load_barycentric_sample
:
304 case nir_intrinsic_load_barycentric_pixel
:
305 case nir_intrinsic_load_barycentric_centroid
:
306 case nir_intrinsic_load_barycentric_at_sample
:
307 case nir_intrinsic_load_barycentric_at_offset
:
308 case nir_intrinsic_load_interpolated_input
:
309 case nir_intrinsic_load_frag_coord
:
310 case nir_intrinsic_load_sample_pos
:
311 case nir_intrinsic_load_layer_id
:
312 case nir_intrinsic_load_local_invocation_id
:
313 case nir_intrinsic_load_local_invocation_index
:
314 case nir_intrinsic_load_subgroup_invocation
:
315 case nir_intrinsic_write_invocation_amd
:
316 case nir_intrinsic_mbcnt_amd
:
317 case nir_intrinsic_load_instance_id
:
318 case nir_intrinsic_ssbo_atomic_add
:
319 case nir_intrinsic_ssbo_atomic_imin
:
320 case nir_intrinsic_ssbo_atomic_umin
:
321 case nir_intrinsic_ssbo_atomic_imax
:
322 case nir_intrinsic_ssbo_atomic_umax
:
323 case nir_intrinsic_ssbo_atomic_and
:
324 case nir_intrinsic_ssbo_atomic_or
:
325 case nir_intrinsic_ssbo_atomic_xor
:
326 case nir_intrinsic_ssbo_atomic_exchange
:
327 case nir_intrinsic_ssbo_atomic_comp_swap
:
328 case nir_intrinsic_global_atomic_add
:
329 case nir_intrinsic_global_atomic_imin
:
330 case nir_intrinsic_global_atomic_umin
:
331 case nir_intrinsic_global_atomic_imax
:
332 case nir_intrinsic_global_atomic_umax
:
333 case nir_intrinsic_global_atomic_and
:
334 case nir_intrinsic_global_atomic_or
:
335 case nir_intrinsic_global_atomic_xor
:
336 case nir_intrinsic_global_atomic_exchange
:
337 case nir_intrinsic_global_atomic_comp_swap
:
338 case nir_intrinsic_image_deref_atomic_add
:
339 case nir_intrinsic_image_deref_atomic_umin
:
340 case nir_intrinsic_image_deref_atomic_imin
:
341 case nir_intrinsic_image_deref_atomic_umax
:
342 case nir_intrinsic_image_deref_atomic_imax
:
343 case nir_intrinsic_image_deref_atomic_and
:
344 case nir_intrinsic_image_deref_atomic_or
:
345 case nir_intrinsic_image_deref_atomic_xor
:
346 case nir_intrinsic_image_deref_atomic_exchange
:
347 case nir_intrinsic_image_deref_atomic_comp_swap
:
348 case nir_intrinsic_image_deref_size
:
349 case nir_intrinsic_shared_atomic_add
:
350 case nir_intrinsic_shared_atomic_imin
:
351 case nir_intrinsic_shared_atomic_umin
:
352 case nir_intrinsic_shared_atomic_imax
:
353 case nir_intrinsic_shared_atomic_umax
:
354 case nir_intrinsic_shared_atomic_and
:
355 case nir_intrinsic_shared_atomic_or
:
356 case nir_intrinsic_shared_atomic_xor
:
357 case nir_intrinsic_shared_atomic_exchange
:
358 case nir_intrinsic_shared_atomic_comp_swap
:
359 case nir_intrinsic_load_scratch
:
360 type
= RegType::vgpr
;
362 case nir_intrinsic_shuffle
:
363 case nir_intrinsic_quad_broadcast
:
364 case nir_intrinsic_quad_swap_horizontal
:
365 case nir_intrinsic_quad_swap_vertical
:
366 case nir_intrinsic_quad_swap_diagonal
:
367 case nir_intrinsic_quad_swizzle_amd
:
368 case nir_intrinsic_masked_swizzle_amd
:
369 case nir_intrinsic_inclusive_scan
:
370 case nir_intrinsic_exclusive_scan
:
371 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
372 size
= lane_mask_size
;
373 type
= RegType::sgpr
;
374 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
375 type
= RegType::sgpr
;
377 type
= RegType::vgpr
;
380 case nir_intrinsic_load_view_index
:
381 type
= ctx
->stage
== fragment_fs
? RegType::vgpr
: RegType::sgpr
;
383 case nir_intrinsic_load_front_face
:
384 case nir_intrinsic_load_helper_invocation
:
385 case nir_intrinsic_is_helper_invocation
:
386 type
= RegType::sgpr
;
387 size
= lane_mask_size
;
389 case nir_intrinsic_reduce
:
390 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
391 size
= lane_mask_size
;
392 type
= RegType::sgpr
;
393 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
394 type
= RegType::sgpr
;
396 type
= RegType::vgpr
;
399 case nir_intrinsic_load_ubo
:
400 case nir_intrinsic_load_ssbo
:
401 case nir_intrinsic_load_global
:
402 case nir_intrinsic_vulkan_resource_index
:
403 type
= ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
405 /* due to copy propagation, the swizzled imov is removed if num dest components == 1 */
406 case nir_intrinsic_load_shared
:
407 if (ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
])
408 type
= RegType::vgpr
;
410 type
= RegType::sgpr
;
413 for (unsigned i
= 0; i
< nir_intrinsic_infos
[intrinsic
->intrinsic
].num_srcs
; i
++) {
414 if (allocated
[intrinsic
->src
[i
].ssa
->index
].type() == RegType::vgpr
)
415 type
= RegType::vgpr
;
419 allocated
[intrinsic
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
421 switch(intrinsic
->intrinsic
) {
422 case nir_intrinsic_load_barycentric_sample
:
423 case nir_intrinsic_load_barycentric_pixel
:
424 case nir_intrinsic_load_barycentric_centroid
:
425 case nir_intrinsic_load_barycentric_at_sample
:
426 case nir_intrinsic_load_barycentric_at_offset
: {
427 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(intrinsic
);
428 spi_ps_inputs
|= get_interp_input(intrinsic
->intrinsic
, mode
);
431 case nir_intrinsic_load_front_face
:
432 spi_ps_inputs
|= S_0286CC_FRONT_FACE_ENA(1);
434 case nir_intrinsic_load_frag_coord
:
435 case nir_intrinsic_load_sample_pos
: {
436 uint8_t mask
= nir_ssa_def_components_read(&intrinsic
->dest
.ssa
);
437 for (unsigned i
= 0; i
< 4; i
++) {
439 spi_ps_inputs
|= S_0286CC_POS_X_FLOAT_ENA(1) << i
;
444 case nir_intrinsic_load_sample_id
:
445 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
447 case nir_intrinsic_load_sample_mask_in
:
448 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
449 spi_ps_inputs
|= S_0286CC_SAMPLE_COVERAGE_ENA(1);
456 case nir_instr_type_tex
: {
457 nir_tex_instr
* tex
= nir_instr_as_tex(instr
);
458 unsigned size
= tex
->dest
.ssa
.num_components
;
460 if (tex
->dest
.ssa
.bit_size
== 64)
462 if (tex
->op
== nir_texop_texture_samples
)
463 assert(!ctx
->divergent_vals
[tex
->dest
.ssa
.index
]);
464 if (ctx
->divergent_vals
[tex
->dest
.ssa
.index
])
465 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::vgpr
, size
));
467 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
470 case nir_instr_type_parallel_copy
: {
471 nir_foreach_parallel_copy_entry(entry
, nir_instr_as_parallel_copy(instr
)) {
472 allocated
[entry
->dest
.ssa
.index
] = allocated
[entry
->src
.ssa
->index
];
476 case nir_instr_type_ssa_undef
: {
477 unsigned size
= nir_instr_as_ssa_undef(instr
)->def
.num_components
;
478 if (nir_instr_as_ssa_undef(instr
)->def
.bit_size
== 64)
480 allocated
[nir_instr_as_ssa_undef(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
483 case nir_instr_type_phi
: {
484 nir_phi_instr
* phi
= nir_instr_as_phi(instr
);
486 unsigned size
= phi
->dest
.ssa
.num_components
;
488 if (phi
->dest
.ssa
.bit_size
== 1) {
489 assert(size
== 1 && "multiple components not yet supported on boolean phis.");
490 type
= RegType::sgpr
;
491 size
*= lane_mask_size
;
492 allocated
[phi
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
496 if (ctx
->divergent_vals
[phi
->dest
.ssa
.index
]) {
497 type
= RegType::vgpr
;
499 type
= RegType::sgpr
;
500 nir_foreach_phi_src (src
, phi
) {
501 if (allocated
[src
->src
.ssa
->index
].type() == RegType::vgpr
)
502 type
= RegType::vgpr
;
503 if (allocated
[src
->src
.ssa
->index
].type() == RegType::none
)
508 size
*= phi
->dest
.ssa
.bit_size
== 64 ? 2 : 1;
509 RegClass rc
= RegClass(type
, size
);
510 if (rc
!= allocated
[phi
->dest
.ssa
.index
].regClass()) {
513 nir_foreach_phi_src(src
, phi
)
514 assert(allocated
[src
->src
.ssa
->index
].size() == rc
.size());
516 allocated
[phi
->dest
.ssa
.index
] = Temp(0, rc
);
526 if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_inputs
)) {
527 /* If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be enabled too */
528 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
531 if (!(spi_ps_inputs
& 0x7F)) {
532 /* At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled */
533 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
536 ctx
->program
->config
->spi_ps_input_ena
= spi_ps_inputs
;
537 ctx
->program
->config
->spi_ps_input_addr
= spi_ps_inputs
;
539 for (unsigned i
= 0; i
< impl
->ssa_alloc
; i
++)
540 allocated
[i
] = Temp(ctx
->program
->allocateId(), allocated
[i
].regClass());
542 ctx
->allocated
.reset(allocated
.release());
543 ctx
->cf_info
.nir_to_aco
.reset(nir_to_aco
.release());
546 Pseudo_instruction
*add_startpgm(struct isel_context
*ctx
)
548 unsigned arg_count
= ctx
->args
->ac
.arg_count
;
549 if (ctx
->stage
== fragment_fs
) {
550 /* LLVM optimizes away unused FS inputs and computes spi_ps_input_addr
551 * itself and then communicates the results back via the ELF binary.
552 * Mirror what LLVM does by re-mapping the VGPR arguments here.
554 * TODO: If we made the FS input scanning code into a separate pass that
555 * could run before argument setup, then this wouldn't be necessary
558 struct ac_shader_args
*args
= &ctx
->args
->ac
;
560 for (unsigned i
= 0, vgpr_arg
= 0, vgpr_reg
= 0; i
< args
->arg_count
; i
++) {
561 if (args
->args
[i
].file
!= AC_ARG_VGPR
) {
566 if (!(ctx
->program
->config
->spi_ps_input_addr
& (1 << vgpr_arg
))) {
567 args
->args
[i
].skip
= true;
569 args
->args
[i
].offset
= vgpr_reg
;
570 vgpr_reg
+= args
->args
[i
].size
;
577 aco_ptr
<Pseudo_instruction
> startpgm
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_startpgm
, Format::PSEUDO
, 0, arg_count
+ 1)};
578 for (unsigned i
= 0, arg
= 0; i
< ctx
->args
->ac
.arg_count
; i
++) {
579 if (ctx
->args
->ac
.args
[i
].skip
)
582 enum ac_arg_regfile file
= ctx
->args
->ac
.args
[i
].file
;
583 unsigned size
= ctx
->args
->ac
.args
[i
].size
;
584 unsigned reg
= ctx
->args
->ac
.args
[i
].offset
;
585 RegClass type
= RegClass(file
== AC_ARG_SGPR
? RegType::sgpr
: RegType::vgpr
, size
);
586 Temp dst
= Temp
{ctx
->program
->allocateId(), type
};
587 ctx
->arg_temps
[i
] = dst
;
588 startpgm
->definitions
[arg
] = Definition(dst
);
589 startpgm
->definitions
[arg
].setFixed(PhysReg
{file
== AC_ARG_SGPR
? reg
: reg
+ 256});
592 startpgm
->definitions
[arg_count
] = Definition
{ctx
->program
->allocateId(), exec
, ctx
->program
->lane_mask
};
593 Pseudo_instruction
*instr
= startpgm
.get();
594 ctx
->block
->instructions
.push_back(std::move(startpgm
));
596 /* Stash these in the program so that they can be accessed later when
599 ctx
->program
->private_segment_buffer
= get_arg(ctx
, ctx
->args
->ring_offsets
);
600 ctx
->program
->scratch_offset
= get_arg(ctx
, ctx
->args
->scratch_offset
);
606 type_size(const struct glsl_type
*type
, bool bindless
)
608 // TODO: don't we need type->std430_base_alignment() here?
609 return glsl_count_attribute_slots(type
, false);
613 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
615 assert(glsl_type_is_vector_or_scalar(type
));
617 uint32_t comp_size
= glsl_type_is_boolean(type
)
618 ? 4 : glsl_get_bit_size(type
) / 8;
619 unsigned length
= glsl_get_vector_elements(type
);
620 *size
= comp_size
* length
,
625 mem_vectorize_callback(unsigned align
, unsigned bit_size
,
626 unsigned num_components
, unsigned high_offset
,
627 nir_intrinsic_instr
*low
, nir_intrinsic_instr
*high
)
629 if ((bit_size
!= 32 && bit_size
!= 64) || num_components
> 4)
632 /* >128 bit loads are split except with SMEM */
633 if (bit_size
* num_components
> 128)
636 switch (low
->intrinsic
) {
637 case nir_intrinsic_load_ubo
:
638 case nir_intrinsic_load_ssbo
:
639 case nir_intrinsic_store_ssbo
:
640 case nir_intrinsic_load_push_constant
:
641 return align
% 4 == 0;
642 case nir_intrinsic_load_deref
:
643 case nir_intrinsic_store_deref
:
644 assert(nir_src_as_deref(low
->src
[0])->mode
== nir_var_mem_shared
);
646 case nir_intrinsic_load_shared
:
647 case nir_intrinsic_store_shared
:
648 if (bit_size
* num_components
> 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
649 return align
% 16 == 0;
651 return align
% 4 == 0;
659 setup_vs_variables(isel_context
*ctx
, nir_shader
*nir
)
661 nir_foreach_variable(variable
, &nir
->inputs
)
663 variable
->data
.driver_location
= variable
->data
.location
* 4;
665 nir_foreach_variable(variable
, &nir
->outputs
)
667 variable
->data
.driver_location
= variable
->data
.location
* 4;
670 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
672 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
673 sizeof(outinfo
->vs_output_param_offset
));
675 ctx
->needs_instance_id
= ctx
->program
->info
->vs
.needs_instance_id
;
677 bool export_clip_dists
= ctx
->options
->key
.vs_common_out
.export_clip_dists
;
679 outinfo
->param_exports
= 0;
680 int pos_written
= 0x1;
681 if (outinfo
->writes_pointsize
|| outinfo
->writes_viewport_index
|| outinfo
->writes_layer
)
682 pos_written
|= 1 << 1;
684 nir_foreach_variable(variable
, &nir
->outputs
)
686 int idx
= variable
->data
.location
;
687 unsigned slots
= variable
->type
->count_attribute_slots(false);
688 if (variable
->data
.compact
) {
689 unsigned component_count
= variable
->data
.location_frac
+ variable
->type
->length
;
690 slots
= (component_count
+ 3) / 4;
693 if (idx
>= VARYING_SLOT_VAR0
|| idx
== VARYING_SLOT_LAYER
|| idx
== VARYING_SLOT_PRIMITIVE_ID
||
694 ((idx
== VARYING_SLOT_CLIP_DIST0
|| idx
== VARYING_SLOT_CLIP_DIST1
) && export_clip_dists
)) {
695 for (unsigned i
= 0; i
< slots
; i
++) {
696 if (outinfo
->vs_output_param_offset
[idx
+ i
] == AC_EXP_PARAM_UNDEFINED
)
697 outinfo
->vs_output_param_offset
[idx
+ i
] = outinfo
->param_exports
++;
701 if (outinfo
->writes_layer
&&
702 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] == AC_EXP_PARAM_UNDEFINED
) {
703 /* when ctx->options->key.has_multiview_view_index = true, the layer
704 * variable isn't declared in NIR and it's isel's job to get the layer */
705 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = outinfo
->param_exports
++;
708 if (outinfo
->export_prim_id
) {
709 assert(outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] == AC_EXP_PARAM_UNDEFINED
);
710 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = outinfo
->param_exports
++;
713 ctx
->num_clip_distances
= util_bitcount(outinfo
->clip_dist_mask
);
714 ctx
->num_cull_distances
= util_bitcount(outinfo
->cull_dist_mask
);
716 assert(ctx
->num_clip_distances
+ ctx
->num_cull_distances
<= 8);
718 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
719 pos_written
|= 1 << 2;
720 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
721 pos_written
|= 1 << 3;
723 outinfo
->pos_exports
= util_bitcount(pos_written
);
727 setup_variables(isel_context
*ctx
, nir_shader
*nir
)
729 switch (nir
->info
.stage
) {
730 case MESA_SHADER_FRAGMENT
: {
731 nir_foreach_variable(variable
, &nir
->outputs
)
733 int idx
= variable
->data
.location
+ variable
->data
.index
;
734 variable
->data
.driver_location
= idx
* 4;
738 case MESA_SHADER_COMPUTE
: {
739 ctx
->program
->config
->lds_size
= (nir
->info
.cs
.shared_size
+ ctx
->program
->lds_alloc_granule
- 1) /
740 ctx
->program
->lds_alloc_granule
;
743 case MESA_SHADER_VERTEX
: {
744 setup_vs_variables(ctx
, nir
);
748 unreachable("Unhandled shader stage.");
753 setup_isel_context(Program
* program
,
754 unsigned shader_count
,
755 struct nir_shader
*const *shaders
,
756 ac_shader_config
* config
,
757 struct radv_shader_args
*args
)
760 for (unsigned i
= 0; i
< shader_count
; i
++) {
761 switch (shaders
[i
]->info
.stage
) {
762 case MESA_SHADER_VERTEX
:
763 program
->stage
|= sw_vs
;
765 case MESA_SHADER_TESS_CTRL
:
766 program
->stage
|= sw_tcs
;
768 case MESA_SHADER_TESS_EVAL
:
769 program
->stage
|= sw_tes
;
771 case MESA_SHADER_GEOMETRY
:
772 program
->stage
|= sw_gs
;
774 case MESA_SHADER_FRAGMENT
:
775 program
->stage
|= sw_fs
;
777 case MESA_SHADER_COMPUTE
:
778 program
->stage
|= sw_cs
;
781 unreachable("Shader stage not implemented");
784 if (program
->stage
== sw_vs
)
785 program
->stage
|= hw_vs
;
786 else if (program
->stage
== sw_fs
)
787 program
->stage
|= hw_fs
;
788 else if (program
->stage
== sw_cs
)
789 program
->stage
|= hw_cs
;
791 unreachable("Shader stage not implemented");
793 program
->config
= config
;
794 program
->info
= args
->shader_info
;
795 program
->chip_class
= args
->options
->chip_class
;
796 program
->family
= args
->options
->family
;
797 program
->wave_size
= args
->shader_info
->wave_size
;
798 program
->lane_mask
= program
->wave_size
== 32 ? s1
: s2
;
800 program
->lds_alloc_granule
= args
->options
->chip_class
>= GFX7
? 512 : 256;
801 program
->lds_limit
= args
->options
->chip_class
>= GFX7
? 65536 : 32768;
802 program
->vgpr_limit
= 256;
803 program
->vgpr_alloc_granule
= 3;
805 if (args
->options
->chip_class
>= GFX10
) {
806 program
->physical_sgprs
= 2560; /* doesn't matter as long as it's at least 128 * 20 */
807 program
->sgpr_alloc_granule
= 127;
808 program
->sgpr_limit
= 106;
809 program
->vgpr_alloc_granule
= program
->wave_size
== 32 ? 7 : 3;
810 } else if (program
->chip_class
>= GFX8
) {
811 program
->physical_sgprs
= 800;
812 program
->sgpr_alloc_granule
= 15;
813 if (args
->options
->family
== CHIP_TONGA
|| args
->options
->family
== CHIP_ICELAND
)
814 program
->sgpr_limit
= 94; /* workaround hardware bug */
816 program
->sgpr_limit
= 102;
818 program
->physical_sgprs
= 512;
819 program
->sgpr_alloc_granule
= 7;
820 program
->sgpr_limit
= 104;
823 /* TODO: we don't have to allocate VCC if we don't need it */
824 program
->needs_vcc
= true;
826 calc_min_waves(program
);
827 program
->vgpr_limit
= get_addr_vgpr_from_waves(program
, program
->min_waves
);
828 program
->sgpr_limit
= get_addr_sgpr_from_waves(program
, program
->min_waves
);
830 isel_context ctx
= {};
831 ctx
.program
= program
;
833 ctx
.options
= args
->options
;
834 ctx
.stage
= program
->stage
;
836 for (unsigned i
= 0; i
< shader_count
; i
++) {
837 nir_shader
*nir
= shaders
[i
];
839 /* align and copy constant data */
840 while (program
->constant_data
.size() % 4u)
841 program
->constant_data
.push_back(0);
842 ctx
.constant_data_offset
= program
->constant_data
.size();
843 program
->constant_data
.insert(program
->constant_data
.end(),
844 (uint8_t*)nir
->constant_data
,
845 (uint8_t*)nir
->constant_data
+ nir
->constant_data_size
);
847 /* the variable setup has to be done before lower_io / CSE */
848 setup_variables(&ctx
, nir
);
850 /* optimize and lower memory operations */
851 bool lower_to_scalar
= false;
852 bool lower_pack
= false;
853 if (nir_opt_load_store_vectorize(nir
,
854 (nir_variable_mode
)(nir_var_mem_ssbo
| nir_var_mem_ubo
|
855 nir_var_mem_push_const
| nir_var_mem_shared
),
856 mem_vectorize_callback
)) {
857 lower_to_scalar
= true;
860 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
861 nir_lower_io(nir
, (nir_variable_mode
)(nir_var_shader_in
| nir_var_shader_out
), type_size
, (nir_lower_io_options
)0);
862 nir_lower_explicit_io(nir
, nir_var_mem_global
, nir_address_format_64bit_global
);
865 nir_lower_alu_to_scalar(nir
, NULL
, NULL
);
869 /* lower ALU operations */
870 // TODO: implement logic64 in aco, it's more effective for sgprs
871 nir_lower_int64(nir
, nir
->options
->lower_int64_options
);
873 nir_opt_idiv_const(nir
, 32);
874 nir_lower_idiv(nir
, nir_lower_idiv_precise
);
876 /* optimize the lowered ALU operations */
877 bool more_algebraic
= true;
878 while (more_algebraic
) {
879 more_algebraic
= false;
880 NIR_PASS_V(nir
, nir_copy_prop
);
881 NIR_PASS_V(nir
, nir_opt_dce
);
882 NIR_PASS_V(nir
, nir_opt_constant_folding
);
883 NIR_PASS(more_algebraic
, nir
, nir_opt_algebraic
);
886 /* Do late algebraic optimization to turn add(a, neg(b)) back into
887 * subs, then the mandatory cleanup after algebraic. Note that it may
888 * produce fnegs, and if so then we need to keep running to squash
891 bool more_late_algebraic
= true;
892 while (more_late_algebraic
) {
893 more_late_algebraic
= false;
894 NIR_PASS(more_late_algebraic
, nir
, nir_opt_algebraic_late
);
895 NIR_PASS_V(nir
, nir_opt_constant_folding
);
896 NIR_PASS_V(nir
, nir_copy_prop
);
897 NIR_PASS_V(nir
, nir_opt_dce
);
898 NIR_PASS_V(nir
, nir_opt_cse
);
902 nir_lower_load_const_to_scalar(nir
);
903 nir_opt_shrink_load(nir
);
904 nir_move_options move_opts
= (nir_move_options
)(
905 nir_move_const_undef
| nir_move_load_ubo
| nir_move_load_input
| nir_move_comparisons
);
906 nir_opt_sink(nir
, move_opts
);
907 nir_opt_move(nir
, move_opts
);
908 nir_convert_to_lcssa(nir
, true, false);
909 nir_lower_phis_to_scalar(nir
);
911 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
912 nir_index_ssa_defs(func
);
913 nir_metadata_require(func
, nir_metadata_block_index
);
915 if (args
->options
->dump_preoptir
) {
916 fprintf(stderr
, "NIR shader before instruction selection:\n");
917 nir_print_shader(nir
, stderr
);
921 unsigned scratch_size
= 0;
922 for (unsigned i
= 0; i
< shader_count
; i
++)
923 scratch_size
= std::max(scratch_size
, shaders
[i
]->scratch_size
);
924 ctx
.program
->config
->scratch_bytes_per_wave
= align(scratch_size
* ctx
.program
->wave_size
, 1024);
926 ctx
.block
= ctx
.program
->create_and_insert_block();
927 ctx
.block
->loop_nest_depth
= 0;
928 ctx
.block
->kind
= block_kind_top_level
;