2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <unordered_map>
29 #include "nir_control_flow.h"
30 #include "vulkan/radv_shader.h"
31 #include "vulkan/radv_descriptor_set.h"
32 #include "vulkan/radv_shader_args.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
37 #include "util/u_math.h"
39 #define MAX_INLINE_PUSH_CONSTS 8
43 struct shader_io_state
{
44 uint8_t mask
[VARYING_SLOT_MAX
];
45 Temp temps
[VARYING_SLOT_MAX
* 4u];
48 memset(mask
, 0, sizeof(mask
));
49 std::fill_n(temps
, VARYING_SLOT_MAX
* 4u, Temp(0, RegClass::v1
));
54 const struct radv_nir_compiler_options
*options
;
55 struct radv_shader_args
*args
;
58 uint32_t constant_data_offset
;
61 std::unique_ptr
<Temp
[]> allocated
;
62 std::unordered_map
<unsigned, std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
>> allocated_vec
;
63 Stage stage
; /* Stage */
64 bool has_gfx10_wave64_bpermute
= false;
67 uint16_t loop_nest_depth
= 0;
71 bool has_divergent_continue
= false;
72 bool has_divergent_branch
= false;
75 bool is_divergent
= false;
77 bool exec_potentially_empty_discard
= false; /* set to false when loop_nest_depth==0 && parent_if.is_divergent==false */
78 uint16_t exec_potentially_empty_break_depth
= UINT16_MAX
;
79 /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth
80 * and parent_if.is_divergent==false. Called _break but it's also used for
82 bool exec_potentially_empty_break
= false;
83 std::unique_ptr
<unsigned[]> nir_to_aco
; /* NIR block index to ACO block index */
86 Temp arg_temps
[AC_MAX_ARGS
];
89 Temp persp_centroid
, linear_centroid
;
94 /* gathered information */
95 uint64_t input_masks
[MESA_SHADER_COMPUTE
];
96 uint64_t output_masks
[MESA_SHADER_COMPUTE
];
98 /* VS output information */
99 bool export_clip_dists
;
100 unsigned num_clip_distances
;
101 unsigned num_cull_distances
;
103 /* tessellation information */
104 unsigned tcs_tess_lvl_out_loc
;
105 unsigned tcs_tess_lvl_in_loc
;
106 uint64_t tcs_temp_only_inputs
;
107 uint32_t tcs_num_inputs
;
108 uint32_t tcs_num_outputs
;
109 uint32_t tcs_num_patch_outputs
;
110 uint32_t tcs_num_patches
;
111 bool tcs_in_out_eq
= false;
113 /* I/O information */
114 shader_io_state inputs
;
115 shader_io_state outputs
;
116 uint8_t output_drv_loc_to_var_slot
[MESA_SHADER_COMPUTE
][VARYING_SLOT_MAX
];
117 uint8_t output_tcs_patch_drv_loc_to_var_slot
[VARYING_SLOT_MAX
];
120 Temp
get_arg(isel_context
*ctx
, struct ac_arg arg
)
123 return ctx
->arg_temps
[arg
.arg_index
];
126 unsigned get_interp_input(nir_intrinsic_op intrin
, enum glsl_interp_mode interp
)
129 case INTERP_MODE_SMOOTH
:
130 case INTERP_MODE_NONE
:
131 if (intrin
== nir_intrinsic_load_barycentric_pixel
||
132 intrin
== nir_intrinsic_load_barycentric_at_sample
||
133 intrin
== nir_intrinsic_load_barycentric_at_offset
)
134 return S_0286CC_PERSP_CENTER_ENA(1);
135 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
136 return S_0286CC_PERSP_CENTROID_ENA(1);
137 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
138 return S_0286CC_PERSP_SAMPLE_ENA(1);
140 case INTERP_MODE_NOPERSPECTIVE
:
141 if (intrin
== nir_intrinsic_load_barycentric_pixel
)
142 return S_0286CC_LINEAR_CENTER_ENA(1);
143 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
144 return S_0286CC_LINEAR_CENTROID_ENA(1);
145 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
146 return S_0286CC_LINEAR_SAMPLE_ENA(1);
154 /* If one side of a divergent IF ends in a branch and the other doesn't, we
155 * might have to emit the contents of the side without the branch at the merge
156 * block instead. This is so that we can use any SGPR live-out of the side
157 * without the branch without creating a linear phi in the invert or merge block. */
159 sanitize_if(nir_function_impl
*impl
, bool *divergent
, nir_if
*nif
)
161 //TODO: skip this if the condition is uniform and there are no divergent breaks/continues?
163 nir_block
*then_block
= nir_if_last_then_block(nif
);
164 nir_block
*else_block
= nir_if_last_else_block(nif
);
165 bool then_jump
= nir_block_ends_in_jump(then_block
) || nir_block_is_unreachable(then_block
);
166 bool else_jump
= nir_block_ends_in_jump(else_block
) || nir_block_is_unreachable(else_block
);
167 if (then_jump
== else_jump
)
170 /* If the continue from block is empty then return as there is nothing to
173 if (nir_cf_list_is_empty_block(else_jump
? &nif
->then_list
: &nif
->else_list
))
176 /* Even though this if statement has a jump on one side, we may still have
177 * phis afterwards. Single-source phis can be produced by loop unrolling
178 * or dead control-flow passes and are perfectly legal. Run a quick phi
179 * removal on the block after the if to clean up any such phis.
181 nir_opt_remove_phis_block(nir_cf_node_as_block(nir_cf_node_next(&nif
->cf_node
)));
183 /* Finally, move the continue from branch after the if-statement. */
184 nir_block
*last_continue_from_blk
= else_jump
? then_block
: else_block
;
185 nir_block
*first_continue_from_blk
= else_jump
?
186 nir_if_first_then_block(nif
) : nir_if_first_else_block(nif
);
189 nir_cf_extract(&tmp
, nir_before_block(first_continue_from_blk
),
190 nir_after_block(last_continue_from_blk
));
191 nir_cf_reinsert(&tmp
, nir_after_cf_node(&nif
->cf_node
));
193 /* nir_cf_extract() invalidates dominance metadata, but it should still be
194 * correct because of the specific type of transformation we did. Block
195 * indices are not valid except for block_0's, which is all we care about for
196 * nir_block_is_unreachable(). */
197 impl
->valid_metadata
=
198 (nir_metadata
)(impl
->valid_metadata
| nir_metadata_dominance
| nir_metadata_block_index
);
204 sanitize_cf_list(nir_function_impl
*impl
, bool *divergent
, struct exec_list
*cf_list
)
206 bool progress
= false;
207 foreach_list_typed(nir_cf_node
, cf_node
, node
, cf_list
) {
208 switch (cf_node
->type
) {
209 case nir_cf_node_block
:
211 case nir_cf_node_if
: {
212 nir_if
*nif
= nir_cf_node_as_if(cf_node
);
213 progress
|= sanitize_cf_list(impl
, divergent
, &nif
->then_list
);
214 progress
|= sanitize_cf_list(impl
, divergent
, &nif
->else_list
);
215 progress
|= sanitize_if(impl
, divergent
, nif
);
218 case nir_cf_node_loop
: {
219 nir_loop
*loop
= nir_cf_node_as_loop(cf_node
);
220 progress
|= sanitize_cf_list(impl
, divergent
, &loop
->body
);
223 case nir_cf_node_function
:
224 unreachable("Invalid cf type");
231 RegClass
get_reg_class(isel_context
*ctx
, RegType type
, unsigned components
, unsigned bitsize
)
234 return RegClass(RegType::sgpr
, ctx
->program
->lane_mask
.size() * components
);
236 return RegClass::get(type
, components
* bitsize
/ 8u);
239 void init_context(isel_context
*ctx
, nir_shader
*shader
)
241 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
242 unsigned lane_mask_size
= ctx
->program
->lane_mask
.size();
244 ctx
->shader
= shader
;
245 ctx
->divergent_vals
= nir_divergence_analysis(shader
, nir_divergence_view_index_uniform
);
247 /* sanitize control flow */
248 nir_metadata_require(impl
, nir_metadata_dominance
);
249 sanitize_cf_list(impl
, ctx
->divergent_vals
, &impl
->body
);
250 nir_metadata_preserve(impl
, (nir_metadata
)~nir_metadata_block_index
);
252 /* we'll need this for isel */
253 nir_metadata_require(impl
, nir_metadata_block_index
);
255 if (!(ctx
->stage
& sw_gs_copy
) && ctx
->options
->dump_preoptir
) {
256 fprintf(stderr
, "NIR shader before instruction selection:\n");
257 nir_print_shader(shader
, stderr
);
260 std::unique_ptr
<Temp
[]> allocated
{new Temp
[impl
->ssa_alloc
]()};
262 unsigned spi_ps_inputs
= 0;
264 std::unique_ptr
<unsigned[]> nir_to_aco
{new unsigned[impl
->num_blocks
]()};
269 nir_foreach_block(block
, impl
) {
270 nir_foreach_instr(instr
, block
) {
271 switch(instr
->type
) {
272 case nir_instr_type_alu
: {
273 nir_alu_instr
*alu_instr
= nir_instr_as_alu(instr
);
274 RegType type
= RegType::sgpr
;
275 switch(alu_instr
->op
) {
297 case nir_op_fround_even
:
301 case nir_op_f2f16_rtz
:
302 case nir_op_f2f16_rtne
:
311 case nir_op_pack_half_2x16
:
312 case nir_op_unpack_half_2x16_split_x
:
313 case nir_op_unpack_half_2x16_split_y
:
316 case nir_op_fddx_fine
:
317 case nir_op_fddy_fine
:
318 case nir_op_fddx_coarse
:
319 case nir_op_fddy_coarse
:
320 case nir_op_fquantize2f16
:
322 case nir_op_frexp_sig
:
323 case nir_op_frexp_exp
:
324 case nir_op_cube_face_index
:
325 case nir_op_cube_face_coord
:
326 type
= RegType::vgpr
;
339 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
342 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
345 for (unsigned i
= 0; i
< nir_op_infos
[alu_instr
->op
].num_inputs
; i
++) {
346 if (allocated
[alu_instr
->src
[i
].src
.ssa
->index
].type() == RegType::vgpr
)
347 type
= RegType::vgpr
;
352 RegClass rc
= get_reg_class(ctx
, type
, alu_instr
->dest
.dest
.ssa
.num_components
, alu_instr
->dest
.dest
.ssa
.bit_size
);
353 allocated
[alu_instr
->dest
.dest
.ssa
.index
] = Temp(0, rc
);
356 case nir_instr_type_load_const
: {
357 unsigned num_components
= nir_instr_as_load_const(instr
)->def
.num_components
;
358 unsigned bit_size
= nir_instr_as_load_const(instr
)->def
.bit_size
;
359 RegClass rc
= get_reg_class(ctx
, RegType::sgpr
, num_components
, bit_size
);
360 allocated
[nir_instr_as_load_const(instr
)->def
.index
] = Temp(0, rc
);
363 case nir_instr_type_intrinsic
: {
364 nir_intrinsic_instr
*intrinsic
= nir_instr_as_intrinsic(instr
);
365 if (!nir_intrinsic_infos
[intrinsic
->intrinsic
].has_dest
)
367 RegType type
= RegType::sgpr
;
368 switch(intrinsic
->intrinsic
) {
369 case nir_intrinsic_load_push_constant
:
370 case nir_intrinsic_load_work_group_id
:
371 case nir_intrinsic_load_num_work_groups
:
372 case nir_intrinsic_load_subgroup_id
:
373 case nir_intrinsic_load_num_subgroups
:
374 case nir_intrinsic_load_first_vertex
:
375 case nir_intrinsic_load_base_instance
:
376 case nir_intrinsic_get_buffer_size
:
377 case nir_intrinsic_vote_all
:
378 case nir_intrinsic_vote_any
:
379 case nir_intrinsic_read_first_invocation
:
380 case nir_intrinsic_read_invocation
:
381 case nir_intrinsic_first_invocation
:
382 case nir_intrinsic_ballot
:
383 type
= RegType::sgpr
;
385 case nir_intrinsic_load_sample_id
:
386 case nir_intrinsic_load_sample_mask_in
:
387 case nir_intrinsic_load_input
:
388 case nir_intrinsic_load_output
:
389 case nir_intrinsic_load_input_vertex
:
390 case nir_intrinsic_load_per_vertex_input
:
391 case nir_intrinsic_load_per_vertex_output
:
392 case nir_intrinsic_load_vertex_id
:
393 case nir_intrinsic_load_vertex_id_zero_base
:
394 case nir_intrinsic_load_barycentric_sample
:
395 case nir_intrinsic_load_barycentric_pixel
:
396 case nir_intrinsic_load_barycentric_model
:
397 case nir_intrinsic_load_barycentric_centroid
:
398 case nir_intrinsic_load_barycentric_at_sample
:
399 case nir_intrinsic_load_barycentric_at_offset
:
400 case nir_intrinsic_load_interpolated_input
:
401 case nir_intrinsic_load_frag_coord
:
402 case nir_intrinsic_load_sample_pos
:
403 case nir_intrinsic_load_layer_id
:
404 case nir_intrinsic_load_local_invocation_id
:
405 case nir_intrinsic_load_local_invocation_index
:
406 case nir_intrinsic_load_subgroup_invocation
:
407 case nir_intrinsic_load_tess_coord
:
408 case nir_intrinsic_write_invocation_amd
:
409 case nir_intrinsic_mbcnt_amd
:
410 case nir_intrinsic_load_instance_id
:
411 case nir_intrinsic_ssbo_atomic_add
:
412 case nir_intrinsic_ssbo_atomic_imin
:
413 case nir_intrinsic_ssbo_atomic_umin
:
414 case nir_intrinsic_ssbo_atomic_imax
:
415 case nir_intrinsic_ssbo_atomic_umax
:
416 case nir_intrinsic_ssbo_atomic_and
:
417 case nir_intrinsic_ssbo_atomic_or
:
418 case nir_intrinsic_ssbo_atomic_xor
:
419 case nir_intrinsic_ssbo_atomic_exchange
:
420 case nir_intrinsic_ssbo_atomic_comp_swap
:
421 case nir_intrinsic_global_atomic_add
:
422 case nir_intrinsic_global_atomic_imin
:
423 case nir_intrinsic_global_atomic_umin
:
424 case nir_intrinsic_global_atomic_imax
:
425 case nir_intrinsic_global_atomic_umax
:
426 case nir_intrinsic_global_atomic_and
:
427 case nir_intrinsic_global_atomic_or
:
428 case nir_intrinsic_global_atomic_xor
:
429 case nir_intrinsic_global_atomic_exchange
:
430 case nir_intrinsic_global_atomic_comp_swap
:
431 case nir_intrinsic_image_deref_atomic_add
:
432 case nir_intrinsic_image_deref_atomic_umin
:
433 case nir_intrinsic_image_deref_atomic_imin
:
434 case nir_intrinsic_image_deref_atomic_umax
:
435 case nir_intrinsic_image_deref_atomic_imax
:
436 case nir_intrinsic_image_deref_atomic_and
:
437 case nir_intrinsic_image_deref_atomic_or
:
438 case nir_intrinsic_image_deref_atomic_xor
:
439 case nir_intrinsic_image_deref_atomic_exchange
:
440 case nir_intrinsic_image_deref_atomic_comp_swap
:
441 case nir_intrinsic_image_deref_size
:
442 case nir_intrinsic_shared_atomic_add
:
443 case nir_intrinsic_shared_atomic_imin
:
444 case nir_intrinsic_shared_atomic_umin
:
445 case nir_intrinsic_shared_atomic_imax
:
446 case nir_intrinsic_shared_atomic_umax
:
447 case nir_intrinsic_shared_atomic_and
:
448 case nir_intrinsic_shared_atomic_or
:
449 case nir_intrinsic_shared_atomic_xor
:
450 case nir_intrinsic_shared_atomic_exchange
:
451 case nir_intrinsic_shared_atomic_comp_swap
:
452 case nir_intrinsic_load_scratch
:
453 case nir_intrinsic_load_invocation_id
:
454 case nir_intrinsic_load_primitive_id
:
455 type
= RegType::vgpr
;
457 case nir_intrinsic_shuffle
:
458 case nir_intrinsic_quad_broadcast
:
459 case nir_intrinsic_quad_swap_horizontal
:
460 case nir_intrinsic_quad_swap_vertical
:
461 case nir_intrinsic_quad_swap_diagonal
:
462 case nir_intrinsic_quad_swizzle_amd
:
463 case nir_intrinsic_masked_swizzle_amd
:
464 case nir_intrinsic_inclusive_scan
:
465 case nir_intrinsic_exclusive_scan
:
466 case nir_intrinsic_reduce
:
467 case nir_intrinsic_load_ubo
:
468 case nir_intrinsic_load_ssbo
:
469 case nir_intrinsic_load_global
:
470 case nir_intrinsic_vulkan_resource_index
:
471 case nir_intrinsic_load_shared
:
472 type
= ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
474 case nir_intrinsic_load_view_index
:
475 type
= ctx
->stage
== fragment_fs
? RegType::vgpr
: RegType::sgpr
;
478 for (unsigned i
= 0; i
< nir_intrinsic_infos
[intrinsic
->intrinsic
].num_srcs
; i
++) {
479 if (allocated
[intrinsic
->src
[i
].ssa
->index
].type() == RegType::vgpr
)
480 type
= RegType::vgpr
;
484 RegClass rc
= get_reg_class(ctx
, type
, intrinsic
->dest
.ssa
.num_components
, intrinsic
->dest
.ssa
.bit_size
);
485 allocated
[intrinsic
->dest
.ssa
.index
] = Temp(0, rc
);
487 switch(intrinsic
->intrinsic
) {
488 case nir_intrinsic_load_barycentric_sample
:
489 case nir_intrinsic_load_barycentric_pixel
:
490 case nir_intrinsic_load_barycentric_centroid
:
491 case nir_intrinsic_load_barycentric_at_sample
:
492 case nir_intrinsic_load_barycentric_at_offset
: {
493 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(intrinsic
);
494 spi_ps_inputs
|= get_interp_input(intrinsic
->intrinsic
, mode
);
497 case nir_intrinsic_load_barycentric_model
:
498 spi_ps_inputs
|= S_0286CC_PERSP_PULL_MODEL_ENA(1);
500 case nir_intrinsic_load_front_face
:
501 spi_ps_inputs
|= S_0286CC_FRONT_FACE_ENA(1);
503 case nir_intrinsic_load_frag_coord
:
504 case nir_intrinsic_load_sample_pos
: {
505 uint8_t mask
= nir_ssa_def_components_read(&intrinsic
->dest
.ssa
);
506 for (unsigned i
= 0; i
< 4; i
++) {
508 spi_ps_inputs
|= S_0286CC_POS_X_FLOAT_ENA(1) << i
;
513 case nir_intrinsic_load_sample_id
:
514 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
516 case nir_intrinsic_load_sample_mask_in
:
517 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
518 spi_ps_inputs
|= S_0286CC_SAMPLE_COVERAGE_ENA(1);
525 case nir_instr_type_tex
: {
526 nir_tex_instr
* tex
= nir_instr_as_tex(instr
);
527 unsigned size
= tex
->dest
.ssa
.num_components
;
529 if (tex
->dest
.ssa
.bit_size
== 64)
531 if (tex
->op
== nir_texop_texture_samples
)
532 assert(!ctx
->divergent_vals
[tex
->dest
.ssa
.index
]);
533 if (ctx
->divergent_vals
[tex
->dest
.ssa
.index
])
534 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::vgpr
, size
));
536 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
539 case nir_instr_type_parallel_copy
: {
540 nir_foreach_parallel_copy_entry(entry
, nir_instr_as_parallel_copy(instr
)) {
541 allocated
[entry
->dest
.ssa
.index
] = allocated
[entry
->src
.ssa
->index
];
545 case nir_instr_type_ssa_undef
: {
546 unsigned num_components
= nir_instr_as_ssa_undef(instr
)->def
.num_components
;
547 unsigned bit_size
= nir_instr_as_ssa_undef(instr
)->def
.bit_size
;
548 RegClass rc
= get_reg_class(ctx
, RegType::sgpr
, num_components
, bit_size
);
549 allocated
[nir_instr_as_ssa_undef(instr
)->def
.index
] = Temp(0, rc
);
552 case nir_instr_type_phi
: {
553 nir_phi_instr
* phi
= nir_instr_as_phi(instr
);
555 unsigned size
= phi
->dest
.ssa
.num_components
;
557 if (phi
->dest
.ssa
.bit_size
== 1) {
558 assert(size
== 1 && "multiple components not yet supported on boolean phis.");
559 type
= RegType::sgpr
;
560 size
*= lane_mask_size
;
561 allocated
[phi
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
565 if (ctx
->divergent_vals
[phi
->dest
.ssa
.index
]) {
566 type
= RegType::vgpr
;
568 type
= RegType::sgpr
;
569 nir_foreach_phi_src (src
, phi
) {
570 if (allocated
[src
->src
.ssa
->index
].type() == RegType::vgpr
)
571 type
= RegType::vgpr
;
572 if (allocated
[src
->src
.ssa
->index
].type() == RegType::none
)
577 RegClass rc
= get_reg_class(ctx
, type
, phi
->dest
.ssa
.num_components
, phi
->dest
.ssa
.bit_size
);
578 if (rc
!= allocated
[phi
->dest
.ssa
.index
].regClass()) {
581 nir_foreach_phi_src(src
, phi
)
582 assert(allocated
[src
->src
.ssa
->index
].size() == rc
.size());
584 allocated
[phi
->dest
.ssa
.index
] = Temp(0, rc
);
594 if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_inputs
)) {
595 /* If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be enabled too */
596 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
599 if (!(spi_ps_inputs
& 0x7F)) {
600 /* At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled */
601 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
604 ctx
->program
->config
->spi_ps_input_ena
= spi_ps_inputs
;
605 ctx
->program
->config
->spi_ps_input_addr
= spi_ps_inputs
;
607 for (unsigned i
= 0; i
< impl
->ssa_alloc
; i
++)
608 allocated
[i
] = Temp(ctx
->program
->allocateId(), allocated
[i
].regClass());
610 ctx
->allocated
.reset(allocated
.release());
611 ctx
->cf_info
.nir_to_aco
.reset(nir_to_aco
.release());
614 Pseudo_instruction
*add_startpgm(struct isel_context
*ctx
)
616 unsigned arg_count
= ctx
->args
->ac
.arg_count
;
617 if (ctx
->stage
== fragment_fs
) {
618 /* LLVM optimizes away unused FS inputs and computes spi_ps_input_addr
619 * itself and then communicates the results back via the ELF binary.
620 * Mirror what LLVM does by re-mapping the VGPR arguments here.
622 * TODO: If we made the FS input scanning code into a separate pass that
623 * could run before argument setup, then this wouldn't be necessary
626 struct ac_shader_args
*args
= &ctx
->args
->ac
;
628 for (unsigned i
= 0, vgpr_arg
= 0, vgpr_reg
= 0; i
< args
->arg_count
; i
++) {
629 if (args
->args
[i
].file
!= AC_ARG_VGPR
) {
634 if (!(ctx
->program
->config
->spi_ps_input_addr
& (1 << vgpr_arg
))) {
635 args
->args
[i
].skip
= true;
637 args
->args
[i
].offset
= vgpr_reg
;
638 vgpr_reg
+= args
->args
[i
].size
;
645 aco_ptr
<Pseudo_instruction
> startpgm
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_startpgm
, Format::PSEUDO
, 0, arg_count
+ 1)};
646 for (unsigned i
= 0, arg
= 0; i
< ctx
->args
->ac
.arg_count
; i
++) {
647 if (ctx
->args
->ac
.args
[i
].skip
)
650 enum ac_arg_regfile file
= ctx
->args
->ac
.args
[i
].file
;
651 unsigned size
= ctx
->args
->ac
.args
[i
].size
;
652 unsigned reg
= ctx
->args
->ac
.args
[i
].offset
;
653 RegClass type
= RegClass(file
== AC_ARG_SGPR
? RegType::sgpr
: RegType::vgpr
, size
);
654 Temp dst
= Temp
{ctx
->program
->allocateId(), type
};
655 ctx
->arg_temps
[i
] = dst
;
656 startpgm
->definitions
[arg
] = Definition(dst
);
657 startpgm
->definitions
[arg
].setFixed(PhysReg
{file
== AC_ARG_SGPR
? reg
: reg
+ 256});
660 startpgm
->definitions
[arg_count
] = Definition
{ctx
->program
->allocateId(), exec
, ctx
->program
->lane_mask
};
661 Pseudo_instruction
*instr
= startpgm
.get();
662 ctx
->block
->instructions
.push_back(std::move(startpgm
));
664 /* Stash these in the program so that they can be accessed later when
667 ctx
->program
->private_segment_buffer
= get_arg(ctx
, ctx
->args
->ring_offsets
);
668 ctx
->program
->scratch_offset
= get_arg(ctx
, ctx
->args
->scratch_offset
);
674 type_size(const struct glsl_type
*type
, bool bindless
)
676 // TODO: don't we need type->std430_base_alignment() here?
677 return glsl_count_attribute_slots(type
, false);
681 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
683 assert(glsl_type_is_vector_or_scalar(type
));
685 uint32_t comp_size
= glsl_type_is_boolean(type
)
686 ? 4 : glsl_get_bit_size(type
) / 8;
687 unsigned length
= glsl_get_vector_elements(type
);
688 *size
= comp_size
* length
,
693 mem_vectorize_callback(unsigned align
, unsigned bit_size
,
694 unsigned num_components
, unsigned high_offset
,
695 nir_intrinsic_instr
*low
, nir_intrinsic_instr
*high
)
697 if ((bit_size
!= 32 && bit_size
!= 64) || num_components
> 4)
700 /* >128 bit loads are split except with SMEM */
701 if (bit_size
* num_components
> 128)
704 switch (low
->intrinsic
) {
705 case nir_intrinsic_load_global
:
706 case nir_intrinsic_store_global
:
707 return align
% 4 == 0;
708 case nir_intrinsic_store_ssbo
:
709 if (low
->src
[0].ssa
->bit_size
< 32 || high
->src
[0].ssa
->bit_size
< 32)
711 return align
% 4 == 0;
712 case nir_intrinsic_load_ssbo
:
713 if (low
->dest
.ssa
.bit_size
< 32 || high
->dest
.ssa
.bit_size
< 32)
715 case nir_intrinsic_load_ubo
:
716 case nir_intrinsic_load_push_constant
:
717 return align
% 4 == 0;
718 case nir_intrinsic_load_deref
:
719 case nir_intrinsic_store_deref
:
720 assert(nir_src_as_deref(low
->src
[0])->mode
== nir_var_mem_shared
);
722 case nir_intrinsic_load_shared
:
723 case nir_intrinsic_store_shared
:
724 if (bit_size
* num_components
> 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
725 return align
% 16 == 0;
727 return align
% 4 == 0;
735 setup_vs_output_info(isel_context
*ctx
, nir_shader
*nir
,
736 bool export_prim_id
, bool export_clip_dists
,
737 radv_vs_output_info
*outinfo
)
739 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
740 sizeof(outinfo
->vs_output_param_offset
));
742 outinfo
->param_exports
= 0;
743 int pos_written
= 0x1;
744 if (outinfo
->writes_pointsize
|| outinfo
->writes_viewport_index
|| outinfo
->writes_layer
)
745 pos_written
|= 1 << 1;
747 uint64_t mask
= ctx
->output_masks
[nir
->info
.stage
];
749 int idx
= u_bit_scan64(&mask
);
750 if (idx
>= VARYING_SLOT_VAR0
|| idx
== VARYING_SLOT_LAYER
||
751 idx
== VARYING_SLOT_PRIMITIVE_ID
|| idx
== VARYING_SLOT_VIEWPORT
||
752 ((idx
== VARYING_SLOT_CLIP_DIST0
|| idx
== VARYING_SLOT_CLIP_DIST1
) && export_clip_dists
)) {
753 if (outinfo
->vs_output_param_offset
[idx
] == AC_EXP_PARAM_UNDEFINED
)
754 outinfo
->vs_output_param_offset
[idx
] = outinfo
->param_exports
++;
757 if (outinfo
->writes_layer
&&
758 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] == AC_EXP_PARAM_UNDEFINED
) {
759 /* when ctx->options->key.has_multiview_view_index = true, the layer
760 * variable isn't declared in NIR and it's isel's job to get the layer */
761 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = outinfo
->param_exports
++;
764 if (export_prim_id
) {
765 assert(outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] == AC_EXP_PARAM_UNDEFINED
);
766 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = outinfo
->param_exports
++;
769 ctx
->export_clip_dists
= export_clip_dists
;
770 ctx
->num_clip_distances
= util_bitcount(outinfo
->clip_dist_mask
);
771 ctx
->num_cull_distances
= util_bitcount(outinfo
->cull_dist_mask
);
773 assert(ctx
->num_clip_distances
+ ctx
->num_cull_distances
<= 8);
775 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
776 pos_written
|= 1 << 2;
777 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
778 pos_written
|= 1 << 3;
780 outinfo
->pos_exports
= util_bitcount(pos_written
);
784 setup_vs_variables(isel_context
*ctx
, nir_shader
*nir
)
786 nir_foreach_variable(variable
, &nir
->inputs
)
788 variable
->data
.driver_location
= variable
->data
.location
* 4;
790 nir_foreach_variable(variable
, &nir
->outputs
)
792 if (ctx
->stage
== vertex_geometry_gs
)
793 variable
->data
.driver_location
= util_bitcount64(ctx
->output_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
794 else if (ctx
->stage
== vertex_es
||
795 ctx
->stage
== vertex_ls
||
796 ctx
->stage
== vertex_tess_control_hs
)
797 // TODO: make this more compact
798 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
799 else if (ctx
->stage
== vertex_vs
|| ctx
->stage
== ngg_vertex_gs
)
800 variable
->data
.driver_location
= variable
->data
.location
* 4;
802 unreachable("Unsupported VS stage");
804 assert(variable
->data
.location
>= 0 && variable
->data
.location
<= UINT8_MAX
);
805 ctx
->output_drv_loc_to_var_slot
[MESA_SHADER_VERTEX
][variable
->data
.driver_location
/ 4] = variable
->data
.location
;
808 if (ctx
->stage
== vertex_vs
|| ctx
->stage
== ngg_vertex_gs
) {
809 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
810 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
811 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
812 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== vertex_es
) {
813 /* TODO: radv_nir_shader_info_pass() already sets this but it's larger
814 * than it needs to be in order to set it better, we have to improve
815 * radv_nir_shader_info_pass() because gfx9_get_gs_info() uses
816 * esgs_itemsize and has to be done before compilation
818 /* radv_es_output_info *outinfo = &ctx->program->info->vs.es_info;
819 outinfo->esgs_itemsize = util_bitcount64(ctx->output_masks[nir->info.stage]) * 16u; */
820 } else if (ctx
->stage
== vertex_ls
) {
821 ctx
->tcs_num_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
824 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
825 /* We need to store the primitive IDs in LDS */
826 unsigned lds_size
= ctx
->program
->info
->ngg_info
.esgs_ring_size
;
827 ctx
->program
->config
->lds_size
= (lds_size
+ ctx
->program
->lds_alloc_granule
- 1) /
828 ctx
->program
->lds_alloc_granule
;
832 void setup_gs_variables(isel_context
*ctx
, nir_shader
*nir
)
834 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
835 nir_foreach_variable(variable
, &nir
->inputs
) {
836 variable
->data
.driver_location
= util_bitcount64(ctx
->input_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
838 ctx
->program
->config
->lds_size
= ctx
->program
->info
->gs_ring_info
.lds_size
; /* Already in units of the alloc granularity */
839 } else if (ctx
->stage
== geometry_gs
) {
840 //TODO: make this more compact
841 nir_foreach_variable(variable
, &nir
->inputs
) {
842 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
)variable
->data
.location
) * 4;
845 unreachable("Unsupported GS stage.");
848 nir_foreach_variable(variable
, &nir
->outputs
) {
849 variable
->data
.driver_location
= variable
->data
.location
* 4;
852 if (ctx
->stage
== vertex_geometry_gs
)
853 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_VERTEX
;
854 else if (ctx
->stage
== tess_eval_geometry_gs
)
855 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_TESS_EVAL
;
859 setup_tcs_info(isel_context
*ctx
, nir_shader
*nir
)
861 /* When the number of TCS input and output vertices are the same (typically 3):
862 * - There is an equal amount of LS and HS invocations
863 * - In case of merged LSHS shaders, the LS and HS halves of the shader
864 * always process the exact same vertex. We can use this knowledge to optimize them.
867 ctx
->stage
== vertex_tess_control_hs
&&
868 ctx
->args
->options
->key
.tcs
.input_vertices
== nir
->info
.tess
.tcs_vertices_out
;
870 if (ctx
->stage
== tess_control_hs
) {
871 ctx
->tcs_num_inputs
= ctx
->args
->options
->key
.tcs
.num_inputs
;
872 } else if (ctx
->stage
== vertex_tess_control_hs
) {
873 ctx
->tcs_num_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
875 if (ctx
->tcs_in_out_eq
) {
876 ctx
->tcs_temp_only_inputs
= ~nir
->info
.tess
.tcs_cross_invocation_inputs_read
&
877 ~nir
->info
.inputs_read_indirectly
&
878 nir
->info
.inputs_read
;
881 unreachable("Unsupported TCS shader stage");
884 ctx
->tcs_num_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
885 ctx
->tcs_num_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
887 ctx
->tcs_num_patches
= get_tcs_num_patches(
888 ctx
->args
->options
->key
.tcs
.input_vertices
,
889 nir
->info
.tess
.tcs_vertices_out
,
891 ctx
->tcs_num_outputs
,
892 ctx
->tcs_num_patch_outputs
,
893 ctx
->args
->options
->tess_offchip_block_dw_size
,
894 ctx
->args
->options
->chip_class
,
895 ctx
->args
->options
->family
);
896 unsigned lds_size
= calculate_tess_lds_size(
897 ctx
->args
->options
->key
.tcs
.input_vertices
,
898 nir
->info
.tess
.tcs_vertices_out
,
900 ctx
->tcs_num_patches
,
901 ctx
->tcs_num_outputs
,
902 ctx
->tcs_num_patch_outputs
);
904 ctx
->args
->shader_info
->tcs
.num_patches
= ctx
->tcs_num_patches
;
905 ctx
->args
->shader_info
->tcs
.lds_size
= lds_size
;
906 ctx
->program
->config
->lds_size
= (lds_size
+ ctx
->program
->lds_alloc_granule
- 1) /
907 ctx
->program
->lds_alloc_granule
;
911 setup_tcs_variables(isel_context
*ctx
, nir_shader
*nir
)
913 nir_foreach_variable(variable
, &nir
->inputs
) {
914 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
917 nir_foreach_variable(variable
, &nir
->outputs
) {
918 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
919 assert(variable
->data
.location
>= 0 && variable
->data
.location
<= UINT8_MAX
);
921 if (variable
->data
.patch
)
922 ctx
->output_tcs_patch_drv_loc_to_var_slot
[variable
->data
.driver_location
/ 4] = variable
->data
.location
;
924 ctx
->output_drv_loc_to_var_slot
[MESA_SHADER_TESS_CTRL
][variable
->data
.driver_location
/ 4] = variable
->data
.location
;
927 ctx
->tcs_tess_lvl_out_loc
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
) * 16u;
928 ctx
->tcs_tess_lvl_in_loc
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
) * 16u;
932 setup_tes_variables(isel_context
*ctx
, nir_shader
*nir
)
934 ctx
->tcs_num_patches
= ctx
->args
->options
->key
.tes
.num_patches
;
935 ctx
->tcs_num_outputs
= ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
937 nir_foreach_variable(variable
, &nir
->inputs
) {
938 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
941 nir_foreach_variable(variable
, &nir
->outputs
) {
942 if (ctx
->stage
== tess_eval_vs
|| ctx
->stage
== ngg_tess_eval_gs
)
943 variable
->data
.driver_location
= variable
->data
.location
* 4;
944 else if (ctx
->stage
== tess_eval_es
)
945 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
946 else if (ctx
->stage
== tess_eval_geometry_gs
)
947 variable
->data
.driver_location
= util_bitcount64(ctx
->output_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
949 unreachable("Unsupported TES shader stage");
952 if (ctx
->stage
== tess_eval_vs
|| ctx
->stage
== ngg_tess_eval_gs
) {
953 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->tes
.outinfo
;
954 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
955 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
960 setup_variables(isel_context
*ctx
, nir_shader
*nir
)
962 switch (nir
->info
.stage
) {
963 case MESA_SHADER_FRAGMENT
: {
964 nir_foreach_variable(variable
, &nir
->outputs
)
966 int idx
= variable
->data
.location
+ variable
->data
.index
;
967 variable
->data
.driver_location
= idx
* 4;
971 case MESA_SHADER_COMPUTE
: {
972 ctx
->program
->config
->lds_size
= (nir
->info
.cs
.shared_size
+ ctx
->program
->lds_alloc_granule
- 1) /
973 ctx
->program
->lds_alloc_granule
;
976 case MESA_SHADER_VERTEX
: {
977 setup_vs_variables(ctx
, nir
);
980 case MESA_SHADER_GEOMETRY
: {
981 setup_gs_variables(ctx
, nir
);
984 case MESA_SHADER_TESS_CTRL
: {
985 setup_tcs_variables(ctx
, nir
);
988 case MESA_SHADER_TESS_EVAL
: {
989 setup_tes_variables(ctx
, nir
);
993 unreachable("Unhandled shader stage.");
998 get_io_masks(isel_context
*ctx
, unsigned shader_count
, struct nir_shader
*const *shaders
)
1000 for (unsigned i
= 0; i
< shader_count
; i
++) {
1001 nir_shader
*nir
= shaders
[i
];
1002 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
1005 uint64_t output_mask
= 0;
1006 nir_foreach_variable(variable
, &nir
->outputs
) {
1007 const glsl_type
*type
= variable
->type
;
1008 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
1009 type
= type
->fields
.array
;
1010 unsigned slots
= type
->count_attribute_slots(false);
1011 if (variable
->data
.compact
) {
1012 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
1013 slots
= (component_count
+ 3) / 4;
1015 output_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
1018 uint64_t input_mask
= 0;
1019 nir_foreach_variable(variable
, &nir
->inputs
) {
1020 const glsl_type
*type
= variable
->type
;
1021 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
1022 type
= type
->fields
.array
;
1023 unsigned slots
= type
->count_attribute_slots(false);
1024 if (variable
->data
.compact
) {
1025 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
1026 slots
= (component_count
+ 3) / 4;
1028 input_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
1031 ctx
->output_masks
[nir
->info
.stage
] |= output_mask
;
1032 if (i
+ 1 < shader_count
)
1033 ctx
->input_masks
[shaders
[i
+ 1]->info
.stage
] |= output_mask
;
1035 ctx
->input_masks
[nir
->info
.stage
] |= input_mask
;
1037 ctx
->output_masks
[shaders
[i
- 1]->info
.stage
] |= input_mask
;
1042 lower_bit_size_callback(const nir_alu_instr
*alu
, void *_
)
1044 if (nir_op_is_vec(alu
->op
))
1047 unsigned bit_size
= alu
->dest
.dest
.ssa
.bit_size
;
1048 if (nir_alu_instr_is_comparison(alu
))
1049 bit_size
= nir_src_bit_size(alu
->src
[0].src
);
1051 if (bit_size
>= 32 || bit_size
== 1)
1054 if (alu
->op
== nir_op_bcsel
)
1057 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1059 if (info
->is_conversion
)
1062 bool is_integer
= info
->output_type
& (nir_type_uint
| nir_type_int
);
1063 for (unsigned i
= 0; is_integer
&& (i
< info
->num_inputs
); i
++)
1064 is_integer
= info
->input_types
[i
] & (nir_type_uint
| nir_type_int
);
1066 return is_integer
? 32 : 0;
1070 setup_nir(isel_context
*ctx
, nir_shader
*nir
)
1072 Program
*program
= ctx
->program
;
1074 /* align and copy constant data */
1075 while (program
->constant_data
.size() % 4u)
1076 program
->constant_data
.push_back(0);
1077 ctx
->constant_data_offset
= program
->constant_data
.size();
1078 program
->constant_data
.insert(program
->constant_data
.end(),
1079 (uint8_t*)nir
->constant_data
,
1080 (uint8_t*)nir
->constant_data
+ nir
->constant_data_size
);
1082 /* the variable setup has to be done before lower_io / CSE */
1083 setup_variables(ctx
, nir
);
1085 /* optimize and lower memory operations */
1086 if (nir_lower_explicit_io(nir
, nir_var_mem_global
, nir_address_format_64bit_global
)) {
1087 nir_opt_constant_folding(nir
);
1091 bool lower_to_scalar
= false;
1092 bool lower_pack
= false;
1093 if (nir_opt_load_store_vectorize(nir
,
1094 (nir_variable_mode
)(nir_var_mem_ssbo
| nir_var_mem_ubo
|
1095 nir_var_mem_push_const
| nir_var_mem_shared
|
1096 nir_var_mem_global
),
1097 mem_vectorize_callback
)) {
1098 lower_to_scalar
= true;
1101 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
1102 nir_lower_io(nir
, (nir_variable_mode
)(nir_var_shader_in
| nir_var_shader_out
), type_size
, (nir_lower_io_options
)0);
1104 if (lower_to_scalar
)
1105 nir_lower_alu_to_scalar(nir
, NULL
, NULL
);
1107 nir_lower_pack(nir
);
1109 /* lower ALU operations */
1110 // TODO: implement logic64 in aco, it's more effective for sgprs
1111 nir_lower_int64(nir
, nir
->options
->lower_int64_options
);
1113 if (nir_lower_bit_size(nir
, lower_bit_size_callback
, NULL
))
1114 nir_copy_prop(nir
); /* allow nir_opt_idiv_const() to optimize lowered divisions */
1116 nir_opt_idiv_const(nir
, 32);
1117 nir_lower_idiv(nir
, nir_lower_idiv_precise
);
1119 /* optimize the lowered ALU operations */
1120 bool more_algebraic
= true;
1121 while (more_algebraic
) {
1122 more_algebraic
= false;
1123 NIR_PASS_V(nir
, nir_copy_prop
);
1124 NIR_PASS_V(nir
, nir_opt_dce
);
1125 NIR_PASS_V(nir
, nir_opt_constant_folding
);
1126 NIR_PASS(more_algebraic
, nir
, nir_opt_algebraic
);
1129 /* Do late algebraic optimization to turn add(a, neg(b)) back into
1130 * subs, then the mandatory cleanup after algebraic. Note that it may
1131 * produce fnegs, and if so then we need to keep running to squash
1134 bool more_late_algebraic
= true;
1135 while (more_late_algebraic
) {
1136 more_late_algebraic
= false;
1137 NIR_PASS(more_late_algebraic
, nir
, nir_opt_algebraic_late
);
1138 NIR_PASS_V(nir
, nir_opt_constant_folding
);
1139 NIR_PASS_V(nir
, nir_copy_prop
);
1140 NIR_PASS_V(nir
, nir_opt_dce
);
1141 NIR_PASS_V(nir
, nir_opt_cse
);
1144 /* cleanup passes */
1145 nir_lower_load_const_to_scalar(nir
);
1146 nir_opt_shrink_load(nir
);
1147 nir_move_options move_opts
= (nir_move_options
)(
1148 nir_move_const_undef
| nir_move_load_ubo
| nir_move_load_input
|
1149 nir_move_comparisons
| nir_move_copies
);
1150 nir_opt_sink(nir
, move_opts
);
1151 nir_opt_move(nir
, move_opts
);
1152 nir_convert_to_lcssa(nir
, true, false);
1153 nir_lower_phis_to_scalar(nir
);
1155 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
1156 nir_index_ssa_defs(func
);
1160 setup_xnack(Program
*program
)
1162 switch (program
->family
) {
1170 program
->xnack_enabled
= true;
1178 setup_isel_context(Program
* program
,
1179 unsigned shader_count
,
1180 struct nir_shader
*const *shaders
,
1181 ac_shader_config
* config
,
1182 struct radv_shader_args
*args
,
1183 bool is_gs_copy_shader
)
1186 for (unsigned i
= 0; i
< shader_count
; i
++) {
1187 switch (shaders
[i
]->info
.stage
) {
1188 case MESA_SHADER_VERTEX
:
1189 program
->stage
|= sw_vs
;
1191 case MESA_SHADER_TESS_CTRL
:
1192 program
->stage
|= sw_tcs
;
1194 case MESA_SHADER_TESS_EVAL
:
1195 program
->stage
|= sw_tes
;
1197 case MESA_SHADER_GEOMETRY
:
1198 program
->stage
|= is_gs_copy_shader
? sw_gs_copy
: sw_gs
;
1200 case MESA_SHADER_FRAGMENT
:
1201 program
->stage
|= sw_fs
;
1203 case MESA_SHADER_COMPUTE
:
1204 program
->stage
|= sw_cs
;
1207 unreachable("Shader stage not implemented");
1210 bool gfx9_plus
= args
->options
->chip_class
>= GFX9
;
1211 bool ngg
= args
->shader_info
->is_ngg
&& args
->options
->chip_class
>= GFX10
;
1212 if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_es
&& !ngg
)
1213 program
->stage
|= hw_es
;
1214 else if (program
->stage
== sw_vs
&& !args
->shader_info
->vs
.as_ls
&& !ngg
)
1215 program
->stage
|= hw_vs
;
1216 else if (program
->stage
== sw_vs
&& ngg
)
1217 program
->stage
|= hw_ngg_gs
; /* GFX10/NGG: VS without GS uses the HW GS stage */
1218 else if (program
->stage
== sw_gs
)
1219 program
->stage
|= hw_gs
;
1220 else if (program
->stage
== sw_fs
)
1221 program
->stage
|= hw_fs
;
1222 else if (program
->stage
== sw_cs
)
1223 program
->stage
|= hw_cs
;
1224 else if (program
->stage
== sw_gs_copy
)
1225 program
->stage
|= hw_vs
;
1226 else if (program
->stage
== (sw_vs
| sw_gs
) && gfx9_plus
&& !ngg
)
1227 program
->stage
|= hw_gs
;
1228 else if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_ls
)
1229 program
->stage
|= hw_ls
; /* GFX6-8: VS is a Local Shader, when tessellation is used */
1230 else if (program
->stage
== sw_tcs
)
1231 program
->stage
|= hw_hs
; /* GFX6-8: TCS is a Hull Shader */
1232 else if (program
->stage
== (sw_vs
| sw_tcs
))
1233 program
->stage
|= hw_hs
; /* GFX9-10: VS+TCS merged into a Hull Shader */
1234 else if (program
->stage
== sw_tes
&& !args
->shader_info
->tes
.as_es
&& !ngg
)
1235 program
->stage
|= hw_vs
; /* GFX6-9: TES without GS uses the HW VS stage (and GFX10/legacy) */
1236 else if (program
->stage
== sw_tes
&& !args
->shader_info
->tes
.as_es
&& ngg
)
1237 program
->stage
|= hw_ngg_gs
; /* GFX10/NGG: TES without GS uses the HW GS stage */
1238 else if (program
->stage
== sw_tes
&& args
->shader_info
->tes
.as_es
&& !ngg
)
1239 program
->stage
|= hw_es
; /* GFX6-8: TES is an Export Shader */
1240 else if (program
->stage
== (sw_tes
| sw_gs
) && gfx9_plus
&& !ngg
)
1241 program
->stage
|= hw_gs
; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */
1243 unreachable("Shader stage not implemented");
1245 program
->config
= config
;
1246 program
->info
= args
->shader_info
;
1247 program
->chip_class
= args
->options
->chip_class
;
1248 program
->family
= args
->options
->family
;
1249 program
->wave_size
= args
->shader_info
->wave_size
;
1250 program
->lane_mask
= program
->wave_size
== 32 ? s1
: s2
;
1252 program
->lds_alloc_granule
= args
->options
->chip_class
>= GFX7
? 512 : 256;
1253 program
->lds_limit
= args
->options
->chip_class
>= GFX7
? 65536 : 32768;
1254 /* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
1255 program
->has_16bank_lds
= args
->options
->family
== CHIP_KABINI
|| args
->options
->family
== CHIP_STONEY
;
1257 program
->vgpr_limit
= 256;
1258 program
->vgpr_alloc_granule
= 3;
1260 if (args
->options
->chip_class
>= GFX10
) {
1261 program
->physical_sgprs
= 2560; /* doesn't matter as long as it's at least 128 * 20 */
1262 program
->sgpr_alloc_granule
= 127;
1263 program
->sgpr_limit
= 106;
1264 program
->vgpr_alloc_granule
= program
->wave_size
== 32 ? 7 : 3;
1265 } else if (program
->chip_class
>= GFX8
) {
1266 program
->physical_sgprs
= 800;
1267 program
->sgpr_alloc_granule
= 15;
1268 if (args
->options
->family
== CHIP_TONGA
|| args
->options
->family
== CHIP_ICELAND
)
1269 program
->sgpr_limit
= 94; /* workaround hardware bug */
1271 program
->sgpr_limit
= 102;
1273 program
->physical_sgprs
= 512;
1274 program
->sgpr_alloc_granule
= 7;
1275 program
->sgpr_limit
= 104;
1278 isel_context ctx
= {};
1279 ctx
.program
= program
;
1281 ctx
.options
= args
->options
;
1282 ctx
.stage
= program
->stage
;
1284 /* TODO: Check if we need to adjust min_waves for unknown workgroup sizes. */
1285 if (program
->stage
& (hw_vs
| hw_fs
)) {
1286 /* PS and legacy VS have separate waves, no workgroups */
1287 program
->workgroup_size
= program
->wave_size
;
1288 } else if (program
->stage
== compute_cs
) {
1289 /* CS sets the workgroup size explicitly */
1290 unsigned* bsize
= program
->info
->cs
.block_size
;
1291 program
->workgroup_size
= bsize
[0] * bsize
[1] * bsize
[2];
1292 } else if ((program
->stage
& hw_es
) || program
->stage
== geometry_gs
) {
1293 /* Unmerged ESGS operate in workgroups if on-chip GS (LDS rings) are enabled on GFX7-8 (not implemented in Mesa) */
1294 program
->workgroup_size
= program
->wave_size
;
1295 } else if (program
->stage
& hw_gs
) {
1296 /* If on-chip GS (LDS rings) are enabled on GFX9 or later, merged GS operates in workgroups */
1297 assert(program
->chip_class
>= GFX9
);
1298 uint32_t es_verts_per_subgrp
= G_028A44_ES_VERTS_PER_SUBGRP(program
->info
->gs_ring_info
.vgt_gs_onchip_cntl
);
1299 uint32_t gs_instr_prims_in_subgrp
= G_028A44_GS_INST_PRIMS_IN_SUBGRP(program
->info
->gs_ring_info
.vgt_gs_onchip_cntl
);
1300 uint32_t workgroup_size
= MAX2(es_verts_per_subgrp
, gs_instr_prims_in_subgrp
);
1301 program
->workgroup_size
= MAX2(MIN2(workgroup_size
, 256), 1);
1302 } else if (program
->stage
== vertex_ls
) {
1303 /* Unmerged LS operates in workgroups */
1304 program
->workgroup_size
= UINT_MAX
; /* TODO: probably tcs_num_patches * tcs_vertices_in, but those are not plumbed to ACO for LS */
1305 } else if (program
->stage
== tess_control_hs
) {
1306 /* Unmerged HS operates in workgroups, size is determined by the output vertices */
1307 setup_tcs_info(&ctx
, shaders
[0]);
1308 program
->workgroup_size
= ctx
.tcs_num_patches
* shaders
[0]->info
.tess
.tcs_vertices_out
;
1309 } else if (program
->stage
== vertex_tess_control_hs
) {
1310 /* Merged LSHS operates in workgroups, but can still have a different number of LS and HS invocations */
1311 setup_tcs_info(&ctx
, shaders
[1]);
1312 program
->workgroup_size
= ctx
.tcs_num_patches
* MAX2(shaders
[1]->info
.tess
.tcs_vertices_out
, ctx
.args
->options
->key
.tcs
.input_vertices
);
1313 } else if (program
->stage
& hw_ngg_gs
) {
1314 /* TODO: Calculate workgroup size of NGG shaders. */
1315 program
->workgroup_size
= UINT_MAX
;
1317 unreachable("Unsupported shader stage.");
1320 calc_min_waves(program
);
1321 program
->vgpr_limit
= get_addr_vgpr_from_waves(program
, program
->min_waves
);
1322 program
->sgpr_limit
= get_addr_sgpr_from_waves(program
, program
->min_waves
);
1324 get_io_masks(&ctx
, shader_count
, shaders
);
1326 unsigned scratch_size
= 0;
1327 if (program
->stage
== gs_copy_vs
) {
1328 assert(shader_count
== 1);
1329 setup_vs_output_info(&ctx
, shaders
[0], false, true, &args
->shader_info
->vs
.outinfo
);
1331 for (unsigned i
= 0; i
< shader_count
; i
++) {
1332 nir_shader
*nir
= shaders
[i
];
1333 setup_nir(&ctx
, nir
);
1336 for (unsigned i
= 0; i
< shader_count
; i
++)
1337 scratch_size
= std::max(scratch_size
, shaders
[i
]->scratch_size
);
1340 ctx
.program
->config
->scratch_bytes_per_wave
= align(scratch_size
* ctx
.program
->wave_size
, 1024);
1342 ctx
.block
= ctx
.program
->create_and_insert_block();
1343 ctx
.block
->loop_nest_depth
= 0;
1344 ctx
.block
->kind
= block_kind_top_level
;
1346 setup_xnack(program
);