2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <unordered_map>
29 #include "vulkan/radv_shader.h"
30 #include "vulkan/radv_descriptor_set.h"
31 #include "vulkan/radv_shader_args.h"
33 #include "ac_exp_param.h"
34 #include "ac_shader_util.h"
36 #include "util/u_math.h"
38 #define MAX_INLINE_PUSH_CONSTS 8
42 struct ge_output_state
{
43 uint8_t mask
[VARYING_SLOT_VAR31
+ 1];
44 Temp outputs
[VARYING_SLOT_VAR31
+ 1][4];
48 const struct radv_nir_compiler_options
*options
;
49 struct radv_shader_args
*args
;
52 uint32_t constant_data_offset
;
55 std::unique_ptr
<Temp
[]> allocated
;
56 std::unordered_map
<unsigned, std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
>> allocated_vec
;
57 Stage stage
; /* Stage */
58 bool has_gfx10_wave64_bpermute
= false;
61 uint16_t loop_nest_depth
= 0;
65 bool has_divergent_continue
= false;
66 bool has_divergent_branch
= false;
69 bool is_divergent
= false;
71 bool exec_potentially_empty
= false;
72 std::unique_ptr
<unsigned[]> nir_to_aco
; /* NIR block index to ACO block index */
75 Temp arg_temps
[AC_MAX_ARGS
];
78 Temp persp_centroid
, linear_centroid
;
83 /* gathered information */
84 uint64_t input_masks
[MESA_SHADER_COMPUTE
];
85 uint64_t output_masks
[MESA_SHADER_COMPUTE
];
87 /* VS output information */
88 unsigned num_clip_distances
;
89 unsigned num_cull_distances
;
91 /* VS or GS output information */
92 ge_output_state vsgs_output
;
95 Temp
get_arg(isel_context
*ctx
, struct ac_arg arg
)
98 return ctx
->arg_temps
[arg
.arg_index
];
101 unsigned get_interp_input(nir_intrinsic_op intrin
, enum glsl_interp_mode interp
)
104 case INTERP_MODE_SMOOTH
:
105 case INTERP_MODE_NONE
:
106 if (intrin
== nir_intrinsic_load_barycentric_pixel
||
107 intrin
== nir_intrinsic_load_barycentric_at_sample
||
108 intrin
== nir_intrinsic_load_barycentric_at_offset
)
109 return S_0286CC_PERSP_CENTER_ENA(1);
110 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
111 return S_0286CC_PERSP_CENTROID_ENA(1);
112 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
113 return S_0286CC_PERSP_SAMPLE_ENA(1);
115 case INTERP_MODE_NOPERSPECTIVE
:
116 if (intrin
== nir_intrinsic_load_barycentric_pixel
)
117 return S_0286CC_LINEAR_CENTER_ENA(1);
118 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
119 return S_0286CC_LINEAR_CENTROID_ENA(1);
120 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
121 return S_0286CC_LINEAR_SAMPLE_ENA(1);
129 void init_context(isel_context
*ctx
, nir_shader
*shader
)
131 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
132 unsigned lane_mask_size
= ctx
->program
->lane_mask
.size();
134 ctx
->shader
= shader
;
135 ctx
->divergent_vals
= nir_divergence_analysis(shader
, nir_divergence_view_index_uniform
);
137 std::unique_ptr
<Temp
[]> allocated
{new Temp
[impl
->ssa_alloc
]()};
139 unsigned spi_ps_inputs
= 0;
141 std::unique_ptr
<unsigned[]> nir_to_aco
{new unsigned[impl
->num_blocks
]()};
146 nir_foreach_block(block
, impl
) {
147 nir_foreach_instr(instr
, block
) {
148 switch(instr
->type
) {
149 case nir_instr_type_alu
: {
150 nir_alu_instr
*alu_instr
= nir_instr_as_alu(instr
);
151 unsigned size
= alu_instr
->dest
.dest
.ssa
.num_components
;
152 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 64)
154 RegType type
= RegType::sgpr
;
155 switch(alu_instr
->op
) {
177 case nir_op_fround_even
:
186 case nir_op_pack_half_2x16
:
187 case nir_op_unpack_half_2x16_split_x
:
188 case nir_op_unpack_half_2x16_split_y
:
191 case nir_op_fddx_fine
:
192 case nir_op_fddy_fine
:
193 case nir_op_fddx_coarse
:
194 case nir_op_fddy_coarse
:
195 case nir_op_fquantize2f16
:
197 case nir_op_frexp_sig
:
198 case nir_op_frexp_exp
:
199 case nir_op_cube_face_index
:
200 case nir_op_cube_face_coord
:
201 type
= RegType::vgpr
;
214 size
= lane_mask_size
;
222 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
225 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
226 size
= lane_mask_size
;
228 if (ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
]) {
229 type
= RegType::vgpr
;
231 if (allocated
[alu_instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
||
232 allocated
[alu_instr
->src
[2].src
.ssa
->index
].type() == RegType::vgpr
) {
233 type
= RegType::vgpr
;
236 if (alu_instr
->src
[1].src
.ssa
->num_components
== 1 && alu_instr
->src
[2].src
.ssa
->num_components
== 1) {
237 assert(allocated
[alu_instr
->src
[1].src
.ssa
->index
].size() == allocated
[alu_instr
->src
[2].src
.ssa
->index
].size());
238 size
= allocated
[alu_instr
->src
[1].src
.ssa
->index
].size();
243 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
244 size
= lane_mask_size
;
246 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
250 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
251 size
= lane_mask_size
;
253 for (unsigned i
= 0; i
< nir_op_infos
[alu_instr
->op
].num_inputs
; i
++) {
254 if (allocated
[alu_instr
->src
[i
].src
.ssa
->index
].type() == RegType::vgpr
)
255 type
= RegType::vgpr
;
260 allocated
[alu_instr
->dest
.dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
263 case nir_instr_type_load_const
: {
264 unsigned size
= nir_instr_as_load_const(instr
)->def
.num_components
;
265 if (nir_instr_as_load_const(instr
)->def
.bit_size
== 64)
267 else if (nir_instr_as_load_const(instr
)->def
.bit_size
== 1)
268 size
*= lane_mask_size
;
269 allocated
[nir_instr_as_load_const(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
272 case nir_instr_type_intrinsic
: {
273 nir_intrinsic_instr
*intrinsic
= nir_instr_as_intrinsic(instr
);
274 if (!nir_intrinsic_infos
[intrinsic
->intrinsic
].has_dest
)
276 unsigned size
= intrinsic
->dest
.ssa
.num_components
;
277 if (intrinsic
->dest
.ssa
.bit_size
== 64)
279 RegType type
= RegType::sgpr
;
280 switch(intrinsic
->intrinsic
) {
281 case nir_intrinsic_load_push_constant
:
282 case nir_intrinsic_load_work_group_id
:
283 case nir_intrinsic_load_num_work_groups
:
284 case nir_intrinsic_load_subgroup_id
:
285 case nir_intrinsic_load_num_subgroups
:
286 case nir_intrinsic_load_first_vertex
:
287 case nir_intrinsic_load_base_instance
:
288 case nir_intrinsic_get_buffer_size
:
289 case nir_intrinsic_vote_all
:
290 case nir_intrinsic_vote_any
:
291 case nir_intrinsic_read_first_invocation
:
292 case nir_intrinsic_read_invocation
:
293 case nir_intrinsic_first_invocation
:
294 type
= RegType::sgpr
;
295 if (intrinsic
->dest
.ssa
.bit_size
== 1)
296 size
= lane_mask_size
;
298 case nir_intrinsic_ballot
:
299 type
= RegType::sgpr
;
301 case nir_intrinsic_load_sample_id
:
302 case nir_intrinsic_load_sample_mask_in
:
303 case nir_intrinsic_load_input
:
304 case nir_intrinsic_load_per_vertex_input
:
305 case nir_intrinsic_load_vertex_id
:
306 case nir_intrinsic_load_vertex_id_zero_base
:
307 case nir_intrinsic_load_barycentric_sample
:
308 case nir_intrinsic_load_barycentric_pixel
:
309 case nir_intrinsic_load_barycentric_centroid
:
310 case nir_intrinsic_load_barycentric_at_sample
:
311 case nir_intrinsic_load_barycentric_at_offset
:
312 case nir_intrinsic_load_interpolated_input
:
313 case nir_intrinsic_load_frag_coord
:
314 case nir_intrinsic_load_sample_pos
:
315 case nir_intrinsic_load_layer_id
:
316 case nir_intrinsic_load_local_invocation_id
:
317 case nir_intrinsic_load_local_invocation_index
:
318 case nir_intrinsic_load_subgroup_invocation
:
319 case nir_intrinsic_write_invocation_amd
:
320 case nir_intrinsic_mbcnt_amd
:
321 case nir_intrinsic_load_instance_id
:
322 case nir_intrinsic_ssbo_atomic_add
:
323 case nir_intrinsic_ssbo_atomic_imin
:
324 case nir_intrinsic_ssbo_atomic_umin
:
325 case nir_intrinsic_ssbo_atomic_imax
:
326 case nir_intrinsic_ssbo_atomic_umax
:
327 case nir_intrinsic_ssbo_atomic_and
:
328 case nir_intrinsic_ssbo_atomic_or
:
329 case nir_intrinsic_ssbo_atomic_xor
:
330 case nir_intrinsic_ssbo_atomic_exchange
:
331 case nir_intrinsic_ssbo_atomic_comp_swap
:
332 case nir_intrinsic_global_atomic_add
:
333 case nir_intrinsic_global_atomic_imin
:
334 case nir_intrinsic_global_atomic_umin
:
335 case nir_intrinsic_global_atomic_imax
:
336 case nir_intrinsic_global_atomic_umax
:
337 case nir_intrinsic_global_atomic_and
:
338 case nir_intrinsic_global_atomic_or
:
339 case nir_intrinsic_global_atomic_xor
:
340 case nir_intrinsic_global_atomic_exchange
:
341 case nir_intrinsic_global_atomic_comp_swap
:
342 case nir_intrinsic_image_deref_atomic_add
:
343 case nir_intrinsic_image_deref_atomic_umin
:
344 case nir_intrinsic_image_deref_atomic_imin
:
345 case nir_intrinsic_image_deref_atomic_umax
:
346 case nir_intrinsic_image_deref_atomic_imax
:
347 case nir_intrinsic_image_deref_atomic_and
:
348 case nir_intrinsic_image_deref_atomic_or
:
349 case nir_intrinsic_image_deref_atomic_xor
:
350 case nir_intrinsic_image_deref_atomic_exchange
:
351 case nir_intrinsic_image_deref_atomic_comp_swap
:
352 case nir_intrinsic_image_deref_size
:
353 case nir_intrinsic_shared_atomic_add
:
354 case nir_intrinsic_shared_atomic_imin
:
355 case nir_intrinsic_shared_atomic_umin
:
356 case nir_intrinsic_shared_atomic_imax
:
357 case nir_intrinsic_shared_atomic_umax
:
358 case nir_intrinsic_shared_atomic_and
:
359 case nir_intrinsic_shared_atomic_or
:
360 case nir_intrinsic_shared_atomic_xor
:
361 case nir_intrinsic_shared_atomic_exchange
:
362 case nir_intrinsic_shared_atomic_comp_swap
:
363 case nir_intrinsic_load_scratch
:
364 case nir_intrinsic_load_invocation_id
:
365 case nir_intrinsic_load_primitive_id
:
366 type
= RegType::vgpr
;
368 case nir_intrinsic_shuffle
:
369 case nir_intrinsic_quad_broadcast
:
370 case nir_intrinsic_quad_swap_horizontal
:
371 case nir_intrinsic_quad_swap_vertical
:
372 case nir_intrinsic_quad_swap_diagonal
:
373 case nir_intrinsic_quad_swizzle_amd
:
374 case nir_intrinsic_masked_swizzle_amd
:
375 case nir_intrinsic_inclusive_scan
:
376 case nir_intrinsic_exclusive_scan
:
377 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
378 size
= lane_mask_size
;
379 type
= RegType::sgpr
;
380 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
381 type
= RegType::sgpr
;
383 type
= RegType::vgpr
;
386 case nir_intrinsic_load_view_index
:
387 type
= ctx
->stage
== fragment_fs
? RegType::vgpr
: RegType::sgpr
;
389 case nir_intrinsic_load_front_face
:
390 case nir_intrinsic_load_helper_invocation
:
391 case nir_intrinsic_is_helper_invocation
:
392 type
= RegType::sgpr
;
393 size
= lane_mask_size
;
395 case nir_intrinsic_reduce
:
396 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
397 size
= lane_mask_size
;
398 type
= RegType::sgpr
;
399 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
400 type
= RegType::sgpr
;
402 type
= RegType::vgpr
;
405 case nir_intrinsic_load_ubo
:
406 case nir_intrinsic_load_ssbo
:
407 case nir_intrinsic_load_global
:
408 case nir_intrinsic_vulkan_resource_index
:
409 type
= ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
411 /* due to copy propagation, the swizzled imov is removed if num dest components == 1 */
412 case nir_intrinsic_load_shared
:
413 if (ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
])
414 type
= RegType::vgpr
;
416 type
= RegType::sgpr
;
419 for (unsigned i
= 0; i
< nir_intrinsic_infos
[intrinsic
->intrinsic
].num_srcs
; i
++) {
420 if (allocated
[intrinsic
->src
[i
].ssa
->index
].type() == RegType::vgpr
)
421 type
= RegType::vgpr
;
425 allocated
[intrinsic
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
427 switch(intrinsic
->intrinsic
) {
428 case nir_intrinsic_load_barycentric_sample
:
429 case nir_intrinsic_load_barycentric_pixel
:
430 case nir_intrinsic_load_barycentric_centroid
:
431 case nir_intrinsic_load_barycentric_at_sample
:
432 case nir_intrinsic_load_barycentric_at_offset
: {
433 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(intrinsic
);
434 spi_ps_inputs
|= get_interp_input(intrinsic
->intrinsic
, mode
);
437 case nir_intrinsic_load_front_face
:
438 spi_ps_inputs
|= S_0286CC_FRONT_FACE_ENA(1);
440 case nir_intrinsic_load_frag_coord
:
441 case nir_intrinsic_load_sample_pos
: {
442 uint8_t mask
= nir_ssa_def_components_read(&intrinsic
->dest
.ssa
);
443 for (unsigned i
= 0; i
< 4; i
++) {
445 spi_ps_inputs
|= S_0286CC_POS_X_FLOAT_ENA(1) << i
;
450 case nir_intrinsic_load_sample_id
:
451 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
453 case nir_intrinsic_load_sample_mask_in
:
454 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
455 spi_ps_inputs
|= S_0286CC_SAMPLE_COVERAGE_ENA(1);
462 case nir_instr_type_tex
: {
463 nir_tex_instr
* tex
= nir_instr_as_tex(instr
);
464 unsigned size
= tex
->dest
.ssa
.num_components
;
466 if (tex
->dest
.ssa
.bit_size
== 64)
468 if (tex
->op
== nir_texop_texture_samples
)
469 assert(!ctx
->divergent_vals
[tex
->dest
.ssa
.index
]);
470 if (ctx
->divergent_vals
[tex
->dest
.ssa
.index
])
471 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::vgpr
, size
));
473 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
476 case nir_instr_type_parallel_copy
: {
477 nir_foreach_parallel_copy_entry(entry
, nir_instr_as_parallel_copy(instr
)) {
478 allocated
[entry
->dest
.ssa
.index
] = allocated
[entry
->src
.ssa
->index
];
482 case nir_instr_type_ssa_undef
: {
483 unsigned size
= nir_instr_as_ssa_undef(instr
)->def
.num_components
;
484 if (nir_instr_as_ssa_undef(instr
)->def
.bit_size
== 64)
486 allocated
[nir_instr_as_ssa_undef(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
489 case nir_instr_type_phi
: {
490 nir_phi_instr
* phi
= nir_instr_as_phi(instr
);
492 unsigned size
= phi
->dest
.ssa
.num_components
;
494 if (phi
->dest
.ssa
.bit_size
== 1) {
495 assert(size
== 1 && "multiple components not yet supported on boolean phis.");
496 type
= RegType::sgpr
;
497 size
*= lane_mask_size
;
498 allocated
[phi
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
502 if (ctx
->divergent_vals
[phi
->dest
.ssa
.index
]) {
503 type
= RegType::vgpr
;
505 type
= RegType::sgpr
;
506 nir_foreach_phi_src (src
, phi
) {
507 if (allocated
[src
->src
.ssa
->index
].type() == RegType::vgpr
)
508 type
= RegType::vgpr
;
509 if (allocated
[src
->src
.ssa
->index
].type() == RegType::none
)
514 size
*= phi
->dest
.ssa
.bit_size
== 64 ? 2 : 1;
515 RegClass rc
= RegClass(type
, size
);
516 if (rc
!= allocated
[phi
->dest
.ssa
.index
].regClass()) {
519 nir_foreach_phi_src(src
, phi
)
520 assert(allocated
[src
->src
.ssa
->index
].size() == rc
.size());
522 allocated
[phi
->dest
.ssa
.index
] = Temp(0, rc
);
532 if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_inputs
)) {
533 /* If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be enabled too */
534 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
537 if (!(spi_ps_inputs
& 0x7F)) {
538 /* At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled */
539 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
542 ctx
->program
->config
->spi_ps_input_ena
= spi_ps_inputs
;
543 ctx
->program
->config
->spi_ps_input_addr
= spi_ps_inputs
;
545 for (unsigned i
= 0; i
< impl
->ssa_alloc
; i
++)
546 allocated
[i
] = Temp(ctx
->program
->allocateId(), allocated
[i
].regClass());
548 ctx
->allocated
.reset(allocated
.release());
549 ctx
->cf_info
.nir_to_aco
.reset(nir_to_aco
.release());
552 Pseudo_instruction
*add_startpgm(struct isel_context
*ctx
)
554 unsigned arg_count
= ctx
->args
->ac
.arg_count
;
555 if (ctx
->stage
== fragment_fs
) {
556 /* LLVM optimizes away unused FS inputs and computes spi_ps_input_addr
557 * itself and then communicates the results back via the ELF binary.
558 * Mirror what LLVM does by re-mapping the VGPR arguments here.
560 * TODO: If we made the FS input scanning code into a separate pass that
561 * could run before argument setup, then this wouldn't be necessary
564 struct ac_shader_args
*args
= &ctx
->args
->ac
;
566 for (unsigned i
= 0, vgpr_arg
= 0, vgpr_reg
= 0; i
< args
->arg_count
; i
++) {
567 if (args
->args
[i
].file
!= AC_ARG_VGPR
) {
572 if (!(ctx
->program
->config
->spi_ps_input_addr
& (1 << vgpr_arg
))) {
573 args
->args
[i
].skip
= true;
575 args
->args
[i
].offset
= vgpr_reg
;
576 vgpr_reg
+= args
->args
[i
].size
;
583 aco_ptr
<Pseudo_instruction
> startpgm
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_startpgm
, Format::PSEUDO
, 0, arg_count
+ 1)};
584 for (unsigned i
= 0, arg
= 0; i
< ctx
->args
->ac
.arg_count
; i
++) {
585 if (ctx
->args
->ac
.args
[i
].skip
)
588 enum ac_arg_regfile file
= ctx
->args
->ac
.args
[i
].file
;
589 unsigned size
= ctx
->args
->ac
.args
[i
].size
;
590 unsigned reg
= ctx
->args
->ac
.args
[i
].offset
;
591 RegClass type
= RegClass(file
== AC_ARG_SGPR
? RegType::sgpr
: RegType::vgpr
, size
);
592 Temp dst
= Temp
{ctx
->program
->allocateId(), type
};
593 ctx
->arg_temps
[i
] = dst
;
594 startpgm
->definitions
[arg
] = Definition(dst
);
595 startpgm
->definitions
[arg
].setFixed(PhysReg
{file
== AC_ARG_SGPR
? reg
: reg
+ 256});
598 startpgm
->definitions
[arg_count
] = Definition
{ctx
->program
->allocateId(), exec
, ctx
->program
->lane_mask
};
599 Pseudo_instruction
*instr
= startpgm
.get();
600 ctx
->block
->instructions
.push_back(std::move(startpgm
));
602 /* Stash these in the program so that they can be accessed later when
605 ctx
->program
->private_segment_buffer
= get_arg(ctx
, ctx
->args
->ring_offsets
);
606 ctx
->program
->scratch_offset
= get_arg(ctx
, ctx
->args
->scratch_offset
);
612 type_size(const struct glsl_type
*type
, bool bindless
)
614 // TODO: don't we need type->std430_base_alignment() here?
615 return glsl_count_attribute_slots(type
, false);
619 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
621 assert(glsl_type_is_vector_or_scalar(type
));
623 uint32_t comp_size
= glsl_type_is_boolean(type
)
624 ? 4 : glsl_get_bit_size(type
) / 8;
625 unsigned length
= glsl_get_vector_elements(type
);
626 *size
= comp_size
* length
,
631 mem_vectorize_callback(unsigned align
, unsigned bit_size
,
632 unsigned num_components
, unsigned high_offset
,
633 nir_intrinsic_instr
*low
, nir_intrinsic_instr
*high
)
635 if ((bit_size
!= 32 && bit_size
!= 64) || num_components
> 4)
638 /* >128 bit loads are split except with SMEM */
639 if (bit_size
* num_components
> 128)
642 switch (low
->intrinsic
) {
643 case nir_intrinsic_load_ubo
:
644 case nir_intrinsic_load_ssbo
:
645 case nir_intrinsic_store_ssbo
:
646 case nir_intrinsic_load_push_constant
:
647 return align
% 4 == 0;
648 case nir_intrinsic_load_deref
:
649 case nir_intrinsic_store_deref
:
650 assert(nir_src_as_deref(low
->src
[0])->mode
== nir_var_mem_shared
);
652 case nir_intrinsic_load_shared
:
653 case nir_intrinsic_store_shared
:
654 if (bit_size
* num_components
> 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
655 return align
% 16 == 0;
657 return align
% 4 == 0;
665 setup_vs_variables(isel_context
*ctx
, nir_shader
*nir
)
667 nir_foreach_variable(variable
, &nir
->inputs
)
669 variable
->data
.driver_location
= variable
->data
.location
* 4;
671 nir_foreach_variable(variable
, &nir
->outputs
)
673 if (ctx
->stage
== vertex_geometry_gs
)
674 variable
->data
.driver_location
= util_bitcount64(ctx
->output_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
675 else if (ctx
->stage
== vertex_es
)
676 //TODO: make this more compact
677 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
)variable
->data
.location
) * 4;
679 variable
->data
.driver_location
= variable
->data
.location
* 4;
682 if (ctx
->stage
== vertex_vs
) {
683 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
685 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
686 sizeof(outinfo
->vs_output_param_offset
));
688 bool export_clip_dists
= ctx
->options
->key
.vs_common_out
.export_clip_dists
;
690 outinfo
->param_exports
= 0;
691 int pos_written
= 0x1;
692 if (outinfo
->writes_pointsize
|| outinfo
->writes_viewport_index
|| outinfo
->writes_layer
)
693 pos_written
|= 1 << 1;
695 uint64_t mask
= ctx
->output_masks
[nir
->info
.stage
];
697 int idx
= u_bit_scan64(&mask
);
698 if (idx
>= VARYING_SLOT_VAR0
|| idx
== VARYING_SLOT_LAYER
|| idx
== VARYING_SLOT_PRIMITIVE_ID
||
699 ((idx
== VARYING_SLOT_CLIP_DIST0
|| idx
== VARYING_SLOT_CLIP_DIST1
) && export_clip_dists
)) {
700 if (outinfo
->vs_output_param_offset
[idx
] == AC_EXP_PARAM_UNDEFINED
)
701 outinfo
->vs_output_param_offset
[idx
] = outinfo
->param_exports
++;
704 if (outinfo
->writes_layer
&&
705 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] == AC_EXP_PARAM_UNDEFINED
) {
706 /* when ctx->options->key.has_multiview_view_index = true, the layer
707 * variable isn't declared in NIR and it's isel's job to get the layer */
708 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = outinfo
->param_exports
++;
711 if (outinfo
->export_prim_id
) {
712 assert(outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] == AC_EXP_PARAM_UNDEFINED
);
713 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = outinfo
->param_exports
++;
716 ctx
->num_clip_distances
= util_bitcount(outinfo
->clip_dist_mask
);
717 ctx
->num_cull_distances
= util_bitcount(outinfo
->cull_dist_mask
);
719 assert(ctx
->num_clip_distances
+ ctx
->num_cull_distances
<= 8);
721 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
722 pos_written
|= 1 << 2;
723 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
724 pos_written
|= 1 << 3;
726 outinfo
->pos_exports
= util_bitcount(pos_written
);
727 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== vertex_es
) {
728 /* TODO: radv_nir_shader_info_pass() already sets this but it's larger
729 * than it needs to be in order to set it better, we have to improve
730 * radv_nir_shader_info_pass() because gfx9_get_gs_info() uses
731 * esgs_itemsize and has to be done before compilation
733 /* radv_es_output_info *outinfo = &ctx->program->info->vs.es_info;
734 outinfo->esgs_itemsize = util_bitcount64(ctx->output_masks[nir->info.stage]) * 16u; */
739 setup_variables(isel_context
*ctx
, nir_shader
*nir
)
741 switch (nir
->info
.stage
) {
742 case MESA_SHADER_FRAGMENT
: {
743 nir_foreach_variable(variable
, &nir
->outputs
)
745 int idx
= variable
->data
.location
+ variable
->data
.index
;
746 variable
->data
.driver_location
= idx
* 4;
750 case MESA_SHADER_COMPUTE
: {
751 ctx
->program
->config
->lds_size
= (nir
->info
.cs
.shared_size
+ ctx
->program
->lds_alloc_granule
- 1) /
752 ctx
->program
->lds_alloc_granule
;
755 case MESA_SHADER_VERTEX
: {
756 setup_vs_variables(ctx
, nir
);
759 case MESA_SHADER_GEOMETRY
: {
760 assert(ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== geometry_gs
);
761 if (ctx
->stage
== vertex_geometry_gs
) {
762 nir_foreach_variable(variable
, &nir
->inputs
) {
763 variable
->data
.driver_location
= util_bitcount64(ctx
->input_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
766 //TODO: make this more compact
767 nir_foreach_variable(variable
, &nir
->inputs
) {
768 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
)variable
->data
.location
) * 4;
771 nir_foreach_variable(variable
, &nir
->outputs
) {
772 variable
->data
.driver_location
= variable
->data
.location
* 4;
774 if (ctx
->stage
== vertex_geometry_gs
)
775 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_VERTEX
; /* tesselation shaders are not yet supported */
779 unreachable("Unhandled shader stage.");
784 get_io_masks(isel_context
*ctx
, unsigned shader_count
, struct nir_shader
*const *shaders
)
786 for (unsigned i
= 0; i
< shader_count
; i
++) {
787 nir_shader
*nir
= shaders
[i
];
788 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
791 uint64_t output_mask
= 0;
792 nir_foreach_variable(variable
, &nir
->outputs
) {
793 const glsl_type
*type
= variable
->type
;
794 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
795 type
= type
->fields
.array
;
796 unsigned slots
= type
->count_attribute_slots(false);
797 if (variable
->data
.compact
) {
798 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
799 slots
= (component_count
+ 3) / 4;
801 output_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
804 uint64_t input_mask
= 0;
805 nir_foreach_variable(variable
, &nir
->inputs
) {
806 const glsl_type
*type
= variable
->type
;
807 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
808 type
= type
->fields
.array
;
809 unsigned slots
= type
->count_attribute_slots(false);
810 if (variable
->data
.compact
) {
811 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
812 slots
= (component_count
+ 3) / 4;
814 input_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
817 ctx
->output_masks
[nir
->info
.stage
] |= output_mask
;
818 if (i
+ 1 < shader_count
)
819 ctx
->input_masks
[shaders
[i
+ 1]->info
.stage
] |= output_mask
;
821 ctx
->input_masks
[nir
->info
.stage
] |= input_mask
;
823 ctx
->output_masks
[shaders
[i
- 1]->info
.stage
] |= input_mask
;
828 setup_isel_context(Program
* program
,
829 unsigned shader_count
,
830 struct nir_shader
*const *shaders
,
831 ac_shader_config
* config
,
832 struct radv_shader_args
*args
)
835 for (unsigned i
= 0; i
< shader_count
; i
++) {
836 switch (shaders
[i
]->info
.stage
) {
837 case MESA_SHADER_VERTEX
:
838 program
->stage
|= sw_vs
;
840 case MESA_SHADER_TESS_CTRL
:
841 program
->stage
|= sw_tcs
;
843 case MESA_SHADER_TESS_EVAL
:
844 program
->stage
|= sw_tes
;
846 case MESA_SHADER_GEOMETRY
:
847 program
->stage
|= sw_gs
;
849 case MESA_SHADER_FRAGMENT
:
850 program
->stage
|= sw_fs
;
852 case MESA_SHADER_COMPUTE
:
853 program
->stage
|= sw_cs
;
856 unreachable("Shader stage not implemented");
859 bool gfx9_plus
= args
->options
->chip_class
>= GFX9
;
860 bool ngg
= args
->shader_info
->is_ngg
&& args
->options
->chip_class
>= GFX10
;
861 if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_es
)
862 program
->stage
|= hw_es
;
863 else if (program
->stage
== sw_vs
&& !args
->shader_info
->vs
.as_ls
)
864 program
->stage
|= hw_vs
;
865 else if (program
->stage
== sw_gs
)
866 program
->stage
|= hw_gs
;
867 else if (program
->stage
== sw_fs
)
868 program
->stage
|= hw_fs
;
869 else if (program
->stage
== sw_cs
)
870 program
->stage
|= hw_cs
;
871 else if (program
->stage
== (sw_vs
| sw_gs
) && gfx9_plus
&& !ngg
)
872 program
->stage
|= hw_gs
;
874 unreachable("Shader stage not implemented");
876 program
->config
= config
;
877 program
->info
= args
->shader_info
;
878 program
->chip_class
= args
->options
->chip_class
;
879 program
->family
= args
->options
->family
;
880 program
->wave_size
= args
->shader_info
->wave_size
;
881 program
->lane_mask
= program
->wave_size
== 32 ? s1
: s2
;
883 program
->lds_alloc_granule
= args
->options
->chip_class
>= GFX7
? 512 : 256;
884 program
->lds_limit
= args
->options
->chip_class
>= GFX7
? 65536 : 32768;
885 program
->vgpr_limit
= 256;
886 program
->vgpr_alloc_granule
= 3;
888 if (args
->options
->chip_class
>= GFX10
) {
889 program
->physical_sgprs
= 2560; /* doesn't matter as long as it's at least 128 * 20 */
890 program
->sgpr_alloc_granule
= 127;
891 program
->sgpr_limit
= 106;
892 program
->vgpr_alloc_granule
= program
->wave_size
== 32 ? 7 : 3;
893 } else if (program
->chip_class
>= GFX8
) {
894 program
->physical_sgprs
= 800;
895 program
->sgpr_alloc_granule
= 15;
896 if (args
->options
->family
== CHIP_TONGA
|| args
->options
->family
== CHIP_ICELAND
)
897 program
->sgpr_limit
= 94; /* workaround hardware bug */
899 program
->sgpr_limit
= 102;
901 program
->physical_sgprs
= 512;
902 program
->sgpr_alloc_granule
= 7;
903 program
->sgpr_limit
= 104;
906 /* TODO: we don't have to allocate VCC if we don't need it */
907 program
->needs_vcc
= true;
909 calc_min_waves(program
);
910 program
->vgpr_limit
= get_addr_vgpr_from_waves(program
, program
->min_waves
);
911 program
->sgpr_limit
= get_addr_sgpr_from_waves(program
, program
->min_waves
);
913 isel_context ctx
= {};
914 ctx
.program
= program
;
916 ctx
.options
= args
->options
;
917 ctx
.stage
= program
->stage
;
919 get_io_masks(&ctx
, shader_count
, shaders
);
921 for (unsigned i
= 0; i
< shader_count
; i
++) {
922 nir_shader
*nir
= shaders
[i
];
924 /* align and copy constant data */
925 while (program
->constant_data
.size() % 4u)
926 program
->constant_data
.push_back(0);
927 ctx
.constant_data_offset
= program
->constant_data
.size();
928 program
->constant_data
.insert(program
->constant_data
.end(),
929 (uint8_t*)nir
->constant_data
,
930 (uint8_t*)nir
->constant_data
+ nir
->constant_data_size
);
932 /* the variable setup has to be done before lower_io / CSE */
933 setup_variables(&ctx
, nir
);
935 /* optimize and lower memory operations */
936 bool lower_to_scalar
= false;
937 bool lower_pack
= false;
938 if (nir_opt_load_store_vectorize(nir
,
939 (nir_variable_mode
)(nir_var_mem_ssbo
| nir_var_mem_ubo
|
940 nir_var_mem_push_const
| nir_var_mem_shared
),
941 mem_vectorize_callback
)) {
942 lower_to_scalar
= true;
945 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
946 nir_lower_io(nir
, (nir_variable_mode
)(nir_var_shader_in
| nir_var_shader_out
), type_size
, (nir_lower_io_options
)0);
947 nir_lower_explicit_io(nir
, nir_var_mem_global
, nir_address_format_64bit_global
);
950 nir_lower_alu_to_scalar(nir
, NULL
, NULL
);
954 /* lower ALU operations */
955 // TODO: implement logic64 in aco, it's more effective for sgprs
956 nir_lower_int64(nir
, nir
->options
->lower_int64_options
);
958 nir_opt_idiv_const(nir
, 32);
959 nir_lower_idiv(nir
, nir_lower_idiv_precise
);
961 /* optimize the lowered ALU operations */
962 bool more_algebraic
= true;
963 while (more_algebraic
) {
964 more_algebraic
= false;
965 NIR_PASS_V(nir
, nir_copy_prop
);
966 NIR_PASS_V(nir
, nir_opt_dce
);
967 NIR_PASS_V(nir
, nir_opt_constant_folding
);
968 NIR_PASS(more_algebraic
, nir
, nir_opt_algebraic
);
971 /* Do late algebraic optimization to turn add(a, neg(b)) back into
972 * subs, then the mandatory cleanup after algebraic. Note that it may
973 * produce fnegs, and if so then we need to keep running to squash
976 bool more_late_algebraic
= true;
977 while (more_late_algebraic
) {
978 more_late_algebraic
= false;
979 NIR_PASS(more_late_algebraic
, nir
, nir_opt_algebraic_late
);
980 NIR_PASS_V(nir
, nir_opt_constant_folding
);
981 NIR_PASS_V(nir
, nir_copy_prop
);
982 NIR_PASS_V(nir
, nir_opt_dce
);
983 NIR_PASS_V(nir
, nir_opt_cse
);
987 nir_lower_load_const_to_scalar(nir
);
988 nir_opt_shrink_load(nir
);
989 nir_move_options move_opts
= (nir_move_options
)(
990 nir_move_const_undef
| nir_move_load_ubo
| nir_move_load_input
| nir_move_comparisons
);
991 nir_opt_sink(nir
, move_opts
);
992 nir_opt_move(nir
, move_opts
);
993 nir_convert_to_lcssa(nir
, true, false);
994 nir_lower_phis_to_scalar(nir
);
996 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
997 nir_index_ssa_defs(func
);
998 nir_metadata_require(func
, nir_metadata_block_index
);
1000 if (args
->options
->dump_preoptir
) {
1001 fprintf(stderr
, "NIR shader before instruction selection:\n");
1002 nir_print_shader(nir
, stderr
);
1006 unsigned scratch_size
= 0;
1007 for (unsigned i
= 0; i
< shader_count
; i
++)
1008 scratch_size
= std::max(scratch_size
, shaders
[i
]->scratch_size
);
1009 ctx
.program
->config
->scratch_bytes_per_wave
= align(scratch_size
* ctx
.program
->wave_size
, 1024);
1011 ctx
.block
= ctx
.program
->create_and_insert_block();
1012 ctx
.block
->loop_nest_depth
= 0;
1013 ctx
.block
->kind
= block_kind_top_level
;