2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 #include "ac_binary.h"
35 #include "amd_family.h"
36 #include "aco_opcodes.h"
39 struct radv_nir_compiler_options
;
40 struct radv_shader_args
;
41 struct radv_shader_info
;
45 extern uint64_t debug_flags
;
49 DEBUG_VALIDATE_RA
= 0x2,
54 * Representation of the instruction's microcode encoding format
55 * Note: Some Vector ALU Formats can be combined, such that:
56 * - VOP2* | VOP3A represents a VOP2 instruction in VOP3A encoding
57 * - VOP2* | DPP represents a VOP2 instruction with data parallel primitive.
58 * - VOP2* | SDWA represents a VOP2 instruction with sub-dword addressing.
60 * (*) The same is applicable for VOP1 and VOPC instructions.
62 enum class Format
: std::uint16_t {
63 /* Pseudo Instruction Format */
65 /* Scalar ALU & Control Formats */
71 /* Scalar Memory Format */
75 /* Vector Memory Buffer Formats */
78 /* Vector Memory Image Format */
89 PSEUDO_REDUCTION
= 18,
91 /* Vector ALU Formats */
99 /* Vector Parameter Interpolation Format */
105 enum barrier_interaction
{
107 barrier_buffer
= 0x1,
109 barrier_atomic
= 0x4,
110 barrier_shared
= 0x8,
122 /* Note that v_rcp_f32, v_exp_f32, v_log_f32, v_sqrt_f32, v_rsq_f32 and
123 * v_mad_f32/v_madak_f32/v_madmk_f32/v_mac_f32 always flush denormals. */
124 fp_denorm_flush
= 0x0,
125 fp_denorm_keep
= 0x3,
129 /* matches encoding of the MODE register */
133 fp_round round16_64
:2;
135 unsigned denorm16_64
:2;
139 /* if false, optimizations which may remove infs/nan/-0.0 can be done */
140 bool preserve_signed_zero_inf_nan32
:1;
141 bool preserve_signed_zero_inf_nan16_64
:1;
142 /* if false, optimizations which may remove denormal flushing can be done */
143 bool must_flush_denorms32
:1;
144 bool must_flush_denorms16_64
:1;
145 bool care_about_round32
:1;
146 bool care_about_round16_64
:1;
148 /* Returns true if instructions using the mode "other" can safely use the
149 * current one instead. */
150 bool canReplace(float_mode other
) const noexcept
{
151 return val
== other
.val
&&
152 (preserve_signed_zero_inf_nan32
|| !other
.preserve_signed_zero_inf_nan32
) &&
153 (preserve_signed_zero_inf_nan16_64
|| !other
.preserve_signed_zero_inf_nan16_64
) &&
154 (must_flush_denorms32
|| !other
.must_flush_denorms32
) &&
155 (must_flush_denorms16_64
|| !other
.must_flush_denorms16_64
) &&
156 (care_about_round32
|| !other
.care_about_round32
) &&
157 (care_about_round16_64
|| !other
.care_about_round16_64
);
161 constexpr Format
asVOP3(Format format
) {
162 return (Format
) ((uint32_t) Format::VOP3
| (uint32_t) format
);
190 /* these are used for WWM and spills to vgpr */
191 v1_linear
= v1
| (1 << 6),
192 v2_linear
= v2
| (1 << 6),
195 RegClass() = default;
196 constexpr RegClass(RC rc
)
198 constexpr RegClass(RegType type
, unsigned size
)
199 : rc((RC
) ((type
== RegType::vgpr
? 1 << 5 : 0) | size
)) {}
201 constexpr operator RC() const { return rc
; }
202 explicit operator bool() = delete;
204 constexpr RegType
type() const { return rc
<= RC::s16
? RegType::sgpr
: RegType::vgpr
; }
205 constexpr unsigned size() const { return (unsigned) rc
& 0x1F; }
206 constexpr bool is_linear() const { return rc
<= RC::s16
|| rc
& (1 << 6); }
207 constexpr RegClass
as_linear() const { return RegClass((RC
) (rc
| (1 << 6))); }
213 /* transitional helper expressions */
214 static constexpr RegClass s1
{RegClass::s1
};
215 static constexpr RegClass s2
{RegClass::s2
};
216 static constexpr RegClass s3
{RegClass::s3
};
217 static constexpr RegClass s4
{RegClass::s4
};
218 static constexpr RegClass s8
{RegClass::s8
};
219 static constexpr RegClass s16
{RegClass::s16
};
220 static constexpr RegClass v1
{RegClass::v1
};
221 static constexpr RegClass v2
{RegClass::v2
};
222 static constexpr RegClass v3
{RegClass::v3
};
223 static constexpr RegClass v4
{RegClass::v4
};
224 static constexpr RegClass v5
{RegClass::v5
};
225 static constexpr RegClass v6
{RegClass::v6
};
226 static constexpr RegClass v7
{RegClass::v7
};
227 static constexpr RegClass v8
{RegClass::v8
};
231 * Each temporary virtual register has a
232 * register class (i.e. size and type)
237 constexpr Temp(uint32_t id
, RegClass cls
) noexcept
238 : id_(id
), reg_class(cls
) {}
240 constexpr uint32_t id() const noexcept
{ return id_
; }
241 constexpr RegClass
regClass() const noexcept
{ return reg_class
; }
243 constexpr unsigned size() const noexcept
{ return reg_class
.size(); }
244 constexpr RegType
type() const noexcept
{ return reg_class
.type(); }
245 constexpr bool is_linear() const noexcept
{ return reg_class
.is_linear(); }
247 constexpr bool operator <(Temp other
) const noexcept
{ return id() < other
.id(); }
248 constexpr bool operator==(Temp other
) const noexcept
{ return id() == other
.id(); }
249 constexpr bool operator!=(Temp other
) const noexcept
{ return id() != other
.id(); }
258 * Represents the physical register for each
259 * Operand and Definition.
262 constexpr PhysReg() = default;
263 explicit constexpr PhysReg(unsigned r
) : reg(r
) {}
264 constexpr operator unsigned() const { return reg
; }
269 /* helper expressions for special registers */
270 static constexpr PhysReg m0
{124};
271 static constexpr PhysReg vcc
{106};
272 static constexpr PhysReg sgpr_null
{125}; /* GFX10+ */
273 static constexpr PhysReg exec
{126};
274 static constexpr PhysReg exec_lo
{126};
275 static constexpr PhysReg exec_hi
{127};
276 static constexpr PhysReg scc
{253};
280 * Initially, each Operand refers to either
281 * a temporary virtual register
282 * or to a constant value
283 * Temporary registers get mapped to physical register during RA
284 * Constant values are inlined into the instruction sequence.
290 : reg_(PhysReg
{128}), isTemp_(false), isFixed_(true), isConstant_(false),
291 isKill_(false), isUndef_(true), isFirstKill_(false), is64BitConst_(false) {}
293 explicit Operand(Temp r
) noexcept
300 setFixed(PhysReg
{128});
303 explicit Operand(uint32_t v
) noexcept
308 setFixed(PhysReg
{128 + v
});
309 else if (v
>= 0xFFFFFFF0) /* [-16 .. -1] */
310 setFixed(PhysReg
{192 - v
});
311 else if (v
== 0x3f000000) /* 0.5 */
312 setFixed(PhysReg
{240});
313 else if (v
== 0xbf000000) /* -0.5 */
314 setFixed(PhysReg
{241});
315 else if (v
== 0x3f800000) /* 1.0 */
316 setFixed(PhysReg
{242});
317 else if (v
== 0xbf800000) /* -1.0 */
318 setFixed(PhysReg
{243});
319 else if (v
== 0x40000000) /* 2.0 */
320 setFixed(PhysReg
{244});
321 else if (v
== 0xc0000000) /* -2.0 */
322 setFixed(PhysReg
{245});
323 else if (v
== 0x40800000) /* 4.0 */
324 setFixed(PhysReg
{246});
325 else if (v
== 0xc0800000) /* -4.0 */
326 setFixed(PhysReg
{247});
327 else /* Literal Constant */
328 setFixed(PhysReg
{255});
330 explicit Operand(uint64_t v
) noexcept
333 is64BitConst_
= true;
335 setFixed(PhysReg
{128 + (uint32_t) v
});
336 else if (v
>= 0xFFFFFFFFFFFFFFF0) /* [-16 .. -1] */
337 setFixed(PhysReg
{192 - (uint32_t) v
});
338 else if (v
== 0x3FE0000000000000) /* 0.5 */
339 setFixed(PhysReg
{240});
340 else if (v
== 0xBFE0000000000000) /* -0.5 */
341 setFixed(PhysReg
{241});
342 else if (v
== 0x3FF0000000000000) /* 1.0 */
343 setFixed(PhysReg
{242});
344 else if (v
== 0xBFF0000000000000) /* -1.0 */
345 setFixed(PhysReg
{243});
346 else if (v
== 0x4000000000000000) /* 2.0 */
347 setFixed(PhysReg
{244});
348 else if (v
== 0xC000000000000000) /* -2.0 */
349 setFixed(PhysReg
{245});
350 else if (v
== 0x4010000000000000) /* 4.0 */
351 setFixed(PhysReg
{246});
352 else if (v
== 0xC010000000000000) /* -4.0 */
353 setFixed(PhysReg
{247});
354 else { /* Literal Constant: we don't know if it is a long or double.*/
356 assert(false && "attempt to create a 64-bit literal constant");
359 explicit Operand(RegClass type
) noexcept
362 data_
.temp
= Temp(0, type
);
363 setFixed(PhysReg
{128});
365 explicit Operand(PhysReg reg
, RegClass type
) noexcept
367 data_
.temp
= Temp(0, type
);
371 constexpr bool isTemp() const noexcept
376 constexpr void setTemp(Temp t
) noexcept
{
377 assert(!isConstant_
);
382 constexpr Temp
getTemp() const noexcept
387 constexpr uint32_t tempId() const noexcept
389 return data_
.temp
.id();
392 constexpr bool hasRegClass() const noexcept
394 return isTemp() || isUndefined();
397 constexpr RegClass
regClass() const noexcept
399 return data_
.temp
.regClass();
402 constexpr unsigned size() const noexcept
405 return is64BitConst_
? 2 : 1;
407 return data_
.temp
.size();
410 constexpr bool isFixed() const noexcept
415 constexpr PhysReg
physReg() const noexcept
420 constexpr void setFixed(PhysReg reg
) noexcept
422 isFixed_
= reg
!= unsigned(-1);
426 constexpr bool isConstant() const noexcept
431 constexpr bool isLiteral() const noexcept
433 return isConstant() && reg_
== 255;
436 constexpr bool isUndefined() const noexcept
441 constexpr uint32_t constantValue() const noexcept
446 constexpr bool constantEquals(uint32_t cmp
) const noexcept
448 return isConstant() && constantValue() == cmp
;
451 constexpr void setKill(bool flag
) noexcept
458 constexpr bool isKill() const noexcept
460 return isKill_
|| isFirstKill();
463 constexpr void setFirstKill(bool flag
) noexcept
470 /* When there are multiple operands killing the same temporary,
471 * isFirstKill() is only returns true for the first one. */
472 constexpr bool isFirstKill() const noexcept
481 Temp temp
= Temp(0, s1
);
488 uint8_t isConstant_
:1;
491 uint8_t isFirstKill_
:1;
492 uint8_t is64BitConst_
:1;
494 /* can't initialize bit-fields in c++11, so work around using a union */
495 uint8_t control_
= 0;
501 * Definitions are the results of Instructions
502 * and refer to temporary virtual registers
503 * which are later mapped to physical registers
505 class Definition final
508 constexpr Definition() : temp(Temp(0, s1
)), reg_(0), isFixed_(0), hasHint_(0), isKill_(0) {}
509 Definition(uint32_t index
, RegClass type
) noexcept
510 : temp(index
, type
) {}
511 explicit Definition(Temp tmp
) noexcept
513 Definition(PhysReg reg
, RegClass type
) noexcept
514 : temp(Temp(0, type
))
518 Definition(uint32_t tmpId
, PhysReg reg
, RegClass type
) noexcept
519 : temp(Temp(tmpId
, type
))
524 constexpr bool isTemp() const noexcept
529 constexpr Temp
getTemp() const noexcept
534 constexpr uint32_t tempId() const noexcept
539 constexpr void setTemp(Temp t
) noexcept
{
543 constexpr RegClass
regClass() const noexcept
545 return temp
.regClass();
548 constexpr unsigned size() const noexcept
553 constexpr bool isFixed() const noexcept
558 constexpr PhysReg
physReg() const noexcept
563 constexpr void setFixed(PhysReg reg
) noexcept
569 constexpr void setHint(PhysReg reg
) noexcept
575 constexpr bool hasHint() const noexcept
580 constexpr void setKill(bool flag
) noexcept
585 constexpr bool isKill() const noexcept
591 Temp temp
= Temp(0, s1
);
599 /* can't initialize bit-fields in c++11, so work around using a union */
600 uint8_t control_
= 0;
611 aco::span
<Operand
> operands
;
612 aco::span
<Definition
> definitions
;
614 constexpr bool isVALU() const noexcept
616 return ((uint16_t) format
& (uint16_t) Format::VOP1
) == (uint16_t) Format::VOP1
617 || ((uint16_t) format
& (uint16_t) Format::VOP2
) == (uint16_t) Format::VOP2
618 || ((uint16_t) format
& (uint16_t) Format::VOPC
) == (uint16_t) Format::VOPC
619 || ((uint16_t) format
& (uint16_t) Format::VOP3A
) == (uint16_t) Format::VOP3A
620 || ((uint16_t) format
& (uint16_t) Format::VOP3B
) == (uint16_t) Format::VOP3B
621 || ((uint16_t) format
& (uint16_t) Format::VOP3P
) == (uint16_t) Format::VOP3P
;
624 constexpr bool isSALU() const noexcept
626 return format
== Format::SOP1
||
627 format
== Format::SOP2
||
628 format
== Format::SOPC
||
629 format
== Format::SOPK
||
630 format
== Format::SOPP
;
633 constexpr bool isVMEM() const noexcept
635 return format
== Format::MTBUF
||
636 format
== Format::MUBUF
||
637 format
== Format::MIMG
;
640 constexpr bool isDPP() const noexcept
642 return (uint16_t) format
& (uint16_t) Format::DPP
;
645 constexpr bool isVOP3() const noexcept
647 return ((uint16_t) format
& (uint16_t) Format::VOP3A
) ||
648 ((uint16_t) format
& (uint16_t) Format::VOP3B
) ||
649 format
== Format::VOP3P
;
652 constexpr bool isSDWA() const noexcept
654 return (uint16_t) format
& (uint16_t) Format::SDWA
;
657 constexpr bool isFlatOrGlobal() const noexcept
659 return format
== Format::FLAT
|| format
== Format::GLOBAL
;
662 constexpr bool usesModifiers() const noexcept
;
664 constexpr bool reads_exec() const noexcept
666 for (const Operand
& op
: operands
) {
667 if (op
.isFixed() && op
.physReg() == exec
)
674 struct SOPK_instruction
: public Instruction
{
678 struct SOPP_instruction
: public Instruction
{
683 struct SOPC_instruction
: public Instruction
{
686 struct SOP1_instruction
: public Instruction
{
689 struct SOP2_instruction
: public Instruction
{
693 * Scalar Memory Format:
694 * For s_(buffer_)load_dword*:
695 * Operand(0): SBASE - SGPR-pair which provides base address
696 * Operand(1): Offset - immediate (un)signed offset or SGPR
697 * Operand(2) / Definition(0): SDATA - SGPR for read / write result
698 * Operand(n-1): SOffset - SGPR offset (Vega only)
700 * Having no operands is also valid for instructions such as s_dcache_inv.
703 struct SMEM_instruction
: public Instruction
{
704 bool glc
; /* VI+: globally coherent */
705 bool dlc
; /* NAVI: device level coherent */
706 bool nv
; /* VEGA only: Non-volatile */
709 barrier_interaction barrier
;
712 struct VOP1_instruction
: public Instruction
{
715 struct VOP2_instruction
: public Instruction
{
718 struct VOPC_instruction
: public Instruction
{
721 struct VOP3A_instruction
: public Instruction
{
730 * Data Parallel Primitives Format:
731 * This format can be used for VOP1, VOP2 or VOPC instructions.
732 * The swizzle applies to the src0 operand.
735 struct DPP_instruction
: public Instruction
{
744 struct Interp_instruction
: public Instruction
{
750 * Local and Global Data Sharing instructions
751 * Operand(0): ADDR - VGPR which supplies the address.
752 * Operand(1): DATA0 - First data VGPR.
753 * Operand(2): DATA1 - Second data VGPR.
754 * Operand(n-1): M0 - LDS size.
755 * Definition(0): VDST - Destination VGPR when results returned to VGPRs.
758 struct DS_instruction
: public Instruction
{
765 * Vector Memory Untyped-buffer Instructions
766 * Operand(0): VADDR - Address source. Can carry an index and/or offset
767 * Operand(1): SRSRC - Specifies which SGPR supplies T# (resource constant)
768 * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant)
769 * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data
772 struct MUBUF_instruction
: public Instruction
{
773 unsigned offset
; /* Unsigned byte offset - 12 bit */
774 bool offen
; /* Supply an offset from VGPR (VADDR) */
775 bool idxen
; /* Supply an index from VGPR (VADDR) */
776 bool glc
; /* globally coherent */
777 bool dlc
; /* NAVI: device level coherent */
778 bool slc
; /* system level coherent */
779 bool tfe
; /* texture fail enable */
780 bool lds
; /* Return read-data to LDS instead of VGPRs */
781 bool disable_wqm
; /* Require an exec mask without helper invocations */
783 barrier_interaction barrier
;
787 * Vector Memory Typed-buffer Instructions
788 * Operand(0): VADDR - Address source. Can carry an index and/or offset
789 * Operand(1): SRSRC - Specifies which SGPR supplies T# (resource constant)
790 * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant)
791 * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data
794 struct MTBUF_instruction
: public Instruction
{
795 uint8_t dfmt
: 4; /* Data Format of data in memory buffer */
796 uint8_t nfmt
: 3; /* Numeric format of data in memory */
797 unsigned offset
; /* Unsigned byte offset - 12 bit */
798 bool offen
; /* Supply an offset from VGPR (VADDR) */
799 bool idxen
; /* Supply an index from VGPR (VADDR) */
800 bool glc
; /* globally coherent */
801 bool dlc
; /* NAVI: device level coherent */
802 bool slc
; /* system level coherent */
803 bool tfe
; /* texture fail enable */
804 bool disable_wqm
; /* Require an exec mask without helper invocations */
806 barrier_interaction barrier
;
810 * Vector Memory Image Instructions
811 * Operand(0): VADDR - Address source. Can carry an offset or an index.
812 * Operand(1): SRSRC - Scalar GPR that specifies the resource constant.
813 * Operand(2): SSAMP - Scalar GPR that specifies sampler constant.
814 * Operand(3) / Definition(0): VDATA - Vector GPR for read / write result.
817 struct MIMG_instruction
: public Instruction
{
818 unsigned dmask
; /* Data VGPR enable mask */
819 unsigned dim
; /* NAVI: dimensionality */
820 bool unrm
; /* Force address to be un-normalized */
821 bool dlc
; /* NAVI: device level coherent */
822 bool glc
; /* globally coherent */
823 bool slc
; /* system level coherent */
824 bool tfe
; /* texture fail enable */
825 bool da
; /* declare an array */
826 bool lwe
; /* Force data to be un-normalized */
827 bool r128
; /* NAVI: Texture resource size */
828 bool a16
; /* VEGA, NAVI: Address components are 16-bits */
829 bool d16
; /* Convert 32-bit data to 16-bit data */
830 bool disable_wqm
; /* Require an exec mask without helper invocations */
832 barrier_interaction barrier
;
836 * Flat/Scratch/Global Instructions
839 * Operand(2) / Definition(0): DATA/VDST
842 struct FLAT_instruction
: public Instruction
{
843 uint16_t offset
; /* Vega/Navi only */
844 bool slc
; /* system level coherent */
845 bool glc
; /* globally coherent */
846 bool dlc
; /* NAVI: device level coherent */
849 bool disable_wqm
; /* Require an exec mask without helper invocations */
851 barrier_interaction barrier
;
854 struct Export_instruction
: public Instruction
{
855 unsigned enabled_mask
;
862 struct Pseudo_instruction
: public Instruction
{
864 PhysReg scratch_sgpr
; /* might not be valid if it's not needed */
867 struct Pseudo_branch_instruction
: public Instruction
{
868 /* target[0] is the block index of the branch target.
869 * For conditional branches, target[1] contains the fall-through alternative.
870 * A value of 0 means the target has not been initialized (BB0 cannot be a branch target).
875 struct Pseudo_barrier_instruction
: public Instruction
{
892 gfx10_wave64_bpermute
896 * Subgroup Reduction Instructions, everything except for the data to be
897 * reduced and the result as inserted by setup_reduce_temp().
898 * Operand(0): data to be reduced
899 * Operand(1): reduce temporary
900 * Operand(2): vector temporary
901 * Definition(0): result
902 * Definition(1): scalar temporary
903 * Definition(2): scalar identity temporary (not used to store identity on GFX10)
904 * Definition(3): scc clobber
905 * Definition(4): vcc clobber
908 struct Pseudo_reduction_instruction
: public Instruction
{
910 unsigned cluster_size
; // must be 0 for scans
913 struct instr_deleter_functor
{
914 void operator()(void* p
) {
920 using aco_ptr
= std::unique_ptr
<T
, instr_deleter_functor
>;
923 T
* create_instruction(aco_opcode opcode
, Format format
, uint32_t num_operands
, uint32_t num_definitions
)
925 std::size_t size
= sizeof(T
) + num_operands
* sizeof(Operand
) + num_definitions
* sizeof(Definition
);
926 char *data
= (char*) calloc(1, size
);
929 inst
->opcode
= opcode
;
930 inst
->format
= format
;
932 inst
->operands
= aco::span
<Operand
>((Operand
*)(data
+ sizeof(T
)), num_operands
);
933 inst
->definitions
= aco::span
<Definition
>((Definition
*)inst
->operands
.end(), num_definitions
);
938 constexpr bool Instruction::usesModifiers() const noexcept
940 if (isDPP() || isSDWA())
944 const VOP3A_instruction
*vop3
= static_cast<const VOP3A_instruction
*>(this);
945 for (unsigned i
= 0; i
< operands
.size(); i
++) {
946 if (vop3
->abs
[i
] || vop3
->opsel
[i
] || vop3
->neg
[i
])
949 return vop3
->opsel
[3] || vop3
->clamp
|| vop3
->omod
;
952 constexpr bool is_phi(Instruction
* instr
)
954 return instr
->opcode
== aco_opcode::p_phi
|| instr
->opcode
== aco_opcode::p_linear_phi
;
957 static inline bool is_phi(aco_ptr
<Instruction
>& instr
)
959 return is_phi(instr
.get());
962 constexpr barrier_interaction
get_barrier_interaction(Instruction
* instr
)
964 switch (instr
->format
) {
966 return static_cast<SMEM_instruction
*>(instr
)->barrier
;
968 return static_cast<MUBUF_instruction
*>(instr
)->barrier
;
970 return static_cast<MIMG_instruction
*>(instr
)->barrier
;
973 case Format::SCRATCH
:
974 return static_cast<FLAT_instruction
*>(instr
)->barrier
;
976 return barrier_shared
;
983 /* uniform indicates that leaving this block,
984 * all actives lanes stay active */
985 block_kind_uniform
= 1 << 0,
986 block_kind_top_level
= 1 << 1,
987 block_kind_loop_preheader
= 1 << 2,
988 block_kind_loop_header
= 1 << 3,
989 block_kind_loop_exit
= 1 << 4,
990 block_kind_continue
= 1 << 5,
991 block_kind_break
= 1 << 6,
992 block_kind_continue_or_break
= 1 << 7,
993 block_kind_discard
= 1 << 8,
994 block_kind_branch
= 1 << 9,
995 block_kind_merge
= 1 << 10,
996 block_kind_invert
= 1 << 11,
997 block_kind_uses_discard_if
= 1 << 12,
998 block_kind_needs_lowering
= 1 << 13,
999 block_kind_uses_demote
= 1 << 14,
1003 struct RegisterDemand
{
1004 constexpr RegisterDemand() = default;
1005 constexpr RegisterDemand(const int16_t v
, const int16_t s
) noexcept
1006 : vgpr
{v
}, sgpr
{s
} {}
1010 constexpr friend bool operator==(const RegisterDemand a
, const RegisterDemand b
) noexcept
{
1011 return a
.vgpr
== b
.vgpr
&& a
.sgpr
== b
.sgpr
;
1014 constexpr bool exceeds(const RegisterDemand other
) const noexcept
{
1015 return vgpr
> other
.vgpr
|| sgpr
> other
.sgpr
;
1018 constexpr RegisterDemand
operator+(const Temp t
) const noexcept
{
1019 if (t
.type() == RegType::sgpr
)
1020 return RegisterDemand( vgpr
, sgpr
+ t
.size() );
1022 return RegisterDemand( vgpr
+ t
.size(), sgpr
);
1025 constexpr RegisterDemand
operator+(const RegisterDemand other
) const noexcept
{
1026 return RegisterDemand(vgpr
+ other
.vgpr
, sgpr
+ other
.sgpr
);
1029 constexpr RegisterDemand
operator-(const RegisterDemand other
) const noexcept
{
1030 return RegisterDemand(vgpr
- other
.vgpr
, sgpr
- other
.sgpr
);
1033 constexpr RegisterDemand
& operator+=(const RegisterDemand other
) noexcept
{
1039 constexpr RegisterDemand
& operator-=(const RegisterDemand other
) noexcept
{
1045 constexpr RegisterDemand
& operator+=(const Temp t
) noexcept
{
1046 if (t
.type() == RegType::sgpr
)
1053 constexpr RegisterDemand
& operator-=(const Temp t
) noexcept
{
1054 if (t
.type() == RegType::sgpr
)
1061 constexpr void update(const RegisterDemand other
) noexcept
{
1062 vgpr
= std::max(vgpr
, other
.vgpr
);
1063 sgpr
= std::max(sgpr
, other
.sgpr
);
1072 unsigned offset
= 0;
1073 std::vector
<aco_ptr
<Instruction
>> instructions
;
1074 std::vector
<unsigned> logical_preds
;
1075 std::vector
<unsigned> linear_preds
;
1076 std::vector
<unsigned> logical_succs
;
1077 std::vector
<unsigned> linear_succs
;
1078 RegisterDemand register_demand
= RegisterDemand();
1079 uint16_t loop_nest_depth
= 0;
1081 int logical_idom
= -1;
1082 int linear_idom
= -1;
1083 Temp live_out_exec
= Temp();
1085 /* this information is needed for predecessors to blocks with phis when
1086 * moving out of ssa */
1087 bool scc_live_out
= false;
1088 PhysReg scratch_sgpr
= PhysReg(); /* only needs to be valid if scc_live_out != false */
1090 Block(unsigned idx
) : index(idx
) {}
1091 Block() : index(0) {}
1094 using Stage
= uint16_t;
1096 /* software stages */
1097 static constexpr Stage sw_vs
= 1 << 0;
1098 static constexpr Stage sw_gs
= 1 << 1;
1099 static constexpr Stage sw_tcs
= 1 << 2;
1100 static constexpr Stage sw_tes
= 1 << 3;
1101 static constexpr Stage sw_fs
= 1 << 4;
1102 static constexpr Stage sw_cs
= 1 << 5;
1103 static constexpr Stage sw_mask
= 0x3f;
1105 /* hardware stages (can't be OR'd, just a mask for convenience when testing multiple) */
1106 static constexpr Stage hw_vs
= 1 << 6;
1107 static constexpr Stage hw_es
= 1 << 7; /* not on GFX9. combined into GS on GFX9 (and GFX10/legacy). */
1108 static constexpr Stage hw_gs
= 1 << 8;
1109 static constexpr Stage hw_ls
= 1 << 9; /* not on GFX9. combined into HS on GFX9 (and GFX10/legacy). */
1110 static constexpr Stage hw_hs
= 1 << 10;
1111 static constexpr Stage hw_fs
= 1 << 11;
1112 static constexpr Stage hw_cs
= 1 << 12;
1113 static constexpr Stage hw_mask
= 0x7f << 6;
1115 /* possible settings of Program::stage */
1116 static constexpr Stage vertex_vs
= sw_vs
| hw_vs
;
1117 static constexpr Stage fragment_fs
= sw_fs
| hw_fs
;
1118 static constexpr Stage compute_cs
= sw_cs
| hw_cs
;
1119 static constexpr Stage tess_eval_vs
= sw_tes
| hw_vs
;
1121 static constexpr Stage ngg_vertex_gs
= sw_vs
| hw_gs
;
1122 static constexpr Stage ngg_vertex_geometry_gs
= sw_vs
| sw_gs
| hw_gs
;
1123 static constexpr Stage ngg_tess_eval_geometry_gs
= sw_tes
| sw_gs
| hw_gs
;
1124 static constexpr Stage ngg_vertex_tess_control_hs
= sw_vs
| sw_tcs
| hw_hs
;
1125 /* GFX9 (and GFX10 if NGG isn't used) */
1126 static constexpr Stage vertex_geometry_gs
= sw_vs
| sw_gs
| hw_gs
;
1127 static constexpr Stage vertex_tess_control_hs
= sw_vs
| sw_tcs
| hw_hs
;
1128 static constexpr Stage tess_eval_geometry_gs
= sw_tes
| sw_gs
| hw_gs
;
1130 static constexpr Stage vertex_ls
= sw_vs
| hw_ls
; /* vertex before tesselation control */
1131 static constexpr Stage vertex_es
= sw_vs
| hw_es
; /* vertex before geometry */
1132 static constexpr Stage tess_control_hs
= sw_tcs
| hw_hs
;
1133 static constexpr Stage tess_eval_es
= sw_tes
| hw_gs
; /* tesselation evaluation before geometry */
1134 static constexpr Stage geometry_gs
= sw_gs
| hw_gs
;
1136 class Program final
{
1138 float_mode next_fp_mode
;
1139 std::vector
<Block
> blocks
;
1140 RegisterDemand max_reg_demand
= RegisterDemand();
1141 uint16_t num_waves
= 0;
1142 uint16_t max_waves
= 0; /* maximum number of waves, regardless of register usage */
1143 ac_shader_config
* config
;
1144 struct radv_shader_info
*info
;
1145 enum chip_class chip_class
;
1146 enum radeon_family family
;
1149 Stage stage
; /* Stage */
1150 bool needs_exact
= false; /* there exists an instruction with disable_wqm = true */
1151 bool needs_wqm
= false; /* there exists a p_wqm instruction */
1152 bool wb_smem_l1_on_end
= false;
1154 std::vector
<uint8_t> constant_data
;
1155 Temp private_segment_buffer
;
1156 Temp scratch_offset
;
1158 uint16_t min_waves
= 0;
1159 uint16_t lds_alloc_granule
;
1160 uint32_t lds_limit
; /* in bytes */
1161 uint16_t vgpr_limit
;
1162 uint16_t sgpr_limit
;
1163 uint16_t physical_sgprs
;
1164 uint16_t sgpr_alloc_granule
; /* minus one. must be power of two */
1165 uint16_t vgpr_alloc_granule
; /* minus one. must be power of two */
1167 bool needs_vcc
= false;
1168 bool needs_xnack_mask
= false;
1169 bool needs_flat_scr
= false;
1171 uint32_t allocateId()
1173 assert(allocationID
<= 16777215);
1174 return allocationID
++;
1177 uint32_t peekAllocationId()
1179 return allocationID
;
1182 void setAllocationId(uint32_t id
)
1187 Block
* create_and_insert_block() {
1188 blocks
.emplace_back(blocks
.size());
1189 blocks
.back().fp_mode
= next_fp_mode
;
1190 return &blocks
.back();
1193 Block
* insert_block(Block
&& block
) {
1194 block
.index
= blocks
.size();
1195 block
.fp_mode
= next_fp_mode
;
1196 blocks
.emplace_back(std::move(block
));
1197 return &blocks
.back();
1201 uint32_t allocationID
= 1;
1205 /* live temps out per block */
1206 std::vector
<std::set
<Temp
>> live_out
;
1207 /* register demand (sgpr/vgpr) per instruction per block */
1208 std::vector
<std::vector
<RegisterDemand
>> register_demand
;
1211 void select_program(Program
*program
,
1212 unsigned shader_count
,
1213 struct nir_shader
*const *shaders
,
1214 ac_shader_config
* config
,
1215 struct radv_shader_args
*args
);
1217 void lower_wqm(Program
* program
, live
& live_vars
,
1218 const struct radv_nir_compiler_options
*options
);
1219 void lower_bool_phis(Program
* program
);
1220 void calc_min_waves(Program
* program
);
1221 void update_vgpr_sgpr_demand(Program
* program
, const RegisterDemand new_demand
);
1222 live
live_var_analysis(Program
* program
, const struct radv_nir_compiler_options
*options
);
1223 std::vector
<uint16_t> dead_code_analysis(Program
*program
);
1224 void dominator_tree(Program
* program
);
1225 void insert_exec_mask(Program
*program
);
1226 void value_numbering(Program
* program
);
1227 void optimize(Program
* program
);
1228 void setup_reduce_temp(Program
* program
);
1229 void lower_to_cssa(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
);
1230 void register_allocation(Program
*program
, std::vector
<std::set
<Temp
>> live_out_per_block
);
1231 void ssa_elimination(Program
* program
);
1232 void lower_to_hw_instr(Program
* program
);
1233 void schedule_program(Program
* program
, live
& live_vars
);
1234 void spill(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
);
1235 void insert_wait_states(Program
* program
);
1236 void insert_NOPs(Program
* program
);
1237 unsigned emit_program(Program
* program
, std::vector
<uint32_t>& code
);
1238 void print_asm(Program
*program
, std::vector
<uint32_t>& binary
,
1239 unsigned exec_size
, std::ostream
& out
);
1240 void validate(Program
* program
, FILE *output
);
1241 bool validate_ra(Program
* program
, const struct radv_nir_compiler_options
*options
, FILE *output
);
1243 void perfwarn(bool cond
, const char *msg
, Instruction
*instr
=NULL
);
1245 #define perfwarn(program, cond, msg, ...) do {} while(0)
1248 void aco_print_instr(Instruction
*instr
, FILE *output
);
1249 void aco_print_program(Program
*program
, FILE *output
);
1251 /* number of sgprs that need to be allocated but might notbe addressable as s0-s105 */
1252 uint16_t get_extra_sgprs(Program
*program
);
1254 /* get number of sgprs/vgprs allocated required to address a number of sgprs/vgprs */
1255 uint16_t get_sgpr_alloc(Program
*program
, uint16_t addressable_sgprs
);
1256 uint16_t get_vgpr_alloc(Program
*program
, uint16_t addressable_vgprs
);
1258 /* return number of addressable sgprs/vgprs for max_waves */
1259 uint16_t get_addr_sgpr_from_waves(Program
*program
, uint16_t max_waves
);
1260 uint16_t get_addr_vgpr_from_waves(Program
*program
, uint16_t max_waves
);
1263 const int16_t opcode_gfx7
[static_cast<int>(aco_opcode::num_opcodes
)];
1264 const int16_t opcode_gfx9
[static_cast<int>(aco_opcode::num_opcodes
)];
1265 const int16_t opcode_gfx10
[static_cast<int>(aco_opcode::num_opcodes
)];
1266 const std::bitset
<static_cast<int>(aco_opcode::num_opcodes
)> can_use_input_modifiers
;
1267 const std::bitset
<static_cast<int>(aco_opcode::num_opcodes
)> can_use_output_modifiers
;
1268 const char *name
[static_cast<int>(aco_opcode::num_opcodes
)];
1269 const aco::Format format
[static_cast<int>(aco_opcode::num_opcodes
)];
1272 extern const Info instr_info
;
1276 #endif /* ACO_IR_H */