2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <unordered_set>
35 #include "ac_binary.h"
36 #include "amd_family.h"
37 #include "aco_opcodes.h"
40 struct radv_nir_compiler_options
;
41 struct radv_shader_args
;
42 struct radv_shader_info
;
46 extern uint64_t debug_flags
;
50 DEBUG_VALIDATE_RA
= 0x2,
55 * Representation of the instruction's microcode encoding format
56 * Note: Some Vector ALU Formats can be combined, such that:
57 * - VOP2* | VOP3A represents a VOP2 instruction in VOP3A encoding
58 * - VOP2* | DPP represents a VOP2 instruction with data parallel primitive.
59 * - VOP2* | SDWA represents a VOP2 instruction with sub-dword addressing.
61 * (*) The same is applicable for VOP1 and VOPC instructions.
63 enum class Format
: std::uint16_t {
64 /* Pseudo Instruction Format */
66 /* Scalar ALU & Control Formats */
72 /* Scalar Memory Format */
76 /* Vector Memory Buffer Formats */
79 /* Vector Memory Image Format */
90 PSEUDO_REDUCTION
= 18,
92 /* Vector ALU Formats */
100 /* Vector Parameter Interpolation Format */
106 enum barrier_interaction
: uint8_t {
108 barrier_buffer
= 0x1,
110 barrier_atomic
= 0x4,
111 barrier_shared
= 0x8,
112 /* used for geometry shaders to ensure vertex data writes are before the
113 * GS_DONE s_sendmsg. */
114 barrier_gs_data
= 0x10,
115 /* used for geometry shaders to ensure s_sendmsg instructions are in-order. */
116 barrier_gs_sendmsg
= 0x20,
117 /* used by barriers. created by s_barrier */
118 barrier_barrier
= 0x40,
130 /* Note that v_rcp_f32, v_exp_f32, v_log_f32, v_sqrt_f32, v_rsq_f32 and
131 * v_mad_f32/v_madak_f32/v_madmk_f32/v_mac_f32 always flush denormals. */
132 fp_denorm_flush
= 0x0,
133 fp_denorm_keep
= 0x3,
137 /* matches encoding of the MODE register */
141 fp_round round16_64
:2;
143 unsigned denorm16_64
:2;
151 /* if false, optimizations which may remove infs/nan/-0.0 can be done */
152 bool preserve_signed_zero_inf_nan32
:1;
153 bool preserve_signed_zero_inf_nan16_64
:1;
154 /* if false, optimizations which may remove denormal flushing can be done */
155 bool must_flush_denorms32
:1;
156 bool must_flush_denorms16_64
:1;
157 bool care_about_round32
:1;
158 bool care_about_round16_64
:1;
160 /* Returns true if instructions using the mode "other" can safely use the
161 * current one instead. */
162 bool canReplace(float_mode other
) const noexcept
{
163 return val
== other
.val
&&
164 (preserve_signed_zero_inf_nan32
|| !other
.preserve_signed_zero_inf_nan32
) &&
165 (preserve_signed_zero_inf_nan16_64
|| !other
.preserve_signed_zero_inf_nan16_64
) &&
166 (must_flush_denorms32
|| !other
.must_flush_denorms32
) &&
167 (must_flush_denorms16_64
|| !other
.must_flush_denorms16_64
) &&
168 (care_about_round32
|| !other
.care_about_round32
) &&
169 (care_about_round16_64
|| !other
.care_about_round16_64
);
173 constexpr Format
asVOP3(Format format
) {
174 return (Format
) ((uint32_t) Format::VOP3
| (uint32_t) format
);
177 constexpr Format
asSDWA(Format format
) {
178 assert(format
== Format::VOP1
|| format
== Format::VOP2
|| format
== Format::VOPC
);
179 return (Format
) ((uint32_t) Format::SDWA
| (uint32_t) format
);
207 /* byte-sized register class */
214 /* these are used for WWM and spills to vgpr */
215 v1_linear
= v1
| (1 << 6),
216 v2_linear
= v2
| (1 << 6),
219 RegClass() = default;
220 constexpr RegClass(RC rc
)
222 constexpr RegClass(RegType type
, unsigned size
)
223 : rc((RC
) ((type
== RegType::vgpr
? 1 << 5 : 0) | size
)) {}
225 constexpr operator RC() const { return rc
; }
226 explicit operator bool() = delete;
228 constexpr RegType
type() const { return rc
<= RC::s16
? RegType::sgpr
: RegType::vgpr
; }
229 constexpr bool is_subdword() const { return rc
& (1 << 7); }
230 constexpr unsigned bytes() const { return ((unsigned) rc
& 0x1F) * (is_subdword() ? 1 : 4); }
231 //TODO: use size() less in favor of bytes()
232 constexpr unsigned size() const { return (bytes() + 3) >> 2; }
233 constexpr bool is_linear() const { return rc
<= RC::s16
|| rc
& (1 << 6); }
234 constexpr RegClass
as_linear() const { return RegClass((RC
) (rc
| (1 << 6))); }
235 constexpr RegClass
as_subdword() const { return RegClass((RC
) (rc
| 1 << 7)); }
237 static constexpr RegClass
get(RegType type
, unsigned bytes
) {
238 if (type
== RegType::sgpr
) {
239 return RegClass(type
, DIV_ROUND_UP(bytes
, 4u));
241 return bytes
% 4u ? RegClass(type
, bytes
).as_subdword() :
242 RegClass(type
, bytes
/ 4u);
250 /* transitional helper expressions */
251 static constexpr RegClass s1
{RegClass::s1
};
252 static constexpr RegClass s2
{RegClass::s2
};
253 static constexpr RegClass s3
{RegClass::s3
};
254 static constexpr RegClass s4
{RegClass::s4
};
255 static constexpr RegClass s8
{RegClass::s8
};
256 static constexpr RegClass s16
{RegClass::s16
};
257 static constexpr RegClass v1
{RegClass::v1
};
258 static constexpr RegClass v2
{RegClass::v2
};
259 static constexpr RegClass v3
{RegClass::v3
};
260 static constexpr RegClass v4
{RegClass::v4
};
261 static constexpr RegClass v5
{RegClass::v5
};
262 static constexpr RegClass v6
{RegClass::v6
};
263 static constexpr RegClass v7
{RegClass::v7
};
264 static constexpr RegClass v8
{RegClass::v8
};
265 static constexpr RegClass v1b
{RegClass::v1b
};
266 static constexpr RegClass v2b
{RegClass::v2b
};
267 static constexpr RegClass v3b
{RegClass::v3b
};
268 static constexpr RegClass v4b
{RegClass::v4b
};
269 static constexpr RegClass v6b
{RegClass::v6b
};
270 static constexpr RegClass v8b
{RegClass::v8b
};
274 * Each temporary virtual register has a
275 * register class (i.e. size and type)
279 Temp() noexcept
: id_(0), reg_class(0) {}
280 constexpr Temp(uint32_t id
, RegClass cls
) noexcept
281 : id_(id
), reg_class(uint8_t(cls
)) {}
283 constexpr uint32_t id() const noexcept
{ return id_
; }
284 constexpr RegClass
regClass() const noexcept
{ return (RegClass::RC
)reg_class
; }
286 constexpr unsigned bytes() const noexcept
{ return regClass().bytes(); }
287 constexpr unsigned size() const noexcept
{ return regClass().size(); }
288 constexpr RegType
type() const noexcept
{ return regClass().type(); }
289 constexpr bool is_linear() const noexcept
{ return regClass().is_linear(); }
291 constexpr bool operator <(Temp other
) const noexcept
{ return id() < other
.id(); }
292 constexpr bool operator==(Temp other
) const noexcept
{ return id() == other
.id(); }
293 constexpr bool operator!=(Temp other
) const noexcept
{ return id() != other
.id(); }
297 uint32_t reg_class
: 8;
302 * Represents the physical register for each
303 * Operand and Definition.
306 constexpr PhysReg() = default;
307 explicit constexpr PhysReg(unsigned r
) : reg_b(r
<< 2) {}
308 constexpr unsigned reg() const { return reg_b
>> 2; }
309 constexpr unsigned byte() const { return reg_b
& 0x3; }
310 constexpr operator unsigned() const { return reg(); }
311 constexpr bool operator==(PhysReg other
) const { return reg_b
== other
.reg_b
; }
312 constexpr bool operator!=(PhysReg other
) const { return reg_b
!= other
.reg_b
; }
313 constexpr bool operator <(PhysReg other
) const { return reg_b
< other
.reg_b
; }
314 constexpr PhysReg
advance(int bytes
) const { PhysReg res
= *this; res
.reg_b
+= bytes
; return res
; }
319 /* helper expressions for special registers */
320 static constexpr PhysReg m0
{124};
321 static constexpr PhysReg vcc
{106};
322 static constexpr PhysReg vcc_hi
{107};
323 static constexpr PhysReg sgpr_null
{125}; /* GFX10+ */
324 static constexpr PhysReg exec
{126};
325 static constexpr PhysReg exec_lo
{126};
326 static constexpr PhysReg exec_hi
{127};
327 static constexpr PhysReg vccz
{251};
328 static constexpr PhysReg execz
{252};
329 static constexpr PhysReg scc
{253};
333 * Initially, each Operand refers to either
334 * a temporary virtual register
335 * or to a constant value
336 * Temporary registers get mapped to physical register during RA
337 * Constant values are inlined into the instruction sequence.
343 : reg_(PhysReg
{128}), isTemp_(false), isFixed_(true), isConstant_(false),
344 isKill_(false), isUndef_(true), isFirstKill_(false), constSize(0),
345 isLateKill_(false) {}
347 explicit Operand(Temp r
) noexcept
354 setFixed(PhysReg
{128});
357 explicit Operand(uint8_t v
) noexcept
359 /* 8-bit constants are only used for copies and copies from any 8-bit
360 * constant can be implemented with a SDWA v_mul_u32_u24. So consider all
361 * to be inline constants. */
365 setFixed(PhysReg
{0u});
367 explicit Operand(uint16_t v
) noexcept
373 setFixed(PhysReg
{128u + v
});
374 else if (v
>= 0xFFF0) /* [-16 .. -1] */
375 setFixed(PhysReg
{192u + (0xFFFF - v
)});
376 else if (v
== 0x3800) /* 0.5 */
377 setFixed(PhysReg
{240});
378 else if (v
== 0xB800) /* -0.5 */
379 setFixed(PhysReg
{241});
380 else if (v
== 0x3C00) /* 1.0 */
381 setFixed(PhysReg
{242});
382 else if (v
== 0xBC00) /* -1.0 */
383 setFixed(PhysReg
{243});
384 else if (v
== 0x4000) /* 2.0 */
385 setFixed(PhysReg
{244});
386 else if (v
== 0xC000) /* -2.0 */
387 setFixed(PhysReg
{245});
388 else if (v
== 0x4400) /* 4.0 */
389 setFixed(PhysReg
{246});
390 else if (v
== 0xC400) /* -4.0 */
391 setFixed(PhysReg
{247});
392 else if (v
== 0x3118) /* 1/2 PI */
393 setFixed(PhysReg
{248});
394 else /* Literal Constant */
395 setFixed(PhysReg
{255});
397 explicit Operand(uint32_t v
, bool is64bit
= false) noexcept
401 constSize
= is64bit
? 3 : 2;
403 setFixed(PhysReg
{128 + v
});
404 else if (v
>= 0xFFFFFFF0) /* [-16 .. -1] */
405 setFixed(PhysReg
{192 - v
});
406 else if (v
== 0x3f000000) /* 0.5 */
407 setFixed(PhysReg
{240});
408 else if (v
== 0xbf000000) /* -0.5 */
409 setFixed(PhysReg
{241});
410 else if (v
== 0x3f800000) /* 1.0 */
411 setFixed(PhysReg
{242});
412 else if (v
== 0xbf800000) /* -1.0 */
413 setFixed(PhysReg
{243});
414 else if (v
== 0x40000000) /* 2.0 */
415 setFixed(PhysReg
{244});
416 else if (v
== 0xc0000000) /* -2.0 */
417 setFixed(PhysReg
{245});
418 else if (v
== 0x40800000) /* 4.0 */
419 setFixed(PhysReg
{246});
420 else if (v
== 0xc0800000) /* -4.0 */
421 setFixed(PhysReg
{247});
422 else { /* Literal Constant */
423 assert(!is64bit
&& "attempt to create a 64-bit literal constant");
424 setFixed(PhysReg
{255});
427 explicit Operand(uint64_t v
) noexcept
432 data_
.i
= (uint32_t) v
;
433 setFixed(PhysReg
{128 + (uint32_t) v
});
434 } else if (v
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
435 data_
.i
= (uint32_t) v
;
436 setFixed(PhysReg
{192 - (uint32_t) v
});
437 } else if (v
== 0x3FE0000000000000) { /* 0.5 */
438 data_
.i
= 0x3f000000;
439 setFixed(PhysReg
{240});
440 } else if (v
== 0xBFE0000000000000) { /* -0.5 */
441 data_
.i
= 0xbf000000;
442 setFixed(PhysReg
{241});
443 } else if (v
== 0x3FF0000000000000) { /* 1.0 */
444 data_
.i
= 0x3f800000;
445 setFixed(PhysReg
{242});
446 } else if (v
== 0xBFF0000000000000) { /* -1.0 */
447 data_
.i
= 0xbf800000;
448 setFixed(PhysReg
{243});
449 } else if (v
== 0x4000000000000000) { /* 2.0 */
450 data_
.i
= 0x40000000;
451 setFixed(PhysReg
{244});
452 } else if (v
== 0xC000000000000000) { /* -2.0 */
453 data_
.i
= 0xc0000000;
454 setFixed(PhysReg
{245});
455 } else if (v
== 0x4010000000000000) { /* 4.0 */
456 data_
.i
= 0x40800000;
457 setFixed(PhysReg
{246});
458 } else if (v
== 0xC010000000000000) { /* -4.0 */
459 data_
.i
= 0xc0800000;
460 setFixed(PhysReg
{247});
461 } else { /* Literal Constant: we don't know if it is a long or double.*/
463 assert(false && "attempt to create a 64-bit literal constant");
466 explicit Operand(RegClass type
) noexcept
469 data_
.temp
= Temp(0, type
);
470 setFixed(PhysReg
{128});
472 explicit Operand(PhysReg reg
, RegClass type
) noexcept
474 data_
.temp
= Temp(0, type
);
478 constexpr bool isTemp() const noexcept
483 constexpr void setTemp(Temp t
) noexcept
{
484 assert(!isConstant_
);
489 constexpr Temp
getTemp() const noexcept
494 constexpr uint32_t tempId() const noexcept
496 return data_
.temp
.id();
499 constexpr bool hasRegClass() const noexcept
501 return isTemp() || isUndefined();
504 constexpr RegClass
regClass() const noexcept
506 return data_
.temp
.regClass();
509 constexpr unsigned bytes() const noexcept
512 return 1 << constSize
;
514 return data_
.temp
.bytes();
517 constexpr unsigned size() const noexcept
520 return constSize
> 2 ? 2 : 1;
522 return data_
.temp
.size();
525 constexpr bool isFixed() const noexcept
530 constexpr PhysReg
physReg() const noexcept
535 constexpr void setFixed(PhysReg reg
) noexcept
537 isFixed_
= reg
!= unsigned(-1);
541 constexpr bool isConstant() const noexcept
546 constexpr bool isLiteral() const noexcept
548 return isConstant() && reg_
== 255;
551 constexpr bool isUndefined() const noexcept
556 constexpr uint32_t constantValue() const noexcept
561 constexpr bool constantEquals(uint32_t cmp
) const noexcept
563 return isConstant() && constantValue() == cmp
;
566 constexpr uint64_t constantValue64(bool signext
=false) const noexcept
568 if (constSize
== 3) {
571 else if (reg_
<= 208)
572 return 0xFFFFFFFFFFFFFFFF - (reg_
- 193);
576 return 0x3FE0000000000000;
578 return 0xBFE0000000000000;
580 return 0x3FF0000000000000;
582 return 0xBFF0000000000000;
584 return 0x4000000000000000;
586 return 0xC000000000000000;
588 return 0x4010000000000000;
590 return 0xC010000000000000;
592 } else if (constSize
== 1) {
593 return (signext
&& (data_
.i
& 0x8000u
) ? 0xffffffffffff0000ull
: 0ull) | data_
.i
;
594 } else if (constSize
== 0) {
595 return (signext
&& (data_
.i
& 0x80u
) ? 0xffffffffffffff00ull
: 0ull) | data_
.i
;
597 return (signext
&& (data_
.i
& 0x80000000u
) ? 0xffffffff00000000ull
: 0ull) | data_
.i
;
600 constexpr bool isOfType(RegType type
) const noexcept
602 return hasRegClass() && regClass().type() == type
;
605 /* Indicates that the killed operand's live range intersects with the
606 * instruction's definitions. Unlike isKill() and isFirstKill(), this is
607 * not set by liveness analysis. */
608 constexpr void setLateKill(bool flag
) noexcept
613 constexpr bool isLateKill() const noexcept
618 constexpr void setKill(bool flag
) noexcept
625 constexpr bool isKill() const noexcept
627 return isKill_
|| isFirstKill();
630 constexpr void setFirstKill(bool flag
) noexcept
637 /* When there are multiple operands killing the same temporary,
638 * isFirstKill() is only returns true for the first one. */
639 constexpr bool isFirstKill() const noexcept
644 constexpr bool isKillBeforeDef() const noexcept
646 return isKill() && !isLateKill();
649 constexpr bool isFirstKillBeforeDef() const noexcept
651 return isFirstKill() && !isLateKill();
654 constexpr bool operator == (Operand other
) const noexcept
656 if (other
.size() != size())
658 if (isFixed() != other
.isFixed() || isKillBeforeDef() != other
.isKillBeforeDef())
660 if (isFixed() && other
.isFixed() && physReg() != other
.physReg())
663 return other
.isLiteral() && other
.constantValue() == constantValue();
664 else if (isConstant())
665 return other
.isConstant() && other
.physReg() == physReg();
666 else if (isUndefined())
667 return other
.isUndefined() && other
.regClass() == regClass();
669 return other
.isTemp() && other
.getTemp() == getTemp();
675 Temp temp
= Temp(0, s1
);
682 uint8_t isConstant_
:1;
685 uint8_t isFirstKill_
:1;
687 uint8_t isLateKill_
:1;
689 /* can't initialize bit-fields in c++11, so work around using a union */
690 uint16_t control_
= 0;
696 * Definitions are the results of Instructions
697 * and refer to temporary virtual registers
698 * which are later mapped to physical registers
700 class Definition final
703 constexpr Definition() : temp(Temp(0, s1
)), reg_(0), isFixed_(0), hasHint_(0), isKill_(0), isPrecise_(0) {}
704 Definition(uint32_t index
, RegClass type
) noexcept
705 : temp(index
, type
) {}
706 explicit Definition(Temp tmp
) noexcept
708 Definition(PhysReg reg
, RegClass type
) noexcept
709 : temp(Temp(0, type
))
713 Definition(uint32_t tmpId
, PhysReg reg
, RegClass type
) noexcept
714 : temp(Temp(tmpId
, type
))
719 constexpr bool isTemp() const noexcept
724 constexpr Temp
getTemp() const noexcept
729 constexpr uint32_t tempId() const noexcept
734 constexpr void setTemp(Temp t
) noexcept
{
738 constexpr RegClass
regClass() const noexcept
740 return temp
.regClass();
743 constexpr unsigned bytes() const noexcept
748 constexpr unsigned size() const noexcept
753 constexpr bool isFixed() const noexcept
758 constexpr PhysReg
physReg() const noexcept
763 constexpr void setFixed(PhysReg reg
) noexcept
769 constexpr void setHint(PhysReg reg
) noexcept
775 constexpr bool hasHint() const noexcept
780 constexpr void setKill(bool flag
) noexcept
785 constexpr bool isKill() const noexcept
790 constexpr void setPrecise(bool precise
) noexcept
792 isPrecise_
= precise
;
795 constexpr bool isPrecise() const noexcept
801 Temp temp
= Temp(0, s1
);
808 uint8_t isPrecise_
:1;
810 /* can't initialize bit-fields in c++11, so work around using a union */
811 uint8_t control_
= 0;
822 aco::span
<Operand
> operands
;
823 aco::span
<Definition
> definitions
;
825 constexpr bool isVALU() const noexcept
827 return ((uint16_t) format
& (uint16_t) Format::VOP1
) == (uint16_t) Format::VOP1
828 || ((uint16_t) format
& (uint16_t) Format::VOP2
) == (uint16_t) Format::VOP2
829 || ((uint16_t) format
& (uint16_t) Format::VOPC
) == (uint16_t) Format::VOPC
830 || ((uint16_t) format
& (uint16_t) Format::VOP3A
) == (uint16_t) Format::VOP3A
831 || ((uint16_t) format
& (uint16_t) Format::VOP3B
) == (uint16_t) Format::VOP3B
832 || format
== Format::VOP3P
;
835 constexpr bool isSALU() const noexcept
837 return format
== Format::SOP1
||
838 format
== Format::SOP2
||
839 format
== Format::SOPC
||
840 format
== Format::SOPK
||
841 format
== Format::SOPP
;
844 constexpr bool isVMEM() const noexcept
846 return format
== Format::MTBUF
||
847 format
== Format::MUBUF
||
848 format
== Format::MIMG
;
851 constexpr bool isDPP() const noexcept
853 return (uint16_t) format
& (uint16_t) Format::DPP
;
856 constexpr bool isVOP3() const noexcept
858 return ((uint16_t) format
& (uint16_t) Format::VOP3A
) ||
859 ((uint16_t) format
& (uint16_t) Format::VOP3B
);
862 constexpr bool isSDWA() const noexcept
864 return (uint16_t) format
& (uint16_t) Format::SDWA
;
867 constexpr bool isFlatOrGlobal() const noexcept
869 return format
== Format::FLAT
|| format
== Format::GLOBAL
;
872 constexpr bool usesModifiers() const noexcept
;
874 constexpr bool reads_exec() const noexcept
876 for (const Operand
& op
: operands
) {
877 if (op
.isFixed() && op
.physReg() == exec
)
883 static_assert(sizeof(Instruction
) == 16, "Unexpected padding");
885 struct SOPK_instruction
: public Instruction
{
889 static_assert(sizeof(SOPK_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
891 struct SOPP_instruction
: public Instruction
{
895 static_assert(sizeof(SOPP_instruction
) == sizeof(Instruction
) + 8, "Unexpected padding");
897 struct SOPC_instruction
: public Instruction
{
899 static_assert(sizeof(SOPC_instruction
) == sizeof(Instruction
) + 0, "Unexpected padding");
901 struct SOP1_instruction
: public Instruction
{
903 static_assert(sizeof(SOP1_instruction
) == sizeof(Instruction
) + 0, "Unexpected padding");
905 struct SOP2_instruction
: public Instruction
{
907 static_assert(sizeof(SOP2_instruction
) == sizeof(Instruction
) + 0, "Unexpected padding");
910 * Scalar Memory Format:
911 * For s_(buffer_)load_dword*:
912 * Operand(0): SBASE - SGPR-pair which provides base address
913 * Operand(1): Offset - immediate (un)signed offset or SGPR
914 * Operand(2) / Definition(0): SDATA - SGPR for read / write result
915 * Operand(n-1): SOffset - SGPR offset (Vega only)
917 * Having no operands is also valid for instructions such as s_dcache_inv.
920 struct SMEM_instruction
: public Instruction
{
921 barrier_interaction barrier
;
922 bool glc
: 1; /* VI+: globally coherent */
923 bool dlc
: 1; /* NAVI: device level coherent */
924 bool nv
: 1; /* VEGA only: Non-volatile */
925 bool can_reorder
: 1;
926 bool disable_wqm
: 1;
927 bool prevent_overflow
: 1; /* avoid overflow when combining additions */
928 uint32_t padding
: 18;
930 static_assert(sizeof(SMEM_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
932 struct VOP1_instruction
: public Instruction
{
934 static_assert(sizeof(VOP1_instruction
) == sizeof(Instruction
) + 0, "Unexpected padding");
936 struct VOP2_instruction
: public Instruction
{
938 static_assert(sizeof(VOP2_instruction
) == sizeof(Instruction
) + 0, "Unexpected padding");
940 struct VOPC_instruction
: public Instruction
{
942 static_assert(sizeof(VOPC_instruction
) == sizeof(Instruction
) + 0, "Unexpected padding");
944 struct VOP3A_instruction
: public Instruction
{
950 uint32_t padding
: 9;
952 static_assert(sizeof(VOP3A_instruction
) == sizeof(Instruction
) + 8, "Unexpected padding");
954 struct VOP3P_instruction
: public Instruction
{
957 uint8_t opsel_lo
: 3;
958 uint8_t opsel_hi
: 3;
960 uint32_t padding
: 9;
962 static_assert(sizeof(VOP3P_instruction
) == sizeof(Instruction
) + 8, "Unexpected padding");
965 * Data Parallel Primitives Format:
966 * This format can be used for VOP1, VOP2 or VOPC instructions.
967 * The swizzle applies to the src0 operand.
970 struct DPP_instruction
: public Instruction
{
974 uint8_t row_mask
: 4;
975 uint8_t bank_mask
: 4;
977 uint32_t padding
: 7;
979 static_assert(sizeof(DPP_instruction
) == sizeof(Instruction
) + 8, "Unexpected padding");
981 enum sdwa_sel
: uint8_t {
985 sdwa_asuint
= 0x7 | 0x10,
993 /* specific values */
998 sdwa_uword0
= sdwa_isword
| 0,
999 sdwa_uword1
= sdwa_isword
| 1,
1002 sdwa_sbyte0
= sdwa_ubyte0
| sdwa_sext
,
1003 sdwa_sbyte1
= sdwa_ubyte1
| sdwa_sext
,
1004 sdwa_sbyte2
= sdwa_ubyte2
| sdwa_sext
,
1005 sdwa_sbyte3
= sdwa_ubyte3
| sdwa_sext
,
1006 sdwa_sword0
= sdwa_uword0
| sdwa_sext
,
1007 sdwa_sword1
= sdwa_uword1
| sdwa_sext
,
1008 sdwa_sdword
= sdwa_udword
| sdwa_sext
,
1010 /* register-allocated */
1011 sdwa_ubyte
= 1 | sdwa_isra
,
1012 sdwa_uword
= 2 | sdwa_isra
,
1013 sdwa_sbyte
= sdwa_ubyte
| sdwa_sext
,
1014 sdwa_sword
= sdwa_uword
| sdwa_sext
,
1018 * Sub-Dword Addressing Format:
1019 * This format can be used for VOP1, VOP2 or VOPC instructions.
1021 * omod and SGPR/constant operands are only available on GFX9+. For VOPC,
1022 * the definition doesn't have to be VCC on GFX9+.
1025 struct SDWA_instruction
: public Instruction
{
1026 /* these destination modifiers aren't available with VOPC except for
1032 bool dst_preserve
: 1;
1034 uint8_t omod
: 2; /* GFX9+ */
1035 uint32_t padding
: 4;
1037 static_assert(sizeof(SDWA_instruction
) == sizeof(Instruction
) + 8, "Unexpected padding");
1039 struct Interp_instruction
: public Instruction
{
1044 static_assert(sizeof(Interp_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
1047 * Local and Global Data Sharing instructions
1048 * Operand(0): ADDR - VGPR which supplies the address.
1049 * Operand(1): DATA0 - First data VGPR.
1050 * Operand(2): DATA1 - Second data VGPR.
1051 * Operand(n-1): M0 - LDS size.
1052 * Definition(0): VDST - Destination VGPR when results returned to VGPRs.
1055 struct DS_instruction
: public Instruction
{
1060 static_assert(sizeof(DS_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
1063 * Vector Memory Untyped-buffer Instructions
1064 * Operand(0): SRSRC - Specifies which SGPR supplies T# (resource constant)
1065 * Operand(1): VADDR - Address source. Can carry an index and/or offset
1066 * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant)
1067 * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data
1070 struct MUBUF_instruction
: public Instruction
{
1071 uint16_t offset
: 12; /* Unsigned byte offset - 12 bit */
1072 bool offen
: 1; /* Supply an offset from VGPR (VADDR) */
1073 bool idxen
: 1; /* Supply an index from VGPR (VADDR) */
1074 bool addr64
: 1; /* SI, CIK: Address size is 64-bit */
1075 bool glc
: 1; /* globally coherent */
1076 bool dlc
: 1; /* NAVI: device level coherent */
1077 bool slc
: 1; /* system level coherent */
1078 bool tfe
: 1; /* texture fail enable */
1079 bool lds
: 1; /* Return read-data to LDS instead of VGPRs */
1080 bool disable_wqm
: 1; /* Require an exec mask without helper invocations */
1081 bool can_reorder
: 1;
1083 uint8_t padding
: 1;
1084 barrier_interaction barrier
;
1086 static_assert(sizeof(MUBUF_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
1089 * Vector Memory Typed-buffer Instructions
1090 * Operand(0): SRSRC - Specifies which SGPR supplies T# (resource constant)
1091 * Operand(1): VADDR - Address source. Can carry an index and/or offset
1092 * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant)
1093 * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data
1096 struct MTBUF_instruction
: public Instruction
{
1097 uint16_t offset
; /* Unsigned byte offset - 12 bit */
1098 barrier_interaction barrier
;
1099 uint8_t dfmt
: 4; /* Data Format of data in memory buffer */
1100 uint8_t nfmt
: 3; /* Numeric format of data in memory */
1101 bool offen
: 1; /* Supply an offset from VGPR (VADDR) */
1102 bool idxen
: 1; /* Supply an index from VGPR (VADDR) */
1103 bool glc
: 1; /* globally coherent */
1104 bool dlc
: 1; /* NAVI: device level coherent */
1105 bool slc
: 1; /* system level coherent */
1106 bool tfe
: 1; /* texture fail enable */
1107 bool disable_wqm
: 1; /* Require an exec mask without helper invocations */
1108 bool can_reorder
: 1;
1109 uint32_t padding
: 25;
1111 static_assert(sizeof(MTBUF_instruction
) == sizeof(Instruction
) + 8, "Unexpected padding");
1114 * Vector Memory Image Instructions
1115 * Operand(0) SRSRC - Scalar GPR that specifies the resource constant.
1116 * Operand(1): SSAMP - Scalar GPR that specifies sampler constant.
1117 * or VDATA - Vector GPR for write data.
1118 * Operand(2): VADDR - Address source. Can carry an offset or an index.
1119 * Definition(0): VDATA - Vector GPR for read result.
1122 struct MIMG_instruction
: public Instruction
{
1123 uint8_t dmask
; /* Data VGPR enable mask */
1124 uint8_t dim
: 3; /* NAVI: dimensionality */
1125 bool unrm
: 1; /* Force address to be un-normalized */
1126 bool dlc
: 1; /* NAVI: device level coherent */
1127 bool glc
: 1; /* globally coherent */
1128 bool slc
: 1; /* system level coherent */
1129 bool tfe
: 1; /* texture fail enable */
1130 bool da
: 1; /* declare an array */
1131 bool lwe
: 1; /* Force data to be un-normalized */
1132 bool r128
: 1; /* NAVI: Texture resource size */
1133 bool a16
: 1; /* VEGA, NAVI: Address components are 16-bits */
1134 bool d16
: 1; /* Convert 32-bit data to 16-bit data */
1135 bool disable_wqm
: 1; /* Require an exec mask without helper invocations */
1136 bool can_reorder
: 1;
1137 uint8_t padding
: 1;
1138 barrier_interaction barrier
;
1140 static_assert(sizeof(MIMG_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
1143 * Flat/Scratch/Global Instructions
1146 * Operand(2) / Definition(0): DATA/VDST
1149 struct FLAT_instruction
: public Instruction
{
1150 uint16_t offset
; /* Vega/Navi only */
1151 bool slc
: 1; /* system level coherent */
1152 bool glc
: 1; /* globally coherent */
1153 bool dlc
: 1; /* NAVI: device level coherent */
1156 bool disable_wqm
: 1; /* Require an exec mask without helper invocations */
1157 bool can_reorder
: 1;
1158 uint8_t padding
: 1;
1159 barrier_interaction barrier
;
1161 static_assert(sizeof(FLAT_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
1163 struct Export_instruction
: public Instruction
{
1164 uint8_t enabled_mask
;
1166 bool compressed
: 1;
1168 bool valid_mask
: 1;
1169 uint32_t padding
: 13;
1171 static_assert(sizeof(Export_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
1173 struct Pseudo_instruction
: public Instruction
{
1174 PhysReg scratch_sgpr
; /* might not be valid if it's not needed */
1178 static_assert(sizeof(Pseudo_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
1180 struct Pseudo_branch_instruction
: public Instruction
{
1181 /* target[0] is the block index of the branch target.
1182 * For conditional branches, target[1] contains the fall-through alternative.
1183 * A value of 0 means the target has not been initialized (BB0 cannot be a branch target).
1187 static_assert(sizeof(Pseudo_branch_instruction
) == sizeof(Instruction
) + 8, "Unexpected padding");
1189 struct Pseudo_barrier_instruction
: public Instruction
{
1191 static_assert(sizeof(Pseudo_barrier_instruction
) == sizeof(Instruction
) + 0, "Unexpected padding");
1193 enum ReduceOp
: uint16_t {
1194 iadd8
, iadd16
, iadd32
, iadd64
,
1195 imul8
, imul16
, imul32
, imul64
,
1196 fadd16
, fadd32
, fadd64
,
1197 fmul16
, fmul32
, fmul64
,
1198 imin8
, imin16
, imin32
, imin64
,
1199 imax8
, imax16
, imax32
, imax64
,
1200 umin8
, umin16
, umin32
, umin64
,
1201 umax8
, umax16
, umax32
, umax64
,
1202 fmin16
, fmin32
, fmin64
,
1203 fmax16
, fmax32
, fmax64
,
1204 iand8
, iand16
, iand32
, iand64
,
1205 ior8
, ior16
, ior32
, ior64
,
1206 ixor8
, ixor16
, ixor32
, ixor64
,
1210 * Subgroup Reduction Instructions, everything except for the data to be
1211 * reduced and the result as inserted by setup_reduce_temp().
1212 * Operand(0): data to be reduced
1213 * Operand(1): reduce temporary
1214 * Operand(2): vector temporary
1215 * Definition(0): result
1216 * Definition(1): scalar temporary
1217 * Definition(2): scalar identity temporary (not used to store identity on GFX10)
1218 * Definition(3): scc clobber
1219 * Definition(4): vcc clobber
1222 struct Pseudo_reduction_instruction
: public Instruction
{
1224 uint16_t cluster_size
; // must be 0 for scans
1226 static_assert(sizeof(Pseudo_reduction_instruction
) == sizeof(Instruction
) + 4, "Unexpected padding");
1228 struct instr_deleter_functor
{
1229 void operator()(void* p
) {
1234 template<typename T
>
1235 using aco_ptr
= std::unique_ptr
<T
, instr_deleter_functor
>;
1237 template<typename T
>
1238 T
* create_instruction(aco_opcode opcode
, Format format
, uint32_t num_operands
, uint32_t num_definitions
)
1240 std::size_t size
= sizeof(T
) + num_operands
* sizeof(Operand
) + num_definitions
* sizeof(Definition
);
1241 char *data
= (char*) calloc(1, size
);
1242 T
* inst
= (T
*) data
;
1244 inst
->opcode
= opcode
;
1245 inst
->format
= format
;
1247 uint16_t operands_offset
= data
+ sizeof(T
) - (char*)&inst
->operands
;
1248 inst
->operands
= aco::span
<Operand
>(operands_offset
, num_operands
);
1249 uint16_t definitions_offset
= (char*)inst
->operands
.end() - (char*)&inst
->definitions
;
1250 inst
->definitions
= aco::span
<Definition
>(definitions_offset
, num_definitions
);
1255 constexpr bool Instruction::usesModifiers() const noexcept
1257 if (isDPP() || isSDWA())
1260 if (format
== Format::VOP3P
) {
1261 const VOP3P_instruction
*vop3p
= static_cast<const VOP3P_instruction
*>(this);
1262 for (unsigned i
= 0; i
< operands
.size(); i
++) {
1263 if (vop3p
->neg_lo
[i
] || vop3p
->neg_hi
[i
])
1266 return vop3p
->opsel_lo
|| vop3p
->opsel_hi
|| vop3p
->clamp
;
1267 } else if (isVOP3()) {
1268 const VOP3A_instruction
*vop3
= static_cast<const VOP3A_instruction
*>(this);
1269 for (unsigned i
= 0; i
< operands
.size(); i
++) {
1270 if (vop3
->abs
[i
] || vop3
->neg
[i
])
1273 return vop3
->opsel
|| vop3
->clamp
|| vop3
->omod
;
1278 constexpr bool is_phi(Instruction
* instr
)
1280 return instr
->opcode
== aco_opcode::p_phi
|| instr
->opcode
== aco_opcode::p_linear_phi
;
1283 static inline bool is_phi(aco_ptr
<Instruction
>& instr
)
1285 return is_phi(instr
.get());
1288 barrier_interaction
get_barrier_interaction(const Instruction
* instr
);
1289 bool is_dead(const std::vector
<uint16_t>& uses
, Instruction
*instr
);
1291 bool can_use_opsel(chip_class chip
, aco_opcode op
, int idx
, bool high
);
1292 bool can_use_SDWA(chip_class chip
, const aco_ptr
<Instruction
>& instr
);
1293 /* updates "instr" and returns the old instruction (or NULL if no update was needed) */
1294 aco_ptr
<Instruction
> convert_to_SDWA(chip_class chip
, aco_ptr
<Instruction
>& instr
);
1297 /* uniform indicates that leaving this block,
1298 * all actives lanes stay active */
1299 block_kind_uniform
= 1 << 0,
1300 block_kind_top_level
= 1 << 1,
1301 block_kind_loop_preheader
= 1 << 2,
1302 block_kind_loop_header
= 1 << 3,
1303 block_kind_loop_exit
= 1 << 4,
1304 block_kind_continue
= 1 << 5,
1305 block_kind_break
= 1 << 6,
1306 block_kind_continue_or_break
= 1 << 7,
1307 block_kind_discard
= 1 << 8,
1308 block_kind_branch
= 1 << 9,
1309 block_kind_merge
= 1 << 10,
1310 block_kind_invert
= 1 << 11,
1311 block_kind_uses_discard_if
= 1 << 12,
1312 block_kind_needs_lowering
= 1 << 13,
1313 block_kind_uses_demote
= 1 << 14,
1314 block_kind_export_end
= 1 << 15,
1318 struct RegisterDemand
{
1319 constexpr RegisterDemand() = default;
1320 constexpr RegisterDemand(const int16_t v
, const int16_t s
) noexcept
1321 : vgpr
{v
}, sgpr
{s
} {}
1325 constexpr friend bool operator==(const RegisterDemand a
, const RegisterDemand b
) noexcept
{
1326 return a
.vgpr
== b
.vgpr
&& a
.sgpr
== b
.sgpr
;
1329 constexpr bool exceeds(const RegisterDemand other
) const noexcept
{
1330 return vgpr
> other
.vgpr
|| sgpr
> other
.sgpr
;
1333 constexpr RegisterDemand
operator+(const Temp t
) const noexcept
{
1334 if (t
.type() == RegType::sgpr
)
1335 return RegisterDemand( vgpr
, sgpr
+ t
.size() );
1337 return RegisterDemand( vgpr
+ t
.size(), sgpr
);
1340 constexpr RegisterDemand
operator+(const RegisterDemand other
) const noexcept
{
1341 return RegisterDemand(vgpr
+ other
.vgpr
, sgpr
+ other
.sgpr
);
1344 constexpr RegisterDemand
operator-(const RegisterDemand other
) const noexcept
{
1345 return RegisterDemand(vgpr
- other
.vgpr
, sgpr
- other
.sgpr
);
1348 constexpr RegisterDemand
& operator+=(const RegisterDemand other
) noexcept
{
1354 constexpr RegisterDemand
& operator-=(const RegisterDemand other
) noexcept
{
1360 constexpr RegisterDemand
& operator+=(const Temp t
) noexcept
{
1361 if (t
.type() == RegType::sgpr
)
1368 constexpr RegisterDemand
& operator-=(const Temp t
) noexcept
{
1369 if (t
.type() == RegType::sgpr
)
1376 constexpr void update(const RegisterDemand other
) noexcept
{
1377 vgpr
= std::max(vgpr
, other
.vgpr
);
1378 sgpr
= std::max(sgpr
, other
.sgpr
);
1387 unsigned offset
= 0;
1388 std::vector
<aco_ptr
<Instruction
>> instructions
;
1389 std::vector
<unsigned> logical_preds
;
1390 std::vector
<unsigned> linear_preds
;
1391 std::vector
<unsigned> logical_succs
;
1392 std::vector
<unsigned> linear_succs
;
1393 RegisterDemand register_demand
= RegisterDemand();
1394 uint16_t loop_nest_depth
= 0;
1396 int logical_idom
= -1;
1397 int linear_idom
= -1;
1398 Temp live_out_exec
= Temp();
1400 /* this information is needed for predecessors to blocks with phis when
1401 * moving out of ssa */
1402 bool scc_live_out
= false;
1403 PhysReg scratch_sgpr
= PhysReg(); /* only needs to be valid if scc_live_out != false */
1405 Block(unsigned idx
) : index(idx
) {}
1406 Block() : index(0) {}
1409 using Stage
= uint16_t;
1411 /* software stages */
1412 static constexpr Stage sw_vs
= 1 << 0;
1413 static constexpr Stage sw_gs
= 1 << 1;
1414 static constexpr Stage sw_tcs
= 1 << 2;
1415 static constexpr Stage sw_tes
= 1 << 3;
1416 static constexpr Stage sw_fs
= 1 << 4;
1417 static constexpr Stage sw_cs
= 1 << 5;
1418 static constexpr Stage sw_gs_copy
= 1 << 6;
1419 static constexpr Stage sw_mask
= 0x7f;
1421 /* hardware stages (can't be OR'd, just a mask for convenience when testing multiple) */
1422 static constexpr Stage hw_vs
= 1 << 7;
1423 static constexpr Stage hw_es
= 1 << 8; /* Export shader: pre-GS (VS or TES) on GFX6-8. Combined into GS on GFX9 (and GFX10/legacy). */
1424 static constexpr Stage hw_gs
= 1 << 9; /* Geometry shader on GFX10/legacy and GFX6-9. */
1425 static constexpr Stage hw_ngg_gs
= 1 << 10; /* Geometry shader on GFX10/NGG. */
1426 static constexpr Stage hw_ls
= 1 << 11; /* Local shader: pre-TCS (VS) on GFX6-8. Combined into HS on GFX9 (and GFX10/legacy). */
1427 static constexpr Stage hw_hs
= 1 << 12; /* Hull shader: TCS on GFX6-8. Merged VS and TCS on GFX9-10. */
1428 static constexpr Stage hw_fs
= 1 << 13;
1429 static constexpr Stage hw_cs
= 1 << 14;
1430 static constexpr Stage hw_mask
= 0xff << 7;
1432 /* possible settings of Program::stage */
1433 static constexpr Stage vertex_vs
= sw_vs
| hw_vs
;
1434 static constexpr Stage fragment_fs
= sw_fs
| hw_fs
;
1435 static constexpr Stage compute_cs
= sw_cs
| hw_cs
;
1436 static constexpr Stage tess_eval_vs
= sw_tes
| hw_vs
;
1437 static constexpr Stage gs_copy_vs
= sw_gs_copy
| hw_vs
;
1439 static constexpr Stage ngg_vertex_gs
= sw_vs
| hw_ngg_gs
;
1440 static constexpr Stage ngg_vertex_geometry_gs
= sw_vs
| sw_gs
| hw_ngg_gs
;
1441 static constexpr Stage ngg_tess_eval_gs
= sw_tes
| hw_ngg_gs
;
1442 static constexpr Stage ngg_tess_eval_geometry_gs
= sw_tes
| sw_gs
| hw_ngg_gs
;
1443 /* GFX9 (and GFX10 if NGG isn't used) */
1444 static constexpr Stage vertex_geometry_gs
= sw_vs
| sw_gs
| hw_gs
;
1445 static constexpr Stage vertex_tess_control_hs
= sw_vs
| sw_tcs
| hw_hs
;
1446 static constexpr Stage tess_eval_geometry_gs
= sw_tes
| sw_gs
| hw_gs
;
1448 static constexpr Stage vertex_ls
= sw_vs
| hw_ls
; /* vertex before tesselation control */
1449 static constexpr Stage vertex_es
= sw_vs
| hw_es
; /* vertex before geometry */
1450 static constexpr Stage tess_control_hs
= sw_tcs
| hw_hs
;
1451 static constexpr Stage tess_eval_es
= sw_tes
| hw_es
; /* tesselation evaluation before geometry */
1452 static constexpr Stage geometry_gs
= sw_gs
| hw_gs
;
1456 statistic_instructions
,
1460 statistic_vmem_clauses
,
1461 statistic_smem_clauses
,
1462 statistic_vmem_score
,
1463 statistic_smem_score
,
1464 statistic_sgpr_presched
,
1465 statistic_vgpr_presched
,
1469 class Program final
{
1471 float_mode next_fp_mode
;
1472 std::vector
<Block
> blocks
;
1473 RegisterDemand max_reg_demand
= RegisterDemand();
1474 uint16_t num_waves
= 0;
1475 uint16_t max_waves
= 0; /* maximum number of waves, regardless of register usage */
1476 ac_shader_config
* config
;
1477 struct radv_shader_info
*info
;
1478 enum chip_class chip_class
;
1479 enum radeon_family family
;
1482 Stage stage
; /* Stage */
1483 bool needs_exact
= false; /* there exists an instruction with disable_wqm = true */
1484 bool needs_wqm
= false; /* there exists a p_wqm instruction */
1485 bool wb_smem_l1_on_end
= false;
1487 std::vector
<uint8_t> constant_data
;
1488 Temp private_segment_buffer
;
1489 Temp scratch_offset
;
1491 uint16_t min_waves
= 0;
1492 uint16_t lds_alloc_granule
;
1493 uint32_t lds_limit
; /* in bytes */
1494 bool has_16bank_lds
;
1495 uint16_t vgpr_limit
;
1496 uint16_t sgpr_limit
;
1497 uint16_t physical_sgprs
;
1498 uint16_t sgpr_alloc_granule
; /* minus one. must be power of two */
1499 uint16_t vgpr_alloc_granule
; /* minus one. must be power of two */
1500 unsigned workgroup_size
; /* if known; otherwise UINT_MAX */
1502 bool xnack_enabled
= false;
1503 bool sram_ecc_enabled
= false;
1504 bool has_fast_fma32
= false;
1506 bool needs_vcc
= false;
1507 bool needs_flat_scr
= false;
1509 bool collect_statistics
= false;
1510 uint32_t statistics
[num_statistics
];
1512 uint32_t allocateId()
1514 assert(allocationID
<= 16777215);
1515 return allocationID
++;
1518 uint32_t peekAllocationId()
1520 return allocationID
;
1523 void setAllocationId(uint32_t id
)
1528 Block
* create_and_insert_block() {
1529 blocks
.emplace_back(blocks
.size());
1530 blocks
.back().fp_mode
= next_fp_mode
;
1531 return &blocks
.back();
1534 Block
* insert_block(Block
&& block
) {
1535 block
.index
= blocks
.size();
1536 block
.fp_mode
= next_fp_mode
;
1537 blocks
.emplace_back(std::move(block
));
1538 return &blocks
.back();
1542 uint32_t allocationID
= 1;
1546 std::size_t operator()(Temp t
) const {
1550 using TempSet
= std::unordered_set
<Temp
, TempHash
>;
1553 /* live temps out per block */
1554 std::vector
<TempSet
> live_out
;
1555 /* register demand (sgpr/vgpr) per instruction per block */
1556 std::vector
<std::vector
<RegisterDemand
>> register_demand
;
1559 void select_program(Program
*program
,
1560 unsigned shader_count
,
1561 struct nir_shader
*const *shaders
,
1562 ac_shader_config
* config
,
1563 struct radv_shader_args
*args
);
1564 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
1565 ac_shader_config
* config
,
1566 struct radv_shader_args
*args
);
1568 void lower_wqm(Program
* program
, live
& live_vars
,
1569 const struct radv_nir_compiler_options
*options
);
1570 void lower_phis(Program
* program
);
1571 void calc_min_waves(Program
* program
);
1572 void update_vgpr_sgpr_demand(Program
* program
, const RegisterDemand new_demand
);
1573 live
live_var_analysis(Program
* program
, const struct radv_nir_compiler_options
*options
);
1574 std::vector
<uint16_t> dead_code_analysis(Program
*program
);
1575 void dominator_tree(Program
* program
);
1576 void insert_exec_mask(Program
*program
);
1577 void value_numbering(Program
* program
);
1578 void optimize(Program
* program
);
1579 void setup_reduce_temp(Program
* program
);
1580 void lower_to_cssa(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
);
1581 void register_allocation(Program
*program
, std::vector
<TempSet
>& live_out_per_block
);
1582 void ssa_elimination(Program
* program
);
1583 void lower_to_hw_instr(Program
* program
);
1584 void schedule_program(Program
* program
, live
& live_vars
);
1585 void spill(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
);
1586 void insert_wait_states(Program
* program
);
1587 void insert_NOPs(Program
* program
);
1588 unsigned emit_program(Program
* program
, std::vector
<uint32_t>& code
);
1589 void print_asm(Program
*program
, std::vector
<uint32_t>& binary
,
1590 unsigned exec_size
, std::ostream
& out
);
1591 void validate(Program
* program
, FILE *output
);
1592 bool validate_ra(Program
* program
, const struct radv_nir_compiler_options
*options
, FILE *output
);
1594 void perfwarn(bool cond
, const char *msg
, Instruction
*instr
=NULL
);
1596 #define perfwarn(program, cond, msg, ...) do {} while(0)
1599 void collect_presched_stats(Program
*program
);
1600 void collect_preasm_stats(Program
*program
);
1601 void collect_postasm_stats(Program
*program
, const std::vector
<uint32_t>& code
);
1603 void aco_print_instr(const Instruction
*instr
, FILE *output
);
1604 void aco_print_program(const Program
*program
, FILE *output
);
1606 /* utilities for dealing with register demand */
1607 RegisterDemand
get_live_changes(aco_ptr
<Instruction
>& instr
);
1608 RegisterDemand
get_temp_registers(aco_ptr
<Instruction
>& instr
);
1609 RegisterDemand
get_demand_before(RegisterDemand demand
, aco_ptr
<Instruction
>& instr
, aco_ptr
<Instruction
>& instr_before
);
1611 /* number of sgprs that need to be allocated but might notbe addressable as s0-s105 */
1612 uint16_t get_extra_sgprs(Program
*program
);
1614 /* get number of sgprs/vgprs allocated required to address a number of sgprs/vgprs */
1615 uint16_t get_sgpr_alloc(Program
*program
, uint16_t addressable_sgprs
);
1616 uint16_t get_vgpr_alloc(Program
*program
, uint16_t addressable_vgprs
);
1618 /* return number of addressable sgprs/vgprs for max_waves */
1619 uint16_t get_addr_sgpr_from_waves(Program
*program
, uint16_t max_waves
);
1620 uint16_t get_addr_vgpr_from_waves(Program
*program
, uint16_t max_waves
);
1623 const int16_t opcode_gfx7
[static_cast<int>(aco_opcode::num_opcodes
)];
1624 const int16_t opcode_gfx9
[static_cast<int>(aco_opcode::num_opcodes
)];
1625 const int16_t opcode_gfx10
[static_cast<int>(aco_opcode::num_opcodes
)];
1626 const std::bitset
<static_cast<int>(aco_opcode::num_opcodes
)> can_use_input_modifiers
;
1627 const std::bitset
<static_cast<int>(aco_opcode::num_opcodes
)> can_use_output_modifiers
;
1628 const std::bitset
<static_cast<int>(aco_opcode::num_opcodes
)> is_atomic
;
1629 const char *name
[static_cast<int>(aco_opcode::num_opcodes
)];
1630 const aco::Format format
[static_cast<int>(aco_opcode::num_opcodes
)];
1631 /* sizes used for input/output modifiers and constants */
1632 const unsigned operand_size
[static_cast<int>(aco_opcode::num_opcodes
)];
1633 const unsigned definition_size
[static_cast<int>(aco_opcode::num_opcodes
)];
1636 extern const Info instr_info
;
1640 #endif /* ACO_IR_H */