2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
31 #include "aco_builder.h"
32 #include "util/u_math.h"
34 #include "vulkan/radv_shader.h"
39 struct lower_context
{
41 std::vector
<aco_ptr
<Instruction
>> instructions
;
44 aco_opcode
get_reduce_opcode(chip_class chip
, ReduceOp op
) {
46 case iadd32
: return chip
>= GFX9
? aco_opcode::v_add_u32
: aco_opcode::v_add_co_u32
;
47 case imul32
: return aco_opcode::v_mul_lo_u32
;
48 case fadd32
: return aco_opcode::v_add_f32
;
49 case fmul32
: return aco_opcode::v_mul_f32
;
50 case imax32
: return aco_opcode::v_max_i32
;
51 case imin32
: return aco_opcode::v_min_i32
;
52 case umin32
: return aco_opcode::v_min_u32
;
53 case umax32
: return aco_opcode::v_max_u32
;
54 case fmin32
: return aco_opcode::v_min_f32
;
55 case fmax32
: return aco_opcode::v_max_f32
;
56 case iand32
: return aco_opcode::v_and_b32
;
57 case ixor32
: return aco_opcode::v_xor_b32
;
58 case ior32
: return aco_opcode::v_or_b32
;
59 case iadd64
: return aco_opcode::num_opcodes
;
60 case imul64
: return aco_opcode::num_opcodes
;
61 case fadd64
: return aco_opcode::v_add_f64
;
62 case fmul64
: return aco_opcode::v_mul_f64
;
63 case imin64
: return aco_opcode::num_opcodes
;
64 case imax64
: return aco_opcode::num_opcodes
;
65 case umin64
: return aco_opcode::num_opcodes
;
66 case umax64
: return aco_opcode::num_opcodes
;
67 case fmin64
: return aco_opcode::v_min_f64
;
68 case fmax64
: return aco_opcode::v_max_f64
;
69 case iand64
: return aco_opcode::num_opcodes
;
70 case ior64
: return aco_opcode::num_opcodes
;
71 case ixor64
: return aco_opcode::num_opcodes
;
72 default: return aco_opcode::num_opcodes
;
76 void emit_vadd32(Builder
& bld
, Definition def
, Operand src0
, Operand src1
)
78 Instruction
*instr
= bld
.vadd32(def
, src0
, src1
, false, Operand(s2
), true);
79 if (instr
->definitions
.size() >= 2) {
80 assert(instr
->definitions
[1].regClass() == bld
.lm
);
81 instr
->definitions
[1].setFixed(vcc
);
85 void emit_int64_dpp_op(lower_context
*ctx
, PhysReg dst_reg
, PhysReg src0_reg
, PhysReg src1_reg
,
86 PhysReg vtmp_reg
, ReduceOp op
,
87 unsigned dpp_ctrl
, unsigned row_mask
, unsigned bank_mask
, bool bound_ctrl
,
88 Operand
*identity
=NULL
)
90 Builder
bld(ctx
->program
, &ctx
->instructions
);
91 Definition dst
[] = {Definition(dst_reg
, v1
), Definition(PhysReg
{dst_reg
+1}, v1
)};
92 Definition vtmp_def
[] = {Definition(vtmp_reg
, v1
), Definition(PhysReg
{vtmp_reg
+1}, v1
)};
93 Operand src0
[] = {Operand(src0_reg
, v1
), Operand(PhysReg
{src0_reg
+1}, v1
)};
94 Operand src1
[] = {Operand(src1_reg
, v1
), Operand(PhysReg
{src1_reg
+1}, v1
)};
95 Operand src1_64
= Operand(src1_reg
, v2
);
96 Operand vtmp_op
[] = {Operand(vtmp_reg
, v1
), Operand(PhysReg
{vtmp_reg
+1}, v1
)};
97 Operand vtmp_op64
= Operand(vtmp_reg
, v2
);
99 if (ctx
->program
->chip_class
>= GFX10
) {
101 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
102 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
103 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
104 bld
.vop3(aco_opcode::v_add_co_u32_e64
, dst
[0], bld
.def(bld
.lm
, vcc
), vtmp_op
[0], src1
[0]);
106 bld
.vop2_dpp(aco_opcode::v_add_co_u32
, dst
[0], bld
.def(bld
.lm
, vcc
), src0
[0], src1
[0],
107 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
109 bld
.vop2_dpp(aco_opcode::v_addc_co_u32
, dst
[1], bld
.def(bld
.lm
, vcc
), src0
[1], src1
[1], Operand(vcc
, bld
.lm
),
110 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
111 } else if (op
== iand64
) {
112 bld
.vop2_dpp(aco_opcode::v_and_b32
, dst
[0], src0
[0], src1
[0],
113 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
114 bld
.vop2_dpp(aco_opcode::v_and_b32
, dst
[1], src0
[1], src1
[1],
115 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
116 } else if (op
== ior64
) {
117 bld
.vop2_dpp(aco_opcode::v_or_b32
, dst
[0], src0
[0], src1
[0],
118 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
119 bld
.vop2_dpp(aco_opcode::v_or_b32
, dst
[1], src0
[1], src1
[1],
120 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
121 } else if (op
== ixor64
) {
122 bld
.vop2_dpp(aco_opcode::v_xor_b32
, dst
[0], src0
[0], src1
[0],
123 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
124 bld
.vop2_dpp(aco_opcode::v_xor_b32
, dst
[1], src0
[1], src1
[1],
125 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
126 } else if (op
== umin64
|| op
== umax64
|| op
== imin64
|| op
== imax64
) {
127 aco_opcode cmp
= aco_opcode::num_opcodes
;
130 cmp
= aco_opcode::v_cmp_gt_u64
;
133 cmp
= aco_opcode::v_cmp_lt_u64
;
136 cmp
= aco_opcode::v_cmp_gt_i64
;
139 cmp
= aco_opcode::v_cmp_lt_i64
;
146 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
147 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[1], identity
[1]);
149 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
150 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
151 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[1], src0
[1],
152 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
154 bld
.vopc(cmp
, bld
.def(bld
.lm
, vcc
), vtmp_op64
, src1_64
);
155 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
[0], vtmp_op
[0], src1
[0], Operand(vcc
, bld
.lm
));
156 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
[1], vtmp_op
[1], src1
[1], Operand(vcc
, bld
.lm
));
157 } else if (op
== imul64
) {
159 * t1 = umul_lo(t4, y_lo)
161 * t0 = umul_lo(t3, y_hi)
163 * t5 = umul_hi(t3, y_lo)
164 * res_hi = iadd(t2, t5)
165 * res_lo = umul_lo(t3, y_lo)
166 * Requires that res_hi != src0[0] and res_hi != src1[0]
167 * and that vtmp[0] != res_hi.
170 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[1]);
171 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[1],
172 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
173 bld
.vop3(aco_opcode::v_mul_lo_u32
, vtmp_def
[1], vtmp_op
[0], src1
[0]);
175 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
176 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
177 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
178 bld
.vop3(aco_opcode::v_mul_lo_u32
, vtmp_def
[0], vtmp_op
[0], src1
[1]);
179 emit_vadd32(bld
, vtmp_def
[1], vtmp_op
[0], vtmp_op
[1]);
181 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
182 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
183 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
184 bld
.vop3(aco_opcode::v_mul_hi_u32
, vtmp_def
[0], vtmp_op
[0], src1
[0]);
185 emit_vadd32(bld
, dst
[1], vtmp_op
[1], vtmp_op
[0]);
187 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
188 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
189 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
190 bld
.vop3(aco_opcode::v_mul_lo_u32
, dst
[0], vtmp_op
[0], src1
[0]);
194 void emit_int64_op(lower_context
*ctx
, PhysReg dst_reg
, PhysReg src0_reg
, PhysReg src1_reg
, PhysReg vtmp
, ReduceOp op
)
196 Builder
bld(ctx
->program
, &ctx
->instructions
);
197 Definition dst
[] = {Definition(dst_reg
, v1
), Definition(PhysReg
{dst_reg
+1}, v1
)};
198 RegClass src0_rc
= src0_reg
.reg
>= 256 ? v1
: s1
;
199 Operand src0
[] = {Operand(src0_reg
, src0_rc
), Operand(PhysReg
{src0_reg
+1}, src0_rc
)};
200 Operand src1
[] = {Operand(src1_reg
, v1
), Operand(PhysReg
{src1_reg
+1}, v1
)};
201 Operand src0_64
= Operand(src0_reg
, src0_reg
.reg
>= 256 ? v2
: s2
);
202 Operand src1_64
= Operand(src1_reg
, v2
);
205 (op
== imul64
|| op
== umin64
|| op
== umax64
|| op
== imin64
|| op
== imax64
)) {
206 assert(vtmp
.reg
!= 0);
207 bld
.vop1(aco_opcode::v_mov_b32
, Definition(vtmp
, v1
), src0
[0]);
208 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+1}, v1
), src0
[1]);
210 src0
[0] = Operand(vtmp
, v1
);
211 src0
[1] = Operand(PhysReg
{vtmp
+1}, v1
);
212 src0_64
= Operand(vtmp
, v2
);
213 } else if (src0_rc
== s1
&& op
== iadd64
) {
214 assert(vtmp
.reg
!= 0);
215 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+1}, v1
), src0
[1]);
216 src0
[1] = Operand(PhysReg
{vtmp
+1}, v1
);
220 if (ctx
->program
->chip_class
>= GFX10
) {
221 bld
.vop3(aco_opcode::v_add_co_u32_e64
, dst
[0], bld
.def(bld
.lm
, vcc
), src0
[0], src1
[0]);
223 bld
.vop2(aco_opcode::v_add_co_u32
, dst
[0], bld
.def(bld
.lm
, vcc
), src0
[0], src1
[0]);
225 bld
.vop2(aco_opcode::v_addc_co_u32
, dst
[1], bld
.def(bld
.lm
, vcc
), src0
[1], src1
[1], Operand(vcc
, bld
.lm
));
226 } else if (op
== iand64
) {
227 bld
.vop2(aco_opcode::v_and_b32
, dst
[0], src0
[0], src1
[0]);
228 bld
.vop2(aco_opcode::v_and_b32
, dst
[1], src0
[1], src1
[1]);
229 } else if (op
== ior64
) {
230 bld
.vop2(aco_opcode::v_or_b32
, dst
[0], src0
[0], src1
[0]);
231 bld
.vop2(aco_opcode::v_or_b32
, dst
[1], src0
[1], src1
[1]);
232 } else if (op
== ixor64
) {
233 bld
.vop2(aco_opcode::v_xor_b32
, dst
[0], src0
[0], src1
[0]);
234 bld
.vop2(aco_opcode::v_xor_b32
, dst
[1], src0
[1], src1
[1]);
235 } else if (op
== umin64
|| op
== umax64
|| op
== imin64
|| op
== imax64
) {
236 aco_opcode cmp
= aco_opcode::num_opcodes
;
239 cmp
= aco_opcode::v_cmp_gt_u64
;
242 cmp
= aco_opcode::v_cmp_lt_u64
;
245 cmp
= aco_opcode::v_cmp_gt_i64
;
248 cmp
= aco_opcode::v_cmp_lt_i64
;
254 bld
.vopc(cmp
, bld
.def(bld
.lm
, vcc
), src0_64
, src1_64
);
255 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
[0], src0
[0], src1
[0], Operand(vcc
, bld
.lm
));
256 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
[1], src0
[1], src1
[1], Operand(vcc
, bld
.lm
));
257 } else if (op
== imul64
) {
258 if (src1_reg
== dst_reg
) {
259 /* it's fine if src0==dst but not if src1==dst */
260 std::swap(src0_reg
, src1_reg
);
261 std::swap(src0
[0], src1
[0]);
262 std::swap(src0
[1], src1
[1]);
263 std::swap(src0_64
, src1_64
);
265 assert(!(src0_reg
== src1_reg
));
266 /* t1 = umul_lo(x_hi, y_lo)
267 * t0 = umul_lo(x_lo, y_hi)
269 * t5 = umul_hi(x_lo, y_lo)
270 * res_hi = iadd(t2, t5)
271 * res_lo = umul_lo(x_lo, y_lo)
272 * assumes that it's ok to modify x_hi/y_hi, since we might not have vtmp
274 Definition
tmp0_def(PhysReg
{src0_reg
+1}, v1
);
275 Definition
tmp1_def(PhysReg
{src1_reg
+1}, v1
);
276 Operand tmp0_op
= src0
[1];
277 Operand tmp1_op
= src1
[1];
278 bld
.vop3(aco_opcode::v_mul_lo_u32
, tmp0_def
, src0
[1], src1
[0]);
279 bld
.vop3(aco_opcode::v_mul_lo_u32
, tmp1_def
, src0
[0], src1
[1]);
280 emit_vadd32(bld
, tmp0_def
, tmp1_op
, tmp0_op
);
281 bld
.vop3(aco_opcode::v_mul_hi_u32
, tmp1_def
, src0
[0], src1
[0]);
282 emit_vadd32(bld
, dst
[1], tmp0_op
, tmp1_op
);
283 bld
.vop3(aco_opcode::v_mul_lo_u32
, dst
[0], src0
[0], src1
[0]);
287 void emit_dpp_op(lower_context
*ctx
, PhysReg dst_reg
, PhysReg src0_reg
, PhysReg src1_reg
,
288 PhysReg vtmp
, ReduceOp op
, unsigned size
,
289 unsigned dpp_ctrl
, unsigned row_mask
, unsigned bank_mask
, bool bound_ctrl
,
290 Operand
*identity
=NULL
) /* for VOP3 with sparse writes */
292 Builder
bld(ctx
->program
, &ctx
->instructions
);
293 RegClass rc
= RegClass(RegType::vgpr
, size
);
294 Definition
dst(dst_reg
, rc
);
295 Operand
src0(src0_reg
, rc
);
296 Operand
src1(src1_reg
, rc
);
298 aco_opcode opcode
= get_reduce_opcode(ctx
->program
->chip_class
, op
);
299 bool vop3
= op
== imul32
|| size
== 2;
302 if (opcode
== aco_opcode::v_add_co_u32
)
303 bld
.vop2_dpp(opcode
, dst
, bld
.def(bld
.lm
, vcc
), src0
, src1
, dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
305 bld
.vop2_dpp(opcode
, dst
, src0
, src1
, dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
309 if (opcode
== aco_opcode::num_opcodes
) {
310 emit_int64_dpp_op(ctx
, dst_reg
,src0_reg
, src1_reg
, vtmp
, op
,
311 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
, identity
);
316 bld
.vop1(aco_opcode::v_mov_b32
, Definition(vtmp
, v1
), identity
[0]);
317 if (identity
&& size
>= 2)
318 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+1}, v1
), identity
[1]);
320 for (unsigned i
= 0; i
< size
; i
++)
321 bld
.vop1_dpp(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{src0_reg
+i
}, v1
),
322 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
324 bld
.vop3(opcode
, dst
, Operand(vtmp
, rc
), src1
);
327 void emit_op(lower_context
*ctx
, PhysReg dst_reg
, PhysReg src0_reg
, PhysReg src1_reg
,
328 PhysReg vtmp
, ReduceOp op
, unsigned size
)
330 Builder
bld(ctx
->program
, &ctx
->instructions
);
331 RegClass rc
= RegClass(RegType::vgpr
, size
);
332 Definition
dst(dst_reg
, rc
);
333 Operand
src0(src0_reg
, RegClass(src0_reg
.reg
>= 256 ? RegType::vgpr
: RegType::sgpr
, size
));
334 Operand
src1(src1_reg
, rc
);
336 aco_opcode opcode
= get_reduce_opcode(ctx
->program
->chip_class
, op
);
337 bool vop3
= op
== imul32
|| size
== 2;
339 if (opcode
== aco_opcode::num_opcodes
) {
340 emit_int64_op(ctx
, dst_reg
, src0_reg
, src1_reg
, vtmp
, op
);
345 bld
.vop3(opcode
, dst
, src0
, src1
);
346 } else if (opcode
== aco_opcode::v_add_co_u32
) {
347 bld
.vop2(opcode
, dst
, bld
.def(bld
.lm
, vcc
), src0
, src1
);
349 bld
.vop2(opcode
, dst
, src0
, src1
);
353 void emit_dpp_mov(lower_context
*ctx
, PhysReg dst
, PhysReg src0
, unsigned size
,
354 unsigned dpp_ctrl
, unsigned row_mask
, unsigned bank_mask
, bool bound_ctrl
)
356 Builder
bld(ctx
->program
, &ctx
->instructions
);
357 for (unsigned i
= 0; i
< size
; i
++) {
358 bld
.vop1_dpp(aco_opcode::v_mov_b32
, Definition(PhysReg
{dst
+i
}, v1
), Operand(PhysReg
{src0
+i
}, v1
),
359 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
363 uint32_t get_reduction_identity(ReduceOp op
, unsigned idx
)
381 return 0x3f800000u
; /* 1.0 */
383 return idx
? 0x3ff00000u
: 0u; /* 1.0 */
387 return idx
? 0x7fffffffu
: 0xffffffffu
;
391 return idx
? 0x80000000u
: 0;
398 return 0x7f800000u
; /* infinity */
400 return idx
? 0x7ff00000u
: 0u; /* infinity */
402 return 0xff800000u
; /* negative infinity */
404 return idx
? 0xfff00000u
: 0u; /* negative infinity */
406 unreachable("Invalid reduction operation");
412 void emit_reduction(lower_context
*ctx
, aco_opcode op
, ReduceOp reduce_op
, unsigned cluster_size
, PhysReg tmp
,
413 PhysReg stmp
, PhysReg vtmp
, PhysReg sitmp
, Operand src
, Definition dst
)
415 assert(cluster_size
== ctx
->program
->wave_size
|| op
== aco_opcode::p_reduce
);
416 assert(cluster_size
<= ctx
->program
->wave_size
);
418 Builder
bld(ctx
->program
, &ctx
->instructions
);
421 identity
[0] = Operand(get_reduction_identity(reduce_op
, 0));
422 identity
[1] = Operand(get_reduction_identity(reduce_op
, 1));
423 Operand vcndmask_identity
[2] = {identity
[0], identity
[1]};
425 /* First, copy the source to tmp and set inactive lanes to the identity */
426 bld
.sop1(Builder::s_or_saveexec
, Definition(stmp
, bld
.lm
), Definition(scc
, s1
), Definition(exec
, bld
.lm
), Operand(UINT64_MAX
), Operand(exec
, bld
.lm
));
428 for (unsigned i
= 0; i
< src
.size(); i
++) {
429 /* p_exclusive_scan needs it to be a sgpr or inline constant for the v_writelane_b32
430 * except on GFX10, where v_writelane_b32 can take a literal. */
431 if (identity
[i
].isLiteral() && op
== aco_opcode::p_exclusive_scan
&& ctx
->program
->chip_class
< GFX10
) {
432 bld
.sop1(aco_opcode::s_mov_b32
, Definition(PhysReg
{sitmp
+i
}, s1
), identity
[i
]);
433 identity
[i
] = Operand(PhysReg
{sitmp
+i
}, s1
);
435 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{tmp
+i
}, v1
), identity
[i
]);
436 vcndmask_identity
[i
] = Operand(PhysReg
{tmp
+i
}, v1
);
437 } else if (identity
[i
].isLiteral()) {
438 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{tmp
+i
}, v1
), identity
[i
]);
439 vcndmask_identity
[i
] = Operand(PhysReg
{tmp
+i
}, v1
);
443 for (unsigned i
= 0; i
< src
.size(); i
++) {
444 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(PhysReg
{tmp
+ i
}, v1
),
445 vcndmask_identity
[i
], Operand(PhysReg
{src
.physReg() + i
}, v1
),
446 Operand(stmp
, bld
.lm
));
449 bool exec_restored
= false;
450 bool dst_written
= false;
452 case aco_opcode::p_reduce
:
453 if (cluster_size
== 1) break;
454 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
455 dpp_quad_perm(1, 0, 3, 2), 0xf, 0xf, false);
456 if (cluster_size
== 2) break;
457 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
458 dpp_quad_perm(2, 3, 0, 1), 0xf, 0xf, false);
459 if (cluster_size
== 4) break;
460 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
461 dpp_row_half_mirror
, 0xf, 0xf, false);
462 if (cluster_size
== 8) break;
463 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
464 dpp_row_mirror
, 0xf, 0xf, false);
465 if (cluster_size
== 16) break;
467 if (ctx
->program
->chip_class
>= GFX10
) {
468 /* GFX10+ doesn't support row_bcast15 and row_bcast31 */
470 for (unsigned i
= 0; i
< src
.size(); i
++)
471 bld
.vop3(aco_opcode::v_permlanex16_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(0u), Operand(0u));
473 if (cluster_size
== 32 && dst
.regClass().type() == RegType::vgpr
) {
474 bld
.sop1(Builder::s_mov
, Definition(exec
, bld
.lm
), Operand(stmp
, bld
.lm
));
475 exec_restored
= true;
476 emit_op(ctx
, dst
.physReg(), tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
479 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
482 if (cluster_size
== 64) {
483 for (unsigned i
= 0; i
< src
.size(); i
++)
484 bld
.vop3(aco_opcode::v_readlane_b32
, Definition(PhysReg
{sitmp
+i
}, s1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(31u));
485 emit_op(ctx
, tmp
, sitmp
, tmp
, vtmp
, reduce_op
, src
.size());
487 } else if (cluster_size
== 32) {
488 for (unsigned i
= 0; i
< src
.size(); i
++)
489 bld
.ds(aco_opcode::ds_swizzle_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{tmp
+i
}, s1
), ds_pattern_bitmode(0x1f, 0, 0x10));
490 bld
.sop1(Builder::s_mov
, Definition(exec
, bld
.lm
), Operand(stmp
, bld
.lm
));
491 exec_restored
= true;
492 emit_op(ctx
, dst
.physReg(), vtmp
, tmp
, PhysReg
{0}, reduce_op
, src
.size());
495 assert(cluster_size
== 64);
496 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
497 dpp_row_bcast15
, 0xa, 0xf, false);
498 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
499 dpp_row_bcast31
, 0xc, 0xf, false);
502 case aco_opcode::p_exclusive_scan
:
503 if (ctx
->program
->chip_class
>= GFX10
) { /* gfx10 doesn't support wf_sr1, so emulate it */
504 /* shift rows right */
505 emit_dpp_mov(ctx
, vtmp
, tmp
, src
.size(), dpp_row_sr(1), 0xf, 0xf, true);
507 /* fill in the gaps in rows 1 and 3 */
508 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0x10000u
));
509 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(0x10000u
));
510 for (unsigned i
= 0; i
< src
.size(); i
++) {
511 Instruction
*perm
= bld
.vop3(aco_opcode::v_permlanex16_b32
,
512 Definition(PhysReg
{vtmp
+i
}, v1
),
513 Operand(PhysReg
{tmp
+i
}, v1
),
514 Operand(0xffffffffu
), Operand(0xffffffffu
)).instr
;
515 static_cast<VOP3A_instruction
*>(perm
)->opsel
[0] = true; /* FI (Fetch Inactive) */
517 bld
.sop1(Builder::s_mov
, Definition(exec
, bld
.lm
), Operand(UINT64_MAX
));
519 if (ctx
->program
->wave_size
== 64) {
520 /* fill in the gap in row 2 */
521 for (unsigned i
= 0; i
< src
.size(); i
++) {
522 bld
.vop3(aco_opcode::v_readlane_b32
, Definition(PhysReg
{sitmp
+i
}, s1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(31u));
523 bld
.vop3(aco_opcode::v_writelane_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{sitmp
+i
}, s1
), Operand(32u));
526 std::swap(tmp
, vtmp
);
528 emit_dpp_mov(ctx
, tmp
, tmp
, src
.size(), dpp_wf_sr1
, 0xf, 0xf, true);
530 for (unsigned i
= 0; i
< src
.size(); i
++) {
531 if (!identity
[i
].isConstant() || identity
[i
].constantValue()) { /* bound_ctrl should take case of this overwise */
532 if (ctx
->program
->chip_class
< GFX10
)
533 assert((identity
[i
].isConstant() && !identity
[i
].isLiteral()) || identity
[i
].physReg() == PhysReg
{sitmp
+i
});
534 bld
.vop3(aco_opcode::v_writelane_b32
, Definition(PhysReg
{tmp
+i
}, v1
),
535 identity
[i
], Operand(0u));
539 case aco_opcode::p_inclusive_scan
:
540 assert(cluster_size
== ctx
->program
->wave_size
);
541 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
542 dpp_row_sr(1), 0xf, 0xf, false, identity
);
543 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
544 dpp_row_sr(2), 0xf, 0xf, false, identity
);
545 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
546 dpp_row_sr(4), 0xf, 0xf, false, identity
);
547 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
548 dpp_row_sr(8), 0xf, 0xf, false, identity
);
549 if (ctx
->program
->chip_class
>= GFX10
) {
550 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0xffff0000u
));
551 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(0xffff0000u
));
552 for (unsigned i
= 0; i
< src
.size(); i
++) {
553 Instruction
*perm
= bld
.vop3(aco_opcode::v_permlanex16_b32
,
554 Definition(PhysReg
{vtmp
+i
}, v1
),
555 Operand(PhysReg
{tmp
+i
}, v1
),
556 Operand(0xffffffffu
), Operand(0xffffffffu
)).instr
;
557 static_cast<VOP3A_instruction
*>(perm
)->opsel
[0] = true; /* FI (Fetch Inactive) */
559 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
561 if (ctx
->program
->wave_size
== 64) {
562 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0u));
563 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(0xffffffffu
));
564 for (unsigned i
= 0; i
< src
.size(); i
++)
565 bld
.vop3(aco_opcode::v_readlane_b32
, Definition(PhysReg
{sitmp
+i
}, s1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(31u));
566 emit_op(ctx
, tmp
, sitmp
, tmp
, vtmp
, reduce_op
, src
.size());
569 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
570 dpp_row_bcast15
, 0xa, 0xf, false, identity
);
571 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
572 dpp_row_bcast31
, 0xc, 0xf, false, identity
);
576 unreachable("Invalid reduction mode");
580 bld
.sop1(Builder::s_mov
, Definition(exec
, bld
.lm
), Operand(stmp
, bld
.lm
));
582 if (op
== aco_opcode::p_reduce
&& dst
.regClass().type() == RegType::sgpr
) {
583 for (unsigned k
= 0; k
< src
.size(); k
++) {
584 bld
.vop3(aco_opcode::v_readlane_b32
, Definition(PhysReg
{dst
.physReg() + k
}, s1
),
585 Operand(PhysReg
{tmp
+ k
}, v1
), Operand(ctx
->program
->wave_size
- 1));
587 } else if (!(dst
.physReg() == tmp
) && !dst_written
) {
588 for (unsigned k
= 0; k
< src
.size(); k
++) {
589 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{dst
.physReg() + k
}, s1
),
590 Operand(PhysReg
{tmp
+ k
}, v1
));
595 struct copy_operation
{
602 void handle_operands(std::map
<PhysReg
, copy_operation
>& copy_map
, lower_context
* ctx
, chip_class chip_class
, Pseudo_instruction
*pi
)
604 Builder
bld(ctx
->program
, &ctx
->instructions
);
605 aco_ptr
<Instruction
> mov
;
606 std::map
<PhysReg
, copy_operation
>::iterator it
= copy_map
.begin();
607 std::map
<PhysReg
, copy_operation
>::iterator target
;
608 bool writes_scc
= false;
610 /* count the number of uses for each dst reg */
611 while (it
!= copy_map
.end()) {
612 if (it
->second
.op
.isConstant()) {
617 if (it
->second
.def
.physReg() == scc
)
620 assert(!pi
->tmp_in_scc
|| !(it
->second
.def
.physReg() == pi
->scratch_sgpr
));
622 /* if src and dst reg are the same, remove operation */
623 if (it
->first
== it
->second
.op
.physReg()) {
624 it
= copy_map
.erase(it
);
627 /* check if the operand reg may be overwritten by another copy operation */
628 target
= copy_map
.find(it
->second
.op
.physReg());
629 if (target
!= copy_map
.end()) {
630 target
->second
.uses
++;
636 /* first, handle paths in the location transfer graph */
637 bool preserve_scc
= pi
->tmp_in_scc
&& !writes_scc
;
638 it
= copy_map
.begin();
639 while (it
!= copy_map
.end()) {
641 /* the target reg is not used as operand for any other copy */
642 if (it
->second
.uses
== 0) {
644 /* try to coalesce 32-bit sgpr copies to 64-bit copies */
645 if (it
->second
.def
.getTemp().type() == RegType::sgpr
&& it
->second
.size
== 1 &&
646 !it
->second
.op
.isConstant() && it
->first
% 2 == it
->second
.op
.physReg() % 2) {
648 PhysReg other_def_reg
= PhysReg
{it
->first
% 2 ? it
->first
- 1 : it
->first
+ 1};
649 PhysReg other_op_reg
= PhysReg
{it
->first
% 2 ? it
->second
.op
.physReg() - 1 : it
->second
.op
.physReg() + 1};
650 std::map
<PhysReg
, copy_operation
>::iterator other
= copy_map
.find(other_def_reg
);
652 if (other
!= copy_map
.end() && !other
->second
.uses
&& other
->second
.size
== 1 &&
653 other
->second
.op
.physReg() == other_op_reg
&& !other
->second
.op
.isConstant()) {
654 std::map
<PhysReg
, copy_operation
>::iterator to_erase
= it
->first
% 2 ? it
: other
;
655 it
= it
->first
% 2 ? other
: it
;
656 copy_map
.erase(to_erase
);
661 if (it
->second
.def
.physReg() == scc
) {
662 bld
.sopc(aco_opcode::s_cmp_lg_i32
, it
->second
.def
, it
->second
.op
, Operand(0u));
664 } else if (it
->second
.size
== 2 && it
->second
.def
.getTemp().type() == RegType::sgpr
) {
665 bld
.sop1(aco_opcode::s_mov_b64
, it
->second
.def
, Operand(it
->second
.op
.physReg(), s2
));
667 bld
.copy(it
->second
.def
, it
->second
.op
);
670 /* reduce the number of uses of the operand reg by one */
671 if (!it
->second
.op
.isConstant()) {
672 for (unsigned i
= 0; i
< it
->second
.size
; i
++) {
673 target
= copy_map
.find(PhysReg
{it
->second
.op
.physReg() + i
});
674 if (target
!= copy_map
.end())
675 target
->second
.uses
--;
680 it
= copy_map
.begin();
683 /* the target reg is used as operand, check the next entry */
688 if (copy_map
.empty())
691 /* all target regs are needed as operand somewhere which means, all entries are part of a cycle */
692 bool constants
= false;
693 for (it
= copy_map
.begin(); it
!= copy_map
.end(); ++it
) {
694 assert(it
->second
.op
.isFixed());
695 if (it
->first
== it
->second
.op
.physReg())
697 /* do constants later */
698 if (it
->second
.op
.isConstant()) {
703 if (preserve_scc
&& it
->second
.def
.getTemp().type() == RegType::sgpr
)
704 assert(!(it
->second
.def
.physReg() == pi
->scratch_sgpr
));
706 /* to resolve the cycle, we have to swap the src reg with the dst reg */
707 copy_operation swap
= it
->second
;
708 assert(swap
.op
.regClass() == swap
.def
.regClass());
709 Operand def_as_op
= Operand(swap
.def
.physReg(), swap
.def
.regClass());
710 Definition op_as_def
= Definition(swap
.op
.physReg(), swap
.op
.regClass());
711 if (chip_class
>= GFX9
&& swap
.def
.getTemp().type() == RegType::vgpr
) {
712 bld
.vop1(aco_opcode::v_swap_b32
, swap
.def
, op_as_def
, swap
.op
, def_as_op
);
713 } else if (swap
.op
.physReg() == scc
|| swap
.def
.physReg() == scc
) {
714 /* we need to swap scc and another sgpr */
715 assert(!preserve_scc
);
717 PhysReg other
= swap
.op
.physReg() == scc
? swap
.def
.physReg() : swap
.op
.physReg();
719 bld
.sop1(aco_opcode::s_mov_b32
, Definition(pi
->scratch_sgpr
, s1
), Operand(scc
, s1
));
720 bld
.sopc(aco_opcode::s_cmp_lg_i32
, Definition(scc
, s1
), Operand(other
, s1
), Operand(0u));
721 bld
.sop1(aco_opcode::s_mov_b32
, Definition(other
, s1
), Operand(pi
->scratch_sgpr
, s1
));
722 } else if (swap
.def
.getTemp().type() == RegType::sgpr
) {
724 bld
.sop1(aco_opcode::s_mov_b32
, Definition(pi
->scratch_sgpr
, s1
), swap
.op
);
725 bld
.sop1(aco_opcode::s_mov_b32
, op_as_def
, def_as_op
);
726 bld
.sop1(aco_opcode::s_mov_b32
, swap
.def
, Operand(pi
->scratch_sgpr
, s1
));
728 bld
.sop2(aco_opcode::s_xor_b32
, op_as_def
, Definition(scc
, s1
), swap
.op
, def_as_op
);
729 bld
.sop2(aco_opcode::s_xor_b32
, swap
.def
, Definition(scc
, s1
), swap
.op
, def_as_op
);
730 bld
.sop2(aco_opcode::s_xor_b32
, op_as_def
, Definition(scc
, s1
), swap
.op
, def_as_op
);
733 bld
.vop2(aco_opcode::v_xor_b32
, op_as_def
, swap
.op
, def_as_op
);
734 bld
.vop2(aco_opcode::v_xor_b32
, swap
.def
, swap
.op
, def_as_op
);
735 bld
.vop2(aco_opcode::v_xor_b32
, op_as_def
, swap
.op
, def_as_op
);
738 /* change the operand reg of the target's use */
739 assert(swap
.uses
== 1);
741 for (++target
; target
!= copy_map
.end(); ++target
) {
742 if (target
->second
.op
.physReg() == it
->first
) {
743 target
->second
.op
.setFixed(swap
.op
.physReg());
749 /* copy constants into a registers which were operands */
751 for (it
= copy_map
.begin(); it
!= copy_map
.end(); ++it
) {
752 if (!it
->second
.op
.isConstant())
754 if (it
->second
.def
.physReg() == scc
) {
755 bld
.sopc(aco_opcode::s_cmp_lg_i32
, Definition(scc
, s1
), Operand(0u), Operand(it
->second
.op
.constantValue() ? 1u : 0u));
757 bld
.copy(it
->second
.def
, it
->second
.op
);
763 void lower_to_hw_instr(Program
* program
)
765 Block
*discard_block
= NULL
;
767 for (size_t i
= 0; i
< program
->blocks
.size(); i
++)
769 Block
*block
= &program
->blocks
[i
];
771 ctx
.program
= program
;
772 Builder
bld(program
, &ctx
.instructions
);
774 bool set_mode
= i
== 0 && block
->fp_mode
.val
!= program
->config
->float_mode
;
775 for (unsigned pred
: block
->linear_preds
) {
776 if (program
->blocks
[pred
].fp_mode
.val
!= block
->fp_mode
.val
) {
782 /* only allow changing modes at top-level blocks so this doesn't break
783 * the "jump over empty blocks" optimization */
784 assert(block
->kind
& block_kind_top_level
);
785 uint32_t mode
= block
->fp_mode
.val
;
786 /* "((size - 1) << 11) | register" (MODE is encoded as register 1) */
787 bld
.sopk(aco_opcode::s_setreg_imm32_b32
, Operand(mode
), (7 << 11) | 1);
790 for (size_t j
= 0; j
< block
->instructions
.size(); j
++) {
791 aco_ptr
<Instruction
>& instr
= block
->instructions
[j
];
792 aco_ptr
<Instruction
> mov
;
793 if (instr
->format
== Format::PSEUDO
) {
794 Pseudo_instruction
*pi
= (Pseudo_instruction
*)instr
.get();
796 switch (instr
->opcode
)
798 case aco_opcode::p_extract_vector
:
800 unsigned reg
= instr
->operands
[0].physReg() + instr
->operands
[1].constantValue() * instr
->definitions
[0].size();
801 RegClass rc
= RegClass(instr
->operands
[0].getTemp().type(), 1);
802 RegClass rc_def
= RegClass(instr
->definitions
[0].getTemp().type(), 1);
803 if (reg
== instr
->definitions
[0].physReg())
806 std::map
<PhysReg
, copy_operation
> copy_operations
;
807 for (unsigned i
= 0; i
< instr
->definitions
[0].size(); i
++) {
808 Definition def
= Definition(PhysReg
{instr
->definitions
[0].physReg() + i
}, rc_def
);
809 copy_operations
[def
.physReg()] = {Operand(PhysReg
{reg
+ i
}, rc
), def
, 0, 1};
811 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
814 case aco_opcode::p_create_vector
:
816 std::map
<PhysReg
, copy_operation
> copy_operations
;
817 RegClass rc_def
= RegClass(instr
->definitions
[0].getTemp().type(), 1);
818 unsigned reg_idx
= 0;
819 for (const Operand
& op
: instr
->operands
) {
820 if (op
.isConstant()) {
821 const PhysReg reg
= PhysReg
{instr
->definitions
[0].physReg() + reg_idx
};
822 const Definition def
= Definition(reg
, rc_def
);
823 copy_operations
[reg
] = {op
, def
, 0, 1};
828 RegClass rc_op
= RegClass(op
.getTemp().type(), 1);
829 for (unsigned j
= 0; j
< op
.size(); j
++)
831 const Operand copy_op
= Operand(PhysReg
{op
.physReg() + j
}, rc_op
);
832 const Definition def
= Definition(PhysReg
{instr
->definitions
[0].physReg() + reg_idx
}, rc_def
);
833 copy_operations
[def
.physReg()] = {copy_op
, def
, 0, 1};
837 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
840 case aco_opcode::p_split_vector
:
842 std::map
<PhysReg
, copy_operation
> copy_operations
;
843 RegClass rc_op
= instr
->operands
[0].isConstant() ? s1
: RegClass(instr
->operands
[0].regClass().type(), 1);
844 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
845 unsigned k
= instr
->definitions
[i
].size();
846 RegClass rc_def
= RegClass(instr
->definitions
[i
].getTemp().type(), 1);
847 for (unsigned j
= 0; j
< k
; j
++) {
848 Operand op
= Operand(PhysReg
{instr
->operands
[0].physReg() + (i
*k
+j
)}, rc_op
);
849 Definition def
= Definition(PhysReg
{instr
->definitions
[i
].physReg() + j
}, rc_def
);
850 copy_operations
[def
.physReg()] = {op
, def
, 0, 1};
853 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
856 case aco_opcode::p_parallelcopy
:
857 case aco_opcode::p_wqm
:
859 std::map
<PhysReg
, copy_operation
> copy_operations
;
860 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
862 Operand operand
= instr
->operands
[i
];
863 if (operand
.isConstant() || operand
.size() == 1) {
864 assert(instr
->definitions
[i
].size() == 1);
865 copy_operations
[instr
->definitions
[i
].physReg()] = {operand
, instr
->definitions
[i
], 0, 1};
867 RegClass def_rc
= RegClass(instr
->definitions
[i
].regClass().type(), 1);
868 RegClass op_rc
= RegClass(operand
.getTemp().type(), 1);
869 for (unsigned j
= 0; j
< operand
.size(); j
++)
871 Operand op
= Operand(PhysReg
{instr
->operands
[i
].physReg() + j
}, op_rc
);
872 Definition def
= Definition(PhysReg
{instr
->definitions
[i
].physReg() + j
}, def_rc
);
873 copy_operations
[def
.physReg()] = {op
, def
, 0, 1};
877 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
880 case aco_opcode::p_exit_early_if
:
882 /* don't bother with an early exit at the end of the program */
883 if (block
->instructions
[j
+ 1]->opcode
== aco_opcode::p_logical_end
&&
884 block
->instructions
[j
+ 2]->opcode
== aco_opcode::s_endpgm
) {
888 if (!discard_block
) {
889 discard_block
= program
->create_and_insert_block();
890 block
= &program
->blocks
[i
];
892 bld
.reset(discard_block
);
893 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
894 0, V_008DFC_SQ_EXP_NULL
, false, true, true);
895 if (program
->wb_smem_l1_on_end
)
896 bld
.smem(aco_opcode::s_dcache_wb
);
897 bld
.sopp(aco_opcode::s_endpgm
);
899 bld
.reset(&ctx
.instructions
);
902 //TODO: exec can be zero here with block_kind_discard
904 assert(instr
->operands
[0].physReg() == scc
);
905 bld
.sopp(aco_opcode::s_cbranch_scc0
, instr
->operands
[0], discard_block
->index
);
907 discard_block
->linear_preds
.push_back(block
->index
);
908 block
->linear_succs
.push_back(discard_block
->index
);
911 case aco_opcode::p_spill
:
913 assert(instr
->operands
[0].regClass() == v1
.as_linear());
914 for (unsigned i
= 0; i
< instr
->operands
[2].size(); i
++) {
915 bld
.vop3(aco_opcode::v_writelane_b32
, bld
.def(v1
, instr
->operands
[0].physReg()),
916 Operand(PhysReg
{instr
->operands
[2].physReg() + i
}, s1
),
917 Operand(instr
->operands
[1].constantValue() + i
));
921 case aco_opcode::p_reload
:
923 assert(instr
->operands
[0].regClass() == v1
.as_linear());
924 for (unsigned i
= 0; i
< instr
->definitions
[0].size(); i
++) {
925 bld
.vop3(aco_opcode::v_readlane_b32
,
926 bld
.def(s1
, PhysReg
{instr
->definitions
[0].physReg() + i
}),
927 instr
->operands
[0], Operand(instr
->operands
[1].constantValue() + i
));
931 case aco_opcode::p_as_uniform
:
933 if (instr
->operands
[0].isConstant() || instr
->operands
[0].regClass().type() == RegType::sgpr
) {
934 std::map
<PhysReg
, copy_operation
> copy_operations
;
935 Operand operand
= instr
->operands
[0];
936 if (operand
.isConstant() || operand
.size() == 1) {
937 assert(instr
->definitions
[0].size() == 1);
938 copy_operations
[instr
->definitions
[0].physReg()] = {operand
, instr
->definitions
[0], 0, 1};
940 for (unsigned i
= 0; i
< operand
.size(); i
++)
942 Operand op
= Operand(PhysReg
{operand
.physReg() + i
}, s1
);
943 Definition def
= Definition(PhysReg
{instr
->definitions
[0].physReg() + i
}, s1
);
944 copy_operations
[def
.physReg()] = {op
, def
, 0, 1};
948 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
950 assert(instr
->operands
[0].regClass().type() == RegType::vgpr
);
951 assert(instr
->definitions
[0].regClass().type() == RegType::sgpr
);
952 assert(instr
->operands
[0].size() == instr
->definitions
[0].size());
953 for (unsigned i
= 0; i
< instr
->definitions
[0].size(); i
++) {
954 bld
.vop1(aco_opcode::v_readfirstlane_b32
,
955 bld
.def(s1
, PhysReg
{instr
->definitions
[0].physReg() + i
}),
956 Operand(PhysReg
{instr
->operands
[0].physReg() + i
}, v1
));
964 } else if (instr
->format
== Format::PSEUDO_BRANCH
) {
965 Pseudo_branch_instruction
* branch
= static_cast<Pseudo_branch_instruction
*>(instr
.get());
966 /* check if all blocks from current to target are empty */
967 bool can_remove
= block
->index
< branch
->target
[0];
968 for (unsigned i
= block
->index
+ 1; can_remove
&& i
< branch
->target
[0]; i
++) {
969 if (program
->blocks
[i
].instructions
.size())
975 switch (instr
->opcode
) {
976 case aco_opcode::p_branch
:
977 assert(block
->linear_succs
[0] == branch
->target
[0]);
978 bld
.sopp(aco_opcode::s_branch
, branch
->target
[0]);
980 case aco_opcode::p_cbranch_nz
:
981 assert(block
->linear_succs
[1] == branch
->target
[0]);
982 if (branch
->operands
[0].physReg() == exec
)
983 bld
.sopp(aco_opcode::s_cbranch_execnz
, branch
->target
[0]);
984 else if (branch
->operands
[0].physReg() == vcc
)
985 bld
.sopp(aco_opcode::s_cbranch_vccnz
, branch
->target
[0]);
987 assert(branch
->operands
[0].physReg() == scc
);
988 bld
.sopp(aco_opcode::s_cbranch_scc1
, branch
->target
[0]);
991 case aco_opcode::p_cbranch_z
:
992 assert(block
->linear_succs
[1] == branch
->target
[0]);
993 if (branch
->operands
[0].physReg() == exec
)
994 bld
.sopp(aco_opcode::s_cbranch_execz
, branch
->target
[0]);
995 else if (branch
->operands
[0].physReg() == vcc
)
996 bld
.sopp(aco_opcode::s_cbranch_vccz
, branch
->target
[0]);
998 assert(branch
->operands
[0].physReg() == scc
);
999 bld
.sopp(aco_opcode::s_cbranch_scc0
, branch
->target
[0]);
1003 unreachable("Unknown Pseudo branch instruction!");
1006 } else if (instr
->format
== Format::PSEUDO_REDUCTION
) {
1007 Pseudo_reduction_instruction
* reduce
= static_cast<Pseudo_reduction_instruction
*>(instr
.get());
1008 if (reduce
->reduce_op
== gfx10_wave64_bpermute
) {
1009 /* Only makes sense on GFX10 wave64 */
1010 assert(program
->chip_class
>= GFX10
);
1011 assert(program
->info
->wave_size
== 64);
1012 assert(instr
->definitions
[0].regClass() == v1
); /* Destination */
1013 assert(instr
->definitions
[1].regClass() == s2
); /* Temp EXEC */
1014 assert(instr
->definitions
[1].physReg() != vcc
);
1015 assert(instr
->definitions
[2].physReg() == scc
); /* SCC clobber */
1016 assert(instr
->operands
[0].physReg() == vcc
); /* Compare */
1017 assert(instr
->operands
[1].regClass() == v2
.as_linear()); /* Temp VGPR pair */
1018 assert(instr
->operands
[2].regClass() == v1
); /* Indices x4 */
1019 assert(instr
->operands
[3].regClass() == v1
); /* Input data */
1021 PhysReg shared_vgpr_reg_lo
= PhysReg(align(program
->config
->num_vgprs
, 4) + 256);
1022 PhysReg shared_vgpr_reg_hi
= PhysReg(shared_vgpr_reg_lo
+ 1);
1023 Operand compare
= instr
->operands
[0];
1024 Operand
tmp1(instr
->operands
[1].physReg(), v1
);
1025 Operand
tmp2(PhysReg(instr
->operands
[1].physReg() + 1), v1
);
1026 Operand index_x4
= instr
->operands
[2];
1027 Operand input_data
= instr
->operands
[3];
1028 Definition
shared_vgpr_lo(shared_vgpr_reg_lo
, v1
);
1029 Definition
shared_vgpr_hi(shared_vgpr_reg_hi
, v1
);
1030 Definition
def_temp1(tmp1
.physReg(), v1
);
1031 Definition
def_temp2(tmp2
.physReg(), v1
);
1033 /* Save EXEC and set it for all lanes */
1034 bld
.sop1(aco_opcode::s_or_saveexec_b64
, instr
->definitions
[1], instr
->definitions
[2],
1035 Definition(exec
, s2
), Operand((uint64_t)-1), Operand(exec
, s2
));
1037 /* HI: Copy data from high lanes 32-63 to shared vgpr */
1038 bld
.vop1_dpp(aco_opcode::v_mov_b32
, shared_vgpr_hi
, input_data
, dpp_quad_perm(0, 1, 2, 3), 0xc, 0xf, false);
1040 /* LO: Copy data from low lanes 0-31 to shared vgpr */
1041 bld
.vop1_dpp(aco_opcode::v_mov_b32
, shared_vgpr_lo
, input_data
, dpp_quad_perm(0, 1, 2, 3), 0x3, 0xf, false);
1042 /* LO: Copy shared vgpr (high lanes' data) to output vgpr */
1043 bld
.vop1_dpp(aco_opcode::v_mov_b32
, def_temp1
, Operand(shared_vgpr_reg_hi
, v1
), dpp_quad_perm(0, 1, 2, 3), 0x3, 0xf, false);
1045 /* HI: Copy shared vgpr (low lanes' data) to output vgpr */
1046 bld
.vop1_dpp(aco_opcode::v_mov_b32
, def_temp1
, Operand(shared_vgpr_reg_lo
, v1
), dpp_quad_perm(0, 1, 2, 3), 0xc, 0xf, false);
1048 /* Permute the original input */
1049 bld
.ds(aco_opcode::ds_bpermute_b32
, def_temp2
, index_x4
, input_data
);
1050 /* Permute the swapped input */
1051 bld
.ds(aco_opcode::ds_bpermute_b32
, def_temp1
, index_x4
, tmp1
);
1053 /* Restore saved EXEC */
1054 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(instr
->definitions
[1].physReg(), s2
));
1055 /* Choose whether to use the original or swapped */
1056 bld
.vop2(aco_opcode::v_cndmask_b32
, instr
->definitions
[0], tmp1
, tmp2
, compare
);
1058 emit_reduction(&ctx
, reduce
->opcode
, reduce
->reduce_op
, reduce
->cluster_size
,
1059 reduce
->operands
[1].physReg(), // tmp
1060 reduce
->definitions
[1].physReg(), // stmp
1061 reduce
->operands
[2].physReg(), // vtmp
1062 reduce
->definitions
[2].physReg(), // sitmp
1063 reduce
->operands
[0], reduce
->definitions
[0]);
1066 ctx
.instructions
.emplace_back(std::move(instr
));
1070 block
->instructions
.swap(ctx
.instructions
);