2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
31 #include "aco_builder.h"
32 #include "util/u_math.h"
34 #include "vulkan/radv_shader.h"
39 struct lower_context
{
41 std::vector
<aco_ptr
<Instruction
>> instructions
;
44 aco_opcode
get_reduce_opcode(chip_class chip
, ReduceOp op
) {
45 /* Because some 16-bit instructions are already VOP3 on GFX10, we use the
46 * 32-bit opcodes (VOP2) which allows to remove the tempory VGPR and to use
47 * DPP with the arithmetic instructions. This requires to sign-extend.
51 case iadd16
: return chip
>= GFX10
? aco_opcode::v_add_u32
: aco_opcode::v_add_u16
;
53 case imul16
: return chip
>= GFX10
? aco_opcode::v_mul_lo_u16_e64
: aco_opcode::v_mul_lo_u16
;
54 case fadd16
: return aco_opcode::v_add_f16
;
55 case fmul16
: return aco_opcode::v_mul_f16
;
57 case imax16
: return chip
>= GFX10
? aco_opcode::v_max_i32
: aco_opcode::v_max_i16
;
59 case imin16
: return chip
>= GFX10
? aco_opcode::v_min_i32
: aco_opcode::v_min_i16
;
61 case umin16
: return chip
>= GFX10
? aco_opcode::v_min_u32
: aco_opcode::v_min_u16
;
63 case umax16
: return chip
>= GFX10
? aco_opcode::v_max_u32
: aco_opcode::v_max_u16
;
64 case fmin16
: return aco_opcode::v_min_f16
;
65 case fmax16
: return aco_opcode::v_max_f16
;
66 case iadd32
: return chip
>= GFX9
? aco_opcode::v_add_u32
: aco_opcode::v_add_co_u32
;
67 case imul32
: return aco_opcode::v_mul_lo_u32
;
68 case fadd32
: return aco_opcode::v_add_f32
;
69 case fmul32
: return aco_opcode::v_mul_f32
;
70 case imax32
: return aco_opcode::v_max_i32
;
71 case imin32
: return aco_opcode::v_min_i32
;
72 case umin32
: return aco_opcode::v_min_u32
;
73 case umax32
: return aco_opcode::v_max_u32
;
74 case fmin32
: return aco_opcode::v_min_f32
;
75 case fmax32
: return aco_opcode::v_max_f32
;
78 case iand32
: return aco_opcode::v_and_b32
;
81 case ixor32
: return aco_opcode::v_xor_b32
;
84 case ior32
: return aco_opcode::v_or_b32
;
85 case iadd64
: return aco_opcode::num_opcodes
;
86 case imul64
: return aco_opcode::num_opcodes
;
87 case fadd64
: return aco_opcode::v_add_f64
;
88 case fmul64
: return aco_opcode::v_mul_f64
;
89 case imin64
: return aco_opcode::num_opcodes
;
90 case imax64
: return aco_opcode::num_opcodes
;
91 case umin64
: return aco_opcode::num_opcodes
;
92 case umax64
: return aco_opcode::num_opcodes
;
93 case fmin64
: return aco_opcode::v_min_f64
;
94 case fmax64
: return aco_opcode::v_max_f64
;
95 case iand64
: return aco_opcode::num_opcodes
;
96 case ior64
: return aco_opcode::num_opcodes
;
97 case ixor64
: return aco_opcode::num_opcodes
;
98 default: return aco_opcode::num_opcodes
;
102 bool is_vop3_reduce_opcode(aco_opcode opcode
)
104 /* 64-bit reductions are VOP3. */
105 if (opcode
== aco_opcode::num_opcodes
)
108 return instr_info
.format
[(int)opcode
] == Format::VOP3
;
111 void emit_vadd32(Builder
& bld
, Definition def
, Operand src0
, Operand src1
)
113 Instruction
*instr
= bld
.vadd32(def
, src0
, src1
, false, Operand(s2
), true);
114 if (instr
->definitions
.size() >= 2) {
115 assert(instr
->definitions
[1].regClass() == bld
.lm
);
116 instr
->definitions
[1].setFixed(vcc
);
120 void emit_int64_dpp_op(lower_context
*ctx
, PhysReg dst_reg
, PhysReg src0_reg
, PhysReg src1_reg
,
121 PhysReg vtmp_reg
, ReduceOp op
,
122 unsigned dpp_ctrl
, unsigned row_mask
, unsigned bank_mask
, bool bound_ctrl
,
123 Operand
*identity
=NULL
)
125 Builder
bld(ctx
->program
, &ctx
->instructions
);
126 Definition dst
[] = {Definition(dst_reg
, v1
), Definition(PhysReg
{dst_reg
+1}, v1
)};
127 Definition vtmp_def
[] = {Definition(vtmp_reg
, v1
), Definition(PhysReg
{vtmp_reg
+1}, v1
)};
128 Operand src0
[] = {Operand(src0_reg
, v1
), Operand(PhysReg
{src0_reg
+1}, v1
)};
129 Operand src1
[] = {Operand(src1_reg
, v1
), Operand(PhysReg
{src1_reg
+1}, v1
)};
130 Operand src1_64
= Operand(src1_reg
, v2
);
131 Operand vtmp_op
[] = {Operand(vtmp_reg
, v1
), Operand(PhysReg
{vtmp_reg
+1}, v1
)};
132 Operand vtmp_op64
= Operand(vtmp_reg
, v2
);
134 if (ctx
->program
->chip_class
>= GFX10
) {
136 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
137 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
138 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
139 bld
.vop3(aco_opcode::v_add_co_u32_e64
, dst
[0], bld
.def(bld
.lm
, vcc
), vtmp_op
[0], src1
[0]);
141 bld
.vop2_dpp(aco_opcode::v_add_co_u32
, dst
[0], bld
.def(bld
.lm
, vcc
), src0
[0], src1
[0],
142 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
144 bld
.vop2_dpp(aco_opcode::v_addc_co_u32
, dst
[1], bld
.def(bld
.lm
, vcc
), src0
[1], src1
[1], Operand(vcc
, bld
.lm
),
145 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
146 } else if (op
== iand64
) {
147 bld
.vop2_dpp(aco_opcode::v_and_b32
, dst
[0], src0
[0], src1
[0],
148 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
149 bld
.vop2_dpp(aco_opcode::v_and_b32
, dst
[1], src0
[1], src1
[1],
150 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
151 } else if (op
== ior64
) {
152 bld
.vop2_dpp(aco_opcode::v_or_b32
, dst
[0], src0
[0], src1
[0],
153 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
154 bld
.vop2_dpp(aco_opcode::v_or_b32
, dst
[1], src0
[1], src1
[1],
155 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
156 } else if (op
== ixor64
) {
157 bld
.vop2_dpp(aco_opcode::v_xor_b32
, dst
[0], src0
[0], src1
[0],
158 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
159 bld
.vop2_dpp(aco_opcode::v_xor_b32
, dst
[1], src0
[1], src1
[1],
160 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
161 } else if (op
== umin64
|| op
== umax64
|| op
== imin64
|| op
== imax64
) {
162 aco_opcode cmp
= aco_opcode::num_opcodes
;
165 cmp
= aco_opcode::v_cmp_gt_u64
;
168 cmp
= aco_opcode::v_cmp_lt_u64
;
171 cmp
= aco_opcode::v_cmp_gt_i64
;
174 cmp
= aco_opcode::v_cmp_lt_i64
;
181 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
182 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[1], identity
[1]);
184 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
185 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
186 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[1], src0
[1],
187 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
189 bld
.vopc(cmp
, bld
.def(bld
.lm
, vcc
), vtmp_op64
, src1_64
);
190 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
[0], vtmp_op
[0], src1
[0], Operand(vcc
, bld
.lm
));
191 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
[1], vtmp_op
[1], src1
[1], Operand(vcc
, bld
.lm
));
192 } else if (op
== imul64
) {
194 * t1 = umul_lo(t4, y_lo)
196 * t0 = umul_lo(t3, y_hi)
198 * t5 = umul_hi(t3, y_lo)
199 * res_hi = iadd(t2, t5)
200 * res_lo = umul_lo(t3, y_lo)
201 * Requires that res_hi != src0[0] and res_hi != src1[0]
202 * and that vtmp[0] != res_hi.
205 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[1]);
206 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[1],
207 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
208 bld
.vop3(aco_opcode::v_mul_lo_u32
, vtmp_def
[1], vtmp_op
[0], src1
[0]);
210 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
211 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
212 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
213 bld
.vop3(aco_opcode::v_mul_lo_u32
, vtmp_def
[0], vtmp_op
[0], src1
[1]);
214 emit_vadd32(bld
, vtmp_def
[1], vtmp_op
[0], vtmp_op
[1]);
216 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
217 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
218 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
219 bld
.vop3(aco_opcode::v_mul_hi_u32
, vtmp_def
[0], vtmp_op
[0], src1
[0]);
220 emit_vadd32(bld
, dst
[1], vtmp_op
[1], vtmp_op
[0]);
222 bld
.vop1(aco_opcode::v_mov_b32
, vtmp_def
[0], identity
[0]);
223 bld
.vop1_dpp(aco_opcode::v_mov_b32
, vtmp_def
[0], src0
[0],
224 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
225 bld
.vop3(aco_opcode::v_mul_lo_u32
, dst
[0], vtmp_op
[0], src1
[0]);
229 void emit_int64_op(lower_context
*ctx
, PhysReg dst_reg
, PhysReg src0_reg
, PhysReg src1_reg
, PhysReg vtmp
, ReduceOp op
)
231 Builder
bld(ctx
->program
, &ctx
->instructions
);
232 Definition dst
[] = {Definition(dst_reg
, v1
), Definition(PhysReg
{dst_reg
+1}, v1
)};
233 RegClass src0_rc
= src0_reg
.reg() >= 256 ? v1
: s1
;
234 Operand src0
[] = {Operand(src0_reg
, src0_rc
), Operand(PhysReg
{src0_reg
+1}, src0_rc
)};
235 Operand src1
[] = {Operand(src1_reg
, v1
), Operand(PhysReg
{src1_reg
+1}, v1
)};
236 Operand src0_64
= Operand(src0_reg
, src0_reg
.reg() >= 256 ? v2
: s2
);
237 Operand src1_64
= Operand(src1_reg
, v2
);
240 (op
== imul64
|| op
== umin64
|| op
== umax64
|| op
== imin64
|| op
== imax64
)) {
241 assert(vtmp
.reg() != 0);
242 bld
.vop1(aco_opcode::v_mov_b32
, Definition(vtmp
, v1
), src0
[0]);
243 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+1}, v1
), src0
[1]);
245 src0
[0] = Operand(vtmp
, v1
);
246 src0
[1] = Operand(PhysReg
{vtmp
+1}, v1
);
247 src0_64
= Operand(vtmp
, v2
);
248 } else if (src0_rc
== s1
&& op
== iadd64
) {
249 assert(vtmp
.reg() != 0);
250 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+1}, v1
), src0
[1]);
251 src0
[1] = Operand(PhysReg
{vtmp
+1}, v1
);
255 if (ctx
->program
->chip_class
>= GFX10
) {
256 bld
.vop3(aco_opcode::v_add_co_u32_e64
, dst
[0], bld
.def(bld
.lm
, vcc
), src0
[0], src1
[0]);
258 bld
.vop2(aco_opcode::v_add_co_u32
, dst
[0], bld
.def(bld
.lm
, vcc
), src0
[0], src1
[0]);
260 bld
.vop2(aco_opcode::v_addc_co_u32
, dst
[1], bld
.def(bld
.lm
, vcc
), src0
[1], src1
[1], Operand(vcc
, bld
.lm
));
261 } else if (op
== iand64
) {
262 bld
.vop2(aco_opcode::v_and_b32
, dst
[0], src0
[0], src1
[0]);
263 bld
.vop2(aco_opcode::v_and_b32
, dst
[1], src0
[1], src1
[1]);
264 } else if (op
== ior64
) {
265 bld
.vop2(aco_opcode::v_or_b32
, dst
[0], src0
[0], src1
[0]);
266 bld
.vop2(aco_opcode::v_or_b32
, dst
[1], src0
[1], src1
[1]);
267 } else if (op
== ixor64
) {
268 bld
.vop2(aco_opcode::v_xor_b32
, dst
[0], src0
[0], src1
[0]);
269 bld
.vop2(aco_opcode::v_xor_b32
, dst
[1], src0
[1], src1
[1]);
270 } else if (op
== umin64
|| op
== umax64
|| op
== imin64
|| op
== imax64
) {
271 aco_opcode cmp
= aco_opcode::num_opcodes
;
274 cmp
= aco_opcode::v_cmp_gt_u64
;
277 cmp
= aco_opcode::v_cmp_lt_u64
;
280 cmp
= aco_opcode::v_cmp_gt_i64
;
283 cmp
= aco_opcode::v_cmp_lt_i64
;
289 bld
.vopc(cmp
, bld
.def(bld
.lm
, vcc
), src0_64
, src1_64
);
290 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
[0], src0
[0], src1
[0], Operand(vcc
, bld
.lm
));
291 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
[1], src0
[1], src1
[1], Operand(vcc
, bld
.lm
));
292 } else if (op
== imul64
) {
293 if (src1_reg
== dst_reg
) {
294 /* it's fine if src0==dst but not if src1==dst */
295 std::swap(src0_reg
, src1_reg
);
296 std::swap(src0
[0], src1
[0]);
297 std::swap(src0
[1], src1
[1]);
298 std::swap(src0_64
, src1_64
);
300 assert(!(src0_reg
== src1_reg
));
301 /* t1 = umul_lo(x_hi, y_lo)
302 * t0 = umul_lo(x_lo, y_hi)
304 * t5 = umul_hi(x_lo, y_lo)
305 * res_hi = iadd(t2, t5)
306 * res_lo = umul_lo(x_lo, y_lo)
307 * assumes that it's ok to modify x_hi/y_hi, since we might not have vtmp
309 Definition
tmp0_def(PhysReg
{src0_reg
+1}, v1
);
310 Definition
tmp1_def(PhysReg
{src1_reg
+1}, v1
);
311 Operand tmp0_op
= src0
[1];
312 Operand tmp1_op
= src1
[1];
313 bld
.vop3(aco_opcode::v_mul_lo_u32
, tmp0_def
, src0
[1], src1
[0]);
314 bld
.vop3(aco_opcode::v_mul_lo_u32
, tmp1_def
, src0
[0], src1
[1]);
315 emit_vadd32(bld
, tmp0_def
, tmp1_op
, tmp0_op
);
316 bld
.vop3(aco_opcode::v_mul_hi_u32
, tmp1_def
, src0
[0], src1
[0]);
317 emit_vadd32(bld
, dst
[1], tmp0_op
, tmp1_op
);
318 bld
.vop3(aco_opcode::v_mul_lo_u32
, dst
[0], src0
[0], src1
[0]);
322 void emit_dpp_op(lower_context
*ctx
, PhysReg dst_reg
, PhysReg src0_reg
, PhysReg src1_reg
,
323 PhysReg vtmp
, ReduceOp op
, unsigned size
,
324 unsigned dpp_ctrl
, unsigned row_mask
, unsigned bank_mask
, bool bound_ctrl
,
325 Operand
*identity
=NULL
) /* for VOP3 with sparse writes */
327 Builder
bld(ctx
->program
, &ctx
->instructions
);
328 RegClass rc
= RegClass(RegType::vgpr
, size
);
329 Definition
dst(dst_reg
, rc
);
330 Operand
src0(src0_reg
, rc
);
331 Operand
src1(src1_reg
, rc
);
333 aco_opcode opcode
= get_reduce_opcode(ctx
->program
->chip_class
, op
);
334 bool vop3
= is_vop3_reduce_opcode(opcode
);
337 if (opcode
== aco_opcode::v_add_co_u32
)
338 bld
.vop2_dpp(opcode
, dst
, bld
.def(bld
.lm
, vcc
), src0
, src1
, dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
340 bld
.vop2_dpp(opcode
, dst
, src0
, src1
, dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
344 if (opcode
== aco_opcode::num_opcodes
) {
345 emit_int64_dpp_op(ctx
, dst_reg
,src0_reg
, src1_reg
, vtmp
, op
,
346 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
, identity
);
351 bld
.vop1(aco_opcode::v_mov_b32
, Definition(vtmp
, v1
), identity
[0]);
352 if (identity
&& size
>= 2)
353 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+1}, v1
), identity
[1]);
355 for (unsigned i
= 0; i
< size
; i
++)
356 bld
.vop1_dpp(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{src0_reg
+i
}, v1
),
357 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
359 bld
.vop3(opcode
, dst
, Operand(vtmp
, rc
), src1
);
362 void emit_op(lower_context
*ctx
, PhysReg dst_reg
, PhysReg src0_reg
, PhysReg src1_reg
,
363 PhysReg vtmp
, ReduceOp op
, unsigned size
)
365 Builder
bld(ctx
->program
, &ctx
->instructions
);
366 RegClass rc
= RegClass(RegType::vgpr
, size
);
367 Definition
dst(dst_reg
, rc
);
368 Operand
src0(src0_reg
, RegClass(src0_reg
.reg() >= 256 ? RegType::vgpr
: RegType::sgpr
, size
));
369 Operand
src1(src1_reg
, rc
);
371 aco_opcode opcode
= get_reduce_opcode(ctx
->program
->chip_class
, op
);
372 bool vop3
= is_vop3_reduce_opcode(opcode
);
374 if (opcode
== aco_opcode::num_opcodes
) {
375 emit_int64_op(ctx
, dst_reg
, src0_reg
, src1_reg
, vtmp
, op
);
380 bld
.vop3(opcode
, dst
, src0
, src1
);
381 } else if (opcode
== aco_opcode::v_add_co_u32
) {
382 bld
.vop2(opcode
, dst
, bld
.def(bld
.lm
, vcc
), src0
, src1
);
384 bld
.vop2(opcode
, dst
, src0
, src1
);
388 void emit_dpp_mov(lower_context
*ctx
, PhysReg dst
, PhysReg src0
, unsigned size
,
389 unsigned dpp_ctrl
, unsigned row_mask
, unsigned bank_mask
, bool bound_ctrl
)
391 Builder
bld(ctx
->program
, &ctx
->instructions
);
392 for (unsigned i
= 0; i
< size
; i
++) {
393 bld
.vop1_dpp(aco_opcode::v_mov_b32
, Definition(PhysReg
{dst
+i
}, v1
), Operand(PhysReg
{src0
+i
}, v1
),
394 dpp_ctrl
, row_mask
, bank_mask
, bound_ctrl
);
398 uint32_t get_reduction_identity(ReduceOp op
, unsigned idx
)
427 return 0x3c00u
; /* 1.0 */
429 return 0x3f800000u
; /* 1.0 */
431 return idx
? 0x3ff00000u
: 0u; /* 1.0 */
439 return idx
? 0x7fffffffu
: 0xffffffffu
;
447 return idx
? 0x80000000u
: 0;
459 return 0x7c00u
; /* infinity */
461 return 0x7f800000u
; /* infinity */
463 return idx
? 0x7ff00000u
: 0u; /* infinity */
465 return 0xfc00u
; /* negative infinity */
467 return 0xff800000u
; /* negative infinity */
469 return idx
? 0xfff00000u
: 0u; /* negative infinity */
471 unreachable("Invalid reduction operation");
477 void emit_ds_swizzle(Builder bld
, PhysReg dst
, PhysReg src
, unsigned size
, unsigned ds_pattern
)
479 for (unsigned i
= 0; i
< size
; i
++) {
480 bld
.ds(aco_opcode::ds_swizzle_b32
, Definition(PhysReg
{dst
+i
}, v1
),
481 Operand(PhysReg
{src
+i
}, v1
), ds_pattern
);
485 void emit_reduction(lower_context
*ctx
, aco_opcode op
, ReduceOp reduce_op
, unsigned cluster_size
, PhysReg tmp
,
486 PhysReg stmp
, PhysReg vtmp
, PhysReg sitmp
, Operand src
, Definition dst
)
488 assert(cluster_size
== ctx
->program
->wave_size
|| op
== aco_opcode::p_reduce
);
489 assert(cluster_size
<= ctx
->program
->wave_size
);
491 Builder
bld(ctx
->program
, &ctx
->instructions
);
494 identity
[0] = Operand(get_reduction_identity(reduce_op
, 0));
495 identity
[1] = Operand(get_reduction_identity(reduce_op
, 1));
496 Operand vcndmask_identity
[2] = {identity
[0], identity
[1]};
498 /* First, copy the source to tmp and set inactive lanes to the identity */
499 bld
.sop1(Builder::s_or_saveexec
, Definition(stmp
, bld
.lm
), Definition(scc
, s1
), Definition(exec
, bld
.lm
), Operand(UINT64_MAX
), Operand(exec
, bld
.lm
));
501 for (unsigned i
= 0; i
< src
.size(); i
++) {
502 /* p_exclusive_scan needs it to be a sgpr or inline constant for the v_writelane_b32
503 * except on GFX10, where v_writelane_b32 can take a literal. */
504 if (identity
[i
].isLiteral() && op
== aco_opcode::p_exclusive_scan
&& ctx
->program
->chip_class
< GFX10
) {
505 bld
.sop1(aco_opcode::s_mov_b32
, Definition(PhysReg
{sitmp
+i
}, s1
), identity
[i
]);
506 identity
[i
] = Operand(PhysReg
{sitmp
+i
}, s1
);
508 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{tmp
+i
}, v1
), identity
[i
]);
509 vcndmask_identity
[i
] = Operand(PhysReg
{tmp
+i
}, v1
);
510 } else if (identity
[i
].isLiteral()) {
511 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{tmp
+i
}, v1
), identity
[i
]);
512 vcndmask_identity
[i
] = Operand(PhysReg
{tmp
+i
}, v1
);
516 for (unsigned i
= 0; i
< src
.size(); i
++) {
517 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(PhysReg
{tmp
+ i
}, v1
),
518 vcndmask_identity
[i
], Operand(PhysReg
{src
.physReg() + i
}, v1
),
519 Operand(stmp
, bld
.lm
));
522 if (src
.regClass() == v1b
) {
523 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
524 sdwa
->operands
[0] = Operand(PhysReg
{tmp
}, v1
);
525 sdwa
->definitions
[0] = Definition(PhysReg
{tmp
}, v1
);
526 if (reduce_op
== imin8
|| reduce_op
== imax8
)
527 sdwa
->sel
[0] = sdwa_sbyte
;
529 sdwa
->sel
[0] = sdwa_ubyte
;
530 sdwa
->dst_sel
= sdwa_udword
;
531 bld
.insert(std::move(sdwa
));
534 bool reduction_needs_last_op
= false;
536 case aco_opcode::p_reduce
:
537 if (cluster_size
== 1) break;
539 if (ctx
->program
->chip_class
<= GFX7
) {
540 reduction_needs_last_op
= true;
541 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), (1 << 15) | dpp_quad_perm(1, 0, 3, 2));
542 if (cluster_size
== 2) break;
543 emit_op(ctx
, tmp
, vtmp
, tmp
, PhysReg
{0}, reduce_op
, src
.size());
544 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), (1 << 15) | dpp_quad_perm(2, 3, 0, 1));
545 if (cluster_size
== 4) break;
546 emit_op(ctx
, tmp
, vtmp
, tmp
, PhysReg
{0}, reduce_op
, src
.size());
547 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1f, 0, 0x04));
548 if (cluster_size
== 8) break;
549 emit_op(ctx
, tmp
, vtmp
, tmp
, PhysReg
{0}, reduce_op
, src
.size());
550 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1f, 0, 0x08));
551 if (cluster_size
== 16) break;
552 emit_op(ctx
, tmp
, vtmp
, tmp
, PhysReg
{0}, reduce_op
, src
.size());
553 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1f, 0, 0x10));
554 if (cluster_size
== 32) break;
555 emit_op(ctx
, tmp
, vtmp
, tmp
, PhysReg
{0}, reduce_op
, src
.size());
556 for (unsigned i
= 0; i
< src
.size(); i
++)
557 bld
.readlane(Definition(PhysReg
{dst
.physReg() + i
}, s1
), Operand(PhysReg
{tmp
+ i
}, v1
), Operand(0u));
558 // TODO: it would be more effective to do the last reduction step on SALU
559 emit_op(ctx
, tmp
, dst
.physReg(), tmp
, vtmp
, reduce_op
, src
.size());
560 reduction_needs_last_op
= false;
564 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(), dpp_quad_perm(1, 0, 3, 2), 0xf, 0xf, false);
565 if (cluster_size
== 2) break;
566 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(), dpp_quad_perm(2, 3, 0, 1), 0xf, 0xf, false);
567 if (cluster_size
== 4) break;
568 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(), dpp_row_half_mirror
, 0xf, 0xf, false);
569 if (cluster_size
== 8) break;
570 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(), dpp_row_mirror
, 0xf, 0xf, false);
571 if (cluster_size
== 16) break;
573 if (ctx
->program
->chip_class
>= GFX10
) {
574 /* GFX10+ doesn't support row_bcast15 and row_bcast31 */
575 for (unsigned i
= 0; i
< src
.size(); i
++)
576 bld
.vop3(aco_opcode::v_permlanex16_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(0u), Operand(0u));
578 if (cluster_size
== 32) {
579 reduction_needs_last_op
= true;
583 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
584 for (unsigned i
= 0; i
< src
.size(); i
++)
585 bld
.readlane(Definition(PhysReg
{dst
.physReg() + i
}, s1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(0u));
586 // TODO: it would be more effective to do the last reduction step on SALU
587 emit_op(ctx
, tmp
, dst
.physReg(), tmp
, vtmp
, reduce_op
, src
.size());
591 if (cluster_size
== 32) {
592 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1f, 0, 0x10));
593 reduction_needs_last_op
= true;
596 assert(cluster_size
== 64);
597 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(), dpp_row_bcast15
, 0xa, 0xf, false);
598 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(), dpp_row_bcast31
, 0xc, 0xf, false);
600 case aco_opcode::p_exclusive_scan
:
601 if (ctx
->program
->chip_class
>= GFX10
) { /* gfx10 doesn't support wf_sr1, so emulate it */
602 /* shift rows right */
603 emit_dpp_mov(ctx
, vtmp
, tmp
, src
.size(), dpp_row_sr(1), 0xf, 0xf, true);
605 /* fill in the gaps in rows 1 and 3 */
606 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0x10000u
));
607 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(0x10000u
));
608 for (unsigned i
= 0; i
< src
.size(); i
++) {
609 Instruction
*perm
= bld
.vop3(aco_opcode::v_permlanex16_b32
,
610 Definition(PhysReg
{vtmp
+i
}, v1
),
611 Operand(PhysReg
{tmp
+i
}, v1
),
612 Operand(0xffffffffu
), Operand(0xffffffffu
)).instr
;
613 static_cast<VOP3A_instruction
*>(perm
)->opsel
= 1; /* FI (Fetch Inactive) */
615 bld
.sop1(Builder::s_mov
, Definition(exec
, bld
.lm
), Operand(UINT64_MAX
));
617 if (ctx
->program
->wave_size
== 64) {
618 /* fill in the gap in row 2 */
619 for (unsigned i
= 0; i
< src
.size(); i
++) {
620 bld
.readlane(Definition(PhysReg
{sitmp
+i
}, s1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(31u));
621 bld
.writelane(Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{sitmp
+i
}, s1
), Operand(32u), Operand(PhysReg
{vtmp
+i
}, v1
));
624 std::swap(tmp
, vtmp
);
625 } else if (ctx
->program
->chip_class
>= GFX8
) {
626 emit_dpp_mov(ctx
, tmp
, tmp
, src
.size(), dpp_wf_sr1
, 0xf, 0xf, true);
628 // TODO: use LDS on CS with a single write and shifted read
629 /* wavefront shift_right by 1 on SI/CI */
630 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), (1 << 15) | dpp_quad_perm(0, 0, 1, 2));
631 emit_ds_swizzle(bld
, tmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1F, 0x00, 0x07)); /* mirror(8) */
632 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0x10101010u
));
633 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(exec_lo
, s1
));
634 for (unsigned i
= 0; i
< src
.size(); i
++)
635 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{tmp
+i
}, v1
));
637 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(UINT64_MAX
));
638 emit_ds_swizzle(bld
, tmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1F, 0x00, 0x08)); /* swap(8) */
639 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0x01000100u
));
640 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(exec_lo
, s1
));
641 for (unsigned i
= 0; i
< src
.size(); i
++)
642 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{tmp
+i
}, v1
));
644 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(UINT64_MAX
));
645 emit_ds_swizzle(bld
, tmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1F, 0x00, 0x10)); /* swap(16) */
646 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(exec_lo
, s1
), Operand(1u), Operand(16u));
647 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(exec_hi
, s1
), Operand(1u), Operand(16u));
648 for (unsigned i
= 0; i
< src
.size(); i
++)
649 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{tmp
+i
}, v1
));
651 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(UINT64_MAX
));
652 for (unsigned i
= 0; i
< src
.size(); i
++) {
653 bld
.writelane(Definition(PhysReg
{vtmp
+i
}, v1
), identity
[i
], Operand(0u), Operand(PhysReg
{vtmp
+i
}, v1
));
654 bld
.readlane(Definition(PhysReg
{sitmp
+i
}, s1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(0u));
655 bld
.writelane(Definition(PhysReg
{vtmp
+i
}, v1
), Operand(PhysReg
{sitmp
+i
}, s1
), Operand(32u), Operand(PhysReg
{vtmp
+i
}, v1
));
656 identity
[i
] = Operand(0u); /* prevent further uses of identity */
658 std::swap(tmp
, vtmp
);
661 for (unsigned i
= 0; i
< src
.size(); i
++) {
662 if (!identity
[i
].isConstant() || identity
[i
].constantValue()) { /* bound_ctrl should take care of this overwise */
663 if (ctx
->program
->chip_class
< GFX10
)
664 assert((identity
[i
].isConstant() && !identity
[i
].isLiteral()) || identity
[i
].physReg() == PhysReg
{sitmp
+i
});
665 bld
.writelane(Definition(PhysReg
{tmp
+i
}, v1
), identity
[i
], Operand(0u), Operand(PhysReg
{tmp
+i
}, v1
));
669 case aco_opcode::p_inclusive_scan
:
670 assert(cluster_size
== ctx
->program
->wave_size
);
671 if (ctx
->program
->chip_class
<= GFX7
) {
672 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1e, 0x00, 0x00));
673 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0xAAAAAAAAu
));
674 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(exec_lo
, s1
));
675 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
677 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(UINT64_MAX
));
678 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x1c, 0x01, 0x00));
679 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0xCCCCCCCCu
));
680 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(exec_lo
, s1
));
681 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
683 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(UINT64_MAX
));
684 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x18, 0x03, 0x00));
685 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0xF0F0F0F0u
));
686 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(exec_lo
, s1
));
687 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
689 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(UINT64_MAX
));
690 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x10, 0x07, 0x00));
691 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_lo
, s1
), Operand(0xFF00FF00u
));
692 bld
.sop1(aco_opcode::s_mov_b32
, Definition(exec_hi
, s1
), Operand(exec_lo
, s1
));
693 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
695 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(UINT64_MAX
));
696 emit_ds_swizzle(bld
, vtmp
, tmp
, src
.size(), ds_pattern_bitmode(0x00, 0x0f, 0x00));
697 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(exec_lo
, s1
), Operand(16u), Operand(16u));
698 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(exec_hi
, s1
), Operand(16u), Operand(16u));
699 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
701 for (unsigned i
= 0; i
< src
.size(); i
++)
702 bld
.readlane(Definition(PhysReg
{sitmp
+i
}, s1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(31u));
703 bld
.sop2(aco_opcode::s_bfm_b64
, Definition(exec
, s2
), Operand(32u), Operand(32u));
704 emit_op(ctx
, tmp
, sitmp
, tmp
, vtmp
, reduce_op
, src
.size());
708 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
709 dpp_row_sr(1), 0xf, 0xf, false, identity
);
710 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
711 dpp_row_sr(2), 0xf, 0xf, false, identity
);
712 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
713 dpp_row_sr(4), 0xf, 0xf, false, identity
);
714 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
715 dpp_row_sr(8), 0xf, 0xf, false, identity
);
716 if (ctx
->program
->chip_class
>= GFX10
) {
717 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(exec_lo
, s1
), Operand(16u), Operand(16u));
718 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(exec_hi
, s1
), Operand(16u), Operand(16u));
719 for (unsigned i
= 0; i
< src
.size(); i
++) {
720 Instruction
*perm
= bld
.vop3(aco_opcode::v_permlanex16_b32
,
721 Definition(PhysReg
{vtmp
+i
}, v1
),
722 Operand(PhysReg
{tmp
+i
}, v1
),
723 Operand(0xffffffffu
), Operand(0xffffffffu
)).instr
;
724 static_cast<VOP3A_instruction
*>(perm
)->opsel
= 1; /* FI (Fetch Inactive) */
726 emit_op(ctx
, tmp
, tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
728 if (ctx
->program
->wave_size
== 64) {
729 bld
.sop2(aco_opcode::s_bfm_b64
, Definition(exec
, s2
), Operand(32u), Operand(32u));
730 for (unsigned i
= 0; i
< src
.size(); i
++)
731 bld
.readlane(Definition(PhysReg
{sitmp
+i
}, s1
), Operand(PhysReg
{tmp
+i
}, v1
), Operand(31u));
732 emit_op(ctx
, tmp
, sitmp
, tmp
, vtmp
, reduce_op
, src
.size());
735 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
736 dpp_row_bcast15
, 0xa, 0xf, false, identity
);
737 emit_dpp_op(ctx
, tmp
, tmp
, tmp
, vtmp
, reduce_op
, src
.size(),
738 dpp_row_bcast31
, 0xc, 0xf, false, identity
);
742 unreachable("Invalid reduction mode");
746 if (op
== aco_opcode::p_reduce
) {
747 if (reduction_needs_last_op
&& dst
.regClass().type() == RegType::vgpr
) {
748 bld
.sop1(Builder::s_mov
, Definition(exec
, bld
.lm
), Operand(stmp
, bld
.lm
));
749 emit_op(ctx
, dst
.physReg(), tmp
, vtmp
, PhysReg
{0}, reduce_op
, src
.size());
753 if (reduction_needs_last_op
)
754 emit_op(ctx
, tmp
, vtmp
, tmp
, PhysReg
{0}, reduce_op
, src
.size());
758 bld
.sop1(Builder::s_mov
, Definition(exec
, bld
.lm
), Operand(stmp
, bld
.lm
));
760 if (dst
.regClass().type() == RegType::sgpr
) {
761 for (unsigned k
= 0; k
< src
.size(); k
++) {
762 bld
.readlane(Definition(PhysReg
{dst
.physReg() + k
}, s1
),
763 Operand(PhysReg
{tmp
+ k
}, v1
), Operand(ctx
->program
->wave_size
- 1));
765 } else if (dst
.physReg() != tmp
) {
766 for (unsigned k
= 0; k
< src
.size(); k
++) {
767 bld
.vop1(aco_opcode::v_mov_b32
, Definition(PhysReg
{dst
.physReg() + k
}, v1
),
768 Operand(PhysReg
{tmp
+ k
}, v1
));
773 struct copy_operation
{
779 uint64_t is_used
= 0;
783 void split_copy(unsigned offset
, Definition
*def
, Operand
*op
, const copy_operation
& src
, bool ignore_uses
, unsigned max_size
)
785 PhysReg def_reg
= src
.def
.physReg();
786 PhysReg op_reg
= src
.op
.physReg();
787 def_reg
.reg_b
+= offset
;
788 op_reg
.reg_b
+= offset
;
790 max_size
= MIN2(max_size
, src
.def
.regClass().type() == RegType::vgpr
? 4 : 8);
792 /* make sure the size is a power of two and reg % bytes == 0 */
794 for (; bytes
<= max_size
; bytes
*= 2) {
795 unsigned next
= bytes
* 2u;
796 bool can_increase
= def_reg
.reg_b
% next
== 0 &&
797 offset
+ next
<= src
.bytes
&& next
<= max_size
;
798 if (!src
.op
.isConstant() && can_increase
)
799 can_increase
= op_reg
.reg_b
% next
== 0;
800 for (unsigned i
= 0; !ignore_uses
&& can_increase
&& (i
< bytes
); i
++)
801 can_increase
= (src
.uses
[offset
+ bytes
+ i
] == 0) == (src
.uses
[offset
] == 0);
806 RegClass def_cls
= bytes
% 4 == 0 ? RegClass(src
.def
.regClass().type(), bytes
/ 4u) :
807 RegClass(src
.def
.regClass().type(), bytes
).as_subdword();
808 *def
= Definition(src
.def
.tempId(), def_reg
, def_cls
);
809 if (src
.op
.isConstant()) {
810 assert(offset
== 0 || (offset
== 4 && src
.op
.bytes() == 8));
811 if (src
.op
.bytes() == 8 && bytes
== 4)
812 *op
= Operand(uint32_t(src
.op
.constantValue64() >> (offset
* 8u)));
816 RegClass op_cls
= bytes
% 4 == 0 ? RegClass(src
.op
.regClass().type(), bytes
/ 4u) :
817 RegClass(src
.op
.regClass().type(), bytes
).as_subdword();
818 *op
= Operand(op_reg
, op_cls
);
819 op
->setTemp(Temp(src
.op
.tempId(), op_cls
));
823 uint32_t get_intersection_mask(int a_start
, int a_size
,
824 int b_start
, int b_size
)
826 int intersection_start
= MAX2(b_start
- a_start
, 0);
827 int intersection_end
= MAX2(b_start
+ b_size
- a_start
, 0);
828 if (intersection_start
>= a_size
|| intersection_end
== 0)
831 uint32_t mask
= u_bit_consecutive(0, a_size
);
832 return u_bit_consecutive(intersection_start
, intersection_end
- intersection_start
) & mask
;
835 bool do_copy(lower_context
* ctx
, Builder
& bld
, const copy_operation
& copy
, bool *preserve_scc
)
837 bool did_copy
= false;
838 for (unsigned offset
= 0; offset
< copy
.bytes
;) {
839 if (copy
.uses
[offset
]) {
846 split_copy(offset
, &def
, &op
, copy
, false, 8);
848 if (def
.physReg() == scc
) {
849 bld
.sopc(aco_opcode::s_cmp_lg_i32
, def
, op
, Operand(0u));
850 *preserve_scc
= true;
851 } else if (def
.bytes() == 8 && def
.getTemp().type() == RegType::sgpr
) {
852 bld
.sop1(aco_opcode::s_mov_b64
, def
, Operand(op
.physReg(), s2
));
857 ctx
->program
->statistics
[statistic_copies
]++;
860 offset
+= def
.bytes();
865 void do_swap(lower_context
*ctx
, Builder
& bld
, const copy_operation
& copy
, bool preserve_scc
, Pseudo_instruction
*pi
)
869 if (copy
.bytes
== 3 && (copy
.def
.physReg().reg_b
% 4 <= 1) &&
870 (copy
.def
.physReg().reg_b
% 4) == (copy
.op
.physReg().reg_b
% 4)) {
871 /* instead of doing a 2-byte and 1-byte swap, do a 4-byte swap and then fixup with a 1-byte swap */
872 PhysReg op
= copy
.op
.physReg();
873 PhysReg def
= copy
.def
.physReg();
878 tmp
.op
= Operand(op
, v1
);
879 tmp
.def
= Definition(def
, v1
);
881 memset(tmp
.uses
, 1, 4);
882 do_swap(ctx
, bld
, tmp
, preserve_scc
, pi
);
884 op
.reg_b
+= copy
.def
.physReg().reg_b
% 4 == 0 ? 3 : 0;
885 def
.reg_b
+= copy
.def
.physReg().reg_b
% 4 == 0 ? 3 : 0;
886 tmp
.op
= Operand(op
, v1b
);
887 tmp
.def
= Definition(def
, v1b
);
890 do_swap(ctx
, bld
, tmp
, preserve_scc
, pi
);
895 for (; offset
< copy
.bytes
;) {
898 split_copy(offset
, &def
, &op
, copy
, true, 8);
900 assert(op
.regClass() == def
.regClass());
901 Operand def_as_op
= Operand(def
.physReg(), def
.regClass());
902 Definition op_as_def
= Definition(op
.physReg(), op
.regClass());
903 if (ctx
->program
->chip_class
>= GFX9
&& def
.regClass() == v1
) {
904 bld
.vop1(aco_opcode::v_swap_b32
, def
, op_as_def
, op
, def_as_op
);
905 ctx
->program
->statistics
[statistic_copies
]++;
906 } else if (def
.regClass() == v1
) {
907 bld
.vop2(aco_opcode::v_xor_b32
, op_as_def
, op
, def_as_op
);
908 bld
.vop2(aco_opcode::v_xor_b32
, def
, op
, def_as_op
);
909 bld
.vop2(aco_opcode::v_xor_b32
, op_as_def
, op
, def_as_op
);
910 ctx
->program
->statistics
[statistic_copies
] += 3;
911 } else if (op
.physReg() == scc
|| def
.physReg() == scc
) {
912 /* we need to swap scc and another sgpr */
913 assert(!preserve_scc
);
915 PhysReg other
= op
.physReg() == scc
? def
.physReg() : op
.physReg();
917 bld
.sop1(aco_opcode::s_mov_b32
, Definition(pi
->scratch_sgpr
, s1
), Operand(scc
, s1
));
918 bld
.sopc(aco_opcode::s_cmp_lg_i32
, Definition(scc
, s1
), Operand(other
, s1
), Operand(0u));
919 bld
.sop1(aco_opcode::s_mov_b32
, Definition(other
, s1
), Operand(pi
->scratch_sgpr
, s1
));
920 ctx
->program
->statistics
[statistic_copies
] += 3;
921 } else if (def
.regClass() == s1
) {
923 bld
.sop1(aco_opcode::s_mov_b32
, Definition(pi
->scratch_sgpr
, s1
), op
);
924 bld
.sop1(aco_opcode::s_mov_b32
, op_as_def
, def_as_op
);
925 bld
.sop1(aco_opcode::s_mov_b32
, def
, Operand(pi
->scratch_sgpr
, s1
));
927 bld
.sop2(aco_opcode::s_xor_b32
, op_as_def
, Definition(scc
, s1
), op
, def_as_op
);
928 bld
.sop2(aco_opcode::s_xor_b32
, def
, Definition(scc
, s1
), op
, def_as_op
);
929 bld
.sop2(aco_opcode::s_xor_b32
, op_as_def
, Definition(scc
, s1
), op
, def_as_op
);
931 ctx
->program
->statistics
[statistic_copies
] += 3;
932 } else if (def
.regClass() == s2
) {
934 bld
.sop1(aco_opcode::s_mov_b32
, Definition(pi
->scratch_sgpr
, s1
), Operand(scc
, s1
));
935 bld
.sop2(aco_opcode::s_xor_b64
, op_as_def
, Definition(scc
, s1
), op
, def_as_op
);
936 bld
.sop2(aco_opcode::s_xor_b64
, def
, Definition(scc
, s1
), op
, def_as_op
);
937 bld
.sop2(aco_opcode::s_xor_b64
, op_as_def
, Definition(scc
, s1
), op
, def_as_op
);
939 bld
.sopc(aco_opcode::s_cmp_lg_i32
, Definition(scc
, s1
), Operand(pi
->scratch_sgpr
, s1
), Operand(0u));
940 ctx
->program
->statistics
[statistic_copies
] += 3;
941 } else if (ctx
->program
->chip_class
>= GFX9
&& def
.bytes() == 2 && def
.physReg().reg() == op
.physReg().reg()) {
942 aco_ptr
<VOP3P_instruction
> vop3p
{create_instruction
<VOP3P_instruction
>(aco_opcode::v_pk_add_u16
, Format::VOP3P
, 2, 1)};
943 vop3p
->operands
[0] = Operand(PhysReg
{op
.physReg().reg()}, v1
);
944 vop3p
->operands
[1] = Operand(0u);
945 vop3p
->definitions
[0] = Definition(PhysReg
{op
.physReg().reg()}, v1
);
946 vop3p
->opsel_lo
= 0x1;
947 vop3p
->opsel_hi
= 0x2;
948 bld
.insert(std::move(vop3p
));
950 assert(def
.regClass().is_subdword());
951 bld
.vop2_sdwa(aco_opcode::v_xor_b32
, op_as_def
, op
, def_as_op
);
952 bld
.vop2_sdwa(aco_opcode::v_xor_b32
, def
, op
, def_as_op
);
953 bld
.vop2_sdwa(aco_opcode::v_xor_b32
, op_as_def
, op
, def_as_op
);
954 ctx
->program
->statistics
[statistic_copies
] += 3;
957 offset
+= def
.bytes();
960 /* fixup in case we swapped bytes we shouldn't have */
961 copy_operation tmp_copy
= copy
;
962 tmp_copy
.op
.setFixed(copy
.def
.physReg());
963 tmp_copy
.def
.setFixed(copy
.op
.physReg());
964 do_copy(ctx
, bld
, tmp_copy
, &preserve_scc
);
967 void handle_operands(std::map
<PhysReg
, copy_operation
>& copy_map
, lower_context
* ctx
, chip_class chip_class
, Pseudo_instruction
*pi
)
969 Builder
bld(ctx
->program
, &ctx
->instructions
);
970 aco_ptr
<Instruction
> mov
;
971 std::map
<PhysReg
, copy_operation
>::iterator it
= copy_map
.begin();
972 std::map
<PhysReg
, copy_operation
>::iterator target
;
973 bool writes_scc
= false;
975 /* count the number of uses for each dst reg */
976 while (it
!= copy_map
.end()) {
978 if (it
->second
.def
.physReg() == scc
)
981 assert(!pi
->tmp_in_scc
|| !(it
->second
.def
.physReg() == pi
->scratch_sgpr
));
983 /* if src and dst reg are the same, remove operation */
984 if (it
->first
== it
->second
.op
.physReg()) {
985 it
= copy_map
.erase(it
);
989 /* split large copies */
990 if (it
->second
.bytes
> 8) {
991 assert(!it
->second
.op
.isConstant());
992 assert(!it
->second
.def
.regClass().is_subdword());
993 RegClass rc
= RegClass(it
->second
.def
.regClass().type(), it
->second
.def
.size() - 2);
994 Definition hi_def
= Definition(PhysReg
{it
->first
+ 2}, rc
);
995 rc
= RegClass(it
->second
.op
.regClass().type(), it
->second
.op
.size() - 2);
996 Operand hi_op
= Operand(PhysReg
{it
->second
.op
.physReg() + 2}, rc
);
997 copy_operation copy
= {hi_op
, hi_def
, it
->second
.bytes
- 8};
998 copy_map
[hi_def
.physReg()] = copy
;
999 assert(it
->second
.op
.physReg().byte() == 0 && it
->second
.def
.physReg().byte() == 0);
1000 it
->second
.op
= Operand(it
->second
.op
.physReg(), it
->second
.op
.regClass().type() == RegType::sgpr
? s2
: v2
);
1001 it
->second
.def
= Definition(it
->second
.def
.physReg(), it
->second
.def
.regClass().type() == RegType::sgpr
? s2
: v2
);
1002 it
->second
.bytes
= 8;
1005 /* check if the definition reg is used by another copy operation */
1006 for (std::pair
<const PhysReg
, copy_operation
>& copy
: copy_map
) {
1007 if (copy
.second
.op
.isConstant())
1009 for (uint16_t i
= 0; i
< it
->second
.bytes
; i
++) {
1010 /* distance might underflow */
1011 unsigned distance
= it
->first
.reg_b
+ i
- copy
.second
.op
.physReg().reg_b
;
1012 if (distance
< copy
.second
.bytes
)
1013 it
->second
.uses
[i
] += 1;
1020 /* first, handle paths in the location transfer graph */
1021 bool preserve_scc
= pi
->tmp_in_scc
&& !writes_scc
;
1022 it
= copy_map
.begin();
1023 while (it
!= copy_map
.end()) {
1025 /* try to coalesce 32-bit sgpr copies to 64-bit copies */
1026 if (it
->second
.is_used
== 0 &&
1027 it
->second
.def
.getTemp().type() == RegType::sgpr
&& it
->second
.bytes
== 4 &&
1028 !it
->second
.op
.isConstant() && it
->first
% 2 == it
->second
.op
.physReg() % 2) {
1030 PhysReg other_def_reg
= PhysReg
{it
->first
% 2 ? it
->first
- 1 : it
->first
+ 1};
1031 PhysReg other_op_reg
= PhysReg
{it
->first
% 2 ? it
->second
.op
.physReg() - 1 : it
->second
.op
.physReg() + 1};
1032 std::map
<PhysReg
, copy_operation
>::iterator other
= copy_map
.find(other_def_reg
);
1034 if (other
!= copy_map
.end() && !other
->second
.is_used
&& other
->second
.bytes
== 4 &&
1035 other
->second
.op
.physReg() == other_op_reg
&& !other
->second
.op
.isConstant()) {
1036 std::map
<PhysReg
, copy_operation
>::iterator to_erase
= it
->first
% 2 ? it
: other
;
1037 it
= it
->first
% 2 ? other
: it
;
1038 copy_map
.erase(to_erase
);
1039 it
->second
.bytes
= 8;
1042 // TODO: try to coalesce subdword copies
1044 /* find portions where the target reg is not used as operand for any other copy */
1045 if (it
->second
.is_used
) {
1046 if (it
->second
.op
.isConstant()) {
1047 /* we have to skip constants until is_used=0 */
1052 unsigned has_zero_use_bytes
= 0;
1053 for (unsigned i
= 0; i
< it
->second
.bytes
; i
++)
1054 has_zero_use_bytes
|= (it
->second
.uses
[i
] == 0) << i
;
1056 if (has_zero_use_bytes
) {
1057 /* Skipping partial copying and doing a v_swap_b32 and then fixup
1058 * copies is usually beneficial for sub-dword copies, but if doing
1059 * a partial copy allows further copies, it should be done instead. */
1060 bool partial_copy
= (has_zero_use_bytes
== 0xf) || (has_zero_use_bytes
== 0xf0);
1061 for (std::pair
<const PhysReg
, copy_operation
>& copy
: copy_map
) {
1064 for (uint16_t i
= 0; i
< copy
.second
.bytes
; i
++) {
1065 /* distance might underflow */
1066 unsigned distance
= copy
.first
.reg_b
+ i
- it
->second
.op
.physReg().reg_b
;
1067 if (distance
< it
->second
.bytes
&& copy
.second
.uses
[i
] == 1 &&
1068 !it
->second
.uses
[distance
])
1069 partial_copy
= true;
1073 if (!partial_copy
) {
1078 /* full target reg is used: register swapping needed */
1084 bool did_copy
= do_copy(ctx
, bld
, it
->second
, &preserve_scc
);
1086 std::pair
<PhysReg
, copy_operation
> copy
= *it
;
1088 if (it
->second
.is_used
== 0) {
1089 /* the target reg is not used as operand for any other copy, so we
1090 * copied to all of it */
1092 it
= copy_map
.begin();
1094 /* we only performed some portions of this copy, so split it to only
1095 * leave the portions that still need to be done */
1096 copy_operation original
= it
->second
; /* the map insertion below can overwrite this */
1098 for (unsigned offset
= 0; offset
< original
.bytes
;) {
1099 if (original
.uses
[offset
] == 0) {
1105 split_copy(offset
, &def
, &op
, original
, false, 8);
1107 copy_operation copy
= {op
, def
, def
.bytes()};
1108 for (unsigned i
= 0; i
< copy
.bytes
; i
++)
1109 copy
.uses
[i
] = original
.uses
[i
+ offset
];
1110 copy_map
[def
.physReg()] = copy
;
1112 offset
+= def
.bytes();
1115 it
= copy_map
.begin();
1118 /* Reduce the number of uses of the operand reg by one. Do this after
1119 * splitting the copy or removing it in case the copy writes to it's own
1120 * operand (for example, v[7:8] = v[8:9]) */
1121 if (did_copy
&& !copy
.second
.op
.isConstant()) {
1122 for (std::pair
<const PhysReg
, copy_operation
>& other
: copy_map
) {
1123 for (uint16_t i
= 0; i
< other
.second
.bytes
; i
++) {
1124 /* distance might underflow */
1125 unsigned distance
= other
.first
.reg_b
+ i
- copy
.second
.op
.physReg().reg_b
;
1126 if (distance
< copy
.second
.bytes
&& !copy
.second
.uses
[distance
])
1127 other
.second
.uses
[i
] -= 1;
1133 if (copy_map
.empty())
1136 /* all target regs are needed as operand somewhere which means, all entries are part of a cycle */
1137 unsigned largest
= 0;
1138 for (const std::pair
<PhysReg
, copy_operation
>& op
: copy_map
)
1139 largest
= MAX2(largest
, op
.second
.bytes
);
1141 while (!copy_map
.empty()) {
1143 /* Perform larger swaps first, because larger swaps swaps can make other
1144 * swaps unnecessary. */
1145 auto it
= copy_map
.begin();
1146 for (auto it2
= copy_map
.begin(); it2
!= copy_map
.end(); ++it2
) {
1147 if (it2
->second
.bytes
> it
->second
.bytes
) {
1149 if (it
->second
.bytes
== largest
)
1154 /* should already be done */
1155 assert(!it
->second
.op
.isConstant());
1157 assert(it
->second
.op
.isFixed());
1158 assert(it
->second
.def
.regClass() == it
->second
.op
.regClass());
1160 if (it
->first
== it
->second
.op
.physReg()) {
1165 if (preserve_scc
&& it
->second
.def
.getTemp().type() == RegType::sgpr
)
1166 assert(!(it
->second
.def
.physReg() == pi
->scratch_sgpr
));
1168 /* to resolve the cycle, we have to swap the src reg with the dst reg */
1169 copy_operation swap
= it
->second
;
1171 /* if this is self-intersecting, we have to split it because
1172 * self-intersecting swaps don't make sense */
1173 PhysReg lower
= swap
.def
.physReg();
1174 PhysReg higher
= swap
.op
.physReg();
1175 if (lower
.reg_b
> higher
.reg_b
)
1176 std::swap(lower
, higher
);
1177 if (higher
.reg_b
- lower
.reg_b
< (int)swap
.bytes
) {
1178 unsigned offset
= higher
.reg_b
- lower
.reg_b
;
1179 RegType type
= swap
.def
.regClass().type();
1181 copy_operation middle
;
1182 lower
.reg_b
+= offset
;
1183 higher
.reg_b
+= offset
;
1184 middle
.bytes
= swap
.bytes
- offset
* 2;
1185 memcpy(middle
.uses
, swap
.uses
+ offset
, middle
.bytes
);
1186 middle
.op
= Operand(lower
, RegClass::get(type
, middle
.bytes
));
1187 middle
.def
= Definition(higher
, RegClass::get(type
, middle
.bytes
));
1188 copy_map
[higher
] = middle
;
1191 lower
.reg_b
+= middle
.bytes
;
1192 higher
.reg_b
+= middle
.bytes
;
1193 end
.bytes
= swap
.bytes
- (offset
+ middle
.bytes
);
1194 memcpy(end
.uses
, swap
.uses
+ offset
+ middle
.bytes
, end
.bytes
);
1195 end
.op
= Operand(lower
, RegClass::get(type
, end
.bytes
));
1196 end
.def
= Definition(higher
, RegClass::get(type
, end
.bytes
));
1197 copy_map
[higher
] = end
;
1199 memset(swap
.uses
+ offset
, 0, swap
.bytes
- offset
);
1200 swap
.bytes
= offset
;
1203 do_swap(ctx
, bld
, swap
, preserve_scc
, pi
);
1205 /* remove from map */
1208 /* change the operand reg of the target's uses and split uses if needed */
1209 target
= copy_map
.begin();
1210 uint32_t bytes_left
= u_bit_consecutive(0, swap
.bytes
);
1211 for (; target
!= copy_map
.end(); ++target
) {
1212 if (target
->second
.op
.physReg() == swap
.def
.physReg() && swap
.bytes
== target
->second
.bytes
) {
1213 target
->second
.op
.setFixed(swap
.op
.physReg());
1217 uint32_t imask
= get_intersection_mask(swap
.def
.physReg().reg_b
, swap
.bytes
,
1218 target
->second
.op
.physReg().reg_b
, target
->second
.bytes
);
1223 assert(target
->second
.bytes
< swap
.bytes
);
1225 int offset
= (int)target
->second
.op
.physReg().reg_b
- (int)swap
.def
.physReg().reg_b
;
1227 /* split and update the middle (the portion that reads the swap's
1228 * definition) to read the swap's operand instead */
1229 int target_op_end
= target
->second
.op
.physReg().reg_b
+ target
->second
.bytes
;
1230 int swap_def_end
= swap
.def
.physReg().reg_b
+ swap
.bytes
;
1231 int before_bytes
= MAX2(-offset
, 0);
1232 int after_bytes
= MAX2(target_op_end
- swap_def_end
, 0);
1233 int middle_bytes
= target
->second
.bytes
- before_bytes
- after_bytes
;
1236 unsigned after_offset
= before_bytes
+ middle_bytes
;
1237 assert(after_offset
> 0);
1238 copy_operation copy
;
1239 copy
.bytes
= after_bytes
;
1240 memcpy(copy
.uses
, target
->second
.uses
+ after_offset
, copy
.bytes
);
1241 RegClass rc
= RegClass::get(target
->second
.op
.regClass().type(), after_bytes
);
1242 copy
.op
= Operand(target
->second
.op
.physReg().advance(after_offset
), rc
);
1243 copy
.def
= Definition(target
->second
.def
.physReg().advance(after_offset
), rc
);
1244 copy_map
[copy
.def
.physReg()] = copy
;
1248 copy_operation copy
;
1249 copy
.bytes
= middle_bytes
;
1250 memcpy(copy
.uses
, target
->second
.uses
+ before_bytes
, copy
.bytes
);
1251 RegClass rc
= RegClass::get(target
->second
.op
.regClass().type(), middle_bytes
);
1252 copy
.op
= Operand(swap
.op
.physReg().advance(MAX2(offset
, 0)), rc
);
1253 copy
.def
= Definition(target
->second
.def
.physReg().advance(before_bytes
), rc
);
1254 copy_map
[copy
.def
.physReg()] = copy
;
1258 copy_operation copy
;
1259 target
->second
.bytes
= before_bytes
;
1260 RegClass rc
= RegClass::get(target
->second
.op
.regClass().type(), before_bytes
);
1261 target
->second
.op
= Operand(target
->second
.op
.physReg(), rc
);
1262 target
->second
.def
= Definition(target
->second
.def
.physReg(), rc
);
1263 memset(target
->second
.uses
+ target
->second
.bytes
, 0, 8 - target
->second
.bytes
);
1266 /* break early since we know each byte of the swap's definition is used
1268 bytes_left
&= ~imask
;
1275 void lower_to_hw_instr(Program
* program
)
1277 Block
*discard_block
= NULL
;
1279 for (size_t i
= 0; i
< program
->blocks
.size(); i
++)
1281 Block
*block
= &program
->blocks
[i
];
1283 ctx
.program
= program
;
1284 Builder
bld(program
, &ctx
.instructions
);
1286 bool set_mode
= i
== 0 && block
->fp_mode
.val
!= program
->config
->float_mode
;
1287 for (unsigned pred
: block
->linear_preds
) {
1288 if (program
->blocks
[pred
].fp_mode
.val
!= block
->fp_mode
.val
) {
1294 /* only allow changing modes at top-level blocks so this doesn't break
1295 * the "jump over empty blocks" optimization */
1296 assert(block
->kind
& block_kind_top_level
);
1297 uint32_t mode
= block
->fp_mode
.val
;
1298 /* "((size - 1) << 11) | register" (MODE is encoded as register 1) */
1299 bld
.sopk(aco_opcode::s_setreg_imm32_b32
, Operand(mode
), (7 << 11) | 1);
1302 for (size_t j
= 0; j
< block
->instructions
.size(); j
++) {
1303 aco_ptr
<Instruction
>& instr
= block
->instructions
[j
];
1304 aco_ptr
<Instruction
> mov
;
1305 if (instr
->format
== Format::PSEUDO
) {
1306 Pseudo_instruction
*pi
= (Pseudo_instruction
*)instr
.get();
1308 switch (instr
->opcode
)
1310 case aco_opcode::p_extract_vector
:
1312 PhysReg reg
= instr
->operands
[0].physReg();
1313 Definition
& def
= instr
->definitions
[0];
1314 reg
.reg_b
+= instr
->operands
[1].constantValue() * def
.bytes();
1316 if (reg
== def
.physReg())
1319 RegClass op_rc
= def
.regClass().is_subdword() ? def
.regClass() :
1320 RegClass(instr
->operands
[0].getTemp().type(), def
.size());
1321 std::map
<PhysReg
, copy_operation
> copy_operations
;
1322 copy_operations
[def
.physReg()] = {Operand(reg
, op_rc
), def
, def
.bytes()};
1323 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
1326 case aco_opcode::p_create_vector
:
1328 std::map
<PhysReg
, copy_operation
> copy_operations
;
1329 PhysReg reg
= instr
->definitions
[0].physReg();
1331 for (const Operand
& op
: instr
->operands
) {
1332 if (op
.isConstant()) {
1333 const Definition def
= Definition(reg
, RegClass(instr
->definitions
[0].getTemp().type(), op
.size()));
1334 copy_operations
[reg
] = {op
, def
, op
.bytes()};
1335 reg
.reg_b
+= op
.bytes();
1338 if (op
.isUndefined()) {
1339 // TODO: coalesce subdword copies if dst byte is 0
1340 reg
.reg_b
+= op
.bytes();
1344 RegClass rc_def
= op
.regClass().is_subdword() ? op
.regClass() :
1345 RegClass(instr
->definitions
[0].getTemp().type(), op
.size());
1346 const Definition def
= Definition(reg
, rc_def
);
1347 copy_operations
[def
.physReg()] = {op
, def
, op
.bytes()};
1348 reg
.reg_b
+= op
.bytes();
1350 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
1353 case aco_opcode::p_split_vector
:
1355 std::map
<PhysReg
, copy_operation
> copy_operations
;
1356 PhysReg reg
= instr
->operands
[0].physReg();
1358 for (const Definition
& def
: instr
->definitions
) {
1359 RegClass rc_op
= def
.regClass().is_subdword() ? def
.regClass() :
1360 RegClass(instr
->operands
[0].getTemp().type(), def
.size());
1361 const Operand op
= Operand(reg
, rc_op
);
1362 copy_operations
[def
.physReg()] = {op
, def
, def
.bytes()};
1363 reg
.reg_b
+= def
.bytes();
1365 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
1368 case aco_opcode::p_parallelcopy
:
1369 case aco_opcode::p_wqm
:
1371 std::map
<PhysReg
, copy_operation
> copy_operations
;
1372 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1373 assert(instr
->definitions
[i
].bytes() == instr
->operands
[i
].bytes());
1374 copy_operations
[instr
->definitions
[i
].physReg()] = {instr
->operands
[i
], instr
->definitions
[i
], instr
->operands
[i
].bytes()};
1376 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
1379 case aco_opcode::p_exit_early_if
:
1381 /* don't bother with an early exit near the end of the program */
1382 if ((block
->instructions
.size() - 1 - j
) <= 4 &&
1383 block
->instructions
.back()->opcode
== aco_opcode::s_endpgm
) {
1384 unsigned null_exp_dest
= (ctx
.program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
1385 bool ignore_early_exit
= true;
1387 for (unsigned k
= j
+ 1; k
< block
->instructions
.size(); ++k
) {
1388 const aco_ptr
<Instruction
> &instr
= block
->instructions
[k
];
1389 if (instr
->opcode
== aco_opcode::s_endpgm
||
1390 instr
->opcode
== aco_opcode::p_logical_end
)
1392 else if (instr
->opcode
== aco_opcode::exp
&&
1393 static_cast<Export_instruction
*>(instr
.get())->dest
== null_exp_dest
)
1395 else if (instr
->opcode
== aco_opcode::p_parallelcopy
&&
1396 instr
->definitions
[0].isFixed() &&
1397 instr
->definitions
[0].physReg() == exec
)
1400 ignore_early_exit
= false;
1403 if (ignore_early_exit
)
1407 if (!discard_block
) {
1408 discard_block
= program
->create_and_insert_block();
1409 block
= &program
->blocks
[i
];
1411 bld
.reset(discard_block
);
1412 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
1413 0, V_008DFC_SQ_EXP_NULL
, false, true, true);
1414 if (program
->wb_smem_l1_on_end
)
1415 bld
.smem(aco_opcode::s_dcache_wb
);
1416 bld
.sopp(aco_opcode::s_endpgm
);
1418 bld
.reset(&ctx
.instructions
);
1421 //TODO: exec can be zero here with block_kind_discard
1423 assert(instr
->operands
[0].physReg() == scc
);
1424 bld
.sopp(aco_opcode::s_cbranch_scc0
, instr
->operands
[0], discard_block
->index
);
1426 discard_block
->linear_preds
.push_back(block
->index
);
1427 block
->linear_succs
.push_back(discard_block
->index
);
1430 case aco_opcode::p_spill
:
1432 assert(instr
->operands
[0].regClass() == v1
.as_linear());
1433 for (unsigned i
= 0; i
< instr
->operands
[2].size(); i
++)
1434 bld
.writelane(bld
.def(v1
, instr
->operands
[0].physReg()),
1435 Operand(PhysReg
{instr
->operands
[2].physReg() + i
}, s1
),
1436 Operand(instr
->operands
[1].constantValue() + i
),
1437 instr
->operands
[0]);
1440 case aco_opcode::p_reload
:
1442 assert(instr
->operands
[0].regClass() == v1
.as_linear());
1443 for (unsigned i
= 0; i
< instr
->definitions
[0].size(); i
++)
1444 bld
.readlane(bld
.def(s1
, PhysReg
{instr
->definitions
[0].physReg() + i
}),
1446 Operand(instr
->operands
[1].constantValue() + i
));
1449 case aco_opcode::p_as_uniform
:
1451 if (instr
->operands
[0].isConstant() || instr
->operands
[0].regClass().type() == RegType::sgpr
) {
1452 std::map
<PhysReg
, copy_operation
> copy_operations
;
1453 copy_operations
[instr
->definitions
[0].physReg()] = {instr
->operands
[0], instr
->definitions
[0], instr
->definitions
[0].bytes()};
1454 handle_operands(copy_operations
, &ctx
, program
->chip_class
, pi
);
1456 assert(instr
->operands
[0].regClass().type() == RegType::vgpr
);
1457 assert(instr
->definitions
[0].regClass().type() == RegType::sgpr
);
1458 assert(instr
->operands
[0].size() == instr
->definitions
[0].size());
1459 for (unsigned i
= 0; i
< instr
->definitions
[0].size(); i
++) {
1460 bld
.vop1(aco_opcode::v_readfirstlane_b32
,
1461 bld
.def(s1
, PhysReg
{instr
->definitions
[0].physReg() + i
}),
1462 Operand(PhysReg
{instr
->operands
[0].physReg() + i
}, v1
));
1470 } else if (instr
->format
== Format::PSEUDO_BRANCH
) {
1471 Pseudo_branch_instruction
* branch
= static_cast<Pseudo_branch_instruction
*>(instr
.get());
1472 /* check if all blocks from current to target are empty */
1473 bool can_remove
= block
->index
< branch
->target
[0];
1474 for (unsigned i
= block
->index
+ 1; can_remove
&& i
< branch
->target
[0]; i
++) {
1475 if (program
->blocks
[i
].instructions
.size())
1481 switch (instr
->opcode
) {
1482 case aco_opcode::p_branch
:
1483 assert(block
->linear_succs
[0] == branch
->target
[0]);
1484 bld
.sopp(aco_opcode::s_branch
, branch
->target
[0]);
1486 case aco_opcode::p_cbranch_nz
:
1487 assert(block
->linear_succs
[1] == branch
->target
[0]);
1488 if (branch
->operands
[0].physReg() == exec
)
1489 bld
.sopp(aco_opcode::s_cbranch_execnz
, branch
->target
[0]);
1490 else if (branch
->operands
[0].physReg() == vcc
)
1491 bld
.sopp(aco_opcode::s_cbranch_vccnz
, branch
->target
[0]);
1493 assert(branch
->operands
[0].physReg() == scc
);
1494 bld
.sopp(aco_opcode::s_cbranch_scc1
, branch
->target
[0]);
1497 case aco_opcode::p_cbranch_z
:
1498 assert(block
->linear_succs
[1] == branch
->target
[0]);
1499 if (branch
->operands
[0].physReg() == exec
)
1500 bld
.sopp(aco_opcode::s_cbranch_execz
, branch
->target
[0]);
1501 else if (branch
->operands
[0].physReg() == vcc
)
1502 bld
.sopp(aco_opcode::s_cbranch_vccz
, branch
->target
[0]);
1504 assert(branch
->operands
[0].physReg() == scc
);
1505 bld
.sopp(aco_opcode::s_cbranch_scc0
, branch
->target
[0]);
1509 unreachable("Unknown Pseudo branch instruction!");
1512 } else if (instr
->format
== Format::PSEUDO_REDUCTION
) {
1513 Pseudo_reduction_instruction
* reduce
= static_cast<Pseudo_reduction_instruction
*>(instr
.get());
1514 if (reduce
->reduce_op
== gfx10_wave64_bpermute
) {
1515 /* Only makes sense on GFX10 wave64 */
1516 assert(program
->chip_class
>= GFX10
);
1517 assert(program
->info
->wave_size
== 64);
1518 assert(instr
->definitions
[0].regClass() == v1
); /* Destination */
1519 assert(instr
->definitions
[1].regClass() == s2
); /* Temp EXEC */
1520 assert(instr
->definitions
[1].physReg() != vcc
);
1521 assert(instr
->definitions
[2].physReg() == scc
); /* SCC clobber */
1522 assert(instr
->operands
[0].physReg() == vcc
); /* Compare */
1523 assert(instr
->operands
[1].regClass() == v2
.as_linear()); /* Temp VGPR pair */
1524 assert(instr
->operands
[2].regClass() == v1
); /* Indices x4 */
1525 assert(instr
->operands
[3].bytes() <= 4); /* Indices x4 */
1527 PhysReg shared_vgpr_reg_lo
= PhysReg(align(program
->config
->num_vgprs
, 4) + 256);
1528 PhysReg shared_vgpr_reg_hi
= PhysReg(shared_vgpr_reg_lo
+ 1);
1529 Operand compare
= instr
->operands
[0];
1530 Operand
tmp1(instr
->operands
[1].physReg(), v1
);
1531 Operand
tmp2(PhysReg(instr
->operands
[1].physReg() + 1), v1
);
1532 Operand index_x4
= instr
->operands
[2];
1533 Operand input_data
= instr
->operands
[3];
1534 Definition
shared_vgpr_lo(shared_vgpr_reg_lo
, v1
);
1535 Definition
shared_vgpr_hi(shared_vgpr_reg_hi
, v1
);
1536 Definition
def_temp1(tmp1
.physReg(), v1
);
1537 Definition
def_temp2(tmp2
.physReg(), v1
);
1539 /* Save EXEC and set it for all lanes */
1540 bld
.sop1(aco_opcode::s_or_saveexec_b64
, instr
->definitions
[1], instr
->definitions
[2],
1541 Definition(exec
, s2
), Operand((uint64_t)-1), Operand(exec
, s2
));
1543 /* HI: Copy data from high lanes 32-63 to shared vgpr */
1544 bld
.vop1_dpp(aco_opcode::v_mov_b32
, shared_vgpr_hi
, input_data
, dpp_quad_perm(0, 1, 2, 3), 0xc, 0xf, false);
1546 /* LO: Copy data from low lanes 0-31 to shared vgpr */
1547 bld
.vop1_dpp(aco_opcode::v_mov_b32
, shared_vgpr_lo
, input_data
, dpp_quad_perm(0, 1, 2, 3), 0x3, 0xf, false);
1548 /* LO: Copy shared vgpr (high lanes' data) to output vgpr */
1549 bld
.vop1_dpp(aco_opcode::v_mov_b32
, def_temp1
, Operand(shared_vgpr_reg_hi
, v1
), dpp_quad_perm(0, 1, 2, 3), 0x3, 0xf, false);
1551 /* HI: Copy shared vgpr (low lanes' data) to output vgpr */
1552 bld
.vop1_dpp(aco_opcode::v_mov_b32
, def_temp1
, Operand(shared_vgpr_reg_lo
, v1
), dpp_quad_perm(0, 1, 2, 3), 0xc, 0xf, false);
1554 /* Permute the original input */
1555 bld
.ds(aco_opcode::ds_bpermute_b32
, def_temp2
, index_x4
, input_data
);
1556 /* Permute the swapped input */
1557 bld
.ds(aco_opcode::ds_bpermute_b32
, def_temp1
, index_x4
, tmp1
);
1559 /* Restore saved EXEC */
1560 bld
.sop1(aco_opcode::s_mov_b64
, Definition(exec
, s2
), Operand(instr
->definitions
[1].physReg(), s2
));
1561 /* Choose whether to use the original or swapped */
1562 bld
.vop2(aco_opcode::v_cndmask_b32
, instr
->definitions
[0], tmp1
, tmp2
, compare
);
1564 emit_reduction(&ctx
, reduce
->opcode
, reduce
->reduce_op
, reduce
->cluster_size
,
1565 reduce
->operands
[1].physReg(), // tmp
1566 reduce
->definitions
[1].physReg(), // stmp
1567 reduce
->operands
[2].physReg(), // vtmp
1568 reduce
->definitions
[2].physReg(), // sitmp
1569 reduce
->operands
[0], reduce
->definitions
[0]);
1572 ctx
.instructions
.emplace_back(std::move(instr
));
1576 block
->instructions
.swap(ctx
.instructions
);