src/amd/compiler/aco_opt_value_numbering.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <map>
  26 #include <unordered_map>
  27 #include "aco_ir.h"
  28
  29 /*
  30  * Implements the algorithm for dominator-tree value numbering
  31  * from "Value Numbering" by Briggs, Cooper, and Simpson.
  32  */
  33
  34 namespace aco {
  35 namespace {
  36
  37 inline
  38 uint32_t murmur_32_scramble(uint32_t h, uint32_t k) {
  39    k *= 0xcc9e2d51;
  40    k = (k << 15) | (k >> 17);
  41    h ^= k * 0x1b873593;
  42    h = (h << 13) | (h >> 19);
  43    h = h * 5 + 0xe6546b64;
  44    return h;
  45 }
  46
  47 template<typename T>
  48 uint32_t hash_murmur_32(Instruction* instr)
  49 {
  50    uint32_t hash = uint32_t(instr->format) << 16 | uint32_t(instr->opcode);
  51
  52    for (const Operand& op : instr->operands)
  53       hash = murmur_32_scramble(hash, op.constantValue());
  54
  55    /* skip format, opcode and pass_flags */
  56    for (unsigned i = 2; i < (sizeof(T) >> 2); i++) {
  57       uint32_t u;
  58       /* Accesses it though a byte array, so doesn't violate the strict aliasing rule */
  59       memcpy(&u, reinterpret_cast<uint8_t *>(instr) + i * 4, 4);
  60       hash = murmur_32_scramble(hash, u);
  61    }
  62
  63    /* Finalize. */
  64    uint32_t len = instr->operands.size() + instr->definitions.size() + sizeof(T);
  65    hash ^= len;
  66    hash ^= hash >> 16;
  67    hash *= 0x85ebca6b;
  68    hash ^= hash >> 13;
  69    hash *= 0xc2b2ae35;
  70    hash ^= hash >> 16;
  71    return hash;
  72 }
  73
  74 struct InstrHash {
  75    /* This hash function uses the Murmur3 algorithm written by Austin Appleby
  76     * https://github.com/aappleby/smhasher/blob/master/src/MurmurHash3.cpp
  77     *
  78     * In order to calculate the expression set, only the right-hand-side of an
  79     * instruction is used for the hash, i.e. everything except the definitions.
  80     */
  81    std::size_t operator()(Instruction* instr) const
  82    {
  83       if (instr->isVOP3())
  84          return hash_murmur_32<VOP3A_instruction>(instr);
  85
  86       if (instr->isDPP())
  87          return hash_murmur_32<DPP_instruction>(instr);
  88
  89       switch (instr->format) {
  90       case Format::SMEM:
  91          return hash_murmur_32<SMEM_instruction>(instr);
  92       case Format::VINTRP:
  93          return hash_murmur_32<Interp_instruction>(instr);
  94       case Format::DS:
  95          return hash_murmur_32<DS_instruction>(instr);
  96       case Format::SOPP:
  97          return hash_murmur_32<SOPP_instruction>(instr);
  98       case Format::SOPK:
  99          return hash_murmur_32<SOPK_instruction>(instr);
 100       case Format::EXP:
 101          return hash_murmur_32<Export_instruction>(instr);
 102       case Format::MUBUF:
 103          return hash_murmur_32<MUBUF_instruction>(instr);
 104       case Format::MIMG:
 105          return hash_murmur_32<MIMG_instruction>(instr);
 106       case Format::MTBUF:
 107          return hash_murmur_32<MTBUF_instruction>(instr);
 108       case Format::FLAT:
 109          return hash_murmur_32<FLAT_instruction>(instr);
 110       case Format::PSEUDO_BRANCH:
 111          return hash_murmur_32<Pseudo_branch_instruction>(instr);
 112       case Format::PSEUDO_REDUCTION:
 113          return hash_murmur_32<Pseudo_reduction_instruction>(instr);
 114       default:
 115          return hash_murmur_32<Instruction>(instr);
 116       }
 117    }
 118 };
 119
 120 struct InstrPred {
 121    bool operator()(Instruction* a, Instruction* b) const
 122    {
 123       if (a->format != b->format)
 124          return false;
 125       if (a->opcode != b->opcode)
 126          return false;
 127       if (a->operands.size() != b->operands.size() || a->definitions.size() != b->definitions.size())
 128          return false; /* possible with pseudo-instructions */
 129       for (unsigned i = 0; i < a->operands.size(); i++) {
 130          if (a->operands[i].isConstant()) {
 131             if (!b->operands[i].isConstant())
 132                return false;
 133             if (a->operands[i].constantValue() != b->operands[i].constantValue())
 134                return false;
 135          }
 136          else if (a->operands[i].isTemp()) {
 137             if (!b->operands[i].isTemp())
 138                return false;
 139             if (a->operands[i].tempId() != b->operands[i].tempId())
 140                return false;
 141          }
 142          else if (a->operands[i].isUndefined() ^ b->operands[i].isUndefined())
 143             return false;
 144          if (a->operands[i].isFixed()) {
 145             if (!b->operands[i].isFixed())
 146                return false;
 147             if (a->operands[i].physReg() != b->operands[i].physReg())
 148                return false;
 149             if (a->operands[i].physReg() == exec && a->pass_flags != b->pass_flags)
 150                return false;
 151          }
 152       }
 153       for (unsigned i = 0; i < a->definitions.size(); i++) {
 154          if (a->definitions[i].isTemp()) {
 155             if (!b->definitions[i].isTemp())
 156                return false;
 157             if (a->definitions[i].regClass() != b->definitions[i].regClass())
 158                return false;
 159          }
 160          if (a->definitions[i].isFixed()) {
 161             if (!b->definitions[i].isFixed())
 162                return false;
 163             if (a->definitions[i].physReg() != b->definitions[i].physReg())
 164                return false;
 165             if (a->definitions[i].physReg() == exec)
 166                return false;
 167          }
 168       }
 169
 170       if (a->opcode == aco_opcode::v_readfirstlane_b32)
 171          return a->pass_flags == b->pass_flags;
 172
 173       /* The results of VOPC depend on the exec mask if used for subgroup operations. */
 174       if ((uint32_t) a->format & (uint32_t) Format::VOPC && a->pass_flags != b->pass_flags)
 175          return false;
 176
 177       if (a->isVOP3()) {
 178          VOP3A_instruction* a3 = static_cast<VOP3A_instruction*>(a);
 179          VOP3A_instruction* b3 = static_cast<VOP3A_instruction*>(b);
 180          for (unsigned i = 0; i < 3; i++) {
 181             if (a3->abs[i] != b3->abs[i] ||
 182                 a3->neg[i] != b3->neg[i])
 183                return false;
 184          }
 185          return a3->clamp == b3->clamp &&
 186                 a3->omod == b3->omod &&
 187                 a3->opsel == b3->opsel;
 188       }
 189       if (a->isDPP()) {
 190          DPP_instruction* aDPP = static_cast<DPP_instruction*>(a);
 191          DPP_instruction* bDPP = static_cast<DPP_instruction*>(b);
 192          return aDPP->pass_flags == bDPP->pass_flags &&
 193                 aDPP->dpp_ctrl == bDPP->dpp_ctrl &&
 194                 aDPP->bank_mask == bDPP->bank_mask &&
 195                 aDPP->row_mask == bDPP->row_mask &&
 196                 aDPP->bound_ctrl == bDPP->bound_ctrl &&
 197                 aDPP->abs[0] == bDPP->abs[0] &&
 198                 aDPP->abs[1] == bDPP->abs[1] &&
 199                 aDPP->neg[0] == bDPP->neg[0] &&
 200                 aDPP->neg[1] == bDPP->neg[1];
 201       }
 202
 203       switch (a->format) {
 204          case Format::SOPK: {
 205             SOPK_instruction* aK = static_cast<SOPK_instruction*>(a);
 206             SOPK_instruction* bK = static_cast<SOPK_instruction*>(b);
 207             return aK->imm == bK->imm;
 208          }
 209          case Format::SMEM: {
 210             SMEM_instruction* aS = static_cast<SMEM_instruction*>(a);
 211             SMEM_instruction* bS = static_cast<SMEM_instruction*>(b);
 212             return aS->can_reorder && bS->can_reorder &&
 213                    aS->glc == bS->glc && aS->nv == bS->nv;
 214          }
 215          case Format::VINTRP: {
 216             Interp_instruction* aI = static_cast<Interp_instruction*>(a);
 217             Interp_instruction* bI = static_cast<Interp_instruction*>(b);
 218             if (aI->attribute != bI->attribute)
 219                return false;
 220             if (aI->component != bI->component)
 221                return false;
 222             return true;
 223          }
 224          case Format::PSEUDO_REDUCTION: {
 225             Pseudo_reduction_instruction *aR = static_cast<Pseudo_reduction_instruction*>(a);
 226             Pseudo_reduction_instruction *bR = static_cast<Pseudo_reduction_instruction*>(b);
 227             return aR->pass_flags == bR->pass_flags &&
 228                    aR->reduce_op == bR->reduce_op &&
 229                    aR->cluster_size == bR->cluster_size;
 230          }
 231          case Format::MTBUF: {
 232             MTBUF_instruction* aM = static_cast<MTBUF_instruction *>(a);
 233             MTBUF_instruction* bM = static_cast<MTBUF_instruction *>(b);
 234             return aM->can_reorder && bM->can_reorder &&
 235                    aM->barrier == bM->barrier &&
 236                    aM->dfmt == bM->dfmt &&
 237                    aM->nfmt == bM->nfmt &&
 238                    aM->offset == bM->offset &&
 239                    aM->offen == bM->offen &&
 240                    aM->idxen == bM->idxen &&
 241                    aM->glc == bM->glc &&
 242                    aM->dlc == bM->dlc &&
 243                    aM->slc == bM->slc &&
 244                    aM->tfe == bM->tfe &&
 245                    aM->disable_wqm == bM->disable_wqm;
 246          }
 247          case Format::MUBUF: {
 248             MUBUF_instruction* aM = static_cast<MUBUF_instruction *>(a);
 249             MUBUF_instruction* bM = static_cast<MUBUF_instruction *>(b);
 250             return aM->can_reorder && bM->can_reorder &&
 251                    aM->barrier == bM->barrier &&
 252                    aM->offset == bM->offset &&
 253                    aM->offen == bM->offen &&
 254                    aM->idxen == bM->idxen &&
 255                    aM->glc == bM->glc &&
 256                    aM->dlc == bM->dlc &&
 257                    aM->slc == bM->slc &&
 258                    aM->tfe == bM->tfe &&
 259                    aM->lds == bM->lds &&
 260                    aM->disable_wqm == bM->disable_wqm;
 261          }
 262          /* we want to optimize these in NIR and don't hassle with load-store dependencies */
 263          case Format::FLAT:
 264          case Format::GLOBAL:
 265          case Format::SCRATCH:
 266          case Format::EXP:
 267          case Format::SOPP:
 268          case Format::PSEUDO_BRANCH:
 269          case Format::PSEUDO_BARRIER:
 270             return false;
 271          case Format::DS: {
 272             if (a->opcode != aco_opcode::ds_bpermute_b32 &&
 273                 a->opcode != aco_opcode::ds_permute_b32 &&
 274                 a->opcode != aco_opcode::ds_swizzle_b32)
 275                return false;
 276             DS_instruction* aD = static_cast<DS_instruction *>(a);
 277             DS_instruction* bD = static_cast<DS_instruction *>(b);
 278             return aD->pass_flags == bD->pass_flags &&
 279                    aD->gds == bD->gds &&
 280                    aD->offset0 == bD->offset0 &&
 281                    aD->offset1 == bD->offset1;
 282          }
 283          case Format::MIMG: {
 284             MIMG_instruction* aM = static_cast<MIMG_instruction*>(a);
 285             MIMG_instruction* bM = static_cast<MIMG_instruction*>(b);
 286             return aM->can_reorder && bM->can_reorder &&
 287                    aM->barrier == bM->barrier &&
 288                    aM->dmask == bM->dmask &&
 289                    aM->unrm == bM->unrm &&
 290                    aM->glc == bM->glc &&
 291                    aM->slc == bM->slc &&
 292                    aM->tfe == bM->tfe &&
 293                    aM->da == bM->da &&
 294                    aM->lwe == bM->lwe &&
 295                    aM->r128 == bM->r128 &&
 296                    aM->a16 == bM->a16 &&
 297                    aM->d16 == bM->d16 &&
 298                    aM->disable_wqm == bM->disable_wqm;
 299          }
 300          default:
 301             return true;
 302       }
 303    }
 304 };
 305
 306 using expr_set = std::unordered_map<Instruction*, uint32_t, InstrHash, InstrPred>;
 307
 308 struct vn_ctx {
 309    Program* program;
 310    expr_set expr_values;
 311    std::map<uint32_t, Temp> renames;
 312
 313    /* The exec id should be the same on the same level of control flow depth.
 314     * Together with the check for dominator relations, it is safe to assume
 315     * that the same exec_id also means the same execution mask.
 316     * Discards increment the exec_id, so that it won't return to the previous value.
 317     */
 318    uint32_t exec_id = 1;
 319
 320    vn_ctx(Program* program) : program(program) {
 321       static_assert(sizeof(Temp) == 4, "Temp must fit in 32bits");
 322       unsigned size = 0;
 323       for (Block& block : program->blocks)
 324          size += block.instructions.size();
 325       expr_values.reserve(size);
 326    }
 327 };
 328
 329
 330 /* dominates() returns true if the parent block dominates the child block and
 331  * if the parent block is part of the same loop or has a smaller loop nest depth.
 332  */
 333 bool dominates(vn_ctx& ctx, uint32_t parent, uint32_t child)
 334 {
 335    unsigned parent_loop_nest_depth = ctx.program->blocks[parent].loop_nest_depth;
 336    while (parent < child && parent_loop_nest_depth <= ctx.program->blocks[child].loop_nest_depth)
 337       child = ctx.program->blocks[child].logical_idom;
 338
 339    return parent == child;
 340 }
 341
 342 void process_block(vn_ctx& ctx, Block& block)
 343 {
 344    std::vector<aco_ptr<Instruction>> new_instructions;
 345    new_instructions.reserve(block.instructions.size());
 346
 347    for (aco_ptr<Instruction>& instr : block.instructions) {
 348       /* first, rename operands */
 349       for (Operand& op : instr->operands) {
 350          if (!op.isTemp())
 351             continue;
 352          auto it = ctx.renames.find(op.tempId());
 353          if (it != ctx.renames.end())
 354             op.setTemp(it->second);
 355       }
 356
 357       if (instr->opcode == aco_opcode::p_discard_if ||
 358           instr->opcode == aco_opcode::p_demote_to_helper)
 359          ctx.exec_id++;
 360
 361       if (instr->definitions.empty() || instr->opcode == aco_opcode::p_phi || instr->opcode == aco_opcode::p_linear_phi) {
 362          new_instructions.emplace_back(std::move(instr));
 363          continue;
 364       }
 365
 366       /* simple copy-propagation through renaming */
 367       if ((instr->opcode == aco_opcode::s_mov_b32 || instr->opcode == aco_opcode::s_mov_b64 || instr->opcode == aco_opcode::v_mov_b32) &&
 368           !instr->definitions[0].isFixed() && instr->operands[0].isTemp() && instr->operands[0].regClass() == instr->definitions[0].regClass() &&
 369           !instr->isDPP() && !((int)instr->format & (int)Format::SDWA)) {
 370          ctx.renames[instr->definitions[0].tempId()] = instr->operands[0].getTemp();
 371       }
 372
 373       instr->pass_flags = ctx.exec_id;
 374       std::pair<expr_set::iterator, bool> res = ctx.expr_values.emplace(instr.get(), block.index);
 375
 376       /* if there was already an expression with the same value number */
 377       if (!res.second) {
 378          Instruction* orig_instr = res.first->first;
 379          assert(instr->definitions.size() == orig_instr->definitions.size());
 380          /* check if the original instruction dominates the current one */
 381          if (dominates(ctx, res.first->second, block.index) &&
 382              ctx.program->blocks[res.first->second].fp_mode.canReplace(block.fp_mode)) {
 383             for (unsigned i = 0; i < instr->definitions.size(); i++) {
 384                assert(instr->definitions[i].regClass() == orig_instr->definitions[i].regClass());
 385                assert(instr->definitions[i].isTemp());
 386                ctx.renames[instr->definitions[i].tempId()] = orig_instr->definitions[i].getTemp();
 387             }
 388          } else {
 389             ctx.expr_values.erase(res.first);
 390             ctx.expr_values.emplace(instr.get(), block.index);
 391             new_instructions.emplace_back(std::move(instr));
 392          }
 393       } else {
 394          new_instructions.emplace_back(std::move(instr));
 395       }
 396    }
 397
 398    block.instructions = std::move(new_instructions);
 399 }
 400
 401 void rename_phi_operands(Block& block, std::map<uint32_t, Temp>& renames)
 402 {
 403    for (aco_ptr<Instruction>& phi : block.instructions) {
 404       if (phi->opcode != aco_opcode::p_phi && phi->opcode != aco_opcode::p_linear_phi)
 405          break;
 406
 407       for (Operand& op : phi->operands) {
 408          if (!op.isTemp())
 409             continue;
 410          auto it = renames.find(op.tempId());
 411          if (it != renames.end())
 412             op.setTemp(it->second);
 413       }
 414    }
 415 }
 416 } /* end namespace */
 417
 418
 419 void value_numbering(Program* program)
 420 {
 421    vn_ctx ctx(program);
 422    std::vector<unsigned> loop_headers;
 423
 424    for (Block& block : program->blocks) {
 425       assert(ctx.exec_id > 0);
 426       /* decrement exec_id when leaving nested control flow */
 427       if (block.kind & block_kind_loop_header)
 428          loop_headers.push_back(block.index);
 429       if (block.kind & block_kind_merge) {
 430          ctx.exec_id--;
 431       } else if (block.kind & block_kind_loop_exit) {
 432          ctx.exec_id -= program->blocks[loop_headers.back()].linear_preds.size();
 433          ctx.exec_id -= block.linear_preds.size();
 434          loop_headers.pop_back();
 435       }
 436
 437       if (block.logical_idom != -1)
 438          process_block(ctx, block);
 439       else
 440          rename_phi_operands(block, ctx.renames);
 441
 442       /* increment exec_id when entering nested control flow */
 443       if (block.kind & block_kind_branch ||
 444           block.kind & block_kind_loop_preheader ||
 445           block.kind & block_kind_break ||
 446           block.kind & block_kind_continue ||
 447           block.kind & block_kind_discard)
 448          ctx.exec_id++;
 449       else if (block.kind & block_kind_continue_or_break)
 450          ctx.exec_id += 2;
 451    }
 452
 453    /* rename loop header phi operands */
 454    for (Block& block : program->blocks) {
 455       if (block.kind & block_kind_loop_header)
 456          rename_phi_operands(block, ctx.renames);
 457    }
 458 }
 459
 460 }