2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
85 label_uniform_bool
= 1 << 21,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
| label_omod2
| label_omod4
| label_omod5
| label_clamp
;
90 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_abs(Temp abs_temp
)
143 add_label(label_abs
);
149 return label
& label_abs
;
152 void set_neg(Temp neg_temp
)
154 add_label(label_neg
);
160 return label
& label_neg
;
163 void set_neg_abs(Temp neg_abs_temp
)
165 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
169 void set_mul(Instruction
* mul
)
171 add_label(label_mul
);
177 return label
& label_mul
;
180 void set_temp(Temp tmp
)
182 add_label(label_temp
);
188 return label
& label_temp
;
191 void set_literal(uint32_t lit
)
193 add_label(label_literal
);
199 return label
& label_literal
;
202 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
204 add_label(label_mad
);
211 return label
& label_mad
;
214 void set_omod2(Temp def
)
216 add_label(label_omod2
);
222 return label
& label_omod2
;
225 void set_omod4(Temp def
)
227 add_label(label_omod4
);
233 return label
& label_omod4
;
236 void set_omod5(Temp def
)
238 add_label(label_omod5
);
244 return label
& label_omod5
;
247 void set_omod_success(Instruction
* omod_instr
)
249 add_label(label_omod_success
);
253 bool is_omod_success()
255 return label
& label_omod_success
;
258 void set_clamp(Temp def
)
260 add_label(label_clamp
);
266 return label
& label_clamp
;
269 void set_clamp_success(Instruction
* clamp_instr
)
271 add_label(label_clamp_success
);
275 bool is_clamp_success()
277 return label
& label_clamp_success
;
282 add_label(label_undefined
);
287 return label
& label_undefined
;
290 void set_vcc(Temp vcc
)
292 add_label(label_vcc
);
298 return label
& label_vcc
;
301 bool is_constant_or_literal()
303 return is_constant() || is_literal();
306 void set_b2f(Temp val
)
308 add_label(label_b2f
);
314 return label
& label_b2f
;
317 void set_add_sub(Instruction
*add_sub_instr
)
319 add_label(label_add_sub
);
320 instr
= add_sub_instr
;
325 return label
& label_add_sub
;
328 void set_bitwise(Instruction
*bitwise_instr
)
330 add_label(label_bitwise
);
331 instr
= bitwise_instr
;
336 return label
& label_bitwise
;
339 void set_minmax(Instruction
*minmax_instr
)
341 add_label(label_minmax
);
342 instr
= minmax_instr
;
347 return label
& label_minmax
;
350 void set_fcmp(Instruction
*fcmp_instr
)
352 add_label(label_fcmp
);
358 return label
& label_fcmp
;
361 void set_uniform_bool(Temp uniform_bool
)
363 add_label(label_uniform_bool
);
367 bool is_uniform_bool()
369 return label
& label_uniform_bool
;
376 std::vector
<aco_ptr
<Instruction
>> instructions
;
378 std::pair
<uint32_t,Temp
> last_literal
;
379 std::vector
<mad_info
> mad_infos
;
380 std::vector
<uint16_t> uses
;
383 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
385 if (instr
->operands
[0].isConstant() ||
386 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
389 switch (instr
->opcode
) {
390 case aco_opcode::v_add_f32
:
391 case aco_opcode::v_mul_f32
:
392 case aco_opcode::v_or_b32
:
393 case aco_opcode::v_and_b32
:
394 case aco_opcode::v_xor_b32
:
395 case aco_opcode::v_max_f32
:
396 case aco_opcode::v_min_f32
:
397 case aco_opcode::v_cmp_eq_f32
:
398 case aco_opcode::v_cmp_lg_f32
:
400 case aco_opcode::v_sub_f32
:
401 instr
->opcode
= aco_opcode::v_subrev_f32
;
403 case aco_opcode::v_cmp_lt_f32
:
404 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
406 case aco_opcode::v_cmp_ge_f32
:
407 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
409 case aco_opcode::v_cmp_lt_i32
:
410 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
417 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
422 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
425 if (instr
->isDPP() || instr
->isSDWA())
428 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
429 instr
->opcode
!= aco_opcode::v_madak_f32
&&
430 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
431 instr
->opcode
!= aco_opcode::v_madak_f16
&&
432 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
433 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
434 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
435 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
436 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
437 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
438 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
441 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
443 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
444 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
445 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
446 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
447 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
450 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
455 assert(!instr
->operands
[0].isLiteral());
456 aco_ptr
<Instruction
> tmp
= std::move(instr
);
457 Format format
= asVOP3(tmp
->format
);
458 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
459 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
460 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
461 instr
->definitions
[i
] = tmp
->definitions
[i
];
462 if (instr
->definitions
[i
].isTemp()) {
463 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
464 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
465 info
.instr
= instr
.get();
470 /* only covers special cases */
471 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
473 switch (instr
->opcode
) {
474 case aco_opcode::v_interp_p2_f32
:
475 case aco_opcode::v_mac_f32
:
476 case aco_opcode::v_writelane_b32
:
477 case aco_opcode::v_writelane_b32_e64
:
478 case aco_opcode::v_cndmask_b32
:
480 case aco_opcode::s_addk_i32
:
481 case aco_opcode::s_mulk_i32
:
482 case aco_opcode::p_wqm
:
483 case aco_opcode::p_extract_vector
:
484 case aco_opcode::p_split_vector
:
485 case aco_opcode::v_readlane_b32
:
486 case aco_opcode::v_readlane_b32_e64
:
487 case aco_opcode::v_readfirstlane_b32
:
490 if ((instr
->format
== Format::MUBUF
||
491 instr
->format
== Format::MIMG
) &&
492 instr
->definitions
.size() == 1 &&
493 instr
->operands
.size() == 4) {
500 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
502 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
503 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
508 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
510 Operand op
= instr
->operands
[op_index
];
514 Temp tmp
= op
.getTemp();
515 if (!ctx
.info
[tmp
.id()].is_add_sub())
518 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
520 switch (add_instr
->opcode
) {
521 case aco_opcode::v_add_u32
:
522 case aco_opcode::v_add_co_u32
:
523 case aco_opcode::s_add_i32
:
524 case aco_opcode::s_add_u32
:
530 if (add_instr
->usesModifiers())
533 for (unsigned i
= 0; i
< 2; i
++) {
534 if (add_instr
->operands
[i
].isConstant()) {
535 *offset
= add_instr
->operands
[i
].constantValue();
536 } else if (add_instr
->operands
[i
].isTemp() &&
537 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
538 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
542 if (!add_instr
->operands
[!i
].isTemp())
545 uint32_t offset2
= 0;
546 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
549 *base
= add_instr
->operands
[!i
].getTemp();
557 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
)
559 // TODO: this functions shouldn't be needed if we store Operand instead of value.
561 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
562 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
566 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
568 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
569 ASSERTED
bool all_const
= false;
570 for (Operand
& op
: instr
->operands
)
571 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
572 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
575 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
577 if (!instr
->operands
[i
].isTemp())
580 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
581 /* propagate undef */
582 if (info
.is_undefined() && is_phi(instr
))
583 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
584 /* propagate reg->reg of same type */
585 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
586 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
587 info
= ctx
.info
[info
.temp
.id()];
590 /* SALU / PSEUDO: propagate inline constants */
591 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
592 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
593 instr
->operands
[i
].setTemp(info
.temp
);
594 info
= ctx
.info
[info
.temp
.id()];
595 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
596 /* propagate vgpr if it can take it */
597 switch (instr
->opcode
) {
598 case aco_opcode::p_create_vector
:
599 case aco_opcode::p_split_vector
:
600 case aco_opcode::p_extract_vector
:
601 case aco_opcode::p_phi
: {
602 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
603 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
605 instr
->operands
[i
] = Operand(info
.temp
);
606 info
= ctx
.info
[info
.temp
.id()];
614 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
615 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
620 /* VALU: propagate neg, abs & inline constants */
621 else if (instr
->isVALU()) {
622 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
623 instr
->operands
[i
].setTemp(info
.temp
);
624 info
= ctx
.info
[info
.temp
.id()];
626 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
629 instr
->operands
[i
] = Operand(info
.temp
);
631 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
633 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
635 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
636 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
637 instr
->operands
[i
].setTemp(info
.temp
);
639 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
642 instr
->operands
[i
].setTemp(info
.temp
);
644 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
646 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
649 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
650 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
651 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
652 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
654 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
655 instr
->operands
[i
] = instr
->operands
[0];
656 instr
->operands
[0] = get_constant_op(ctx
, info
.val
);
658 } else if (can_use_VOP3(instr
)) {
660 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
666 /* MUBUF: propagate constants and combine additions */
667 else if (instr
->format
== Format::MUBUF
) {
668 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
671 while (info
.is_temp())
672 info
= ctx
.info
[info
.temp
.id()];
674 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
675 assert(!mubuf
->idxen
);
676 instr
->operands
[i
] = Operand(v1
);
677 mubuf
->offset
+= info
.val
;
678 mubuf
->offen
= false;
680 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
681 instr
->operands
[2] = Operand((uint32_t) 0);
682 mubuf
->offset
+= info
.val
;
684 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
685 assert(!mubuf
->idxen
);
686 instr
->operands
[i
].setTemp(base
);
687 mubuf
->offset
+= offset
;
689 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
690 instr
->operands
[i
].setTemp(base
);
691 mubuf
->offset
+= offset
;
696 /* DS: combine additions */
697 else if (instr
->format
== Format::DS
) {
699 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
702 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
703 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
704 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
705 if (offset
% 4 == 0 &&
706 ds
->offset0
+ (offset
>> 2) <= 255 &&
707 ds
->offset1
+ (offset
>> 2) <= 255) {
708 instr
->operands
[i
].setTemp(base
);
709 ds
->offset0
+= offset
>> 2;
710 ds
->offset1
+= offset
>> 2;
713 if (ds
->offset0
+ offset
<= 65535) {
714 instr
->operands
[i
].setTemp(base
);
715 ds
->offset0
+= offset
;
721 /* SMEM: propagate constants and combine additions */
722 else if (instr
->format
== Format::SMEM
) {
724 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
727 if (i
== 1 && info
.is_constant_or_literal() &&
728 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
729 instr
->operands
[i
] = Operand(info
.val
);
731 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
732 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
734 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
735 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
739 smem
->operands
[1] = Operand(offset
);
740 smem
->operands
.back() = Operand(base
);
742 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
743 new_instr
->operands
[0] = smem
->operands
[0];
744 new_instr
->operands
[1] = Operand(offset
);
745 if (smem
->definitions
.empty())
746 new_instr
->operands
[2] = smem
->operands
[2];
747 new_instr
->operands
.back() = Operand(base
);
748 if (!smem
->definitions
.empty())
749 new_instr
->definitions
[0] = smem
->definitions
[0];
750 new_instr
->can_reorder
= smem
->can_reorder
;
751 new_instr
->barrier
= smem
->barrier
;
752 instr
.reset(new_instr
);
753 smem
= static_cast<SMEM_instruction
*>(instr
.get());
760 /* if this instruction doesn't define anything, return */
761 if (instr
->definitions
.empty())
764 switch (instr
->opcode
) {
765 case aco_opcode::p_create_vector
: {
766 unsigned num_ops
= instr
->operands
.size();
767 for (const Operand
& op
: instr
->operands
) {
768 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
769 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
771 if (num_ops
!= instr
->operands
.size()) {
772 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
773 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
774 instr
->definitions
[0] = old_vec
->definitions
[0];
776 for (Operand
& old_op
: old_vec
->operands
) {
777 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
778 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
779 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
780 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
781 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
782 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
783 instr
->operands
[k
++] = op
;
786 instr
->operands
[k
++] = old_op
;
789 assert(k
== num_ops
);
791 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
792 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
793 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
794 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
797 case aco_opcode::p_split_vector
: {
798 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
800 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
801 assert(instr
->definitions
.size() == vec
->operands
.size());
802 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
803 Operand vec_op
= vec
->operands
[i
];
804 if (vec_op
.isConstant()) {
805 if (vec_op
.isLiteral())
806 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
807 else if (vec_op
.size() == 1)
808 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
810 assert(vec_op
.isTemp());
811 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
816 case aco_opcode::p_extract_vector
: { /* mov */
817 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
819 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
820 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
821 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
823 /* convert this extract into a mov instruction */
824 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
825 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
826 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
827 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
828 instr
->opcode
= opcode
;
829 instr
->format
= format
;
830 while (instr
->operands
.size() > 1)
831 instr
->operands
.pop_back();
832 instr
->operands
[0] = vec_op
;
834 if (vec_op
.isConstant()) {
835 if (vec_op
.isLiteral())
836 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
837 else if (vec_op
.size() == 1)
838 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
840 assert(vec_op
.isTemp());
841 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
846 case aco_opcode::s_mov_b32
: /* propagate */
847 case aco_opcode::s_mov_b64
:
848 case aco_opcode::v_mov_b32
:
849 case aco_opcode::p_as_uniform
:
850 if (instr
->definitions
[0].isFixed()) {
851 /* don't copy-propagate copies into fixed registers */
852 } else if (instr
->usesModifiers()) {
854 } else if (instr
->operands
[0].isConstant()) {
855 if (instr
->operands
[0].isLiteral())
856 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
857 else if (instr
->operands
[0].size() == 1)
858 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
859 } else if (instr
->operands
[0].isTemp()) {
860 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
862 assert(instr
->operands
[0].isFixed());
865 case aco_opcode::p_is_helper
:
866 if (!ctx
.program
->needs_wqm
)
867 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
869 case aco_opcode::s_movk_i32
: {
870 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
871 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
872 if (v
<= 64 || v
>= 0xfffffff0)
873 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
875 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
878 case aco_opcode::v_bfrev_b32
:
879 case aco_opcode::s_brev_b32
: {
880 if (instr
->operands
[0].isConstant()) {
881 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
882 if (v
<= 64 || v
>= 0xfffffff0)
883 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
885 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
889 case aco_opcode::s_bfm_b32
: {
890 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
891 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
892 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
893 uint32_t v
= ((1u << size
) - 1u) << start
;
894 if (v
<= 64 || v
>= 0xfffffff0)
895 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
897 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
900 case aco_opcode::v_mul_f32
: { /* omod */
901 /* TODO: try to move the negate/abs modifier to the consumer instead */
902 if (instr
->usesModifiers())
905 for (unsigned i
= 0; i
< 2; i
++) {
906 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
907 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
908 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
909 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
910 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
911 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
912 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
913 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
914 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
915 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
924 case aco_opcode::v_and_b32
: /* abs */
925 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
926 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
927 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
929 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
931 case aco_opcode::v_xor_b32
: { /* neg */
932 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
933 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
934 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
935 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
936 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
937 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
938 instr
->opcode
= aco_opcode::v_or_b32
;
939 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
941 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
945 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
949 case aco_opcode::v_med3_f32
: { /* clamp */
950 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
951 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
952 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
953 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
957 bool found_zero
= false, found_one
= false;
958 for (unsigned i
= 0; i
< 3; i
++)
960 if (instr
->operands
[i
].constantEquals(0))
962 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
967 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
968 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
972 case aco_opcode::v_cndmask_b32
:
973 if (instr
->operands
[0].constantEquals(0) &&
974 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
975 instr
->operands
[2].isTemp())
976 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
977 else if (instr
->operands
[0].constantEquals(0) &&
978 instr
->operands
[1].constantEquals(0x3f800000u
) &&
979 instr
->operands
[2].isTemp())
980 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
982 case aco_opcode::v_cmp_lg_u32
:
983 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
984 instr
->operands
[0].constantEquals(0) &&
985 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
986 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
988 case aco_opcode::p_phi
:
989 case aco_opcode::p_linear_phi
: {
990 /* lower_bool_phis() can create phis like this */
991 bool all_same_temp
= instr
->operands
[0].isTemp();
992 /* this check is needed when moving uniform loop counters out of a divergent loop */
994 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
995 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
996 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
997 all_same_temp
= false;
1000 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1002 bool all_undef
= instr
->operands
[0].isUndefined();
1003 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1004 if (!instr
->operands
[i
].isUndefined())
1008 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1012 case aco_opcode::v_add_u32
:
1013 case aco_opcode::v_add_co_u32
:
1014 case aco_opcode::s_add_i32
:
1015 case aco_opcode::s_add_u32
:
1016 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1018 case aco_opcode::s_and_b32
:
1019 case aco_opcode::s_and_b64
:
1020 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1021 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1022 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1025 case aco_opcode::s_not_b32
:
1026 case aco_opcode::s_not_b64
:
1027 case aco_opcode::s_or_b32
:
1028 case aco_opcode::s_or_b64
:
1029 case aco_opcode::s_xor_b32
:
1030 case aco_opcode::s_xor_b64
:
1031 case aco_opcode::s_lshl_b32
:
1032 case aco_opcode::v_or_b32
:
1033 case aco_opcode::v_lshlrev_b32
:
1034 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1036 case aco_opcode::v_min_f32
:
1037 case aco_opcode::v_min_f16
:
1038 case aco_opcode::v_min_u32
:
1039 case aco_opcode::v_min_i32
:
1040 case aco_opcode::v_min_u16
:
1041 case aco_opcode::v_min_i16
:
1042 case aco_opcode::v_max_f32
:
1043 case aco_opcode::v_max_f16
:
1044 case aco_opcode::v_max_u32
:
1045 case aco_opcode::v_max_i32
:
1046 case aco_opcode::v_max_u16
:
1047 case aco_opcode::v_max_i16
:
1048 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1050 case aco_opcode::v_cmp_lt_f32
:
1051 case aco_opcode::v_cmp_eq_f32
:
1052 case aco_opcode::v_cmp_le_f32
:
1053 case aco_opcode::v_cmp_gt_f32
:
1054 case aco_opcode::v_cmp_lg_f32
:
1055 case aco_opcode::v_cmp_ge_f32
:
1056 case aco_opcode::v_cmp_o_f32
:
1057 case aco_opcode::v_cmp_u_f32
:
1058 case aco_opcode::v_cmp_nge_f32
:
1059 case aco_opcode::v_cmp_nlg_f32
:
1060 case aco_opcode::v_cmp_ngt_f32
:
1061 case aco_opcode::v_cmp_nle_f32
:
1062 case aco_opcode::v_cmp_neq_f32
:
1063 case aco_opcode::v_cmp_nlt_f32
:
1064 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1066 case aco_opcode::s_cselect_b64
:
1067 case aco_opcode::s_cselect_b32
:
1068 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1069 instr
->operands
[1].constantEquals(0)) {
1070 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1071 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1079 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1081 *ordered
= *unordered
= op
;
1083 #define CMP(ord, unord) \
1084 case aco_opcode::v_cmp_##ord##_f32:\
1085 case aco_opcode::v_cmp_n##unord##_f32:\
1086 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1087 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1088 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1102 aco_opcode
get_ordered(aco_opcode op
)
1104 aco_opcode ordered
, unordered
, inverse
;
1105 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1108 aco_opcode
get_unordered(aco_opcode op
)
1110 aco_opcode ordered
, unordered
, inverse
;
1111 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1114 aco_opcode
get_inverse(aco_opcode op
)
1116 aco_opcode ordered
, unordered
, inverse
;
1117 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1120 bool is_cmp(aco_opcode op
)
1122 aco_opcode ordered
, unordered
, inverse
;
1123 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1126 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1128 if (ctx
.info
[tmp
.id()].is_temp())
1129 return ctx
.info
[tmp
.id()].temp
.id();
1134 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1136 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1137 for (const Operand
& op
: instr
->operands
) {
1139 ctx
.uses
[op
.tempId()]--;
1144 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1146 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1148 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1151 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1153 if (instr
->definitions
.size() == 2) {
1154 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1155 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1162 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1163 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1164 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1166 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1168 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1171 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1173 bool neg
[2] = {false, false};
1174 bool abs
[2] = {false, false};
1176 Instruction
*op_instr
[2];
1179 for (unsigned i
= 0; i
< 2; i
++) {
1180 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1184 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1186 if (op_instr
[i
]->opcode
!= expected_cmp
)
1188 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1191 if (op_instr
[i
]->isVOP3()) {
1192 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1193 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1195 neg
[i
] = vop3
->neg
[0];
1196 abs
[i
] = vop3
->abs
[0];
1197 opsel
|= (vop3
->opsel
& 1) << i
;
1200 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1201 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1202 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1208 if (op
[1].type() == RegType::sgpr
)
1209 std::swap(op
[0], op
[1]);
1210 //TODO: we can use two different SGPRs on GFX10
1211 if (op
[0].type() == RegType::sgpr
&& op
[1].type() == RegType::sgpr
)
1214 ctx
.uses
[op
[0].id()]++;
1215 ctx
.uses
[op
[1].id()]++;
1216 decrease_uses(ctx
, op_instr
[0]);
1217 decrease_uses(ctx
, op_instr
[1]);
1219 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1220 Instruction
*new_instr
;
1221 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
) {
1222 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1223 for (unsigned i
= 0; i
< 2; i
++) {
1224 vop3
->neg
[i
] = neg
[i
];
1225 vop3
->abs
[i
] = abs
[i
];
1227 vop3
->opsel
= opsel
;
1228 new_instr
= static_cast<Instruction
*>(vop3
);
1230 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1232 new_instr
->operands
[0] = Operand(op
[0]);
1233 new_instr
->operands
[1] = Operand(op
[1]);
1234 new_instr
->definitions
[0] = instr
->definitions
[0];
1236 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1237 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1239 instr
.reset(new_instr
);
1244 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1245 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1246 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1248 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1250 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1253 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1254 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1256 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1257 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1258 if (!nan_test
|| !cmp
)
1261 if (cmp
->opcode
== expected_nan_test
)
1262 std::swap(nan_test
, cmp
);
1263 else if (nan_test
->opcode
!= expected_nan_test
)
1266 if (!is_cmp(cmp
->opcode
))
1269 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1271 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1274 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1275 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1276 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1277 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1278 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1280 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1283 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1284 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1285 decrease_uses(ctx
, nan_test
);
1286 decrease_uses(ctx
, cmp
);
1288 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1289 Instruction
*new_instr
;
1290 if (cmp
->isVOP3()) {
1291 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1292 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1293 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1294 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1295 new_vop3
->clamp
= cmp_vop3
->clamp
;
1296 new_vop3
->omod
= cmp_vop3
->omod
;
1297 new_vop3
->opsel
= cmp_vop3
->opsel
;
1298 new_instr
= new_vop3
;
1300 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1302 new_instr
->operands
[0] = cmp
->operands
[0];
1303 new_instr
->operands
[1] = cmp
->operands
[1];
1304 new_instr
->definitions
[0] = instr
->definitions
[0];
1306 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1307 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1309 instr
.reset(new_instr
);
1314 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1315 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1316 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1318 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1320 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1323 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1325 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1326 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1328 if (!nan_test
|| !cmp
)
1331 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1332 if (cmp
->opcode
== expected_nan_test
)
1333 std::swap(nan_test
, cmp
);
1334 else if (nan_test
->opcode
!= expected_nan_test
)
1337 if (!is_cmp(cmp
->opcode
))
1340 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1342 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1345 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1346 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1347 if (prop_nan0
!= prop_nan1
)
1350 if (nan_test
->isVOP3()) {
1351 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1352 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1356 int constant_operand
= -1;
1357 for (unsigned i
= 0; i
< 2; i
++) {
1358 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1359 constant_operand
= !i
;
1363 if (constant_operand
== -1)
1367 if (cmp
->operands
[constant_operand
].isConstant()) {
1368 constant
= cmp
->operands
[constant_operand
].constantValue();
1369 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1370 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1371 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1373 constant
= ctx
.info
[id
].val
;
1379 memcpy(&constantf
, &constant
, 4);
1380 if (isnan(constantf
))
1383 if (cmp
->operands
[0].isTemp())
1384 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1385 if (cmp
->operands
[1].isTemp())
1386 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1387 decrease_uses(ctx
, nan_test
);
1388 decrease_uses(ctx
, cmp
);
1390 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1391 Instruction
*new_instr
;
1392 if (cmp
->isVOP3()) {
1393 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1394 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1395 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1396 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1397 new_vop3
->clamp
= cmp_vop3
->clamp
;
1398 new_vop3
->omod
= cmp_vop3
->omod
;
1399 new_vop3
->opsel
= cmp_vop3
->opsel
;
1400 new_instr
= new_vop3
;
1402 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1404 new_instr
->operands
[0] = cmp
->operands
[0];
1405 new_instr
->operands
[1] = cmp
->operands
[1];
1406 new_instr
->definitions
[0] = instr
->definitions
[0];
1408 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1409 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1411 instr
.reset(new_instr
);
1416 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1417 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1419 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1421 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1423 if (!instr
->operands
[0].isTemp())
1426 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1430 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1431 if (new_opcode
== aco_opcode::last_opcode
)
1434 if (cmp
->operands
[0].isTemp())
1435 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1436 if (cmp
->operands
[1].isTemp())
1437 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1438 decrease_uses(ctx
, cmp
);
1440 Instruction
*new_instr
;
1441 if (cmp
->isVOP3()) {
1442 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1443 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1444 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1445 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1446 new_vop3
->clamp
= cmp_vop3
->clamp
;
1447 new_vop3
->omod
= cmp_vop3
->omod
;
1448 new_vop3
->opsel
= cmp_vop3
->opsel
;
1449 new_instr
= new_vop3
;
1451 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1453 new_instr
->operands
[0] = cmp
->operands
[0];
1454 new_instr
->operands
[1] = cmp
->operands
[1];
1455 new_instr
->definitions
[0] = instr
->definitions
[0];
1457 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1458 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1460 instr
.reset(new_instr
);
1465 /* op1(op2(1, 2), 0) if swap = false
1466 * op1(0, op2(1, 2)) if swap = true */
1467 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1468 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1469 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1470 bool *op1_clamp
, uint8_t *op1_omod
,
1471 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1474 if (op1_instr
->opcode
!= op1
)
1477 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1478 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1481 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1482 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1484 /* don't support inbetween clamp/omod */
1485 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1488 /* get operands and modifiers and check inbetween modifiers */
1489 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1490 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1493 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1494 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1498 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1499 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1502 if (inbetween_opsel
)
1503 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1504 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1508 shuffle
[shuffle_str
[0] - '0'] = 0;
1509 shuffle
[shuffle_str
[1] - '0'] = 1;
1510 shuffle
[shuffle_str
[2] - '0'] = 2;
1512 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1513 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1514 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1515 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1516 *opsel
|= 1 << shuffle
[0];
1518 for (unsigned i
= 0; i
< 2; i
++) {
1519 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1520 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1521 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1522 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1523 *opsel
|= 1 << shuffle
[i
+ 1];
1526 /* check operands */
1527 unsigned sgpr_id
= 0;
1528 for (unsigned i
= 0; i
< 3; i
++) {
1529 Operand op
= operands
[i
];
1530 if (op
.isLiteral()) {
1532 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1533 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1535 sgpr_id
= op
.tempId();
1542 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1543 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1544 bool clamp
, unsigned omod
)
1546 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1547 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1548 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1549 new_instr
->clamp
= clamp
;
1550 new_instr
->omod
= omod
;
1551 new_instr
->opsel
= opsel
;
1552 new_instr
->operands
[0] = operands
[0];
1553 new_instr
->operands
[1] = operands
[1];
1554 new_instr
->operands
[2] = operands
[2];
1555 new_instr
->definitions
[0] = instr
->definitions
[0];
1556 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1558 instr
.reset(new_instr
);
1561 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1563 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1564 (label_omod_success
| label_clamp_success
);
1566 for (unsigned swap
= 0; swap
< 2; swap
++) {
1567 if (!((1 << swap
) & ops
))
1570 Operand operands
[3];
1571 bool neg
[3], abs
[3], clamp
;
1572 uint8_t opsel
= 0, omod
= 0;
1573 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1574 instr
.get(), swap
, shuffle
,
1575 operands
, neg
, abs
, &opsel
,
1576 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1577 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1578 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1579 if (omod_clamp
& label_omod_success
)
1580 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1581 if (omod_clamp
& label_clamp_success
)
1582 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1589 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1590 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1591 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1592 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1593 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1594 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1595 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1598 if (!instr
->operands
[0].isTemp())
1600 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1603 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1606 switch (op2_instr
->opcode
) {
1607 case aco_opcode::s_and_b32
:
1608 case aco_opcode::s_or_b32
:
1609 case aco_opcode::s_xor_b32
:
1610 case aco_opcode::s_and_b64
:
1611 case aco_opcode::s_or_b64
:
1612 case aco_opcode::s_xor_b64
:
1618 /* create instruction */
1619 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1620 ctx
.uses
[instr
->operands
[0].tempId()]--;
1621 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1623 switch (op2_instr
->opcode
) {
1624 case aco_opcode::s_and_b32
:
1625 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1627 case aco_opcode::s_or_b32
:
1628 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1630 case aco_opcode::s_xor_b32
:
1631 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1633 case aco_opcode::s_and_b64
:
1634 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1636 case aco_opcode::s_or_b64
:
1637 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1639 case aco_opcode::s_xor_b64
:
1640 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1649 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1650 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1651 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1652 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1653 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1655 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1658 for (unsigned i
= 0; i
< 2; i
++) {
1659 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1660 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1663 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1664 instr
->operands
[0] = instr
->operands
[!i
];
1665 instr
->operands
[1] = op2_instr
->operands
[0];
1666 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1668 switch (instr
->opcode
) {
1669 case aco_opcode::s_and_b32
:
1670 instr
->opcode
= aco_opcode::s_andn2_b32
;
1672 case aco_opcode::s_or_b32
:
1673 instr
->opcode
= aco_opcode::s_orn2_b32
;
1675 case aco_opcode::s_and_b64
:
1676 instr
->opcode
= aco_opcode::s_andn2_b64
;
1678 case aco_opcode::s_or_b64
:
1679 instr
->opcode
= aco_opcode::s_orn2_b64
;
1690 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1691 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1693 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1696 for (unsigned i
= 0; i
< 2; i
++) {
1697 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1698 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1701 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1702 if (shift
< 1 || shift
> 4)
1705 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1706 instr
->operands
[1] = instr
->operands
[!i
];
1707 instr
->operands
[0] = op2_instr
->operands
[0];
1708 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1710 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1711 aco_opcode::s_lshl2_add_u32
,
1712 aco_opcode::s_lshl3_add_u32
,
1713 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1720 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1723 #define MINMAX(type, gfx9) \
1724 case aco_opcode::v_min_##type:\
1725 case aco_opcode::v_max_##type:\
1726 case aco_opcode::v_med3_##type:\
1727 *min = aco_opcode::v_min_##type;\
1728 *max = aco_opcode::v_max_##type;\
1729 *med3 = aco_opcode::v_med3_##type;\
1730 *min3 = aco_opcode::v_min3_##type;\
1731 *max3 = aco_opcode::v_max3_##type;\
1732 *some_gfx9_only = gfx9;\
1746 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1747 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1748 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1749 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1751 aco_opcode other_op
;
1752 if (instr
->opcode
== min
)
1754 else if (instr
->opcode
== max
)
1759 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1760 (label_omod_success
| label_clamp_success
);
1762 for (unsigned swap
= 0; swap
< 2; swap
++) {
1763 Operand operands
[3];
1764 bool neg
[3], abs
[3], clamp
, inbetween_neg
, inbetween_abs
;
1765 uint8_t opsel
= 0, omod
= 0;
1766 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1767 "012", operands
, neg
, abs
, &opsel
,
1768 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1769 int const0_idx
= -1, const1_idx
= -1;
1770 uint32_t const0
= 0, const1
= 0;
1771 for (int i
= 0; i
< 3; i
++) {
1773 if (operands
[i
].isConstant()) {
1774 val
= operands
[i
].constantValue();
1775 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1776 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1777 val
= ctx
.info
[operands
[i
].tempId()].val
;
1781 if (const0_idx
>= 0) {
1789 if (const0_idx
< 0 || const1_idx
< 0)
1792 if (opsel
& (1 << const0_idx
))
1794 if (opsel
& (1 << const1_idx
))
1797 int lower_idx
= const0_idx
;
1799 case aco_opcode::v_min_f32
:
1800 case aco_opcode::v_min_f16
: {
1801 float const0_f
, const1_f
;
1802 if (min
== aco_opcode::v_min_f32
) {
1803 memcpy(&const0_f
, &const0
, 4);
1804 memcpy(&const1_f
, &const1
, 4);
1806 const0_f
= _mesa_half_to_float(const0
);
1807 const1_f
= _mesa_half_to_float(const1
);
1809 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1810 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1811 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1812 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1813 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1816 case aco_opcode::v_min_u32
: {
1817 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1820 case aco_opcode::v_min_u16
: {
1821 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1824 case aco_opcode::v_min_i32
: {
1825 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1826 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1827 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1830 case aco_opcode::v_min_i16
: {
1831 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1832 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1833 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1839 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1841 if (instr
->opcode
== min
) {
1842 if (upper_idx
!= 0 || lower_idx
== 0)
1845 if (upper_idx
== 0 || lower_idx
!= 0)
1849 neg
[1] ^= inbetween_neg
;
1850 neg
[2] ^= inbetween_neg
;
1851 abs
[1] |= inbetween_abs
;
1852 abs
[2] |= inbetween_abs
;
1854 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1855 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1856 if (omod_clamp
& label_omod_success
)
1857 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1858 if (omod_clamp
& label_clamp_success
)
1859 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1869 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1871 /* find candidates and create the set of sgprs already read */
1872 unsigned sgpr_ids
[2] = {0, 0};
1873 uint32_t operand_mask
= 0;
1874 bool has_literal
= false;
1875 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1876 if (instr
->operands
[i
].isLiteral())
1878 if (!instr
->operands
[i
].isTemp())
1880 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1881 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
1882 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
1884 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1885 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
1886 operand_mask
|= 1u << i
;
1888 unsigned max_sgprs
= 1;
1892 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
1894 /* keep on applying sgprs until there is nothing left to be done */
1895 while (operand_mask
) {
1896 uint32_t sgpr_idx
= 0;
1897 uint32_t sgpr_info_id
= 0;
1898 uint32_t mask
= operand_mask
;
1901 unsigned i
= u_bit_scan(&mask
);
1902 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1903 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1905 sgpr_info_id
= instr
->operands
[i
].tempId();
1908 operand_mask
&= ~(1u << sgpr_idx
);
1910 /* Applying two sgprs require making it VOP3, so don't do it unless it's
1911 * definitively beneficial.
1912 * TODO: this is too conservative because later the use count could be reduced to 1 */
1913 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1)
1916 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
1917 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
1918 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
1921 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1922 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
1923 } else if (can_swap_operands(instr
)) {
1924 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1925 instr
->operands
[0] = Operand(sgpr
);
1926 /* swap bits using a 4-entry LUT */
1927 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
1928 operand_mask
= (operand_mask
& ~0x3) | swapped
;
1929 } else if (can_use_VOP3(instr
)) {
1930 to_VOP3(ctx
, instr
);
1931 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
1936 sgpr_ids
[num_sgprs
++] = sgpr
.id();
1937 ctx
.uses
[sgpr_info_id
]--;
1938 ctx
.uses
[sgpr
.id()]++;
1940 break; /* for testing purposes, only apply 1 new sgpr */
1944 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1946 /* check if we could apply omod on predecessor */
1947 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1948 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
1949 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
1951 unsigned idx
= op0
? 0 : 1;
1952 /* omod was successfully applied */
1953 /* if the omod instruction is v_mad, we also have to change the original add */
1954 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1955 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1956 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1957 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1958 add_instr
->definitions
[0] = instr
->definitions
[0];
1961 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1962 /* check if we have an additional clamp modifier */
1963 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1964 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
1965 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1966 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1968 /* change definition ssa-id of modified instruction */
1969 omod_instr
->definitions
[0] = instr
->definitions
[0];
1971 /* change the definition of instr to something unused, e.g. the original omod def */
1972 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1973 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1976 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1977 /* in all other cases, label this instruction as option for multiply-add */
1978 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1982 /* check if we could apply clamp on predecessor */
1983 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1985 bool found_zero
= false, found_one
= false;
1986 for (unsigned i
= 0; i
< 3; i
++)
1988 if (instr
->operands
[i
].constantEquals(0))
1990 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1995 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1996 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1997 /* clamp was successfully applied */
1998 /* if the clamp instruction is v_mad, we also have to change the original add */
1999 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2000 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2001 add_instr
->definitions
[0] = instr
->definitions
[0];
2003 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2004 /* change definition ssa-id of modified instruction */
2005 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2007 /* change the definition of instr to something unused, e.g. the original omod def */
2008 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2009 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2014 /* omod has no effect if denormals are enabled */
2015 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2017 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2018 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2019 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2020 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2021 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2022 to_VOP3(ctx
, instr
);
2023 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2024 def_info
.set_omod_success(instr
.get());
2025 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2026 to_VOP3(ctx
, instr
);
2027 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2028 def_info
.set_omod_success(instr
.get());
2029 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2030 to_VOP3(ctx
, instr
);
2031 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2032 def_info
.set_omod_success(instr
.get());
2033 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2034 to_VOP3(ctx
, instr
);
2035 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2036 def_info
.set_clamp_success(instr
.get());
2043 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2044 // this would mean that we'd have to fix the instruction uses while value propagation
2046 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2048 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2051 if (instr
->isVALU()) {
2052 if (can_apply_sgprs(instr
))
2053 apply_sgprs(ctx
, instr
);
2054 if (apply_omod_clamp(ctx
, block
, instr
))
2058 /* TODO: There are still some peephole optimizations that could be done:
2059 * - abs(a - b) -> s_absdiff_i32
2060 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2061 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2062 * These aren't probably too interesting though.
2063 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2064 * probably more useful than the previously mentioned optimizations.
2065 * The various comparison optimizations also currently only work with 32-bit
2068 /* neg(mul(a, b)) -> mul(neg(a), b) */
2069 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2070 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2072 if (!ctx
.info
[val
.id()].is_mul())
2075 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2077 if (mul_instr
->operands
[0].isLiteral())
2079 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2082 /* convert to mul(neg(a), b) */
2083 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2084 Definition def
= instr
->definitions
[0];
2085 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2086 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2087 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2088 instr
->operands
[0] = mul_instr
->operands
[0];
2089 instr
->operands
[1] = mul_instr
->operands
[1];
2090 instr
->definitions
[0] = def
;
2091 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2092 if (mul_instr
->isVOP3()) {
2093 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2094 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2095 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2096 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2097 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2098 new_mul
->omod
= mul
->omod
;
2100 new_mul
->neg
[0] ^= true;
2101 new_mul
->clamp
= false;
2103 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2106 /* combine mul+add -> mad */
2107 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2108 instr
->opcode
== aco_opcode::v_sub_f32
||
2109 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2110 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2111 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2113 uint32_t uses_src0
= UINT32_MAX
;
2114 uint32_t uses_src1
= UINT32_MAX
;
2115 Instruction
* mul_instr
= nullptr;
2116 unsigned add_op_idx
;
2117 /* check if any of the operands is a multiplication */
2118 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2119 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2120 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2121 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2123 /* find the 'best' mul instruction to combine with the add */
2124 if (uses_src0
< uses_src1
) {
2125 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2127 } else if (uses_src1
< uses_src0
) {
2128 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2130 } else if (uses_src0
!= UINT32_MAX
) {
2131 /* tiebreaker: quite random what to pick */
2132 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2133 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2136 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2141 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2142 bool neg
[3] = {false, false, false};
2143 bool abs
[3] = {false, false, false};
2146 bool need_vop3
= false;
2148 unsigned cur_sgpr
= 0;
2149 op
[0] = mul_instr
->operands
[0];
2150 op
[1] = mul_instr
->operands
[1];
2151 op
[2] = instr
->operands
[add_op_idx
];
2152 for (unsigned i
= 0; i
< 3; i
++)
2154 if (op
[i
].isLiteral())
2156 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
&& op
[i
].tempId() != cur_sgpr
) {
2158 cur_sgpr
= op
[i
].tempId();
2160 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2163 // TODO: would be better to check this before selecting a mul instr?
2167 if (mul_instr
->isVOP3()) {
2168 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2169 neg
[0] = vop3
->neg
[0];
2170 neg
[1] = vop3
->neg
[1];
2171 abs
[0] = vop3
->abs
[0];
2172 abs
[1] = vop3
->abs
[1];
2174 /* we cannot use these modifiers between mul and add */
2175 if (vop3
->clamp
|| vop3
->omod
)
2179 /* convert to mad */
2180 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2181 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2183 ctx
.uses
[op
[0].tempId()]++;
2185 ctx
.uses
[op
[1].tempId()]++;
2188 if (instr
->isVOP3()) {
2189 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2190 neg
[2] = vop3
->neg
[add_op_idx
];
2191 abs
[2] = vop3
->abs
[add_op_idx
];
2193 clamp
= vop3
->clamp
;
2194 /* abs of the multiplication result */
2195 if (vop3
->abs
[1 - add_op_idx
]) {
2201 /* neg of the multiplication result */
2202 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2205 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2206 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2208 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2209 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2213 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2214 for (unsigned i
= 0; i
< 3; i
++)
2216 mad
->operands
[i
] = op
[i
];
2217 mad
->neg
[i
] = neg
[i
];
2218 mad
->abs
[i
] = abs
[i
];
2222 mad
->definitions
[0] = instr
->definitions
[0];
2224 /* mark this ssa_def to be re-checked for profitability and literals */
2225 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2226 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2227 instr
.reset(mad
.release());
2231 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2232 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2233 for (unsigned i
= 0; i
< 2; i
++) {
2234 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2235 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2236 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2237 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2238 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2240 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2241 new_instr
->operands
[0] = Operand(0u);
2242 new_instr
->operands
[1] = instr
->operands
[!i
];
2243 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2244 new_instr
->definitions
[0] = instr
->definitions
[0];
2245 instr
.reset(new_instr
.release());
2246 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2250 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2251 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2252 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2253 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2254 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2255 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2256 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2257 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2258 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2259 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2260 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2261 combine_salu_lshl_add(ctx
, instr
);
2262 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2263 combine_salu_not_bitwise(ctx
, instr
);
2264 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2265 if (combine_inverse_comparison(ctx
, instr
)) ;
2266 else combine_salu_not_bitwise(ctx
, instr
);
2267 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2268 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2269 if (combine_ordering_test(ctx
, instr
)) ;
2270 else if (combine_comparison_ordering(ctx
, instr
)) ;
2271 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2272 else combine_salu_n2(ctx
, instr
);
2274 aco_opcode min
, max
, min3
, max3
, med3
;
2275 bool some_gfx9_only
;
2276 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2277 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2278 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2279 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2285 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2287 const uint32_t threshold
= 4;
2289 if (is_dead(ctx
.uses
, instr
.get())) {
2294 /* convert split_vector into extract_vector if only one definition is ever used */
2295 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2296 unsigned num_used
= 0;
2298 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2299 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2304 if (num_used
== 1) {
2305 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2306 extract
->operands
[0] = instr
->operands
[0];
2307 extract
->operands
[1] = Operand((uint32_t) idx
);
2308 extract
->definitions
[0] = instr
->definitions
[idx
];
2309 instr
.reset(extract
.release());
2313 /* re-check mad instructions */
2314 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2315 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2316 /* first, check profitability */
2317 if (ctx
.uses
[info
->mul_temp_id
]) {
2318 ctx
.uses
[info
->mul_temp_id
]++;
2319 if (instr
->operands
[0].isTemp())
2320 ctx
.uses
[instr
->operands
[0].tempId()]--;
2321 if (instr
->operands
[1].isTemp())
2322 ctx
.uses
[instr
->operands
[1].tempId()]--;
2323 instr
.swap(info
->add_instr
);
2325 /* second, check possible literals */
2326 } else if (!info
->needs_vop3
) {
2327 uint32_t literal_idx
= 0;
2328 uint32_t literal_uses
= UINT32_MAX
;
2329 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2331 if (!instr
->operands
[i
].isTemp())
2333 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2334 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2335 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2336 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2339 literal_uses
= UINT32_MAX
;
2343 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2344 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2345 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2349 if (literal_uses
< threshold
) {
2350 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2351 info
->check_literal
= true;
2352 info
->literal_idx
= literal_idx
;
2358 /* check for literals */
2359 if (!instr
->isSALU() && !instr
->isVALU())
2362 if (instr
->isSDWA() || instr
->isDPP() || instr
->isVOP3())
2363 return; /* some encodings can't ever take literals */
2365 /* we do not apply the literals yet as we don't know if it is profitable */
2366 Operand
current_literal(s1
);
2368 unsigned literal_id
= 0;
2369 unsigned literal_uses
= UINT32_MAX
;
2370 Operand
literal(s1
);
2371 unsigned num_operands
= instr
->isSALU() ? instr
->operands
.size() : 1;
2373 unsigned sgpr_ids
[2] = {0, 0};
2374 bool is_literal_sgpr
= false;
2377 /* choose a literal to apply */
2378 for (unsigned i
= 0; i
< num_operands
; i
++) {
2379 Operand op
= instr
->operands
[i
];
2380 if (op
.isLiteral()) {
2381 current_literal
= op
;
2383 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2384 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2385 op
.tempId() != sgpr_ids
[0])
2386 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2390 if (!can_accept_constant(instr
, i
))
2393 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2394 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2396 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2397 literal_uses
= ctx
.uses
[op
.tempId()];
2398 literal_id
= op
.tempId();
2401 mask
|= (op
.tempId() == literal_id
) << i
;
2405 /* don't go over the constant bus limit */
2406 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2407 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2408 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2411 if (literal_id
&& literal_uses
< threshold
&&
2412 (current_literal
.isUndefined() ||
2413 (current_literal
.size() == literal
.size() &&
2414 current_literal
.constantValue() == literal
.constantValue()))) {
2415 /* mark the literal to be applied */
2417 unsigned i
= u_bit_scan(&mask
);
2418 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2419 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2425 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2427 /* Cleanup Dead Instructions */
2431 /* apply literals on MAD */
2432 bool literals_applied
= false;
2433 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2434 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2435 if (!info
->needs_vop3
) {
2436 aco_ptr
<Instruction
> new_mad
;
2437 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2438 if (info
->literal_idx
== 2) { /* add literal -> madak */
2439 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2440 new_mad
->operands
[0] = instr
->operands
[0];
2441 new_mad
->operands
[1] = instr
->operands
[1];
2442 } else { /* mul literal -> madmk */
2443 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2444 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2445 new_mad
->operands
[1] = instr
->operands
[2];
2447 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2448 new_mad
->definitions
[0] = instr
->definitions
[0];
2449 instr
.swap(new_mad
);
2451 literals_applied
= true;
2455 /* apply literals on SALU/VALU */
2456 if (!literals_applied
&& (instr
->isSALU() || instr
->isVALU())) {
2457 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2458 Operand op
= instr
->operands
[i
];
2459 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2460 Operand
literal(ctx
.info
[op
.tempId()].val
);
2461 if (instr
->isVALU() && i
> 0)
2462 to_VOP3(ctx
, instr
);
2463 instr
->operands
[i
] = literal
;
2468 ctx
.instructions
.emplace_back(std::move(instr
));
2472 void optimize(Program
* program
)
2475 ctx
.program
= program
;
2476 std::vector
<ssa_info
> info(program
->peekAllocationId());
2477 ctx
.info
= info
.data();
2479 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2480 for (Block
& block
: program
->blocks
) {
2481 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2482 label_instruction(ctx
, block
, instr
);
2485 ctx
.uses
= std::move(dead_code_analysis(program
));
2487 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2488 for (Block
& block
: program
->blocks
) {
2489 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2490 combine_instruction(ctx
, block
, instr
);
2493 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2494 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2495 Block
* block
= &(*it
);
2496 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2497 select_instruction(ctx
, *it
);
2500 /* 4. Add literals to instructions */
2501 for (Block
& block
: program
->blocks
) {
2502 ctx
.instructions
.clear();
2503 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2504 apply_literals(ctx
, instr
);
2505 block
.instructions
.swap(ctx
.instructions
);