2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
88 label_vcc_hint
= 1 << 25,
91 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
92 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
93 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
94 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
;
95 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
105 void add_label(Label new_label
)
107 /* Since all labels which use "instr" use it for the same thing
108 * (indicating the defining instruction), there is no need to clear
109 * any other instr labels. */
110 if (new_label
& instr_labels
)
111 label
&= ~temp_labels
; /* instr and temp alias */
113 if (new_label
& temp_labels
) {
114 label
&= ~temp_labels
;
115 label
&= ~instr_labels
; /* instr and temp alias */
118 if (new_label
& val_labels
)
119 label
&= ~val_labels
;
124 void set_vec(Instruction
* vec
)
126 add_label(label_vec
);
132 return label
& label_vec
;
135 void set_constant(uint32_t constant
)
137 add_label(label_constant
);
143 return label
& label_constant
;
146 void set_constant_64bit(uint32_t constant
)
148 add_label(label_constant_64bit
);
152 bool is_constant_64bit()
154 return label
& label_constant_64bit
;
157 void set_abs(Temp abs_temp
)
159 add_label(label_abs
);
165 return label
& label_abs
;
168 void set_neg(Temp neg_temp
)
170 add_label(label_neg
);
176 return label
& label_neg
;
179 void set_neg_abs(Temp neg_abs_temp
)
181 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
185 void set_mul(Instruction
* mul
)
187 add_label(label_mul
);
193 return label
& label_mul
;
196 void set_temp(Temp tmp
)
198 add_label(label_temp
);
204 return label
& label_temp
;
207 void set_literal(uint32_t lit
)
209 add_label(label_literal
);
215 return label
& label_literal
;
218 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
220 add_label(label_mad
);
227 return label
& label_mad
;
230 void set_omod2(Temp def
)
232 add_label(label_omod2
);
238 return label
& label_omod2
;
241 void set_omod4(Temp def
)
243 add_label(label_omod4
);
249 return label
& label_omod4
;
252 void set_omod5(Temp def
)
254 add_label(label_omod5
);
260 return label
& label_omod5
;
263 void set_omod_success(Instruction
* omod_instr
)
265 add_label(label_omod_success
);
269 bool is_omod_success()
271 return label
& label_omod_success
;
274 void set_clamp(Temp def
)
276 add_label(label_clamp
);
282 return label
& label_clamp
;
285 void set_clamp_success(Instruction
* clamp_instr
)
287 add_label(label_clamp_success
);
291 bool is_clamp_success()
293 return label
& label_clamp_success
;
298 add_label(label_undefined
);
303 return label
& label_undefined
;
306 void set_vcc(Temp vcc
)
308 add_label(label_vcc
);
314 return label
& label_vcc
;
317 bool is_constant_or_literal()
319 return is_constant() || is_literal();
322 void set_b2f(Temp val
)
324 add_label(label_b2f
);
330 return label
& label_b2f
;
333 void set_add_sub(Instruction
*add_sub_instr
)
335 add_label(label_add_sub
);
336 instr
= add_sub_instr
;
341 return label
& label_add_sub
;
344 void set_bitwise(Instruction
*bitwise_instr
)
346 add_label(label_bitwise
);
347 instr
= bitwise_instr
;
352 return label
& label_bitwise
;
355 void set_uniform_bitwise()
357 add_label(label_uniform_bitwise
);
360 bool is_uniform_bitwise()
362 return label
& label_uniform_bitwise
;
365 void set_minmax(Instruction
*minmax_instr
)
367 add_label(label_minmax
);
368 instr
= minmax_instr
;
373 return label
& label_minmax
;
376 void set_fcmp(Instruction
*fcmp_instr
)
378 add_label(label_fcmp
);
384 return label
& label_fcmp
;
387 void set_scc_invert(Temp scc_inv
)
389 add_label(label_scc_invert
);
395 return label
& label_scc_invert
;
398 void set_uniform_bool(Temp uniform_bool
)
400 add_label(label_uniform_bool
);
404 bool is_uniform_bool()
406 return label
& label_uniform_bool
;
411 add_label(label_vcc_hint
);
416 return label
& label_vcc_hint
;
422 std::vector
<aco_ptr
<Instruction
>> instructions
;
424 std::pair
<uint32_t,Temp
> last_literal
;
425 std::vector
<mad_info
> mad_infos
;
426 std::vector
<uint16_t> uses
;
429 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
431 if (instr
->operands
[0].isConstant() ||
432 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
435 switch (instr
->opcode
) {
436 case aco_opcode::v_add_f32
:
437 case aco_opcode::v_mul_f32
:
438 case aco_opcode::v_or_b32
:
439 case aco_opcode::v_and_b32
:
440 case aco_opcode::v_xor_b32
:
441 case aco_opcode::v_max_f32
:
442 case aco_opcode::v_min_f32
:
443 case aco_opcode::v_max_i32
:
444 case aco_opcode::v_min_i32
:
445 case aco_opcode::v_max_u32
:
446 case aco_opcode::v_min_u32
:
447 case aco_opcode::v_cmp_eq_f32
:
448 case aco_opcode::v_cmp_lg_f32
:
450 case aco_opcode::v_sub_f32
:
451 instr
->opcode
= aco_opcode::v_subrev_f32
;
453 case aco_opcode::v_cmp_lt_f32
:
454 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
456 case aco_opcode::v_cmp_ge_f32
:
457 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
459 case aco_opcode::v_cmp_lt_i32
:
460 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
467 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
472 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
475 if (instr
->isDPP() || instr
->isSDWA())
478 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
479 instr
->opcode
!= aco_opcode::v_madak_f32
&&
480 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
481 instr
->opcode
!= aco_opcode::v_madak_f16
&&
482 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
483 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
484 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
485 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
486 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
487 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
488 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
491 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
493 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
494 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
495 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
496 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
497 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
500 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
505 aco_ptr
<Instruction
> tmp
= std::move(instr
);
506 Format format
= asVOP3(tmp
->format
);
507 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
508 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
509 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
510 instr
->definitions
[i
] = tmp
->definitions
[i
];
511 if (instr
->definitions
[i
].isTemp()) {
512 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
513 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
514 info
.instr
= instr
.get();
519 /* only covers special cases */
520 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
522 switch (instr
->opcode
) {
523 case aco_opcode::v_interp_p2_f32
:
524 case aco_opcode::v_mac_f32
:
525 case aco_opcode::v_writelane_b32
:
526 case aco_opcode::v_writelane_b32_e64
:
527 case aco_opcode::v_cndmask_b32
:
529 case aco_opcode::s_addk_i32
:
530 case aco_opcode::s_mulk_i32
:
531 case aco_opcode::p_wqm
:
532 case aco_opcode::p_extract_vector
:
533 case aco_opcode::p_split_vector
:
534 case aco_opcode::v_readlane_b32
:
535 case aco_opcode::v_readlane_b32_e64
:
536 case aco_opcode::v_readfirstlane_b32
:
539 if ((instr
->format
== Format::MUBUF
||
540 instr
->format
== Format::MIMG
) &&
541 instr
->definitions
.size() == 1 &&
542 instr
->operands
.size() == 4) {
549 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
551 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
552 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
557 /* check constant bus and literal limitations */
558 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
560 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
561 Operand
literal32(s1
);
562 Operand
literal64(s2
);
563 unsigned num_sgprs
= 0;
564 unsigned sgpr
[] = {0, 0};
566 for (unsigned i
= 0; i
< num_operands
; i
++) {
567 Operand op
= operands
[i
];
569 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
570 /* two reads of the same SGPR count as 1 to the limit */
571 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
573 sgpr
[num_sgprs
++] = op
.tempId();
578 } else if (op
.isLiteral()) {
579 if (ctx
.program
->chip_class
< GFX10
)
582 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
584 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
587 /* Any number of 32-bit literals counts as only 1 to the limit. Same
588 * (but separately) for 64-bit literals. */
589 if (op
.size() == 1 && literal32
.isUndefined()) {
592 } else if (op
.size() == 2 && literal64
.isUndefined()) {
605 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
607 Operand op
= instr
->operands
[op_index
];
611 Temp tmp
= op
.getTemp();
612 if (!ctx
.info
[tmp
.id()].is_add_sub())
615 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
617 switch (add_instr
->opcode
) {
618 case aco_opcode::v_add_u32
:
619 case aco_opcode::v_add_co_u32
:
620 case aco_opcode::s_add_i32
:
621 case aco_opcode::s_add_u32
:
627 if (add_instr
->usesModifiers())
630 for (unsigned i
= 0; i
< 2; i
++) {
631 if (add_instr
->operands
[i
].isConstant()) {
632 *offset
= add_instr
->operands
[i
].constantValue();
633 } else if (add_instr
->operands
[i
].isTemp() &&
634 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
635 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
639 if (!add_instr
->operands
[!i
].isTemp())
642 uint32_t offset2
= 0;
643 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
646 *base
= add_instr
->operands
[!i
].getTemp();
654 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
656 // TODO: this functions shouldn't be needed if we store Operand instead of value.
657 Operand
op(val
, is64bit
);
658 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
659 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
663 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
665 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
666 ASSERTED
bool all_const
= false;
667 for (Operand
& op
: instr
->operands
)
668 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
669 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
672 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
674 if (!instr
->operands
[i
].isTemp())
677 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
678 /* propagate undef */
679 if (info
.is_undefined() && is_phi(instr
))
680 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
681 /* propagate reg->reg of same type */
682 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
683 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
684 info
= ctx
.info
[info
.temp
.id()];
687 /* SALU / PSEUDO: propagate inline constants */
688 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
689 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
690 instr
->operands
[i
].setTemp(info
.temp
);
691 info
= ctx
.info
[info
.temp
.id()];
692 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
693 /* propagate vgpr if it can take it */
694 switch (instr
->opcode
) {
695 case aco_opcode::p_create_vector
:
696 case aco_opcode::p_split_vector
:
697 case aco_opcode::p_extract_vector
:
698 case aco_opcode::p_phi
: {
699 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
700 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
702 instr
->operands
[i
] = Operand(info
.temp
);
703 info
= ctx
.info
[info
.temp
.id()];
711 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
712 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
717 /* VALU: propagate neg, abs & inline constants */
718 else if (instr
->isVALU()) {
719 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
720 instr
->operands
[i
].setTemp(info
.temp
);
721 info
= ctx
.info
[info
.temp
.id()];
723 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
726 instr
->operands
[i
] = Operand(info
.temp
);
728 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
730 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
732 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
733 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
734 instr
->operands
[i
].setTemp(info
.temp
);
736 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
739 instr
->operands
[i
].setTemp(info
.temp
);
741 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
743 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
746 if ((info
.is_constant() || info
.is_constant_64bit()) && can_accept_constant(instr
, i
)) {
747 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
748 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
749 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
750 instr
->operands
[i
] = op
;
752 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
753 instr
->operands
[i
] = instr
->operands
[0];
754 instr
->operands
[0] = op
;
756 } else if (can_use_VOP3(ctx
, instr
)) {
758 instr
->operands
[i
] = op
;
764 /* MUBUF: propagate constants and combine additions */
765 else if (instr
->format
== Format::MUBUF
) {
766 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
769 while (info
.is_temp())
770 info
= ctx
.info
[info
.temp
.id()];
772 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
773 assert(!mubuf
->idxen
);
774 instr
->operands
[i
] = Operand(v1
);
775 mubuf
->offset
+= info
.val
;
776 mubuf
->offen
= false;
778 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
779 instr
->operands
[2] = Operand((uint32_t) 0);
780 mubuf
->offset
+= info
.val
;
782 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
783 assert(!mubuf
->idxen
);
784 instr
->operands
[i
].setTemp(base
);
785 mubuf
->offset
+= offset
;
787 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
788 instr
->operands
[i
].setTemp(base
);
789 mubuf
->offset
+= offset
;
794 /* DS: combine additions */
795 else if (instr
->format
== Format::DS
) {
797 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
800 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
801 if (has_usable_ds_offset
&&
802 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
803 base
.regClass() == instr
->operands
[i
].regClass() &&
804 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
805 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
806 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
807 if (offset
% 4 == 0 &&
808 ds
->offset0
+ (offset
>> 2) <= 255 &&
809 ds
->offset1
+ (offset
>> 2) <= 255) {
810 instr
->operands
[i
].setTemp(base
);
811 ds
->offset0
+= offset
>> 2;
812 ds
->offset1
+= offset
>> 2;
815 if (ds
->offset0
+ offset
<= 65535) {
816 instr
->operands
[i
].setTemp(base
);
817 ds
->offset0
+= offset
;
823 /* SMEM: propagate constants and combine additions */
824 else if (instr
->format
== Format::SMEM
) {
826 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
829 if (i
== 1 && info
.is_constant_or_literal() &&
830 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
831 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
832 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
833 instr
->operands
[i
] = Operand(info
.val
);
835 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
836 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
838 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
839 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
843 smem
->operands
[1] = Operand(offset
);
844 smem
->operands
.back() = Operand(base
);
846 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
847 new_instr
->operands
[0] = smem
->operands
[0];
848 new_instr
->operands
[1] = Operand(offset
);
849 if (smem
->definitions
.empty())
850 new_instr
->operands
[2] = smem
->operands
[2];
851 new_instr
->operands
.back() = Operand(base
);
852 if (!smem
->definitions
.empty())
853 new_instr
->definitions
[0] = smem
->definitions
[0];
854 new_instr
->can_reorder
= smem
->can_reorder
;
855 new_instr
->barrier
= smem
->barrier
;
856 instr
.reset(new_instr
);
857 smem
= static_cast<SMEM_instruction
*>(instr
.get());
863 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
864 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
865 /* Flip the branch instruction to get rid of the scc_invert instruction */
866 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
867 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
872 /* if this instruction doesn't define anything, return */
873 if (instr
->definitions
.empty())
876 switch (instr
->opcode
) {
877 case aco_opcode::p_create_vector
: {
878 unsigned num_ops
= instr
->operands
.size();
879 for (const Operand
& op
: instr
->operands
) {
880 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
881 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
883 if (num_ops
!= instr
->operands
.size()) {
884 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
885 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
886 instr
->definitions
[0] = old_vec
->definitions
[0];
888 for (Operand
& old_op
: old_vec
->operands
) {
889 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
890 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
891 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
892 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
893 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
894 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
895 instr
->operands
[k
++] = op
;
898 instr
->operands
[k
++] = old_op
;
901 assert(k
== num_ops
);
903 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
904 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
905 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
906 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
909 case aco_opcode::p_split_vector
: {
910 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
912 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
913 assert(instr
->definitions
.size() == vec
->operands
.size());
914 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
915 Operand vec_op
= vec
->operands
[i
];
916 if (vec_op
.isConstant()) {
917 if (vec_op
.isLiteral())
918 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
919 else if (vec_op
.size() == 1)
920 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
921 else if (vec_op
.size() == 2)
922 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
924 assert(vec_op
.isTemp());
925 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
930 case aco_opcode::p_extract_vector
: { /* mov */
931 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
933 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
934 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
935 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
937 /* convert this extract into a mov instruction */
938 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
939 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
940 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
941 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
942 instr
->opcode
= opcode
;
943 instr
->format
= format
;
944 while (instr
->operands
.size() > 1)
945 instr
->operands
.pop_back();
946 instr
->operands
[0] = vec_op
;
948 if (vec_op
.isConstant()) {
949 if (vec_op
.isLiteral())
950 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
951 else if (vec_op
.size() == 1)
952 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
953 else if (vec_op
.size() == 2)
954 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(vec_op
.constantValue());
957 assert(vec_op
.isTemp());
958 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
963 case aco_opcode::s_mov_b32
: /* propagate */
964 case aco_opcode::s_mov_b64
:
965 case aco_opcode::v_mov_b32
:
966 case aco_opcode::p_as_uniform
:
967 if (instr
->definitions
[0].isFixed()) {
968 /* don't copy-propagate copies into fixed registers */
969 } else if (instr
->usesModifiers()) {
971 } else if (instr
->operands
[0].isConstant()) {
972 if (instr
->operands
[0].isLiteral())
973 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
974 else if (instr
->operands
[0].size() == 1)
975 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
976 else if (instr
->operands
[0].size() == 2)
977 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
978 } else if (instr
->operands
[0].isTemp()) {
979 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
981 assert(instr
->operands
[0].isFixed());
984 case aco_opcode::p_is_helper
:
985 if (!ctx
.program
->needs_wqm
)
986 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
988 case aco_opcode::s_movk_i32
: {
989 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
990 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
991 if (v
<= 64 || v
>= 0xfffffff0)
992 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
994 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
997 case aco_opcode::v_bfrev_b32
:
998 case aco_opcode::s_brev_b32
: {
999 if (instr
->operands
[0].isConstant()) {
1000 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1001 if (v
<= 64 || v
>= 0xfffffff0)
1002 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1004 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1008 case aco_opcode::s_bfm_b32
: {
1009 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1010 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1011 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1012 uint32_t v
= ((1u << size
) - 1u) << start
;
1013 if (v
<= 64 || v
>= 0xfffffff0)
1014 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1016 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1019 case aco_opcode::v_mul_f32
: { /* omod */
1020 /* TODO: try to move the negate/abs modifier to the consumer instead */
1021 if (instr
->usesModifiers())
1024 for (unsigned i
= 0; i
< 2; i
++) {
1025 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1026 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1027 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1028 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1029 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1030 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1031 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1032 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1033 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1034 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1043 case aco_opcode::v_and_b32
: /* abs */
1044 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1045 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1046 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1048 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1050 case aco_opcode::v_xor_b32
: { /* neg */
1051 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1052 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1053 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1054 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1055 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1056 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1057 instr
->opcode
= aco_opcode::v_or_b32
;
1058 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1060 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1064 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1068 case aco_opcode::v_med3_f32
: { /* clamp */
1069 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1070 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1071 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1072 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1076 bool found_zero
= false, found_one
= false;
1077 for (unsigned i
= 0; i
< 3; i
++)
1079 if (instr
->operands
[i
].constantEquals(0))
1081 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1086 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1087 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1091 case aco_opcode::v_cndmask_b32
:
1092 if (instr
->operands
[0].constantEquals(0) &&
1093 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1094 instr
->operands
[2].isTemp())
1095 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1096 else if (instr
->operands
[0].constantEquals(0) &&
1097 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1098 instr
->operands
[2].isTemp())
1099 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1101 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1103 case aco_opcode::v_cmp_lg_u32
:
1104 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1105 instr
->operands
[0].constantEquals(0) &&
1106 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1107 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1109 case aco_opcode::p_phi
:
1110 case aco_opcode::p_linear_phi
: {
1111 /* lower_bool_phis() can create phis like this */
1112 bool all_same_temp
= instr
->operands
[0].isTemp();
1113 /* this check is needed when moving uniform loop counters out of a divergent loop */
1115 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1116 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1117 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1118 all_same_temp
= false;
1120 if (all_same_temp
) {
1121 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1123 bool all_undef
= instr
->operands
[0].isUndefined();
1124 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1125 if (!instr
->operands
[i
].isUndefined())
1129 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1133 case aco_opcode::v_add_u32
:
1134 case aco_opcode::v_add_co_u32
:
1135 case aco_opcode::s_add_i32
:
1136 case aco_opcode::s_add_u32
:
1137 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1139 case aco_opcode::s_not_b32
:
1140 case aco_opcode::s_not_b64
:
1141 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1142 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1143 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1144 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1145 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1146 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1148 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1150 case aco_opcode::s_and_b32
:
1151 case aco_opcode::s_and_b64
:
1152 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&& instr
->operands
[0].isTemp()) {
1153 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1154 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1155 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1156 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1158 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1159 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1160 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1161 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1166 case aco_opcode::s_or_b32
:
1167 case aco_opcode::s_or_b64
:
1168 case aco_opcode::s_xor_b32
:
1169 case aco_opcode::s_xor_b64
:
1170 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1171 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1173 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1176 case aco_opcode::s_lshl_b32
:
1177 case aco_opcode::v_or_b32
:
1178 case aco_opcode::v_lshlrev_b32
:
1179 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1181 case aco_opcode::v_min_f32
:
1182 case aco_opcode::v_min_f16
:
1183 case aco_opcode::v_min_u32
:
1184 case aco_opcode::v_min_i32
:
1185 case aco_opcode::v_min_u16
:
1186 case aco_opcode::v_min_i16
:
1187 case aco_opcode::v_max_f32
:
1188 case aco_opcode::v_max_f16
:
1189 case aco_opcode::v_max_u32
:
1190 case aco_opcode::v_max_i32
:
1191 case aco_opcode::v_max_u16
:
1192 case aco_opcode::v_max_i16
:
1193 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1195 case aco_opcode::v_cmp_lt_f32
:
1196 case aco_opcode::v_cmp_eq_f32
:
1197 case aco_opcode::v_cmp_le_f32
:
1198 case aco_opcode::v_cmp_gt_f32
:
1199 case aco_opcode::v_cmp_lg_f32
:
1200 case aco_opcode::v_cmp_ge_f32
:
1201 case aco_opcode::v_cmp_o_f32
:
1202 case aco_opcode::v_cmp_u_f32
:
1203 case aco_opcode::v_cmp_nge_f32
:
1204 case aco_opcode::v_cmp_nlg_f32
:
1205 case aco_opcode::v_cmp_ngt_f32
:
1206 case aco_opcode::v_cmp_nle_f32
:
1207 case aco_opcode::v_cmp_neq_f32
:
1208 case aco_opcode::v_cmp_nlt_f32
:
1209 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1211 case aco_opcode::s_cselect_b64
:
1212 case aco_opcode::s_cselect_b32
:
1213 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1214 instr
->operands
[1].constantEquals(0)) {
1215 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1216 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1218 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1219 /* Flip the operands to get rid of the scc_invert instruction */
1220 std::swap(instr
->operands
[0], instr
->operands
[1]);
1221 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1224 case aco_opcode::p_wqm
:
1225 if (instr
->operands
[0].isTemp() &&
1226 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1227 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1235 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1237 *ordered
= *unordered
= op
;
1239 #define CMP(ord, unord) \
1240 case aco_opcode::v_cmp_##ord##_f32:\
1241 case aco_opcode::v_cmp_n##unord##_f32:\
1242 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1243 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1244 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1258 aco_opcode
get_ordered(aco_opcode op
)
1260 aco_opcode ordered
, unordered
, inverse
;
1261 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1264 aco_opcode
get_unordered(aco_opcode op
)
1266 aco_opcode ordered
, unordered
, inverse
;
1267 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1270 aco_opcode
get_inverse(aco_opcode op
)
1272 aco_opcode ordered
, unordered
, inverse
;
1273 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1276 bool is_cmp(aco_opcode op
)
1278 aco_opcode ordered
, unordered
, inverse
;
1279 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1282 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1284 if (ctx
.info
[tmp
.id()].is_temp())
1285 return ctx
.info
[tmp
.id()].temp
.id();
1290 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1292 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1293 for (const Operand
& op
: instr
->operands
) {
1295 ctx
.uses
[op
.tempId()]--;
1300 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1302 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1304 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1307 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1309 if (instr
->definitions
.size() == 2) {
1310 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1311 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1318 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1319 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1320 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1322 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1324 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1327 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1329 bool neg
[2] = {false, false};
1330 bool abs
[2] = {false, false};
1332 Instruction
*op_instr
[2];
1335 for (unsigned i
= 0; i
< 2; i
++) {
1336 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1340 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1342 if (op_instr
[i
]->opcode
!= expected_cmp
)
1344 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1347 if (op_instr
[i
]->isVOP3()) {
1348 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1349 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1351 neg
[i
] = vop3
->neg
[0];
1352 abs
[i
] = vop3
->abs
[0];
1353 opsel
|= (vop3
->opsel
& 1) << i
;
1356 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1357 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1358 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1364 if (op
[1].type() == RegType::sgpr
)
1365 std::swap(op
[0], op
[1]);
1366 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1367 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1370 ctx
.uses
[op
[0].id()]++;
1371 ctx
.uses
[op
[1].id()]++;
1372 decrease_uses(ctx
, op_instr
[0]);
1373 decrease_uses(ctx
, op_instr
[1]);
1375 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1376 Instruction
*new_instr
;
1377 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1378 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1379 for (unsigned i
= 0; i
< 2; i
++) {
1380 vop3
->neg
[i
] = neg
[i
];
1381 vop3
->abs
[i
] = abs
[i
];
1383 vop3
->opsel
= opsel
;
1384 new_instr
= static_cast<Instruction
*>(vop3
);
1386 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1388 new_instr
->operands
[0] = Operand(op
[0]);
1389 new_instr
->operands
[1] = Operand(op
[1]);
1390 new_instr
->definitions
[0] = instr
->definitions
[0];
1392 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1393 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1395 instr
.reset(new_instr
);
1400 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1401 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1402 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1404 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1406 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1409 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1410 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1412 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1413 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1414 if (!nan_test
|| !cmp
)
1417 if (cmp
->opcode
== expected_nan_test
)
1418 std::swap(nan_test
, cmp
);
1419 else if (nan_test
->opcode
!= expected_nan_test
)
1422 if (!is_cmp(cmp
->opcode
))
1425 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1427 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1430 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1431 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1432 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1433 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1434 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1436 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1439 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1440 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1441 decrease_uses(ctx
, nan_test
);
1442 decrease_uses(ctx
, cmp
);
1444 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1445 Instruction
*new_instr
;
1446 if (cmp
->isVOP3()) {
1447 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1448 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1449 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1450 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1451 new_vop3
->clamp
= cmp_vop3
->clamp
;
1452 new_vop3
->omod
= cmp_vop3
->omod
;
1453 new_vop3
->opsel
= cmp_vop3
->opsel
;
1454 new_instr
= new_vop3
;
1456 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1458 new_instr
->operands
[0] = cmp
->operands
[0];
1459 new_instr
->operands
[1] = cmp
->operands
[1];
1460 new_instr
->definitions
[0] = instr
->definitions
[0];
1462 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1463 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1465 instr
.reset(new_instr
);
1470 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1471 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1472 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1474 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1476 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1479 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1481 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1482 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1484 if (!nan_test
|| !cmp
)
1487 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1488 if (cmp
->opcode
== expected_nan_test
)
1489 std::swap(nan_test
, cmp
);
1490 else if (nan_test
->opcode
!= expected_nan_test
)
1493 if (!is_cmp(cmp
->opcode
))
1496 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1498 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1501 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1502 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1503 if (prop_nan0
!= prop_nan1
)
1506 if (nan_test
->isVOP3()) {
1507 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1508 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1512 int constant_operand
= -1;
1513 for (unsigned i
= 0; i
< 2; i
++) {
1514 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1515 constant_operand
= !i
;
1519 if (constant_operand
== -1)
1523 if (cmp
->operands
[constant_operand
].isConstant()) {
1524 constant
= cmp
->operands
[constant_operand
].constantValue();
1525 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1526 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1527 unsigned id
= original_temp_id(ctx
, tmp
);
1528 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1530 constant
= ctx
.info
[id
].val
;
1536 memcpy(&constantf
, &constant
, 4);
1537 if (isnan(constantf
))
1540 if (cmp
->operands
[0].isTemp())
1541 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1542 if (cmp
->operands
[1].isTemp())
1543 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1544 decrease_uses(ctx
, nan_test
);
1545 decrease_uses(ctx
, cmp
);
1547 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1548 Instruction
*new_instr
;
1549 if (cmp
->isVOP3()) {
1550 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1551 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1552 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1553 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1554 new_vop3
->clamp
= cmp_vop3
->clamp
;
1555 new_vop3
->omod
= cmp_vop3
->omod
;
1556 new_vop3
->opsel
= cmp_vop3
->opsel
;
1557 new_instr
= new_vop3
;
1559 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1561 new_instr
->operands
[0] = cmp
->operands
[0];
1562 new_instr
->operands
[1] = cmp
->operands
[1];
1563 new_instr
->definitions
[0] = instr
->definitions
[0];
1565 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1566 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1568 instr
.reset(new_instr
);
1573 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1574 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1576 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1578 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1580 if (!instr
->operands
[0].isTemp())
1583 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1587 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1588 if (new_opcode
== aco_opcode::last_opcode
)
1591 if (cmp
->operands
[0].isTemp())
1592 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1593 if (cmp
->operands
[1].isTemp())
1594 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1595 decrease_uses(ctx
, cmp
);
1597 Instruction
*new_instr
;
1598 if (cmp
->isVOP3()) {
1599 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1600 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1601 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1602 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1603 new_vop3
->clamp
= cmp_vop3
->clamp
;
1604 new_vop3
->omod
= cmp_vop3
->omod
;
1605 new_vop3
->opsel
= cmp_vop3
->opsel
;
1606 new_instr
= new_vop3
;
1608 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1610 new_instr
->operands
[0] = cmp
->operands
[0];
1611 new_instr
->operands
[1] = cmp
->operands
[1];
1612 new_instr
->definitions
[0] = instr
->definitions
[0];
1614 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1615 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1617 instr
.reset(new_instr
);
1622 /* op1(op2(1, 2), 0) if swap = false
1623 * op1(0, op2(1, 2)) if swap = true */
1624 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1625 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1626 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1627 bool *op1_clamp
, uint8_t *op1_omod
,
1628 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1631 if (op1_instr
->opcode
!= op1
)
1634 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1635 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1638 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1639 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1641 /* don't support inbetween clamp/omod */
1642 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1645 /* get operands and modifiers and check inbetween modifiers */
1646 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1647 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1650 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1651 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1655 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1656 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1659 if (inbetween_opsel
)
1660 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1661 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1665 shuffle
[shuffle_str
[0] - '0'] = 0;
1666 shuffle
[shuffle_str
[1] - '0'] = 1;
1667 shuffle
[shuffle_str
[2] - '0'] = 2;
1669 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1670 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1671 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1672 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1673 *opsel
|= 1 << shuffle
[0];
1675 for (unsigned i
= 0; i
< 2; i
++) {
1676 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1677 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1678 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1679 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1680 *opsel
|= 1 << shuffle
[i
+ 1];
1683 /* check operands */
1684 if (!check_vop3_operands(ctx
, 3, operands
))
1690 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1691 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1692 bool clamp
, unsigned omod
)
1694 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1695 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1696 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1697 new_instr
->clamp
= clamp
;
1698 new_instr
->omod
= omod
;
1699 new_instr
->opsel
= opsel
;
1700 new_instr
->operands
[0] = operands
[0];
1701 new_instr
->operands
[1] = operands
[1];
1702 new_instr
->operands
[2] = operands
[2];
1703 new_instr
->definitions
[0] = instr
->definitions
[0];
1704 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1706 instr
.reset(new_instr
);
1709 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1711 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1712 (label_omod_success
| label_clamp_success
);
1714 for (unsigned swap
= 0; swap
< 2; swap
++) {
1715 if (!((1 << swap
) & ops
))
1718 Operand operands
[3];
1719 bool neg
[3], abs
[3], clamp
;
1720 uint8_t opsel
= 0, omod
= 0;
1721 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1722 instr
.get(), swap
, shuffle
,
1723 operands
, neg
, abs
, &opsel
,
1724 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1725 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1726 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1727 if (omod_clamp
& label_omod_success
)
1728 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1729 if (omod_clamp
& label_clamp_success
)
1730 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1737 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1739 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1742 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1743 (label_omod_success
| label_clamp_success
);
1745 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1746 * max(-min(a, b), c) -> max3(-a, -b, c) */
1747 for (unsigned swap
= 0; swap
< 2; swap
++) {
1748 Operand operands
[3];
1749 bool neg
[3], abs
[3], clamp
;
1750 uint8_t opsel
= 0, omod
= 0;
1752 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1753 instr
.get(), swap
, "012",
1754 operands
, neg
, abs
, &opsel
,
1755 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1757 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1760 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1761 if (omod_clamp
& label_omod_success
)
1762 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1763 if (omod_clamp
& label_clamp_success
)
1764 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1771 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1772 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1773 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1774 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1775 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1776 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1777 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1780 if (!instr
->operands
[0].isTemp())
1782 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1785 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1788 switch (op2_instr
->opcode
) {
1789 case aco_opcode::s_and_b32
:
1790 case aco_opcode::s_or_b32
:
1791 case aco_opcode::s_xor_b32
:
1792 case aco_opcode::s_and_b64
:
1793 case aco_opcode::s_or_b64
:
1794 case aco_opcode::s_xor_b64
:
1800 /* create instruction */
1801 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1802 ctx
.uses
[instr
->operands
[0].tempId()]--;
1803 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1805 switch (op2_instr
->opcode
) {
1806 case aco_opcode::s_and_b32
:
1807 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1809 case aco_opcode::s_or_b32
:
1810 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1812 case aco_opcode::s_xor_b32
:
1813 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1815 case aco_opcode::s_and_b64
:
1816 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1818 case aco_opcode::s_or_b64
:
1819 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1821 case aco_opcode::s_xor_b64
:
1822 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1831 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1832 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1833 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1834 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1835 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1837 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1840 for (unsigned i
= 0; i
< 2; i
++) {
1841 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1842 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1845 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1846 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1849 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1850 instr
->operands
[0] = instr
->operands
[!i
];
1851 instr
->operands
[1] = op2_instr
->operands
[0];
1852 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1854 switch (instr
->opcode
) {
1855 case aco_opcode::s_and_b32
:
1856 instr
->opcode
= aco_opcode::s_andn2_b32
;
1858 case aco_opcode::s_or_b32
:
1859 instr
->opcode
= aco_opcode::s_orn2_b32
;
1861 case aco_opcode::s_and_b64
:
1862 instr
->opcode
= aco_opcode::s_andn2_b64
;
1864 case aco_opcode::s_or_b64
:
1865 instr
->opcode
= aco_opcode::s_orn2_b64
;
1876 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1877 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1879 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1882 for (unsigned i
= 0; i
< 2; i
++) {
1883 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1884 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1887 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1888 if (shift
< 1 || shift
> 4)
1891 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1892 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1895 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1896 instr
->operands
[1] = instr
->operands
[!i
];
1897 instr
->operands
[0] = op2_instr
->operands
[0];
1898 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1900 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1901 aco_opcode::s_lshl2_add_u32
,
1902 aco_opcode::s_lshl3_add_u32
,
1903 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1910 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1913 #define MINMAX(type, gfx9) \
1914 case aco_opcode::v_min_##type:\
1915 case aco_opcode::v_max_##type:\
1916 case aco_opcode::v_med3_##type:\
1917 *min = aco_opcode::v_min_##type;\
1918 *max = aco_opcode::v_max_##type;\
1919 *med3 = aco_opcode::v_med3_##type;\
1920 *min3 = aco_opcode::v_min3_##type;\
1921 *max3 = aco_opcode::v_max3_##type;\
1922 *some_gfx9_only = gfx9;\
1936 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1937 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1938 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1939 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1941 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1942 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1943 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1944 aco_opcode other_op
;
1945 if (instr
->opcode
== min
)
1947 else if (instr
->opcode
== max
)
1952 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1953 (label_omod_success
| label_clamp_success
);
1955 for (unsigned swap
= 0; swap
< 2; swap
++) {
1956 Operand operands
[3];
1957 bool neg
[3], abs
[3], clamp
;
1958 uint8_t opsel
= 0, omod
= 0;
1959 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1960 "012", operands
, neg
, abs
, &opsel
,
1961 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1962 int const0_idx
= -1, const1_idx
= -1;
1963 uint32_t const0
= 0, const1
= 0;
1964 for (int i
= 0; i
< 3; i
++) {
1966 if (operands
[i
].isConstant()) {
1967 val
= operands
[i
].constantValue();
1968 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1969 val
= ctx
.info
[operands
[i
].tempId()].val
;
1973 if (const0_idx
>= 0) {
1981 if (const0_idx
< 0 || const1_idx
< 0)
1984 if (opsel
& (1 << const0_idx
))
1986 if (opsel
& (1 << const1_idx
))
1989 int lower_idx
= const0_idx
;
1991 case aco_opcode::v_min_f32
:
1992 case aco_opcode::v_min_f16
: {
1993 float const0_f
, const1_f
;
1994 if (min
== aco_opcode::v_min_f32
) {
1995 memcpy(&const0_f
, &const0
, 4);
1996 memcpy(&const1_f
, &const1
, 4);
1998 const0_f
= _mesa_half_to_float(const0
);
1999 const1_f
= _mesa_half_to_float(const1
);
2001 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2002 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2003 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2004 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2005 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2008 case aco_opcode::v_min_u32
: {
2009 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2012 case aco_opcode::v_min_u16
: {
2013 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2016 case aco_opcode::v_min_i32
: {
2017 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2018 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2019 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2022 case aco_opcode::v_min_i16
: {
2023 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2024 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2025 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2031 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2033 if (instr
->opcode
== min
) {
2034 if (upper_idx
!= 0 || lower_idx
== 0)
2037 if (upper_idx
== 0 || lower_idx
!= 0)
2041 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2042 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2043 if (omod_clamp
& label_omod_success
)
2044 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2045 if (omod_clamp
& label_clamp_success
)
2046 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2056 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2058 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2059 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2060 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2062 /* find candidates and create the set of sgprs already read */
2063 unsigned sgpr_ids
[2] = {0, 0};
2064 uint32_t operand_mask
= 0;
2065 bool has_literal
= false;
2066 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2067 if (instr
->operands
[i
].isLiteral())
2069 if (!instr
->operands
[i
].isTemp())
2071 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2072 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2073 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2075 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2076 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2077 operand_mask
|= 1u << i
;
2079 unsigned max_sgprs
= 1;
2080 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2085 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2087 /* keep on applying sgprs until there is nothing left to be done */
2088 while (operand_mask
) {
2089 uint32_t sgpr_idx
= 0;
2090 uint32_t sgpr_info_id
= 0;
2091 uint32_t mask
= operand_mask
;
2094 unsigned i
= u_bit_scan(&mask
);
2095 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2096 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2098 sgpr_info_id
= instr
->operands
[i
].tempId();
2101 operand_mask
&= ~(1u << sgpr_idx
);
2103 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2104 * definitively beneficial.
2105 * TODO: this is too conservative because later the use count could be reduced to 1 */
2106 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2109 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2110 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2111 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2114 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2115 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2116 } else if (can_swap_operands(instr
)) {
2117 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2118 instr
->operands
[0] = Operand(sgpr
);
2119 /* swap bits using a 4-entry LUT */
2120 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2121 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2122 } else if (can_use_VOP3(ctx
, instr
)) {
2123 to_VOP3(ctx
, instr
);
2124 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2130 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2131 ctx
.uses
[sgpr_info_id
]--;
2132 ctx
.uses
[sgpr
.id()]++;
2136 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2138 /* check if we could apply omod on predecessor */
2139 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2140 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2141 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2143 unsigned idx
= op0
? 0 : 1;
2144 /* omod was successfully applied */
2145 /* if the omod instruction is v_mad, we also have to change the original add */
2146 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2147 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2148 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2149 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2150 add_instr
->definitions
[0] = instr
->definitions
[0];
2153 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2154 /* check if we have an additional clamp modifier */
2155 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2156 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2157 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2158 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2160 /* change definition ssa-id of modified instruction */
2161 omod_instr
->definitions
[0] = instr
->definitions
[0];
2163 /* change the definition of instr to something unused, e.g. the original omod def */
2164 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2165 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2168 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2169 /* in all other cases, label this instruction as option for multiply-add */
2170 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2174 /* check if we could apply clamp on predecessor */
2175 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2177 bool found_zero
= false, found_one
= false;
2178 for (unsigned i
= 0; i
< 3; i
++)
2180 if (instr
->operands
[i
].constantEquals(0))
2182 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2187 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2188 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2189 /* clamp was successfully applied */
2190 /* if the clamp instruction is v_mad, we also have to change the original add */
2191 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2192 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2193 add_instr
->definitions
[0] = instr
->definitions
[0];
2195 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2196 /* change definition ssa-id of modified instruction */
2197 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2199 /* change the definition of instr to something unused, e.g. the original omod def */
2200 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2201 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2206 /* omod has no effect if denormals are enabled */
2207 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2209 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2210 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2211 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2212 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2213 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2214 to_VOP3(ctx
, instr
);
2215 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2216 def_info
.set_omod_success(instr
.get());
2217 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2218 to_VOP3(ctx
, instr
);
2219 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2220 def_info
.set_omod_success(instr
.get());
2221 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2222 to_VOP3(ctx
, instr
);
2223 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2224 def_info
.set_omod_success(instr
.get());
2225 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2226 to_VOP3(ctx
, instr
);
2227 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2228 def_info
.set_clamp_success(instr
.get());
2235 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2236 // this would mean that we'd have to fix the instruction uses while value propagation
2238 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2240 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2243 if (instr
->isVALU()) {
2244 if (can_apply_sgprs(instr
))
2245 apply_sgprs(ctx
, instr
);
2246 if (apply_omod_clamp(ctx
, block
, instr
))
2250 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2251 instr
->definitions
[0].setHint(vcc
);
2254 /* TODO: There are still some peephole optimizations that could be done:
2255 * - abs(a - b) -> s_absdiff_i32
2256 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2257 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2258 * These aren't probably too interesting though.
2259 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2260 * probably more useful than the previously mentioned optimizations.
2261 * The various comparison optimizations also currently only work with 32-bit
2264 /* neg(mul(a, b)) -> mul(neg(a), b) */
2265 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2266 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2268 if (!ctx
.info
[val
.id()].is_mul())
2271 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2273 if (mul_instr
->operands
[0].isLiteral())
2275 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2278 /* convert to mul(neg(a), b) */
2279 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2280 Definition def
= instr
->definitions
[0];
2281 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2282 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2283 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2284 instr
->operands
[0] = mul_instr
->operands
[0];
2285 instr
->operands
[1] = mul_instr
->operands
[1];
2286 instr
->definitions
[0] = def
;
2287 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2288 if (mul_instr
->isVOP3()) {
2289 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2290 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2291 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2292 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2293 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2294 new_mul
->omod
= mul
->omod
;
2296 new_mul
->neg
[0] ^= true;
2297 new_mul
->clamp
= false;
2299 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2302 /* combine mul+add -> mad */
2303 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2304 instr
->opcode
== aco_opcode::v_sub_f32
||
2305 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2306 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2307 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2309 uint32_t uses_src0
= UINT32_MAX
;
2310 uint32_t uses_src1
= UINT32_MAX
;
2311 Instruction
* mul_instr
= nullptr;
2312 unsigned add_op_idx
;
2313 /* check if any of the operands is a multiplication */
2314 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2315 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2316 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2317 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2319 /* find the 'best' mul instruction to combine with the add */
2320 if (uses_src0
< uses_src1
) {
2321 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2323 } else if (uses_src1
< uses_src0
) {
2324 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2326 } else if (uses_src0
!= UINT32_MAX
) {
2327 /* tiebreaker: quite random what to pick */
2328 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2329 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2332 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2337 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2338 bool neg
[3] = {false, false, false};
2339 bool abs
[3] = {false, false, false};
2342 op
[0] = mul_instr
->operands
[0];
2343 op
[1] = mul_instr
->operands
[1];
2344 op
[2] = instr
->operands
[add_op_idx
];
2345 // TODO: would be better to check this before selecting a mul instr?
2346 if (!check_vop3_operands(ctx
, 3, op
))
2349 if (mul_instr
->isVOP3()) {
2350 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2351 neg
[0] = vop3
->neg
[0];
2352 neg
[1] = vop3
->neg
[1];
2353 abs
[0] = vop3
->abs
[0];
2354 abs
[1] = vop3
->abs
[1];
2355 /* we cannot use these modifiers between mul and add */
2356 if (vop3
->clamp
|| vop3
->omod
)
2360 /* convert to mad */
2361 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2362 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2364 ctx
.uses
[op
[0].tempId()]++;
2366 ctx
.uses
[op
[1].tempId()]++;
2369 if (instr
->isVOP3()) {
2370 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2371 neg
[2] = vop3
->neg
[add_op_idx
];
2372 abs
[2] = vop3
->abs
[add_op_idx
];
2374 clamp
= vop3
->clamp
;
2375 /* abs of the multiplication result */
2376 if (vop3
->abs
[1 - add_op_idx
]) {
2382 /* neg of the multiplication result */
2383 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2385 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2386 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2387 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2388 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2390 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2391 for (unsigned i
= 0; i
< 3; i
++)
2393 mad
->operands
[i
] = op
[i
];
2394 mad
->neg
[i
] = neg
[i
];
2395 mad
->abs
[i
] = abs
[i
];
2399 mad
->definitions
[0] = instr
->definitions
[0];
2401 /* mark this ssa_def to be re-checked for profitability and literals */
2402 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2403 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2404 instr
.reset(mad
.release());
2408 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2409 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2410 for (unsigned i
= 0; i
< 2; i
++) {
2411 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2412 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2413 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2414 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2415 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2417 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2418 new_instr
->operands
[0] = Operand(0u);
2419 new_instr
->operands
[1] = instr
->operands
[!i
];
2420 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2421 new_instr
->definitions
[0] = instr
->definitions
[0];
2422 instr
.reset(new_instr
.release());
2423 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2427 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2428 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2429 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2430 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2431 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2432 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2433 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2434 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2435 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2436 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2437 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2438 combine_salu_lshl_add(ctx
, instr
);
2439 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2440 combine_salu_not_bitwise(ctx
, instr
);
2441 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2442 if (combine_inverse_comparison(ctx
, instr
)) ;
2443 else combine_salu_not_bitwise(ctx
, instr
);
2444 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2445 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2446 if (combine_ordering_test(ctx
, instr
)) ;
2447 else if (combine_comparison_ordering(ctx
, instr
)) ;
2448 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2449 else combine_salu_n2(ctx
, instr
);
2451 aco_opcode min
, max
, min3
, max3
, med3
;
2452 bool some_gfx9_only
;
2453 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2454 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2455 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2456 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2462 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2464 const uint32_t threshold
= 4;
2466 if (is_dead(ctx
.uses
, instr
.get())) {
2471 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2472 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2473 unsigned num_used
= 0;
2475 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2476 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2482 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2483 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2484 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2488 for (Operand
& vec_op
: vec
->operands
) {
2489 if (off
== idx
* instr
->definitions
[0].size()) {
2493 off
+= vec_op
.size();
2495 if (off
!= instr
->operands
[0].size()) {
2496 ctx
.uses
[instr
->operands
[0].tempId()]--;
2497 for (Operand
& vec_op
: vec
->operands
) {
2498 if (vec_op
.isTemp())
2499 ctx
.uses
[vec_op
.tempId()]--;
2502 ctx
.uses
[op
.tempId()]++;
2504 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2505 extract
->operands
[0] = op
;
2506 extract
->definitions
[0] = instr
->definitions
[idx
];
2507 instr
.reset(extract
.release());
2513 if (!done
&& num_used
== 1) {
2514 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2515 extract
->operands
[0] = instr
->operands
[0];
2516 extract
->operands
[1] = Operand((uint32_t) idx
);
2517 extract
->definitions
[0] = instr
->definitions
[idx
];
2518 instr
.reset(extract
.release());
2522 mad_info
* mad_info
= NULL
;
2523 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2524 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2525 /* re-check mad instructions */
2526 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2527 ctx
.uses
[mad_info
->mul_temp_id
]++;
2528 if (instr
->operands
[0].isTemp())
2529 ctx
.uses
[instr
->operands
[0].tempId()]--;
2530 if (instr
->operands
[1].isTemp())
2531 ctx
.uses
[instr
->operands
[1].tempId()]--;
2532 instr
.swap(mad_info
->add_instr
);
2535 /* check literals */
2536 else if (!instr
->usesModifiers()) {
2537 bool sgpr_used
= false;
2538 uint32_t literal_idx
= 0;
2539 uint32_t literal_uses
= UINT32_MAX
;
2540 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2542 if (instr
->operands
[i
].isConstant() && i
> 0) {
2543 literal_uses
= UINT32_MAX
;
2546 if (!instr
->operands
[i
].isTemp())
2548 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2549 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2550 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2551 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2554 literal_uses
= UINT32_MAX
;
2557 /* don't break because we still need to check constants */
2558 } else if (!sgpr_used
&&
2559 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2560 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2561 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2565 if (literal_uses
< threshold
) {
2566 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2567 mad_info
->check_literal
= true;
2568 mad_info
->literal_idx
= literal_idx
;
2574 /* check for literals */
2575 if (!instr
->isSALU() && !instr
->isVALU())
2578 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2579 return; /* some encodings can't ever take literals */
2581 /* we do not apply the literals yet as we don't know if it is profitable */
2582 Operand
current_literal(s1
);
2584 unsigned literal_id
= 0;
2585 unsigned literal_uses
= UINT32_MAX
;
2586 Operand
literal(s1
);
2587 unsigned num_operands
= 1;
2588 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2589 num_operands
= instr
->operands
.size();
2591 unsigned sgpr_ids
[2] = {0, 0};
2592 bool is_literal_sgpr
= false;
2595 /* choose a literal to apply */
2596 for (unsigned i
= 0; i
< num_operands
; i
++) {
2597 Operand op
= instr
->operands
[i
];
2598 if (op
.isLiteral()) {
2599 current_literal
= op
;
2601 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2602 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2603 op
.tempId() != sgpr_ids
[0])
2604 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2608 if (!can_accept_constant(instr
, i
))
2611 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2612 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2614 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2615 literal_uses
= ctx
.uses
[op
.tempId()];
2616 literal_id
= op
.tempId();
2619 mask
|= (op
.tempId() == literal_id
) << i
;
2623 /* don't go over the constant bus limit */
2624 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2625 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2626 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2627 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2628 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2629 const_bus_limit
= 2;
2631 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2632 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2635 if (literal_id
&& literal_uses
< threshold
&&
2636 (current_literal
.isUndefined() ||
2637 (current_literal
.size() == literal
.size() &&
2638 current_literal
.constantValue() == literal
.constantValue()))) {
2639 /* mark the literal to be applied */
2641 unsigned i
= u_bit_scan(&mask
);
2642 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2643 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2649 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2651 /* Cleanup Dead Instructions */
2655 /* apply literals on MAD */
2656 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2657 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2658 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2659 aco_ptr
<Instruction
> new_mad
;
2660 if (info
->literal_idx
== 2) { /* add literal -> madak */
2661 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2662 new_mad
->operands
[0] = instr
->operands
[0];
2663 new_mad
->operands
[1] = instr
->operands
[1];
2664 } else { /* mul literal -> madmk */
2665 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2666 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2667 new_mad
->operands
[1] = instr
->operands
[2];
2669 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2670 new_mad
->definitions
[0] = instr
->definitions
[0];
2671 ctx
.instructions
.emplace_back(std::move(new_mad
));
2676 /* apply literals on other SALU/VALU */
2677 if (instr
->isSALU() || instr
->isVALU()) {
2678 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2679 Operand op
= instr
->operands
[i
];
2680 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2681 Operand
literal(ctx
.info
[op
.tempId()].val
);
2682 if (instr
->isVALU() && i
> 0)
2683 to_VOP3(ctx
, instr
);
2684 instr
->operands
[i
] = literal
;
2689 ctx
.instructions
.emplace_back(std::move(instr
));
2693 void optimize(Program
* program
)
2696 ctx
.program
= program
;
2697 std::vector
<ssa_info
> info(program
->peekAllocationId());
2698 ctx
.info
= info
.data();
2700 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2701 for (Block
& block
: program
->blocks
) {
2702 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2703 label_instruction(ctx
, block
, instr
);
2706 ctx
.uses
= std::move(dead_code_analysis(program
));
2708 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2709 for (Block
& block
: program
->blocks
) {
2710 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2711 combine_instruction(ctx
, block
, instr
);
2714 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2715 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2716 Block
* block
= &(*it
);
2717 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2718 select_instruction(ctx
, *it
);
2721 /* 4. Add literals to instructions */
2722 for (Block
& block
: program
->blocks
) {
2723 ctx
.instructions
.clear();
2724 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2725 apply_literals(ctx
, instr
);
2726 block
.instructions
.swap(ctx
.instructions
);