2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
85 label_uniform_bool
= 1 << 21,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
;
90 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_abs(Temp abs_temp
)
143 add_label(label_abs
);
149 return label
& label_abs
;
152 void set_neg(Temp neg_temp
)
154 add_label(label_neg
);
160 return label
& label_neg
;
163 void set_neg_abs(Temp neg_abs_temp
)
165 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
169 void set_mul(Instruction
* mul
)
171 add_label(label_mul
);
177 return label
& label_mul
;
180 void set_temp(Temp tmp
)
182 add_label(label_temp
);
188 return label
& label_temp
;
191 void set_literal(uint32_t lit
)
193 add_label(label_literal
);
199 return label
& label_literal
;
202 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
204 add_label(label_mad
);
211 return label
& label_mad
;
216 add_label(label_omod2
);
221 return label
& label_omod2
;
226 add_label(label_omod4
);
231 return label
& label_omod4
;
236 add_label(label_omod5
);
241 return label
& label_omod5
;
244 void set_omod_success(Instruction
* omod_instr
)
246 add_label(label_omod_success
);
250 bool is_omod_success()
252 return label
& label_omod_success
;
257 add_label(label_clamp
);
262 return label
& label_clamp
;
265 void set_clamp_success(Instruction
* clamp_instr
)
267 add_label(label_clamp_success
);
271 bool is_clamp_success()
273 return label
& label_clamp_success
;
278 add_label(label_undefined
);
283 return label
& label_undefined
;
286 void set_vcc(Temp vcc
)
288 add_label(label_vcc
);
294 return label
& label_vcc
;
297 bool is_constant_or_literal()
299 return is_constant() || is_literal();
302 void set_b2f(Temp val
)
304 add_label(label_b2f
);
310 return label
& label_b2f
;
313 void set_add_sub(Instruction
*add_sub_instr
)
315 add_label(label_add_sub
);
316 instr
= add_sub_instr
;
321 return label
& label_add_sub
;
324 void set_bitwise(Instruction
*bitwise_instr
)
326 add_label(label_bitwise
);
327 instr
= bitwise_instr
;
332 return label
& label_bitwise
;
335 void set_minmax(Instruction
*minmax_instr
)
337 add_label(label_minmax
);
338 instr
= minmax_instr
;
343 return label
& label_minmax
;
346 void set_fcmp(Instruction
*fcmp_instr
)
348 add_label(label_fcmp
);
354 return label
& label_fcmp
;
357 void set_uniform_bool(Temp uniform_bool
)
359 add_label(label_uniform_bool
);
363 bool is_uniform_bool()
365 return label
& label_uniform_bool
;
372 std::vector
<aco_ptr
<Instruction
>> instructions
;
374 std::pair
<uint32_t,Temp
> last_literal
;
375 std::vector
<mad_info
> mad_infos
;
376 std::vector
<uint16_t> uses
;
379 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
381 if (instr
->operands
[0].isConstant() ||
382 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
385 switch (instr
->opcode
) {
386 case aco_opcode::v_add_f32
:
387 case aco_opcode::v_mul_f32
:
388 case aco_opcode::v_or_b32
:
389 case aco_opcode::v_and_b32
:
390 case aco_opcode::v_xor_b32
:
391 case aco_opcode::v_max_f32
:
392 case aco_opcode::v_min_f32
:
393 case aco_opcode::v_cmp_eq_f32
:
394 case aco_opcode::v_cmp_lg_f32
:
396 case aco_opcode::v_sub_f32
:
397 instr
->opcode
= aco_opcode::v_subrev_f32
;
399 case aco_opcode::v_cmp_lt_f32
:
400 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
402 case aco_opcode::v_cmp_ge_f32
:
403 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
405 case aco_opcode::v_cmp_lt_i32
:
406 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
413 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
415 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
418 if (instr
->isDPP() || instr
->isSDWA())
421 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
422 instr
->opcode
!= aco_opcode::v_madak_f32
&&
423 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
424 instr
->opcode
!= aco_opcode::v_madak_f16
;
427 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
429 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
430 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
431 instr
->opcode
!= aco_opcode::v_writelane_b32
;
434 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
439 assert(!instr
->operands
[0].isLiteral());
440 aco_ptr
<Instruction
> tmp
= std::move(instr
);
441 Format format
= asVOP3(tmp
->format
);
442 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
443 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
444 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
445 instr
->definitions
[i
] = tmp
->definitions
[i
];
446 if (instr
->definitions
[i
].isTemp()) {
447 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
448 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
449 info
.instr
= instr
.get();
454 /* only covers special cases */
455 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
457 switch (instr
->opcode
) {
458 case aco_opcode::v_interp_p2_f32
:
459 case aco_opcode::v_mac_f32
:
460 case aco_opcode::v_writelane_b32
:
461 case aco_opcode::v_cndmask_b32
:
463 case aco_opcode::s_addk_i32
:
464 case aco_opcode::s_mulk_i32
:
465 case aco_opcode::p_wqm
:
466 case aco_opcode::p_extract_vector
:
467 case aco_opcode::p_split_vector
:
468 case aco_opcode::v_readlane_b32
:
469 case aco_opcode::v_readfirstlane_b32
:
472 if ((instr
->format
== Format::MUBUF
||
473 instr
->format
== Format::MIMG
) &&
474 instr
->definitions
.size() == 1 &&
475 instr
->operands
.size() == 4) {
482 bool valu_can_accept_literal(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, unsigned operand
)
484 /* instructions like v_cndmask_b32 can't take a literal because they always
486 if (instr
->operands
.size() >= 3 &&
487 instr
->operands
[2].isTemp() && instr
->operands
[2].regClass().type() == RegType::sgpr
)
490 // TODO: VOP3 can take a literal on GFX10
491 return !instr
->isSDWA() && !instr
->isDPP() && !instr
->isVOP3() &&
492 operand
== 0 && can_accept_constant(instr
, operand
);
495 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
497 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
)
502 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
504 Operand op
= instr
->operands
[op_index
];
508 Temp tmp
= op
.getTemp();
509 if (!ctx
.info
[tmp
.id()].is_add_sub())
512 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
514 switch (add_instr
->opcode
) {
515 case aco_opcode::v_add_u32
:
516 case aco_opcode::v_add_co_u32
:
517 case aco_opcode::s_add_i32
:
518 case aco_opcode::s_add_u32
:
524 if (add_instr
->usesModifiers())
527 for (unsigned i
= 0; i
< 2; i
++) {
528 if (add_instr
->operands
[i
].isConstant()) {
529 *offset
= add_instr
->operands
[i
].constantValue();
530 } else if (add_instr
->operands
[i
].isTemp() &&
531 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
532 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
536 if (!add_instr
->operands
[!i
].isTemp())
539 uint32_t offset2
= 0;
540 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
543 *base
= add_instr
->operands
[!i
].getTemp();
551 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
553 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
554 ASSERTED
bool all_const
= false;
555 for (Operand
& op
: instr
->operands
)
556 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
557 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
560 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
562 if (!instr
->operands
[i
].isTemp())
565 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
566 /* propagate undef */
567 if (info
.is_undefined() && is_phi(instr
))
568 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
569 /* propagate reg->reg of same type */
570 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
571 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
572 info
= ctx
.info
[info
.temp
.id()];
575 /* SALU / PSEUDO: propagate inline constants */
576 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
577 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
578 instr
->operands
[i
].setTemp(info
.temp
);
579 info
= ctx
.info
[info
.temp
.id()];
580 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
581 /* propagate vgpr if it can take it */
582 switch (instr
->opcode
) {
583 case aco_opcode::p_create_vector
:
584 case aco_opcode::p_split_vector
:
585 case aco_opcode::p_extract_vector
:
586 case aco_opcode::p_phi
: {
587 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
588 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
590 instr
->operands
[i
] = Operand(info
.temp
);
591 info
= ctx
.info
[info
.temp
.id()];
599 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
600 instr
->operands
[i
] = Operand(info
.val
);
605 /* VALU: propagate neg, abs & inline constants */
606 else if (instr
->isVALU()) {
607 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
608 instr
->operands
[i
].setTemp(info
.temp
);
609 info
= ctx
.info
[info
.temp
.id()];
611 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
614 instr
->operands
[i
] = Operand(info
.temp
);
616 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
618 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
620 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
621 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
622 instr
->operands
[i
].setTemp(info
.temp
);
624 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
627 instr
->operands
[i
].setTemp(info
.temp
);
629 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
631 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
634 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
635 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
637 instr
->operands
[i
] = Operand(info
.val
);
639 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
640 instr
->operands
[i
] = instr
->operands
[0];
641 instr
->operands
[0] = Operand(info
.val
);
643 } else if (can_use_VOP3(instr
)) {
645 instr
->operands
[i
] = Operand(info
.val
);
651 /* MUBUF: propagate constants and combine additions */
652 else if (instr
->format
== Format::MUBUF
) {
653 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
656 while (info
.is_temp())
657 info
= ctx
.info
[info
.temp
.id()];
659 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
660 assert(!mubuf
->idxen
);
661 instr
->operands
[i
] = Operand(v1
);
662 mubuf
->offset
+= info
.val
;
663 mubuf
->offen
= false;
665 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
666 instr
->operands
[2] = Operand((uint32_t) 0);
667 mubuf
->offset
+= info
.val
;
669 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
670 assert(!mubuf
->idxen
);
671 instr
->operands
[i
].setTemp(base
);
672 mubuf
->offset
+= offset
;
674 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
675 instr
->operands
[i
].setTemp(base
);
676 mubuf
->offset
+= offset
;
681 /* DS: combine additions */
682 else if (instr
->format
== Format::DS
) {
684 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
687 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass()) {
688 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
689 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
690 if (offset
% 4 == 0 &&
691 ds
->offset0
+ (offset
>> 2) <= 255 &&
692 ds
->offset1
+ (offset
>> 2) <= 255) {
693 instr
->operands
[i
].setTemp(base
);
694 ds
->offset0
+= offset
>> 2;
695 ds
->offset1
+= offset
>> 2;
698 if (ds
->offset0
+ offset
<= 65535) {
699 instr
->operands
[i
].setTemp(base
);
700 ds
->offset0
+= offset
;
706 /* SMEM: propagate constants and combine additions */
707 else if (instr
->format
== Format::SMEM
) {
709 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
712 if (i
== 1 && info
.is_constant_or_literal() && info
.val
<= 0xFFFFF) {
713 instr
->operands
[i
] = Operand(info
.val
);
715 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
716 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
718 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
719 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
723 smem
->operands
[1] = Operand(offset
);
724 smem
->operands
.back() = Operand(base
);
726 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
727 new_instr
->operands
[0] = smem
->operands
[0];
728 new_instr
->operands
[1] = Operand(offset
);
729 if (smem
->definitions
.empty())
730 new_instr
->operands
[2] = smem
->operands
[2];
731 new_instr
->operands
.back() = Operand(base
);
732 if (!smem
->definitions
.empty())
733 new_instr
->definitions
[0] = smem
->definitions
[0];
734 new_instr
->can_reorder
= smem
->can_reorder
;
735 new_instr
->barrier
= smem
->barrier
;
736 instr
.reset(new_instr
);
737 smem
= static_cast<SMEM_instruction
*>(instr
.get());
744 /* if this instruction doesn't define anything, return */
745 if (instr
->definitions
.empty())
748 switch (instr
->opcode
) {
749 case aco_opcode::p_create_vector
: {
750 unsigned num_ops
= instr
->operands
.size();
751 for (const Operand
& op
: instr
->operands
) {
752 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
753 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
755 if (num_ops
!= instr
->operands
.size()) {
756 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
757 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
758 instr
->definitions
[0] = old_vec
->definitions
[0];
760 for (Operand
& old_op
: old_vec
->operands
) {
761 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
762 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++)
763 instr
->operands
[k
++] = ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
765 instr
->operands
[k
++] = old_op
;
768 assert(k
== num_ops
);
770 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
771 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
772 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
773 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
776 case aco_opcode::p_split_vector
: {
777 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
779 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
780 assert(instr
->definitions
.size() == vec
->operands
.size());
781 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
782 Operand vec_op
= vec
->operands
[i
];
783 if (vec_op
.isConstant()) {
784 if (vec_op
.isLiteral())
785 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
786 else if (vec_op
.size() == 1)
787 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
789 assert(vec_op
.isTemp());
790 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
795 case aco_opcode::p_extract_vector
: { /* mov */
796 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
798 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
799 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
800 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
802 /* convert this extract into a mov instruction */
803 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
804 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
805 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
806 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
807 instr
->opcode
= opcode
;
808 instr
->format
= format
;
809 instr
->operands
= {instr
->operands
.begin(), 1 };
810 instr
->operands
[0] = vec_op
;
812 if (vec_op
.isConstant()) {
813 if (vec_op
.isLiteral())
814 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
815 else if (vec_op
.size() == 1)
816 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
818 assert(vec_op
.isTemp());
819 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
824 case aco_opcode::s_mov_b32
: /* propagate */
825 case aco_opcode::s_mov_b64
:
826 case aco_opcode::v_mov_b32
:
827 case aco_opcode::p_as_uniform
:
828 if (instr
->definitions
[0].isFixed()) {
829 /* don't copy-propagate copies into fixed registers */
830 } else if (instr
->usesModifiers()) {
832 } else if (instr
->operands
[0].isConstant()) {
833 if (instr
->operands
[0].isLiteral())
834 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
835 else if (instr
->operands
[0].size() == 1)
836 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
837 } else if (instr
->operands
[0].isTemp()) {
838 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
840 assert(instr
->operands
[0].isFixed());
843 case aco_opcode::p_is_helper
:
844 if (!ctx
.program
->needs_wqm
)
845 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
847 case aco_opcode::s_movk_i32
: {
848 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
849 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
850 if (v
<= 64 || v
>= 0xfffffff0)
851 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
853 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
856 case aco_opcode::v_bfrev_b32
:
857 case aco_opcode::s_brev_b32
: {
858 if (instr
->operands
[0].isConstant()) {
859 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
860 if (v
<= 64 || v
>= 0xfffffff0)
861 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
863 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
867 case aco_opcode::s_bfm_b32
: {
868 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
869 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
870 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
871 uint32_t v
= ((1u << size
) - 1u) << start
;
872 if (v
<= 64 || v
>= 0xfffffff0)
873 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
875 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
878 case aco_opcode::v_mul_f32
: { /* omod */
879 /* TODO: try to move the negate/abs modifier to the consumer instead */
880 if (instr
->usesModifiers())
883 for (unsigned i
= 0; i
< 2; i
++) {
884 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
885 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
886 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2();
887 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
888 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4();
889 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
890 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5();
891 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
892 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
893 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
902 case aco_opcode::v_and_b32
: /* abs */
903 if (instr
->operands
[0].constantEquals(0x7FFFFFFF) && instr
->operands
[1].isTemp())
904 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
906 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
908 case aco_opcode::v_xor_b32
: { /* neg */
909 if (instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
910 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
911 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
913 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
914 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
915 instr
->opcode
= aco_opcode::v_or_b32
;
916 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
918 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
922 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
926 case aco_opcode::v_med3_f32
: { /* clamp */
927 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
928 if (vop3
->abs
[0] || vop3
->neg
[0] || vop3
->opsel
[0] ||
929 vop3
->abs
[1] || vop3
->neg
[1] || vop3
->opsel
[1] ||
930 vop3
->abs
[2] || vop3
->neg
[2] || vop3
->opsel
[2] ||
935 bool found_zero
= false, found_one
= false;
936 for (unsigned i
= 0; i
< 3; i
++)
938 if (instr
->operands
[i
].constantEquals(0))
940 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
945 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
946 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp();
950 case aco_opcode::v_cndmask_b32
:
951 if (instr
->operands
[0].constantEquals(0) &&
952 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
953 instr
->operands
[2].isTemp())
954 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
955 else if (instr
->operands
[0].constantEquals(0) &&
956 instr
->operands
[1].constantEquals(0x3f800000u
) &&
957 instr
->operands
[2].isTemp())
958 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
960 case aco_opcode::v_cmp_lg_u32
:
961 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
962 instr
->operands
[0].constantEquals(0) &&
963 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
964 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
966 case aco_opcode::p_phi
:
967 case aco_opcode::p_linear_phi
: {
968 /* lower_bool_phis() can create phis like this */
969 bool all_same_temp
= instr
->operands
[0].isTemp();
970 /* this check is needed when moving uniform loop counters out of a divergent loop */
972 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
973 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
974 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
975 all_same_temp
= false;
978 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
980 bool all_undef
= instr
->operands
[0].isUndefined();
981 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
982 if (!instr
->operands
[i
].isUndefined())
986 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
990 case aco_opcode::v_add_u32
:
991 case aco_opcode::v_add_co_u32
:
992 case aco_opcode::s_add_i32
:
993 case aco_opcode::s_add_u32
:
994 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
996 case aco_opcode::s_and_b32
:
997 case aco_opcode::s_and_b64
:
998 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
999 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1000 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1003 case aco_opcode::s_not_b32
:
1004 case aco_opcode::s_not_b64
:
1005 case aco_opcode::s_or_b32
:
1006 case aco_opcode::s_or_b64
:
1007 case aco_opcode::s_xor_b32
:
1008 case aco_opcode::s_xor_b64
:
1009 case aco_opcode::s_lshl_b32
:
1010 case aco_opcode::v_or_b32
:
1011 case aco_opcode::v_lshlrev_b32
:
1012 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1014 case aco_opcode::v_min_f32
:
1015 case aco_opcode::v_min_f16
:
1016 case aco_opcode::v_min_u32
:
1017 case aco_opcode::v_min_i32
:
1018 case aco_opcode::v_min_u16
:
1019 case aco_opcode::v_min_i16
:
1020 case aco_opcode::v_max_f32
:
1021 case aco_opcode::v_max_f16
:
1022 case aco_opcode::v_max_u32
:
1023 case aco_opcode::v_max_i32
:
1024 case aco_opcode::v_max_u16
:
1025 case aco_opcode::v_max_i16
:
1026 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1028 case aco_opcode::v_cmp_lt_f32
:
1029 case aco_opcode::v_cmp_eq_f32
:
1030 case aco_opcode::v_cmp_le_f32
:
1031 case aco_opcode::v_cmp_gt_f32
:
1032 case aco_opcode::v_cmp_lg_f32
:
1033 case aco_opcode::v_cmp_ge_f32
:
1034 case aco_opcode::v_cmp_o_f32
:
1035 case aco_opcode::v_cmp_u_f32
:
1036 case aco_opcode::v_cmp_nge_f32
:
1037 case aco_opcode::v_cmp_nlg_f32
:
1038 case aco_opcode::v_cmp_ngt_f32
:
1039 case aco_opcode::v_cmp_nle_f32
:
1040 case aco_opcode::v_cmp_neq_f32
:
1041 case aco_opcode::v_cmp_nlt_f32
:
1042 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1044 case aco_opcode::s_cselect_b64
:
1045 case aco_opcode::s_cselect_b32
:
1046 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1047 instr
->operands
[1].constantEquals(0)) {
1048 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1049 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1057 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1059 *ordered
= *unordered
= op
;
1061 #define CMP(ord, unord) \
1062 case aco_opcode::v_cmp_##ord##_f32:\
1063 case aco_opcode::v_cmp_n##unord##_f32:\
1064 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1065 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1066 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1080 aco_opcode
get_ordered(aco_opcode op
)
1082 aco_opcode ordered
, unordered
, inverse
;
1083 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1086 aco_opcode
get_unordered(aco_opcode op
)
1088 aco_opcode ordered
, unordered
, inverse
;
1089 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1092 aco_opcode
get_inverse(aco_opcode op
)
1094 aco_opcode ordered
, unordered
, inverse
;
1095 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1098 bool is_cmp(aco_opcode op
)
1100 aco_opcode ordered
, unordered
, inverse
;
1101 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1104 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1106 if (ctx
.info
[tmp
.id()].is_temp())
1107 return ctx
.info
[tmp
.id()].temp
.id();
1112 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1114 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1115 for (const Operand
& op
: instr
->operands
) {
1117 ctx
.uses
[op
.tempId()]--;
1122 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1124 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1126 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1129 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1131 if (instr
->definitions
.size() == 2) {
1132 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1133 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1140 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1141 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1142 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1144 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1146 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1149 bool neg
[2] = {false, false};
1150 bool abs
[2] = {false, false};
1151 bool opsel
[2] = {false, false};
1152 Instruction
*op_instr
[2];
1155 for (unsigned i
= 0; i
< 2; i
++) {
1156 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1160 aco_opcode expected_cmp
= instr
->opcode
== aco_opcode::s_or_b64
?
1161 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1163 if (op_instr
[i
]->opcode
!= expected_cmp
)
1165 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1168 if (op_instr
[i
]->isVOP3()) {
1169 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1170 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
[0] != vop3
->opsel
[1])
1172 neg
[i
] = vop3
->neg
[0];
1173 abs
[i
] = vop3
->abs
[0];
1174 opsel
[i
] = vop3
->opsel
[0];
1177 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1178 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1179 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1181 /* shouldn't happen yet, but best to be safe */
1182 if (op1
.type() != RegType::vgpr
)
1188 ctx
.uses
[op
[0].id()]++;
1189 ctx
.uses
[op
[1].id()]++;
1190 decrease_uses(ctx
, op_instr
[0]);
1191 decrease_uses(ctx
, op_instr
[1]);
1193 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1194 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1195 Instruction
*new_instr
;
1196 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
[0] || opsel
[1]) {
1197 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1198 for (unsigned i
= 0; i
< 2; i
++) {
1199 vop3
->neg
[i
] = neg
[i
];
1200 vop3
->abs
[i
] = abs
[i
];
1201 vop3
->opsel
[i
] = opsel
[i
];
1203 new_instr
= static_cast<Instruction
*>(vop3
);
1205 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1207 new_instr
->operands
[0] = Operand(op
[0]);
1208 new_instr
->operands
[1] = Operand(op
[1]);
1209 new_instr
->definitions
[0] = instr
->definitions
[0];
1211 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1212 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1214 instr
.reset(new_instr
);
1219 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1220 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1221 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1223 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1225 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1228 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1229 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1231 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1232 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1233 if (!nan_test
|| !cmp
)
1236 if (cmp
->opcode
== expected_nan_test
)
1237 std::swap(nan_test
, cmp
);
1238 else if (nan_test
->opcode
!= expected_nan_test
)
1241 if (!is_cmp(cmp
->opcode
))
1244 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1246 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1249 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1250 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1251 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1252 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1253 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1255 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1258 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1259 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1260 decrease_uses(ctx
, nan_test
);
1261 decrease_uses(ctx
, cmp
);
1263 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1264 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1265 Instruction
*new_instr
;
1266 if (cmp
->isVOP3()) {
1267 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1268 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1269 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1270 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1271 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1272 new_vop3
->clamp
= cmp_vop3
->clamp
;
1273 new_vop3
->omod
= cmp_vop3
->omod
;
1274 new_instr
= new_vop3
;
1276 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1278 new_instr
->operands
[0] = cmp
->operands
[0];
1279 new_instr
->operands
[1] = cmp
->operands
[1];
1280 new_instr
->definitions
[0] = instr
->definitions
[0];
1282 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1283 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1285 instr
.reset(new_instr
);
1290 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1291 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1292 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1294 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1296 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1299 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1300 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1302 if (!nan_test
|| !cmp
)
1305 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1306 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1307 if (cmp
->opcode
== expected_nan_test
)
1308 std::swap(nan_test
, cmp
);
1309 else if (nan_test
->opcode
!= expected_nan_test
)
1312 if (!is_cmp(cmp
->opcode
))
1315 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1317 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1320 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1321 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1322 if (prop_nan0
!= prop_nan1
)
1325 int constant_operand
= -1;
1326 for (unsigned i
= 0; i
< 2; i
++) {
1327 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1328 constant_operand
= !i
;
1332 if (constant_operand
== -1)
1336 if (cmp
->operands
[constant_operand
].isConstant()) {
1337 constant
= cmp
->operands
[constant_operand
].constantValue();
1338 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1339 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1340 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1342 constant
= ctx
.info
[id
].val
;
1348 memcpy(&constantf
, &constant
, 4);
1349 if (isnan(constantf
))
1352 if (cmp
->operands
[0].isTemp())
1353 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1354 if (cmp
->operands
[1].isTemp())
1355 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1356 decrease_uses(ctx
, nan_test
);
1357 decrease_uses(ctx
, cmp
);
1359 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1360 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1361 Instruction
*new_instr
;
1362 if (cmp
->isVOP3()) {
1363 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1364 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1365 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1366 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1367 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1368 new_vop3
->clamp
= cmp_vop3
->clamp
;
1369 new_vop3
->omod
= cmp_vop3
->omod
;
1370 new_instr
= new_vop3
;
1372 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1374 new_instr
->operands
[0] = cmp
->operands
[0];
1375 new_instr
->operands
[1] = cmp
->operands
[1];
1376 new_instr
->definitions
[0] = instr
->definitions
[0];
1378 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1379 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1381 instr
.reset(new_instr
);
1386 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1387 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1389 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1391 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1393 if (!instr
->operands
[0].isTemp())
1396 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1400 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1401 if (new_opcode
== aco_opcode::last_opcode
)
1404 if (cmp
->operands
[0].isTemp())
1405 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1406 if (cmp
->operands
[1].isTemp())
1407 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1408 decrease_uses(ctx
, cmp
);
1410 Instruction
*new_instr
;
1411 if (cmp
->isVOP3()) {
1412 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1413 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1414 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1415 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1416 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1417 new_vop3
->clamp
= cmp_vop3
->clamp
;
1418 new_vop3
->omod
= cmp_vop3
->omod
;
1419 new_instr
= new_vop3
;
1421 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1423 new_instr
->operands
[0] = cmp
->operands
[0];
1424 new_instr
->operands
[1] = cmp
->operands
[1];
1425 new_instr
->definitions
[0] = instr
->definitions
[0];
1427 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1428 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1430 instr
.reset(new_instr
);
1435 /* op1(op2(1, 2), 0) if swap = false
1436 * op1(0, op2(1, 2)) if swap = true */
1437 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1438 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1439 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1440 bool *op1_clamp
, unsigned *op1_omod
,
1441 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1444 if (op1_instr
->opcode
!= op1
)
1447 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1448 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1451 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1452 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1454 /* don't support inbetween clamp/omod */
1455 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1458 /* get operands and modifiers and check inbetween modifiers */
1459 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1460 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1463 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1464 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1468 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1469 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1472 if (inbetween_opsel
)
1473 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
[swap
] : false;
1474 else if (op1_vop3
&& op1_vop3
->opsel
[swap
])
1478 shuffle
[shuffle_str
[0] - '0'] = 0;
1479 shuffle
[shuffle_str
[1] - '0'] = 1;
1480 shuffle
[shuffle_str
[2] - '0'] = 2;
1482 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1483 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1484 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1485 opsel
[shuffle
[0]] = op1_vop3
? op1_vop3
->opsel
[!swap
] : false;
1487 for (unsigned i
= 0; i
< 2; i
++) {
1488 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1489 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1490 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1491 opsel
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->opsel
[i
] : false;
1494 /* check operands */
1495 unsigned sgpr_id
= 0;
1496 for (unsigned i
= 0; i
< 3; i
++) {
1497 Operand op
= operands
[i
];
1498 if (op
.isLiteral()) {
1500 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1501 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1503 sgpr_id
= op
.tempId();
1510 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1511 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1512 bool clamp
, unsigned omod
)
1514 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1515 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1516 memcpy(new_instr
->opsel
, opsel
, sizeof(bool[3]));
1517 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1518 new_instr
->clamp
= clamp
;
1519 new_instr
->omod
= omod
;
1520 new_instr
->operands
[0] = operands
[0];
1521 new_instr
->operands
[1] = operands
[1];
1522 new_instr
->operands
[2] = operands
[2];
1523 new_instr
->definitions
[0] = instr
->definitions
[0];
1524 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1526 instr
.reset(new_instr
);
1529 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1531 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1532 (label_omod_success
| label_clamp_success
);
1534 for (unsigned swap
= 0; swap
< 2; swap
++) {
1535 if (!((1 << swap
) & ops
))
1538 Operand operands
[3];
1539 bool neg
[3], abs
[3], opsel
[3], clamp
;
1541 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1542 instr
.get(), swap
, shuffle
,
1543 operands
, neg
, abs
, opsel
,
1544 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1545 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1546 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1547 if (omod_clamp
& label_omod_success
)
1548 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1549 if (omod_clamp
& label_clamp_success
)
1550 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1557 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1558 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1559 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1560 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1561 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1562 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1563 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1566 if (!instr
->operands
[0].isTemp())
1568 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1571 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1574 switch (op2_instr
->opcode
) {
1575 case aco_opcode::s_and_b32
:
1576 case aco_opcode::s_or_b32
:
1577 case aco_opcode::s_xor_b32
:
1578 case aco_opcode::s_and_b64
:
1579 case aco_opcode::s_or_b64
:
1580 case aco_opcode::s_xor_b64
:
1586 /* create instruction */
1587 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1588 ctx
.uses
[instr
->operands
[0].tempId()]--;
1589 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1591 switch (op2_instr
->opcode
) {
1592 case aco_opcode::s_and_b32
:
1593 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1595 case aco_opcode::s_or_b32
:
1596 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1598 case aco_opcode::s_xor_b32
:
1599 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1601 case aco_opcode::s_and_b64
:
1602 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1604 case aco_opcode::s_or_b64
:
1605 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1607 case aco_opcode::s_xor_b64
:
1608 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1617 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1618 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1619 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1620 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1621 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1623 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1626 for (unsigned i
= 0; i
< 2; i
++) {
1627 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1628 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1631 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1632 instr
->operands
[0] = instr
->operands
[!i
];
1633 instr
->operands
[1] = op2_instr
->operands
[0];
1634 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1636 switch (instr
->opcode
) {
1637 case aco_opcode::s_and_b32
:
1638 instr
->opcode
= aco_opcode::s_andn2_b32
;
1640 case aco_opcode::s_or_b32
:
1641 instr
->opcode
= aco_opcode::s_orn2_b32
;
1643 case aco_opcode::s_and_b64
:
1644 instr
->opcode
= aco_opcode::s_andn2_b64
;
1646 case aco_opcode::s_or_b64
:
1647 instr
->opcode
= aco_opcode::s_orn2_b64
;
1658 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1659 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1661 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1664 for (unsigned i
= 0; i
< 2; i
++) {
1665 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1666 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1669 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1670 if (shift
< 1 || shift
> 4)
1673 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1674 instr
->operands
[1] = instr
->operands
[!i
];
1675 instr
->operands
[0] = op2_instr
->operands
[0];
1676 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1678 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1679 aco_opcode::s_lshl2_add_u32
,
1680 aco_opcode::s_lshl3_add_u32
,
1681 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1688 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1691 #define MINMAX(type, gfx9) \
1692 case aco_opcode::v_min_##type:\
1693 case aco_opcode::v_max_##type:\
1694 case aco_opcode::v_med3_##type:\
1695 *min = aco_opcode::v_min_##type;\
1696 *max = aco_opcode::v_max_##type;\
1697 *med3 = aco_opcode::v_med3_##type;\
1698 *min3 = aco_opcode::v_min3_##type;\
1699 *max3 = aco_opcode::v_max3_##type;\
1700 *some_gfx9_only = gfx9;\
1714 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1715 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1716 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1717 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1719 aco_opcode other_op
;
1720 if (instr
->opcode
== min
)
1722 else if (instr
->opcode
== max
)
1727 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1728 (label_omod_success
| label_clamp_success
);
1730 for (unsigned swap
= 0; swap
< 2; swap
++) {
1731 Operand operands
[3];
1732 bool neg
[3], abs
[3], opsel
[3], clamp
, inbetween_neg
, inbetween_abs
;
1734 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1735 "012", operands
, neg
, abs
, opsel
,
1736 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1737 int const0_idx
= -1, const1_idx
= -1;
1738 uint32_t const0
= 0, const1
= 0;
1739 for (int i
= 0; i
< 3; i
++) {
1741 if (operands
[i
].isConstant()) {
1742 val
= operands
[i
].constantValue();
1743 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1744 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1745 val
= ctx
.info
[operands
[i
].tempId()].val
;
1749 if (const0_idx
>= 0) {
1757 if (const0_idx
< 0 || const1_idx
< 0)
1760 if (opsel
[const0_idx
])
1762 if (opsel
[const1_idx
])
1765 int lower_idx
= const0_idx
;
1767 case aco_opcode::v_min_f32
:
1768 case aco_opcode::v_min_f16
: {
1769 float const0_f
, const1_f
;
1770 if (min
== aco_opcode::v_min_f32
) {
1771 memcpy(&const0_f
, &const0
, 4);
1772 memcpy(&const1_f
, &const1
, 4);
1774 const0_f
= _mesa_half_to_float(const0
);
1775 const1_f
= _mesa_half_to_float(const1
);
1777 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1778 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1779 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1780 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1781 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1784 case aco_opcode::v_min_u32
: {
1785 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1788 case aco_opcode::v_min_u16
: {
1789 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1792 case aco_opcode::v_min_i32
: {
1793 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1794 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1795 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1798 case aco_opcode::v_min_i16
: {
1799 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1800 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1801 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1807 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1809 if (instr
->opcode
== min
) {
1810 if (upper_idx
!= 0 || lower_idx
== 0)
1813 if (upper_idx
== 0 || lower_idx
!= 0)
1817 neg
[1] ^= inbetween_neg
;
1818 neg
[2] ^= inbetween_neg
;
1819 abs
[1] |= inbetween_abs
;
1820 abs
[2] |= inbetween_abs
;
1822 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1823 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1824 if (omod_clamp
& label_omod_success
)
1825 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1826 if (omod_clamp
& label_clamp_success
)
1827 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1837 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1840 uint32_t sgpr_idx
= 0;
1841 uint32_t sgpr_info_id
= 0;
1842 bool has_sgpr
= false;
1843 uint32_t sgpr_ssa_id
= 0;
1844 /* find 'best' possible sgpr */
1845 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
1847 if (instr
->operands
[i
].isLiteral()) {
1851 if (!instr
->operands
[i
].isTemp())
1853 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1855 sgpr_ssa_id
= instr
->operands
[i
].tempId();
1858 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1859 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
1860 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1861 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1863 sgpr_info_id
= instr
->operands
[i
].tempId();
1867 if (!has_sgpr
&& sgpr_info_id
!= 0) {
1868 ssa_info
& info
= ctx
.info
[sgpr_info_id
];
1869 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1870 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1871 ctx
.uses
[sgpr_info_id
]--;
1872 ctx
.uses
[info
.temp
.id()]++;
1873 } else if (can_swap_operands(instr
)) {
1874 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1875 instr
->operands
[0] = Operand(info
.temp
);
1876 ctx
.uses
[sgpr_info_id
]--;
1877 ctx
.uses
[info
.temp
.id()]++;
1878 } else if (can_use_VOP3(instr
)) {
1879 to_VOP3(ctx
, instr
);
1880 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1881 ctx
.uses
[sgpr_info_id
]--;
1882 ctx
.uses
[info
.temp
.id()]++;
1885 /* we can have two sgprs on one instruction if it is the same sgpr! */
1886 } else if (sgpr_info_id
!= 0 &&
1887 sgpr_ssa_id
== sgpr_info_id
&&
1888 ctx
.uses
[sgpr_info_id
] == 1 &&
1889 can_use_VOP3(instr
)) {
1890 to_VOP3(ctx
, instr
);
1891 instr
->operands
[sgpr_idx
] = Operand(ctx
.info
[sgpr_info_id
].temp
);
1892 ctx
.uses
[sgpr_info_id
]--;
1893 ctx
.uses
[ctx
.info
[sgpr_info_id
].temp
.id()]++;
1897 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1899 /* check if we could apply omod on predecessor */
1900 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1901 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success()) {
1903 /* omod was successfully applied */
1904 /* if the omod instruction is v_mad, we also have to change the original add */
1905 if (ctx
.info
[instr
->operands
[1].tempId()].is_mad()) {
1906 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[1].tempId()].val
].add_instr
.get();
1907 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1908 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1909 add_instr
->definitions
[0] = instr
->definitions
[0];
1912 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
1913 /* check if we have an additional clamp modifier */
1914 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1) {
1915 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1916 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1918 /* change definition ssa-id of modified instruction */
1919 omod_instr
->definitions
[0] = instr
->definitions
[0];
1921 /* change the definition of instr to something unused, e.g. the original omod def */
1922 instr
->definitions
[0] = Definition(instr
->operands
[1].getTemp());
1923 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1926 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1927 /* in all other cases, label this instruction as option for multiply-add */
1928 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1932 /* check if we could apply clamp on predecessor */
1933 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1935 bool found_zero
= false, found_one
= false;
1936 for (unsigned i
= 0; i
< 3; i
++)
1938 if (instr
->operands
[i
].constantEquals(0))
1940 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1945 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1946 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1947 /* clamp was successfully applied */
1948 /* if the clamp instruction is v_mad, we also have to change the original add */
1949 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1950 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1951 add_instr
->definitions
[0] = instr
->definitions
[0];
1953 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1954 /* change definition ssa-id of modified instruction */
1955 clamp_instr
->definitions
[0] = instr
->definitions
[0];
1957 /* change the definition of instr to something unused, e.g. the original omod def */
1958 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1959 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1964 /* omod has no effect if denormals are enabled */
1965 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
1967 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
1968 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1969 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
1970 if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod2()) {
1971 to_VOP3(ctx
, instr
);
1972 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
1973 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1974 } else if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod4()) {
1975 to_VOP3(ctx
, instr
);
1976 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
1977 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1978 } else if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod5()) {
1979 to_VOP3(ctx
, instr
);
1980 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
1981 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1982 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp()) {
1983 to_VOP3(ctx
, instr
);
1984 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
1985 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1992 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
1993 // this would mean that we'd have to fix the instruction uses while value propagation
1995 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1997 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2000 if (instr
->isVALU()) {
2001 if (can_apply_sgprs(instr
))
2002 apply_sgprs(ctx
, instr
);
2003 if (apply_omod_clamp(ctx
, block
, instr
))
2007 /* TODO: There are still some peephole optimizations that could be done:
2008 * - abs(a - b) -> s_absdiff_i32
2009 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2010 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2011 * These aren't probably too interesting though.
2012 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2013 * probably more useful than the previously mentioned optimizations.
2014 * The various comparison optimizations also currently only work with 32-bit
2017 /* neg(mul(a, b)) -> mul(neg(a), b) */
2018 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2019 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2021 if (!ctx
.info
[val
.id()].is_mul())
2024 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2026 if (mul_instr
->operands
[0].isLiteral())
2028 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2031 /* convert to mul(neg(a), b) */
2032 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2033 Definition def
= instr
->definitions
[0];
2034 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2035 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2036 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2037 instr
->operands
[0] = mul_instr
->operands
[0];
2038 instr
->operands
[1] = mul_instr
->operands
[1];
2039 instr
->definitions
[0] = def
;
2040 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2041 if (mul_instr
->isVOP3()) {
2042 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2043 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2044 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2045 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2046 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2047 new_mul
->omod
= mul
->omod
;
2049 new_mul
->neg
[0] ^= true;
2050 new_mul
->clamp
= false;
2052 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2055 /* combine mul+add -> mad */
2056 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2057 instr
->opcode
== aco_opcode::v_sub_f32
||
2058 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2059 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2060 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2062 uint32_t uses_src0
= UINT32_MAX
;
2063 uint32_t uses_src1
= UINT32_MAX
;
2064 Instruction
* mul_instr
= nullptr;
2065 unsigned add_op_idx
;
2066 /* check if any of the operands is a multiplication */
2067 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2068 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2069 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2070 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2072 /* find the 'best' mul instruction to combine with the add */
2073 if (uses_src0
< uses_src1
) {
2074 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2076 } else if (uses_src1
< uses_src0
) {
2077 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2079 } else if (uses_src0
!= UINT32_MAX
) {
2080 /* tiebreaker: quite random what to pick */
2081 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2082 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2085 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2090 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2091 bool neg
[3] = {false, false, false};
2092 bool abs
[3] = {false, false, false};
2095 bool need_vop3
= false;
2097 op
[0] = mul_instr
->operands
[0];
2098 op
[1] = mul_instr
->operands
[1];
2099 op
[2] = instr
->operands
[add_op_idx
];
2100 for (unsigned i
= 0; i
< 3; i
++)
2102 if (op
[i
].isLiteral())
2104 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
)
2106 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2109 // TODO: would be better to check this before selecting a mul instr?
2113 if (mul_instr
->isVOP3()) {
2114 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2115 neg
[0] = vop3
->neg
[0];
2116 neg
[1] = vop3
->neg
[1];
2117 abs
[0] = vop3
->abs
[0];
2118 abs
[1] = vop3
->abs
[1];
2120 /* we cannot use these modifiers between mul and add */
2121 if (vop3
->clamp
|| vop3
->omod
)
2125 /* convert to mad */
2126 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2127 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2129 ctx
.uses
[op
[0].tempId()]++;
2131 ctx
.uses
[op
[1].tempId()]++;
2134 if (instr
->isVOP3()) {
2135 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2136 neg
[2] = vop3
->neg
[add_op_idx
];
2137 abs
[2] = vop3
->abs
[add_op_idx
];
2139 clamp
= vop3
->clamp
;
2140 /* abs of the multiplication result */
2141 if (vop3
->abs
[1 - add_op_idx
]) {
2147 /* neg of the multiplication result */
2148 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2151 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2152 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2154 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2155 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2159 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2160 for (unsigned i
= 0; i
< 3; i
++)
2162 mad
->operands
[i
] = op
[i
];
2163 mad
->neg
[i
] = neg
[i
];
2164 mad
->abs
[i
] = abs
[i
];
2168 mad
->definitions
[0] = instr
->definitions
[0];
2170 /* mark this ssa_def to be re-checked for profitability and literals */
2171 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2172 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2173 instr
.reset(mad
.release());
2177 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2178 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2179 for (unsigned i
= 0; i
< 2; i
++) {
2180 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2181 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2182 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2183 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2184 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2186 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2187 new_instr
->operands
[0] = Operand(0u);
2188 new_instr
->operands
[1] = instr
->operands
[!i
];
2189 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2190 new_instr
->definitions
[0] = instr
->definitions
[0];
2191 instr
.reset(new_instr
.release());
2192 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2196 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2197 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2198 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2199 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2200 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2201 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2202 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2203 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2204 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2205 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2206 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2207 combine_salu_lshl_add(ctx
, instr
);
2208 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2209 combine_salu_not_bitwise(ctx
, instr
);
2210 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2211 if (combine_inverse_comparison(ctx
, instr
)) ;
2212 else combine_salu_not_bitwise(ctx
, instr
);
2213 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
) {
2214 combine_salu_n2(ctx
, instr
);
2215 } else if (instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2216 if (combine_ordering_test(ctx
, instr
)) ;
2217 else if (combine_comparison_ordering(ctx
, instr
)) ;
2218 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2219 else combine_salu_n2(ctx
, instr
);
2221 aco_opcode min
, max
, min3
, max3
, med3
;
2222 bool some_gfx9_only
;
2223 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2224 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2225 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2226 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2232 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2234 const uint32_t threshold
= 4;
2236 /* Dead Code Elimination:
2237 * We remove instructions if they define temporaries which all are unused */
2238 const bool is_used
= instr
->definitions
.empty() ||
2239 std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
2240 [&ctx
](const Definition
& def
) { return ctx
.uses
[def
.tempId()]; });
2246 /* convert split_vector into extract_vector if only one definition is ever used */
2247 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2248 unsigned num_used
= 0;
2250 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2251 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2256 if (num_used
== 1) {
2257 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2258 extract
->operands
[0] = instr
->operands
[0];
2259 extract
->operands
[1] = Operand((uint32_t) idx
);
2260 extract
->definitions
[0] = instr
->definitions
[idx
];
2261 instr
.reset(extract
.release());
2265 /* re-check mad instructions */
2266 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2267 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2268 /* first, check profitability */
2269 if (ctx
.uses
[info
->mul_temp_id
]) {
2270 ctx
.uses
[info
->mul_temp_id
]++;
2271 instr
.swap(info
->add_instr
);
2273 /* second, check possible literals */
2274 } else if (!info
->needs_vop3
) {
2275 uint32_t literal_idx
= 0;
2276 uint32_t literal_uses
= UINT32_MAX
;
2277 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2279 if (!instr
->operands
[i
].isTemp())
2281 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2282 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2283 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2284 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2287 literal_uses
= UINT32_MAX
;
2291 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2292 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2293 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2297 if (literal_uses
< threshold
) {
2298 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2299 info
->check_literal
= true;
2300 info
->literal_idx
= literal_idx
;
2306 /* check for literals */
2307 /* we do not apply the literals yet as we don't know if it is profitable */
2308 if (instr
->isSALU()) {
2309 uint32_t literal_idx
= 0;
2310 uint32_t literal_uses
= UINT32_MAX
;
2311 bool has_literal
= false;
2312 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2314 if (instr
->operands
[i
].isLiteral()) {
2318 if (!instr
->operands
[i
].isTemp())
2320 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2321 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2322 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2326 if (!has_literal
&& literal_uses
< threshold
) {
2327 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2328 if (ctx
.uses
[instr
->operands
[literal_idx
].tempId()] == 0)
2329 instr
->operands
[literal_idx
] = Operand(ctx
.info
[instr
->operands
[literal_idx
].tempId()].val
);
2331 } else if (instr
->isVALU() && valu_can_accept_literal(ctx
, instr
, 0) &&
2332 instr
->operands
[0].isTemp() &&
2333 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2334 ctx
.uses
[instr
->operands
[0].tempId()] < threshold
) {
2335 ctx
.uses
[instr
->operands
[0].tempId()]--;
2336 if (ctx
.uses
[instr
->operands
[0].tempId()] == 0)
2337 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2343 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2345 /* Cleanup Dead Instructions */
2349 /* apply literals on SALU */
2350 if (instr
->isSALU()) {
2351 for (Operand
& op
: instr
->operands
) {
2356 if (ctx
.info
[op
.tempId()].is_literal() &&
2357 ctx
.uses
[op
.tempId()] == 0)
2358 op
= Operand(ctx
.info
[op
.tempId()].val
);
2362 /* apply literals on VALU */
2363 else if (instr
->isVALU() && !instr
->isVOP3() &&
2364 instr
->operands
[0].isTemp() &&
2365 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2366 ctx
.uses
[instr
->operands
[0].tempId()] == 0) {
2367 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2370 /* apply literals on MAD */
2371 else if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2372 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2373 aco_ptr
<Instruction
> new_mad
;
2374 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2375 if (info
->literal_idx
== 2) { /* add literal -> madak */
2376 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2377 new_mad
->operands
[0] = instr
->operands
[0];
2378 new_mad
->operands
[1] = instr
->operands
[1];
2379 } else { /* mul literal -> madmk */
2380 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2381 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2382 new_mad
->operands
[1] = instr
->operands
[2];
2384 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2385 new_mad
->definitions
[0] = instr
->definitions
[0];
2386 instr
.swap(new_mad
);
2390 ctx
.instructions
.emplace_back(std::move(instr
));
2394 void optimize(Program
* program
)
2397 ctx
.program
= program
;
2398 std::vector
<ssa_info
> info(program
->peekAllocationId());
2399 ctx
.info
= info
.data();
2401 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2402 for (Block
& block
: program
->blocks
) {
2403 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2404 label_instruction(ctx
, block
, instr
);
2407 ctx
.uses
= std::move(dead_code_analysis(program
));
2409 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2410 for (Block
& block
: program
->blocks
) {
2411 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2412 combine_instruction(ctx
, block
, instr
);
2415 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2416 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2417 Block
* block
= &(*it
);
2418 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2419 select_instruction(ctx
, *it
);
2422 /* 4. Add literals to instructions */
2423 for (Block
& block
: program
->blocks
) {
2424 ctx
.instructions
.clear();
2425 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2426 apply_literals(ctx
, instr
);
2427 block
.instructions
.swap(ctx
.instructions
);