2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant_32bit
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
94 label_constant_16bit
= 1 << 29,
97 static constexpr uint64_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
98 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
99 static constexpr uint64_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
100 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
101 static constexpr uint32_t val_labels
= label_constant_32bit
| label_constant_64bit
| label_constant_16bit
| label_literal
;
111 ssa_info() : label(0) {}
113 void add_label(Label new_label
)
115 /* Since all labels which use "instr" use it for the same thing
116 * (indicating the defining instruction), there is no need to clear
117 * any other instr labels. */
118 if (new_label
& instr_labels
)
119 label
&= ~(temp_labels
| val_labels
); /* instr, temp and val alias */
121 if (new_label
& temp_labels
) {
122 label
&= ~temp_labels
;
123 label
&= ~(instr_labels
| val_labels
); /* instr, temp and val alias */
126 uint32_t const_labels
= label_literal
| label_constant_32bit
| label_constant_64bit
| label_constant_16bit
;
127 if (new_label
& const_labels
) {
128 label
&= ~val_labels
| const_labels
;
129 label
&= ~(instr_labels
| temp_labels
); /* instr, temp and val alias */
130 } else if (new_label
& val_labels
) {
131 label
&= ~val_labels
;
132 label
&= ~(instr_labels
| temp_labels
); /* instr, temp and val alias */
138 void set_vec(Instruction
* vec
)
140 add_label(label_vec
);
146 return label
& label_vec
;
149 void set_constant(chip_class chip
, uint64_t constant
)
151 Operand
op16((uint16_t)constant
);
152 Operand
op32((uint32_t)constant
);
153 add_label(label_literal
);
156 if (chip
>= GFX8
&& !op16
.isLiteral())
157 add_label(label_constant_16bit
);
159 if (!op32
.isLiteral() || ((uint32_t)constant
== 0x3e22f983 && chip
>= GFX8
))
160 add_label(label_constant_32bit
);
162 if (constant
<= 64) {
163 add_label(label_constant_64bit
);
164 } else if (constant
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
165 add_label(label_constant_64bit
);
166 } else if (constant
== 0x3FE0000000000000) { /* 0.5 */
167 add_label(label_constant_64bit
);
168 } else if (constant
== 0xBFE0000000000000) { /* -0.5 */
169 add_label(label_constant_64bit
);
170 } else if (constant
== 0x3FF0000000000000) { /* 1.0 */
171 add_label(label_constant_64bit
);
172 } else if (constant
== 0xBFF0000000000000) { /* -1.0 */
173 add_label(label_constant_64bit
);
174 } else if (constant
== 0x4000000000000000) { /* 2.0 */
175 add_label(label_constant_64bit
);
176 } else if (constant
== 0xC000000000000000) { /* -2.0 */
177 add_label(label_constant_64bit
);
178 } else if (constant
== 0x4010000000000000) { /* 4.0 */
179 add_label(label_constant_64bit
);
180 } else if (constant
== 0xC010000000000000) { /* -4.0 */
181 add_label(label_constant_64bit
);
184 if (label
& label_constant_64bit
) {
185 val
= Operand(constant
).constantValue();
187 label
&= ~(label_literal
| label_constant_16bit
| label_constant_32bit
);
191 bool is_constant(unsigned bits
)
195 return label
& label_literal
;
197 return label
& label_constant_16bit
;
199 return label
& label_constant_32bit
;
201 return label
& label_constant_64bit
;
206 bool is_literal(unsigned bits
)
208 bool is_lit
= label
& label_literal
;
213 return is_lit
&& ~(label
& label_constant_16bit
);
215 return is_lit
&& ~(label
& label_constant_32bit
);
222 bool is_constant_or_literal(unsigned bits
)
225 return label
& label_constant_64bit
;
227 return label
& label_literal
;
230 void set_abs(Temp abs_temp
)
232 add_label(label_abs
);
238 return label
& label_abs
;
241 void set_neg(Temp neg_temp
)
243 add_label(label_neg
);
249 return label
& label_neg
;
252 void set_neg_abs(Temp neg_abs_temp
)
254 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
258 void set_mul(Instruction
* mul
)
260 add_label(label_mul
);
266 return label
& label_mul
;
269 void set_temp(Temp tmp
)
271 add_label(label_temp
);
277 return label
& label_temp
;
280 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
282 add_label(label_mad
);
283 mad
->pass_flags
= mad_info_idx
;
289 return label
& label_mad
;
292 void set_omod2(Temp def
)
294 add_label(label_omod2
);
300 return label
& label_omod2
;
303 void set_omod4(Temp def
)
305 add_label(label_omod4
);
311 return label
& label_omod4
;
314 void set_omod5(Temp def
)
316 add_label(label_omod5
);
322 return label
& label_omod5
;
325 void set_omod_success(Instruction
* omod_instr
)
327 add_label(label_omod_success
);
331 bool is_omod_success()
333 return label
& label_omod_success
;
336 void set_clamp(Temp def
)
338 add_label(label_clamp
);
344 return label
& label_clamp
;
347 void set_clamp_success(Instruction
* clamp_instr
)
349 add_label(label_clamp_success
);
353 bool is_clamp_success()
355 return label
& label_clamp_success
;
360 add_label(label_undefined
);
365 return label
& label_undefined
;
368 void set_vcc(Temp vcc
)
370 add_label(label_vcc
);
376 return label
& label_vcc
;
379 void set_b2f(Temp val
)
381 add_label(label_b2f
);
387 return label
& label_b2f
;
390 void set_add_sub(Instruction
*add_sub_instr
)
392 add_label(label_add_sub
);
393 instr
= add_sub_instr
;
398 return label
& label_add_sub
;
401 void set_bitwise(Instruction
*bitwise_instr
)
403 add_label(label_bitwise
);
404 instr
= bitwise_instr
;
409 return label
& label_bitwise
;
412 void set_uniform_bitwise()
414 add_label(label_uniform_bitwise
);
417 bool is_uniform_bitwise()
419 return label
& label_uniform_bitwise
;
422 void set_minmax(Instruction
*minmax_instr
)
424 add_label(label_minmax
);
425 instr
= minmax_instr
;
430 return label
& label_minmax
;
433 void set_fcmp(Instruction
*fcmp_instr
)
435 add_label(label_fcmp
);
441 return label
& label_fcmp
;
444 void set_scc_needed()
446 add_label(label_scc_needed
);
451 return label
& label_scc_needed
;
454 void set_scc_invert(Temp scc_inv
)
456 add_label(label_scc_invert
);
462 return label
& label_scc_invert
;
465 void set_uniform_bool(Temp uniform_bool
)
467 add_label(label_uniform_bool
);
471 bool is_uniform_bool()
473 return label
& label_uniform_bool
;
478 add_label(label_vcc_hint
);
483 return label
& label_vcc_hint
;
486 void set_b2i(Temp val
)
488 add_label(label_b2i
);
494 return label
& label_b2i
;
501 std::vector
<aco_ptr
<Instruction
>> instructions
;
503 std::pair
<uint32_t,Temp
> last_literal
;
504 std::vector
<mad_info
> mad_infos
;
505 std::vector
<uint16_t> uses
;
510 aco_opcode unordered
;
511 aco_opcode ordered_swapped
;
512 aco_opcode unordered_swapped
;
518 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
);
520 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
522 if (instr
->operands
[0].isConstant() ||
523 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
526 switch (instr
->opcode
) {
527 case aco_opcode::v_add_f16
:
528 case aco_opcode::v_add_f32
:
529 case aco_opcode::v_mul_f16
:
530 case aco_opcode::v_mul_f32
:
531 case aco_opcode::v_or_b32
:
532 case aco_opcode::v_and_b32
:
533 case aco_opcode::v_xor_b32
:
534 case aco_opcode::v_max_f16
:
535 case aco_opcode::v_max_f32
:
536 case aco_opcode::v_min_f16
:
537 case aco_opcode::v_min_f32
:
538 case aco_opcode::v_max_i32
:
539 case aco_opcode::v_min_i32
:
540 case aco_opcode::v_max_u32
:
541 case aco_opcode::v_min_u32
:
542 case aco_opcode::v_max_i16
:
543 case aco_opcode::v_min_i16
:
544 case aco_opcode::v_max_u16
:
545 case aco_opcode::v_min_u16
:
546 case aco_opcode::v_max_i16_e64
:
547 case aco_opcode::v_min_i16_e64
:
548 case aco_opcode::v_max_u16_e64
:
549 case aco_opcode::v_min_u16_e64
:
551 case aco_opcode::v_sub_f16
:
552 instr
->opcode
= aco_opcode::v_subrev_f16
;
554 case aco_opcode::v_sub_f32
:
555 instr
->opcode
= aco_opcode::v_subrev_f32
;
557 case aco_opcode::v_sub_co_u32
:
558 instr
->opcode
= aco_opcode::v_subrev_co_u32
;
560 case aco_opcode::v_sub_u16
:
561 instr
->opcode
= aco_opcode::v_subrev_u16
;
563 case aco_opcode::v_sub_u32
:
564 instr
->opcode
= aco_opcode::v_subrev_u32
;
568 get_cmp_info(instr
->opcode
, &info
);
569 if (info
.ordered
== instr
->opcode
) {
570 instr
->opcode
= info
.ordered_swapped
;
573 if (info
.unordered
== instr
->opcode
) {
574 instr
->opcode
= info
.unordered_swapped
;
582 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
587 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
590 if (instr
->isDPP() || instr
->isSDWA())
593 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
594 instr
->opcode
!= aco_opcode::v_madak_f32
&&
595 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
596 instr
->opcode
!= aco_opcode::v_madak_f16
&&
597 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
598 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
599 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
600 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
601 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
602 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
603 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
606 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
608 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
609 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
610 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
611 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
612 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
615 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
620 aco_ptr
<Instruction
> tmp
= std::move(instr
);
621 Format format
= asVOP3(tmp
->format
);
622 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
623 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
624 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
625 instr
->definitions
[i
] = tmp
->definitions
[i
];
626 if (instr
->definitions
[i
].isTemp()) {
627 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
628 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
629 info
.instr
= instr
.get();
634 /* only covers special cases */
635 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
638 case aco_opcode::v_interp_p2_f32
:
639 case aco_opcode::v_mac_f32
:
640 case aco_opcode::v_writelane_b32
:
641 case aco_opcode::v_writelane_b32_e64
:
642 case aco_opcode::v_cndmask_b32
:
644 case aco_opcode::s_addk_i32
:
645 case aco_opcode::s_mulk_i32
:
646 case aco_opcode::p_wqm
:
647 case aco_opcode::p_extract_vector
:
648 case aco_opcode::p_split_vector
:
649 case aco_opcode::v_readlane_b32
:
650 case aco_opcode::v_readlane_b32_e64
:
651 case aco_opcode::v_readfirstlane_b32
:
658 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
660 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
661 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
666 /* check constant bus and literal limitations */
667 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
669 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
670 Operand
literal32(s1
);
671 Operand
literal64(s2
);
672 unsigned num_sgprs
= 0;
673 unsigned sgpr
[] = {0, 0};
675 for (unsigned i
= 0; i
< num_operands
; i
++) {
676 Operand op
= operands
[i
];
678 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
679 /* two reads of the same SGPR count as 1 to the limit */
680 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
682 sgpr
[num_sgprs
++] = op
.tempId();
687 } else if (op
.isLiteral()) {
688 if (ctx
.program
->chip_class
< GFX10
)
691 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
693 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
696 /* Any number of 32-bit literals counts as only 1 to the limit. Same
697 * (but separately) for 64-bit literals. */
698 if (op
.size() == 1 && literal32
.isUndefined()) {
701 } else if (op
.size() == 2 && literal64
.isUndefined()) {
714 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
716 Operand op
= instr
->operands
[op_index
];
720 Temp tmp
= op
.getTemp();
721 if (!ctx
.info
[tmp
.id()].is_add_sub())
724 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
726 switch (add_instr
->opcode
) {
727 case aco_opcode::v_add_u32
:
728 case aco_opcode::v_add_co_u32
:
729 case aco_opcode::v_add_co_u32_e64
:
730 case aco_opcode::s_add_i32
:
731 case aco_opcode::s_add_u32
:
737 if (add_instr
->usesModifiers())
740 for (unsigned i
= 0; i
< 2; i
++) {
741 if (add_instr
->operands
[i
].isConstant()) {
742 *offset
= add_instr
->operands
[i
].constantValue();
743 } else if (add_instr
->operands
[i
].isTemp() &&
744 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal(32)) {
745 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
749 if (!add_instr
->operands
[!i
].isTemp())
752 uint32_t offset2
= 0;
753 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
756 *base
= add_instr
->operands
[!i
].getTemp();
764 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
766 if (instr
->format
== Format::PSEUDO
)
767 return instr
->operands
[index
].bytes() * 8u;
768 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
769 return index
== 2 ? 64 : 32;
770 else if (instr
->isVALU() || instr
->isSALU())
771 return instr_info
.operand_size
[(int)instr
->opcode
];
776 Operand
get_constant_op(opt_ctx
&ctx
, ssa_info info
, uint32_t bits
)
779 return Operand((uint8_t)info
.val
);
781 return Operand((uint16_t)info
.val
);
782 // TODO: this functions shouldn't be needed if we store Operand instead of value.
783 Operand
op(info
.val
, bits
== 64);
784 if (info
.is_literal(32) && info
.val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
785 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
789 bool fixed_to_exec(Operand op
)
791 return op
.isFixed() && op
.physReg() == exec
;
794 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
796 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
797 ASSERTED
bool all_const
= false;
798 for (Operand
& op
: instr
->operands
)
799 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal(32));
800 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
803 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
805 if (!instr
->operands
[i
].isTemp())
808 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
809 /* propagate undef */
810 if (info
.is_undefined() && is_phi(instr
))
811 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
812 /* propagate reg->reg of same type */
813 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
814 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
815 info
= ctx
.info
[info
.temp
.id()];
818 /* SALU / PSEUDO: propagate inline constants */
819 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
820 bool is_subdword
= false;
821 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
822 if (instr
->format
== Format::PSEUDO
) {
823 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
824 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
825 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
826 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
827 if (is_subdword
&& ctx
.program
->chip_class
< GFX9
)
831 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
832 instr
->operands
[i
].setTemp(info
.temp
);
833 info
= ctx
.info
[info
.temp
.id()];
834 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
835 /* propagate vgpr if it can take it */
836 switch (instr
->opcode
) {
837 case aco_opcode::p_create_vector
:
838 case aco_opcode::p_split_vector
:
839 case aco_opcode::p_extract_vector
:
840 case aco_opcode::p_phi
: {
841 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
842 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
844 instr
->operands
[i
] = Operand(info
.temp
);
845 info
= ctx
.info
[info
.temp
.id()];
853 unsigned bits
= get_operand_size(instr
, i
);
854 if ((info
.is_constant(bits
) || (!is_subdword
&& info
.is_literal(bits
) && instr
->format
== Format::PSEUDO
)) &&
855 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
856 instr
->operands
[i
] = get_constant_op(ctx
, info
, bits
);
861 /* VALU: propagate neg, abs & inline constants */
862 else if (instr
->isVALU()) {
863 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
864 instr
->operands
[i
].setTemp(info
.temp
);
865 info
= ctx
.info
[info
.temp
.id()];
868 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
869 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
870 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
872 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
875 instr
->operands
[i
] = Operand(info
.temp
);
877 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
879 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
881 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
882 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
883 instr
->operands
[i
].setTemp(info
.temp
);
885 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
886 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
887 instr
->operands
[i
].setTemp(info
.temp
);
889 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
892 instr
->operands
[i
].setTemp(info
.temp
);
894 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
896 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
899 unsigned bits
= get_operand_size(instr
, i
);
900 if (info
.is_constant(bits
) && alu_can_accept_constant(instr
->opcode
, i
)) {
901 Operand op
= get_constant_op(ctx
, info
, bits
);
902 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
903 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
904 instr
->operands
[i
] = op
;
906 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
907 instr
->operands
[i
] = instr
->operands
[0];
908 instr
->operands
[0] = op
;
910 } else if (can_use_VOP3(ctx
, instr
)) {
912 instr
->operands
[i
] = op
;
918 /* MUBUF: propagate constants and combine additions */
919 else if (instr
->format
== Format::MUBUF
) {
920 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
923 while (info
.is_temp())
924 info
= ctx
.info
[info
.temp
.id()];
926 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
927 assert(!mubuf
->idxen
);
928 instr
->operands
[1] = Operand(v1
);
929 mubuf
->offset
+= info
.val
;
930 mubuf
->offen
= false;
932 } else if (i
== 2 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
933 instr
->operands
[2] = Operand((uint32_t) 0);
934 mubuf
->offset
+= info
.val
;
936 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
937 assert(!mubuf
->idxen
);
938 instr
->operands
[1].setTemp(base
);
939 mubuf
->offset
+= offset
;
941 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
942 instr
->operands
[i
].setTemp(base
);
943 mubuf
->offset
+= offset
;
948 /* DS: combine additions */
949 else if (instr
->format
== Format::DS
) {
951 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
954 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
955 if (has_usable_ds_offset
&&
956 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
957 base
.regClass() == instr
->operands
[i
].regClass() &&
958 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
959 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
960 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
961 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
962 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
964 if ((offset
& mask
) == 0 &&
965 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
966 ds
->offset1
+ (offset
>> shifts
) <= 255) {
967 instr
->operands
[i
].setTemp(base
);
968 ds
->offset0
+= offset
>> shifts
;
969 ds
->offset1
+= offset
>> shifts
;
972 if (ds
->offset0
+ offset
<= 65535) {
973 instr
->operands
[i
].setTemp(base
);
974 ds
->offset0
+= offset
;
980 /* SMEM: propagate constants and combine additions */
981 else if (instr
->format
== Format::SMEM
) {
983 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
986 if (i
== 1 && info
.is_constant_or_literal(32) &&
987 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
988 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
989 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
990 instr
->operands
[i
] = Operand(info
.val
);
992 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
993 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
995 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal(32) ||
996 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
1000 smem
->operands
[1] = Operand(offset
);
1001 smem
->operands
.back() = Operand(base
);
1003 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
1004 new_instr
->operands
[0] = smem
->operands
[0];
1005 new_instr
->operands
[1] = Operand(offset
);
1006 if (smem
->definitions
.empty())
1007 new_instr
->operands
[2] = smem
->operands
[2];
1008 new_instr
->operands
.back() = Operand(base
);
1009 if (!smem
->definitions
.empty())
1010 new_instr
->definitions
[0] = smem
->definitions
[0];
1011 new_instr
->can_reorder
= smem
->can_reorder
;
1012 new_instr
->barrier
= smem
->barrier
;
1013 new_instr
->glc
= smem
->glc
;
1014 new_instr
->dlc
= smem
->dlc
;
1015 new_instr
->nv
= smem
->nv
;
1016 new_instr
->disable_wqm
= smem
->disable_wqm
;
1017 instr
.reset(new_instr
);
1018 smem
= static_cast<SMEM_instruction
*>(instr
.get());
1024 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
1025 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1026 /* Flip the branch instruction to get rid of the scc_invert instruction */
1027 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
1028 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1033 /* if this instruction doesn't define anything, return */
1034 if (instr
->definitions
.empty())
1037 switch (instr
->opcode
) {
1038 case aco_opcode::p_create_vector
: {
1039 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
1040 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
1042 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1046 unsigned num_ops
= instr
->operands
.size();
1047 for (const Operand
& op
: instr
->operands
) {
1048 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
1049 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
1051 if (num_ops
!= instr
->operands
.size()) {
1052 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
1053 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
1054 instr
->definitions
[0] = old_vec
->definitions
[0];
1056 for (Operand
& old_op
: old_vec
->operands
) {
1057 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
1058 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
1059 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
1060 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
1061 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
1062 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
1063 instr
->operands
[k
++] = op
;
1066 instr
->operands
[k
++] = old_op
;
1069 assert(k
== num_ops
);
1072 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
1075 case aco_opcode::p_split_vector
: {
1076 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1078 if (info
.is_constant_or_literal(32)) {
1079 uint32_t val
= info
.val
;
1080 for (Definition def
: instr
->definitions
) {
1081 uint32_t mask
= u_bit_consecutive(0, def
.bytes() * 8u);
1082 ctx
.info
[def
.tempId()].set_constant(ctx
.program
->chip_class
, val
& mask
);
1083 val
>>= def
.bytes() * 8u;
1086 } else if (!info
.is_vec()) {
1090 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1091 unsigned split_offset
= 0;
1092 unsigned vec_offset
= 0;
1093 unsigned vec_index
= 0;
1094 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
1095 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
1096 vec_offset
+= vec
->operands
[vec_index
++].bytes();
1098 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
1101 Operand vec_op
= vec
->operands
[vec_index
];
1102 if (vec_op
.isConstant()) {
1103 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(ctx
.program
->chip_class
, vec_op
.constantValue64());
1104 } else if (vec_op
.isUndefined()) {
1105 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1107 assert(vec_op
.isTemp());
1108 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1113 case aco_opcode::p_extract_vector
: { /* mov */
1114 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1115 const unsigned index
= instr
->operands
[1].constantValue();
1116 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1118 if (info
.is_constant_or_literal(32)) {
1119 uint32_t mask
= u_bit_consecutive(0, instr
->definitions
[0].bytes() * 8u);
1120 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, (info
.val
>> (dst_offset
* 8u)) & mask
);
1122 } else if (!info
.is_vec()) {
1126 /* check if we index directly into a vector element */
1127 Instruction
* vec
= info
.instr
;
1128 unsigned offset
= 0;
1130 for (const Operand
& op
: vec
->operands
) {
1131 if (offset
< dst_offset
) {
1132 offset
+= op
.bytes();
1134 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1138 /* convert this extract into a copy instruction */
1139 instr
->opcode
= aco_opcode::p_parallelcopy
;
1140 instr
->operands
.pop_back();
1141 instr
->operands
[0] = op
;
1143 if (op
.isConstant()) {
1144 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, op
.constantValue64());
1145 } else if (op
.isUndefined()) {
1146 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1148 assert(op
.isTemp());
1149 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1155 case aco_opcode::s_mov_b32
: /* propagate */
1156 case aco_opcode::s_mov_b64
:
1157 case aco_opcode::v_mov_b32
:
1158 case aco_opcode::p_as_uniform
:
1159 if (instr
->definitions
[0].isFixed()) {
1160 /* don't copy-propagate copies into fixed registers */
1161 } else if (instr
->usesModifiers()) {
1163 } else if (instr
->operands
[0].isConstant()) {
1164 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, instr
->operands
[0].constantValue64());
1165 } else if (instr
->operands
[0].isTemp()) {
1166 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1168 assert(instr
->operands
[0].isFixed());
1171 case aco_opcode::p_is_helper
:
1172 if (!ctx
.program
->needs_wqm
)
1173 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, 0u);
1175 case aco_opcode::s_movk_i32
: {
1176 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1177 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1178 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1181 case aco_opcode::v_bfrev_b32
:
1182 case aco_opcode::s_brev_b32
: {
1183 if (instr
->operands
[0].isConstant()) {
1184 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1185 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1189 case aco_opcode::s_bfm_b32
: {
1190 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1191 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1192 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1193 uint32_t v
= ((1u << size
) - 1u) << start
;
1194 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1198 case aco_opcode::v_mul_f16
:
1199 case aco_opcode::v_mul_f32
: { /* omod */
1200 /* TODO: try to move the negate/abs modifier to the consumer instead */
1201 if (instr
->usesModifiers())
1204 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1206 for (unsigned i
= 0; i
< 2; i
++) {
1207 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1208 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1209 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1210 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1211 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1212 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1213 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1214 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1215 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1216 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1225 case aco_opcode::v_and_b32
: { /* abs */
1226 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1227 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1228 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1229 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1230 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1232 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1235 case aco_opcode::v_xor_b32
: { /* neg */
1236 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1237 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1238 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1239 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1240 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1241 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1242 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1243 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1244 instr
->opcode
= aco_opcode::v_or_b32
;
1245 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1247 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1251 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1255 case aco_opcode::v_med3_f16
:
1256 case aco_opcode::v_med3_f32
: { /* clamp */
1257 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1258 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1259 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1260 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1264 bool found_zero
= false, found_one
= false;
1265 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1266 for (unsigned i
= 0; i
< 3; i
++)
1268 if (instr
->operands
[i
].constantEquals(0))
1270 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1275 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1276 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1280 case aco_opcode::v_cndmask_b32
:
1281 if (instr
->operands
[0].constantEquals(0) &&
1282 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1283 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1284 else if (instr
->operands
[0].constantEquals(0) &&
1285 instr
->operands
[1].constantEquals(0x3f800000u
))
1286 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1287 else if (instr
->operands
[0].constantEquals(0) &&
1288 instr
->operands
[1].constantEquals(1))
1289 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1291 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1293 case aco_opcode::v_cmp_lg_u32
:
1294 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1295 instr
->operands
[0].constantEquals(0) &&
1296 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1297 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1299 case aco_opcode::p_phi
:
1300 case aco_opcode::p_linear_phi
: {
1301 /* lower_bool_phis() can create phis like this */
1302 bool all_same_temp
= instr
->operands
[0].isTemp();
1303 /* this check is needed when moving uniform loop counters out of a divergent loop */
1305 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1306 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1307 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1308 all_same_temp
= false;
1310 if (all_same_temp
) {
1311 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1313 bool all_undef
= instr
->operands
[0].isUndefined();
1314 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1315 if (!instr
->operands
[i
].isUndefined())
1319 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1323 case aco_opcode::v_add_u32
:
1324 case aco_opcode::v_add_co_u32
:
1325 case aco_opcode::v_add_co_u32_e64
:
1326 case aco_opcode::s_add_i32
:
1327 case aco_opcode::s_add_u32
:
1328 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1330 case aco_opcode::s_not_b32
:
1331 case aco_opcode::s_not_b64
:
1332 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1333 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1334 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1335 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1336 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1337 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1339 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1341 case aco_opcode::s_and_b32
:
1342 case aco_opcode::s_and_b64
:
1343 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1344 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1345 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1346 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1347 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1349 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1350 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1351 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1352 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1357 case aco_opcode::s_or_b32
:
1358 case aco_opcode::s_or_b64
:
1359 case aco_opcode::s_xor_b32
:
1360 case aco_opcode::s_xor_b64
:
1361 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1362 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1364 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1367 case aco_opcode::s_lshl_b32
:
1368 case aco_opcode::v_or_b32
:
1369 case aco_opcode::v_lshlrev_b32
:
1370 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1372 case aco_opcode::v_min_f32
:
1373 case aco_opcode::v_min_f16
:
1374 case aco_opcode::v_min_u32
:
1375 case aco_opcode::v_min_i32
:
1376 case aco_opcode::v_min_u16
:
1377 case aco_opcode::v_min_i16
:
1378 case aco_opcode::v_max_f32
:
1379 case aco_opcode::v_max_f16
:
1380 case aco_opcode::v_max_u32
:
1381 case aco_opcode::v_max_i32
:
1382 case aco_opcode::v_max_u16
:
1383 case aco_opcode::v_max_i16
:
1384 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1387 case aco_opcode::v_cmp_##cmp##_f16:\
1388 case aco_opcode::v_cmp_##cmp##_f32:\
1389 case aco_opcode::v_cmp_##cmp##_f64:\
1390 case aco_opcode::v_cmp_n##cmp##_f16:\
1391 case aco_opcode::v_cmp_n##cmp##_f32:\
1392 case aco_opcode::v_cmp_n##cmp##_f64:
1399 case aco_opcode::v_cmp_o_f16
:
1400 case aco_opcode::v_cmp_u_f16
:
1401 case aco_opcode::v_cmp_o_f32
:
1402 case aco_opcode::v_cmp_u_f32
:
1403 case aco_opcode::v_cmp_o_f64
:
1404 case aco_opcode::v_cmp_u_f64
:
1406 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1408 case aco_opcode::s_cselect_b64
:
1409 case aco_opcode::s_cselect_b32
:
1410 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1411 instr
->operands
[1].constantEquals(0)) {
1412 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1413 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1415 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1416 /* Flip the operands to get rid of the scc_invert instruction */
1417 std::swap(instr
->operands
[0], instr
->operands
[1]);
1418 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1421 case aco_opcode::p_wqm
:
1422 if (instr
->operands
[0].isTemp() &&
1423 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1424 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1432 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
)
1434 info
->ordered
= aco_opcode::num_opcodes
;
1435 info
->unordered
= aco_opcode::num_opcodes
;
1436 info
->ordered_swapped
= aco_opcode::num_opcodes
;
1437 info
->unordered_swapped
= aco_opcode::num_opcodes
;
1439 #define CMP2(ord, unord, ord_swap, unord_swap, sz) \
1440 case aco_opcode::v_cmp_##ord##_f##sz:\
1441 case aco_opcode::v_cmp_n##unord##_f##sz:\
1442 info->ordered = aco_opcode::v_cmp_##ord##_f##sz;\
1443 info->unordered = aco_opcode::v_cmp_n##unord##_f##sz;\
1444 info->ordered_swapped = aco_opcode::v_cmp_##ord_swap##_f##sz;\
1445 info->unordered_swapped = aco_opcode::v_cmp_n##unord_swap##_f##sz;\
1446 info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz : aco_opcode::v_cmp_n##ord##_f##sz;\
1447 info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 : aco_opcode::v_cmp_n##unord##_f32;\
1450 #define CMP(ord, unord, ord_swap, unord_swap) \
1451 CMP2(ord, unord, ord_swap, unord_swap, 16)\
1452 CMP2(ord, unord, ord_swap, unord_swap, 32)\
1453 CMP2(ord, unord, ord_swap, unord_swap, 64)
1454 CMP(lt
, /*n*/ge
, gt
, /*n*/le
)
1455 CMP(eq
, /*n*/lg
, eq
, /*n*/lg
)
1456 CMP(le
, /*n*/gt
, ge
, /*n*/lt
)
1457 CMP(gt
, /*n*/le
, lt
, /*n*/le
)
1458 CMP(lg
, /*n*/eq
, lg
, /*n*/eq
)
1459 CMP(ge
, /*n*/lt
, le
, /*n*/gt
)
1462 #define ORD_TEST(sz) \
1463 case aco_opcode::v_cmp_u_f##sz:\
1464 info->f32 = aco_opcode::v_cmp_u_f32;\
1465 info->inverse = aco_opcode::v_cmp_o_f##sz;\
1468 case aco_opcode::v_cmp_o_f##sz:\
1469 info->f32 = aco_opcode::v_cmp_o_f32;\
1470 info->inverse = aco_opcode::v_cmp_u_f##sz;\
1482 aco_opcode
get_ordered(aco_opcode op
)
1485 return get_cmp_info(op
, &info
) ? info
.ordered
: aco_opcode::num_opcodes
;
1488 aco_opcode
get_unordered(aco_opcode op
)
1491 return get_cmp_info(op
, &info
) ? info
.unordered
: aco_opcode::num_opcodes
;
1494 aco_opcode
get_inverse(aco_opcode op
)
1497 return get_cmp_info(op
, &info
) ? info
.inverse
: aco_opcode::num_opcodes
;
1500 aco_opcode
get_f32_cmp(aco_opcode op
)
1503 return get_cmp_info(op
, &info
) ? info
.f32
: aco_opcode::num_opcodes
;
1506 unsigned get_cmp_bitsize(aco_opcode op
)
1509 return get_cmp_info(op
, &info
) ? info
.size
: 0;
1512 bool is_cmp(aco_opcode op
)
1515 return get_cmp_info(op
, &info
) && info
.ordered
!= aco_opcode::num_opcodes
;
1518 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1520 if (ctx
.info
[tmp
.id()].is_temp())
1521 return ctx
.info
[tmp
.id()].temp
.id();
1526 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1528 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1529 for (const Operand
& op
: instr
->operands
) {
1531 ctx
.uses
[op
.tempId()]--;
1536 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1538 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1540 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1543 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1545 if (instr
->definitions
.size() == 2) {
1546 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1547 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1554 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1555 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1556 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1558 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1560 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1563 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1565 bool neg
[2] = {false, false};
1566 bool abs
[2] = {false, false};
1568 Instruction
*op_instr
[2];
1571 unsigned bitsize
= 0;
1572 for (unsigned i
= 0; i
< 2; i
++) {
1573 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1577 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1578 unsigned op_bitsize
= get_cmp_bitsize(op_instr
[i
]->opcode
);
1580 if (get_f32_cmp(op_instr
[i
]->opcode
) != expected_cmp
)
1582 if (bitsize
&& op_bitsize
!= bitsize
)
1584 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1587 if (op_instr
[i
]->isVOP3()) {
1588 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1589 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1591 neg
[i
] = vop3
->neg
[0];
1592 abs
[i
] = vop3
->abs
[0];
1593 opsel
|= (vop3
->opsel
& 1) << i
;
1596 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1597 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1598 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1602 bitsize
= op_bitsize
;
1605 if (op
[1].type() == RegType::sgpr
)
1606 std::swap(op
[0], op
[1]);
1607 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1608 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1611 ctx
.uses
[op
[0].id()]++;
1612 ctx
.uses
[op
[1].id()]++;
1613 decrease_uses(ctx
, op_instr
[0]);
1614 decrease_uses(ctx
, op_instr
[1]);
1616 aco_opcode new_op
= aco_opcode::num_opcodes
;
1619 new_op
= is_or
? aco_opcode::v_cmp_u_f16
: aco_opcode::v_cmp_o_f16
;
1622 new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1625 new_op
= is_or
? aco_opcode::v_cmp_u_f64
: aco_opcode::v_cmp_o_f64
;
1628 Instruction
*new_instr
;
1629 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1630 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1631 for (unsigned i
= 0; i
< 2; i
++) {
1632 vop3
->neg
[i
] = neg
[i
];
1633 vop3
->abs
[i
] = abs
[i
];
1635 vop3
->opsel
= opsel
;
1636 new_instr
= static_cast<Instruction
*>(vop3
);
1638 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1640 new_instr
->operands
[0] = Operand(op
[0]);
1641 new_instr
->operands
[1] = Operand(op
[1]);
1642 new_instr
->definitions
[0] = instr
->definitions
[0];
1644 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1645 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1647 instr
.reset(new_instr
);
1652 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1653 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1654 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1656 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1658 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1661 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1662 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1664 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1665 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1666 if (!nan_test
|| !cmp
)
1669 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1670 std::swap(nan_test
, cmp
);
1671 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1674 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1677 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1679 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1682 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1683 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1684 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1685 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1686 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1688 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1691 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1692 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1693 decrease_uses(ctx
, nan_test
);
1694 decrease_uses(ctx
, cmp
);
1696 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1697 Instruction
*new_instr
;
1698 if (cmp
->isVOP3()) {
1699 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1700 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1701 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1702 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1703 new_vop3
->clamp
= cmp_vop3
->clamp
;
1704 new_vop3
->omod
= cmp_vop3
->omod
;
1705 new_vop3
->opsel
= cmp_vop3
->opsel
;
1706 new_instr
= new_vop3
;
1708 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1710 new_instr
->operands
[0] = cmp
->operands
[0];
1711 new_instr
->operands
[1] = cmp
->operands
[1];
1712 new_instr
->definitions
[0] = instr
->definitions
[0];
1714 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1715 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1717 instr
.reset(new_instr
);
1722 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1723 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1724 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1726 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1728 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1731 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1733 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1734 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1736 if (!nan_test
|| !cmp
)
1739 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1740 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1741 std::swap(nan_test
, cmp
);
1742 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1745 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1748 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1750 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1753 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1754 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1755 if (prop_nan0
!= prop_nan1
)
1758 if (nan_test
->isVOP3()) {
1759 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1760 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1764 int constant_operand
= -1;
1765 for (unsigned i
= 0; i
< 2; i
++) {
1766 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1767 constant_operand
= !i
;
1771 if (constant_operand
== -1)
1775 if (cmp
->operands
[constant_operand
].isConstant()) {
1776 constant
= cmp
->operands
[constant_operand
].constantValue();
1777 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1778 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1779 unsigned id
= original_temp_id(ctx
, tmp
);
1780 if (!ctx
.info
[id
].is_constant_or_literal(32))
1782 constant
= ctx
.info
[id
].val
;
1788 memcpy(&constantf
, &constant
, 4);
1789 if (isnan(constantf
))
1792 if (cmp
->operands
[0].isTemp())
1793 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1794 if (cmp
->operands
[1].isTemp())
1795 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1796 decrease_uses(ctx
, nan_test
);
1797 decrease_uses(ctx
, cmp
);
1799 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1800 Instruction
*new_instr
;
1801 if (cmp
->isVOP3()) {
1802 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1803 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1804 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1805 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1806 new_vop3
->clamp
= cmp_vop3
->clamp
;
1807 new_vop3
->omod
= cmp_vop3
->omod
;
1808 new_vop3
->opsel
= cmp_vop3
->opsel
;
1809 new_instr
= new_vop3
;
1811 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1813 new_instr
->operands
[0] = cmp
->operands
[0];
1814 new_instr
->operands
[1] = cmp
->operands
[1];
1815 new_instr
->definitions
[0] = instr
->definitions
[0];
1817 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1818 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1820 instr
.reset(new_instr
);
1825 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1826 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1828 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1830 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1832 if (!instr
->operands
[0].isTemp())
1835 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1839 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1840 if (new_opcode
== aco_opcode::num_opcodes
)
1843 if (cmp
->operands
[0].isTemp())
1844 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1845 if (cmp
->operands
[1].isTemp())
1846 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1847 decrease_uses(ctx
, cmp
);
1849 Instruction
*new_instr
;
1850 if (cmp
->isVOP3()) {
1851 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1852 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1853 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1854 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1855 new_vop3
->clamp
= cmp_vop3
->clamp
;
1856 new_vop3
->omod
= cmp_vop3
->omod
;
1857 new_vop3
->opsel
= cmp_vop3
->opsel
;
1858 new_instr
= new_vop3
;
1860 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1862 new_instr
->operands
[0] = cmp
->operands
[0];
1863 new_instr
->operands
[1] = cmp
->operands
[1];
1864 new_instr
->definitions
[0] = instr
->definitions
[0];
1866 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1867 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1869 instr
.reset(new_instr
);
1874 /* op1(op2(1, 2), 0) if swap = false
1875 * op1(0, op2(1, 2)) if swap = true */
1876 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1877 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1878 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1879 bool *op1_clamp
, uint8_t *op1_omod
,
1880 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1883 if (op1_instr
->opcode
!= op1
)
1886 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1887 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1889 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1892 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1893 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1895 /* don't support inbetween clamp/omod */
1896 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1899 /* get operands and modifiers and check inbetween modifiers */
1900 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1901 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1904 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1905 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1909 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1910 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1913 if (inbetween_opsel
)
1914 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1915 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1919 shuffle
[shuffle_str
[0] - '0'] = 0;
1920 shuffle
[shuffle_str
[1] - '0'] = 1;
1921 shuffle
[shuffle_str
[2] - '0'] = 2;
1923 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1924 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1925 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1926 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1927 *opsel
|= 1 << shuffle
[0];
1929 for (unsigned i
= 0; i
< 2; i
++) {
1930 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1931 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1932 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1933 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1934 *opsel
|= 1 << shuffle
[i
+ 1];
1937 /* check operands */
1938 if (!check_vop3_operands(ctx
, 3, operands
))
1944 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1945 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1946 bool clamp
, unsigned omod
)
1948 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1949 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1950 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1951 new_instr
->clamp
= clamp
;
1952 new_instr
->omod
= omod
;
1953 new_instr
->opsel
= opsel
;
1954 new_instr
->operands
[0] = operands
[0];
1955 new_instr
->operands
[1] = operands
[1];
1956 new_instr
->operands
[2] = operands
[2];
1957 new_instr
->definitions
[0] = instr
->definitions
[0];
1958 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1960 instr
.reset(new_instr
);
1963 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1965 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1966 (label_omod_success
| label_clamp_success
);
1968 for (unsigned swap
= 0; swap
< 2; swap
++) {
1969 if (!((1 << swap
) & ops
))
1972 Operand operands
[3];
1973 bool neg
[3], abs
[3], clamp
;
1974 uint8_t opsel
= 0, omod
= 0;
1975 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1976 instr
.get(), swap
, shuffle
,
1977 operands
, neg
, abs
, &opsel
,
1978 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1979 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1980 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1981 if (omod_clamp
& label_omod_success
)
1982 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1983 if (omod_clamp
& label_clamp_success
)
1984 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1991 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1993 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1996 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1997 (label_omod_success
| label_clamp_success
);
1999 /* min(-max(a, b), c) -> min3(-a, -b, c) *
2000 * max(-min(a, b), c) -> max3(-a, -b, c) */
2001 for (unsigned swap
= 0; swap
< 2; swap
++) {
2002 Operand operands
[3];
2003 bool neg
[3], abs
[3], clamp
;
2004 uint8_t opsel
= 0, omod
= 0;
2006 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
2007 instr
.get(), swap
, "012",
2008 operands
, neg
, abs
, &opsel
,
2009 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
2011 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2014 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2015 if (omod_clamp
& label_omod_success
)
2016 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2017 if (omod_clamp
& label_clamp_success
)
2018 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2025 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
2026 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
2027 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
2028 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
2029 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
2030 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
2031 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2034 if (!instr
->operands
[0].isTemp())
2036 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
2039 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
2042 switch (op2_instr
->opcode
) {
2043 case aco_opcode::s_and_b32
:
2044 case aco_opcode::s_or_b32
:
2045 case aco_opcode::s_xor_b32
:
2046 case aco_opcode::s_and_b64
:
2047 case aco_opcode::s_or_b64
:
2048 case aco_opcode::s_xor_b64
:
2054 /* create instruction */
2055 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
2056 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
2057 ctx
.uses
[instr
->operands
[0].tempId()]--;
2058 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
2060 switch (op2_instr
->opcode
) {
2061 case aco_opcode::s_and_b32
:
2062 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
2064 case aco_opcode::s_or_b32
:
2065 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
2067 case aco_opcode::s_xor_b32
:
2068 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
2070 case aco_opcode::s_and_b64
:
2071 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
2073 case aco_opcode::s_or_b64
:
2074 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
2076 case aco_opcode::s_xor_b64
:
2077 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
2086 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
2087 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
2088 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
2089 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
2090 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2092 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
2095 for (unsigned i
= 0; i
< 2; i
++) {
2096 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2097 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
2099 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
2102 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2103 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2106 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2107 instr
->operands
[0] = instr
->operands
[!i
];
2108 instr
->operands
[1] = op2_instr
->operands
[0];
2109 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2111 switch (instr
->opcode
) {
2112 case aco_opcode::s_and_b32
:
2113 instr
->opcode
= aco_opcode::s_andn2_b32
;
2115 case aco_opcode::s_or_b32
:
2116 instr
->opcode
= aco_opcode::s_orn2_b32
;
2118 case aco_opcode::s_and_b64
:
2119 instr
->opcode
= aco_opcode::s_andn2_b64
;
2121 case aco_opcode::s_or_b64
:
2122 instr
->opcode
= aco_opcode::s_orn2_b64
;
2133 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2134 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2136 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
2139 for (unsigned i
= 0; i
< 2; i
++) {
2140 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2141 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
2142 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
2144 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
2147 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2148 if (shift
< 1 || shift
> 4)
2151 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2152 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2155 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2156 instr
->operands
[1] = instr
->operands
[!i
];
2157 instr
->operands
[0] = op2_instr
->operands
[0];
2158 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2160 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2161 aco_opcode::s_lshl2_add_u32
,
2162 aco_opcode::s_lshl3_add_u32
,
2163 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2170 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2172 if (instr
->usesModifiers())
2175 for (unsigned i
= 0; i
< 2; i
++) {
2176 if (!((1 << i
) & ops
))
2178 if (instr
->operands
[i
].isTemp() &&
2179 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2180 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2182 aco_ptr
<Instruction
> new_instr
;
2183 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2184 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2185 } else if (ctx
.program
->chip_class
>= GFX10
||
2186 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2187 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2191 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2192 new_instr
->definitions
[0] = instr
->definitions
[0];
2193 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2194 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2195 new_instr
->definitions
[1].setHint(vcc
);
2196 new_instr
->operands
[0] = Operand(0u);
2197 new_instr
->operands
[1] = instr
->operands
[!i
];
2198 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2199 instr
= std::move(new_instr
);
2200 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2208 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2211 #define MINMAX(type, gfx9) \
2212 case aco_opcode::v_min_##type:\
2213 case aco_opcode::v_max_##type:\
2214 case aco_opcode::v_med3_##type:\
2215 *min = aco_opcode::v_min_##type;\
2216 *max = aco_opcode::v_max_##type;\
2217 *med3 = aco_opcode::v_med3_##type;\
2218 *min3 = aco_opcode::v_min3_##type;\
2219 *max3 = aco_opcode::v_max3_##type;\
2220 *some_gfx9_only = gfx9;\
2234 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2235 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2236 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2237 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2239 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2240 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2241 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2242 aco_opcode other_op
;
2243 if (instr
->opcode
== min
)
2245 else if (instr
->opcode
== max
)
2250 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2251 (label_omod_success
| label_clamp_success
);
2253 for (unsigned swap
= 0; swap
< 2; swap
++) {
2254 Operand operands
[3];
2255 bool neg
[3], abs
[3], clamp
;
2256 uint8_t opsel
= 0, omod
= 0;
2257 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2258 "012", operands
, neg
, abs
, &opsel
,
2259 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2260 int const0_idx
= -1, const1_idx
= -1;
2261 uint32_t const0
= 0, const1
= 0;
2262 for (int i
= 0; i
< 3; i
++) {
2264 if (operands
[i
].isConstant()) {
2265 val
= operands
[i
].constantValue();
2266 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal(32)) {
2267 val
= ctx
.info
[operands
[i
].tempId()].val
;
2271 if (const0_idx
>= 0) {
2279 if (const0_idx
< 0 || const1_idx
< 0)
2282 if (opsel
& (1 << const0_idx
))
2284 if (opsel
& (1 << const1_idx
))
2287 int lower_idx
= const0_idx
;
2289 case aco_opcode::v_min_f32
:
2290 case aco_opcode::v_min_f16
: {
2291 float const0_f
, const1_f
;
2292 if (min
== aco_opcode::v_min_f32
) {
2293 memcpy(&const0_f
, &const0
, 4);
2294 memcpy(&const1_f
, &const1
, 4);
2296 const0_f
= _mesa_half_to_float(const0
);
2297 const1_f
= _mesa_half_to_float(const1
);
2299 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2300 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2301 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2302 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2303 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2306 case aco_opcode::v_min_u32
: {
2307 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2310 case aco_opcode::v_min_u16
: {
2311 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2314 case aco_opcode::v_min_i32
: {
2315 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2316 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2317 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2320 case aco_opcode::v_min_i16
: {
2321 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2322 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2323 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2329 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2331 if (instr
->opcode
== min
) {
2332 if (upper_idx
!= 0 || lower_idx
== 0)
2335 if (upper_idx
== 0 || lower_idx
!= 0)
2339 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2340 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2341 if (omod_clamp
& label_omod_success
)
2342 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2343 if (omod_clamp
& label_clamp_success
)
2344 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2354 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2356 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2357 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2358 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2360 /* find candidates and create the set of sgprs already read */
2361 unsigned sgpr_ids
[2] = {0, 0};
2362 uint32_t operand_mask
= 0;
2363 bool has_literal
= false;
2364 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2365 if (instr
->operands
[i
].isLiteral())
2367 if (!instr
->operands
[i
].isTemp())
2369 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2370 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2371 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2373 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2374 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2375 operand_mask
|= 1u << i
;
2377 unsigned max_sgprs
= 1;
2378 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2383 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2385 /* keep on applying sgprs until there is nothing left to be done */
2386 while (operand_mask
) {
2387 uint32_t sgpr_idx
= 0;
2388 uint32_t sgpr_info_id
= 0;
2389 uint32_t mask
= operand_mask
;
2392 unsigned i
= u_bit_scan(&mask
);
2393 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2394 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2396 sgpr_info_id
= instr
->operands
[i
].tempId();
2399 operand_mask
&= ~(1u << sgpr_idx
);
2401 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2402 * definitively beneficial.
2403 * TODO: this is too conservative because later the use count could be reduced to 1 */
2404 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2407 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2408 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2409 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2412 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2413 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2414 } else if (can_swap_operands(instr
)) {
2415 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2416 instr
->operands
[0] = Operand(sgpr
);
2417 /* swap bits using a 4-entry LUT */
2418 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2419 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2420 } else if (can_use_VOP3(ctx
, instr
)) {
2421 to_VOP3(ctx
, instr
);
2422 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2428 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2429 ctx
.uses
[sgpr_info_id
]--;
2430 ctx
.uses
[sgpr
.id()]++;
2434 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2436 /* check if we could apply omod on predecessor */
2437 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2438 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2439 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2441 unsigned idx
= op0
? 0 : 1;
2442 /* omod was successfully applied */
2443 /* if the omod instruction is v_mad, we also have to change the original add */
2444 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2445 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].instr
->pass_flags
].add_instr
.get();
2446 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2447 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2448 add_instr
->definitions
[0] = instr
->definitions
[0];
2451 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2452 /* check if we have an additional clamp modifier */
2453 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2454 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2455 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2456 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2458 /* change definition ssa-id of modified instruction */
2459 omod_instr
->definitions
[0] = instr
->definitions
[0];
2461 /* change the definition of instr to something unused, e.g. the original omod def */
2462 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2463 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2466 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2467 /* in all other cases, label this instruction as option for multiply-add */
2468 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2472 /* check if we could apply clamp on predecessor */
2473 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2474 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2476 bool found_zero
= false, found_one
= false;
2477 for (unsigned i
= 0; i
< 3; i
++)
2479 if (instr
->operands
[i
].constantEquals(0))
2481 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2486 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2487 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2488 /* clamp was successfully applied */
2489 /* if the clamp instruction is v_mad, we also have to change the original add */
2490 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2491 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].instr
->pass_flags
].add_instr
.get();
2492 add_instr
->definitions
[0] = instr
->definitions
[0];
2494 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2495 /* change definition ssa-id of modified instruction */
2496 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2498 /* change the definition of instr to something unused, e.g. the original omod def */
2499 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2500 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2505 /* omod has no effect if denormals are enabled */
2506 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2507 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2508 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2509 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2510 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2511 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2512 to_VOP3(ctx
, instr
);
2513 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2514 def_info
.set_omod_success(instr
.get());
2515 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2516 to_VOP3(ctx
, instr
);
2517 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2518 def_info
.set_omod_success(instr
.get());
2519 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2520 to_VOP3(ctx
, instr
);
2521 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2522 def_info
.set_omod_success(instr
.get());
2523 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2524 to_VOP3(ctx
, instr
);
2525 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2526 def_info
.set_clamp_success(instr
.get());
2533 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2534 // this would mean that we'd have to fix the instruction uses while value propagation
2536 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2538 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2541 if (instr
->isVALU()) {
2542 if (can_apply_sgprs(instr
))
2543 apply_sgprs(ctx
, instr
);
2544 if (apply_omod_clamp(ctx
, block
, instr
))
2548 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2549 instr
->definitions
[0].setHint(vcc
);
2552 /* TODO: There are still some peephole optimizations that could be done:
2553 * - abs(a - b) -> s_absdiff_i32
2554 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2555 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2556 * These aren't probably too interesting though.
2557 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2558 * probably more useful than the previously mentioned optimizations.
2559 * The various comparison optimizations also currently only work with 32-bit
2562 /* neg(mul(a, b)) -> mul(neg(a), b) */
2563 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2564 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2566 if (!ctx
.info
[val
.id()].is_mul())
2569 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2571 if (mul_instr
->operands
[0].isLiteral())
2573 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2576 /* convert to mul(neg(a), b) */
2577 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2578 Definition def
= instr
->definitions
[0];
2579 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2580 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2581 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2582 instr
->operands
[0] = mul_instr
->operands
[0];
2583 instr
->operands
[1] = mul_instr
->operands
[1];
2584 instr
->definitions
[0] = def
;
2585 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2586 if (mul_instr
->isVOP3()) {
2587 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2588 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2589 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2590 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2591 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2592 new_mul
->omod
= mul
->omod
;
2594 new_mul
->neg
[0] ^= true;
2595 new_mul
->clamp
= false;
2597 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2601 /* combine mul+add -> mad */
2602 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2603 instr
->opcode
== aco_opcode::v_sub_f32
||
2604 instr
->opcode
== aco_opcode::v_subrev_f32
;
2605 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2606 instr
->opcode
== aco_opcode::v_sub_f16
||
2607 instr
->opcode
== aco_opcode::v_subrev_f16
;
2608 if (mad16
|| mad32
) {
2609 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2610 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2611 if (need_fma
&& instr
->definitions
[0].isPrecise())
2613 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2616 uint32_t uses_src0
= UINT32_MAX
;
2617 uint32_t uses_src1
= UINT32_MAX
;
2618 Instruction
* mul_instr
= nullptr;
2619 unsigned add_op_idx
;
2620 /* check if any of the operands is a multiplication */
2621 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2622 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2623 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2624 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2625 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2626 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2628 /* find the 'best' mul instruction to combine with the add */
2629 if (uses_src0
< uses_src1
) {
2630 mul_instr
= op0_info
->instr
;
2632 } else if (uses_src1
< uses_src0
) {
2633 mul_instr
= op1_info
->instr
;
2635 } else if (uses_src0
!= UINT32_MAX
) {
2636 /* tiebreaker: quite random what to pick */
2637 if (op0_info
->instr
->operands
[0].isLiteral()) {
2638 mul_instr
= op1_info
->instr
;
2641 mul_instr
= op0_info
->instr
;
2646 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2647 bool neg
[3] = {false, false, false};
2648 bool abs
[3] = {false, false, false};
2651 op
[0] = mul_instr
->operands
[0];
2652 op
[1] = mul_instr
->operands
[1];
2653 op
[2] = instr
->operands
[add_op_idx
];
2654 // TODO: would be better to check this before selecting a mul instr?
2655 if (!check_vop3_operands(ctx
, 3, op
))
2658 if (mul_instr
->isVOP3()) {
2659 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2660 neg
[0] = vop3
->neg
[0];
2661 neg
[1] = vop3
->neg
[1];
2662 abs
[0] = vop3
->abs
[0];
2663 abs
[1] = vop3
->abs
[1];
2664 /* we cannot use these modifiers between mul and add */
2665 if (vop3
->clamp
|| vop3
->omod
)
2669 /* convert to mad */
2670 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2671 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2673 ctx
.uses
[op
[0].tempId()]++;
2675 ctx
.uses
[op
[1].tempId()]++;
2678 if (instr
->isVOP3()) {
2679 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2680 neg
[2] = vop3
->neg
[add_op_idx
];
2681 abs
[2] = vop3
->abs
[add_op_idx
];
2683 clamp
= vop3
->clamp
;
2684 /* abs of the multiplication result */
2685 if (vop3
->abs
[1 - add_op_idx
]) {
2691 /* neg of the multiplication result */
2692 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2694 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2695 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2696 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2697 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2699 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2701 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2702 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2704 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2705 for (unsigned i
= 0; i
< 3; i
++)
2707 mad
->operands
[i
] = op
[i
];
2708 mad
->neg
[i
] = neg
[i
];
2709 mad
->abs
[i
] = abs
[i
];
2713 mad
->definitions
[0] = instr
->definitions
[0];
2715 /* mark this ssa_def to be re-checked for profitability and literals */
2716 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2717 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2718 instr
.reset(mad
.release());
2722 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2723 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2724 for (unsigned i
= 0; i
< 2; i
++) {
2725 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2726 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2727 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2728 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2729 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2731 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2732 new_instr
->operands
[0] = Operand(0u);
2733 new_instr
->operands
[1] = instr
->operands
[!i
];
2734 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2735 new_instr
->definitions
[0] = instr
->definitions
[0];
2736 instr
.reset(new_instr
.release());
2737 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2741 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2742 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2743 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2744 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2745 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2746 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2747 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2748 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2749 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2750 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2751 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2752 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2753 else if (ctx
.program
->chip_class
>= GFX9
) {
2754 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2755 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2756 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2757 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2758 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2759 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2760 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2762 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2763 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2764 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2765 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2766 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2767 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2768 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2769 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2770 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2771 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2772 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2773 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2774 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2775 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2776 combine_salu_lshl_add(ctx
, instr
);
2777 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2778 combine_salu_not_bitwise(ctx
, instr
);
2779 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2780 if (combine_inverse_comparison(ctx
, instr
)) ;
2781 else combine_salu_not_bitwise(ctx
, instr
);
2782 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2783 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2784 if (combine_ordering_test(ctx
, instr
)) ;
2785 else if (combine_comparison_ordering(ctx
, instr
)) ;
2786 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2787 else combine_salu_n2(ctx
, instr
);
2789 aco_opcode min
, max
, min3
, max3
, med3
;
2790 bool some_gfx9_only
;
2791 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2792 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2793 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2794 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2799 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2801 switch (instr
->opcode
) {
2802 case aco_opcode::s_and_b32
:
2803 case aco_opcode::s_and_b64
:
2804 instr
->opcode
= aco_opcode::s_and_b32
;
2806 case aco_opcode::s_or_b32
:
2807 case aco_opcode::s_or_b64
:
2808 instr
->opcode
= aco_opcode::s_or_b32
;
2810 case aco_opcode::s_xor_b32
:
2811 case aco_opcode::s_xor_b64
:
2812 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2815 /* Don't transform other instructions. They are very unlikely to appear here. */
2819 for (Operand
&op
: instr
->operands
) {
2820 ctx
.uses
[op
.tempId()]--;
2822 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2823 /* Just use the uniform boolean temp. */
2824 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2825 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2826 /* Use the SCC definition of the predecessor instruction.
2827 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2828 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2830 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2831 assert(pred_instr
->definitions
.size() >= 2);
2832 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2833 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2835 unreachable("Invalid operand on uniform bitwise instruction.");
2838 ctx
.uses
[op
.tempId()]++;
2841 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2842 assert(instr
->operands
[0].regClass() == s1
);
2843 assert(instr
->operands
[1].regClass() == s1
);
2847 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2849 const uint32_t threshold
= 4;
2851 if (is_dead(ctx
.uses
, instr
.get())) {
2856 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2857 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2858 unsigned num_used
= 0;
2860 unsigned split_offset
= 0;
2861 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2862 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2865 split_offset
= offset
;
2869 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2870 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2871 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2875 for (Operand
& vec_op
: vec
->operands
) {
2876 if (off
== split_offset
) {
2880 off
+= vec_op
.bytes();
2882 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2883 ctx
.uses
[instr
->operands
[0].tempId()]--;
2884 for (Operand
& vec_op
: vec
->operands
) {
2885 if (vec_op
.isTemp())
2886 ctx
.uses
[vec_op
.tempId()]--;
2889 ctx
.uses
[op
.tempId()]++;
2891 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2892 extract
->operands
[0] = op
;
2893 extract
->definitions
[0] = instr
->definitions
[idx
];
2894 instr
.reset(extract
.release());
2900 if (!done
&& num_used
== 1 &&
2901 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2902 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2903 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2904 extract
->operands
[0] = instr
->operands
[0];
2905 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2906 extract
->definitions
[0] = instr
->definitions
[idx
];
2907 instr
.reset(extract
.release());
2911 mad_info
* mad_info
= NULL
;
2912 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2913 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].instr
->pass_flags
];
2914 /* re-check mad instructions */
2915 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2916 ctx
.uses
[mad_info
->mul_temp_id
]++;
2917 if (instr
->operands
[0].isTemp())
2918 ctx
.uses
[instr
->operands
[0].tempId()]--;
2919 if (instr
->operands
[1].isTemp())
2920 ctx
.uses
[instr
->operands
[1].tempId()]--;
2921 instr
.swap(mad_info
->add_instr
);
2924 /* check literals */
2925 else if (!instr
->usesModifiers()) {
2926 /* FMA can only take literals on GFX10+ */
2927 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2928 ctx
.program
->chip_class
< GFX10
)
2931 bool sgpr_used
= false;
2932 uint32_t literal_idx
= 0;
2933 uint32_t literal_uses
= UINT32_MAX
;
2934 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2936 if (instr
->operands
[i
].isConstant() && i
> 0) {
2937 literal_uses
= UINT32_MAX
;
2940 if (!instr
->operands
[i
].isTemp())
2942 unsigned bits
= get_operand_size(instr
, i
);
2943 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2944 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2945 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
)) {
2946 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2949 literal_uses
= UINT32_MAX
;
2952 /* don't break because we still need to check constants */
2953 } else if (!sgpr_used
&&
2954 ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
) &&
2955 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2956 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2961 /* Limit the number of literals to apply to not increase the code
2962 * size too much, but always apply literals for v_mad->v_madak
2963 * because both instructions are 64-bit and this doesn't increase
2965 * TODO: try to apply the literals earlier to lower the number of
2966 * uses below threshold
2968 if (literal_uses
< threshold
|| literal_idx
== 2) {
2969 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2970 mad_info
->check_literal
= true;
2971 mad_info
->literal_idx
= literal_idx
;
2977 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2978 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2979 instr
->operands
.size() &&
2980 instr
->operands
[0].isTemp()) {
2981 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2983 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2984 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2985 instr
->operands
[2].isTemp()) {
2986 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2989 /* check for literals */
2990 if (!instr
->isSALU() && !instr
->isVALU())
2993 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2994 if (instr
->definitions
.size() &&
2995 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2996 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2997 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2999 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
3000 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
3001 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
3002 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
3003 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
3004 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
3010 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
3011 return; /* some encodings can't ever take literals */
3013 /* we do not apply the literals yet as we don't know if it is profitable */
3014 Operand
current_literal(s1
);
3016 unsigned literal_id
= 0;
3017 unsigned literal_uses
= UINT32_MAX
;
3018 Operand
literal(s1
);
3019 unsigned num_operands
= 1;
3020 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
3021 num_operands
= instr
->operands
.size();
3022 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
3023 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
3026 unsigned sgpr_ids
[2] = {0, 0};
3027 bool is_literal_sgpr
= false;
3030 /* choose a literal to apply */
3031 for (unsigned i
= 0; i
< num_operands
; i
++) {
3032 Operand op
= instr
->operands
[i
];
3033 unsigned bits
= get_operand_size(instr
, i
);
3035 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
3036 op
.tempId() != sgpr_ids
[0])
3037 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
3039 if (op
.isLiteral()) {
3040 current_literal
= op
;
3042 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal(bits
)) {
3046 if (!alu_can_accept_constant(instr
->opcode
, i
))
3049 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
3050 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
3052 literal
= Operand(ctx
.info
[op
.tempId()].val
);
3053 literal_uses
= ctx
.uses
[op
.tempId()];
3054 literal_id
= op
.tempId();
3057 mask
|= (op
.tempId() == literal_id
) << i
;
3061 /* don't go over the constant bus limit */
3062 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
3063 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
3064 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
3065 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
3066 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
3067 const_bus_limit
= 2;
3069 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
3070 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
3073 if (literal_id
&& literal_uses
< threshold
&&
3074 (current_literal
.isUndefined() ||
3075 (current_literal
.size() == literal
.size() &&
3076 current_literal
.constantValue() == literal
.constantValue()))) {
3077 /* mark the literal to be applied */
3079 unsigned i
= u_bit_scan(&mask
);
3080 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
3081 ctx
.uses
[instr
->operands
[i
].tempId()]--;
3087 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
3089 /* Cleanup Dead Instructions */
3093 /* apply literals on MAD */
3094 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
3095 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].instr
->pass_flags
];
3096 if (info
->check_literal
&&
3097 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
3098 aco_ptr
<Instruction
> new_mad
;
3100 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
3101 if (instr
->opcode
== aco_opcode::v_fma_f32
)
3102 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
3103 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
3104 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
3105 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
3106 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
3108 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
3109 if (info
->literal_idx
== 2) { /* add literal -> madak */
3110 new_mad
->operands
[0] = instr
->operands
[0];
3111 new_mad
->operands
[1] = instr
->operands
[1];
3112 } else { /* mul literal -> madmk */
3113 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
3114 new_mad
->operands
[1] = instr
->operands
[2];
3116 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
3117 new_mad
->definitions
[0] = instr
->definitions
[0];
3118 ctx
.instructions
.emplace_back(std::move(new_mad
));
3123 /* apply literals on other SALU/VALU */
3124 if (instr
->isSALU() || instr
->isVALU()) {
3125 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
3126 Operand op
= instr
->operands
[i
];
3127 unsigned bits
= get_operand_size(instr
, i
);
3128 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal(bits
) && ctx
.uses
[op
.tempId()] == 0) {
3129 Operand
literal(ctx
.info
[op
.tempId()].val
);
3130 if (instr
->isVALU() && i
> 0)
3131 to_VOP3(ctx
, instr
);
3132 instr
->operands
[i
] = literal
;
3137 ctx
.instructions
.emplace_back(std::move(instr
));
3141 void optimize(Program
* program
)
3144 ctx
.program
= program
;
3145 std::vector
<ssa_info
> info(program
->peekAllocationId());
3146 ctx
.info
= info
.data();
3148 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
3149 for (Block
& block
: program
->blocks
) {
3150 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3151 label_instruction(ctx
, block
, instr
);
3154 ctx
.uses
= dead_code_analysis(program
);
3156 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3157 for (Block
& block
: program
->blocks
) {
3158 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3159 combine_instruction(ctx
, block
, instr
);
3162 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3163 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3164 Block
* block
= &(*it
);
3165 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3166 select_instruction(ctx
, *it
);
3169 /* 4. Add literals to instructions */
3170 for (Block
& block
: program
->blocks
) {
3171 ctx
.instructions
.clear();
3172 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3173 apply_literals(ctx
, instr
);
3174 block
.instructions
.swap(ctx
.instructions
);