2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant_32bit
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
94 label_constant_16bit
= 1 << 29,
97 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
98 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
99 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
100 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
101 static constexpr uint32_t val_labels
= label_constant_32bit
| label_constant_64bit
| label_constant_16bit
| label_literal
| label_mad
;
111 ssa_info() : label(0) {}
113 void add_label(Label new_label
)
115 /* Since all labels which use "instr" use it for the same thing
116 * (indicating the defining instruction), there is no need to clear
117 * any other instr labels. */
118 if (new_label
& instr_labels
)
119 label
&= ~temp_labels
; /* instr and temp alias */
121 if (new_label
& temp_labels
) {
122 label
&= ~temp_labels
;
123 label
&= ~instr_labels
; /* instr and temp alias */
126 uint32_t const_labels
= label_literal
| label_constant_32bit
| label_constant_64bit
| label_constant_16bit
;
127 if (new_label
& const_labels
)
128 label
&= ~val_labels
| const_labels
;
129 else if (new_label
& val_labels
)
130 label
&= ~val_labels
;
135 void set_vec(Instruction
* vec
)
137 add_label(label_vec
);
143 return label
& label_vec
;
146 void set_constant(chip_class chip
, uint64_t constant
)
148 Operand
op16((uint16_t)constant
);
149 Operand
op32((uint32_t)constant
);
150 add_label(label_literal
);
153 if (chip
>= GFX8
&& !op16
.isLiteral())
154 add_label(label_constant_16bit
);
156 if (!op32
.isLiteral() || ((uint32_t)constant
== 0x3e22f983 && chip
>= GFX8
))
157 add_label(label_constant_32bit
);
159 if (constant
<= 64) {
160 add_label(label_constant_64bit
);
161 } else if (constant
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
162 add_label(label_constant_64bit
);
163 } else if (constant
== 0x3FE0000000000000) { /* 0.5 */
164 add_label(label_constant_64bit
);
165 } else if (constant
== 0xBFE0000000000000) { /* -0.5 */
166 add_label(label_constant_64bit
);
167 } else if (constant
== 0x3FF0000000000000) { /* 1.0 */
168 add_label(label_constant_64bit
);
169 } else if (constant
== 0xBFF0000000000000) { /* -1.0 */
170 add_label(label_constant_64bit
);
171 } else if (constant
== 0x4000000000000000) { /* 2.0 */
172 add_label(label_constant_64bit
);
173 } else if (constant
== 0xC000000000000000) { /* -2.0 */
174 add_label(label_constant_64bit
);
175 } else if (constant
== 0x4010000000000000) { /* 4.0 */
176 add_label(label_constant_64bit
);
177 } else if (constant
== 0xC010000000000000) { /* -4.0 */
178 add_label(label_constant_64bit
);
181 if (label
& label_constant_64bit
) {
182 val
= Operand(constant
).constantValue();
184 label
&= ~(label_literal
| label_constant_16bit
| label_constant_32bit
);
188 bool is_constant(unsigned bits
)
192 return label
& label_literal
;
194 return label
& label_constant_16bit
;
196 return label
& label_constant_32bit
;
198 return label
& label_constant_64bit
;
203 bool is_literal(unsigned bits
)
205 bool is_lit
= label
& label_literal
;
210 return is_lit
&& ~(label
& label_constant_16bit
);
212 return is_lit
&& ~(label
& label_constant_32bit
);
219 bool is_constant_or_literal(unsigned bits
)
222 return label
& label_constant_64bit
;
224 return label
& label_literal
;
227 void set_abs(Temp abs_temp
)
229 add_label(label_abs
);
235 return label
& label_abs
;
238 void set_neg(Temp neg_temp
)
240 add_label(label_neg
);
246 return label
& label_neg
;
249 void set_neg_abs(Temp neg_abs_temp
)
251 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
255 void set_mul(Instruction
* mul
)
257 add_label(label_mul
);
263 return label
& label_mul
;
266 void set_temp(Temp tmp
)
268 add_label(label_temp
);
274 return label
& label_temp
;
277 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
279 add_label(label_mad
);
286 return label
& label_mad
;
289 void set_omod2(Temp def
)
291 add_label(label_omod2
);
297 return label
& label_omod2
;
300 void set_omod4(Temp def
)
302 add_label(label_omod4
);
308 return label
& label_omod4
;
311 void set_omod5(Temp def
)
313 add_label(label_omod5
);
319 return label
& label_omod5
;
322 void set_omod_success(Instruction
* omod_instr
)
324 add_label(label_omod_success
);
328 bool is_omod_success()
330 return label
& label_omod_success
;
333 void set_clamp(Temp def
)
335 add_label(label_clamp
);
341 return label
& label_clamp
;
344 void set_clamp_success(Instruction
* clamp_instr
)
346 add_label(label_clamp_success
);
350 bool is_clamp_success()
352 return label
& label_clamp_success
;
357 add_label(label_undefined
);
362 return label
& label_undefined
;
365 void set_vcc(Temp vcc
)
367 add_label(label_vcc
);
373 return label
& label_vcc
;
376 void set_b2f(Temp val
)
378 add_label(label_b2f
);
384 return label
& label_b2f
;
387 void set_add_sub(Instruction
*add_sub_instr
)
389 add_label(label_add_sub
);
390 instr
= add_sub_instr
;
395 return label
& label_add_sub
;
398 void set_bitwise(Instruction
*bitwise_instr
)
400 add_label(label_bitwise
);
401 instr
= bitwise_instr
;
406 return label
& label_bitwise
;
409 void set_uniform_bitwise()
411 add_label(label_uniform_bitwise
);
414 bool is_uniform_bitwise()
416 return label
& label_uniform_bitwise
;
419 void set_minmax(Instruction
*minmax_instr
)
421 add_label(label_minmax
);
422 instr
= minmax_instr
;
427 return label
& label_minmax
;
430 void set_fcmp(Instruction
*fcmp_instr
)
432 add_label(label_fcmp
);
438 return label
& label_fcmp
;
441 void set_scc_needed()
443 add_label(label_scc_needed
);
448 return label
& label_scc_needed
;
451 void set_scc_invert(Temp scc_inv
)
453 add_label(label_scc_invert
);
459 return label
& label_scc_invert
;
462 void set_uniform_bool(Temp uniform_bool
)
464 add_label(label_uniform_bool
);
468 bool is_uniform_bool()
470 return label
& label_uniform_bool
;
475 add_label(label_vcc_hint
);
480 return label
& label_vcc_hint
;
483 void set_b2i(Temp val
)
485 add_label(label_b2i
);
491 return label
& label_b2i
;
498 std::vector
<aco_ptr
<Instruction
>> instructions
;
500 std::pair
<uint32_t,Temp
> last_literal
;
501 std::vector
<mad_info
> mad_infos
;
502 std::vector
<uint16_t> uses
;
505 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
507 if (instr
->operands
[0].isConstant() ||
508 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
511 switch (instr
->opcode
) {
512 case aco_opcode::v_add_f32
:
513 case aco_opcode::v_mul_f32
:
514 case aco_opcode::v_or_b32
:
515 case aco_opcode::v_and_b32
:
516 case aco_opcode::v_xor_b32
:
517 case aco_opcode::v_max_f32
:
518 case aco_opcode::v_min_f32
:
519 case aco_opcode::v_max_i32
:
520 case aco_opcode::v_min_i32
:
521 case aco_opcode::v_max_u32
:
522 case aco_opcode::v_min_u32
:
523 case aco_opcode::v_cmp_eq_f32
:
524 case aco_opcode::v_cmp_lg_f32
:
526 case aco_opcode::v_sub_f32
:
527 instr
->opcode
= aco_opcode::v_subrev_f32
;
529 case aco_opcode::v_cmp_lt_f32
:
530 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
532 case aco_opcode::v_cmp_ge_f32
:
533 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
535 case aco_opcode::v_cmp_lt_i32
:
536 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
543 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
548 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
551 if (instr
->isDPP() || instr
->isSDWA())
554 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
555 instr
->opcode
!= aco_opcode::v_madak_f32
&&
556 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
557 instr
->opcode
!= aco_opcode::v_madak_f16
&&
558 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
559 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
560 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
561 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
562 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
563 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
564 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
567 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
569 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
570 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
571 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
572 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
573 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
576 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
581 aco_ptr
<Instruction
> tmp
= std::move(instr
);
582 Format format
= asVOP3(tmp
->format
);
583 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
584 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
585 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
586 instr
->definitions
[i
] = tmp
->definitions
[i
];
587 if (instr
->definitions
[i
].isTemp()) {
588 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
589 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
590 info
.instr
= instr
.get();
595 /* only covers special cases */
596 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
599 case aco_opcode::v_interp_p2_f32
:
600 case aco_opcode::v_mac_f32
:
601 case aco_opcode::v_writelane_b32
:
602 case aco_opcode::v_writelane_b32_e64
:
603 case aco_opcode::v_cndmask_b32
:
605 case aco_opcode::s_addk_i32
:
606 case aco_opcode::s_mulk_i32
:
607 case aco_opcode::p_wqm
:
608 case aco_opcode::p_extract_vector
:
609 case aco_opcode::p_split_vector
:
610 case aco_opcode::v_readlane_b32
:
611 case aco_opcode::v_readlane_b32_e64
:
612 case aco_opcode::v_readfirstlane_b32
:
619 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
621 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
622 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
627 /* check constant bus and literal limitations */
628 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
630 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
631 Operand
literal32(s1
);
632 Operand
literal64(s2
);
633 unsigned num_sgprs
= 0;
634 unsigned sgpr
[] = {0, 0};
636 for (unsigned i
= 0; i
< num_operands
; i
++) {
637 Operand op
= operands
[i
];
639 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
640 /* two reads of the same SGPR count as 1 to the limit */
641 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
643 sgpr
[num_sgprs
++] = op
.tempId();
648 } else if (op
.isLiteral()) {
649 if (ctx
.program
->chip_class
< GFX10
)
652 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
654 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
657 /* Any number of 32-bit literals counts as only 1 to the limit. Same
658 * (but separately) for 64-bit literals. */
659 if (op
.size() == 1 && literal32
.isUndefined()) {
662 } else if (op
.size() == 2 && literal64
.isUndefined()) {
675 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
677 Operand op
= instr
->operands
[op_index
];
681 Temp tmp
= op
.getTemp();
682 if (!ctx
.info
[tmp
.id()].is_add_sub())
685 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
687 switch (add_instr
->opcode
) {
688 case aco_opcode::v_add_u32
:
689 case aco_opcode::v_add_co_u32
:
690 case aco_opcode::v_add_co_u32_e64
:
691 case aco_opcode::s_add_i32
:
692 case aco_opcode::s_add_u32
:
698 if (add_instr
->usesModifiers())
701 for (unsigned i
= 0; i
< 2; i
++) {
702 if (add_instr
->operands
[i
].isConstant()) {
703 *offset
= add_instr
->operands
[i
].constantValue();
704 } else if (add_instr
->operands
[i
].isTemp() &&
705 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal(32)) {
706 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
710 if (!add_instr
->operands
[!i
].isTemp())
713 uint32_t offset2
= 0;
714 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
717 *base
= add_instr
->operands
[!i
].getTemp();
725 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
727 if (instr
->format
== Format::PSEUDO
)
728 return instr
->operands
[index
].bytes() * 8u;
729 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
730 return index
== 2 ? 64 : 32;
731 else if (instr
->isVALU() || instr
->isSALU())
732 return instr_info
.operand_size
[(int)instr
->opcode
];
737 Operand
get_constant_op(opt_ctx
&ctx
, ssa_info info
, uint32_t bits
)
740 return Operand((uint8_t)info
.val
);
742 return Operand((uint16_t)info
.val
);
743 // TODO: this functions shouldn't be needed if we store Operand instead of value.
744 Operand
op(info
.val
, bits
== 64);
745 if (info
.is_literal(32) && info
.val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
746 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
750 bool fixed_to_exec(Operand op
)
752 return op
.isFixed() && op
.physReg() == exec
;
755 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
757 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
758 ASSERTED
bool all_const
= false;
759 for (Operand
& op
: instr
->operands
)
760 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal(32));
761 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
764 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
766 if (!instr
->operands
[i
].isTemp())
769 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
770 /* propagate undef */
771 if (info
.is_undefined() && is_phi(instr
))
772 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
773 /* propagate reg->reg of same type */
774 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
775 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
776 info
= ctx
.info
[info
.temp
.id()];
779 /* SALU / PSEUDO: propagate inline constants */
780 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
781 bool is_subdword
= false;
782 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
783 if (instr
->format
== Format::PSEUDO
) {
784 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
785 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
786 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
787 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
788 if (is_subdword
&& ctx
.program
->chip_class
< GFX9
)
792 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
793 instr
->operands
[i
].setTemp(info
.temp
);
794 info
= ctx
.info
[info
.temp
.id()];
795 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
796 /* propagate vgpr if it can take it */
797 switch (instr
->opcode
) {
798 case aco_opcode::p_create_vector
:
799 case aco_opcode::p_split_vector
:
800 case aco_opcode::p_extract_vector
:
801 case aco_opcode::p_phi
: {
802 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
803 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
805 instr
->operands
[i
] = Operand(info
.temp
);
806 info
= ctx
.info
[info
.temp
.id()];
814 unsigned bits
= get_operand_size(instr
, i
);
815 if ((info
.is_constant(bits
) || (!is_subdword
&& info
.is_literal(bits
) && instr
->format
== Format::PSEUDO
)) &&
816 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
817 instr
->operands
[i
] = get_constant_op(ctx
, info
, bits
);
822 /* VALU: propagate neg, abs & inline constants */
823 else if (instr
->isVALU()) {
824 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
825 instr
->operands
[i
].setTemp(info
.temp
);
826 info
= ctx
.info
[info
.temp
.id()];
829 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
830 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
831 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
833 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
836 instr
->operands
[i
] = Operand(info
.temp
);
838 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
840 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
842 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
843 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
844 instr
->operands
[i
].setTemp(info
.temp
);
846 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
847 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
848 instr
->operands
[i
].setTemp(info
.temp
);
850 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
853 instr
->operands
[i
].setTemp(info
.temp
);
855 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
857 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
860 unsigned bits
= get_operand_size(instr
, i
);
861 if (info
.is_constant(bits
) && alu_can_accept_constant(instr
->opcode
, i
)) {
862 Operand op
= get_constant_op(ctx
, info
, bits
);
863 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
864 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
865 instr
->operands
[i
] = op
;
867 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
868 instr
->operands
[i
] = instr
->operands
[0];
869 instr
->operands
[0] = op
;
871 } else if (can_use_VOP3(ctx
, instr
)) {
873 instr
->operands
[i
] = op
;
879 /* MUBUF: propagate constants and combine additions */
880 else if (instr
->format
== Format::MUBUF
) {
881 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
884 while (info
.is_temp())
885 info
= ctx
.info
[info
.temp
.id()];
887 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
888 assert(!mubuf
->idxen
);
889 instr
->operands
[1] = Operand(v1
);
890 mubuf
->offset
+= info
.val
;
891 mubuf
->offen
= false;
893 } else if (i
== 2 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
894 instr
->operands
[2] = Operand((uint32_t) 0);
895 mubuf
->offset
+= info
.val
;
897 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
898 assert(!mubuf
->idxen
);
899 instr
->operands
[1].setTemp(base
);
900 mubuf
->offset
+= offset
;
902 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
903 instr
->operands
[i
].setTemp(base
);
904 mubuf
->offset
+= offset
;
909 /* DS: combine additions */
910 else if (instr
->format
== Format::DS
) {
912 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
915 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
916 if (has_usable_ds_offset
&&
917 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
918 base
.regClass() == instr
->operands
[i
].regClass() &&
919 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
920 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
921 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
922 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
923 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
925 if ((offset
& mask
) == 0 &&
926 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
927 ds
->offset1
+ (offset
>> shifts
) <= 255) {
928 instr
->operands
[i
].setTemp(base
);
929 ds
->offset0
+= offset
>> shifts
;
930 ds
->offset1
+= offset
>> shifts
;
933 if (ds
->offset0
+ offset
<= 65535) {
934 instr
->operands
[i
].setTemp(base
);
935 ds
->offset0
+= offset
;
941 /* SMEM: propagate constants and combine additions */
942 else if (instr
->format
== Format::SMEM
) {
944 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
947 if (i
== 1 && info
.is_constant_or_literal(32) &&
948 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
949 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
950 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
951 instr
->operands
[i
] = Operand(info
.val
);
953 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
954 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
956 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal(32) ||
957 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
961 smem
->operands
[1] = Operand(offset
);
962 smem
->operands
.back() = Operand(base
);
964 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
965 new_instr
->operands
[0] = smem
->operands
[0];
966 new_instr
->operands
[1] = Operand(offset
);
967 if (smem
->definitions
.empty())
968 new_instr
->operands
[2] = smem
->operands
[2];
969 new_instr
->operands
.back() = Operand(base
);
970 if (!smem
->definitions
.empty())
971 new_instr
->definitions
[0] = smem
->definitions
[0];
972 new_instr
->can_reorder
= smem
->can_reorder
;
973 new_instr
->barrier
= smem
->barrier
;
974 new_instr
->glc
= smem
->glc
;
975 new_instr
->dlc
= smem
->dlc
;
976 new_instr
->nv
= smem
->nv
;
977 new_instr
->disable_wqm
= smem
->disable_wqm
;
978 instr
.reset(new_instr
);
979 smem
= static_cast<SMEM_instruction
*>(instr
.get());
985 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
986 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
987 /* Flip the branch instruction to get rid of the scc_invert instruction */
988 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
989 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
994 /* if this instruction doesn't define anything, return */
995 if (instr
->definitions
.empty())
998 switch (instr
->opcode
) {
999 case aco_opcode::p_create_vector
: {
1000 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
1001 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
1003 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1007 unsigned num_ops
= instr
->operands
.size();
1008 for (const Operand
& op
: instr
->operands
) {
1009 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
1010 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
1012 if (num_ops
!= instr
->operands
.size()) {
1013 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
1014 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
1015 instr
->definitions
[0] = old_vec
->definitions
[0];
1017 for (Operand
& old_op
: old_vec
->operands
) {
1018 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
1019 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
1020 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
1021 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
1022 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
1023 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
1024 instr
->operands
[k
++] = op
;
1027 instr
->operands
[k
++] = old_op
;
1030 assert(k
== num_ops
);
1033 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
1036 case aco_opcode::p_split_vector
: {
1037 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
1039 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1040 unsigned split_offset
= 0;
1041 unsigned vec_offset
= 0;
1042 unsigned vec_index
= 0;
1043 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
1044 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
1045 vec_offset
+= vec
->operands
[vec_index
++].bytes();
1047 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
1050 Operand vec_op
= vec
->operands
[vec_index
];
1051 if (vec_op
.isConstant()) {
1052 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(ctx
.program
->chip_class
, vec_op
.constantValue64());
1053 } else if (vec_op
.isUndefined()) {
1054 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1056 assert(vec_op
.isTemp());
1057 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1062 case aco_opcode::p_extract_vector
: { /* mov */
1063 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
1066 /* check if we index directly into a vector element */
1067 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1068 const unsigned index
= instr
->operands
[1].constantValue();
1069 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1070 unsigned offset
= 0;
1072 for (const Operand
& op
: vec
->operands
) {
1073 if (offset
< dst_offset
) {
1074 offset
+= op
.bytes();
1076 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1080 /* convert this extract into a copy instruction */
1081 instr
->opcode
= aco_opcode::p_parallelcopy
;
1082 instr
->operands
.pop_back();
1083 instr
->operands
[0] = op
;
1085 if (op
.isConstant()) {
1086 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, op
.constantValue64());
1087 } else if (op
.isUndefined()) {
1088 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1090 assert(op
.isTemp());
1091 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1097 case aco_opcode::s_mov_b32
: /* propagate */
1098 case aco_opcode::s_mov_b64
:
1099 case aco_opcode::v_mov_b32
:
1100 case aco_opcode::p_as_uniform
:
1101 if (instr
->definitions
[0].isFixed()) {
1102 /* don't copy-propagate copies into fixed registers */
1103 } else if (instr
->usesModifiers()) {
1105 } else if (instr
->operands
[0].isConstant()) {
1106 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, instr
->operands
[0].constantValue64());
1107 } else if (instr
->operands
[0].isTemp()) {
1108 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1110 assert(instr
->operands
[0].isFixed());
1113 case aco_opcode::p_is_helper
:
1114 if (!ctx
.program
->needs_wqm
)
1115 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, 0u);
1117 case aco_opcode::s_movk_i32
: {
1118 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1119 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1120 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1123 case aco_opcode::v_bfrev_b32
:
1124 case aco_opcode::s_brev_b32
: {
1125 if (instr
->operands
[0].isConstant()) {
1126 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1127 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1131 case aco_opcode::s_bfm_b32
: {
1132 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1133 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1134 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1135 uint32_t v
= ((1u << size
) - 1u) << start
;
1136 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1140 case aco_opcode::v_mul_f16
:
1141 case aco_opcode::v_mul_f32
: { /* omod */
1142 /* TODO: try to move the negate/abs modifier to the consumer instead */
1143 if (instr
->usesModifiers())
1146 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1148 for (unsigned i
= 0; i
< 2; i
++) {
1149 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1150 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1151 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1152 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1153 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1154 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1155 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1156 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1157 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1158 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1167 case aco_opcode::v_and_b32
: { /* abs */
1168 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1169 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1170 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1171 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1172 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1174 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1177 case aco_opcode::v_xor_b32
: { /* neg */
1178 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1179 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1180 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1181 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1182 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1183 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1184 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1185 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1186 instr
->opcode
= aco_opcode::v_or_b32
;
1187 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1189 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1193 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1197 case aco_opcode::v_med3_f16
:
1198 case aco_opcode::v_med3_f32
: { /* clamp */
1199 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1200 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1201 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1202 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1206 bool found_zero
= false, found_one
= false;
1207 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1208 for (unsigned i
= 0; i
< 3; i
++)
1210 if (instr
->operands
[i
].constantEquals(0))
1212 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1217 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1218 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1222 case aco_opcode::v_cndmask_b32
:
1223 if (instr
->operands
[0].constantEquals(0) &&
1224 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1225 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1226 else if (instr
->operands
[0].constantEquals(0) &&
1227 instr
->operands
[1].constantEquals(0x3f800000u
))
1228 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1229 else if (instr
->operands
[0].constantEquals(0) &&
1230 instr
->operands
[1].constantEquals(1))
1231 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1233 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1235 case aco_opcode::v_cmp_lg_u32
:
1236 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1237 instr
->operands
[0].constantEquals(0) &&
1238 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1239 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1241 case aco_opcode::p_phi
:
1242 case aco_opcode::p_linear_phi
: {
1243 /* lower_bool_phis() can create phis like this */
1244 bool all_same_temp
= instr
->operands
[0].isTemp();
1245 /* this check is needed when moving uniform loop counters out of a divergent loop */
1247 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1248 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1249 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1250 all_same_temp
= false;
1252 if (all_same_temp
) {
1253 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1255 bool all_undef
= instr
->operands
[0].isUndefined();
1256 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1257 if (!instr
->operands
[i
].isUndefined())
1261 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1265 case aco_opcode::v_add_u32
:
1266 case aco_opcode::v_add_co_u32
:
1267 case aco_opcode::v_add_co_u32_e64
:
1268 case aco_opcode::s_add_i32
:
1269 case aco_opcode::s_add_u32
:
1270 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1272 case aco_opcode::s_not_b32
:
1273 case aco_opcode::s_not_b64
:
1274 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1275 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1276 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1277 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1278 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1279 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1281 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1283 case aco_opcode::s_and_b32
:
1284 case aco_opcode::s_and_b64
:
1285 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1286 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1287 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1288 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1289 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1291 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1292 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1293 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1294 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1299 case aco_opcode::s_or_b32
:
1300 case aco_opcode::s_or_b64
:
1301 case aco_opcode::s_xor_b32
:
1302 case aco_opcode::s_xor_b64
:
1303 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1304 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1306 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1309 case aco_opcode::s_lshl_b32
:
1310 case aco_opcode::v_or_b32
:
1311 case aco_opcode::v_lshlrev_b32
:
1312 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1314 case aco_opcode::v_min_f32
:
1315 case aco_opcode::v_min_f16
:
1316 case aco_opcode::v_min_u32
:
1317 case aco_opcode::v_min_i32
:
1318 case aco_opcode::v_min_u16
:
1319 case aco_opcode::v_min_i16
:
1320 case aco_opcode::v_max_f32
:
1321 case aco_opcode::v_max_f16
:
1322 case aco_opcode::v_max_u32
:
1323 case aco_opcode::v_max_i32
:
1324 case aco_opcode::v_max_u16
:
1325 case aco_opcode::v_max_i16
:
1326 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1328 case aco_opcode::v_cmp_lt_f32
:
1329 case aco_opcode::v_cmp_eq_f32
:
1330 case aco_opcode::v_cmp_le_f32
:
1331 case aco_opcode::v_cmp_gt_f32
:
1332 case aco_opcode::v_cmp_lg_f32
:
1333 case aco_opcode::v_cmp_ge_f32
:
1334 case aco_opcode::v_cmp_o_f32
:
1335 case aco_opcode::v_cmp_u_f32
:
1336 case aco_opcode::v_cmp_nge_f32
:
1337 case aco_opcode::v_cmp_nlg_f32
:
1338 case aco_opcode::v_cmp_ngt_f32
:
1339 case aco_opcode::v_cmp_nle_f32
:
1340 case aco_opcode::v_cmp_neq_f32
:
1341 case aco_opcode::v_cmp_nlt_f32
:
1342 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1344 case aco_opcode::s_cselect_b64
:
1345 case aco_opcode::s_cselect_b32
:
1346 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1347 instr
->operands
[1].constantEquals(0)) {
1348 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1349 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1351 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1352 /* Flip the operands to get rid of the scc_invert instruction */
1353 std::swap(instr
->operands
[0], instr
->operands
[1]);
1354 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1357 case aco_opcode::p_wqm
:
1358 if (instr
->operands
[0].isTemp() &&
1359 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1360 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1368 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1370 *ordered
= *unordered
= op
;
1372 #define CMP(ord, unord) \
1373 case aco_opcode::v_cmp_##ord##_f32:\
1374 case aco_opcode::v_cmp_n##unord##_f32:\
1375 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1376 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1377 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1391 aco_opcode
get_ordered(aco_opcode op
)
1393 aco_opcode ordered
, unordered
, inverse
;
1394 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::num_opcodes
;
1397 aco_opcode
get_unordered(aco_opcode op
)
1399 aco_opcode ordered
, unordered
, inverse
;
1400 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::num_opcodes
;
1403 aco_opcode
get_inverse(aco_opcode op
)
1405 aco_opcode ordered
, unordered
, inverse
;
1406 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::num_opcodes
;
1409 bool is_cmp(aco_opcode op
)
1411 aco_opcode ordered
, unordered
, inverse
;
1412 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1415 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1417 if (ctx
.info
[tmp
.id()].is_temp())
1418 return ctx
.info
[tmp
.id()].temp
.id();
1423 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1425 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1426 for (const Operand
& op
: instr
->operands
) {
1428 ctx
.uses
[op
.tempId()]--;
1433 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1435 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1437 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1440 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1442 if (instr
->definitions
.size() == 2) {
1443 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1444 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1451 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1452 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1453 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1455 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1457 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1460 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1462 bool neg
[2] = {false, false};
1463 bool abs
[2] = {false, false};
1465 Instruction
*op_instr
[2];
1468 for (unsigned i
= 0; i
< 2; i
++) {
1469 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1473 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1475 if (op_instr
[i
]->opcode
!= expected_cmp
)
1477 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1480 if (op_instr
[i
]->isVOP3()) {
1481 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1482 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1484 neg
[i
] = vop3
->neg
[0];
1485 abs
[i
] = vop3
->abs
[0];
1486 opsel
|= (vop3
->opsel
& 1) << i
;
1489 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1490 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1491 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1497 if (op
[1].type() == RegType::sgpr
)
1498 std::swap(op
[0], op
[1]);
1499 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1500 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1503 ctx
.uses
[op
[0].id()]++;
1504 ctx
.uses
[op
[1].id()]++;
1505 decrease_uses(ctx
, op_instr
[0]);
1506 decrease_uses(ctx
, op_instr
[1]);
1508 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1509 Instruction
*new_instr
;
1510 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1511 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1512 for (unsigned i
= 0; i
< 2; i
++) {
1513 vop3
->neg
[i
] = neg
[i
];
1514 vop3
->abs
[i
] = abs
[i
];
1516 vop3
->opsel
= opsel
;
1517 new_instr
= static_cast<Instruction
*>(vop3
);
1519 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1521 new_instr
->operands
[0] = Operand(op
[0]);
1522 new_instr
->operands
[1] = Operand(op
[1]);
1523 new_instr
->definitions
[0] = instr
->definitions
[0];
1525 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1526 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1528 instr
.reset(new_instr
);
1533 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1534 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1535 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1537 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1539 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1542 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1543 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1545 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1546 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1547 if (!nan_test
|| !cmp
)
1550 if (cmp
->opcode
== expected_nan_test
)
1551 std::swap(nan_test
, cmp
);
1552 else if (nan_test
->opcode
!= expected_nan_test
)
1555 if (!is_cmp(cmp
->opcode
))
1558 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1560 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1563 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1564 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1565 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1566 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1567 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1569 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1572 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1573 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1574 decrease_uses(ctx
, nan_test
);
1575 decrease_uses(ctx
, cmp
);
1577 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1578 Instruction
*new_instr
;
1579 if (cmp
->isVOP3()) {
1580 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1581 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1582 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1583 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1584 new_vop3
->clamp
= cmp_vop3
->clamp
;
1585 new_vop3
->omod
= cmp_vop3
->omod
;
1586 new_vop3
->opsel
= cmp_vop3
->opsel
;
1587 new_instr
= new_vop3
;
1589 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1591 new_instr
->operands
[0] = cmp
->operands
[0];
1592 new_instr
->operands
[1] = cmp
->operands
[1];
1593 new_instr
->definitions
[0] = instr
->definitions
[0];
1595 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1596 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1598 instr
.reset(new_instr
);
1603 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1604 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1605 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1607 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1609 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1612 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1614 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1615 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1617 if (!nan_test
|| !cmp
)
1620 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1621 if (cmp
->opcode
== expected_nan_test
)
1622 std::swap(nan_test
, cmp
);
1623 else if (nan_test
->opcode
!= expected_nan_test
)
1626 if (!is_cmp(cmp
->opcode
))
1629 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1631 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1634 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1635 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1636 if (prop_nan0
!= prop_nan1
)
1639 if (nan_test
->isVOP3()) {
1640 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1641 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1645 int constant_operand
= -1;
1646 for (unsigned i
= 0; i
< 2; i
++) {
1647 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1648 constant_operand
= !i
;
1652 if (constant_operand
== -1)
1656 if (cmp
->operands
[constant_operand
].isConstant()) {
1657 constant
= cmp
->operands
[constant_operand
].constantValue();
1658 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1659 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1660 unsigned id
= original_temp_id(ctx
, tmp
);
1661 if (!ctx
.info
[id
].is_constant_or_literal(32))
1663 constant
= ctx
.info
[id
].val
;
1669 memcpy(&constantf
, &constant
, 4);
1670 if (isnan(constantf
))
1673 if (cmp
->operands
[0].isTemp())
1674 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1675 if (cmp
->operands
[1].isTemp())
1676 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1677 decrease_uses(ctx
, nan_test
);
1678 decrease_uses(ctx
, cmp
);
1680 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1681 Instruction
*new_instr
;
1682 if (cmp
->isVOP3()) {
1683 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1684 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1685 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1686 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1687 new_vop3
->clamp
= cmp_vop3
->clamp
;
1688 new_vop3
->omod
= cmp_vop3
->omod
;
1689 new_vop3
->opsel
= cmp_vop3
->opsel
;
1690 new_instr
= new_vop3
;
1692 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1694 new_instr
->operands
[0] = cmp
->operands
[0];
1695 new_instr
->operands
[1] = cmp
->operands
[1];
1696 new_instr
->definitions
[0] = instr
->definitions
[0];
1698 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1699 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1701 instr
.reset(new_instr
);
1706 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1707 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1709 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1711 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1713 if (!instr
->operands
[0].isTemp())
1716 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1720 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1721 if (new_opcode
== aco_opcode::num_opcodes
)
1724 if (cmp
->operands
[0].isTemp())
1725 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1726 if (cmp
->operands
[1].isTemp())
1727 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1728 decrease_uses(ctx
, cmp
);
1730 Instruction
*new_instr
;
1731 if (cmp
->isVOP3()) {
1732 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1733 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1734 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1735 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1736 new_vop3
->clamp
= cmp_vop3
->clamp
;
1737 new_vop3
->omod
= cmp_vop3
->omod
;
1738 new_vop3
->opsel
= cmp_vop3
->opsel
;
1739 new_instr
= new_vop3
;
1741 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1743 new_instr
->operands
[0] = cmp
->operands
[0];
1744 new_instr
->operands
[1] = cmp
->operands
[1];
1745 new_instr
->definitions
[0] = instr
->definitions
[0];
1747 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1748 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1750 instr
.reset(new_instr
);
1755 /* op1(op2(1, 2), 0) if swap = false
1756 * op1(0, op2(1, 2)) if swap = true */
1757 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1758 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1759 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1760 bool *op1_clamp
, uint8_t *op1_omod
,
1761 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1764 if (op1_instr
->opcode
!= op1
)
1767 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1768 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1770 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1773 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1774 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1776 /* don't support inbetween clamp/omod */
1777 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1780 /* get operands and modifiers and check inbetween modifiers */
1781 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1782 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1785 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1786 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1790 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1791 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1794 if (inbetween_opsel
)
1795 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1796 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1800 shuffle
[shuffle_str
[0] - '0'] = 0;
1801 shuffle
[shuffle_str
[1] - '0'] = 1;
1802 shuffle
[shuffle_str
[2] - '0'] = 2;
1804 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1805 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1806 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1807 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1808 *opsel
|= 1 << shuffle
[0];
1810 for (unsigned i
= 0; i
< 2; i
++) {
1811 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1812 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1813 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1814 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1815 *opsel
|= 1 << shuffle
[i
+ 1];
1818 /* check operands */
1819 if (!check_vop3_operands(ctx
, 3, operands
))
1825 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1826 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1827 bool clamp
, unsigned omod
)
1829 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1830 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1831 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1832 new_instr
->clamp
= clamp
;
1833 new_instr
->omod
= omod
;
1834 new_instr
->opsel
= opsel
;
1835 new_instr
->operands
[0] = operands
[0];
1836 new_instr
->operands
[1] = operands
[1];
1837 new_instr
->operands
[2] = operands
[2];
1838 new_instr
->definitions
[0] = instr
->definitions
[0];
1839 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1841 instr
.reset(new_instr
);
1844 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1846 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1847 (label_omod_success
| label_clamp_success
);
1849 for (unsigned swap
= 0; swap
< 2; swap
++) {
1850 if (!((1 << swap
) & ops
))
1853 Operand operands
[3];
1854 bool neg
[3], abs
[3], clamp
;
1855 uint8_t opsel
= 0, omod
= 0;
1856 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1857 instr
.get(), swap
, shuffle
,
1858 operands
, neg
, abs
, &opsel
,
1859 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1860 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1861 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1862 if (omod_clamp
& label_omod_success
)
1863 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1864 if (omod_clamp
& label_clamp_success
)
1865 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1872 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1874 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1877 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1878 (label_omod_success
| label_clamp_success
);
1880 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1881 * max(-min(a, b), c) -> max3(-a, -b, c) */
1882 for (unsigned swap
= 0; swap
< 2; swap
++) {
1883 Operand operands
[3];
1884 bool neg
[3], abs
[3], clamp
;
1885 uint8_t opsel
= 0, omod
= 0;
1887 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1888 instr
.get(), swap
, "012",
1889 operands
, neg
, abs
, &opsel
,
1890 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1892 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1895 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1896 if (omod_clamp
& label_omod_success
)
1897 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1898 if (omod_clamp
& label_clamp_success
)
1899 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1906 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1907 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1908 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1909 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1910 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1911 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1912 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1915 if (!instr
->operands
[0].isTemp())
1917 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1920 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1923 switch (op2_instr
->opcode
) {
1924 case aco_opcode::s_and_b32
:
1925 case aco_opcode::s_or_b32
:
1926 case aco_opcode::s_xor_b32
:
1927 case aco_opcode::s_and_b64
:
1928 case aco_opcode::s_or_b64
:
1929 case aco_opcode::s_xor_b64
:
1935 /* create instruction */
1936 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1937 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1938 ctx
.uses
[instr
->operands
[0].tempId()]--;
1939 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1941 switch (op2_instr
->opcode
) {
1942 case aco_opcode::s_and_b32
:
1943 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1945 case aco_opcode::s_or_b32
:
1946 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1948 case aco_opcode::s_xor_b32
:
1949 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1951 case aco_opcode::s_and_b64
:
1952 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1954 case aco_opcode::s_or_b64
:
1955 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1957 case aco_opcode::s_xor_b64
:
1958 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1967 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1968 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1969 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1970 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1971 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1973 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1976 for (unsigned i
= 0; i
< 2; i
++) {
1977 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1978 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1980 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
1983 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1984 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1987 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1988 instr
->operands
[0] = instr
->operands
[!i
];
1989 instr
->operands
[1] = op2_instr
->operands
[0];
1990 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1992 switch (instr
->opcode
) {
1993 case aco_opcode::s_and_b32
:
1994 instr
->opcode
= aco_opcode::s_andn2_b32
;
1996 case aco_opcode::s_or_b32
:
1997 instr
->opcode
= aco_opcode::s_orn2_b32
;
1999 case aco_opcode::s_and_b64
:
2000 instr
->opcode
= aco_opcode::s_andn2_b64
;
2002 case aco_opcode::s_or_b64
:
2003 instr
->opcode
= aco_opcode::s_orn2_b64
;
2014 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2015 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2017 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
2020 for (unsigned i
= 0; i
< 2; i
++) {
2021 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2022 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
2023 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
2025 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
2028 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2029 if (shift
< 1 || shift
> 4)
2032 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2033 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2036 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2037 instr
->operands
[1] = instr
->operands
[!i
];
2038 instr
->operands
[0] = op2_instr
->operands
[0];
2039 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2041 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2042 aco_opcode::s_lshl2_add_u32
,
2043 aco_opcode::s_lshl3_add_u32
,
2044 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2051 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2053 if (instr
->usesModifiers())
2056 for (unsigned i
= 0; i
< 2; i
++) {
2057 if (!((1 << i
) & ops
))
2059 if (instr
->operands
[i
].isTemp() &&
2060 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2061 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2063 aco_ptr
<Instruction
> new_instr
;
2064 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2065 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2066 } else if (ctx
.program
->chip_class
>= GFX10
||
2067 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2068 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2072 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2073 new_instr
->definitions
[0] = instr
->definitions
[0];
2074 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2075 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2076 new_instr
->definitions
[1].setHint(vcc
);
2077 new_instr
->operands
[0] = Operand(0u);
2078 new_instr
->operands
[1] = instr
->operands
[!i
];
2079 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2080 instr
= std::move(new_instr
);
2081 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2089 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2092 #define MINMAX(type, gfx9) \
2093 case aco_opcode::v_min_##type:\
2094 case aco_opcode::v_max_##type:\
2095 case aco_opcode::v_med3_##type:\
2096 *min = aco_opcode::v_min_##type;\
2097 *max = aco_opcode::v_max_##type;\
2098 *med3 = aco_opcode::v_med3_##type;\
2099 *min3 = aco_opcode::v_min3_##type;\
2100 *max3 = aco_opcode::v_max3_##type;\
2101 *some_gfx9_only = gfx9;\
2115 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2116 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2117 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2118 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2120 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2121 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2122 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2123 aco_opcode other_op
;
2124 if (instr
->opcode
== min
)
2126 else if (instr
->opcode
== max
)
2131 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2132 (label_omod_success
| label_clamp_success
);
2134 for (unsigned swap
= 0; swap
< 2; swap
++) {
2135 Operand operands
[3];
2136 bool neg
[3], abs
[3], clamp
;
2137 uint8_t opsel
= 0, omod
= 0;
2138 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2139 "012", operands
, neg
, abs
, &opsel
,
2140 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2141 int const0_idx
= -1, const1_idx
= -1;
2142 uint32_t const0
= 0, const1
= 0;
2143 for (int i
= 0; i
< 3; i
++) {
2145 if (operands
[i
].isConstant()) {
2146 val
= operands
[i
].constantValue();
2147 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal(32)) {
2148 val
= ctx
.info
[operands
[i
].tempId()].val
;
2152 if (const0_idx
>= 0) {
2160 if (const0_idx
< 0 || const1_idx
< 0)
2163 if (opsel
& (1 << const0_idx
))
2165 if (opsel
& (1 << const1_idx
))
2168 int lower_idx
= const0_idx
;
2170 case aco_opcode::v_min_f32
:
2171 case aco_opcode::v_min_f16
: {
2172 float const0_f
, const1_f
;
2173 if (min
== aco_opcode::v_min_f32
) {
2174 memcpy(&const0_f
, &const0
, 4);
2175 memcpy(&const1_f
, &const1
, 4);
2177 const0_f
= _mesa_half_to_float(const0
);
2178 const1_f
= _mesa_half_to_float(const1
);
2180 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2181 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2182 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2183 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2184 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2187 case aco_opcode::v_min_u32
: {
2188 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2191 case aco_opcode::v_min_u16
: {
2192 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2195 case aco_opcode::v_min_i32
: {
2196 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2197 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2198 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2201 case aco_opcode::v_min_i16
: {
2202 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2203 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2204 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2210 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2212 if (instr
->opcode
== min
) {
2213 if (upper_idx
!= 0 || lower_idx
== 0)
2216 if (upper_idx
== 0 || lower_idx
!= 0)
2220 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2221 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2222 if (omod_clamp
& label_omod_success
)
2223 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2224 if (omod_clamp
& label_clamp_success
)
2225 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2235 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2237 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2238 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2239 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2241 /* find candidates and create the set of sgprs already read */
2242 unsigned sgpr_ids
[2] = {0, 0};
2243 uint32_t operand_mask
= 0;
2244 bool has_literal
= false;
2245 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2246 if (instr
->operands
[i
].isLiteral())
2248 if (!instr
->operands
[i
].isTemp())
2250 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2251 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2252 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2254 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2255 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2256 operand_mask
|= 1u << i
;
2258 unsigned max_sgprs
= 1;
2259 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2264 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2266 /* keep on applying sgprs until there is nothing left to be done */
2267 while (operand_mask
) {
2268 uint32_t sgpr_idx
= 0;
2269 uint32_t sgpr_info_id
= 0;
2270 uint32_t mask
= operand_mask
;
2273 unsigned i
= u_bit_scan(&mask
);
2274 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2275 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2277 sgpr_info_id
= instr
->operands
[i
].tempId();
2280 operand_mask
&= ~(1u << sgpr_idx
);
2282 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2283 * definitively beneficial.
2284 * TODO: this is too conservative because later the use count could be reduced to 1 */
2285 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2288 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2289 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2290 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2293 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2294 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2295 } else if (can_swap_operands(instr
)) {
2296 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2297 instr
->operands
[0] = Operand(sgpr
);
2298 /* swap bits using a 4-entry LUT */
2299 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2300 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2301 } else if (can_use_VOP3(ctx
, instr
)) {
2302 to_VOP3(ctx
, instr
);
2303 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2309 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2310 ctx
.uses
[sgpr_info_id
]--;
2311 ctx
.uses
[sgpr
.id()]++;
2315 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2317 /* check if we could apply omod on predecessor */
2318 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2319 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2320 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2322 unsigned idx
= op0
? 0 : 1;
2323 /* omod was successfully applied */
2324 /* if the omod instruction is v_mad, we also have to change the original add */
2325 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2326 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2327 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2328 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2329 add_instr
->definitions
[0] = instr
->definitions
[0];
2332 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2333 /* check if we have an additional clamp modifier */
2334 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2335 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2336 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2337 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2339 /* change definition ssa-id of modified instruction */
2340 omod_instr
->definitions
[0] = instr
->definitions
[0];
2342 /* change the definition of instr to something unused, e.g. the original omod def */
2343 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2344 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2347 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2348 /* in all other cases, label this instruction as option for multiply-add */
2349 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2353 /* check if we could apply clamp on predecessor */
2354 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2355 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2357 bool found_zero
= false, found_one
= false;
2358 for (unsigned i
= 0; i
< 3; i
++)
2360 if (instr
->operands
[i
].constantEquals(0))
2362 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2367 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2368 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2369 /* clamp was successfully applied */
2370 /* if the clamp instruction is v_mad, we also have to change the original add */
2371 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2372 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2373 add_instr
->definitions
[0] = instr
->definitions
[0];
2375 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2376 /* change definition ssa-id of modified instruction */
2377 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2379 /* change the definition of instr to something unused, e.g. the original omod def */
2380 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2381 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2386 /* omod has no effect if denormals are enabled */
2387 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2388 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2389 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2390 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2391 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2392 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2393 to_VOP3(ctx
, instr
);
2394 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2395 def_info
.set_omod_success(instr
.get());
2396 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2397 to_VOP3(ctx
, instr
);
2398 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2399 def_info
.set_omod_success(instr
.get());
2400 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2401 to_VOP3(ctx
, instr
);
2402 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2403 def_info
.set_omod_success(instr
.get());
2404 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2405 to_VOP3(ctx
, instr
);
2406 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2407 def_info
.set_clamp_success(instr
.get());
2414 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2415 // this would mean that we'd have to fix the instruction uses while value propagation
2417 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2419 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2422 if (instr
->isVALU()) {
2423 if (can_apply_sgprs(instr
))
2424 apply_sgprs(ctx
, instr
);
2425 if (apply_omod_clamp(ctx
, block
, instr
))
2429 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2430 instr
->definitions
[0].setHint(vcc
);
2433 /* TODO: There are still some peephole optimizations that could be done:
2434 * - abs(a - b) -> s_absdiff_i32
2435 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2436 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2437 * These aren't probably too interesting though.
2438 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2439 * probably more useful than the previously mentioned optimizations.
2440 * The various comparison optimizations also currently only work with 32-bit
2443 /* neg(mul(a, b)) -> mul(neg(a), b) */
2444 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2445 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2447 if (!ctx
.info
[val
.id()].is_mul())
2450 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2452 if (mul_instr
->operands
[0].isLiteral())
2454 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2457 /* convert to mul(neg(a), b) */
2458 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2459 Definition def
= instr
->definitions
[0];
2460 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2461 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2462 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2463 instr
->operands
[0] = mul_instr
->operands
[0];
2464 instr
->operands
[1] = mul_instr
->operands
[1];
2465 instr
->definitions
[0] = def
;
2466 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2467 if (mul_instr
->isVOP3()) {
2468 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2469 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2470 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2471 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2472 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2473 new_mul
->omod
= mul
->omod
;
2475 new_mul
->neg
[0] ^= true;
2476 new_mul
->clamp
= false;
2478 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2482 /* combine mul+add -> mad */
2483 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2484 instr
->opcode
== aco_opcode::v_sub_f32
||
2485 instr
->opcode
== aco_opcode::v_subrev_f32
;
2486 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2487 instr
->opcode
== aco_opcode::v_sub_f16
||
2488 instr
->opcode
== aco_opcode::v_subrev_f16
;
2489 if (mad16
|| mad32
) {
2490 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2491 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2492 if (need_fma
&& instr
->definitions
[0].isPrecise())
2494 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2497 uint32_t uses_src0
= UINT32_MAX
;
2498 uint32_t uses_src1
= UINT32_MAX
;
2499 Instruction
* mul_instr
= nullptr;
2500 unsigned add_op_idx
;
2501 /* check if any of the operands is a multiplication */
2502 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2503 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2504 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2505 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2506 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2507 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2509 /* find the 'best' mul instruction to combine with the add */
2510 if (uses_src0
< uses_src1
) {
2511 mul_instr
= op0_info
->instr
;
2513 } else if (uses_src1
< uses_src0
) {
2514 mul_instr
= op1_info
->instr
;
2516 } else if (uses_src0
!= UINT32_MAX
) {
2517 /* tiebreaker: quite random what to pick */
2518 if (op0_info
->instr
->operands
[0].isLiteral()) {
2519 mul_instr
= op1_info
->instr
;
2522 mul_instr
= op0_info
->instr
;
2527 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2528 bool neg
[3] = {false, false, false};
2529 bool abs
[3] = {false, false, false};
2532 op
[0] = mul_instr
->operands
[0];
2533 op
[1] = mul_instr
->operands
[1];
2534 op
[2] = instr
->operands
[add_op_idx
];
2535 // TODO: would be better to check this before selecting a mul instr?
2536 if (!check_vop3_operands(ctx
, 3, op
))
2539 if (mul_instr
->isVOP3()) {
2540 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2541 neg
[0] = vop3
->neg
[0];
2542 neg
[1] = vop3
->neg
[1];
2543 abs
[0] = vop3
->abs
[0];
2544 abs
[1] = vop3
->abs
[1];
2545 /* we cannot use these modifiers between mul and add */
2546 if (vop3
->clamp
|| vop3
->omod
)
2550 /* convert to mad */
2551 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2552 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2554 ctx
.uses
[op
[0].tempId()]++;
2556 ctx
.uses
[op
[1].tempId()]++;
2559 if (instr
->isVOP3()) {
2560 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2561 neg
[2] = vop3
->neg
[add_op_idx
];
2562 abs
[2] = vop3
->abs
[add_op_idx
];
2564 clamp
= vop3
->clamp
;
2565 /* abs of the multiplication result */
2566 if (vop3
->abs
[1 - add_op_idx
]) {
2572 /* neg of the multiplication result */
2573 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2575 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2576 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2577 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2578 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2580 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2582 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2583 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2585 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2586 for (unsigned i
= 0; i
< 3; i
++)
2588 mad
->operands
[i
] = op
[i
];
2589 mad
->neg
[i
] = neg
[i
];
2590 mad
->abs
[i
] = abs
[i
];
2594 mad
->definitions
[0] = instr
->definitions
[0];
2596 /* mark this ssa_def to be re-checked for profitability and literals */
2597 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2598 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2599 instr
.reset(mad
.release());
2603 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2604 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2605 for (unsigned i
= 0; i
< 2; i
++) {
2606 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2607 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2608 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2609 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2610 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2612 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2613 new_instr
->operands
[0] = Operand(0u);
2614 new_instr
->operands
[1] = instr
->operands
[!i
];
2615 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2616 new_instr
->definitions
[0] = instr
->definitions
[0];
2617 instr
.reset(new_instr
.release());
2618 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2622 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2623 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2624 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2625 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2626 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2627 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2628 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2629 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2630 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2631 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2632 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2633 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2634 else if (ctx
.program
->chip_class
>= GFX9
) {
2635 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2636 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2637 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2638 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2639 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2640 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2641 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2643 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2644 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2645 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2646 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2647 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2648 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2649 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2650 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2651 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2652 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2653 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2654 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2655 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2656 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2657 combine_salu_lshl_add(ctx
, instr
);
2658 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2659 combine_salu_not_bitwise(ctx
, instr
);
2660 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2661 if (combine_inverse_comparison(ctx
, instr
)) ;
2662 else combine_salu_not_bitwise(ctx
, instr
);
2663 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2664 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2665 if (combine_ordering_test(ctx
, instr
)) ;
2666 else if (combine_comparison_ordering(ctx
, instr
)) ;
2667 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2668 else combine_salu_n2(ctx
, instr
);
2670 aco_opcode min
, max
, min3
, max3
, med3
;
2671 bool some_gfx9_only
;
2672 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2673 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2674 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2675 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2680 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2682 switch (instr
->opcode
) {
2683 case aco_opcode::s_and_b32
:
2684 case aco_opcode::s_and_b64
:
2685 instr
->opcode
= aco_opcode::s_and_b32
;
2687 case aco_opcode::s_or_b32
:
2688 case aco_opcode::s_or_b64
:
2689 instr
->opcode
= aco_opcode::s_or_b32
;
2691 case aco_opcode::s_xor_b32
:
2692 case aco_opcode::s_xor_b64
:
2693 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2696 /* Don't transform other instructions. They are very unlikely to appear here. */
2700 for (Operand
&op
: instr
->operands
) {
2701 ctx
.uses
[op
.tempId()]--;
2703 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2704 /* Just use the uniform boolean temp. */
2705 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2706 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2707 /* Use the SCC definition of the predecessor instruction.
2708 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2709 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2711 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2712 assert(pred_instr
->definitions
.size() >= 2);
2713 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2714 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2716 unreachable("Invalid operand on uniform bitwise instruction.");
2719 ctx
.uses
[op
.tempId()]++;
2722 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2723 assert(instr
->operands
[0].regClass() == s1
);
2724 assert(instr
->operands
[1].regClass() == s1
);
2728 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2730 const uint32_t threshold
= 4;
2732 if (is_dead(ctx
.uses
, instr
.get())) {
2737 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2738 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2739 unsigned num_used
= 0;
2741 unsigned split_offset
= 0;
2742 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2743 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2746 split_offset
= offset
;
2750 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2751 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2752 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2756 for (Operand
& vec_op
: vec
->operands
) {
2757 if (off
== split_offset
) {
2761 off
+= vec_op
.bytes();
2763 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2764 ctx
.uses
[instr
->operands
[0].tempId()]--;
2765 for (Operand
& vec_op
: vec
->operands
) {
2766 if (vec_op
.isTemp())
2767 ctx
.uses
[vec_op
.tempId()]--;
2770 ctx
.uses
[op
.tempId()]++;
2772 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2773 extract
->operands
[0] = op
;
2774 extract
->definitions
[0] = instr
->definitions
[idx
];
2775 instr
.reset(extract
.release());
2781 if (!done
&& num_used
== 1 &&
2782 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2783 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2784 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2785 extract
->operands
[0] = instr
->operands
[0];
2786 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2787 extract
->definitions
[0] = instr
->definitions
[idx
];
2788 instr
.reset(extract
.release());
2792 mad_info
* mad_info
= NULL
;
2793 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2794 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2795 /* re-check mad instructions */
2796 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2797 ctx
.uses
[mad_info
->mul_temp_id
]++;
2798 if (instr
->operands
[0].isTemp())
2799 ctx
.uses
[instr
->operands
[0].tempId()]--;
2800 if (instr
->operands
[1].isTemp())
2801 ctx
.uses
[instr
->operands
[1].tempId()]--;
2802 instr
.swap(mad_info
->add_instr
);
2805 /* check literals */
2806 else if (!instr
->usesModifiers()) {
2807 /* FMA can only take literals on GFX10+ */
2808 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2809 ctx
.program
->chip_class
< GFX10
)
2812 bool sgpr_used
= false;
2813 uint32_t literal_idx
= 0;
2814 uint32_t literal_uses
= UINT32_MAX
;
2815 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2817 if (instr
->operands
[i
].isConstant() && i
> 0) {
2818 literal_uses
= UINT32_MAX
;
2821 if (!instr
->operands
[i
].isTemp())
2823 unsigned bits
= get_operand_size(instr
, i
);
2824 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2825 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2826 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
)) {
2827 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2830 literal_uses
= UINT32_MAX
;
2833 /* don't break because we still need to check constants */
2834 } else if (!sgpr_used
&&
2835 ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
) &&
2836 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2837 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2842 /* Limit the number of literals to apply to not increase the code
2843 * size too much, but always apply literals for v_mad->v_madak
2844 * because both instructions are 64-bit and this doesn't increase
2846 * TODO: try to apply the literals earlier to lower the number of
2847 * uses below threshold
2849 if (literal_uses
< threshold
|| literal_idx
== 2) {
2850 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2851 mad_info
->check_literal
= true;
2852 mad_info
->literal_idx
= literal_idx
;
2858 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2859 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2860 instr
->operands
.size() &&
2861 instr
->operands
[0].isTemp()) {
2862 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2864 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2865 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2866 instr
->operands
[2].isTemp()) {
2867 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2870 /* check for literals */
2871 if (!instr
->isSALU() && !instr
->isVALU())
2874 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2875 if (instr
->definitions
.size() &&
2876 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2877 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2878 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2880 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2881 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2882 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2883 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2884 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2885 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2891 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2892 return; /* some encodings can't ever take literals */
2894 /* we do not apply the literals yet as we don't know if it is profitable */
2895 Operand
current_literal(s1
);
2897 unsigned literal_id
= 0;
2898 unsigned literal_uses
= UINT32_MAX
;
2899 Operand
literal(s1
);
2900 unsigned num_operands
= 1;
2901 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2902 num_operands
= instr
->operands
.size();
2903 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2904 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2907 unsigned sgpr_ids
[2] = {0, 0};
2908 bool is_literal_sgpr
= false;
2911 /* choose a literal to apply */
2912 for (unsigned i
= 0; i
< num_operands
; i
++) {
2913 Operand op
= instr
->operands
[i
];
2914 unsigned bits
= get_operand_size(instr
, i
);
2916 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2917 op
.tempId() != sgpr_ids
[0])
2918 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2920 if (op
.isLiteral()) {
2921 current_literal
= op
;
2923 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal(bits
)) {
2927 if (!alu_can_accept_constant(instr
->opcode
, i
))
2930 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2931 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2933 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2934 literal_uses
= ctx
.uses
[op
.tempId()];
2935 literal_id
= op
.tempId();
2938 mask
|= (op
.tempId() == literal_id
) << i
;
2942 /* don't go over the constant bus limit */
2943 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2944 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2945 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2946 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2947 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2948 const_bus_limit
= 2;
2950 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2951 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2954 if (literal_id
&& literal_uses
< threshold
&&
2955 (current_literal
.isUndefined() ||
2956 (current_literal
.size() == literal
.size() &&
2957 current_literal
.constantValue() == literal
.constantValue()))) {
2958 /* mark the literal to be applied */
2960 unsigned i
= u_bit_scan(&mask
);
2961 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2962 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2968 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2970 /* Cleanup Dead Instructions */
2974 /* apply literals on MAD */
2975 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2976 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2977 if (info
->check_literal
&&
2978 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2979 aco_ptr
<Instruction
> new_mad
;
2981 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
2982 if (instr
->opcode
== aco_opcode::v_fma_f32
)
2983 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
2984 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
2985 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
2986 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
2987 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
2989 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
2990 if (info
->literal_idx
== 2) { /* add literal -> madak */
2991 new_mad
->operands
[0] = instr
->operands
[0];
2992 new_mad
->operands
[1] = instr
->operands
[1];
2993 } else { /* mul literal -> madmk */
2994 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2995 new_mad
->operands
[1] = instr
->operands
[2];
2997 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2998 new_mad
->definitions
[0] = instr
->definitions
[0];
2999 ctx
.instructions
.emplace_back(std::move(new_mad
));
3004 /* apply literals on other SALU/VALU */
3005 if (instr
->isSALU() || instr
->isVALU()) {
3006 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
3007 Operand op
= instr
->operands
[i
];
3008 unsigned bits
= get_operand_size(instr
, i
);
3009 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal(bits
) && ctx
.uses
[op
.tempId()] == 0) {
3010 Operand
literal(ctx
.info
[op
.tempId()].val
);
3011 if (instr
->isVALU() && i
> 0)
3012 to_VOP3(ctx
, instr
);
3013 instr
->operands
[i
] = literal
;
3018 ctx
.instructions
.emplace_back(std::move(instr
));
3022 void optimize(Program
* program
)
3025 ctx
.program
= program
;
3026 std::vector
<ssa_info
> info(program
->peekAllocationId());
3027 ctx
.info
= info
.data();
3029 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
3030 for (Block
& block
: program
->blocks
) {
3031 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3032 label_instruction(ctx
, block
, instr
);
3035 ctx
.uses
= dead_code_analysis(program
);
3037 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3038 for (Block
& block
: program
->blocks
) {
3039 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3040 combine_instruction(ctx
, block
, instr
);
3043 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3044 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3045 Block
* block
= &(*it
);
3046 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3047 select_instruction(ctx
, *it
);
3050 /* 4. Add literals to instructions */
3051 for (Block
& block
: program
->blocks
) {
3052 ctx
.instructions
.clear();
3053 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3054 apply_literals(ctx
, instr
);
3055 block
.instructions
.swap(ctx
.instructions
);