2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant_32bit
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
94 label_constant_16bit
= 1 << 29,
97 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
98 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
99 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
100 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
101 static constexpr uint32_t val_labels
= label_constant_32bit
| label_constant_64bit
| label_constant_16bit
| label_literal
| label_mad
;
111 ssa_info() : label(0) {}
113 void add_label(Label new_label
)
115 /* Since all labels which use "instr" use it for the same thing
116 * (indicating the defining instruction), there is no need to clear
117 * any other instr labels. */
118 if (new_label
& instr_labels
)
119 label
&= ~temp_labels
; /* instr and temp alias */
121 if (new_label
& temp_labels
) {
122 label
&= ~temp_labels
;
123 label
&= ~instr_labels
; /* instr and temp alias */
126 uint32_t const_labels
= label_literal
| label_constant_32bit
| label_constant_64bit
| label_constant_16bit
;
127 if (new_label
& const_labels
)
128 label
&= ~val_labels
| const_labels
;
129 else if (new_label
& val_labels
)
130 label
&= ~val_labels
;
135 void set_vec(Instruction
* vec
)
137 add_label(label_vec
);
143 return label
& label_vec
;
146 void set_constant(chip_class chip
, uint64_t constant
)
148 Operand
op16((uint16_t)constant
);
149 Operand
op32((uint32_t)constant
);
150 add_label(label_literal
);
153 if (chip
>= GFX8
&& !op16
.isLiteral())
154 add_label(label_constant_16bit
);
156 if (!op32
.isLiteral() || ((uint32_t)constant
== 0x3e22f983 && chip
>= GFX8
))
157 add_label(label_constant_32bit
);
159 if (constant
<= 64) {
160 add_label(label_constant_64bit
);
161 } else if (constant
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
162 add_label(label_constant_64bit
);
163 } else if (constant
== 0x3FE0000000000000) { /* 0.5 */
164 add_label(label_constant_64bit
);
165 } else if (constant
== 0xBFE0000000000000) { /* -0.5 */
166 add_label(label_constant_64bit
);
167 } else if (constant
== 0x3FF0000000000000) { /* 1.0 */
168 add_label(label_constant_64bit
);
169 } else if (constant
== 0xBFF0000000000000) { /* -1.0 */
170 add_label(label_constant_64bit
);
171 } else if (constant
== 0x4000000000000000) { /* 2.0 */
172 add_label(label_constant_64bit
);
173 } else if (constant
== 0xC000000000000000) { /* -2.0 */
174 add_label(label_constant_64bit
);
175 } else if (constant
== 0x4010000000000000) { /* 4.0 */
176 add_label(label_constant_64bit
);
177 } else if (constant
== 0xC010000000000000) { /* -4.0 */
178 add_label(label_constant_64bit
);
181 if (label
& label_constant_64bit
) {
182 val
= Operand(constant
).constantValue();
184 label
&= ~(label_literal
| label_constant_16bit
| label_constant_32bit
);
188 bool is_constant(unsigned bits
)
192 return label
& label_literal
;
194 return label
& label_constant_16bit
;
196 return label
& label_constant_32bit
;
198 return label
& label_constant_64bit
;
203 bool is_literal(unsigned bits
)
205 bool is_lit
= label
& label_literal
;
210 return is_lit
&& ~(label
& label_constant_16bit
);
212 return is_lit
&& ~(label
& label_constant_32bit
);
219 bool is_constant_or_literal(unsigned bits
)
222 return label
& label_constant_64bit
;
224 return label
& label_literal
;
227 void set_abs(Temp abs_temp
)
229 add_label(label_abs
);
235 return label
& label_abs
;
238 void set_neg(Temp neg_temp
)
240 add_label(label_neg
);
246 return label
& label_neg
;
249 void set_neg_abs(Temp neg_abs_temp
)
251 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
255 void set_mul(Instruction
* mul
)
257 add_label(label_mul
);
263 return label
& label_mul
;
266 void set_temp(Temp tmp
)
268 add_label(label_temp
);
274 return label
& label_temp
;
277 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
279 add_label(label_mad
);
286 return label
& label_mad
;
289 void set_omod2(Temp def
)
291 add_label(label_omod2
);
297 return label
& label_omod2
;
300 void set_omod4(Temp def
)
302 add_label(label_omod4
);
308 return label
& label_omod4
;
311 void set_omod5(Temp def
)
313 add_label(label_omod5
);
319 return label
& label_omod5
;
322 void set_omod_success(Instruction
* omod_instr
)
324 add_label(label_omod_success
);
328 bool is_omod_success()
330 return label
& label_omod_success
;
333 void set_clamp(Temp def
)
335 add_label(label_clamp
);
341 return label
& label_clamp
;
344 void set_clamp_success(Instruction
* clamp_instr
)
346 add_label(label_clamp_success
);
350 bool is_clamp_success()
352 return label
& label_clamp_success
;
357 add_label(label_undefined
);
362 return label
& label_undefined
;
365 void set_vcc(Temp vcc
)
367 add_label(label_vcc
);
373 return label
& label_vcc
;
376 void set_b2f(Temp val
)
378 add_label(label_b2f
);
384 return label
& label_b2f
;
387 void set_add_sub(Instruction
*add_sub_instr
)
389 add_label(label_add_sub
);
390 instr
= add_sub_instr
;
395 return label
& label_add_sub
;
398 void set_bitwise(Instruction
*bitwise_instr
)
400 add_label(label_bitwise
);
401 instr
= bitwise_instr
;
406 return label
& label_bitwise
;
409 void set_uniform_bitwise()
411 add_label(label_uniform_bitwise
);
414 bool is_uniform_bitwise()
416 return label
& label_uniform_bitwise
;
419 void set_minmax(Instruction
*minmax_instr
)
421 add_label(label_minmax
);
422 instr
= minmax_instr
;
427 return label
& label_minmax
;
430 void set_fcmp(Instruction
*fcmp_instr
)
432 add_label(label_fcmp
);
438 return label
& label_fcmp
;
441 void set_scc_needed()
443 add_label(label_scc_needed
);
448 return label
& label_scc_needed
;
451 void set_scc_invert(Temp scc_inv
)
453 add_label(label_scc_invert
);
459 return label
& label_scc_invert
;
462 void set_uniform_bool(Temp uniform_bool
)
464 add_label(label_uniform_bool
);
468 bool is_uniform_bool()
470 return label
& label_uniform_bool
;
475 add_label(label_vcc_hint
);
480 return label
& label_vcc_hint
;
483 void set_b2i(Temp val
)
485 add_label(label_b2i
);
491 return label
& label_b2i
;
498 std::vector
<aco_ptr
<Instruction
>> instructions
;
500 std::pair
<uint32_t,Temp
> last_literal
;
501 std::vector
<mad_info
> mad_infos
;
502 std::vector
<uint16_t> uses
;
505 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
507 if (instr
->operands
[0].isConstant() ||
508 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
511 switch (instr
->opcode
) {
512 case aco_opcode::v_add_f16
:
513 case aco_opcode::v_add_f32
:
514 case aco_opcode::v_mul_f16
:
515 case aco_opcode::v_mul_f32
:
516 case aco_opcode::v_or_b32
:
517 case aco_opcode::v_and_b32
:
518 case aco_opcode::v_xor_b32
:
519 case aco_opcode::v_max_f16
:
520 case aco_opcode::v_max_f32
:
521 case aco_opcode::v_min_f16
:
522 case aco_opcode::v_min_f32
:
523 case aco_opcode::v_max_i32
:
524 case aco_opcode::v_min_i32
:
525 case aco_opcode::v_max_u32
:
526 case aco_opcode::v_min_u32
:
527 case aco_opcode::v_cmp_eq_f16
:
528 case aco_opcode::v_cmp_eq_f32
:
529 case aco_opcode::v_cmp_lg_f16
:
530 case aco_opcode::v_cmp_lg_f32
:
532 case aco_opcode::v_sub_f16
:
533 instr
->opcode
= aco_opcode::v_subrev_f16
;
535 case aco_opcode::v_sub_f32
:
536 instr
->opcode
= aco_opcode::v_subrev_f32
;
538 case aco_opcode::v_cmp_lt_f16
:
539 instr
->opcode
= aco_opcode::v_cmp_gt_f16
;
541 case aco_opcode::v_cmp_lt_f32
:
542 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
544 case aco_opcode::v_cmp_ge_f16
:
545 instr
->opcode
= aco_opcode::v_cmp_le_f16
;
547 case aco_opcode::v_cmp_ge_f32
:
548 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
550 case aco_opcode::v_cmp_lt_i32
:
551 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
558 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
563 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
566 if (instr
->isDPP() || instr
->isSDWA())
569 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
570 instr
->opcode
!= aco_opcode::v_madak_f32
&&
571 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
572 instr
->opcode
!= aco_opcode::v_madak_f16
&&
573 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
574 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
575 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
576 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
577 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
578 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
579 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
582 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
584 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
585 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
586 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
587 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
588 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
591 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
596 aco_ptr
<Instruction
> tmp
= std::move(instr
);
597 Format format
= asVOP3(tmp
->format
);
598 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
599 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
600 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
601 instr
->definitions
[i
] = tmp
->definitions
[i
];
602 if (instr
->definitions
[i
].isTemp()) {
603 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
604 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
605 info
.instr
= instr
.get();
610 /* only covers special cases */
611 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
614 case aco_opcode::v_interp_p2_f32
:
615 case aco_opcode::v_mac_f32
:
616 case aco_opcode::v_writelane_b32
:
617 case aco_opcode::v_writelane_b32_e64
:
618 case aco_opcode::v_cndmask_b32
:
620 case aco_opcode::s_addk_i32
:
621 case aco_opcode::s_mulk_i32
:
622 case aco_opcode::p_wqm
:
623 case aco_opcode::p_extract_vector
:
624 case aco_opcode::p_split_vector
:
625 case aco_opcode::v_readlane_b32
:
626 case aco_opcode::v_readlane_b32_e64
:
627 case aco_opcode::v_readfirstlane_b32
:
634 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
636 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
637 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
642 /* check constant bus and literal limitations */
643 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
645 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
646 Operand
literal32(s1
);
647 Operand
literal64(s2
);
648 unsigned num_sgprs
= 0;
649 unsigned sgpr
[] = {0, 0};
651 for (unsigned i
= 0; i
< num_operands
; i
++) {
652 Operand op
= operands
[i
];
654 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
655 /* two reads of the same SGPR count as 1 to the limit */
656 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
658 sgpr
[num_sgprs
++] = op
.tempId();
663 } else if (op
.isLiteral()) {
664 if (ctx
.program
->chip_class
< GFX10
)
667 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
669 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
672 /* Any number of 32-bit literals counts as only 1 to the limit. Same
673 * (but separately) for 64-bit literals. */
674 if (op
.size() == 1 && literal32
.isUndefined()) {
677 } else if (op
.size() == 2 && literal64
.isUndefined()) {
690 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
692 Operand op
= instr
->operands
[op_index
];
696 Temp tmp
= op
.getTemp();
697 if (!ctx
.info
[tmp
.id()].is_add_sub())
700 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
702 switch (add_instr
->opcode
) {
703 case aco_opcode::v_add_u32
:
704 case aco_opcode::v_add_co_u32
:
705 case aco_opcode::v_add_co_u32_e64
:
706 case aco_opcode::s_add_i32
:
707 case aco_opcode::s_add_u32
:
713 if (add_instr
->usesModifiers())
716 for (unsigned i
= 0; i
< 2; i
++) {
717 if (add_instr
->operands
[i
].isConstant()) {
718 *offset
= add_instr
->operands
[i
].constantValue();
719 } else if (add_instr
->operands
[i
].isTemp() &&
720 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal(32)) {
721 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
725 if (!add_instr
->operands
[!i
].isTemp())
728 uint32_t offset2
= 0;
729 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
732 *base
= add_instr
->operands
[!i
].getTemp();
740 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
742 if (instr
->format
== Format::PSEUDO
)
743 return instr
->operands
[index
].bytes() * 8u;
744 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
745 return index
== 2 ? 64 : 32;
746 else if (instr
->isVALU() || instr
->isSALU())
747 return instr_info
.operand_size
[(int)instr
->opcode
];
752 Operand
get_constant_op(opt_ctx
&ctx
, ssa_info info
, uint32_t bits
)
755 return Operand((uint8_t)info
.val
);
757 return Operand((uint16_t)info
.val
);
758 // TODO: this functions shouldn't be needed if we store Operand instead of value.
759 Operand
op(info
.val
, bits
== 64);
760 if (info
.is_literal(32) && info
.val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
761 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
765 bool fixed_to_exec(Operand op
)
767 return op
.isFixed() && op
.physReg() == exec
;
770 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
772 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
773 ASSERTED
bool all_const
= false;
774 for (Operand
& op
: instr
->operands
)
775 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal(32));
776 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
779 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
781 if (!instr
->operands
[i
].isTemp())
784 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
785 /* propagate undef */
786 if (info
.is_undefined() && is_phi(instr
))
787 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
788 /* propagate reg->reg of same type */
789 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
790 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
791 info
= ctx
.info
[info
.temp
.id()];
794 /* SALU / PSEUDO: propagate inline constants */
795 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
796 bool is_subdword
= false;
797 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
798 if (instr
->format
== Format::PSEUDO
) {
799 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
800 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
801 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
802 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
803 if (is_subdword
&& ctx
.program
->chip_class
< GFX9
)
807 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
808 instr
->operands
[i
].setTemp(info
.temp
);
809 info
= ctx
.info
[info
.temp
.id()];
810 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
811 /* propagate vgpr if it can take it */
812 switch (instr
->opcode
) {
813 case aco_opcode::p_create_vector
:
814 case aco_opcode::p_split_vector
:
815 case aco_opcode::p_extract_vector
:
816 case aco_opcode::p_phi
: {
817 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
818 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
820 instr
->operands
[i
] = Operand(info
.temp
);
821 info
= ctx
.info
[info
.temp
.id()];
829 unsigned bits
= get_operand_size(instr
, i
);
830 if ((info
.is_constant(bits
) || (!is_subdword
&& info
.is_literal(bits
) && instr
->format
== Format::PSEUDO
)) &&
831 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
832 instr
->operands
[i
] = get_constant_op(ctx
, info
, bits
);
837 /* VALU: propagate neg, abs & inline constants */
838 else if (instr
->isVALU()) {
839 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
840 instr
->operands
[i
].setTemp(info
.temp
);
841 info
= ctx
.info
[info
.temp
.id()];
844 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
845 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
846 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
848 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
851 instr
->operands
[i
] = Operand(info
.temp
);
853 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
855 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
857 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
858 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
859 instr
->operands
[i
].setTemp(info
.temp
);
861 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
862 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
863 instr
->operands
[i
].setTemp(info
.temp
);
865 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
868 instr
->operands
[i
].setTemp(info
.temp
);
870 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
872 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
875 unsigned bits
= get_operand_size(instr
, i
);
876 if (info
.is_constant(bits
) && alu_can_accept_constant(instr
->opcode
, i
)) {
877 Operand op
= get_constant_op(ctx
, info
, bits
);
878 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
879 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
880 instr
->operands
[i
] = op
;
882 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
883 instr
->operands
[i
] = instr
->operands
[0];
884 instr
->operands
[0] = op
;
886 } else if (can_use_VOP3(ctx
, instr
)) {
888 instr
->operands
[i
] = op
;
894 /* MUBUF: propagate constants and combine additions */
895 else if (instr
->format
== Format::MUBUF
) {
896 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
899 while (info
.is_temp())
900 info
= ctx
.info
[info
.temp
.id()];
902 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
903 assert(!mubuf
->idxen
);
904 instr
->operands
[1] = Operand(v1
);
905 mubuf
->offset
+= info
.val
;
906 mubuf
->offen
= false;
908 } else if (i
== 2 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
909 instr
->operands
[2] = Operand((uint32_t) 0);
910 mubuf
->offset
+= info
.val
;
912 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
913 assert(!mubuf
->idxen
);
914 instr
->operands
[1].setTemp(base
);
915 mubuf
->offset
+= offset
;
917 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
918 instr
->operands
[i
].setTemp(base
);
919 mubuf
->offset
+= offset
;
924 /* DS: combine additions */
925 else if (instr
->format
== Format::DS
) {
927 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
930 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
931 if (has_usable_ds_offset
&&
932 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
933 base
.regClass() == instr
->operands
[i
].regClass() &&
934 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
935 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
936 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
937 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
938 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
940 if ((offset
& mask
) == 0 &&
941 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
942 ds
->offset1
+ (offset
>> shifts
) <= 255) {
943 instr
->operands
[i
].setTemp(base
);
944 ds
->offset0
+= offset
>> shifts
;
945 ds
->offset1
+= offset
>> shifts
;
948 if (ds
->offset0
+ offset
<= 65535) {
949 instr
->operands
[i
].setTemp(base
);
950 ds
->offset0
+= offset
;
956 /* SMEM: propagate constants and combine additions */
957 else if (instr
->format
== Format::SMEM
) {
959 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
962 if (i
== 1 && info
.is_constant_or_literal(32) &&
963 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
964 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
965 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
966 instr
->operands
[i
] = Operand(info
.val
);
968 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
969 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
971 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal(32) ||
972 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
976 smem
->operands
[1] = Operand(offset
);
977 smem
->operands
.back() = Operand(base
);
979 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
980 new_instr
->operands
[0] = smem
->operands
[0];
981 new_instr
->operands
[1] = Operand(offset
);
982 if (smem
->definitions
.empty())
983 new_instr
->operands
[2] = smem
->operands
[2];
984 new_instr
->operands
.back() = Operand(base
);
985 if (!smem
->definitions
.empty())
986 new_instr
->definitions
[0] = smem
->definitions
[0];
987 new_instr
->can_reorder
= smem
->can_reorder
;
988 new_instr
->barrier
= smem
->barrier
;
989 new_instr
->glc
= smem
->glc
;
990 new_instr
->dlc
= smem
->dlc
;
991 new_instr
->nv
= smem
->nv
;
992 new_instr
->disable_wqm
= smem
->disable_wqm
;
993 instr
.reset(new_instr
);
994 smem
= static_cast<SMEM_instruction
*>(instr
.get());
1000 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
1001 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1002 /* Flip the branch instruction to get rid of the scc_invert instruction */
1003 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
1004 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1009 /* if this instruction doesn't define anything, return */
1010 if (instr
->definitions
.empty())
1013 switch (instr
->opcode
) {
1014 case aco_opcode::p_create_vector
: {
1015 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
1016 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
1018 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1022 unsigned num_ops
= instr
->operands
.size();
1023 for (const Operand
& op
: instr
->operands
) {
1024 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
1025 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
1027 if (num_ops
!= instr
->operands
.size()) {
1028 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
1029 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
1030 instr
->definitions
[0] = old_vec
->definitions
[0];
1032 for (Operand
& old_op
: old_vec
->operands
) {
1033 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
1034 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
1035 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
1036 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
1037 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
1038 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
1039 instr
->operands
[k
++] = op
;
1042 instr
->operands
[k
++] = old_op
;
1045 assert(k
== num_ops
);
1048 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
1051 case aco_opcode::p_split_vector
: {
1052 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1054 if (info
.is_constant_or_literal(32)) {
1055 uint32_t val
= info
.val
;
1056 for (Definition def
: instr
->definitions
) {
1057 uint32_t mask
= u_bit_consecutive(0, def
.bytes() * 8u);
1058 ctx
.info
[def
.tempId()].set_constant(ctx
.program
->chip_class
, val
& mask
);
1059 val
>>= def
.bytes() * 8u;
1062 } else if (!info
.is_vec()) {
1066 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1067 unsigned split_offset
= 0;
1068 unsigned vec_offset
= 0;
1069 unsigned vec_index
= 0;
1070 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
1071 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
1072 vec_offset
+= vec
->operands
[vec_index
++].bytes();
1074 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
1077 Operand vec_op
= vec
->operands
[vec_index
];
1078 if (vec_op
.isConstant()) {
1079 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(ctx
.program
->chip_class
, vec_op
.constantValue64());
1080 } else if (vec_op
.isUndefined()) {
1081 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1083 assert(vec_op
.isTemp());
1084 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1089 case aco_opcode::p_extract_vector
: { /* mov */
1090 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1091 const unsigned index
= instr
->operands
[1].constantValue();
1092 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1094 if (info
.is_constant_or_literal(32)) {
1095 uint32_t mask
= u_bit_consecutive(0, instr
->definitions
[0].bytes() * 8u);
1096 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, (info
.val
>> (dst_offset
* 8u)) & mask
);
1098 } else if (!info
.is_vec()) {
1102 /* check if we index directly into a vector element */
1103 Instruction
* vec
= info
.instr
;
1104 unsigned offset
= 0;
1106 for (const Operand
& op
: vec
->operands
) {
1107 if (offset
< dst_offset
) {
1108 offset
+= op
.bytes();
1110 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1114 /* convert this extract into a copy instruction */
1115 instr
->opcode
= aco_opcode::p_parallelcopy
;
1116 instr
->operands
.pop_back();
1117 instr
->operands
[0] = op
;
1119 if (op
.isConstant()) {
1120 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, op
.constantValue64());
1121 } else if (op
.isUndefined()) {
1122 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1124 assert(op
.isTemp());
1125 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1131 case aco_opcode::s_mov_b32
: /* propagate */
1132 case aco_opcode::s_mov_b64
:
1133 case aco_opcode::v_mov_b32
:
1134 case aco_opcode::p_as_uniform
:
1135 if (instr
->definitions
[0].isFixed()) {
1136 /* don't copy-propagate copies into fixed registers */
1137 } else if (instr
->usesModifiers()) {
1139 } else if (instr
->operands
[0].isConstant()) {
1140 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, instr
->operands
[0].constantValue64());
1141 } else if (instr
->operands
[0].isTemp()) {
1142 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1144 assert(instr
->operands
[0].isFixed());
1147 case aco_opcode::p_is_helper
:
1148 if (!ctx
.program
->needs_wqm
)
1149 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, 0u);
1151 case aco_opcode::s_movk_i32
: {
1152 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1153 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1154 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1157 case aco_opcode::v_bfrev_b32
:
1158 case aco_opcode::s_brev_b32
: {
1159 if (instr
->operands
[0].isConstant()) {
1160 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1161 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1165 case aco_opcode::s_bfm_b32
: {
1166 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1167 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1168 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1169 uint32_t v
= ((1u << size
) - 1u) << start
;
1170 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1174 case aco_opcode::v_mul_f16
:
1175 case aco_opcode::v_mul_f32
: { /* omod */
1176 /* TODO: try to move the negate/abs modifier to the consumer instead */
1177 if (instr
->usesModifiers())
1180 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1182 for (unsigned i
= 0; i
< 2; i
++) {
1183 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1184 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1185 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1186 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1187 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1188 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1189 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1190 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1191 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1192 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1201 case aco_opcode::v_and_b32
: { /* abs */
1202 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1203 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1204 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1205 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1206 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1208 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1211 case aco_opcode::v_xor_b32
: { /* neg */
1212 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1213 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1214 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1215 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1216 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1217 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1218 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1219 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1220 instr
->opcode
= aco_opcode::v_or_b32
;
1221 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1223 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1227 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1231 case aco_opcode::v_med3_f16
:
1232 case aco_opcode::v_med3_f32
: { /* clamp */
1233 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1234 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1235 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1236 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1240 bool found_zero
= false, found_one
= false;
1241 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1242 for (unsigned i
= 0; i
< 3; i
++)
1244 if (instr
->operands
[i
].constantEquals(0))
1246 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1251 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1252 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1256 case aco_opcode::v_cndmask_b32
:
1257 if (instr
->operands
[0].constantEquals(0) &&
1258 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1259 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1260 else if (instr
->operands
[0].constantEquals(0) &&
1261 instr
->operands
[1].constantEquals(0x3f800000u
))
1262 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1263 else if (instr
->operands
[0].constantEquals(0) &&
1264 instr
->operands
[1].constantEquals(1))
1265 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1267 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1269 case aco_opcode::v_cmp_lg_u32
:
1270 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1271 instr
->operands
[0].constantEquals(0) &&
1272 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1273 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1275 case aco_opcode::p_phi
:
1276 case aco_opcode::p_linear_phi
: {
1277 /* lower_bool_phis() can create phis like this */
1278 bool all_same_temp
= instr
->operands
[0].isTemp();
1279 /* this check is needed when moving uniform loop counters out of a divergent loop */
1281 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1282 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1283 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1284 all_same_temp
= false;
1286 if (all_same_temp
) {
1287 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1289 bool all_undef
= instr
->operands
[0].isUndefined();
1290 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1291 if (!instr
->operands
[i
].isUndefined())
1295 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1299 case aco_opcode::v_add_u32
:
1300 case aco_opcode::v_add_co_u32
:
1301 case aco_opcode::v_add_co_u32_e64
:
1302 case aco_opcode::s_add_i32
:
1303 case aco_opcode::s_add_u32
:
1304 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1306 case aco_opcode::s_not_b32
:
1307 case aco_opcode::s_not_b64
:
1308 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1309 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1310 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1311 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1312 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1313 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1315 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1317 case aco_opcode::s_and_b32
:
1318 case aco_opcode::s_and_b64
:
1319 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1320 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1321 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1322 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1323 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1325 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1326 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1327 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1328 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1333 case aco_opcode::s_or_b32
:
1334 case aco_opcode::s_or_b64
:
1335 case aco_opcode::s_xor_b32
:
1336 case aco_opcode::s_xor_b64
:
1337 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1338 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1340 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1343 case aco_opcode::s_lshl_b32
:
1344 case aco_opcode::v_or_b32
:
1345 case aco_opcode::v_lshlrev_b32
:
1346 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1348 case aco_opcode::v_min_f32
:
1349 case aco_opcode::v_min_f16
:
1350 case aco_opcode::v_min_u32
:
1351 case aco_opcode::v_min_i32
:
1352 case aco_opcode::v_min_u16
:
1353 case aco_opcode::v_min_i16
:
1354 case aco_opcode::v_max_f32
:
1355 case aco_opcode::v_max_f16
:
1356 case aco_opcode::v_max_u32
:
1357 case aco_opcode::v_max_i32
:
1358 case aco_opcode::v_max_u16
:
1359 case aco_opcode::v_max_i16
:
1360 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1363 case aco_opcode::v_cmp_##cmp##_f16:\
1364 case aco_opcode::v_cmp_##cmp##_f32:\
1365 case aco_opcode::v_cmp_##cmp##_f64:\
1366 case aco_opcode::v_cmp_n##cmp##_f16:\
1367 case aco_opcode::v_cmp_n##cmp##_f32:\
1368 case aco_opcode::v_cmp_n##cmp##_f64:
1375 case aco_opcode::v_cmp_o_f16
:
1376 case aco_opcode::v_cmp_u_f16
:
1377 case aco_opcode::v_cmp_o_f32
:
1378 case aco_opcode::v_cmp_u_f32
:
1379 case aco_opcode::v_cmp_o_f64
:
1380 case aco_opcode::v_cmp_u_f64
:
1382 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1384 case aco_opcode::s_cselect_b64
:
1385 case aco_opcode::s_cselect_b32
:
1386 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1387 instr
->operands
[1].constantEquals(0)) {
1388 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1389 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1391 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1392 /* Flip the operands to get rid of the scc_invert instruction */
1393 std::swap(instr
->operands
[0], instr
->operands
[1]);
1394 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1397 case aco_opcode::p_wqm
:
1398 if (instr
->operands
[0].isTemp() &&
1399 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1400 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1410 aco_opcode unordered
;
1416 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
)
1418 info
->ordered
= aco_opcode::num_opcodes
;
1419 info
->unordered
= aco_opcode::num_opcodes
;
1421 #define CMP2(ord, unord, sz) \
1422 case aco_opcode::v_cmp_##ord##_f##sz:\
1423 case aco_opcode::v_cmp_n##unord##_f##sz:\
1424 info->ordered = aco_opcode::v_cmp_##ord##_f##sz;\
1425 info->unordered = aco_opcode::v_cmp_n##unord##_f##sz;\
1426 info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz : aco_opcode::v_cmp_n##ord##_f##sz;\
1427 info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 : aco_opcode::v_cmp_n##unord##_f32;\
1430 #define CMP(ord, unord) \
1431 CMP2(ord, unord, 16)\
1432 CMP2(ord, unord, 32)\
1433 CMP2(ord, unord, 64)
1442 #define ORD_TEST(sz) \
1443 case aco_opcode::v_cmp_u_f##sz:\
1444 info->f32 = aco_opcode::v_cmp_u_f32;\
1445 info->inverse = aco_opcode::v_cmp_o_f##sz;\
1448 case aco_opcode::v_cmp_o_f##sz:\
1449 info->f32 = aco_opcode::v_cmp_o_f32;\
1450 info->inverse = aco_opcode::v_cmp_u_f##sz;\
1462 aco_opcode
get_ordered(aco_opcode op
)
1465 return get_cmp_info(op
, &info
) ? info
.ordered
: aco_opcode::num_opcodes
;
1468 aco_opcode
get_unordered(aco_opcode op
)
1471 return get_cmp_info(op
, &info
) ? info
.unordered
: aco_opcode::num_opcodes
;
1474 aco_opcode
get_inverse(aco_opcode op
)
1477 return get_cmp_info(op
, &info
) ? info
.inverse
: aco_opcode::num_opcodes
;
1480 aco_opcode
get_f32_cmp(aco_opcode op
)
1483 return get_cmp_info(op
, &info
) ? info
.f32
: aco_opcode::num_opcodes
;
1486 unsigned get_cmp_bitsize(aco_opcode op
)
1489 return get_cmp_info(op
, &info
) ? info
.size
: 0;
1492 bool is_cmp(aco_opcode op
)
1495 return get_cmp_info(op
, &info
) && info
.ordered
!= aco_opcode::num_opcodes
;
1498 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1500 if (ctx
.info
[tmp
.id()].is_temp())
1501 return ctx
.info
[tmp
.id()].temp
.id();
1506 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1508 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1509 for (const Operand
& op
: instr
->operands
) {
1511 ctx
.uses
[op
.tempId()]--;
1516 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1518 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1520 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1523 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1525 if (instr
->definitions
.size() == 2) {
1526 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1527 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1534 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1535 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1536 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1538 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1540 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1543 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1545 bool neg
[2] = {false, false};
1546 bool abs
[2] = {false, false};
1548 Instruction
*op_instr
[2];
1551 unsigned bitsize
= 0;
1552 for (unsigned i
= 0; i
< 2; i
++) {
1553 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1557 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1558 unsigned op_bitsize
= get_cmp_bitsize(op_instr
[i
]->opcode
);
1560 if (get_f32_cmp(op_instr
[i
]->opcode
) != expected_cmp
)
1562 if (bitsize
&& op_bitsize
!= bitsize
)
1564 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1567 if (op_instr
[i
]->isVOP3()) {
1568 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1569 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1571 neg
[i
] = vop3
->neg
[0];
1572 abs
[i
] = vop3
->abs
[0];
1573 opsel
|= (vop3
->opsel
& 1) << i
;
1576 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1577 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1578 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1582 bitsize
= op_bitsize
;
1585 if (op
[1].type() == RegType::sgpr
)
1586 std::swap(op
[0], op
[1]);
1587 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1588 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1591 ctx
.uses
[op
[0].id()]++;
1592 ctx
.uses
[op
[1].id()]++;
1593 decrease_uses(ctx
, op_instr
[0]);
1594 decrease_uses(ctx
, op_instr
[1]);
1596 aco_opcode new_op
= aco_opcode::num_opcodes
;
1599 new_op
= is_or
? aco_opcode::v_cmp_u_f16
: aco_opcode::v_cmp_o_f16
;
1602 new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1605 new_op
= is_or
? aco_opcode::v_cmp_u_f64
: aco_opcode::v_cmp_o_f64
;
1608 Instruction
*new_instr
;
1609 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1610 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1611 for (unsigned i
= 0; i
< 2; i
++) {
1612 vop3
->neg
[i
] = neg
[i
];
1613 vop3
->abs
[i
] = abs
[i
];
1615 vop3
->opsel
= opsel
;
1616 new_instr
= static_cast<Instruction
*>(vop3
);
1618 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1620 new_instr
->operands
[0] = Operand(op
[0]);
1621 new_instr
->operands
[1] = Operand(op
[1]);
1622 new_instr
->definitions
[0] = instr
->definitions
[0];
1624 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1625 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1627 instr
.reset(new_instr
);
1632 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1633 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1634 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1636 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1638 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1641 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1642 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1644 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1645 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1646 if (!nan_test
|| !cmp
)
1649 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1650 std::swap(nan_test
, cmp
);
1651 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1654 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1657 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1659 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1662 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1663 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1664 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1665 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1666 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1668 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1671 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1672 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1673 decrease_uses(ctx
, nan_test
);
1674 decrease_uses(ctx
, cmp
);
1676 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1677 Instruction
*new_instr
;
1678 if (cmp
->isVOP3()) {
1679 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1680 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1681 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1682 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1683 new_vop3
->clamp
= cmp_vop3
->clamp
;
1684 new_vop3
->omod
= cmp_vop3
->omod
;
1685 new_vop3
->opsel
= cmp_vop3
->opsel
;
1686 new_instr
= new_vop3
;
1688 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1690 new_instr
->operands
[0] = cmp
->operands
[0];
1691 new_instr
->operands
[1] = cmp
->operands
[1];
1692 new_instr
->definitions
[0] = instr
->definitions
[0];
1694 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1695 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1697 instr
.reset(new_instr
);
1702 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1703 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1704 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1706 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1708 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1711 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1713 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1714 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1716 if (!nan_test
|| !cmp
)
1719 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1720 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1721 std::swap(nan_test
, cmp
);
1722 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1725 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1728 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1730 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1733 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1734 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1735 if (prop_nan0
!= prop_nan1
)
1738 if (nan_test
->isVOP3()) {
1739 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1740 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1744 int constant_operand
= -1;
1745 for (unsigned i
= 0; i
< 2; i
++) {
1746 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1747 constant_operand
= !i
;
1751 if (constant_operand
== -1)
1755 if (cmp
->operands
[constant_operand
].isConstant()) {
1756 constant
= cmp
->operands
[constant_operand
].constantValue();
1757 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1758 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1759 unsigned id
= original_temp_id(ctx
, tmp
);
1760 if (!ctx
.info
[id
].is_constant_or_literal(32))
1762 constant
= ctx
.info
[id
].val
;
1768 memcpy(&constantf
, &constant
, 4);
1769 if (isnan(constantf
))
1772 if (cmp
->operands
[0].isTemp())
1773 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1774 if (cmp
->operands
[1].isTemp())
1775 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1776 decrease_uses(ctx
, nan_test
);
1777 decrease_uses(ctx
, cmp
);
1779 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1780 Instruction
*new_instr
;
1781 if (cmp
->isVOP3()) {
1782 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1783 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1784 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1785 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1786 new_vop3
->clamp
= cmp_vop3
->clamp
;
1787 new_vop3
->omod
= cmp_vop3
->omod
;
1788 new_vop3
->opsel
= cmp_vop3
->opsel
;
1789 new_instr
= new_vop3
;
1791 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1793 new_instr
->operands
[0] = cmp
->operands
[0];
1794 new_instr
->operands
[1] = cmp
->operands
[1];
1795 new_instr
->definitions
[0] = instr
->definitions
[0];
1797 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1798 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1800 instr
.reset(new_instr
);
1805 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1806 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1808 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1810 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1812 if (!instr
->operands
[0].isTemp())
1815 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1819 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1820 if (new_opcode
== aco_opcode::num_opcodes
)
1823 if (cmp
->operands
[0].isTemp())
1824 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1825 if (cmp
->operands
[1].isTemp())
1826 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1827 decrease_uses(ctx
, cmp
);
1829 Instruction
*new_instr
;
1830 if (cmp
->isVOP3()) {
1831 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1832 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1833 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1834 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1835 new_vop3
->clamp
= cmp_vop3
->clamp
;
1836 new_vop3
->omod
= cmp_vop3
->omod
;
1837 new_vop3
->opsel
= cmp_vop3
->opsel
;
1838 new_instr
= new_vop3
;
1840 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1842 new_instr
->operands
[0] = cmp
->operands
[0];
1843 new_instr
->operands
[1] = cmp
->operands
[1];
1844 new_instr
->definitions
[0] = instr
->definitions
[0];
1846 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1847 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1849 instr
.reset(new_instr
);
1854 /* op1(op2(1, 2), 0) if swap = false
1855 * op1(0, op2(1, 2)) if swap = true */
1856 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1857 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1858 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1859 bool *op1_clamp
, uint8_t *op1_omod
,
1860 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1863 if (op1_instr
->opcode
!= op1
)
1866 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1867 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1869 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1872 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1873 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1875 /* don't support inbetween clamp/omod */
1876 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1879 /* get operands and modifiers and check inbetween modifiers */
1880 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1881 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1884 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1885 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1889 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1890 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1893 if (inbetween_opsel
)
1894 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1895 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1899 shuffle
[shuffle_str
[0] - '0'] = 0;
1900 shuffle
[shuffle_str
[1] - '0'] = 1;
1901 shuffle
[shuffle_str
[2] - '0'] = 2;
1903 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1904 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1905 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1906 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1907 *opsel
|= 1 << shuffle
[0];
1909 for (unsigned i
= 0; i
< 2; i
++) {
1910 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1911 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1912 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1913 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1914 *opsel
|= 1 << shuffle
[i
+ 1];
1917 /* check operands */
1918 if (!check_vop3_operands(ctx
, 3, operands
))
1924 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1925 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1926 bool clamp
, unsigned omod
)
1928 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1929 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1930 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1931 new_instr
->clamp
= clamp
;
1932 new_instr
->omod
= omod
;
1933 new_instr
->opsel
= opsel
;
1934 new_instr
->operands
[0] = operands
[0];
1935 new_instr
->operands
[1] = operands
[1];
1936 new_instr
->operands
[2] = operands
[2];
1937 new_instr
->definitions
[0] = instr
->definitions
[0];
1938 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1940 instr
.reset(new_instr
);
1943 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1945 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1946 (label_omod_success
| label_clamp_success
);
1948 for (unsigned swap
= 0; swap
< 2; swap
++) {
1949 if (!((1 << swap
) & ops
))
1952 Operand operands
[3];
1953 bool neg
[3], abs
[3], clamp
;
1954 uint8_t opsel
= 0, omod
= 0;
1955 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1956 instr
.get(), swap
, shuffle
,
1957 operands
, neg
, abs
, &opsel
,
1958 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1959 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1960 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1961 if (omod_clamp
& label_omod_success
)
1962 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1963 if (omod_clamp
& label_clamp_success
)
1964 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1971 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1973 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1976 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1977 (label_omod_success
| label_clamp_success
);
1979 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1980 * max(-min(a, b), c) -> max3(-a, -b, c) */
1981 for (unsigned swap
= 0; swap
< 2; swap
++) {
1982 Operand operands
[3];
1983 bool neg
[3], abs
[3], clamp
;
1984 uint8_t opsel
= 0, omod
= 0;
1986 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1987 instr
.get(), swap
, "012",
1988 operands
, neg
, abs
, &opsel
,
1989 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1991 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1994 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1995 if (omod_clamp
& label_omod_success
)
1996 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1997 if (omod_clamp
& label_clamp_success
)
1998 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2005 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
2006 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
2007 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
2008 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
2009 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
2010 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
2011 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2014 if (!instr
->operands
[0].isTemp())
2016 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
2019 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
2022 switch (op2_instr
->opcode
) {
2023 case aco_opcode::s_and_b32
:
2024 case aco_opcode::s_or_b32
:
2025 case aco_opcode::s_xor_b32
:
2026 case aco_opcode::s_and_b64
:
2027 case aco_opcode::s_or_b64
:
2028 case aco_opcode::s_xor_b64
:
2034 /* create instruction */
2035 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
2036 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
2037 ctx
.uses
[instr
->operands
[0].tempId()]--;
2038 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
2040 switch (op2_instr
->opcode
) {
2041 case aco_opcode::s_and_b32
:
2042 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
2044 case aco_opcode::s_or_b32
:
2045 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
2047 case aco_opcode::s_xor_b32
:
2048 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
2050 case aco_opcode::s_and_b64
:
2051 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
2053 case aco_opcode::s_or_b64
:
2054 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
2056 case aco_opcode::s_xor_b64
:
2057 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
2066 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
2067 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
2068 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
2069 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
2070 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2072 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
2075 for (unsigned i
= 0; i
< 2; i
++) {
2076 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2077 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
2079 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
2082 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2083 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2086 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2087 instr
->operands
[0] = instr
->operands
[!i
];
2088 instr
->operands
[1] = op2_instr
->operands
[0];
2089 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2091 switch (instr
->opcode
) {
2092 case aco_opcode::s_and_b32
:
2093 instr
->opcode
= aco_opcode::s_andn2_b32
;
2095 case aco_opcode::s_or_b32
:
2096 instr
->opcode
= aco_opcode::s_orn2_b32
;
2098 case aco_opcode::s_and_b64
:
2099 instr
->opcode
= aco_opcode::s_andn2_b64
;
2101 case aco_opcode::s_or_b64
:
2102 instr
->opcode
= aco_opcode::s_orn2_b64
;
2113 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2114 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2116 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
2119 for (unsigned i
= 0; i
< 2; i
++) {
2120 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2121 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
2122 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
2124 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
2127 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2128 if (shift
< 1 || shift
> 4)
2131 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2132 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2135 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2136 instr
->operands
[1] = instr
->operands
[!i
];
2137 instr
->operands
[0] = op2_instr
->operands
[0];
2138 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2140 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2141 aco_opcode::s_lshl2_add_u32
,
2142 aco_opcode::s_lshl3_add_u32
,
2143 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2150 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2152 if (instr
->usesModifiers())
2155 for (unsigned i
= 0; i
< 2; i
++) {
2156 if (!((1 << i
) & ops
))
2158 if (instr
->operands
[i
].isTemp() &&
2159 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2160 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2162 aco_ptr
<Instruction
> new_instr
;
2163 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2164 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2165 } else if (ctx
.program
->chip_class
>= GFX10
||
2166 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2167 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2171 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2172 new_instr
->definitions
[0] = instr
->definitions
[0];
2173 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2174 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2175 new_instr
->definitions
[1].setHint(vcc
);
2176 new_instr
->operands
[0] = Operand(0u);
2177 new_instr
->operands
[1] = instr
->operands
[!i
];
2178 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2179 instr
= std::move(new_instr
);
2180 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2188 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2191 #define MINMAX(type, gfx9) \
2192 case aco_opcode::v_min_##type:\
2193 case aco_opcode::v_max_##type:\
2194 case aco_opcode::v_med3_##type:\
2195 *min = aco_opcode::v_min_##type;\
2196 *max = aco_opcode::v_max_##type;\
2197 *med3 = aco_opcode::v_med3_##type;\
2198 *min3 = aco_opcode::v_min3_##type;\
2199 *max3 = aco_opcode::v_max3_##type;\
2200 *some_gfx9_only = gfx9;\
2214 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2215 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2216 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2217 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2219 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2220 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2221 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2222 aco_opcode other_op
;
2223 if (instr
->opcode
== min
)
2225 else if (instr
->opcode
== max
)
2230 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2231 (label_omod_success
| label_clamp_success
);
2233 for (unsigned swap
= 0; swap
< 2; swap
++) {
2234 Operand operands
[3];
2235 bool neg
[3], abs
[3], clamp
;
2236 uint8_t opsel
= 0, omod
= 0;
2237 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2238 "012", operands
, neg
, abs
, &opsel
,
2239 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2240 int const0_idx
= -1, const1_idx
= -1;
2241 uint32_t const0
= 0, const1
= 0;
2242 for (int i
= 0; i
< 3; i
++) {
2244 if (operands
[i
].isConstant()) {
2245 val
= operands
[i
].constantValue();
2246 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal(32)) {
2247 val
= ctx
.info
[operands
[i
].tempId()].val
;
2251 if (const0_idx
>= 0) {
2259 if (const0_idx
< 0 || const1_idx
< 0)
2262 if (opsel
& (1 << const0_idx
))
2264 if (opsel
& (1 << const1_idx
))
2267 int lower_idx
= const0_idx
;
2269 case aco_opcode::v_min_f32
:
2270 case aco_opcode::v_min_f16
: {
2271 float const0_f
, const1_f
;
2272 if (min
== aco_opcode::v_min_f32
) {
2273 memcpy(&const0_f
, &const0
, 4);
2274 memcpy(&const1_f
, &const1
, 4);
2276 const0_f
= _mesa_half_to_float(const0
);
2277 const1_f
= _mesa_half_to_float(const1
);
2279 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2280 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2281 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2282 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2283 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2286 case aco_opcode::v_min_u32
: {
2287 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2290 case aco_opcode::v_min_u16
: {
2291 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2294 case aco_opcode::v_min_i32
: {
2295 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2296 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2297 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2300 case aco_opcode::v_min_i16
: {
2301 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2302 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2303 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2309 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2311 if (instr
->opcode
== min
) {
2312 if (upper_idx
!= 0 || lower_idx
== 0)
2315 if (upper_idx
== 0 || lower_idx
!= 0)
2319 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2320 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2321 if (omod_clamp
& label_omod_success
)
2322 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2323 if (omod_clamp
& label_clamp_success
)
2324 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2334 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2336 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2337 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2338 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2340 /* find candidates and create the set of sgprs already read */
2341 unsigned sgpr_ids
[2] = {0, 0};
2342 uint32_t operand_mask
= 0;
2343 bool has_literal
= false;
2344 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2345 if (instr
->operands
[i
].isLiteral())
2347 if (!instr
->operands
[i
].isTemp())
2349 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2350 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2351 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2353 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2354 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2355 operand_mask
|= 1u << i
;
2357 unsigned max_sgprs
= 1;
2358 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2363 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2365 /* keep on applying sgprs until there is nothing left to be done */
2366 while (operand_mask
) {
2367 uint32_t sgpr_idx
= 0;
2368 uint32_t sgpr_info_id
= 0;
2369 uint32_t mask
= operand_mask
;
2372 unsigned i
= u_bit_scan(&mask
);
2373 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2374 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2376 sgpr_info_id
= instr
->operands
[i
].tempId();
2379 operand_mask
&= ~(1u << sgpr_idx
);
2381 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2382 * definitively beneficial.
2383 * TODO: this is too conservative because later the use count could be reduced to 1 */
2384 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2387 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2388 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2389 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2392 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2393 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2394 } else if (can_swap_operands(instr
)) {
2395 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2396 instr
->operands
[0] = Operand(sgpr
);
2397 /* swap bits using a 4-entry LUT */
2398 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2399 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2400 } else if (can_use_VOP3(ctx
, instr
)) {
2401 to_VOP3(ctx
, instr
);
2402 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2408 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2409 ctx
.uses
[sgpr_info_id
]--;
2410 ctx
.uses
[sgpr
.id()]++;
2414 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2416 /* check if we could apply omod on predecessor */
2417 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2418 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2419 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2421 unsigned idx
= op0
? 0 : 1;
2422 /* omod was successfully applied */
2423 /* if the omod instruction is v_mad, we also have to change the original add */
2424 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2425 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2426 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2427 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2428 add_instr
->definitions
[0] = instr
->definitions
[0];
2431 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2432 /* check if we have an additional clamp modifier */
2433 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2434 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2435 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2436 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2438 /* change definition ssa-id of modified instruction */
2439 omod_instr
->definitions
[0] = instr
->definitions
[0];
2441 /* change the definition of instr to something unused, e.g. the original omod def */
2442 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2443 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2446 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2447 /* in all other cases, label this instruction as option for multiply-add */
2448 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2452 /* check if we could apply clamp on predecessor */
2453 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2454 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2456 bool found_zero
= false, found_one
= false;
2457 for (unsigned i
= 0; i
< 3; i
++)
2459 if (instr
->operands
[i
].constantEquals(0))
2461 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2466 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2467 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2468 /* clamp was successfully applied */
2469 /* if the clamp instruction is v_mad, we also have to change the original add */
2470 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2471 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2472 add_instr
->definitions
[0] = instr
->definitions
[0];
2474 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2475 /* change definition ssa-id of modified instruction */
2476 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2478 /* change the definition of instr to something unused, e.g. the original omod def */
2479 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2480 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2485 /* omod has no effect if denormals are enabled */
2486 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2487 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2488 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2489 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2490 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2491 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2492 to_VOP3(ctx
, instr
);
2493 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2494 def_info
.set_omod_success(instr
.get());
2495 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2496 to_VOP3(ctx
, instr
);
2497 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2498 def_info
.set_omod_success(instr
.get());
2499 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2500 to_VOP3(ctx
, instr
);
2501 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2502 def_info
.set_omod_success(instr
.get());
2503 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2504 to_VOP3(ctx
, instr
);
2505 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2506 def_info
.set_clamp_success(instr
.get());
2513 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2514 // this would mean that we'd have to fix the instruction uses while value propagation
2516 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2518 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2521 if (instr
->isVALU()) {
2522 if (can_apply_sgprs(instr
))
2523 apply_sgprs(ctx
, instr
);
2524 if (apply_omod_clamp(ctx
, block
, instr
))
2528 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2529 instr
->definitions
[0].setHint(vcc
);
2532 /* TODO: There are still some peephole optimizations that could be done:
2533 * - abs(a - b) -> s_absdiff_i32
2534 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2535 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2536 * These aren't probably too interesting though.
2537 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2538 * probably more useful than the previously mentioned optimizations.
2539 * The various comparison optimizations also currently only work with 32-bit
2542 /* neg(mul(a, b)) -> mul(neg(a), b) */
2543 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2544 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2546 if (!ctx
.info
[val
.id()].is_mul())
2549 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2551 if (mul_instr
->operands
[0].isLiteral())
2553 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2556 /* convert to mul(neg(a), b) */
2557 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2558 Definition def
= instr
->definitions
[0];
2559 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2560 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2561 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2562 instr
->operands
[0] = mul_instr
->operands
[0];
2563 instr
->operands
[1] = mul_instr
->operands
[1];
2564 instr
->definitions
[0] = def
;
2565 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2566 if (mul_instr
->isVOP3()) {
2567 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2568 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2569 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2570 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2571 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2572 new_mul
->omod
= mul
->omod
;
2574 new_mul
->neg
[0] ^= true;
2575 new_mul
->clamp
= false;
2577 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2581 /* combine mul+add -> mad */
2582 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2583 instr
->opcode
== aco_opcode::v_sub_f32
||
2584 instr
->opcode
== aco_opcode::v_subrev_f32
;
2585 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2586 instr
->opcode
== aco_opcode::v_sub_f16
||
2587 instr
->opcode
== aco_opcode::v_subrev_f16
;
2588 if (mad16
|| mad32
) {
2589 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2590 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2591 if (need_fma
&& instr
->definitions
[0].isPrecise())
2593 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2596 uint32_t uses_src0
= UINT32_MAX
;
2597 uint32_t uses_src1
= UINT32_MAX
;
2598 Instruction
* mul_instr
= nullptr;
2599 unsigned add_op_idx
;
2600 /* check if any of the operands is a multiplication */
2601 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2602 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2603 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2604 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2605 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2606 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2608 /* find the 'best' mul instruction to combine with the add */
2609 if (uses_src0
< uses_src1
) {
2610 mul_instr
= op0_info
->instr
;
2612 } else if (uses_src1
< uses_src0
) {
2613 mul_instr
= op1_info
->instr
;
2615 } else if (uses_src0
!= UINT32_MAX
) {
2616 /* tiebreaker: quite random what to pick */
2617 if (op0_info
->instr
->operands
[0].isLiteral()) {
2618 mul_instr
= op1_info
->instr
;
2621 mul_instr
= op0_info
->instr
;
2626 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2627 bool neg
[3] = {false, false, false};
2628 bool abs
[3] = {false, false, false};
2631 op
[0] = mul_instr
->operands
[0];
2632 op
[1] = mul_instr
->operands
[1];
2633 op
[2] = instr
->operands
[add_op_idx
];
2634 // TODO: would be better to check this before selecting a mul instr?
2635 if (!check_vop3_operands(ctx
, 3, op
))
2638 if (mul_instr
->isVOP3()) {
2639 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2640 neg
[0] = vop3
->neg
[0];
2641 neg
[1] = vop3
->neg
[1];
2642 abs
[0] = vop3
->abs
[0];
2643 abs
[1] = vop3
->abs
[1];
2644 /* we cannot use these modifiers between mul and add */
2645 if (vop3
->clamp
|| vop3
->omod
)
2649 /* convert to mad */
2650 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2651 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2653 ctx
.uses
[op
[0].tempId()]++;
2655 ctx
.uses
[op
[1].tempId()]++;
2658 if (instr
->isVOP3()) {
2659 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2660 neg
[2] = vop3
->neg
[add_op_idx
];
2661 abs
[2] = vop3
->abs
[add_op_idx
];
2663 clamp
= vop3
->clamp
;
2664 /* abs of the multiplication result */
2665 if (vop3
->abs
[1 - add_op_idx
]) {
2671 /* neg of the multiplication result */
2672 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2674 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2675 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2676 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2677 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2679 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2681 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2682 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2684 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2685 for (unsigned i
= 0; i
< 3; i
++)
2687 mad
->operands
[i
] = op
[i
];
2688 mad
->neg
[i
] = neg
[i
];
2689 mad
->abs
[i
] = abs
[i
];
2693 mad
->definitions
[0] = instr
->definitions
[0];
2695 /* mark this ssa_def to be re-checked for profitability and literals */
2696 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2697 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2698 instr
.reset(mad
.release());
2702 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2703 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2704 for (unsigned i
= 0; i
< 2; i
++) {
2705 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2706 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2707 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2708 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2709 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2711 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2712 new_instr
->operands
[0] = Operand(0u);
2713 new_instr
->operands
[1] = instr
->operands
[!i
];
2714 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2715 new_instr
->definitions
[0] = instr
->definitions
[0];
2716 instr
.reset(new_instr
.release());
2717 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2721 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2722 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2723 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2724 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2725 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2726 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2727 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2728 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2729 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2730 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2731 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2732 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2733 else if (ctx
.program
->chip_class
>= GFX9
) {
2734 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2735 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2736 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2737 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2738 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2739 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2740 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2742 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2743 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2744 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2745 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2746 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2747 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2748 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2749 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2750 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2751 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2752 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2753 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2754 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2755 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2756 combine_salu_lshl_add(ctx
, instr
);
2757 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2758 combine_salu_not_bitwise(ctx
, instr
);
2759 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2760 if (combine_inverse_comparison(ctx
, instr
)) ;
2761 else combine_salu_not_bitwise(ctx
, instr
);
2762 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2763 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2764 if (combine_ordering_test(ctx
, instr
)) ;
2765 else if (combine_comparison_ordering(ctx
, instr
)) ;
2766 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2767 else combine_salu_n2(ctx
, instr
);
2769 aco_opcode min
, max
, min3
, max3
, med3
;
2770 bool some_gfx9_only
;
2771 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2772 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2773 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2774 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2779 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2781 switch (instr
->opcode
) {
2782 case aco_opcode::s_and_b32
:
2783 case aco_opcode::s_and_b64
:
2784 instr
->opcode
= aco_opcode::s_and_b32
;
2786 case aco_opcode::s_or_b32
:
2787 case aco_opcode::s_or_b64
:
2788 instr
->opcode
= aco_opcode::s_or_b32
;
2790 case aco_opcode::s_xor_b32
:
2791 case aco_opcode::s_xor_b64
:
2792 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2795 /* Don't transform other instructions. They are very unlikely to appear here. */
2799 for (Operand
&op
: instr
->operands
) {
2800 ctx
.uses
[op
.tempId()]--;
2802 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2803 /* Just use the uniform boolean temp. */
2804 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2805 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2806 /* Use the SCC definition of the predecessor instruction.
2807 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2808 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2810 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2811 assert(pred_instr
->definitions
.size() >= 2);
2812 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2813 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2815 unreachable("Invalid operand on uniform bitwise instruction.");
2818 ctx
.uses
[op
.tempId()]++;
2821 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2822 assert(instr
->operands
[0].regClass() == s1
);
2823 assert(instr
->operands
[1].regClass() == s1
);
2827 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2829 const uint32_t threshold
= 4;
2831 if (is_dead(ctx
.uses
, instr
.get())) {
2836 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2837 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2838 unsigned num_used
= 0;
2840 unsigned split_offset
= 0;
2841 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2842 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2845 split_offset
= offset
;
2849 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2850 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2851 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2855 for (Operand
& vec_op
: vec
->operands
) {
2856 if (off
== split_offset
) {
2860 off
+= vec_op
.bytes();
2862 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2863 ctx
.uses
[instr
->operands
[0].tempId()]--;
2864 for (Operand
& vec_op
: vec
->operands
) {
2865 if (vec_op
.isTemp())
2866 ctx
.uses
[vec_op
.tempId()]--;
2869 ctx
.uses
[op
.tempId()]++;
2871 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2872 extract
->operands
[0] = op
;
2873 extract
->definitions
[0] = instr
->definitions
[idx
];
2874 instr
.reset(extract
.release());
2880 if (!done
&& num_used
== 1 &&
2881 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2882 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2883 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2884 extract
->operands
[0] = instr
->operands
[0];
2885 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2886 extract
->definitions
[0] = instr
->definitions
[idx
];
2887 instr
.reset(extract
.release());
2891 mad_info
* mad_info
= NULL
;
2892 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2893 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2894 /* re-check mad instructions */
2895 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2896 ctx
.uses
[mad_info
->mul_temp_id
]++;
2897 if (instr
->operands
[0].isTemp())
2898 ctx
.uses
[instr
->operands
[0].tempId()]--;
2899 if (instr
->operands
[1].isTemp())
2900 ctx
.uses
[instr
->operands
[1].tempId()]--;
2901 instr
.swap(mad_info
->add_instr
);
2904 /* check literals */
2905 else if (!instr
->usesModifiers()) {
2906 /* FMA can only take literals on GFX10+ */
2907 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2908 ctx
.program
->chip_class
< GFX10
)
2911 bool sgpr_used
= false;
2912 uint32_t literal_idx
= 0;
2913 uint32_t literal_uses
= UINT32_MAX
;
2914 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2916 if (instr
->operands
[i
].isConstant() && i
> 0) {
2917 literal_uses
= UINT32_MAX
;
2920 if (!instr
->operands
[i
].isTemp())
2922 unsigned bits
= get_operand_size(instr
, i
);
2923 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2924 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2925 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
)) {
2926 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2929 literal_uses
= UINT32_MAX
;
2932 /* don't break because we still need to check constants */
2933 } else if (!sgpr_used
&&
2934 ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
) &&
2935 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2936 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2941 /* Limit the number of literals to apply to not increase the code
2942 * size too much, but always apply literals for v_mad->v_madak
2943 * because both instructions are 64-bit and this doesn't increase
2945 * TODO: try to apply the literals earlier to lower the number of
2946 * uses below threshold
2948 if (literal_uses
< threshold
|| literal_idx
== 2) {
2949 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2950 mad_info
->check_literal
= true;
2951 mad_info
->literal_idx
= literal_idx
;
2957 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2958 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2959 instr
->operands
.size() &&
2960 instr
->operands
[0].isTemp()) {
2961 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2963 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2964 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2965 instr
->operands
[2].isTemp()) {
2966 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2969 /* check for literals */
2970 if (!instr
->isSALU() && !instr
->isVALU())
2973 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2974 if (instr
->definitions
.size() &&
2975 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2976 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2977 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2979 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2980 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2981 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2982 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2983 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2984 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2990 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2991 return; /* some encodings can't ever take literals */
2993 /* we do not apply the literals yet as we don't know if it is profitable */
2994 Operand
current_literal(s1
);
2996 unsigned literal_id
= 0;
2997 unsigned literal_uses
= UINT32_MAX
;
2998 Operand
literal(s1
);
2999 unsigned num_operands
= 1;
3000 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
3001 num_operands
= instr
->operands
.size();
3002 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
3003 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
3006 unsigned sgpr_ids
[2] = {0, 0};
3007 bool is_literal_sgpr
= false;
3010 /* choose a literal to apply */
3011 for (unsigned i
= 0; i
< num_operands
; i
++) {
3012 Operand op
= instr
->operands
[i
];
3013 unsigned bits
= get_operand_size(instr
, i
);
3015 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
3016 op
.tempId() != sgpr_ids
[0])
3017 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
3019 if (op
.isLiteral()) {
3020 current_literal
= op
;
3022 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal(bits
)) {
3026 if (!alu_can_accept_constant(instr
->opcode
, i
))
3029 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
3030 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
3032 literal
= Operand(ctx
.info
[op
.tempId()].val
);
3033 literal_uses
= ctx
.uses
[op
.tempId()];
3034 literal_id
= op
.tempId();
3037 mask
|= (op
.tempId() == literal_id
) << i
;
3041 /* don't go over the constant bus limit */
3042 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
3043 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
3044 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
3045 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
3046 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
3047 const_bus_limit
= 2;
3049 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
3050 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
3053 if (literal_id
&& literal_uses
< threshold
&&
3054 (current_literal
.isUndefined() ||
3055 (current_literal
.size() == literal
.size() &&
3056 current_literal
.constantValue() == literal
.constantValue()))) {
3057 /* mark the literal to be applied */
3059 unsigned i
= u_bit_scan(&mask
);
3060 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
3061 ctx
.uses
[instr
->operands
[i
].tempId()]--;
3067 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
3069 /* Cleanup Dead Instructions */
3073 /* apply literals on MAD */
3074 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
3075 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
3076 if (info
->check_literal
&&
3077 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
3078 aco_ptr
<Instruction
> new_mad
;
3080 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
3081 if (instr
->opcode
== aco_opcode::v_fma_f32
)
3082 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
3083 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
3084 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
3085 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
3086 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
3088 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
3089 if (info
->literal_idx
== 2) { /* add literal -> madak */
3090 new_mad
->operands
[0] = instr
->operands
[0];
3091 new_mad
->operands
[1] = instr
->operands
[1];
3092 } else { /* mul literal -> madmk */
3093 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
3094 new_mad
->operands
[1] = instr
->operands
[2];
3096 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
3097 new_mad
->definitions
[0] = instr
->definitions
[0];
3098 ctx
.instructions
.emplace_back(std::move(new_mad
));
3103 /* apply literals on other SALU/VALU */
3104 if (instr
->isSALU() || instr
->isVALU()) {
3105 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
3106 Operand op
= instr
->operands
[i
];
3107 unsigned bits
= get_operand_size(instr
, i
);
3108 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal(bits
) && ctx
.uses
[op
.tempId()] == 0) {
3109 Operand
literal(ctx
.info
[op
.tempId()].val
);
3110 if (instr
->isVALU() && i
> 0)
3111 to_VOP3(ctx
, instr
);
3112 instr
->operands
[i
] = literal
;
3117 ctx
.instructions
.emplace_back(std::move(instr
));
3121 void optimize(Program
* program
)
3124 ctx
.program
= program
;
3125 std::vector
<ssa_info
> info(program
->peekAllocationId());
3126 ctx
.info
= info
.data();
3128 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
3129 for (Block
& block
: program
->blocks
) {
3130 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3131 label_instruction(ctx
, block
, instr
);
3134 ctx
.uses
= dead_code_analysis(program
);
3136 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3137 for (Block
& block
: program
->blocks
) {
3138 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3139 combine_instruction(ctx
, block
, instr
);
3142 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3143 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3144 Block
* block
= &(*it
);
3145 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3146 select_instruction(ctx
, *it
);
3149 /* 4. Add literals to instructions */
3150 for (Block
& block
: program
->blocks
) {
3151 ctx
.instructions
.clear();
3152 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3153 apply_literals(ctx
, instr
);
3154 block
.instructions
.swap(ctx
.instructions
);