2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
87 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
88 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
| label_omod2
| label_omod4
| label_omod5
| label_clamp
;
89 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
99 void add_label(Label new_label
)
101 /* Since all labels which use "instr" use it for the same thing
102 * (indicating the defining instruction), there is no need to clear
103 * any other instr labels. */
104 if (new_label
& instr_labels
)
105 label
&= ~temp_labels
; /* instr and temp alias */
107 if (new_label
& temp_labels
) {
108 label
&= ~temp_labels
;
109 label
&= ~instr_labels
; /* instr and temp alias */
112 if (new_label
& val_labels
)
113 label
&= ~val_labels
;
118 void set_vec(Instruction
* vec
)
120 add_label(label_vec
);
126 return label
& label_vec
;
129 void set_constant(uint32_t constant
)
131 add_label(label_constant
);
137 return label
& label_constant
;
140 void set_abs(Temp abs_temp
)
142 add_label(label_abs
);
148 return label
& label_abs
;
151 void set_neg(Temp neg_temp
)
153 add_label(label_neg
);
159 return label
& label_neg
;
162 void set_neg_abs(Temp neg_abs_temp
)
164 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
168 void set_mul(Instruction
* mul
)
170 add_label(label_mul
);
176 return label
& label_mul
;
179 void set_temp(Temp tmp
)
181 add_label(label_temp
);
187 return label
& label_temp
;
190 void set_literal(uint32_t lit
)
192 add_label(label_literal
);
198 return label
& label_literal
;
201 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
203 add_label(label_mad
);
210 return label
& label_mad
;
213 void set_omod2(Temp def
)
215 add_label(label_omod2
);
221 return label
& label_omod2
;
224 void set_omod4(Temp def
)
226 add_label(label_omod4
);
232 return label
& label_omod4
;
235 void set_omod5(Temp def
)
237 add_label(label_omod5
);
243 return label
& label_omod5
;
246 void set_omod_success(Instruction
* omod_instr
)
248 add_label(label_omod_success
);
252 bool is_omod_success()
254 return label
& label_omod_success
;
257 void set_clamp(Temp def
)
259 add_label(label_clamp
);
265 return label
& label_clamp
;
268 void set_clamp_success(Instruction
* clamp_instr
)
270 add_label(label_clamp_success
);
274 bool is_clamp_success()
276 return label
& label_clamp_success
;
281 add_label(label_undefined
);
286 return label
& label_undefined
;
289 void set_vcc(Temp vcc
)
291 add_label(label_vcc
);
297 return label
& label_vcc
;
300 bool is_constant_or_literal()
302 return is_constant() || is_literal();
305 void set_b2f(Temp val
)
307 add_label(label_b2f
);
313 return label
& label_b2f
;
316 void set_add_sub(Instruction
*add_sub_instr
)
318 add_label(label_add_sub
);
319 instr
= add_sub_instr
;
324 return label
& label_add_sub
;
327 void set_bitwise(Instruction
*bitwise_instr
)
329 add_label(label_bitwise
);
330 instr
= bitwise_instr
;
335 return label
& label_bitwise
;
338 void set_minmax(Instruction
*minmax_instr
)
340 add_label(label_minmax
);
341 instr
= minmax_instr
;
346 return label
& label_minmax
;
349 void set_fcmp(Instruction
*fcmp_instr
)
351 add_label(label_fcmp
);
357 return label
& label_fcmp
;
360 void set_uniform_bool(Temp uniform_bool
)
362 add_label(label_uniform_bool
);
366 bool is_uniform_bool()
368 return label
& label_uniform_bool
;
375 std::vector
<aco_ptr
<Instruction
>> instructions
;
377 std::pair
<uint32_t,Temp
> last_literal
;
378 std::vector
<mad_info
> mad_infos
;
379 std::vector
<uint16_t> uses
;
382 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
384 if (instr
->operands
[0].isConstant() ||
385 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
388 switch (instr
->opcode
) {
389 case aco_opcode::v_add_f32
:
390 case aco_opcode::v_mul_f32
:
391 case aco_opcode::v_or_b32
:
392 case aco_opcode::v_and_b32
:
393 case aco_opcode::v_xor_b32
:
394 case aco_opcode::v_max_f32
:
395 case aco_opcode::v_min_f32
:
396 case aco_opcode::v_cmp_eq_f32
:
397 case aco_opcode::v_cmp_lg_f32
:
399 case aco_opcode::v_sub_f32
:
400 instr
->opcode
= aco_opcode::v_subrev_f32
;
402 case aco_opcode::v_cmp_lt_f32
:
403 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
405 case aco_opcode::v_cmp_ge_f32
:
406 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
408 case aco_opcode::v_cmp_lt_i32
:
409 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
416 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
421 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
424 if (instr
->isDPP() || instr
->isSDWA())
427 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
428 instr
->opcode
!= aco_opcode::v_madak_f32
&&
429 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
430 instr
->opcode
!= aco_opcode::v_madak_f16
&&
431 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
432 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
433 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
434 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
435 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
436 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
437 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
440 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
442 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
443 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
444 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
445 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
446 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
449 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
454 aco_ptr
<Instruction
> tmp
= std::move(instr
);
455 Format format
= asVOP3(tmp
->format
);
456 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
457 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
458 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
459 instr
->definitions
[i
] = tmp
->definitions
[i
];
460 if (instr
->definitions
[i
].isTemp()) {
461 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
462 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
463 info
.instr
= instr
.get();
468 /* only covers special cases */
469 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
471 switch (instr
->opcode
) {
472 case aco_opcode::v_interp_p2_f32
:
473 case aco_opcode::v_mac_f32
:
474 case aco_opcode::v_writelane_b32
:
475 case aco_opcode::v_writelane_b32_e64
:
476 case aco_opcode::v_cndmask_b32
:
478 case aco_opcode::s_addk_i32
:
479 case aco_opcode::s_mulk_i32
:
480 case aco_opcode::p_wqm
:
481 case aco_opcode::p_extract_vector
:
482 case aco_opcode::p_split_vector
:
483 case aco_opcode::v_readlane_b32
:
484 case aco_opcode::v_readlane_b32_e64
:
485 case aco_opcode::v_readfirstlane_b32
:
488 if ((instr
->format
== Format::MUBUF
||
489 instr
->format
== Format::MIMG
) &&
490 instr
->definitions
.size() == 1 &&
491 instr
->operands
.size() == 4) {
498 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
500 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
501 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
506 /* check constant bus and literal limitations */
507 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
509 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
510 Operand
literal32(s1
);
511 Operand
literal64(s2
);
512 unsigned num_sgprs
= 0;
513 unsigned sgpr
[] = {0, 0};
515 for (unsigned i
= 0; i
< num_operands
; i
++) {
516 Operand op
= operands
[i
];
518 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
519 /* two reads of the same SGPR count as 1 to the limit */
520 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
522 sgpr
[num_sgprs
++] = op
.tempId();
527 } else if (op
.isLiteral()) {
528 if (ctx
.program
->chip_class
< GFX10
)
531 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
533 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
536 /* Any number of 32-bit literals counts as only 1 to the limit. Same
537 * (but separately) for 64-bit literals. */
538 if (op
.size() == 1 && literal32
.isUndefined()) {
541 } else if (op
.size() == 2 && literal64
.isUndefined()) {
554 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
556 Operand op
= instr
->operands
[op_index
];
560 Temp tmp
= op
.getTemp();
561 if (!ctx
.info
[tmp
.id()].is_add_sub())
564 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
566 switch (add_instr
->opcode
) {
567 case aco_opcode::v_add_u32
:
568 case aco_opcode::v_add_co_u32
:
569 case aco_opcode::s_add_i32
:
570 case aco_opcode::s_add_u32
:
576 if (add_instr
->usesModifiers())
579 for (unsigned i
= 0; i
< 2; i
++) {
580 if (add_instr
->operands
[i
].isConstant()) {
581 *offset
= add_instr
->operands
[i
].constantValue();
582 } else if (add_instr
->operands
[i
].isTemp() &&
583 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
584 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
588 if (!add_instr
->operands
[!i
].isTemp())
591 uint32_t offset2
= 0;
592 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
595 *base
= add_instr
->operands
[!i
].getTemp();
603 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
)
605 // TODO: this functions shouldn't be needed if we store Operand instead of value.
607 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
608 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
612 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
614 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
615 ASSERTED
bool all_const
= false;
616 for (Operand
& op
: instr
->operands
)
617 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
618 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
621 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
623 if (!instr
->operands
[i
].isTemp())
626 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
627 /* propagate undef */
628 if (info
.is_undefined() && is_phi(instr
))
629 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
630 /* propagate reg->reg of same type */
631 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
632 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
633 info
= ctx
.info
[info
.temp
.id()];
636 /* SALU / PSEUDO: propagate inline constants */
637 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
638 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
639 instr
->operands
[i
].setTemp(info
.temp
);
640 info
= ctx
.info
[info
.temp
.id()];
641 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
642 /* propagate vgpr if it can take it */
643 switch (instr
->opcode
) {
644 case aco_opcode::p_create_vector
:
645 case aco_opcode::p_split_vector
:
646 case aco_opcode::p_extract_vector
:
647 case aco_opcode::p_phi
: {
648 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
649 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
651 instr
->operands
[i
] = Operand(info
.temp
);
652 info
= ctx
.info
[info
.temp
.id()];
660 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
661 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
666 /* VALU: propagate neg, abs & inline constants */
667 else if (instr
->isVALU()) {
668 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
669 instr
->operands
[i
].setTemp(info
.temp
);
670 info
= ctx
.info
[info
.temp
.id()];
672 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
675 instr
->operands
[i
] = Operand(info
.temp
);
677 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
679 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
681 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
682 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
683 instr
->operands
[i
].setTemp(info
.temp
);
685 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
688 instr
->operands
[i
].setTemp(info
.temp
);
690 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
692 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
695 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
696 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
697 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
698 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
700 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
701 instr
->operands
[i
] = instr
->operands
[0];
702 instr
->operands
[0] = get_constant_op(ctx
, info
.val
);
704 } else if (can_use_VOP3(ctx
, instr
)) {
706 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
712 /* MUBUF: propagate constants and combine additions */
713 else if (instr
->format
== Format::MUBUF
) {
714 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
717 while (info
.is_temp())
718 info
= ctx
.info
[info
.temp
.id()];
720 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
721 assert(!mubuf
->idxen
);
722 instr
->operands
[i
] = Operand(v1
);
723 mubuf
->offset
+= info
.val
;
724 mubuf
->offen
= false;
726 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
727 instr
->operands
[2] = Operand((uint32_t) 0);
728 mubuf
->offset
+= info
.val
;
730 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
731 assert(!mubuf
->idxen
);
732 instr
->operands
[i
].setTemp(base
);
733 mubuf
->offset
+= offset
;
735 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
736 instr
->operands
[i
].setTemp(base
);
737 mubuf
->offset
+= offset
;
742 /* DS: combine additions */
743 else if (instr
->format
== Format::DS
) {
745 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
748 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
749 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
750 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
751 if (offset
% 4 == 0 &&
752 ds
->offset0
+ (offset
>> 2) <= 255 &&
753 ds
->offset1
+ (offset
>> 2) <= 255) {
754 instr
->operands
[i
].setTemp(base
);
755 ds
->offset0
+= offset
>> 2;
756 ds
->offset1
+= offset
>> 2;
759 if (ds
->offset0
+ offset
<= 65535) {
760 instr
->operands
[i
].setTemp(base
);
761 ds
->offset0
+= offset
;
767 /* SMEM: propagate constants and combine additions */
768 else if (instr
->format
== Format::SMEM
) {
770 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
773 if (i
== 1 && info
.is_constant_or_literal() &&
774 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
775 instr
->operands
[i
] = Operand(info
.val
);
777 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
778 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
780 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
781 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
785 smem
->operands
[1] = Operand(offset
);
786 smem
->operands
.back() = Operand(base
);
788 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
789 new_instr
->operands
[0] = smem
->operands
[0];
790 new_instr
->operands
[1] = Operand(offset
);
791 if (smem
->definitions
.empty())
792 new_instr
->operands
[2] = smem
->operands
[2];
793 new_instr
->operands
.back() = Operand(base
);
794 if (!smem
->definitions
.empty())
795 new_instr
->definitions
[0] = smem
->definitions
[0];
796 new_instr
->can_reorder
= smem
->can_reorder
;
797 new_instr
->barrier
= smem
->barrier
;
798 instr
.reset(new_instr
);
799 smem
= static_cast<SMEM_instruction
*>(instr
.get());
806 /* if this instruction doesn't define anything, return */
807 if (instr
->definitions
.empty())
810 switch (instr
->opcode
) {
811 case aco_opcode::p_create_vector
: {
812 unsigned num_ops
= instr
->operands
.size();
813 for (const Operand
& op
: instr
->operands
) {
814 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
815 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
817 if (num_ops
!= instr
->operands
.size()) {
818 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
819 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
820 instr
->definitions
[0] = old_vec
->definitions
[0];
822 for (Operand
& old_op
: old_vec
->operands
) {
823 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
824 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
825 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
826 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
827 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
828 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
829 instr
->operands
[k
++] = op
;
832 instr
->operands
[k
++] = old_op
;
835 assert(k
== num_ops
);
837 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
838 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
839 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
840 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
843 case aco_opcode::p_split_vector
: {
844 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
846 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
847 assert(instr
->definitions
.size() == vec
->operands
.size());
848 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
849 Operand vec_op
= vec
->operands
[i
];
850 if (vec_op
.isConstant()) {
851 if (vec_op
.isLiteral())
852 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
853 else if (vec_op
.size() == 1)
854 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
856 assert(vec_op
.isTemp());
857 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
862 case aco_opcode::p_extract_vector
: { /* mov */
863 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
865 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
866 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
867 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
869 /* convert this extract into a mov instruction */
870 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
871 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
872 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
873 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
874 instr
->opcode
= opcode
;
875 instr
->format
= format
;
876 while (instr
->operands
.size() > 1)
877 instr
->operands
.pop_back();
878 instr
->operands
[0] = vec_op
;
880 if (vec_op
.isConstant()) {
881 if (vec_op
.isLiteral())
882 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
883 else if (vec_op
.size() == 1)
884 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
886 assert(vec_op
.isTemp());
887 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
892 case aco_opcode::s_mov_b32
: /* propagate */
893 case aco_opcode::s_mov_b64
:
894 case aco_opcode::v_mov_b32
:
895 case aco_opcode::p_as_uniform
:
896 if (instr
->definitions
[0].isFixed()) {
897 /* don't copy-propagate copies into fixed registers */
898 } else if (instr
->usesModifiers()) {
900 } else if (instr
->operands
[0].isConstant()) {
901 if (instr
->operands
[0].isLiteral())
902 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
903 else if (instr
->operands
[0].size() == 1)
904 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
905 } else if (instr
->operands
[0].isTemp()) {
906 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
908 assert(instr
->operands
[0].isFixed());
911 case aco_opcode::p_is_helper
:
912 if (!ctx
.program
->needs_wqm
)
913 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
915 case aco_opcode::s_movk_i32
: {
916 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
917 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
918 if (v
<= 64 || v
>= 0xfffffff0)
919 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
921 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
924 case aco_opcode::v_bfrev_b32
:
925 case aco_opcode::s_brev_b32
: {
926 if (instr
->operands
[0].isConstant()) {
927 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
928 if (v
<= 64 || v
>= 0xfffffff0)
929 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
931 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
935 case aco_opcode::s_bfm_b32
: {
936 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
937 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
938 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
939 uint32_t v
= ((1u << size
) - 1u) << start
;
940 if (v
<= 64 || v
>= 0xfffffff0)
941 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
943 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
946 case aco_opcode::v_mul_f32
: { /* omod */
947 /* TODO: try to move the negate/abs modifier to the consumer instead */
948 if (instr
->usesModifiers())
951 for (unsigned i
= 0; i
< 2; i
++) {
952 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
953 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
954 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
955 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
956 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
957 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
958 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
959 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
960 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
961 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
970 case aco_opcode::v_and_b32
: /* abs */
971 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
972 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
973 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
975 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
977 case aco_opcode::v_xor_b32
: { /* neg */
978 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
979 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
980 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
981 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
982 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
983 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
984 instr
->opcode
= aco_opcode::v_or_b32
;
985 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
987 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
991 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
995 case aco_opcode::v_med3_f32
: { /* clamp */
996 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
997 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
998 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
999 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1003 bool found_zero
= false, found_one
= false;
1004 for (unsigned i
= 0; i
< 3; i
++)
1006 if (instr
->operands
[i
].constantEquals(0))
1008 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1013 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1014 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1018 case aco_opcode::v_cndmask_b32
:
1019 if (instr
->operands
[0].constantEquals(0) &&
1020 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1021 instr
->operands
[2].isTemp())
1022 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1023 else if (instr
->operands
[0].constantEquals(0) &&
1024 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1025 instr
->operands
[2].isTemp())
1026 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1028 case aco_opcode::v_cmp_lg_u32
:
1029 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1030 instr
->operands
[0].constantEquals(0) &&
1031 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1032 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1034 case aco_opcode::p_phi
:
1035 case aco_opcode::p_linear_phi
: {
1036 /* lower_bool_phis() can create phis like this */
1037 bool all_same_temp
= instr
->operands
[0].isTemp();
1038 /* this check is needed when moving uniform loop counters out of a divergent loop */
1040 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1041 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1042 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1043 all_same_temp
= false;
1045 if (all_same_temp
) {
1046 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1048 bool all_undef
= instr
->operands
[0].isUndefined();
1049 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1050 if (!instr
->operands
[i
].isUndefined())
1054 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1058 case aco_opcode::v_add_u32
:
1059 case aco_opcode::v_add_co_u32
:
1060 case aco_opcode::s_add_i32
:
1061 case aco_opcode::s_add_u32
:
1062 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1064 case aco_opcode::s_and_b32
:
1065 case aco_opcode::s_and_b64
:
1066 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1067 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1068 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1071 case aco_opcode::s_not_b32
:
1072 case aco_opcode::s_not_b64
:
1073 case aco_opcode::s_or_b32
:
1074 case aco_opcode::s_or_b64
:
1075 case aco_opcode::s_xor_b32
:
1076 case aco_opcode::s_xor_b64
:
1077 case aco_opcode::s_lshl_b32
:
1078 case aco_opcode::v_or_b32
:
1079 case aco_opcode::v_lshlrev_b32
:
1080 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1082 case aco_opcode::v_min_f32
:
1083 case aco_opcode::v_min_f16
:
1084 case aco_opcode::v_min_u32
:
1085 case aco_opcode::v_min_i32
:
1086 case aco_opcode::v_min_u16
:
1087 case aco_opcode::v_min_i16
:
1088 case aco_opcode::v_max_f32
:
1089 case aco_opcode::v_max_f16
:
1090 case aco_opcode::v_max_u32
:
1091 case aco_opcode::v_max_i32
:
1092 case aco_opcode::v_max_u16
:
1093 case aco_opcode::v_max_i16
:
1094 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1096 case aco_opcode::v_cmp_lt_f32
:
1097 case aco_opcode::v_cmp_eq_f32
:
1098 case aco_opcode::v_cmp_le_f32
:
1099 case aco_opcode::v_cmp_gt_f32
:
1100 case aco_opcode::v_cmp_lg_f32
:
1101 case aco_opcode::v_cmp_ge_f32
:
1102 case aco_opcode::v_cmp_o_f32
:
1103 case aco_opcode::v_cmp_u_f32
:
1104 case aco_opcode::v_cmp_nge_f32
:
1105 case aco_opcode::v_cmp_nlg_f32
:
1106 case aco_opcode::v_cmp_ngt_f32
:
1107 case aco_opcode::v_cmp_nle_f32
:
1108 case aco_opcode::v_cmp_neq_f32
:
1109 case aco_opcode::v_cmp_nlt_f32
:
1110 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1112 case aco_opcode::s_cselect_b64
:
1113 case aco_opcode::s_cselect_b32
:
1114 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1115 instr
->operands
[1].constantEquals(0)) {
1116 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1117 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1125 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1127 *ordered
= *unordered
= op
;
1129 #define CMP(ord, unord) \
1130 case aco_opcode::v_cmp_##ord##_f32:\
1131 case aco_opcode::v_cmp_n##unord##_f32:\
1132 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1133 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1134 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1148 aco_opcode
get_ordered(aco_opcode op
)
1150 aco_opcode ordered
, unordered
, inverse
;
1151 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1154 aco_opcode
get_unordered(aco_opcode op
)
1156 aco_opcode ordered
, unordered
, inverse
;
1157 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1160 aco_opcode
get_inverse(aco_opcode op
)
1162 aco_opcode ordered
, unordered
, inverse
;
1163 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1166 bool is_cmp(aco_opcode op
)
1168 aco_opcode ordered
, unordered
, inverse
;
1169 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1172 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1174 if (ctx
.info
[tmp
.id()].is_temp())
1175 return ctx
.info
[tmp
.id()].temp
.id();
1180 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1182 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1183 for (const Operand
& op
: instr
->operands
) {
1185 ctx
.uses
[op
.tempId()]--;
1190 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1192 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1194 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1197 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1199 if (instr
->definitions
.size() == 2) {
1200 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1201 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1208 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1209 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1210 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1212 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1214 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1217 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1219 bool neg
[2] = {false, false};
1220 bool abs
[2] = {false, false};
1222 Instruction
*op_instr
[2];
1225 for (unsigned i
= 0; i
< 2; i
++) {
1226 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1230 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1232 if (op_instr
[i
]->opcode
!= expected_cmp
)
1234 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1237 if (op_instr
[i
]->isVOP3()) {
1238 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1239 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1241 neg
[i
] = vop3
->neg
[0];
1242 abs
[i
] = vop3
->abs
[0];
1243 opsel
|= (vop3
->opsel
& 1) << i
;
1246 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1247 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1248 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1254 if (op
[1].type() == RegType::sgpr
)
1255 std::swap(op
[0], op
[1]);
1256 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1257 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1260 ctx
.uses
[op
[0].id()]++;
1261 ctx
.uses
[op
[1].id()]++;
1262 decrease_uses(ctx
, op_instr
[0]);
1263 decrease_uses(ctx
, op_instr
[1]);
1265 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1266 Instruction
*new_instr
;
1267 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1268 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1269 for (unsigned i
= 0; i
< 2; i
++) {
1270 vop3
->neg
[i
] = neg
[i
];
1271 vop3
->abs
[i
] = abs
[i
];
1273 vop3
->opsel
= opsel
;
1274 new_instr
= static_cast<Instruction
*>(vop3
);
1276 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1278 new_instr
->operands
[0] = Operand(op
[0]);
1279 new_instr
->operands
[1] = Operand(op
[1]);
1280 new_instr
->definitions
[0] = instr
->definitions
[0];
1282 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1283 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1285 instr
.reset(new_instr
);
1290 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1291 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1292 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1294 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1296 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1299 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1300 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1302 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1303 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1304 if (!nan_test
|| !cmp
)
1307 if (cmp
->opcode
== expected_nan_test
)
1308 std::swap(nan_test
, cmp
);
1309 else if (nan_test
->opcode
!= expected_nan_test
)
1312 if (!is_cmp(cmp
->opcode
))
1315 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1317 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1320 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1321 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1322 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1323 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1324 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1326 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1329 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1330 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1331 decrease_uses(ctx
, nan_test
);
1332 decrease_uses(ctx
, cmp
);
1334 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1335 Instruction
*new_instr
;
1336 if (cmp
->isVOP3()) {
1337 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1338 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1339 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1340 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1341 new_vop3
->clamp
= cmp_vop3
->clamp
;
1342 new_vop3
->omod
= cmp_vop3
->omod
;
1343 new_vop3
->opsel
= cmp_vop3
->opsel
;
1344 new_instr
= new_vop3
;
1346 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1348 new_instr
->operands
[0] = cmp
->operands
[0];
1349 new_instr
->operands
[1] = cmp
->operands
[1];
1350 new_instr
->definitions
[0] = instr
->definitions
[0];
1352 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1353 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1355 instr
.reset(new_instr
);
1360 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1361 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1362 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1364 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1366 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1369 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1371 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1372 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1374 if (!nan_test
|| !cmp
)
1377 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1378 if (cmp
->opcode
== expected_nan_test
)
1379 std::swap(nan_test
, cmp
);
1380 else if (nan_test
->opcode
!= expected_nan_test
)
1383 if (!is_cmp(cmp
->opcode
))
1386 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1388 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1391 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1392 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1393 if (prop_nan0
!= prop_nan1
)
1396 if (nan_test
->isVOP3()) {
1397 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1398 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1402 int constant_operand
= -1;
1403 for (unsigned i
= 0; i
< 2; i
++) {
1404 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1405 constant_operand
= !i
;
1409 if (constant_operand
== -1)
1413 if (cmp
->operands
[constant_operand
].isConstant()) {
1414 constant
= cmp
->operands
[constant_operand
].constantValue();
1415 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1416 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1417 unsigned id
= original_temp_id(ctx
, tmp
);
1418 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1420 constant
= ctx
.info
[id
].val
;
1426 memcpy(&constantf
, &constant
, 4);
1427 if (isnan(constantf
))
1430 if (cmp
->operands
[0].isTemp())
1431 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1432 if (cmp
->operands
[1].isTemp())
1433 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1434 decrease_uses(ctx
, nan_test
);
1435 decrease_uses(ctx
, cmp
);
1437 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1438 Instruction
*new_instr
;
1439 if (cmp
->isVOP3()) {
1440 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1441 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1442 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1443 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1444 new_vop3
->clamp
= cmp_vop3
->clamp
;
1445 new_vop3
->omod
= cmp_vop3
->omod
;
1446 new_vop3
->opsel
= cmp_vop3
->opsel
;
1447 new_instr
= new_vop3
;
1449 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1451 new_instr
->operands
[0] = cmp
->operands
[0];
1452 new_instr
->operands
[1] = cmp
->operands
[1];
1453 new_instr
->definitions
[0] = instr
->definitions
[0];
1455 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1456 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1458 instr
.reset(new_instr
);
1463 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1464 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1466 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1468 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1470 if (!instr
->operands
[0].isTemp())
1473 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1477 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1478 if (new_opcode
== aco_opcode::last_opcode
)
1481 if (cmp
->operands
[0].isTemp())
1482 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1483 if (cmp
->operands
[1].isTemp())
1484 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1485 decrease_uses(ctx
, cmp
);
1487 Instruction
*new_instr
;
1488 if (cmp
->isVOP3()) {
1489 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1490 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1491 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1492 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1493 new_vop3
->clamp
= cmp_vop3
->clamp
;
1494 new_vop3
->omod
= cmp_vop3
->omod
;
1495 new_vop3
->opsel
= cmp_vop3
->opsel
;
1496 new_instr
= new_vop3
;
1498 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1500 new_instr
->operands
[0] = cmp
->operands
[0];
1501 new_instr
->operands
[1] = cmp
->operands
[1];
1502 new_instr
->definitions
[0] = instr
->definitions
[0];
1504 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1505 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1507 instr
.reset(new_instr
);
1512 /* op1(op2(1, 2), 0) if swap = false
1513 * op1(0, op2(1, 2)) if swap = true */
1514 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1515 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1516 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1517 bool *op1_clamp
, uint8_t *op1_omod
,
1518 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1521 if (op1_instr
->opcode
!= op1
)
1524 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1525 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1528 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1529 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1531 /* don't support inbetween clamp/omod */
1532 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1535 /* get operands and modifiers and check inbetween modifiers */
1536 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1537 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1540 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1541 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1545 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1546 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1549 if (inbetween_opsel
)
1550 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1551 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1555 shuffle
[shuffle_str
[0] - '0'] = 0;
1556 shuffle
[shuffle_str
[1] - '0'] = 1;
1557 shuffle
[shuffle_str
[2] - '0'] = 2;
1559 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1560 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1561 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1562 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1563 *opsel
|= 1 << shuffle
[0];
1565 for (unsigned i
= 0; i
< 2; i
++) {
1566 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1567 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1568 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1569 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1570 *opsel
|= 1 << shuffle
[i
+ 1];
1573 /* check operands */
1574 if (!check_vop3_operands(ctx
, 3, operands
))
1580 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1581 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1582 bool clamp
, unsigned omod
)
1584 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1585 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1586 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1587 new_instr
->clamp
= clamp
;
1588 new_instr
->omod
= omod
;
1589 new_instr
->opsel
= opsel
;
1590 new_instr
->operands
[0] = operands
[0];
1591 new_instr
->operands
[1] = operands
[1];
1592 new_instr
->operands
[2] = operands
[2];
1593 new_instr
->definitions
[0] = instr
->definitions
[0];
1594 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1596 instr
.reset(new_instr
);
1599 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1601 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1602 (label_omod_success
| label_clamp_success
);
1604 for (unsigned swap
= 0; swap
< 2; swap
++) {
1605 if (!((1 << swap
) & ops
))
1608 Operand operands
[3];
1609 bool neg
[3], abs
[3], clamp
;
1610 uint8_t opsel
= 0, omod
= 0;
1611 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1612 instr
.get(), swap
, shuffle
,
1613 operands
, neg
, abs
, &opsel
,
1614 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1615 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1616 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1617 if (omod_clamp
& label_omod_success
)
1618 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1619 if (omod_clamp
& label_clamp_success
)
1620 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1627 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1628 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1629 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1630 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1631 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1632 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1633 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1636 if (!instr
->operands
[0].isTemp())
1638 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1641 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1644 switch (op2_instr
->opcode
) {
1645 case aco_opcode::s_and_b32
:
1646 case aco_opcode::s_or_b32
:
1647 case aco_opcode::s_xor_b32
:
1648 case aco_opcode::s_and_b64
:
1649 case aco_opcode::s_or_b64
:
1650 case aco_opcode::s_xor_b64
:
1656 /* create instruction */
1657 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1658 ctx
.uses
[instr
->operands
[0].tempId()]--;
1659 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1661 switch (op2_instr
->opcode
) {
1662 case aco_opcode::s_and_b32
:
1663 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1665 case aco_opcode::s_or_b32
:
1666 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1668 case aco_opcode::s_xor_b32
:
1669 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1671 case aco_opcode::s_and_b64
:
1672 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1674 case aco_opcode::s_or_b64
:
1675 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1677 case aco_opcode::s_xor_b64
:
1678 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1687 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1688 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1689 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1690 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1691 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1693 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1696 for (unsigned i
= 0; i
< 2; i
++) {
1697 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1698 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1701 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1702 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1705 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1706 instr
->operands
[0] = instr
->operands
[!i
];
1707 instr
->operands
[1] = op2_instr
->operands
[0];
1708 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1710 switch (instr
->opcode
) {
1711 case aco_opcode::s_and_b32
:
1712 instr
->opcode
= aco_opcode::s_andn2_b32
;
1714 case aco_opcode::s_or_b32
:
1715 instr
->opcode
= aco_opcode::s_orn2_b32
;
1717 case aco_opcode::s_and_b64
:
1718 instr
->opcode
= aco_opcode::s_andn2_b64
;
1720 case aco_opcode::s_or_b64
:
1721 instr
->opcode
= aco_opcode::s_orn2_b64
;
1732 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1733 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1735 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1738 for (unsigned i
= 0; i
< 2; i
++) {
1739 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1740 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1743 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1744 if (shift
< 1 || shift
> 4)
1747 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1748 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1751 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1752 instr
->operands
[1] = instr
->operands
[!i
];
1753 instr
->operands
[0] = op2_instr
->operands
[0];
1754 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1756 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1757 aco_opcode::s_lshl2_add_u32
,
1758 aco_opcode::s_lshl3_add_u32
,
1759 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1766 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1769 #define MINMAX(type, gfx9) \
1770 case aco_opcode::v_min_##type:\
1771 case aco_opcode::v_max_##type:\
1772 case aco_opcode::v_med3_##type:\
1773 *min = aco_opcode::v_min_##type;\
1774 *max = aco_opcode::v_max_##type;\
1775 *med3 = aco_opcode::v_med3_##type;\
1776 *min3 = aco_opcode::v_min3_##type;\
1777 *max3 = aco_opcode::v_max3_##type;\
1778 *some_gfx9_only = gfx9;\
1792 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1793 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1794 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1795 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1797 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1798 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1799 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1800 aco_opcode other_op
;
1801 if (instr
->opcode
== min
)
1803 else if (instr
->opcode
== max
)
1808 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1809 (label_omod_success
| label_clamp_success
);
1811 for (unsigned swap
= 0; swap
< 2; swap
++) {
1812 Operand operands
[3];
1813 bool neg
[3], abs
[3], clamp
;
1814 uint8_t opsel
= 0, omod
= 0;
1815 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1816 "012", operands
, neg
, abs
, &opsel
,
1817 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1818 int const0_idx
= -1, const1_idx
= -1;
1819 uint32_t const0
= 0, const1
= 0;
1820 for (int i
= 0; i
< 3; i
++) {
1822 if (operands
[i
].isConstant()) {
1823 val
= operands
[i
].constantValue();
1824 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1825 val
= ctx
.info
[operands
[i
].tempId()].val
;
1829 if (const0_idx
>= 0) {
1837 if (const0_idx
< 0 || const1_idx
< 0)
1840 if (opsel
& (1 << const0_idx
))
1842 if (opsel
& (1 << const1_idx
))
1845 int lower_idx
= const0_idx
;
1847 case aco_opcode::v_min_f32
:
1848 case aco_opcode::v_min_f16
: {
1849 float const0_f
, const1_f
;
1850 if (min
== aco_opcode::v_min_f32
) {
1851 memcpy(&const0_f
, &const0
, 4);
1852 memcpy(&const1_f
, &const1
, 4);
1854 const0_f
= _mesa_half_to_float(const0
);
1855 const1_f
= _mesa_half_to_float(const1
);
1857 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1858 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1859 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1860 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1861 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1864 case aco_opcode::v_min_u32
: {
1865 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1868 case aco_opcode::v_min_u16
: {
1869 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1872 case aco_opcode::v_min_i32
: {
1873 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1874 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1875 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1878 case aco_opcode::v_min_i16
: {
1879 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1880 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1881 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1887 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1889 if (instr
->opcode
== min
) {
1890 if (upper_idx
!= 0 || lower_idx
== 0)
1893 if (upper_idx
== 0 || lower_idx
!= 0)
1897 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1898 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1899 if (omod_clamp
& label_omod_success
)
1900 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1901 if (omod_clamp
& label_clamp_success
)
1902 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1912 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1914 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
1915 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
1916 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
1918 /* find candidates and create the set of sgprs already read */
1919 unsigned sgpr_ids
[2] = {0, 0};
1920 uint32_t operand_mask
= 0;
1921 bool has_literal
= false;
1922 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1923 if (instr
->operands
[i
].isLiteral())
1925 if (!instr
->operands
[i
].isTemp())
1927 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1928 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
1929 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
1931 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1932 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
1933 operand_mask
|= 1u << i
;
1935 unsigned max_sgprs
= 1;
1936 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
1941 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
1943 /* keep on applying sgprs until there is nothing left to be done */
1944 while (operand_mask
) {
1945 uint32_t sgpr_idx
= 0;
1946 uint32_t sgpr_info_id
= 0;
1947 uint32_t mask
= operand_mask
;
1950 unsigned i
= u_bit_scan(&mask
);
1951 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1952 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1954 sgpr_info_id
= instr
->operands
[i
].tempId();
1957 operand_mask
&= ~(1u << sgpr_idx
);
1959 /* Applying two sgprs require making it VOP3, so don't do it unless it's
1960 * definitively beneficial.
1961 * TODO: this is too conservative because later the use count could be reduced to 1 */
1962 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
1965 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
1966 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
1967 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
1970 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1971 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
1972 } else if (can_swap_operands(instr
)) {
1973 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1974 instr
->operands
[0] = Operand(sgpr
);
1975 /* swap bits using a 4-entry LUT */
1976 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
1977 operand_mask
= (operand_mask
& ~0x3) | swapped
;
1978 } else if (can_use_VOP3(ctx
, instr
)) {
1979 to_VOP3(ctx
, instr
);
1980 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
1985 sgpr_ids
[num_sgprs
++] = sgpr
.id();
1986 ctx
.uses
[sgpr_info_id
]--;
1987 ctx
.uses
[sgpr
.id()]++;
1991 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1993 /* check if we could apply omod on predecessor */
1994 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1995 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
1996 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
1998 unsigned idx
= op0
? 0 : 1;
1999 /* omod was successfully applied */
2000 /* if the omod instruction is v_mad, we also have to change the original add */
2001 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2002 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2003 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2004 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2005 add_instr
->definitions
[0] = instr
->definitions
[0];
2008 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2009 /* check if we have an additional clamp modifier */
2010 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2011 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2012 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2013 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2015 /* change definition ssa-id of modified instruction */
2016 omod_instr
->definitions
[0] = instr
->definitions
[0];
2018 /* change the definition of instr to something unused, e.g. the original omod def */
2019 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2020 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2023 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2024 /* in all other cases, label this instruction as option for multiply-add */
2025 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2029 /* check if we could apply clamp on predecessor */
2030 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2032 bool found_zero
= false, found_one
= false;
2033 for (unsigned i
= 0; i
< 3; i
++)
2035 if (instr
->operands
[i
].constantEquals(0))
2037 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2042 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2043 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2044 /* clamp was successfully applied */
2045 /* if the clamp instruction is v_mad, we also have to change the original add */
2046 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2047 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2048 add_instr
->definitions
[0] = instr
->definitions
[0];
2050 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2051 /* change definition ssa-id of modified instruction */
2052 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2054 /* change the definition of instr to something unused, e.g. the original omod def */
2055 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2056 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2061 /* omod has no effect if denormals are enabled */
2062 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2064 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2065 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2066 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2067 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2068 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2069 to_VOP3(ctx
, instr
);
2070 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2071 def_info
.set_omod_success(instr
.get());
2072 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2073 to_VOP3(ctx
, instr
);
2074 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2075 def_info
.set_omod_success(instr
.get());
2076 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2077 to_VOP3(ctx
, instr
);
2078 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2079 def_info
.set_omod_success(instr
.get());
2080 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2081 to_VOP3(ctx
, instr
);
2082 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2083 def_info
.set_clamp_success(instr
.get());
2090 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2091 // this would mean that we'd have to fix the instruction uses while value propagation
2093 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2095 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2098 if (instr
->isVALU()) {
2099 if (can_apply_sgprs(instr
))
2100 apply_sgprs(ctx
, instr
);
2101 if (apply_omod_clamp(ctx
, block
, instr
))
2105 /* TODO: There are still some peephole optimizations that could be done:
2106 * - abs(a - b) -> s_absdiff_i32
2107 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2108 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2109 * These aren't probably too interesting though.
2110 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2111 * probably more useful than the previously mentioned optimizations.
2112 * The various comparison optimizations also currently only work with 32-bit
2115 /* neg(mul(a, b)) -> mul(neg(a), b) */
2116 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2117 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2119 if (!ctx
.info
[val
.id()].is_mul())
2122 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2124 if (mul_instr
->operands
[0].isLiteral())
2126 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2129 /* convert to mul(neg(a), b) */
2130 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2131 Definition def
= instr
->definitions
[0];
2132 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2133 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2134 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2135 instr
->operands
[0] = mul_instr
->operands
[0];
2136 instr
->operands
[1] = mul_instr
->operands
[1];
2137 instr
->definitions
[0] = def
;
2138 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2139 if (mul_instr
->isVOP3()) {
2140 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2141 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2142 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2143 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2144 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2145 new_mul
->omod
= mul
->omod
;
2147 new_mul
->neg
[0] ^= true;
2148 new_mul
->clamp
= false;
2150 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2153 /* combine mul+add -> mad */
2154 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2155 instr
->opcode
== aco_opcode::v_sub_f32
||
2156 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2157 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2158 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2160 uint32_t uses_src0
= UINT32_MAX
;
2161 uint32_t uses_src1
= UINT32_MAX
;
2162 Instruction
* mul_instr
= nullptr;
2163 unsigned add_op_idx
;
2164 /* check if any of the operands is a multiplication */
2165 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2166 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2167 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2168 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2170 /* find the 'best' mul instruction to combine with the add */
2171 if (uses_src0
< uses_src1
) {
2172 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2174 } else if (uses_src1
< uses_src0
) {
2175 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2177 } else if (uses_src0
!= UINT32_MAX
) {
2178 /* tiebreaker: quite random what to pick */
2179 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2180 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2183 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2188 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2189 bool neg
[3] = {false, false, false};
2190 bool abs
[3] = {false, false, false};
2193 op
[0] = mul_instr
->operands
[0];
2194 op
[1] = mul_instr
->operands
[1];
2195 op
[2] = instr
->operands
[add_op_idx
];
2196 // TODO: would be better to check this before selecting a mul instr?
2197 if (!check_vop3_operands(ctx
, 3, op
))
2200 if (mul_instr
->isVOP3()) {
2201 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2202 neg
[0] = vop3
->neg
[0];
2203 neg
[1] = vop3
->neg
[1];
2204 abs
[0] = vop3
->abs
[0];
2205 abs
[1] = vop3
->abs
[1];
2206 /* we cannot use these modifiers between mul and add */
2207 if (vop3
->clamp
|| vop3
->omod
)
2211 /* convert to mad */
2212 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2213 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2215 ctx
.uses
[op
[0].tempId()]++;
2217 ctx
.uses
[op
[1].tempId()]++;
2220 if (instr
->isVOP3()) {
2221 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2222 neg
[2] = vop3
->neg
[add_op_idx
];
2223 abs
[2] = vop3
->abs
[add_op_idx
];
2225 clamp
= vop3
->clamp
;
2226 /* abs of the multiplication result */
2227 if (vop3
->abs
[1 - add_op_idx
]) {
2233 /* neg of the multiplication result */
2234 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2236 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2237 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2238 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2239 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2241 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2242 for (unsigned i
= 0; i
< 3; i
++)
2244 mad
->operands
[i
] = op
[i
];
2245 mad
->neg
[i
] = neg
[i
];
2246 mad
->abs
[i
] = abs
[i
];
2250 mad
->definitions
[0] = instr
->definitions
[0];
2252 /* mark this ssa_def to be re-checked for profitability and literals */
2253 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2254 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2255 instr
.reset(mad
.release());
2259 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2260 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2261 for (unsigned i
= 0; i
< 2; i
++) {
2262 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2263 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2264 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2265 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2266 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2268 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2269 new_instr
->operands
[0] = Operand(0u);
2270 new_instr
->operands
[1] = instr
->operands
[!i
];
2271 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2272 new_instr
->definitions
[0] = instr
->definitions
[0];
2273 instr
.reset(new_instr
.release());
2274 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2278 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2279 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2280 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2281 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2282 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2283 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2284 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2285 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2286 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2287 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2288 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2289 combine_salu_lshl_add(ctx
, instr
);
2290 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2291 combine_salu_not_bitwise(ctx
, instr
);
2292 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2293 if (combine_inverse_comparison(ctx
, instr
)) ;
2294 else combine_salu_not_bitwise(ctx
, instr
);
2295 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2296 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2297 if (combine_ordering_test(ctx
, instr
)) ;
2298 else if (combine_comparison_ordering(ctx
, instr
)) ;
2299 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2300 else combine_salu_n2(ctx
, instr
);
2302 aco_opcode min
, max
, min3
, max3
, med3
;
2303 bool some_gfx9_only
;
2304 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2305 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2306 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2307 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2313 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2315 const uint32_t threshold
= 4;
2317 if (is_dead(ctx
.uses
, instr
.get())) {
2322 /* convert split_vector into extract_vector if only one definition is ever used */
2323 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2324 unsigned num_used
= 0;
2326 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2327 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2332 if (num_used
== 1) {
2333 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2334 extract
->operands
[0] = instr
->operands
[0];
2335 extract
->operands
[1] = Operand((uint32_t) idx
);
2336 extract
->definitions
[0] = instr
->definitions
[idx
];
2337 instr
.reset(extract
.release());
2341 mad_info
* mad_info
= NULL
;
2342 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2343 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2344 /* re-check mad instructions */
2345 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2346 ctx
.uses
[mad_info
->mul_temp_id
]++;
2347 if (instr
->operands
[0].isTemp())
2348 ctx
.uses
[instr
->operands
[0].tempId()]--;
2349 if (instr
->operands
[1].isTemp())
2350 ctx
.uses
[instr
->operands
[1].tempId()]--;
2351 instr
.swap(mad_info
->add_instr
);
2354 /* check literals */
2355 else if (!instr
->usesModifiers()) {
2356 bool sgpr_used
= false;
2357 uint32_t literal_idx
= 0;
2358 uint32_t literal_uses
= UINT32_MAX
;
2359 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2361 if (instr
->operands
[i
].isConstant() && i
> 0) {
2362 literal_uses
= UINT32_MAX
;
2365 if (!instr
->operands
[i
].isTemp())
2367 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2368 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2369 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2370 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2373 literal_uses
= UINT32_MAX
;
2376 /* don't break because we still need to check constants */
2377 } else if (!sgpr_used
&&
2378 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2379 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2380 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2384 if (literal_uses
< threshold
) {
2385 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2386 mad_info
->check_literal
= true;
2387 mad_info
->literal_idx
= literal_idx
;
2393 /* check for literals */
2394 if (!instr
->isSALU() && !instr
->isVALU())
2397 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2398 return; /* some encodings can't ever take literals */
2400 /* we do not apply the literals yet as we don't know if it is profitable */
2401 Operand
current_literal(s1
);
2403 unsigned literal_id
= 0;
2404 unsigned literal_uses
= UINT32_MAX
;
2405 Operand
literal(s1
);
2406 unsigned num_operands
= 1;
2407 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2408 num_operands
= instr
->operands
.size();
2410 unsigned sgpr_ids
[2] = {0, 0};
2411 bool is_literal_sgpr
= false;
2414 /* choose a literal to apply */
2415 for (unsigned i
= 0; i
< num_operands
; i
++) {
2416 Operand op
= instr
->operands
[i
];
2417 if (op
.isLiteral()) {
2418 current_literal
= op
;
2420 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2421 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2422 op
.tempId() != sgpr_ids
[0])
2423 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2427 if (!can_accept_constant(instr
, i
))
2430 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2431 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2433 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2434 literal_uses
= ctx
.uses
[op
.tempId()];
2435 literal_id
= op
.tempId();
2438 mask
|= (op
.tempId() == literal_id
) << i
;
2442 /* don't go over the constant bus limit */
2443 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2444 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2445 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2446 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2447 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2448 const_bus_limit
= 2;
2450 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2451 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2454 if (literal_id
&& literal_uses
< threshold
&&
2455 (current_literal
.isUndefined() ||
2456 (current_literal
.size() == literal
.size() &&
2457 current_literal
.constantValue() == literal
.constantValue()))) {
2458 /* mark the literal to be applied */
2460 unsigned i
= u_bit_scan(&mask
);
2461 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2462 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2468 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2470 /* Cleanup Dead Instructions */
2474 /* apply literals on MAD */
2475 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2476 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2477 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2478 aco_ptr
<Instruction
> new_mad
;
2479 if (info
->literal_idx
== 2) { /* add literal -> madak */
2480 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2481 new_mad
->operands
[0] = instr
->operands
[0];
2482 new_mad
->operands
[1] = instr
->operands
[1];
2483 } else { /* mul literal -> madmk */
2484 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2485 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2486 new_mad
->operands
[1] = instr
->operands
[2];
2488 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2489 new_mad
->definitions
[0] = instr
->definitions
[0];
2490 ctx
.instructions
.emplace_back(std::move(new_mad
));
2495 /* apply literals on other SALU/VALU */
2496 if (instr
->isSALU() || instr
->isVALU()) {
2497 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2498 Operand op
= instr
->operands
[i
];
2499 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2500 Operand
literal(ctx
.info
[op
.tempId()].val
);
2501 if (instr
->isVALU() && i
> 0)
2502 to_VOP3(ctx
, instr
);
2503 instr
->operands
[i
] = literal
;
2508 ctx
.instructions
.emplace_back(std::move(instr
));
2512 void optimize(Program
* program
)
2515 ctx
.program
= program
;
2516 std::vector
<ssa_info
> info(program
->peekAllocationId());
2517 ctx
.info
= info
.data();
2519 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2520 for (Block
& block
: program
->blocks
) {
2521 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2522 label_instruction(ctx
, block
, instr
);
2525 ctx
.uses
= std::move(dead_code_analysis(program
));
2527 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2528 for (Block
& block
: program
->blocks
) {
2529 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2530 combine_instruction(ctx
, block
, instr
);
2533 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2534 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2535 Block
* block
= &(*it
);
2536 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2537 select_instruction(ctx
, *it
);
2540 /* 4. Add literals to instructions */
2541 for (Block
& block
: program
->blocks
) {
2542 ctx
.instructions
.clear();
2543 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2544 apply_literals(ctx
, instr
);
2545 block
.instructions
.swap(ctx
.instructions
);