2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
85 label_uniform_bool
= 1 << 21,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
| label_omod2
| label_omod4
| label_omod5
| label_clamp
;
90 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_abs(Temp abs_temp
)
143 add_label(label_abs
);
149 return label
& label_abs
;
152 void set_neg(Temp neg_temp
)
154 add_label(label_neg
);
160 return label
& label_neg
;
163 void set_neg_abs(Temp neg_abs_temp
)
165 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
169 void set_mul(Instruction
* mul
)
171 add_label(label_mul
);
177 return label
& label_mul
;
180 void set_temp(Temp tmp
)
182 add_label(label_temp
);
188 return label
& label_temp
;
191 void set_literal(uint32_t lit
)
193 add_label(label_literal
);
199 return label
& label_literal
;
202 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
204 add_label(label_mad
);
211 return label
& label_mad
;
214 void set_omod2(Temp def
)
216 add_label(label_omod2
);
222 return label
& label_omod2
;
225 void set_omod4(Temp def
)
227 add_label(label_omod4
);
233 return label
& label_omod4
;
236 void set_omod5(Temp def
)
238 add_label(label_omod5
);
244 return label
& label_omod5
;
247 void set_omod_success(Instruction
* omod_instr
)
249 add_label(label_omod_success
);
253 bool is_omod_success()
255 return label
& label_omod_success
;
258 void set_clamp(Temp def
)
260 add_label(label_clamp
);
266 return label
& label_clamp
;
269 void set_clamp_success(Instruction
* clamp_instr
)
271 add_label(label_clamp_success
);
275 bool is_clamp_success()
277 return label
& label_clamp_success
;
282 add_label(label_undefined
);
287 return label
& label_undefined
;
290 void set_vcc(Temp vcc
)
292 add_label(label_vcc
);
298 return label
& label_vcc
;
301 bool is_constant_or_literal()
303 return is_constant() || is_literal();
306 void set_b2f(Temp val
)
308 add_label(label_b2f
);
314 return label
& label_b2f
;
317 void set_add_sub(Instruction
*add_sub_instr
)
319 add_label(label_add_sub
);
320 instr
= add_sub_instr
;
325 return label
& label_add_sub
;
328 void set_bitwise(Instruction
*bitwise_instr
)
330 add_label(label_bitwise
);
331 instr
= bitwise_instr
;
336 return label
& label_bitwise
;
339 void set_minmax(Instruction
*minmax_instr
)
341 add_label(label_minmax
);
342 instr
= minmax_instr
;
347 return label
& label_minmax
;
350 void set_fcmp(Instruction
*fcmp_instr
)
352 add_label(label_fcmp
);
358 return label
& label_fcmp
;
361 void set_uniform_bool(Temp uniform_bool
)
363 add_label(label_uniform_bool
);
367 bool is_uniform_bool()
369 return label
& label_uniform_bool
;
376 std::vector
<aco_ptr
<Instruction
>> instructions
;
378 std::pair
<uint32_t,Temp
> last_literal
;
379 std::vector
<mad_info
> mad_infos
;
380 std::vector
<uint16_t> uses
;
383 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
385 if (instr
->operands
[0].isConstant() ||
386 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
389 switch (instr
->opcode
) {
390 case aco_opcode::v_add_f32
:
391 case aco_opcode::v_mul_f32
:
392 case aco_opcode::v_or_b32
:
393 case aco_opcode::v_and_b32
:
394 case aco_opcode::v_xor_b32
:
395 case aco_opcode::v_max_f32
:
396 case aco_opcode::v_min_f32
:
397 case aco_opcode::v_cmp_eq_f32
:
398 case aco_opcode::v_cmp_lg_f32
:
400 case aco_opcode::v_sub_f32
:
401 instr
->opcode
= aco_opcode::v_subrev_f32
;
403 case aco_opcode::v_cmp_lt_f32
:
404 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
406 case aco_opcode::v_cmp_ge_f32
:
407 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
409 case aco_opcode::v_cmp_lt_i32
:
410 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
417 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
419 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
422 if (instr
->isDPP() || instr
->isSDWA())
425 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
426 instr
->opcode
!= aco_opcode::v_madak_f32
&&
427 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
428 instr
->opcode
!= aco_opcode::v_madak_f16
&&
429 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
430 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
431 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
434 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
436 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
437 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
438 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
439 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
440 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
443 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
448 assert(!instr
->operands
[0].isLiteral());
449 aco_ptr
<Instruction
> tmp
= std::move(instr
);
450 Format format
= asVOP3(tmp
->format
);
451 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
452 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
453 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
454 instr
->definitions
[i
] = tmp
->definitions
[i
];
455 if (instr
->definitions
[i
].isTemp()) {
456 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
457 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
458 info
.instr
= instr
.get();
463 /* only covers special cases */
464 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
466 switch (instr
->opcode
) {
467 case aco_opcode::v_interp_p2_f32
:
468 case aco_opcode::v_mac_f32
:
469 case aco_opcode::v_writelane_b32
:
470 case aco_opcode::v_writelane_b32_e64
:
471 case aco_opcode::v_cndmask_b32
:
473 case aco_opcode::s_addk_i32
:
474 case aco_opcode::s_mulk_i32
:
475 case aco_opcode::p_wqm
:
476 case aco_opcode::p_extract_vector
:
477 case aco_opcode::p_split_vector
:
478 case aco_opcode::v_readlane_b32
:
479 case aco_opcode::v_readlane_b32_e64
:
480 case aco_opcode::v_readfirstlane_b32
:
483 if ((instr
->format
== Format::MUBUF
||
484 instr
->format
== Format::MIMG
) &&
485 instr
->definitions
.size() == 1 &&
486 instr
->operands
.size() == 4) {
493 bool valu_can_accept_literal(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, unsigned operand
)
495 /* instructions like v_cndmask_b32 can't take a literal because they always
497 if (instr
->operands
.size() >= 3 &&
498 instr
->operands
[2].isTemp() && instr
->operands
[2].regClass().type() == RegType::sgpr
)
501 // TODO: VOP3 can take a literal on GFX10
502 return !instr
->isSDWA() && !instr
->isDPP() && !instr
->isVOP3() &&
503 operand
== 0 && can_accept_constant(instr
, operand
);
506 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
508 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
509 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
514 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
516 Operand op
= instr
->operands
[op_index
];
520 Temp tmp
= op
.getTemp();
521 if (!ctx
.info
[tmp
.id()].is_add_sub())
524 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
526 switch (add_instr
->opcode
) {
527 case aco_opcode::v_add_u32
:
528 case aco_opcode::v_add_co_u32
:
529 case aco_opcode::s_add_i32
:
530 case aco_opcode::s_add_u32
:
536 if (add_instr
->usesModifiers())
539 for (unsigned i
= 0; i
< 2; i
++) {
540 if (add_instr
->operands
[i
].isConstant()) {
541 *offset
= add_instr
->operands
[i
].constantValue();
542 } else if (add_instr
->operands
[i
].isTemp() &&
543 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
544 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
548 if (!add_instr
->operands
[!i
].isTemp())
551 uint32_t offset2
= 0;
552 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
555 *base
= add_instr
->operands
[!i
].getTemp();
563 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
)
565 // TODO: this functions shouldn't be needed if we store Operand instead of value.
567 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
568 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
572 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
574 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
575 ASSERTED
bool all_const
= false;
576 for (Operand
& op
: instr
->operands
)
577 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
578 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
581 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
583 if (!instr
->operands
[i
].isTemp())
586 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
587 /* propagate undef */
588 if (info
.is_undefined() && is_phi(instr
))
589 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
590 /* propagate reg->reg of same type */
591 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
592 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
593 info
= ctx
.info
[info
.temp
.id()];
596 /* SALU / PSEUDO: propagate inline constants */
597 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
598 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
599 instr
->operands
[i
].setTemp(info
.temp
);
600 info
= ctx
.info
[info
.temp
.id()];
601 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
602 /* propagate vgpr if it can take it */
603 switch (instr
->opcode
) {
604 case aco_opcode::p_create_vector
:
605 case aco_opcode::p_split_vector
:
606 case aco_opcode::p_extract_vector
:
607 case aco_opcode::p_phi
: {
608 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
609 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
611 instr
->operands
[i
] = Operand(info
.temp
);
612 info
= ctx
.info
[info
.temp
.id()];
620 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
621 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
626 /* VALU: propagate neg, abs & inline constants */
627 else if (instr
->isVALU()) {
628 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
629 instr
->operands
[i
].setTemp(info
.temp
);
630 info
= ctx
.info
[info
.temp
.id()];
632 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
635 instr
->operands
[i
] = Operand(info
.temp
);
637 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
639 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
641 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
642 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
643 instr
->operands
[i
].setTemp(info
.temp
);
645 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
648 instr
->operands
[i
].setTemp(info
.temp
);
650 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
652 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
655 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
656 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
657 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
658 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
660 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
661 instr
->operands
[i
] = instr
->operands
[0];
662 instr
->operands
[0] = get_constant_op(ctx
, info
.val
);
664 } else if (can_use_VOP3(instr
)) {
666 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
672 /* MUBUF: propagate constants and combine additions */
673 else if (instr
->format
== Format::MUBUF
) {
674 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
677 while (info
.is_temp())
678 info
= ctx
.info
[info
.temp
.id()];
680 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
681 assert(!mubuf
->idxen
);
682 instr
->operands
[i
] = Operand(v1
);
683 mubuf
->offset
+= info
.val
;
684 mubuf
->offen
= false;
686 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
687 instr
->operands
[2] = Operand((uint32_t) 0);
688 mubuf
->offset
+= info
.val
;
690 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
691 assert(!mubuf
->idxen
);
692 instr
->operands
[i
].setTemp(base
);
693 mubuf
->offset
+= offset
;
695 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
696 instr
->operands
[i
].setTemp(base
);
697 mubuf
->offset
+= offset
;
702 /* DS: combine additions */
703 else if (instr
->format
== Format::DS
) {
705 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
708 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
709 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
710 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
711 if (offset
% 4 == 0 &&
712 ds
->offset0
+ (offset
>> 2) <= 255 &&
713 ds
->offset1
+ (offset
>> 2) <= 255) {
714 instr
->operands
[i
].setTemp(base
);
715 ds
->offset0
+= offset
>> 2;
716 ds
->offset1
+= offset
>> 2;
719 if (ds
->offset0
+ offset
<= 65535) {
720 instr
->operands
[i
].setTemp(base
);
721 ds
->offset0
+= offset
;
727 /* SMEM: propagate constants and combine additions */
728 else if (instr
->format
== Format::SMEM
) {
730 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
733 if (i
== 1 && info
.is_constant_or_literal() &&
734 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
735 instr
->operands
[i
] = Operand(info
.val
);
737 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
738 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
740 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
741 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
745 smem
->operands
[1] = Operand(offset
);
746 smem
->operands
.back() = Operand(base
);
748 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
749 new_instr
->operands
[0] = smem
->operands
[0];
750 new_instr
->operands
[1] = Operand(offset
);
751 if (smem
->definitions
.empty())
752 new_instr
->operands
[2] = smem
->operands
[2];
753 new_instr
->operands
.back() = Operand(base
);
754 if (!smem
->definitions
.empty())
755 new_instr
->definitions
[0] = smem
->definitions
[0];
756 new_instr
->can_reorder
= smem
->can_reorder
;
757 new_instr
->barrier
= smem
->barrier
;
758 instr
.reset(new_instr
);
759 smem
= static_cast<SMEM_instruction
*>(instr
.get());
766 /* if this instruction doesn't define anything, return */
767 if (instr
->definitions
.empty())
770 switch (instr
->opcode
) {
771 case aco_opcode::p_create_vector
: {
772 unsigned num_ops
= instr
->operands
.size();
773 for (const Operand
& op
: instr
->operands
) {
774 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
775 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
777 if (num_ops
!= instr
->operands
.size()) {
778 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
779 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
780 instr
->definitions
[0] = old_vec
->definitions
[0];
782 for (Operand
& old_op
: old_vec
->operands
) {
783 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
784 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
785 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
786 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
787 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
788 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
789 instr
->operands
[k
++] = op
;
792 instr
->operands
[k
++] = old_op
;
795 assert(k
== num_ops
);
797 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
798 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
799 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
800 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
803 case aco_opcode::p_split_vector
: {
804 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
806 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
807 assert(instr
->definitions
.size() == vec
->operands
.size());
808 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
809 Operand vec_op
= vec
->operands
[i
];
810 if (vec_op
.isConstant()) {
811 if (vec_op
.isLiteral())
812 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
813 else if (vec_op
.size() == 1)
814 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
816 assert(vec_op
.isTemp());
817 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
822 case aco_opcode::p_extract_vector
: { /* mov */
823 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
825 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
826 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
827 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
829 /* convert this extract into a mov instruction */
830 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
831 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
832 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
833 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
834 instr
->opcode
= opcode
;
835 instr
->format
= format
;
836 while (instr
->operands
.size() > 1)
837 instr
->operands
.pop_back();
838 instr
->operands
[0] = vec_op
;
840 if (vec_op
.isConstant()) {
841 if (vec_op
.isLiteral())
842 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
843 else if (vec_op
.size() == 1)
844 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
846 assert(vec_op
.isTemp());
847 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
852 case aco_opcode::s_mov_b32
: /* propagate */
853 case aco_opcode::s_mov_b64
:
854 case aco_opcode::v_mov_b32
:
855 case aco_opcode::p_as_uniform
:
856 if (instr
->definitions
[0].isFixed()) {
857 /* don't copy-propagate copies into fixed registers */
858 } else if (instr
->usesModifiers()) {
860 } else if (instr
->operands
[0].isConstant()) {
861 if (instr
->operands
[0].isLiteral())
862 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
863 else if (instr
->operands
[0].size() == 1)
864 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
865 } else if (instr
->operands
[0].isTemp()) {
866 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
868 assert(instr
->operands
[0].isFixed());
871 case aco_opcode::p_is_helper
:
872 if (!ctx
.program
->needs_wqm
)
873 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
875 case aco_opcode::s_movk_i32
: {
876 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
877 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
878 if (v
<= 64 || v
>= 0xfffffff0)
879 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
881 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
884 case aco_opcode::v_bfrev_b32
:
885 case aco_opcode::s_brev_b32
: {
886 if (instr
->operands
[0].isConstant()) {
887 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
888 if (v
<= 64 || v
>= 0xfffffff0)
889 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
891 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
895 case aco_opcode::s_bfm_b32
: {
896 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
897 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
898 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
899 uint32_t v
= ((1u << size
) - 1u) << start
;
900 if (v
<= 64 || v
>= 0xfffffff0)
901 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
903 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
906 case aco_opcode::v_mul_f32
: { /* omod */
907 /* TODO: try to move the negate/abs modifier to the consumer instead */
908 if (instr
->usesModifiers())
911 for (unsigned i
= 0; i
< 2; i
++) {
912 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
913 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
914 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
915 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
916 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
917 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
918 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
919 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
920 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
921 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
930 case aco_opcode::v_and_b32
: /* abs */
931 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
932 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
933 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
935 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
937 case aco_opcode::v_xor_b32
: { /* neg */
938 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
939 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
940 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
941 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
942 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
943 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
944 instr
->opcode
= aco_opcode::v_or_b32
;
945 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
947 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
951 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
955 case aco_opcode::v_med3_f32
: { /* clamp */
956 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
957 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
958 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
959 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
963 bool found_zero
= false, found_one
= false;
964 for (unsigned i
= 0; i
< 3; i
++)
966 if (instr
->operands
[i
].constantEquals(0))
968 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
973 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
974 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
978 case aco_opcode::v_cndmask_b32
:
979 if (instr
->operands
[0].constantEquals(0) &&
980 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
981 instr
->operands
[2].isTemp())
982 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
983 else if (instr
->operands
[0].constantEquals(0) &&
984 instr
->operands
[1].constantEquals(0x3f800000u
) &&
985 instr
->operands
[2].isTemp())
986 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
988 case aco_opcode::v_cmp_lg_u32
:
989 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
990 instr
->operands
[0].constantEquals(0) &&
991 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
992 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
994 case aco_opcode::p_phi
:
995 case aco_opcode::p_linear_phi
: {
996 /* lower_bool_phis() can create phis like this */
997 bool all_same_temp
= instr
->operands
[0].isTemp();
998 /* this check is needed when moving uniform loop counters out of a divergent loop */
1000 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1001 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1002 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1003 all_same_temp
= false;
1005 if (all_same_temp
) {
1006 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1008 bool all_undef
= instr
->operands
[0].isUndefined();
1009 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1010 if (!instr
->operands
[i
].isUndefined())
1014 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1018 case aco_opcode::v_add_u32
:
1019 case aco_opcode::v_add_co_u32
:
1020 case aco_opcode::s_add_i32
:
1021 case aco_opcode::s_add_u32
:
1022 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1024 case aco_opcode::s_and_b32
:
1025 case aco_opcode::s_and_b64
:
1026 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1027 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1028 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1031 case aco_opcode::s_not_b32
:
1032 case aco_opcode::s_not_b64
:
1033 case aco_opcode::s_or_b32
:
1034 case aco_opcode::s_or_b64
:
1035 case aco_opcode::s_xor_b32
:
1036 case aco_opcode::s_xor_b64
:
1037 case aco_opcode::s_lshl_b32
:
1038 case aco_opcode::v_or_b32
:
1039 case aco_opcode::v_lshlrev_b32
:
1040 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1042 case aco_opcode::v_min_f32
:
1043 case aco_opcode::v_min_f16
:
1044 case aco_opcode::v_min_u32
:
1045 case aco_opcode::v_min_i32
:
1046 case aco_opcode::v_min_u16
:
1047 case aco_opcode::v_min_i16
:
1048 case aco_opcode::v_max_f32
:
1049 case aco_opcode::v_max_f16
:
1050 case aco_opcode::v_max_u32
:
1051 case aco_opcode::v_max_i32
:
1052 case aco_opcode::v_max_u16
:
1053 case aco_opcode::v_max_i16
:
1054 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1056 case aco_opcode::v_cmp_lt_f32
:
1057 case aco_opcode::v_cmp_eq_f32
:
1058 case aco_opcode::v_cmp_le_f32
:
1059 case aco_opcode::v_cmp_gt_f32
:
1060 case aco_opcode::v_cmp_lg_f32
:
1061 case aco_opcode::v_cmp_ge_f32
:
1062 case aco_opcode::v_cmp_o_f32
:
1063 case aco_opcode::v_cmp_u_f32
:
1064 case aco_opcode::v_cmp_nge_f32
:
1065 case aco_opcode::v_cmp_nlg_f32
:
1066 case aco_opcode::v_cmp_ngt_f32
:
1067 case aco_opcode::v_cmp_nle_f32
:
1068 case aco_opcode::v_cmp_neq_f32
:
1069 case aco_opcode::v_cmp_nlt_f32
:
1070 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1072 case aco_opcode::s_cselect_b64
:
1073 case aco_opcode::s_cselect_b32
:
1074 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1075 instr
->operands
[1].constantEquals(0)) {
1076 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1077 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1085 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1087 *ordered
= *unordered
= op
;
1089 #define CMP(ord, unord) \
1090 case aco_opcode::v_cmp_##ord##_f32:\
1091 case aco_opcode::v_cmp_n##unord##_f32:\
1092 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1093 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1094 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1108 aco_opcode
get_ordered(aco_opcode op
)
1110 aco_opcode ordered
, unordered
, inverse
;
1111 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1114 aco_opcode
get_unordered(aco_opcode op
)
1116 aco_opcode ordered
, unordered
, inverse
;
1117 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1120 aco_opcode
get_inverse(aco_opcode op
)
1122 aco_opcode ordered
, unordered
, inverse
;
1123 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1126 bool is_cmp(aco_opcode op
)
1128 aco_opcode ordered
, unordered
, inverse
;
1129 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1132 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1134 if (ctx
.info
[tmp
.id()].is_temp())
1135 return ctx
.info
[tmp
.id()].temp
.id();
1140 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1142 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1143 for (const Operand
& op
: instr
->operands
) {
1145 ctx
.uses
[op
.tempId()]--;
1150 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1152 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1154 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1157 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1159 if (instr
->definitions
.size() == 2) {
1160 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1161 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1168 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1169 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1170 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1172 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1174 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1177 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1179 bool neg
[2] = {false, false};
1180 bool abs
[2] = {false, false};
1182 Instruction
*op_instr
[2];
1185 for (unsigned i
= 0; i
< 2; i
++) {
1186 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1190 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1192 if (op_instr
[i
]->opcode
!= expected_cmp
)
1194 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1197 if (op_instr
[i
]->isVOP3()) {
1198 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1199 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1201 neg
[i
] = vop3
->neg
[0];
1202 abs
[i
] = vop3
->abs
[0];
1203 opsel
|= (vop3
->opsel
& 1) << i
;
1206 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1207 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1208 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1214 if (op
[1].type() == RegType::sgpr
)
1215 std::swap(op
[0], op
[1]);
1216 //TODO: we can use two different SGPRs on GFX10
1217 if (op
[0].type() == RegType::sgpr
&& op
[1].type() == RegType::sgpr
)
1220 ctx
.uses
[op
[0].id()]++;
1221 ctx
.uses
[op
[1].id()]++;
1222 decrease_uses(ctx
, op_instr
[0]);
1223 decrease_uses(ctx
, op_instr
[1]);
1225 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1226 Instruction
*new_instr
;
1227 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
) {
1228 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1229 for (unsigned i
= 0; i
< 2; i
++) {
1230 vop3
->neg
[i
] = neg
[i
];
1231 vop3
->abs
[i
] = abs
[i
];
1233 vop3
->opsel
= opsel
;
1234 new_instr
= static_cast<Instruction
*>(vop3
);
1236 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1238 new_instr
->operands
[0] = Operand(op
[0]);
1239 new_instr
->operands
[1] = Operand(op
[1]);
1240 new_instr
->definitions
[0] = instr
->definitions
[0];
1242 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1243 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1245 instr
.reset(new_instr
);
1250 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1251 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1252 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1254 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1256 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1259 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1260 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1262 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1263 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1264 if (!nan_test
|| !cmp
)
1267 if (cmp
->opcode
== expected_nan_test
)
1268 std::swap(nan_test
, cmp
);
1269 else if (nan_test
->opcode
!= expected_nan_test
)
1272 if (!is_cmp(cmp
->opcode
))
1275 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1277 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1280 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1281 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1282 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1283 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1284 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1286 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1289 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1290 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1291 decrease_uses(ctx
, nan_test
);
1292 decrease_uses(ctx
, cmp
);
1294 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1295 Instruction
*new_instr
;
1296 if (cmp
->isVOP3()) {
1297 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1298 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1299 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1300 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1301 new_vop3
->clamp
= cmp_vop3
->clamp
;
1302 new_vop3
->omod
= cmp_vop3
->omod
;
1303 new_vop3
->opsel
= cmp_vop3
->opsel
;
1304 new_instr
= new_vop3
;
1306 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1308 new_instr
->operands
[0] = cmp
->operands
[0];
1309 new_instr
->operands
[1] = cmp
->operands
[1];
1310 new_instr
->definitions
[0] = instr
->definitions
[0];
1312 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1313 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1315 instr
.reset(new_instr
);
1320 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1321 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1322 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1324 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1326 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1329 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1331 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1332 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1334 if (!nan_test
|| !cmp
)
1337 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1338 if (cmp
->opcode
== expected_nan_test
)
1339 std::swap(nan_test
, cmp
);
1340 else if (nan_test
->opcode
!= expected_nan_test
)
1343 if (!is_cmp(cmp
->opcode
))
1346 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1348 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1351 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1352 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1353 if (prop_nan0
!= prop_nan1
)
1356 if (nan_test
->isVOP3()) {
1357 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1358 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1362 int constant_operand
= -1;
1363 for (unsigned i
= 0; i
< 2; i
++) {
1364 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1365 constant_operand
= !i
;
1369 if (constant_operand
== -1)
1373 if (cmp
->operands
[constant_operand
].isConstant()) {
1374 constant
= cmp
->operands
[constant_operand
].constantValue();
1375 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1376 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1377 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1379 constant
= ctx
.info
[id
].val
;
1385 memcpy(&constantf
, &constant
, 4);
1386 if (isnan(constantf
))
1389 if (cmp
->operands
[0].isTemp())
1390 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1391 if (cmp
->operands
[1].isTemp())
1392 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1393 decrease_uses(ctx
, nan_test
);
1394 decrease_uses(ctx
, cmp
);
1396 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1397 Instruction
*new_instr
;
1398 if (cmp
->isVOP3()) {
1399 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1400 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1401 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1402 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1403 new_vop3
->clamp
= cmp_vop3
->clamp
;
1404 new_vop3
->omod
= cmp_vop3
->omod
;
1405 new_vop3
->opsel
= cmp_vop3
->opsel
;
1406 new_instr
= new_vop3
;
1408 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1410 new_instr
->operands
[0] = cmp
->operands
[0];
1411 new_instr
->operands
[1] = cmp
->operands
[1];
1412 new_instr
->definitions
[0] = instr
->definitions
[0];
1414 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1415 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1417 instr
.reset(new_instr
);
1422 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1423 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1425 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1427 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1429 if (!instr
->operands
[0].isTemp())
1432 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1436 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1437 if (new_opcode
== aco_opcode::last_opcode
)
1440 if (cmp
->operands
[0].isTemp())
1441 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1442 if (cmp
->operands
[1].isTemp())
1443 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1444 decrease_uses(ctx
, cmp
);
1446 Instruction
*new_instr
;
1447 if (cmp
->isVOP3()) {
1448 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1449 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1450 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1451 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1452 new_vop3
->clamp
= cmp_vop3
->clamp
;
1453 new_vop3
->omod
= cmp_vop3
->omod
;
1454 new_vop3
->opsel
= cmp_vop3
->opsel
;
1455 new_instr
= new_vop3
;
1457 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1459 new_instr
->operands
[0] = cmp
->operands
[0];
1460 new_instr
->operands
[1] = cmp
->operands
[1];
1461 new_instr
->definitions
[0] = instr
->definitions
[0];
1463 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1464 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1466 instr
.reset(new_instr
);
1471 /* op1(op2(1, 2), 0) if swap = false
1472 * op1(0, op2(1, 2)) if swap = true */
1473 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1474 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1475 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1476 bool *op1_clamp
, uint8_t *op1_omod
,
1477 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1480 if (op1_instr
->opcode
!= op1
)
1483 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1484 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1487 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1488 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1490 /* don't support inbetween clamp/omod */
1491 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1494 /* get operands and modifiers and check inbetween modifiers */
1495 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1496 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1499 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1500 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1504 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1505 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1508 if (inbetween_opsel
)
1509 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1510 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1514 shuffle
[shuffle_str
[0] - '0'] = 0;
1515 shuffle
[shuffle_str
[1] - '0'] = 1;
1516 shuffle
[shuffle_str
[2] - '0'] = 2;
1518 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1519 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1520 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1521 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1522 *opsel
|= 1 << shuffle
[0];
1524 for (unsigned i
= 0; i
< 2; i
++) {
1525 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1526 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1527 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1528 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1529 *opsel
|= 1 << shuffle
[i
+ 1];
1532 /* check operands */
1533 unsigned sgpr_id
= 0;
1534 for (unsigned i
= 0; i
< 3; i
++) {
1535 Operand op
= operands
[i
];
1536 if (op
.isLiteral()) {
1538 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1539 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1541 sgpr_id
= op
.tempId();
1548 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1549 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1550 bool clamp
, unsigned omod
)
1552 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1553 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1554 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1555 new_instr
->clamp
= clamp
;
1556 new_instr
->omod
= omod
;
1557 new_instr
->opsel
= opsel
;
1558 new_instr
->operands
[0] = operands
[0];
1559 new_instr
->operands
[1] = operands
[1];
1560 new_instr
->operands
[2] = operands
[2];
1561 new_instr
->definitions
[0] = instr
->definitions
[0];
1562 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1564 instr
.reset(new_instr
);
1567 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1569 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1570 (label_omod_success
| label_clamp_success
);
1572 for (unsigned swap
= 0; swap
< 2; swap
++) {
1573 if (!((1 << swap
) & ops
))
1576 Operand operands
[3];
1577 bool neg
[3], abs
[3], clamp
;
1578 uint8_t opsel
= 0, omod
= 0;
1579 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1580 instr
.get(), swap
, shuffle
,
1581 operands
, neg
, abs
, &opsel
,
1582 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1583 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1584 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1585 if (omod_clamp
& label_omod_success
)
1586 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1587 if (omod_clamp
& label_clamp_success
)
1588 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1595 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1596 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1597 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1598 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1599 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1600 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1601 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1604 if (!instr
->operands
[0].isTemp())
1606 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1609 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1612 switch (op2_instr
->opcode
) {
1613 case aco_opcode::s_and_b32
:
1614 case aco_opcode::s_or_b32
:
1615 case aco_opcode::s_xor_b32
:
1616 case aco_opcode::s_and_b64
:
1617 case aco_opcode::s_or_b64
:
1618 case aco_opcode::s_xor_b64
:
1624 /* create instruction */
1625 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1626 ctx
.uses
[instr
->operands
[0].tempId()]--;
1627 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1629 switch (op2_instr
->opcode
) {
1630 case aco_opcode::s_and_b32
:
1631 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1633 case aco_opcode::s_or_b32
:
1634 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1636 case aco_opcode::s_xor_b32
:
1637 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1639 case aco_opcode::s_and_b64
:
1640 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1642 case aco_opcode::s_or_b64
:
1643 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1645 case aco_opcode::s_xor_b64
:
1646 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1655 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1656 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1657 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1658 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1659 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1661 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1664 for (unsigned i
= 0; i
< 2; i
++) {
1665 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1666 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1669 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1670 instr
->operands
[0] = instr
->operands
[!i
];
1671 instr
->operands
[1] = op2_instr
->operands
[0];
1672 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1674 switch (instr
->opcode
) {
1675 case aco_opcode::s_and_b32
:
1676 instr
->opcode
= aco_opcode::s_andn2_b32
;
1678 case aco_opcode::s_or_b32
:
1679 instr
->opcode
= aco_opcode::s_orn2_b32
;
1681 case aco_opcode::s_and_b64
:
1682 instr
->opcode
= aco_opcode::s_andn2_b64
;
1684 case aco_opcode::s_or_b64
:
1685 instr
->opcode
= aco_opcode::s_orn2_b64
;
1696 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1697 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1699 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1702 for (unsigned i
= 0; i
< 2; i
++) {
1703 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1704 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1707 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1708 if (shift
< 1 || shift
> 4)
1711 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1712 instr
->operands
[1] = instr
->operands
[!i
];
1713 instr
->operands
[0] = op2_instr
->operands
[0];
1714 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1716 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1717 aco_opcode::s_lshl2_add_u32
,
1718 aco_opcode::s_lshl3_add_u32
,
1719 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1726 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1729 #define MINMAX(type, gfx9) \
1730 case aco_opcode::v_min_##type:\
1731 case aco_opcode::v_max_##type:\
1732 case aco_opcode::v_med3_##type:\
1733 *min = aco_opcode::v_min_##type;\
1734 *max = aco_opcode::v_max_##type;\
1735 *med3 = aco_opcode::v_med3_##type;\
1736 *min3 = aco_opcode::v_min3_##type;\
1737 *max3 = aco_opcode::v_max3_##type;\
1738 *some_gfx9_only = gfx9;\
1752 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1753 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1754 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1755 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1757 aco_opcode other_op
;
1758 if (instr
->opcode
== min
)
1760 else if (instr
->opcode
== max
)
1765 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1766 (label_omod_success
| label_clamp_success
);
1768 for (unsigned swap
= 0; swap
< 2; swap
++) {
1769 Operand operands
[3];
1770 bool neg
[3], abs
[3], clamp
, inbetween_neg
, inbetween_abs
;
1771 uint8_t opsel
= 0, omod
= 0;
1772 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1773 "012", operands
, neg
, abs
, &opsel
,
1774 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1775 int const0_idx
= -1, const1_idx
= -1;
1776 uint32_t const0
= 0, const1
= 0;
1777 for (int i
= 0; i
< 3; i
++) {
1779 if (operands
[i
].isConstant()) {
1780 val
= operands
[i
].constantValue();
1781 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1782 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1783 val
= ctx
.info
[operands
[i
].tempId()].val
;
1787 if (const0_idx
>= 0) {
1795 if (const0_idx
< 0 || const1_idx
< 0)
1798 if (opsel
& (1 << const0_idx
))
1800 if (opsel
& (1 << const1_idx
))
1803 int lower_idx
= const0_idx
;
1805 case aco_opcode::v_min_f32
:
1806 case aco_opcode::v_min_f16
: {
1807 float const0_f
, const1_f
;
1808 if (min
== aco_opcode::v_min_f32
) {
1809 memcpy(&const0_f
, &const0
, 4);
1810 memcpy(&const1_f
, &const1
, 4);
1812 const0_f
= _mesa_half_to_float(const0
);
1813 const1_f
= _mesa_half_to_float(const1
);
1815 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1816 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1817 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1818 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1819 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1822 case aco_opcode::v_min_u32
: {
1823 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1826 case aco_opcode::v_min_u16
: {
1827 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1830 case aco_opcode::v_min_i32
: {
1831 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1832 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1833 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1836 case aco_opcode::v_min_i16
: {
1837 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1838 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1839 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1845 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1847 if (instr
->opcode
== min
) {
1848 if (upper_idx
!= 0 || lower_idx
== 0)
1851 if (upper_idx
== 0 || lower_idx
!= 0)
1855 neg
[1] ^= inbetween_neg
;
1856 neg
[2] ^= inbetween_neg
;
1857 abs
[1] |= inbetween_abs
;
1858 abs
[2] |= inbetween_abs
;
1860 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1861 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1862 if (omod_clamp
& label_omod_success
)
1863 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1864 if (omod_clamp
& label_clamp_success
)
1865 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1875 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1878 uint32_t sgpr_idx
= 0;
1879 uint32_t sgpr_info_id
= 0;
1880 bool has_sgpr
= false;
1881 uint32_t sgpr_ssa_id
= 0;
1882 /* find 'best' possible sgpr */
1883 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
1885 if (instr
->operands
[i
].isLiteral()) {
1889 if (!instr
->operands
[i
].isTemp())
1891 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1893 sgpr_ssa_id
= instr
->operands
[i
].tempId();
1896 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1897 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
1898 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1899 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1901 sgpr_info_id
= instr
->operands
[i
].tempId();
1905 if (!has_sgpr
&& sgpr_info_id
!= 0) {
1906 ssa_info
& info
= ctx
.info
[sgpr_info_id
];
1907 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1908 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1909 ctx
.uses
[sgpr_info_id
]--;
1910 ctx
.uses
[info
.temp
.id()]++;
1911 } else if (can_swap_operands(instr
)) {
1912 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1913 instr
->operands
[0] = Operand(info
.temp
);
1914 ctx
.uses
[sgpr_info_id
]--;
1915 ctx
.uses
[info
.temp
.id()]++;
1916 } else if (can_use_VOP3(instr
)) {
1917 to_VOP3(ctx
, instr
);
1918 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1919 ctx
.uses
[sgpr_info_id
]--;
1920 ctx
.uses
[info
.temp
.id()]++;
1923 /* we can have two sgprs on one instruction if it is the same sgpr! */
1924 } else if (sgpr_info_id
!= 0 &&
1925 sgpr_ssa_id
== ctx
.info
[sgpr_info_id
].temp
.id() &&
1926 ctx
.uses
[sgpr_info_id
] == 1 &&
1927 can_use_VOP3(instr
)) {
1928 to_VOP3(ctx
, instr
);
1929 instr
->operands
[sgpr_idx
] = Operand(ctx
.info
[sgpr_info_id
].temp
);
1930 ctx
.uses
[sgpr_info_id
]--;
1931 ctx
.uses
[ctx
.info
[sgpr_info_id
].temp
.id()]++;
1935 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1937 /* check if we could apply omod on predecessor */
1938 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1939 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
1940 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
1942 unsigned idx
= op0
? 0 : 1;
1943 /* omod was successfully applied */
1944 /* if the omod instruction is v_mad, we also have to change the original add */
1945 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1946 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1947 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1948 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1949 add_instr
->definitions
[0] = instr
->definitions
[0];
1952 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1953 /* check if we have an additional clamp modifier */
1954 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1955 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
1956 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1957 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1959 /* change definition ssa-id of modified instruction */
1960 omod_instr
->definitions
[0] = instr
->definitions
[0];
1962 /* change the definition of instr to something unused, e.g. the original omod def */
1963 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1964 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1967 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1968 /* in all other cases, label this instruction as option for multiply-add */
1969 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1973 /* check if we could apply clamp on predecessor */
1974 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1976 bool found_zero
= false, found_one
= false;
1977 for (unsigned i
= 0; i
< 3; i
++)
1979 if (instr
->operands
[i
].constantEquals(0))
1981 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1986 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1987 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1988 /* clamp was successfully applied */
1989 /* if the clamp instruction is v_mad, we also have to change the original add */
1990 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1991 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1992 add_instr
->definitions
[0] = instr
->definitions
[0];
1994 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1995 /* change definition ssa-id of modified instruction */
1996 clamp_instr
->definitions
[0] = instr
->definitions
[0];
1998 /* change the definition of instr to something unused, e.g. the original omod def */
1999 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2000 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2005 /* omod has no effect if denormals are enabled */
2006 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2008 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2009 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2010 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2011 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2012 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2013 to_VOP3(ctx
, instr
);
2014 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2015 def_info
.set_omod_success(instr
.get());
2016 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2017 to_VOP3(ctx
, instr
);
2018 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2019 def_info
.set_omod_success(instr
.get());
2020 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2021 to_VOP3(ctx
, instr
);
2022 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2023 def_info
.set_omod_success(instr
.get());
2024 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2025 to_VOP3(ctx
, instr
);
2026 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2027 def_info
.set_clamp_success(instr
.get());
2034 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2035 // this would mean that we'd have to fix the instruction uses while value propagation
2037 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2039 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2042 if (instr
->isVALU()) {
2043 if (can_apply_sgprs(instr
))
2044 apply_sgprs(ctx
, instr
);
2045 if (apply_omod_clamp(ctx
, block
, instr
))
2049 /* TODO: There are still some peephole optimizations that could be done:
2050 * - abs(a - b) -> s_absdiff_i32
2051 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2052 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2053 * These aren't probably too interesting though.
2054 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2055 * probably more useful than the previously mentioned optimizations.
2056 * The various comparison optimizations also currently only work with 32-bit
2059 /* neg(mul(a, b)) -> mul(neg(a), b) */
2060 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2061 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2063 if (!ctx
.info
[val
.id()].is_mul())
2066 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2068 if (mul_instr
->operands
[0].isLiteral())
2070 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2073 /* convert to mul(neg(a), b) */
2074 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2075 Definition def
= instr
->definitions
[0];
2076 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2077 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2078 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2079 instr
->operands
[0] = mul_instr
->operands
[0];
2080 instr
->operands
[1] = mul_instr
->operands
[1];
2081 instr
->definitions
[0] = def
;
2082 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2083 if (mul_instr
->isVOP3()) {
2084 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2085 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2086 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2087 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2088 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2089 new_mul
->omod
= mul
->omod
;
2091 new_mul
->neg
[0] ^= true;
2092 new_mul
->clamp
= false;
2094 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2097 /* combine mul+add -> mad */
2098 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2099 instr
->opcode
== aco_opcode::v_sub_f32
||
2100 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2101 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2102 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2104 uint32_t uses_src0
= UINT32_MAX
;
2105 uint32_t uses_src1
= UINT32_MAX
;
2106 Instruction
* mul_instr
= nullptr;
2107 unsigned add_op_idx
;
2108 /* check if any of the operands is a multiplication */
2109 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2110 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2111 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2112 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2114 /* find the 'best' mul instruction to combine with the add */
2115 if (uses_src0
< uses_src1
) {
2116 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2118 } else if (uses_src1
< uses_src0
) {
2119 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2121 } else if (uses_src0
!= UINT32_MAX
) {
2122 /* tiebreaker: quite random what to pick */
2123 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2124 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2127 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2132 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2133 bool neg
[3] = {false, false, false};
2134 bool abs
[3] = {false, false, false};
2137 bool need_vop3
= false;
2139 unsigned cur_sgpr
= 0;
2140 op
[0] = mul_instr
->operands
[0];
2141 op
[1] = mul_instr
->operands
[1];
2142 op
[2] = instr
->operands
[add_op_idx
];
2143 for (unsigned i
= 0; i
< 3; i
++)
2145 if (op
[i
].isLiteral())
2147 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
&& op
[i
].tempId() != cur_sgpr
) {
2149 cur_sgpr
= op
[i
].tempId();
2151 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2154 // TODO: would be better to check this before selecting a mul instr?
2158 if (mul_instr
->isVOP3()) {
2159 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2160 neg
[0] = vop3
->neg
[0];
2161 neg
[1] = vop3
->neg
[1];
2162 abs
[0] = vop3
->abs
[0];
2163 abs
[1] = vop3
->abs
[1];
2165 /* we cannot use these modifiers between mul and add */
2166 if (vop3
->clamp
|| vop3
->omod
)
2170 /* convert to mad */
2171 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2172 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2174 ctx
.uses
[op
[0].tempId()]++;
2176 ctx
.uses
[op
[1].tempId()]++;
2179 if (instr
->isVOP3()) {
2180 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2181 neg
[2] = vop3
->neg
[add_op_idx
];
2182 abs
[2] = vop3
->abs
[add_op_idx
];
2184 clamp
= vop3
->clamp
;
2185 /* abs of the multiplication result */
2186 if (vop3
->abs
[1 - add_op_idx
]) {
2192 /* neg of the multiplication result */
2193 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2196 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2197 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2199 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2200 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2204 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2205 for (unsigned i
= 0; i
< 3; i
++)
2207 mad
->operands
[i
] = op
[i
];
2208 mad
->neg
[i
] = neg
[i
];
2209 mad
->abs
[i
] = abs
[i
];
2213 mad
->definitions
[0] = instr
->definitions
[0];
2215 /* mark this ssa_def to be re-checked for profitability and literals */
2216 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2217 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2218 instr
.reset(mad
.release());
2222 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2223 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2224 for (unsigned i
= 0; i
< 2; i
++) {
2225 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2226 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2227 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2228 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2229 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2231 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2232 new_instr
->operands
[0] = Operand(0u);
2233 new_instr
->operands
[1] = instr
->operands
[!i
];
2234 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2235 new_instr
->definitions
[0] = instr
->definitions
[0];
2236 instr
.reset(new_instr
.release());
2237 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2241 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2242 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2243 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2244 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2245 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2246 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2247 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2248 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2249 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2250 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2251 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2252 combine_salu_lshl_add(ctx
, instr
);
2253 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2254 combine_salu_not_bitwise(ctx
, instr
);
2255 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2256 if (combine_inverse_comparison(ctx
, instr
)) ;
2257 else combine_salu_not_bitwise(ctx
, instr
);
2258 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2259 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2260 if (combine_ordering_test(ctx
, instr
)) ;
2261 else if (combine_comparison_ordering(ctx
, instr
)) ;
2262 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2263 else combine_salu_n2(ctx
, instr
);
2265 aco_opcode min
, max
, min3
, max3
, med3
;
2266 bool some_gfx9_only
;
2267 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2268 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2269 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2270 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2276 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2278 const uint32_t threshold
= 4;
2280 if (is_dead(ctx
.uses
, instr
.get())) {
2285 /* convert split_vector into extract_vector if only one definition is ever used */
2286 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2287 unsigned num_used
= 0;
2289 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2290 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2295 if (num_used
== 1) {
2296 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2297 extract
->operands
[0] = instr
->operands
[0];
2298 extract
->operands
[1] = Operand((uint32_t) idx
);
2299 extract
->definitions
[0] = instr
->definitions
[idx
];
2300 instr
.reset(extract
.release());
2304 /* re-check mad instructions */
2305 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2306 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2307 /* first, check profitability */
2308 if (ctx
.uses
[info
->mul_temp_id
]) {
2309 ctx
.uses
[info
->mul_temp_id
]++;
2310 if (instr
->operands
[0].isTemp())
2311 ctx
.uses
[instr
->operands
[0].tempId()]--;
2312 if (instr
->operands
[1].isTemp())
2313 ctx
.uses
[instr
->operands
[1].tempId()]--;
2314 instr
.swap(info
->add_instr
);
2316 /* second, check possible literals */
2317 } else if (!info
->needs_vop3
) {
2318 uint32_t literal_idx
= 0;
2319 uint32_t literal_uses
= UINT32_MAX
;
2320 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2322 if (!instr
->operands
[i
].isTemp())
2324 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2325 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2326 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2327 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2330 literal_uses
= UINT32_MAX
;
2334 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2335 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2336 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2340 if (literal_uses
< threshold
) {
2341 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2342 info
->check_literal
= true;
2343 info
->literal_idx
= literal_idx
;
2348 /* check for literals */
2349 /* we do not apply the literals yet as we don't know if it is profitable */
2350 if (instr
->isSALU()) {
2351 uint32_t literal_idx
= 0;
2352 uint32_t literal_uses
= UINT32_MAX
;
2353 bool has_literal
= false;
2354 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2356 if (instr
->operands
[i
].isLiteral()) {
2360 if (!instr
->operands
[i
].isTemp())
2362 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2363 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2364 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2368 if (!has_literal
&& literal_uses
< threshold
) {
2369 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2370 if (ctx
.uses
[instr
->operands
[literal_idx
].tempId()] == 0)
2371 instr
->operands
[literal_idx
] = Operand(ctx
.info
[instr
->operands
[literal_idx
].tempId()].val
);
2373 } else if (instr
->isVALU() && valu_can_accept_literal(ctx
, instr
, 0) &&
2374 instr
->operands
[0].isTemp() &&
2375 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2376 ctx
.uses
[instr
->operands
[0].tempId()] < threshold
) {
2377 ctx
.uses
[instr
->operands
[0].tempId()]--;
2378 if (ctx
.uses
[instr
->operands
[0].tempId()] == 0)
2379 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2385 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2387 /* Cleanup Dead Instructions */
2391 /* apply literals on SALU */
2392 if (instr
->isSALU()) {
2393 for (Operand
& op
: instr
->operands
) {
2398 if (ctx
.info
[op
.tempId()].is_literal() &&
2399 ctx
.uses
[op
.tempId()] == 0)
2400 op
= Operand(ctx
.info
[op
.tempId()].val
);
2404 /* apply literals on VALU */
2405 else if (instr
->isVALU() && !instr
->isVOP3() &&
2406 instr
->operands
[0].isTemp() &&
2407 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2408 ctx
.uses
[instr
->operands
[0].tempId()] == 0) {
2409 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2412 /* apply literals on MAD */
2413 else if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2414 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2415 aco_ptr
<Instruction
> new_mad
;
2416 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2417 if (info
->literal_idx
== 2) { /* add literal -> madak */
2418 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2419 new_mad
->operands
[0] = instr
->operands
[0];
2420 new_mad
->operands
[1] = instr
->operands
[1];
2421 } else { /* mul literal -> madmk */
2422 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2423 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2424 new_mad
->operands
[1] = instr
->operands
[2];
2426 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2427 new_mad
->definitions
[0] = instr
->definitions
[0];
2428 instr
.swap(new_mad
);
2432 ctx
.instructions
.emplace_back(std::move(instr
));
2436 void optimize(Program
* program
)
2439 ctx
.program
= program
;
2440 std::vector
<ssa_info
> info(program
->peekAllocationId());
2441 ctx
.info
= info
.data();
2443 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2444 for (Block
& block
: program
->blocks
) {
2445 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2446 label_instruction(ctx
, block
, instr
);
2449 ctx
.uses
= std::move(dead_code_analysis(program
));
2451 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2452 for (Block
& block
: program
->blocks
) {
2453 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2454 combine_instruction(ctx
, block
, instr
);
2457 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2458 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2459 Block
* block
= &(*it
);
2460 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2461 select_instruction(ctx
, *it
);
2464 /* 4. Add literals to instructions */
2465 for (Block
& block
: program
->blocks
) {
2466 ctx
.instructions
.clear();
2467 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2468 apply_literals(ctx
, instr
);
2469 block
.instructions
.swap(ctx
.instructions
);