2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
| label_omod2
| label_omod4
| label_omod5
| label_clamp
;
90 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_constant_64bit(uint32_t constant
)
143 add_label(label_constant_64bit
);
147 bool is_constant_64bit()
149 return label
& label_constant_64bit
;
152 void set_abs(Temp abs_temp
)
154 add_label(label_abs
);
160 return label
& label_abs
;
163 void set_neg(Temp neg_temp
)
165 add_label(label_neg
);
171 return label
& label_neg
;
174 void set_neg_abs(Temp neg_abs_temp
)
176 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
180 void set_mul(Instruction
* mul
)
182 add_label(label_mul
);
188 return label
& label_mul
;
191 void set_temp(Temp tmp
)
193 add_label(label_temp
);
199 return label
& label_temp
;
202 void set_literal(uint32_t lit
)
204 add_label(label_literal
);
210 return label
& label_literal
;
213 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
215 add_label(label_mad
);
222 return label
& label_mad
;
225 void set_omod2(Temp def
)
227 add_label(label_omod2
);
233 return label
& label_omod2
;
236 void set_omod4(Temp def
)
238 add_label(label_omod4
);
244 return label
& label_omod4
;
247 void set_omod5(Temp def
)
249 add_label(label_omod5
);
255 return label
& label_omod5
;
258 void set_omod_success(Instruction
* omod_instr
)
260 add_label(label_omod_success
);
264 bool is_omod_success()
266 return label
& label_omod_success
;
269 void set_clamp(Temp def
)
271 add_label(label_clamp
);
277 return label
& label_clamp
;
280 void set_clamp_success(Instruction
* clamp_instr
)
282 add_label(label_clamp_success
);
286 bool is_clamp_success()
288 return label
& label_clamp_success
;
293 add_label(label_undefined
);
298 return label
& label_undefined
;
301 void set_vcc(Temp vcc
)
303 add_label(label_vcc
);
309 return label
& label_vcc
;
312 bool is_constant_or_literal()
314 return is_constant() || is_literal();
317 void set_b2f(Temp val
)
319 add_label(label_b2f
);
325 return label
& label_b2f
;
328 void set_add_sub(Instruction
*add_sub_instr
)
330 add_label(label_add_sub
);
331 instr
= add_sub_instr
;
336 return label
& label_add_sub
;
339 void set_bitwise(Instruction
*bitwise_instr
)
341 add_label(label_bitwise
);
342 instr
= bitwise_instr
;
347 return label
& label_bitwise
;
350 void set_minmax(Instruction
*minmax_instr
)
352 add_label(label_minmax
);
353 instr
= minmax_instr
;
358 return label
& label_minmax
;
361 void set_fcmp(Instruction
*fcmp_instr
)
363 add_label(label_fcmp
);
369 return label
& label_fcmp
;
372 void set_uniform_bool(Temp uniform_bool
)
374 add_label(label_uniform_bool
);
378 bool is_uniform_bool()
380 return label
& label_uniform_bool
;
387 std::vector
<aco_ptr
<Instruction
>> instructions
;
389 std::pair
<uint32_t,Temp
> last_literal
;
390 std::vector
<mad_info
> mad_infos
;
391 std::vector
<uint16_t> uses
;
394 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
396 if (instr
->operands
[0].isConstant() ||
397 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
400 switch (instr
->opcode
) {
401 case aco_opcode::v_add_f32
:
402 case aco_opcode::v_mul_f32
:
403 case aco_opcode::v_or_b32
:
404 case aco_opcode::v_and_b32
:
405 case aco_opcode::v_xor_b32
:
406 case aco_opcode::v_max_f32
:
407 case aco_opcode::v_min_f32
:
408 case aco_opcode::v_max_i32
:
409 case aco_opcode::v_min_i32
:
410 case aco_opcode::v_max_u32
:
411 case aco_opcode::v_min_u32
:
412 case aco_opcode::v_cmp_eq_f32
:
413 case aco_opcode::v_cmp_lg_f32
:
415 case aco_opcode::v_sub_f32
:
416 instr
->opcode
= aco_opcode::v_subrev_f32
;
418 case aco_opcode::v_cmp_lt_f32
:
419 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
421 case aco_opcode::v_cmp_ge_f32
:
422 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
424 case aco_opcode::v_cmp_lt_i32
:
425 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
432 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
437 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
440 if (instr
->isDPP() || instr
->isSDWA())
443 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
444 instr
->opcode
!= aco_opcode::v_madak_f32
&&
445 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
446 instr
->opcode
!= aco_opcode::v_madak_f16
&&
447 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
448 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
449 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
450 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
451 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
452 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
453 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
456 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
458 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
459 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
460 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
461 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
462 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
465 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
470 aco_ptr
<Instruction
> tmp
= std::move(instr
);
471 Format format
= asVOP3(tmp
->format
);
472 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
473 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
474 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
475 instr
->definitions
[i
] = tmp
->definitions
[i
];
476 if (instr
->definitions
[i
].isTemp()) {
477 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
478 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
479 info
.instr
= instr
.get();
484 /* only covers special cases */
485 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
487 switch (instr
->opcode
) {
488 case aco_opcode::v_interp_p2_f32
:
489 case aco_opcode::v_mac_f32
:
490 case aco_opcode::v_writelane_b32
:
491 case aco_opcode::v_writelane_b32_e64
:
492 case aco_opcode::v_cndmask_b32
:
494 case aco_opcode::s_addk_i32
:
495 case aco_opcode::s_mulk_i32
:
496 case aco_opcode::p_wqm
:
497 case aco_opcode::p_extract_vector
:
498 case aco_opcode::p_split_vector
:
499 case aco_opcode::v_readlane_b32
:
500 case aco_opcode::v_readlane_b32_e64
:
501 case aco_opcode::v_readfirstlane_b32
:
504 if ((instr
->format
== Format::MUBUF
||
505 instr
->format
== Format::MIMG
) &&
506 instr
->definitions
.size() == 1 &&
507 instr
->operands
.size() == 4) {
514 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
516 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
517 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
522 /* check constant bus and literal limitations */
523 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
525 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
526 Operand
literal32(s1
);
527 Operand
literal64(s2
);
528 unsigned num_sgprs
= 0;
529 unsigned sgpr
[] = {0, 0};
531 for (unsigned i
= 0; i
< num_operands
; i
++) {
532 Operand op
= operands
[i
];
534 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
535 /* two reads of the same SGPR count as 1 to the limit */
536 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
538 sgpr
[num_sgprs
++] = op
.tempId();
543 } else if (op
.isLiteral()) {
544 if (ctx
.program
->chip_class
< GFX10
)
547 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
549 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
552 /* Any number of 32-bit literals counts as only 1 to the limit. Same
553 * (but separately) for 64-bit literals. */
554 if (op
.size() == 1 && literal32
.isUndefined()) {
557 } else if (op
.size() == 2 && literal64
.isUndefined()) {
570 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
572 Operand op
= instr
->operands
[op_index
];
576 Temp tmp
= op
.getTemp();
577 if (!ctx
.info
[tmp
.id()].is_add_sub())
580 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
582 switch (add_instr
->opcode
) {
583 case aco_opcode::v_add_u32
:
584 case aco_opcode::v_add_co_u32
:
585 case aco_opcode::s_add_i32
:
586 case aco_opcode::s_add_u32
:
592 if (add_instr
->usesModifiers())
595 for (unsigned i
= 0; i
< 2; i
++) {
596 if (add_instr
->operands
[i
].isConstant()) {
597 *offset
= add_instr
->operands
[i
].constantValue();
598 } else if (add_instr
->operands
[i
].isTemp() &&
599 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
600 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
604 if (!add_instr
->operands
[!i
].isTemp())
607 uint32_t offset2
= 0;
608 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
611 *base
= add_instr
->operands
[!i
].getTemp();
619 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
621 // TODO: this functions shouldn't be needed if we store Operand instead of value.
622 Operand
op(val
, is64bit
);
623 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
624 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
628 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
630 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
631 ASSERTED
bool all_const
= false;
632 for (Operand
& op
: instr
->operands
)
633 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
634 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
637 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
639 if (!instr
->operands
[i
].isTemp())
642 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
643 /* propagate undef */
644 if (info
.is_undefined() && is_phi(instr
))
645 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
646 /* propagate reg->reg of same type */
647 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
648 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
649 info
= ctx
.info
[info
.temp
.id()];
652 /* SALU / PSEUDO: propagate inline constants */
653 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
654 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
655 instr
->operands
[i
].setTemp(info
.temp
);
656 info
= ctx
.info
[info
.temp
.id()];
657 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
658 /* propagate vgpr if it can take it */
659 switch (instr
->opcode
) {
660 case aco_opcode::p_create_vector
:
661 case aco_opcode::p_split_vector
:
662 case aco_opcode::p_extract_vector
:
663 case aco_opcode::p_phi
: {
664 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
665 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
667 instr
->operands
[i
] = Operand(info
.temp
);
668 info
= ctx
.info
[info
.temp
.id()];
676 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
677 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
682 /* VALU: propagate neg, abs & inline constants */
683 else if (instr
->isVALU()) {
684 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
685 instr
->operands
[i
].setTemp(info
.temp
);
686 info
= ctx
.info
[info
.temp
.id()];
688 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
691 instr
->operands
[i
] = Operand(info
.temp
);
693 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
695 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
697 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
698 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
699 instr
->operands
[i
].setTemp(info
.temp
);
701 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
704 instr
->operands
[i
].setTemp(info
.temp
);
706 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
708 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
711 if ((info
.is_constant() || info
.is_constant_64bit()) && can_accept_constant(instr
, i
)) {
712 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
713 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
714 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
715 instr
->operands
[i
] = op
;
717 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
718 instr
->operands
[i
] = instr
->operands
[0];
719 instr
->operands
[0] = op
;
721 } else if (can_use_VOP3(ctx
, instr
)) {
723 instr
->operands
[i
] = op
;
729 /* MUBUF: propagate constants and combine additions */
730 else if (instr
->format
== Format::MUBUF
) {
731 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
734 while (info
.is_temp())
735 info
= ctx
.info
[info
.temp
.id()];
737 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
738 assert(!mubuf
->idxen
);
739 instr
->operands
[i
] = Operand(v1
);
740 mubuf
->offset
+= info
.val
;
741 mubuf
->offen
= false;
743 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
744 instr
->operands
[2] = Operand((uint32_t) 0);
745 mubuf
->offset
+= info
.val
;
747 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
748 assert(!mubuf
->idxen
);
749 instr
->operands
[i
].setTemp(base
);
750 mubuf
->offset
+= offset
;
752 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
753 instr
->operands
[i
].setTemp(base
);
754 mubuf
->offset
+= offset
;
759 /* DS: combine additions */
760 else if (instr
->format
== Format::DS
) {
762 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
765 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
766 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
767 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
768 if (offset
% 4 == 0 &&
769 ds
->offset0
+ (offset
>> 2) <= 255 &&
770 ds
->offset1
+ (offset
>> 2) <= 255) {
771 instr
->operands
[i
].setTemp(base
);
772 ds
->offset0
+= offset
>> 2;
773 ds
->offset1
+= offset
>> 2;
776 if (ds
->offset0
+ offset
<= 65535) {
777 instr
->operands
[i
].setTemp(base
);
778 ds
->offset0
+= offset
;
784 /* SMEM: propagate constants and combine additions */
785 else if (instr
->format
== Format::SMEM
) {
787 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
790 if (i
== 1 && info
.is_constant_or_literal() &&
791 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
792 instr
->operands
[i
] = Operand(info
.val
);
794 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
795 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
797 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
798 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
802 smem
->operands
[1] = Operand(offset
);
803 smem
->operands
.back() = Operand(base
);
805 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
806 new_instr
->operands
[0] = smem
->operands
[0];
807 new_instr
->operands
[1] = Operand(offset
);
808 if (smem
->definitions
.empty())
809 new_instr
->operands
[2] = smem
->operands
[2];
810 new_instr
->operands
.back() = Operand(base
);
811 if (!smem
->definitions
.empty())
812 new_instr
->definitions
[0] = smem
->definitions
[0];
813 new_instr
->can_reorder
= smem
->can_reorder
;
814 new_instr
->barrier
= smem
->barrier
;
815 instr
.reset(new_instr
);
816 smem
= static_cast<SMEM_instruction
*>(instr
.get());
823 /* if this instruction doesn't define anything, return */
824 if (instr
->definitions
.empty())
827 switch (instr
->opcode
) {
828 case aco_opcode::p_create_vector
: {
829 unsigned num_ops
= instr
->operands
.size();
830 for (const Operand
& op
: instr
->operands
) {
831 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
832 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
834 if (num_ops
!= instr
->operands
.size()) {
835 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
836 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
837 instr
->definitions
[0] = old_vec
->definitions
[0];
839 for (Operand
& old_op
: old_vec
->operands
) {
840 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
841 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
842 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
843 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
844 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
845 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
846 instr
->operands
[k
++] = op
;
849 instr
->operands
[k
++] = old_op
;
852 assert(k
== num_ops
);
854 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
855 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
856 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
857 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
860 case aco_opcode::p_split_vector
: {
861 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
863 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
864 assert(instr
->definitions
.size() == vec
->operands
.size());
865 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
866 Operand vec_op
= vec
->operands
[i
];
867 if (vec_op
.isConstant()) {
868 if (vec_op
.isLiteral())
869 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
870 else if (vec_op
.size() == 1)
871 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
872 else if (vec_op
.size() == 2)
873 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
875 assert(vec_op
.isTemp());
876 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
881 case aco_opcode::p_extract_vector
: { /* mov */
882 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
884 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
885 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
886 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
888 /* convert this extract into a mov instruction */
889 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
890 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
891 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
892 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
893 instr
->opcode
= opcode
;
894 instr
->format
= format
;
895 while (instr
->operands
.size() > 1)
896 instr
->operands
.pop_back();
897 instr
->operands
[0] = vec_op
;
899 if (vec_op
.isConstant()) {
900 if (vec_op
.isLiteral())
901 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
902 else if (vec_op
.size() == 1)
903 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
904 else if (vec_op
.size() == 2)
905 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(vec_op
.constantValue());
908 assert(vec_op
.isTemp());
909 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
914 case aco_opcode::s_mov_b32
: /* propagate */
915 case aco_opcode::s_mov_b64
:
916 case aco_opcode::v_mov_b32
:
917 case aco_opcode::p_as_uniform
:
918 if (instr
->definitions
[0].isFixed()) {
919 /* don't copy-propagate copies into fixed registers */
920 } else if (instr
->usesModifiers()) {
922 } else if (instr
->operands
[0].isConstant()) {
923 if (instr
->operands
[0].isLiteral())
924 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
925 else if (instr
->operands
[0].size() == 1)
926 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
927 else if (instr
->operands
[0].size() == 2)
928 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
929 } else if (instr
->operands
[0].isTemp()) {
930 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
932 assert(instr
->operands
[0].isFixed());
935 case aco_opcode::p_is_helper
:
936 if (!ctx
.program
->needs_wqm
)
937 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
939 case aco_opcode::s_movk_i32
: {
940 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
941 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
942 if (v
<= 64 || v
>= 0xfffffff0)
943 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
945 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
948 case aco_opcode::v_bfrev_b32
:
949 case aco_opcode::s_brev_b32
: {
950 if (instr
->operands
[0].isConstant()) {
951 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
952 if (v
<= 64 || v
>= 0xfffffff0)
953 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
955 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
959 case aco_opcode::s_bfm_b32
: {
960 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
961 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
962 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
963 uint32_t v
= ((1u << size
) - 1u) << start
;
964 if (v
<= 64 || v
>= 0xfffffff0)
965 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
967 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
970 case aco_opcode::v_mul_f32
: { /* omod */
971 /* TODO: try to move the negate/abs modifier to the consumer instead */
972 if (instr
->usesModifiers())
975 for (unsigned i
= 0; i
< 2; i
++) {
976 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
977 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
978 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
979 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
980 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
981 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
982 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
983 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
984 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
985 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
994 case aco_opcode::v_and_b32
: /* abs */
995 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
996 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
997 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
999 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1001 case aco_opcode::v_xor_b32
: { /* neg */
1002 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1003 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1004 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1005 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1006 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1007 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1008 instr
->opcode
= aco_opcode::v_or_b32
;
1009 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1011 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1015 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1019 case aco_opcode::v_med3_f32
: { /* clamp */
1020 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1021 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1022 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1023 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1027 bool found_zero
= false, found_one
= false;
1028 for (unsigned i
= 0; i
< 3; i
++)
1030 if (instr
->operands
[i
].constantEquals(0))
1032 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1037 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1038 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1042 case aco_opcode::v_cndmask_b32
:
1043 if (instr
->operands
[0].constantEquals(0) &&
1044 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1045 instr
->operands
[2].isTemp())
1046 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1047 else if (instr
->operands
[0].constantEquals(0) &&
1048 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1049 instr
->operands
[2].isTemp())
1050 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1052 case aco_opcode::v_cmp_lg_u32
:
1053 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1054 instr
->operands
[0].constantEquals(0) &&
1055 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1056 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1058 case aco_opcode::p_phi
:
1059 case aco_opcode::p_linear_phi
: {
1060 /* lower_bool_phis() can create phis like this */
1061 bool all_same_temp
= instr
->operands
[0].isTemp();
1062 /* this check is needed when moving uniform loop counters out of a divergent loop */
1064 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1065 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1066 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1067 all_same_temp
= false;
1069 if (all_same_temp
) {
1070 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1072 bool all_undef
= instr
->operands
[0].isUndefined();
1073 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1074 if (!instr
->operands
[i
].isUndefined())
1078 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1082 case aco_opcode::v_add_u32
:
1083 case aco_opcode::v_add_co_u32
:
1084 case aco_opcode::s_add_i32
:
1085 case aco_opcode::s_add_u32
:
1086 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1088 case aco_opcode::s_and_b32
:
1089 case aco_opcode::s_and_b64
:
1090 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1091 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1092 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1095 case aco_opcode::s_not_b32
:
1096 case aco_opcode::s_not_b64
:
1097 case aco_opcode::s_or_b32
:
1098 case aco_opcode::s_or_b64
:
1099 case aco_opcode::s_xor_b32
:
1100 case aco_opcode::s_xor_b64
:
1101 case aco_opcode::s_lshl_b32
:
1102 case aco_opcode::v_or_b32
:
1103 case aco_opcode::v_lshlrev_b32
:
1104 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1106 case aco_opcode::v_min_f32
:
1107 case aco_opcode::v_min_f16
:
1108 case aco_opcode::v_min_u32
:
1109 case aco_opcode::v_min_i32
:
1110 case aco_opcode::v_min_u16
:
1111 case aco_opcode::v_min_i16
:
1112 case aco_opcode::v_max_f32
:
1113 case aco_opcode::v_max_f16
:
1114 case aco_opcode::v_max_u32
:
1115 case aco_opcode::v_max_i32
:
1116 case aco_opcode::v_max_u16
:
1117 case aco_opcode::v_max_i16
:
1118 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1120 case aco_opcode::v_cmp_lt_f32
:
1121 case aco_opcode::v_cmp_eq_f32
:
1122 case aco_opcode::v_cmp_le_f32
:
1123 case aco_opcode::v_cmp_gt_f32
:
1124 case aco_opcode::v_cmp_lg_f32
:
1125 case aco_opcode::v_cmp_ge_f32
:
1126 case aco_opcode::v_cmp_o_f32
:
1127 case aco_opcode::v_cmp_u_f32
:
1128 case aco_opcode::v_cmp_nge_f32
:
1129 case aco_opcode::v_cmp_nlg_f32
:
1130 case aco_opcode::v_cmp_ngt_f32
:
1131 case aco_opcode::v_cmp_nle_f32
:
1132 case aco_opcode::v_cmp_neq_f32
:
1133 case aco_opcode::v_cmp_nlt_f32
:
1134 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1136 case aco_opcode::s_cselect_b64
:
1137 case aco_opcode::s_cselect_b32
:
1138 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1139 instr
->operands
[1].constantEquals(0)) {
1140 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1141 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1149 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1151 *ordered
= *unordered
= op
;
1153 #define CMP(ord, unord) \
1154 case aco_opcode::v_cmp_##ord##_f32:\
1155 case aco_opcode::v_cmp_n##unord##_f32:\
1156 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1157 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1158 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1172 aco_opcode
get_ordered(aco_opcode op
)
1174 aco_opcode ordered
, unordered
, inverse
;
1175 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1178 aco_opcode
get_unordered(aco_opcode op
)
1180 aco_opcode ordered
, unordered
, inverse
;
1181 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1184 aco_opcode
get_inverse(aco_opcode op
)
1186 aco_opcode ordered
, unordered
, inverse
;
1187 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1190 bool is_cmp(aco_opcode op
)
1192 aco_opcode ordered
, unordered
, inverse
;
1193 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1196 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1198 if (ctx
.info
[tmp
.id()].is_temp())
1199 return ctx
.info
[tmp
.id()].temp
.id();
1204 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1206 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1207 for (const Operand
& op
: instr
->operands
) {
1209 ctx
.uses
[op
.tempId()]--;
1214 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1216 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1218 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1221 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1223 if (instr
->definitions
.size() == 2) {
1224 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1225 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1232 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1233 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1234 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1236 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1238 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1241 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1243 bool neg
[2] = {false, false};
1244 bool abs
[2] = {false, false};
1246 Instruction
*op_instr
[2];
1249 for (unsigned i
= 0; i
< 2; i
++) {
1250 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1254 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1256 if (op_instr
[i
]->opcode
!= expected_cmp
)
1258 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1261 if (op_instr
[i
]->isVOP3()) {
1262 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1263 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1265 neg
[i
] = vop3
->neg
[0];
1266 abs
[i
] = vop3
->abs
[0];
1267 opsel
|= (vop3
->opsel
& 1) << i
;
1270 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1271 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1272 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1278 if (op
[1].type() == RegType::sgpr
)
1279 std::swap(op
[0], op
[1]);
1280 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1281 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1284 ctx
.uses
[op
[0].id()]++;
1285 ctx
.uses
[op
[1].id()]++;
1286 decrease_uses(ctx
, op_instr
[0]);
1287 decrease_uses(ctx
, op_instr
[1]);
1289 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1290 Instruction
*new_instr
;
1291 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1292 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1293 for (unsigned i
= 0; i
< 2; i
++) {
1294 vop3
->neg
[i
] = neg
[i
];
1295 vop3
->abs
[i
] = abs
[i
];
1297 vop3
->opsel
= opsel
;
1298 new_instr
= static_cast<Instruction
*>(vop3
);
1300 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1302 new_instr
->operands
[0] = Operand(op
[0]);
1303 new_instr
->operands
[1] = Operand(op
[1]);
1304 new_instr
->definitions
[0] = instr
->definitions
[0];
1306 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1307 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1309 instr
.reset(new_instr
);
1314 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1315 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1316 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1318 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1320 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1323 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1324 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1326 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1327 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1328 if (!nan_test
|| !cmp
)
1331 if (cmp
->opcode
== expected_nan_test
)
1332 std::swap(nan_test
, cmp
);
1333 else if (nan_test
->opcode
!= expected_nan_test
)
1336 if (!is_cmp(cmp
->opcode
))
1339 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1341 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1344 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1345 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1346 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1347 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1348 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1350 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1353 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1354 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1355 decrease_uses(ctx
, nan_test
);
1356 decrease_uses(ctx
, cmp
);
1358 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1359 Instruction
*new_instr
;
1360 if (cmp
->isVOP3()) {
1361 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1362 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1363 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1364 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1365 new_vop3
->clamp
= cmp_vop3
->clamp
;
1366 new_vop3
->omod
= cmp_vop3
->omod
;
1367 new_vop3
->opsel
= cmp_vop3
->opsel
;
1368 new_instr
= new_vop3
;
1370 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1372 new_instr
->operands
[0] = cmp
->operands
[0];
1373 new_instr
->operands
[1] = cmp
->operands
[1];
1374 new_instr
->definitions
[0] = instr
->definitions
[0];
1376 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1377 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1379 instr
.reset(new_instr
);
1384 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1385 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1386 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1388 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1390 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1393 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1395 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1396 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1398 if (!nan_test
|| !cmp
)
1401 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1402 if (cmp
->opcode
== expected_nan_test
)
1403 std::swap(nan_test
, cmp
);
1404 else if (nan_test
->opcode
!= expected_nan_test
)
1407 if (!is_cmp(cmp
->opcode
))
1410 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1412 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1415 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1416 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1417 if (prop_nan0
!= prop_nan1
)
1420 if (nan_test
->isVOP3()) {
1421 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1422 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1426 int constant_operand
= -1;
1427 for (unsigned i
= 0; i
< 2; i
++) {
1428 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1429 constant_operand
= !i
;
1433 if (constant_operand
== -1)
1437 if (cmp
->operands
[constant_operand
].isConstant()) {
1438 constant
= cmp
->operands
[constant_operand
].constantValue();
1439 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1440 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1441 unsigned id
= original_temp_id(ctx
, tmp
);
1442 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1444 constant
= ctx
.info
[id
].val
;
1450 memcpy(&constantf
, &constant
, 4);
1451 if (isnan(constantf
))
1454 if (cmp
->operands
[0].isTemp())
1455 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1456 if (cmp
->operands
[1].isTemp())
1457 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1458 decrease_uses(ctx
, nan_test
);
1459 decrease_uses(ctx
, cmp
);
1461 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1462 Instruction
*new_instr
;
1463 if (cmp
->isVOP3()) {
1464 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1465 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1466 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1467 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1468 new_vop3
->clamp
= cmp_vop3
->clamp
;
1469 new_vop3
->omod
= cmp_vop3
->omod
;
1470 new_vop3
->opsel
= cmp_vop3
->opsel
;
1471 new_instr
= new_vop3
;
1473 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1475 new_instr
->operands
[0] = cmp
->operands
[0];
1476 new_instr
->operands
[1] = cmp
->operands
[1];
1477 new_instr
->definitions
[0] = instr
->definitions
[0];
1479 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1480 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1482 instr
.reset(new_instr
);
1487 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1488 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1490 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1492 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1494 if (!instr
->operands
[0].isTemp())
1497 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1501 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1502 if (new_opcode
== aco_opcode::last_opcode
)
1505 if (cmp
->operands
[0].isTemp())
1506 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1507 if (cmp
->operands
[1].isTemp())
1508 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1509 decrease_uses(ctx
, cmp
);
1511 Instruction
*new_instr
;
1512 if (cmp
->isVOP3()) {
1513 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1514 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1515 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1516 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1517 new_vop3
->clamp
= cmp_vop3
->clamp
;
1518 new_vop3
->omod
= cmp_vop3
->omod
;
1519 new_vop3
->opsel
= cmp_vop3
->opsel
;
1520 new_instr
= new_vop3
;
1522 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1524 new_instr
->operands
[0] = cmp
->operands
[0];
1525 new_instr
->operands
[1] = cmp
->operands
[1];
1526 new_instr
->definitions
[0] = instr
->definitions
[0];
1528 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1529 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1531 instr
.reset(new_instr
);
1536 /* op1(op2(1, 2), 0) if swap = false
1537 * op1(0, op2(1, 2)) if swap = true */
1538 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1539 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1540 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1541 bool *op1_clamp
, uint8_t *op1_omod
,
1542 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1545 if (op1_instr
->opcode
!= op1
)
1548 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1549 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1552 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1553 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1555 /* don't support inbetween clamp/omod */
1556 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1559 /* get operands and modifiers and check inbetween modifiers */
1560 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1561 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1564 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1565 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1569 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1570 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1573 if (inbetween_opsel
)
1574 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1575 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1579 shuffle
[shuffle_str
[0] - '0'] = 0;
1580 shuffle
[shuffle_str
[1] - '0'] = 1;
1581 shuffle
[shuffle_str
[2] - '0'] = 2;
1583 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1584 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1585 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1586 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1587 *opsel
|= 1 << shuffle
[0];
1589 for (unsigned i
= 0; i
< 2; i
++) {
1590 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1591 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1592 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1593 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1594 *opsel
|= 1 << shuffle
[i
+ 1];
1597 /* check operands */
1598 if (!check_vop3_operands(ctx
, 3, operands
))
1604 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1605 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1606 bool clamp
, unsigned omod
)
1608 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1609 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1610 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1611 new_instr
->clamp
= clamp
;
1612 new_instr
->omod
= omod
;
1613 new_instr
->opsel
= opsel
;
1614 new_instr
->operands
[0] = operands
[0];
1615 new_instr
->operands
[1] = operands
[1];
1616 new_instr
->operands
[2] = operands
[2];
1617 new_instr
->definitions
[0] = instr
->definitions
[0];
1618 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1620 instr
.reset(new_instr
);
1623 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1625 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1626 (label_omod_success
| label_clamp_success
);
1628 for (unsigned swap
= 0; swap
< 2; swap
++) {
1629 if (!((1 << swap
) & ops
))
1632 Operand operands
[3];
1633 bool neg
[3], abs
[3], clamp
;
1634 uint8_t opsel
= 0, omod
= 0;
1635 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1636 instr
.get(), swap
, shuffle
,
1637 operands
, neg
, abs
, &opsel
,
1638 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1639 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1640 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1641 if (omod_clamp
& label_omod_success
)
1642 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1643 if (omod_clamp
& label_clamp_success
)
1644 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1651 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1653 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1656 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1657 (label_omod_success
| label_clamp_success
);
1659 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1660 * max(-min(a, b), c) -> max3(-a, -b, c) */
1661 for (unsigned swap
= 0; swap
< 2; swap
++) {
1662 Operand operands
[3];
1663 bool neg
[3], abs
[3], clamp
;
1664 uint8_t opsel
= 0, omod
= 0;
1666 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1667 instr
.get(), swap
, "012",
1668 operands
, neg
, abs
, &opsel
,
1669 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1671 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1674 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1675 if (omod_clamp
& label_omod_success
)
1676 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1677 if (omod_clamp
& label_clamp_success
)
1678 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1685 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1686 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1687 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1688 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1689 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1690 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1691 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1694 if (!instr
->operands
[0].isTemp())
1696 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1699 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1702 switch (op2_instr
->opcode
) {
1703 case aco_opcode::s_and_b32
:
1704 case aco_opcode::s_or_b32
:
1705 case aco_opcode::s_xor_b32
:
1706 case aco_opcode::s_and_b64
:
1707 case aco_opcode::s_or_b64
:
1708 case aco_opcode::s_xor_b64
:
1714 /* create instruction */
1715 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1716 ctx
.uses
[instr
->operands
[0].tempId()]--;
1717 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1719 switch (op2_instr
->opcode
) {
1720 case aco_opcode::s_and_b32
:
1721 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1723 case aco_opcode::s_or_b32
:
1724 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1726 case aco_opcode::s_xor_b32
:
1727 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1729 case aco_opcode::s_and_b64
:
1730 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1732 case aco_opcode::s_or_b64
:
1733 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1735 case aco_opcode::s_xor_b64
:
1736 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1745 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1746 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1747 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1748 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1749 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1751 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1754 for (unsigned i
= 0; i
< 2; i
++) {
1755 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1756 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1759 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1760 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1763 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1764 instr
->operands
[0] = instr
->operands
[!i
];
1765 instr
->operands
[1] = op2_instr
->operands
[0];
1766 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1768 switch (instr
->opcode
) {
1769 case aco_opcode::s_and_b32
:
1770 instr
->opcode
= aco_opcode::s_andn2_b32
;
1772 case aco_opcode::s_or_b32
:
1773 instr
->opcode
= aco_opcode::s_orn2_b32
;
1775 case aco_opcode::s_and_b64
:
1776 instr
->opcode
= aco_opcode::s_andn2_b64
;
1778 case aco_opcode::s_or_b64
:
1779 instr
->opcode
= aco_opcode::s_orn2_b64
;
1790 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1791 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1793 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1796 for (unsigned i
= 0; i
< 2; i
++) {
1797 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1798 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1801 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1802 if (shift
< 1 || shift
> 4)
1805 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1806 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1809 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1810 instr
->operands
[1] = instr
->operands
[!i
];
1811 instr
->operands
[0] = op2_instr
->operands
[0];
1812 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1814 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1815 aco_opcode::s_lshl2_add_u32
,
1816 aco_opcode::s_lshl3_add_u32
,
1817 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1824 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1827 #define MINMAX(type, gfx9) \
1828 case aco_opcode::v_min_##type:\
1829 case aco_opcode::v_max_##type:\
1830 case aco_opcode::v_med3_##type:\
1831 *min = aco_opcode::v_min_##type;\
1832 *max = aco_opcode::v_max_##type;\
1833 *med3 = aco_opcode::v_med3_##type;\
1834 *min3 = aco_opcode::v_min3_##type;\
1835 *max3 = aco_opcode::v_max3_##type;\
1836 *some_gfx9_only = gfx9;\
1850 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1851 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1852 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1853 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1855 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1856 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1857 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1858 aco_opcode other_op
;
1859 if (instr
->opcode
== min
)
1861 else if (instr
->opcode
== max
)
1866 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1867 (label_omod_success
| label_clamp_success
);
1869 for (unsigned swap
= 0; swap
< 2; swap
++) {
1870 Operand operands
[3];
1871 bool neg
[3], abs
[3], clamp
;
1872 uint8_t opsel
= 0, omod
= 0;
1873 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1874 "012", operands
, neg
, abs
, &opsel
,
1875 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1876 int const0_idx
= -1, const1_idx
= -1;
1877 uint32_t const0
= 0, const1
= 0;
1878 for (int i
= 0; i
< 3; i
++) {
1880 if (operands
[i
].isConstant()) {
1881 val
= operands
[i
].constantValue();
1882 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1883 val
= ctx
.info
[operands
[i
].tempId()].val
;
1887 if (const0_idx
>= 0) {
1895 if (const0_idx
< 0 || const1_idx
< 0)
1898 if (opsel
& (1 << const0_idx
))
1900 if (opsel
& (1 << const1_idx
))
1903 int lower_idx
= const0_idx
;
1905 case aco_opcode::v_min_f32
:
1906 case aco_opcode::v_min_f16
: {
1907 float const0_f
, const1_f
;
1908 if (min
== aco_opcode::v_min_f32
) {
1909 memcpy(&const0_f
, &const0
, 4);
1910 memcpy(&const1_f
, &const1
, 4);
1912 const0_f
= _mesa_half_to_float(const0
);
1913 const1_f
= _mesa_half_to_float(const1
);
1915 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1916 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1917 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1918 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1919 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1922 case aco_opcode::v_min_u32
: {
1923 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1926 case aco_opcode::v_min_u16
: {
1927 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1930 case aco_opcode::v_min_i32
: {
1931 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1932 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1933 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1936 case aco_opcode::v_min_i16
: {
1937 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1938 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1939 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1945 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1947 if (instr
->opcode
== min
) {
1948 if (upper_idx
!= 0 || lower_idx
== 0)
1951 if (upper_idx
== 0 || lower_idx
!= 0)
1955 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1956 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1957 if (omod_clamp
& label_omod_success
)
1958 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1959 if (omod_clamp
& label_clamp_success
)
1960 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1970 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1972 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
1973 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
1974 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
1976 /* find candidates and create the set of sgprs already read */
1977 unsigned sgpr_ids
[2] = {0, 0};
1978 uint32_t operand_mask
= 0;
1979 bool has_literal
= false;
1980 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1981 if (instr
->operands
[i
].isLiteral())
1983 if (!instr
->operands
[i
].isTemp())
1985 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1986 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
1987 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
1989 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1990 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
1991 operand_mask
|= 1u << i
;
1993 unsigned max_sgprs
= 1;
1994 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
1999 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2001 /* keep on applying sgprs until there is nothing left to be done */
2002 while (operand_mask
) {
2003 uint32_t sgpr_idx
= 0;
2004 uint32_t sgpr_info_id
= 0;
2005 uint32_t mask
= operand_mask
;
2008 unsigned i
= u_bit_scan(&mask
);
2009 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2010 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2012 sgpr_info_id
= instr
->operands
[i
].tempId();
2015 operand_mask
&= ~(1u << sgpr_idx
);
2017 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2018 * definitively beneficial.
2019 * TODO: this is too conservative because later the use count could be reduced to 1 */
2020 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2023 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2024 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2025 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2028 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2029 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2030 } else if (can_swap_operands(instr
)) {
2031 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2032 instr
->operands
[0] = Operand(sgpr
);
2033 /* swap bits using a 4-entry LUT */
2034 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2035 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2036 } else if (can_use_VOP3(ctx
, instr
)) {
2037 to_VOP3(ctx
, instr
);
2038 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2043 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2044 ctx
.uses
[sgpr_info_id
]--;
2045 ctx
.uses
[sgpr
.id()]++;
2049 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2051 /* check if we could apply omod on predecessor */
2052 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2053 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2054 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2056 unsigned idx
= op0
? 0 : 1;
2057 /* omod was successfully applied */
2058 /* if the omod instruction is v_mad, we also have to change the original add */
2059 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2060 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2061 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2062 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2063 add_instr
->definitions
[0] = instr
->definitions
[0];
2066 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2067 /* check if we have an additional clamp modifier */
2068 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2069 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2070 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2071 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2073 /* change definition ssa-id of modified instruction */
2074 omod_instr
->definitions
[0] = instr
->definitions
[0];
2076 /* change the definition of instr to something unused, e.g. the original omod def */
2077 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2078 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2081 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2082 /* in all other cases, label this instruction as option for multiply-add */
2083 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2087 /* check if we could apply clamp on predecessor */
2088 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2090 bool found_zero
= false, found_one
= false;
2091 for (unsigned i
= 0; i
< 3; i
++)
2093 if (instr
->operands
[i
].constantEquals(0))
2095 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2100 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2101 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2102 /* clamp was successfully applied */
2103 /* if the clamp instruction is v_mad, we also have to change the original add */
2104 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2105 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2106 add_instr
->definitions
[0] = instr
->definitions
[0];
2108 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2109 /* change definition ssa-id of modified instruction */
2110 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2112 /* change the definition of instr to something unused, e.g. the original omod def */
2113 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2114 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2119 /* omod has no effect if denormals are enabled */
2120 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2122 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2123 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2124 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2125 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2126 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2127 to_VOP3(ctx
, instr
);
2128 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2129 def_info
.set_omod_success(instr
.get());
2130 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2131 to_VOP3(ctx
, instr
);
2132 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2133 def_info
.set_omod_success(instr
.get());
2134 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2135 to_VOP3(ctx
, instr
);
2136 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2137 def_info
.set_omod_success(instr
.get());
2138 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2139 to_VOP3(ctx
, instr
);
2140 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2141 def_info
.set_clamp_success(instr
.get());
2148 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2149 // this would mean that we'd have to fix the instruction uses while value propagation
2151 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2153 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2156 if (instr
->isVALU()) {
2157 if (can_apply_sgprs(instr
))
2158 apply_sgprs(ctx
, instr
);
2159 if (apply_omod_clamp(ctx
, block
, instr
))
2163 /* TODO: There are still some peephole optimizations that could be done:
2164 * - abs(a - b) -> s_absdiff_i32
2165 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2166 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2167 * These aren't probably too interesting though.
2168 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2169 * probably more useful than the previously mentioned optimizations.
2170 * The various comparison optimizations also currently only work with 32-bit
2173 /* neg(mul(a, b)) -> mul(neg(a), b) */
2174 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2175 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2177 if (!ctx
.info
[val
.id()].is_mul())
2180 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2182 if (mul_instr
->operands
[0].isLiteral())
2184 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2187 /* convert to mul(neg(a), b) */
2188 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2189 Definition def
= instr
->definitions
[0];
2190 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2191 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2192 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2193 instr
->operands
[0] = mul_instr
->operands
[0];
2194 instr
->operands
[1] = mul_instr
->operands
[1];
2195 instr
->definitions
[0] = def
;
2196 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2197 if (mul_instr
->isVOP3()) {
2198 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2199 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2200 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2201 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2202 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2203 new_mul
->omod
= mul
->omod
;
2205 new_mul
->neg
[0] ^= true;
2206 new_mul
->clamp
= false;
2208 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2211 /* combine mul+add -> mad */
2212 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2213 instr
->opcode
== aco_opcode::v_sub_f32
||
2214 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2215 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2216 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2218 uint32_t uses_src0
= UINT32_MAX
;
2219 uint32_t uses_src1
= UINT32_MAX
;
2220 Instruction
* mul_instr
= nullptr;
2221 unsigned add_op_idx
;
2222 /* check if any of the operands is a multiplication */
2223 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2224 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2225 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2226 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2228 /* find the 'best' mul instruction to combine with the add */
2229 if (uses_src0
< uses_src1
) {
2230 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2232 } else if (uses_src1
< uses_src0
) {
2233 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2235 } else if (uses_src0
!= UINT32_MAX
) {
2236 /* tiebreaker: quite random what to pick */
2237 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2238 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2241 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2246 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2247 bool neg
[3] = {false, false, false};
2248 bool abs
[3] = {false, false, false};
2251 op
[0] = mul_instr
->operands
[0];
2252 op
[1] = mul_instr
->operands
[1];
2253 op
[2] = instr
->operands
[add_op_idx
];
2254 // TODO: would be better to check this before selecting a mul instr?
2255 if (!check_vop3_operands(ctx
, 3, op
))
2258 if (mul_instr
->isVOP3()) {
2259 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2260 neg
[0] = vop3
->neg
[0];
2261 neg
[1] = vop3
->neg
[1];
2262 abs
[0] = vop3
->abs
[0];
2263 abs
[1] = vop3
->abs
[1];
2264 /* we cannot use these modifiers between mul and add */
2265 if (vop3
->clamp
|| vop3
->omod
)
2269 /* convert to mad */
2270 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2271 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2273 ctx
.uses
[op
[0].tempId()]++;
2275 ctx
.uses
[op
[1].tempId()]++;
2278 if (instr
->isVOP3()) {
2279 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2280 neg
[2] = vop3
->neg
[add_op_idx
];
2281 abs
[2] = vop3
->abs
[add_op_idx
];
2283 clamp
= vop3
->clamp
;
2284 /* abs of the multiplication result */
2285 if (vop3
->abs
[1 - add_op_idx
]) {
2291 /* neg of the multiplication result */
2292 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2294 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2295 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2296 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2297 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2299 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2300 for (unsigned i
= 0; i
< 3; i
++)
2302 mad
->operands
[i
] = op
[i
];
2303 mad
->neg
[i
] = neg
[i
];
2304 mad
->abs
[i
] = abs
[i
];
2308 mad
->definitions
[0] = instr
->definitions
[0];
2310 /* mark this ssa_def to be re-checked for profitability and literals */
2311 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2312 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2313 instr
.reset(mad
.release());
2317 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2318 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2319 for (unsigned i
= 0; i
< 2; i
++) {
2320 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2321 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2322 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2323 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2324 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2326 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2327 new_instr
->operands
[0] = Operand(0u);
2328 new_instr
->operands
[1] = instr
->operands
[!i
];
2329 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2330 new_instr
->definitions
[0] = instr
->definitions
[0];
2331 instr
.reset(new_instr
.release());
2332 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2336 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2337 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2338 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2339 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2340 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2341 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2342 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2343 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2344 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2345 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2346 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2347 combine_salu_lshl_add(ctx
, instr
);
2348 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2349 combine_salu_not_bitwise(ctx
, instr
);
2350 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2351 if (combine_inverse_comparison(ctx
, instr
)) ;
2352 else combine_salu_not_bitwise(ctx
, instr
);
2353 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2354 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2355 if (combine_ordering_test(ctx
, instr
)) ;
2356 else if (combine_comparison_ordering(ctx
, instr
)) ;
2357 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2358 else combine_salu_n2(ctx
, instr
);
2360 aco_opcode min
, max
, min3
, max3
, med3
;
2361 bool some_gfx9_only
;
2362 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2363 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2364 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2365 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2371 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2373 const uint32_t threshold
= 4;
2375 if (is_dead(ctx
.uses
, instr
.get())) {
2380 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2381 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2382 unsigned num_used
= 0;
2384 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2385 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2391 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2392 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2393 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2397 for (Operand
& vec_op
: vec
->operands
) {
2398 if (off
== idx
* instr
->definitions
[0].size()) {
2402 off
+= vec_op
.size();
2404 if (off
!= instr
->operands
[0].size()) {
2405 ctx
.uses
[instr
->operands
[0].tempId()]--;
2406 for (Operand
& vec_op
: vec
->operands
) {
2407 if (vec_op
.isTemp())
2408 ctx
.uses
[vec_op
.tempId()]--;
2411 ctx
.uses
[op
.tempId()]++;
2413 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2414 extract
->operands
[0] = op
;
2415 extract
->definitions
[0] = instr
->definitions
[idx
];
2416 instr
.reset(extract
.release());
2422 if (!done
&& num_used
== 1) {
2423 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2424 extract
->operands
[0] = instr
->operands
[0];
2425 extract
->operands
[1] = Operand((uint32_t) idx
);
2426 extract
->definitions
[0] = instr
->definitions
[idx
];
2427 instr
.reset(extract
.release());
2431 mad_info
* mad_info
= NULL
;
2432 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2433 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2434 /* re-check mad instructions */
2435 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2436 ctx
.uses
[mad_info
->mul_temp_id
]++;
2437 if (instr
->operands
[0].isTemp())
2438 ctx
.uses
[instr
->operands
[0].tempId()]--;
2439 if (instr
->operands
[1].isTemp())
2440 ctx
.uses
[instr
->operands
[1].tempId()]--;
2441 instr
.swap(mad_info
->add_instr
);
2444 /* check literals */
2445 else if (!instr
->usesModifiers()) {
2446 bool sgpr_used
= false;
2447 uint32_t literal_idx
= 0;
2448 uint32_t literal_uses
= UINT32_MAX
;
2449 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2451 if (instr
->operands
[i
].isConstant() && i
> 0) {
2452 literal_uses
= UINT32_MAX
;
2455 if (!instr
->operands
[i
].isTemp())
2457 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2458 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2459 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2460 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2463 literal_uses
= UINT32_MAX
;
2466 /* don't break because we still need to check constants */
2467 } else if (!sgpr_used
&&
2468 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2469 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2470 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2474 if (literal_uses
< threshold
) {
2475 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2476 mad_info
->check_literal
= true;
2477 mad_info
->literal_idx
= literal_idx
;
2483 /* check for literals */
2484 if (!instr
->isSALU() && !instr
->isVALU())
2487 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2488 return; /* some encodings can't ever take literals */
2490 /* we do not apply the literals yet as we don't know if it is profitable */
2491 Operand
current_literal(s1
);
2493 unsigned literal_id
= 0;
2494 unsigned literal_uses
= UINT32_MAX
;
2495 Operand
literal(s1
);
2496 unsigned num_operands
= 1;
2497 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2498 num_operands
= instr
->operands
.size();
2500 unsigned sgpr_ids
[2] = {0, 0};
2501 bool is_literal_sgpr
= false;
2504 /* choose a literal to apply */
2505 for (unsigned i
= 0; i
< num_operands
; i
++) {
2506 Operand op
= instr
->operands
[i
];
2507 if (op
.isLiteral()) {
2508 current_literal
= op
;
2510 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2511 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2512 op
.tempId() != sgpr_ids
[0])
2513 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2517 if (!can_accept_constant(instr
, i
))
2520 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2521 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2523 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2524 literal_uses
= ctx
.uses
[op
.tempId()];
2525 literal_id
= op
.tempId();
2528 mask
|= (op
.tempId() == literal_id
) << i
;
2532 /* don't go over the constant bus limit */
2533 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2534 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2535 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2536 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2537 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2538 const_bus_limit
= 2;
2540 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2541 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2544 if (literal_id
&& literal_uses
< threshold
&&
2545 (current_literal
.isUndefined() ||
2546 (current_literal
.size() == literal
.size() &&
2547 current_literal
.constantValue() == literal
.constantValue()))) {
2548 /* mark the literal to be applied */
2550 unsigned i
= u_bit_scan(&mask
);
2551 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2552 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2558 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2560 /* Cleanup Dead Instructions */
2564 /* apply literals on MAD */
2565 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2566 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2567 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2568 aco_ptr
<Instruction
> new_mad
;
2569 if (info
->literal_idx
== 2) { /* add literal -> madak */
2570 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2571 new_mad
->operands
[0] = instr
->operands
[0];
2572 new_mad
->operands
[1] = instr
->operands
[1];
2573 } else { /* mul literal -> madmk */
2574 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2575 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2576 new_mad
->operands
[1] = instr
->operands
[2];
2578 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2579 new_mad
->definitions
[0] = instr
->definitions
[0];
2580 ctx
.instructions
.emplace_back(std::move(new_mad
));
2585 /* apply literals on other SALU/VALU */
2586 if (instr
->isSALU() || instr
->isVALU()) {
2587 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2588 Operand op
= instr
->operands
[i
];
2589 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2590 Operand
literal(ctx
.info
[op
.tempId()].val
);
2591 if (instr
->isVALU() && i
> 0)
2592 to_VOP3(ctx
, instr
);
2593 instr
->operands
[i
] = literal
;
2598 ctx
.instructions
.emplace_back(std::move(instr
));
2602 void optimize(Program
* program
)
2605 ctx
.program
= program
;
2606 std::vector
<ssa_info
> info(program
->peekAllocationId());
2607 ctx
.info
= info
.data();
2609 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2610 for (Block
& block
: program
->blocks
) {
2611 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2612 label_instruction(ctx
, block
, instr
);
2615 ctx
.uses
= std::move(dead_code_analysis(program
));
2617 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2618 for (Block
& block
: program
->blocks
) {
2619 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2620 combine_instruction(ctx
, block
, instr
);
2623 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2624 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2625 Block
* block
= &(*it
);
2626 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2627 select_instruction(ctx
, *it
);
2630 /* 4. Add literals to instructions */
2631 for (Block
& block
: program
->blocks
) {
2632 ctx
.instructions
.clear();
2633 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2634 apply_literals(ctx
, instr
);
2635 block
.instructions
.swap(ctx
.instructions
);