2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
88 label_vcc_hint
= 1 << 25,
89 label_scc_needed
= 1 << 26,
93 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
94 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
95 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
96 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
97 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
107 ssa_info() : label(0) {}
109 void add_label(Label new_label
)
111 /* Since all labels which use "instr" use it for the same thing
112 * (indicating the defining instruction), there is no need to clear
113 * any other instr labels. */
114 if (new_label
& instr_labels
)
115 label
&= ~temp_labels
; /* instr and temp alias */
117 if (new_label
& temp_labels
) {
118 label
&= ~temp_labels
;
119 label
&= ~instr_labels
; /* instr and temp alias */
122 if (new_label
& val_labels
)
123 label
&= ~val_labels
;
128 void set_vec(Instruction
* vec
)
130 add_label(label_vec
);
136 return label
& label_vec
;
139 void set_constant(uint32_t constant
)
141 add_label(label_constant
);
147 return label
& label_constant
;
150 void set_constant_64bit(uint32_t constant
)
152 add_label(label_constant_64bit
);
156 bool is_constant_64bit()
158 return label
& label_constant_64bit
;
161 void set_abs(Temp abs_temp
)
163 add_label(label_abs
);
169 return label
& label_abs
;
172 void set_neg(Temp neg_temp
)
174 add_label(label_neg
);
180 return label
& label_neg
;
183 void set_neg_abs(Temp neg_abs_temp
)
185 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
189 void set_mul(Instruction
* mul
)
191 add_label(label_mul
);
197 return label
& label_mul
;
200 void set_temp(Temp tmp
)
202 add_label(label_temp
);
208 return label
& label_temp
;
211 void set_literal(uint32_t lit
)
213 add_label(label_literal
);
219 return label
& label_literal
;
222 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
224 add_label(label_mad
);
231 return label
& label_mad
;
234 void set_omod2(Temp def
)
236 add_label(label_omod2
);
242 return label
& label_omod2
;
245 void set_omod4(Temp def
)
247 add_label(label_omod4
);
253 return label
& label_omod4
;
256 void set_omod5(Temp def
)
258 add_label(label_omod5
);
264 return label
& label_omod5
;
267 void set_omod_success(Instruction
* omod_instr
)
269 add_label(label_omod_success
);
273 bool is_omod_success()
275 return label
& label_omod_success
;
278 void set_clamp(Temp def
)
280 add_label(label_clamp
);
286 return label
& label_clamp
;
289 void set_clamp_success(Instruction
* clamp_instr
)
291 add_label(label_clamp_success
);
295 bool is_clamp_success()
297 return label
& label_clamp_success
;
302 add_label(label_undefined
);
307 return label
& label_undefined
;
310 void set_vcc(Temp vcc
)
312 add_label(label_vcc
);
318 return label
& label_vcc
;
321 bool is_constant_or_literal()
323 return is_constant() || is_literal();
326 void set_b2f(Temp val
)
328 add_label(label_b2f
);
334 return label
& label_b2f
;
337 void set_add_sub(Instruction
*add_sub_instr
)
339 add_label(label_add_sub
);
340 instr
= add_sub_instr
;
345 return label
& label_add_sub
;
348 void set_bitwise(Instruction
*bitwise_instr
)
350 add_label(label_bitwise
);
351 instr
= bitwise_instr
;
356 return label
& label_bitwise
;
359 void set_uniform_bitwise()
361 add_label(label_uniform_bitwise
);
364 bool is_uniform_bitwise()
366 return label
& label_uniform_bitwise
;
369 void set_minmax(Instruction
*minmax_instr
)
371 add_label(label_minmax
);
372 instr
= minmax_instr
;
377 return label
& label_minmax
;
380 void set_fcmp(Instruction
*fcmp_instr
)
382 add_label(label_fcmp
);
388 return label
& label_fcmp
;
391 void set_scc_needed()
393 add_label(label_scc_needed
);
398 return label
& label_scc_needed
;
401 void set_scc_invert(Temp scc_inv
)
403 add_label(label_scc_invert
);
409 return label
& label_scc_invert
;
412 void set_uniform_bool(Temp uniform_bool
)
414 add_label(label_uniform_bool
);
418 bool is_uniform_bool()
420 return label
& label_uniform_bool
;
425 add_label(label_vcc_hint
);
430 return label
& label_vcc_hint
;
433 void set_b2i(Temp val
)
435 add_label(label_b2i
);
441 return label
& label_b2i
;
448 std::vector
<aco_ptr
<Instruction
>> instructions
;
450 std::pair
<uint32_t,Temp
> last_literal
;
451 std::vector
<mad_info
> mad_infos
;
452 std::vector
<uint16_t> uses
;
455 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
457 if (instr
->operands
[0].isConstant() ||
458 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
461 switch (instr
->opcode
) {
462 case aco_opcode::v_add_f32
:
463 case aco_opcode::v_mul_f32
:
464 case aco_opcode::v_or_b32
:
465 case aco_opcode::v_and_b32
:
466 case aco_opcode::v_xor_b32
:
467 case aco_opcode::v_max_f32
:
468 case aco_opcode::v_min_f32
:
469 case aco_opcode::v_max_i32
:
470 case aco_opcode::v_min_i32
:
471 case aco_opcode::v_max_u32
:
472 case aco_opcode::v_min_u32
:
473 case aco_opcode::v_cmp_eq_f32
:
474 case aco_opcode::v_cmp_lg_f32
:
476 case aco_opcode::v_sub_f32
:
477 instr
->opcode
= aco_opcode::v_subrev_f32
;
479 case aco_opcode::v_cmp_lt_f32
:
480 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
482 case aco_opcode::v_cmp_ge_f32
:
483 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
485 case aco_opcode::v_cmp_lt_i32
:
486 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
493 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
498 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
501 if (instr
->isDPP() || instr
->isSDWA())
504 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
505 instr
->opcode
!= aco_opcode::v_madak_f32
&&
506 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
507 instr
->opcode
!= aco_opcode::v_madak_f16
&&
508 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
509 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
510 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
511 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
512 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
513 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
514 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
517 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
519 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
520 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
521 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
522 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
523 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
526 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
531 aco_ptr
<Instruction
> tmp
= std::move(instr
);
532 Format format
= asVOP3(tmp
->format
);
533 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
534 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
535 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
536 instr
->definitions
[i
] = tmp
->definitions
[i
];
537 if (instr
->definitions
[i
].isTemp()) {
538 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
539 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
540 info
.instr
= instr
.get();
545 /* only covers special cases */
546 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
549 case aco_opcode::v_interp_p2_f32
:
550 case aco_opcode::v_mac_f32
:
551 case aco_opcode::v_writelane_b32
:
552 case aco_opcode::v_writelane_b32_e64
:
553 case aco_opcode::v_cndmask_b32
:
555 case aco_opcode::s_addk_i32
:
556 case aco_opcode::s_mulk_i32
:
557 case aco_opcode::p_wqm
:
558 case aco_opcode::p_extract_vector
:
559 case aco_opcode::p_split_vector
:
560 case aco_opcode::v_readlane_b32
:
561 case aco_opcode::v_readlane_b32_e64
:
562 case aco_opcode::v_readfirstlane_b32
:
569 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
571 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
572 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
577 /* check constant bus and literal limitations */
578 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
580 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
581 Operand
literal32(s1
);
582 Operand
literal64(s2
);
583 unsigned num_sgprs
= 0;
584 unsigned sgpr
[] = {0, 0};
586 for (unsigned i
= 0; i
< num_operands
; i
++) {
587 Operand op
= operands
[i
];
589 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
590 /* two reads of the same SGPR count as 1 to the limit */
591 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
593 sgpr
[num_sgprs
++] = op
.tempId();
598 } else if (op
.isLiteral()) {
599 if (ctx
.program
->chip_class
< GFX10
)
602 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
604 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
607 /* Any number of 32-bit literals counts as only 1 to the limit. Same
608 * (but separately) for 64-bit literals. */
609 if (op
.size() == 1 && literal32
.isUndefined()) {
612 } else if (op
.size() == 2 && literal64
.isUndefined()) {
625 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
627 Operand op
= instr
->operands
[op_index
];
631 Temp tmp
= op
.getTemp();
632 if (!ctx
.info
[tmp
.id()].is_add_sub())
635 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
637 switch (add_instr
->opcode
) {
638 case aco_opcode::v_add_u32
:
639 case aco_opcode::v_add_co_u32
:
640 case aco_opcode::v_add_co_u32_e64
:
641 case aco_opcode::s_add_i32
:
642 case aco_opcode::s_add_u32
:
648 if (add_instr
->usesModifiers())
651 for (unsigned i
= 0; i
< 2; i
++) {
652 if (add_instr
->operands
[i
].isConstant()) {
653 *offset
= add_instr
->operands
[i
].constantValue();
654 } else if (add_instr
->operands
[i
].isTemp() &&
655 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
656 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
660 if (!add_instr
->operands
[!i
].isTemp())
663 uint32_t offset2
= 0;
664 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
667 *base
= add_instr
->operands
[!i
].getTemp();
675 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
677 // TODO: this functions shouldn't be needed if we store Operand instead of value.
678 Operand
op(val
, is64bit
);
679 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
680 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
684 bool fixed_to_exec(Operand op
)
686 return op
.isFixed() && op
.physReg() == exec
;
689 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
691 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
692 ASSERTED
bool all_const
= false;
693 for (Operand
& op
: instr
->operands
)
694 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
695 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
698 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
700 if (!instr
->operands
[i
].isTemp())
703 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
704 /* propagate undef */
705 if (info
.is_undefined() && is_phi(instr
))
706 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
707 /* propagate reg->reg of same type */
708 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
709 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
710 info
= ctx
.info
[info
.temp
.id()];
713 /* SALU / PSEUDO: propagate inline constants */
714 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
715 const bool is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
716 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
717 // TODO: optimize SGPR and constant propagation for subdword pseudo instructions on gfx9+
721 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
722 instr
->operands
[i
].setTemp(info
.temp
);
723 info
= ctx
.info
[info
.temp
.id()];
724 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
725 /* propagate vgpr if it can take it */
726 switch (instr
->opcode
) {
727 case aco_opcode::p_create_vector
:
728 case aco_opcode::p_split_vector
:
729 case aco_opcode::p_extract_vector
:
730 case aco_opcode::p_phi
: {
731 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
732 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
734 instr
->operands
[i
] = Operand(info
.temp
);
735 info
= ctx
.info
[info
.temp
.id()];
743 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) &&
744 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
745 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
750 /* VALU: propagate neg, abs & inline constants */
751 else if (instr
->isVALU()) {
752 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
753 instr
->operands
[i
].setTemp(info
.temp
);
754 info
= ctx
.info
[info
.temp
.id()];
756 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
759 instr
->operands
[i
] = Operand(info
.temp
);
761 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
763 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
765 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
766 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
767 instr
->operands
[i
].setTemp(info
.temp
);
769 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
772 instr
->operands
[i
].setTemp(info
.temp
);
774 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
776 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
779 if ((info
.is_constant() || info
.is_constant_64bit()) && alu_can_accept_constant(instr
->opcode
, i
)) {
780 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
781 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
782 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
783 instr
->operands
[i
] = op
;
785 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
786 instr
->operands
[i
] = instr
->operands
[0];
787 instr
->operands
[0] = op
;
789 } else if (can_use_VOP3(ctx
, instr
)) {
791 instr
->operands
[i
] = op
;
797 /* MUBUF: propagate constants and combine additions */
798 else if (instr
->format
== Format::MUBUF
) {
799 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
802 while (info
.is_temp())
803 info
= ctx
.info
[info
.temp
.id()];
805 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
806 assert(!mubuf
->idxen
);
807 instr
->operands
[1] = Operand(v1
);
808 mubuf
->offset
+= info
.val
;
809 mubuf
->offen
= false;
811 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
812 instr
->operands
[2] = Operand((uint32_t) 0);
813 mubuf
->offset
+= info
.val
;
815 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
816 assert(!mubuf
->idxen
);
817 instr
->operands
[1].setTemp(base
);
818 mubuf
->offset
+= offset
;
820 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
821 instr
->operands
[i
].setTemp(base
);
822 mubuf
->offset
+= offset
;
827 /* DS: combine additions */
828 else if (instr
->format
== Format::DS
) {
830 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
833 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
834 if (has_usable_ds_offset
&&
835 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
836 base
.regClass() == instr
->operands
[i
].regClass() &&
837 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
838 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
839 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
840 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
841 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
843 if ((offset
& mask
) == 0 &&
844 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
845 ds
->offset1
+ (offset
>> shifts
) <= 255) {
846 instr
->operands
[i
].setTemp(base
);
847 ds
->offset0
+= offset
>> shifts
;
848 ds
->offset1
+= offset
>> shifts
;
851 if (ds
->offset0
+ offset
<= 65535) {
852 instr
->operands
[i
].setTemp(base
);
853 ds
->offset0
+= offset
;
859 /* SMEM: propagate constants and combine additions */
860 else if (instr
->format
== Format::SMEM
) {
862 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
865 if (i
== 1 && info
.is_constant_or_literal() &&
866 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
867 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
868 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
869 instr
->operands
[i
] = Operand(info
.val
);
871 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
872 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
874 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
875 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
879 smem
->operands
[1] = Operand(offset
);
880 smem
->operands
.back() = Operand(base
);
882 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
883 new_instr
->operands
[0] = smem
->operands
[0];
884 new_instr
->operands
[1] = Operand(offset
);
885 if (smem
->definitions
.empty())
886 new_instr
->operands
[2] = smem
->operands
[2];
887 new_instr
->operands
.back() = Operand(base
);
888 if (!smem
->definitions
.empty())
889 new_instr
->definitions
[0] = smem
->definitions
[0];
890 new_instr
->can_reorder
= smem
->can_reorder
;
891 new_instr
->barrier
= smem
->barrier
;
892 new_instr
->glc
= smem
->glc
;
893 new_instr
->dlc
= smem
->dlc
;
894 new_instr
->nv
= smem
->nv
;
895 new_instr
->disable_wqm
= smem
->disable_wqm
;
896 instr
.reset(new_instr
);
897 smem
= static_cast<SMEM_instruction
*>(instr
.get());
903 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
904 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
905 /* Flip the branch instruction to get rid of the scc_invert instruction */
906 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
907 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
912 /* if this instruction doesn't define anything, return */
913 if (instr
->definitions
.empty())
916 switch (instr
->opcode
) {
917 case aco_opcode::p_create_vector
: {
918 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
919 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
921 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
925 unsigned num_ops
= instr
->operands
.size();
926 for (const Operand
& op
: instr
->operands
) {
927 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
928 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
930 if (num_ops
!= instr
->operands
.size()) {
931 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
932 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
933 instr
->definitions
[0] = old_vec
->definitions
[0];
935 for (Operand
& old_op
: old_vec
->operands
) {
936 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
937 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
938 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
939 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
940 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
941 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
942 instr
->operands
[k
++] = op
;
945 instr
->operands
[k
++] = old_op
;
948 assert(k
== num_ops
);
951 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
954 case aco_opcode::p_split_vector
: {
955 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
957 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
958 unsigned split_offset
= 0;
959 unsigned vec_offset
= 0;
960 unsigned vec_index
= 0;
961 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
962 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
963 vec_offset
+= vec
->operands
[vec_index
++].bytes();
965 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
968 Operand vec_op
= vec
->operands
[vec_index
];
969 if (vec_op
.isConstant()) {
970 if (vec_op
.isLiteral())
971 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
972 else if (vec_op
.size() == 1)
973 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
974 else if (vec_op
.size() == 2)
975 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
976 } else if (vec_op
.isUndefined()) {
977 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
979 assert(vec_op
.isTemp());
980 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
985 case aco_opcode::p_extract_vector
: { /* mov */
986 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
989 /* check if we index directly into a vector element */
990 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
991 const unsigned index
= instr
->operands
[1].constantValue();
992 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
995 for (const Operand
& op
: vec
->operands
) {
996 if (offset
< dst_offset
) {
997 offset
+= op
.bytes();
999 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1003 /* convert this extract into a copy instruction */
1004 instr
->opcode
= aco_opcode::p_parallelcopy
;
1005 instr
->operands
.pop_back();
1006 instr
->operands
[0] = op
;
1008 if (op
.isConstant()) {
1010 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(op
.constantValue());
1011 else if (op
.size() == 1)
1012 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(op
.constantValue());
1013 else if (op
.size() == 2)
1014 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(op
.constantValue());
1015 } else if (op
.isUndefined()) {
1016 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1018 assert(op
.isTemp());
1019 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1025 case aco_opcode::s_mov_b32
: /* propagate */
1026 case aco_opcode::s_mov_b64
:
1027 case aco_opcode::v_mov_b32
:
1028 case aco_opcode::p_as_uniform
:
1029 if (instr
->definitions
[0].isFixed()) {
1030 /* don't copy-propagate copies into fixed registers */
1031 } else if (instr
->usesModifiers()) {
1033 } else if (instr
->operands
[0].isConstant()) {
1034 if (instr
->operands
[0].isLiteral())
1035 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
1036 else if (instr
->operands
[0].size() == 1)
1037 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
1038 else if (instr
->operands
[0].size() == 2)
1039 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
1040 } else if (instr
->operands
[0].isTemp()) {
1041 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1043 assert(instr
->operands
[0].isFixed());
1046 case aco_opcode::p_is_helper
:
1047 if (!ctx
.program
->needs_wqm
)
1048 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
1050 case aco_opcode::s_movk_i32
: {
1051 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1052 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1053 if (v
<= 64 || v
>= 0xfffffff0)
1054 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1056 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1059 case aco_opcode::v_bfrev_b32
:
1060 case aco_opcode::s_brev_b32
: {
1061 if (instr
->operands
[0].isConstant()) {
1062 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1063 if (v
<= 64 || v
>= 0xfffffff0)
1064 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1066 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1070 case aco_opcode::s_bfm_b32
: {
1071 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1072 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1073 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1074 uint32_t v
= ((1u << size
) - 1u) << start
;
1075 if (v
<= 64 || v
>= 0xfffffff0)
1076 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1078 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1082 case aco_opcode::v_mul_f32
: { /* omod */
1083 /* TODO: try to move the negate/abs modifier to the consumer instead */
1084 if (instr
->usesModifiers())
1087 for (unsigned i
= 0; i
< 2; i
++) {
1088 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1089 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1090 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1091 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1092 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1093 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1094 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1095 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1096 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1097 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1106 case aco_opcode::v_mul_f16
: {
1107 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1110 case aco_opcode::v_and_b32
: /* abs */
1111 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1112 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1113 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1115 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1117 case aco_opcode::v_xor_b32
: { /* neg */
1118 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1119 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1120 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1121 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1122 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1123 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1124 instr
->opcode
= aco_opcode::v_or_b32
;
1125 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1127 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1131 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1135 case aco_opcode::v_med3_f32
: { /* clamp */
1136 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1137 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1138 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1139 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1143 bool found_zero
= false, found_one
= false;
1144 for (unsigned i
= 0; i
< 3; i
++)
1146 if (instr
->operands
[i
].constantEquals(0))
1148 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1153 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1154 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1158 case aco_opcode::v_cndmask_b32
:
1159 if (instr
->operands
[0].constantEquals(0) &&
1160 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1161 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1162 else if (instr
->operands
[0].constantEquals(0) &&
1163 instr
->operands
[1].constantEquals(0x3f800000u
))
1164 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1165 else if (instr
->operands
[0].constantEquals(0) &&
1166 instr
->operands
[1].constantEquals(1))
1167 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1169 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1171 case aco_opcode::v_cmp_lg_u32
:
1172 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1173 instr
->operands
[0].constantEquals(0) &&
1174 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1175 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1177 case aco_opcode::p_phi
:
1178 case aco_opcode::p_linear_phi
: {
1179 /* lower_bool_phis() can create phis like this */
1180 bool all_same_temp
= instr
->operands
[0].isTemp();
1181 /* this check is needed when moving uniform loop counters out of a divergent loop */
1183 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1184 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1185 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1186 all_same_temp
= false;
1188 if (all_same_temp
) {
1189 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1191 bool all_undef
= instr
->operands
[0].isUndefined();
1192 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1193 if (!instr
->operands
[i
].isUndefined())
1197 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1201 case aco_opcode::v_add_u32
:
1202 case aco_opcode::v_add_co_u32
:
1203 case aco_opcode::v_add_co_u32_e64
:
1204 case aco_opcode::s_add_i32
:
1205 case aco_opcode::s_add_u32
:
1206 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1208 case aco_opcode::s_not_b32
:
1209 case aco_opcode::s_not_b64
:
1210 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1211 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1212 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1213 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1214 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1215 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1217 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1219 case aco_opcode::s_and_b32
:
1220 case aco_opcode::s_and_b64
:
1221 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1222 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1223 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1224 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1225 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1227 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1228 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1229 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1230 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1235 case aco_opcode::s_or_b32
:
1236 case aco_opcode::s_or_b64
:
1237 case aco_opcode::s_xor_b32
:
1238 case aco_opcode::s_xor_b64
:
1239 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1240 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1242 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1245 case aco_opcode::s_lshl_b32
:
1246 case aco_opcode::v_or_b32
:
1247 case aco_opcode::v_lshlrev_b32
:
1248 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1250 case aco_opcode::v_min_f32
:
1251 case aco_opcode::v_min_f16
:
1252 case aco_opcode::v_min_u32
:
1253 case aco_opcode::v_min_i32
:
1254 case aco_opcode::v_min_u16
:
1255 case aco_opcode::v_min_i16
:
1256 case aco_opcode::v_max_f32
:
1257 case aco_opcode::v_max_f16
:
1258 case aco_opcode::v_max_u32
:
1259 case aco_opcode::v_max_i32
:
1260 case aco_opcode::v_max_u16
:
1261 case aco_opcode::v_max_i16
:
1262 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1264 case aco_opcode::v_cmp_lt_f32
:
1265 case aco_opcode::v_cmp_eq_f32
:
1266 case aco_opcode::v_cmp_le_f32
:
1267 case aco_opcode::v_cmp_gt_f32
:
1268 case aco_opcode::v_cmp_lg_f32
:
1269 case aco_opcode::v_cmp_ge_f32
:
1270 case aco_opcode::v_cmp_o_f32
:
1271 case aco_opcode::v_cmp_u_f32
:
1272 case aco_opcode::v_cmp_nge_f32
:
1273 case aco_opcode::v_cmp_nlg_f32
:
1274 case aco_opcode::v_cmp_ngt_f32
:
1275 case aco_opcode::v_cmp_nle_f32
:
1276 case aco_opcode::v_cmp_neq_f32
:
1277 case aco_opcode::v_cmp_nlt_f32
:
1278 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1280 case aco_opcode::s_cselect_b64
:
1281 case aco_opcode::s_cselect_b32
:
1282 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1283 instr
->operands
[1].constantEquals(0)) {
1284 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1285 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1287 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1288 /* Flip the operands to get rid of the scc_invert instruction */
1289 std::swap(instr
->operands
[0], instr
->operands
[1]);
1290 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1293 case aco_opcode::p_wqm
:
1294 if (instr
->operands
[0].isTemp() &&
1295 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1296 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1304 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1306 *ordered
= *unordered
= op
;
1308 #define CMP(ord, unord) \
1309 case aco_opcode::v_cmp_##ord##_f32:\
1310 case aco_opcode::v_cmp_n##unord##_f32:\
1311 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1312 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1313 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1327 aco_opcode
get_ordered(aco_opcode op
)
1329 aco_opcode ordered
, unordered
, inverse
;
1330 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::num_opcodes
;
1333 aco_opcode
get_unordered(aco_opcode op
)
1335 aco_opcode ordered
, unordered
, inverse
;
1336 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::num_opcodes
;
1339 aco_opcode
get_inverse(aco_opcode op
)
1341 aco_opcode ordered
, unordered
, inverse
;
1342 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::num_opcodes
;
1345 bool is_cmp(aco_opcode op
)
1347 aco_opcode ordered
, unordered
, inverse
;
1348 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1351 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1353 if (ctx
.info
[tmp
.id()].is_temp())
1354 return ctx
.info
[tmp
.id()].temp
.id();
1359 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1361 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1362 for (const Operand
& op
: instr
->operands
) {
1364 ctx
.uses
[op
.tempId()]--;
1369 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1371 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1373 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1376 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1378 if (instr
->definitions
.size() == 2) {
1379 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1380 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1387 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1388 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1389 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1391 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1393 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1396 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1398 bool neg
[2] = {false, false};
1399 bool abs
[2] = {false, false};
1401 Instruction
*op_instr
[2];
1404 for (unsigned i
= 0; i
< 2; i
++) {
1405 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1409 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1411 if (op_instr
[i
]->opcode
!= expected_cmp
)
1413 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1416 if (op_instr
[i
]->isVOP3()) {
1417 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1418 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1420 neg
[i
] = vop3
->neg
[0];
1421 abs
[i
] = vop3
->abs
[0];
1422 opsel
|= (vop3
->opsel
& 1) << i
;
1425 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1426 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1427 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1433 if (op
[1].type() == RegType::sgpr
)
1434 std::swap(op
[0], op
[1]);
1435 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1436 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1439 ctx
.uses
[op
[0].id()]++;
1440 ctx
.uses
[op
[1].id()]++;
1441 decrease_uses(ctx
, op_instr
[0]);
1442 decrease_uses(ctx
, op_instr
[1]);
1444 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1445 Instruction
*new_instr
;
1446 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1447 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1448 for (unsigned i
= 0; i
< 2; i
++) {
1449 vop3
->neg
[i
] = neg
[i
];
1450 vop3
->abs
[i
] = abs
[i
];
1452 vop3
->opsel
= opsel
;
1453 new_instr
= static_cast<Instruction
*>(vop3
);
1455 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1457 new_instr
->operands
[0] = Operand(op
[0]);
1458 new_instr
->operands
[1] = Operand(op
[1]);
1459 new_instr
->definitions
[0] = instr
->definitions
[0];
1461 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1462 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1464 instr
.reset(new_instr
);
1469 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1470 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1471 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1473 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1475 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1478 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1479 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1481 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1482 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1483 if (!nan_test
|| !cmp
)
1486 if (cmp
->opcode
== expected_nan_test
)
1487 std::swap(nan_test
, cmp
);
1488 else if (nan_test
->opcode
!= expected_nan_test
)
1491 if (!is_cmp(cmp
->opcode
))
1494 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1496 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1499 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1500 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1501 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1502 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1503 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1505 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1508 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1509 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1510 decrease_uses(ctx
, nan_test
);
1511 decrease_uses(ctx
, cmp
);
1513 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1514 Instruction
*new_instr
;
1515 if (cmp
->isVOP3()) {
1516 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1517 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1518 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1519 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1520 new_vop3
->clamp
= cmp_vop3
->clamp
;
1521 new_vop3
->omod
= cmp_vop3
->omod
;
1522 new_vop3
->opsel
= cmp_vop3
->opsel
;
1523 new_instr
= new_vop3
;
1525 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1527 new_instr
->operands
[0] = cmp
->operands
[0];
1528 new_instr
->operands
[1] = cmp
->operands
[1];
1529 new_instr
->definitions
[0] = instr
->definitions
[0];
1531 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1532 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1534 instr
.reset(new_instr
);
1539 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1540 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1541 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1543 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1545 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1548 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1550 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1551 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1553 if (!nan_test
|| !cmp
)
1556 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1557 if (cmp
->opcode
== expected_nan_test
)
1558 std::swap(nan_test
, cmp
);
1559 else if (nan_test
->opcode
!= expected_nan_test
)
1562 if (!is_cmp(cmp
->opcode
))
1565 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1567 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1570 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1571 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1572 if (prop_nan0
!= prop_nan1
)
1575 if (nan_test
->isVOP3()) {
1576 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1577 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1581 int constant_operand
= -1;
1582 for (unsigned i
= 0; i
< 2; i
++) {
1583 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1584 constant_operand
= !i
;
1588 if (constant_operand
== -1)
1592 if (cmp
->operands
[constant_operand
].isConstant()) {
1593 constant
= cmp
->operands
[constant_operand
].constantValue();
1594 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1595 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1596 unsigned id
= original_temp_id(ctx
, tmp
);
1597 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1599 constant
= ctx
.info
[id
].val
;
1605 memcpy(&constantf
, &constant
, 4);
1606 if (isnan(constantf
))
1609 if (cmp
->operands
[0].isTemp())
1610 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1611 if (cmp
->operands
[1].isTemp())
1612 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1613 decrease_uses(ctx
, nan_test
);
1614 decrease_uses(ctx
, cmp
);
1616 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1617 Instruction
*new_instr
;
1618 if (cmp
->isVOP3()) {
1619 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1620 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1621 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1622 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1623 new_vop3
->clamp
= cmp_vop3
->clamp
;
1624 new_vop3
->omod
= cmp_vop3
->omod
;
1625 new_vop3
->opsel
= cmp_vop3
->opsel
;
1626 new_instr
= new_vop3
;
1628 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1630 new_instr
->operands
[0] = cmp
->operands
[0];
1631 new_instr
->operands
[1] = cmp
->operands
[1];
1632 new_instr
->definitions
[0] = instr
->definitions
[0];
1634 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1635 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1637 instr
.reset(new_instr
);
1642 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1643 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1645 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1647 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1649 if (!instr
->operands
[0].isTemp())
1652 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1656 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1657 if (new_opcode
== aco_opcode::num_opcodes
)
1660 if (cmp
->operands
[0].isTemp())
1661 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1662 if (cmp
->operands
[1].isTemp())
1663 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1664 decrease_uses(ctx
, cmp
);
1666 Instruction
*new_instr
;
1667 if (cmp
->isVOP3()) {
1668 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1669 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1670 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1671 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1672 new_vop3
->clamp
= cmp_vop3
->clamp
;
1673 new_vop3
->omod
= cmp_vop3
->omod
;
1674 new_vop3
->opsel
= cmp_vop3
->opsel
;
1675 new_instr
= new_vop3
;
1677 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1679 new_instr
->operands
[0] = cmp
->operands
[0];
1680 new_instr
->operands
[1] = cmp
->operands
[1];
1681 new_instr
->definitions
[0] = instr
->definitions
[0];
1683 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1684 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1686 instr
.reset(new_instr
);
1691 /* op1(op2(1, 2), 0) if swap = false
1692 * op1(0, op2(1, 2)) if swap = true */
1693 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1694 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1695 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1696 bool *op1_clamp
, uint8_t *op1_omod
,
1697 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1700 if (op1_instr
->opcode
!= op1
)
1703 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1704 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1706 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1709 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1710 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1712 /* don't support inbetween clamp/omod */
1713 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1716 /* get operands and modifiers and check inbetween modifiers */
1717 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1718 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1721 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1722 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1726 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1727 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1730 if (inbetween_opsel
)
1731 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1732 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1736 shuffle
[shuffle_str
[0] - '0'] = 0;
1737 shuffle
[shuffle_str
[1] - '0'] = 1;
1738 shuffle
[shuffle_str
[2] - '0'] = 2;
1740 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1741 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1742 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1743 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1744 *opsel
|= 1 << shuffle
[0];
1746 for (unsigned i
= 0; i
< 2; i
++) {
1747 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1748 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1749 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1750 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1751 *opsel
|= 1 << shuffle
[i
+ 1];
1754 /* check operands */
1755 if (!check_vop3_operands(ctx
, 3, operands
))
1761 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1762 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1763 bool clamp
, unsigned omod
)
1765 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1766 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1767 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1768 new_instr
->clamp
= clamp
;
1769 new_instr
->omod
= omod
;
1770 new_instr
->opsel
= opsel
;
1771 new_instr
->operands
[0] = operands
[0];
1772 new_instr
->operands
[1] = operands
[1];
1773 new_instr
->operands
[2] = operands
[2];
1774 new_instr
->definitions
[0] = instr
->definitions
[0];
1775 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1777 instr
.reset(new_instr
);
1780 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1782 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1783 (label_omod_success
| label_clamp_success
);
1785 for (unsigned swap
= 0; swap
< 2; swap
++) {
1786 if (!((1 << swap
) & ops
))
1789 Operand operands
[3];
1790 bool neg
[3], abs
[3], clamp
;
1791 uint8_t opsel
= 0, omod
= 0;
1792 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1793 instr
.get(), swap
, shuffle
,
1794 operands
, neg
, abs
, &opsel
,
1795 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1796 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1797 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1798 if (omod_clamp
& label_omod_success
)
1799 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1800 if (omod_clamp
& label_clamp_success
)
1801 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1808 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1810 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1813 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1814 (label_omod_success
| label_clamp_success
);
1816 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1817 * max(-min(a, b), c) -> max3(-a, -b, c) */
1818 for (unsigned swap
= 0; swap
< 2; swap
++) {
1819 Operand operands
[3];
1820 bool neg
[3], abs
[3], clamp
;
1821 uint8_t opsel
= 0, omod
= 0;
1823 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1824 instr
.get(), swap
, "012",
1825 operands
, neg
, abs
, &opsel
,
1826 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1828 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1831 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1832 if (omod_clamp
& label_omod_success
)
1833 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1834 if (omod_clamp
& label_clamp_success
)
1835 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1842 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1843 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1844 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1845 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1846 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1847 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1848 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1851 if (!instr
->operands
[0].isTemp())
1853 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1856 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1859 switch (op2_instr
->opcode
) {
1860 case aco_opcode::s_and_b32
:
1861 case aco_opcode::s_or_b32
:
1862 case aco_opcode::s_xor_b32
:
1863 case aco_opcode::s_and_b64
:
1864 case aco_opcode::s_or_b64
:
1865 case aco_opcode::s_xor_b64
:
1871 /* create instruction */
1872 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1873 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1874 ctx
.uses
[instr
->operands
[0].tempId()]--;
1875 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1877 switch (op2_instr
->opcode
) {
1878 case aco_opcode::s_and_b32
:
1879 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1881 case aco_opcode::s_or_b32
:
1882 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1884 case aco_opcode::s_xor_b32
:
1885 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1887 case aco_opcode::s_and_b64
:
1888 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1890 case aco_opcode::s_or_b64
:
1891 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1893 case aco_opcode::s_xor_b64
:
1894 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1903 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1904 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1905 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1906 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1907 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1909 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1912 for (unsigned i
= 0; i
< 2; i
++) {
1913 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1914 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1916 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
1919 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1920 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1923 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1924 instr
->operands
[0] = instr
->operands
[!i
];
1925 instr
->operands
[1] = op2_instr
->operands
[0];
1926 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1928 switch (instr
->opcode
) {
1929 case aco_opcode::s_and_b32
:
1930 instr
->opcode
= aco_opcode::s_andn2_b32
;
1932 case aco_opcode::s_or_b32
:
1933 instr
->opcode
= aco_opcode::s_orn2_b32
;
1935 case aco_opcode::s_and_b64
:
1936 instr
->opcode
= aco_opcode::s_andn2_b64
;
1938 case aco_opcode::s_or_b64
:
1939 instr
->opcode
= aco_opcode::s_orn2_b64
;
1950 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1951 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1953 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
1956 for (unsigned i
= 0; i
< 2; i
++) {
1957 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1958 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
1959 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
1961 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
1964 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1965 if (shift
< 1 || shift
> 4)
1968 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1969 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1972 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1973 instr
->operands
[1] = instr
->operands
[!i
];
1974 instr
->operands
[0] = op2_instr
->operands
[0];
1975 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1977 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1978 aco_opcode::s_lshl2_add_u32
,
1979 aco_opcode::s_lshl3_add_u32
,
1980 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1987 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
1989 if (instr
->usesModifiers())
1992 for (unsigned i
= 0; i
< 2; i
++) {
1993 if (!((1 << i
) & ops
))
1995 if (instr
->operands
[i
].isTemp() &&
1996 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
1997 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
1999 aco_ptr
<Instruction
> new_instr
;
2000 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2001 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2002 } else if (ctx
.program
->chip_class
>= GFX10
||
2003 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2004 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2008 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2009 new_instr
->definitions
[0] = instr
->definitions
[0];
2010 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2011 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2012 new_instr
->definitions
[1].setHint(vcc
);
2013 new_instr
->operands
[0] = Operand(0u);
2014 new_instr
->operands
[1] = instr
->operands
[!i
];
2015 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2016 instr
= std::move(new_instr
);
2017 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2025 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2028 #define MINMAX(type, gfx9) \
2029 case aco_opcode::v_min_##type:\
2030 case aco_opcode::v_max_##type:\
2031 case aco_opcode::v_med3_##type:\
2032 *min = aco_opcode::v_min_##type;\
2033 *max = aco_opcode::v_max_##type;\
2034 *med3 = aco_opcode::v_med3_##type;\
2035 *min3 = aco_opcode::v_min3_##type;\
2036 *max3 = aco_opcode::v_max3_##type;\
2037 *some_gfx9_only = gfx9;\
2051 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2052 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2053 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2054 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2056 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2057 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2058 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2059 aco_opcode other_op
;
2060 if (instr
->opcode
== min
)
2062 else if (instr
->opcode
== max
)
2067 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2068 (label_omod_success
| label_clamp_success
);
2070 for (unsigned swap
= 0; swap
< 2; swap
++) {
2071 Operand operands
[3];
2072 bool neg
[3], abs
[3], clamp
;
2073 uint8_t opsel
= 0, omod
= 0;
2074 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2075 "012", operands
, neg
, abs
, &opsel
,
2076 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2077 int const0_idx
= -1, const1_idx
= -1;
2078 uint32_t const0
= 0, const1
= 0;
2079 for (int i
= 0; i
< 3; i
++) {
2081 if (operands
[i
].isConstant()) {
2082 val
= operands
[i
].constantValue();
2083 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
2084 val
= ctx
.info
[operands
[i
].tempId()].val
;
2088 if (const0_idx
>= 0) {
2096 if (const0_idx
< 0 || const1_idx
< 0)
2099 if (opsel
& (1 << const0_idx
))
2101 if (opsel
& (1 << const1_idx
))
2104 int lower_idx
= const0_idx
;
2106 case aco_opcode::v_min_f32
:
2107 case aco_opcode::v_min_f16
: {
2108 float const0_f
, const1_f
;
2109 if (min
== aco_opcode::v_min_f32
) {
2110 memcpy(&const0_f
, &const0
, 4);
2111 memcpy(&const1_f
, &const1
, 4);
2113 const0_f
= _mesa_half_to_float(const0
);
2114 const1_f
= _mesa_half_to_float(const1
);
2116 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2117 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2118 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2119 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2120 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2123 case aco_opcode::v_min_u32
: {
2124 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2127 case aco_opcode::v_min_u16
: {
2128 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2131 case aco_opcode::v_min_i32
: {
2132 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2133 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2134 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2137 case aco_opcode::v_min_i16
: {
2138 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2139 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2140 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2146 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2148 if (instr
->opcode
== min
) {
2149 if (upper_idx
!= 0 || lower_idx
== 0)
2152 if (upper_idx
== 0 || lower_idx
!= 0)
2156 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2157 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2158 if (omod_clamp
& label_omod_success
)
2159 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2160 if (omod_clamp
& label_clamp_success
)
2161 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2171 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2173 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2174 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2175 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2177 /* find candidates and create the set of sgprs already read */
2178 unsigned sgpr_ids
[2] = {0, 0};
2179 uint32_t operand_mask
= 0;
2180 bool has_literal
= false;
2181 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2182 if (instr
->operands
[i
].isLiteral())
2184 if (!instr
->operands
[i
].isTemp())
2186 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2187 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2188 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2190 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2191 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2192 operand_mask
|= 1u << i
;
2194 unsigned max_sgprs
= 1;
2195 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2200 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2202 /* keep on applying sgprs until there is nothing left to be done */
2203 while (operand_mask
) {
2204 uint32_t sgpr_idx
= 0;
2205 uint32_t sgpr_info_id
= 0;
2206 uint32_t mask
= operand_mask
;
2209 unsigned i
= u_bit_scan(&mask
);
2210 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2211 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2213 sgpr_info_id
= instr
->operands
[i
].tempId();
2216 operand_mask
&= ~(1u << sgpr_idx
);
2218 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2219 * definitively beneficial.
2220 * TODO: this is too conservative because later the use count could be reduced to 1 */
2221 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2224 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2225 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2226 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2229 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2230 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2231 } else if (can_swap_operands(instr
)) {
2232 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2233 instr
->operands
[0] = Operand(sgpr
);
2234 /* swap bits using a 4-entry LUT */
2235 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2236 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2237 } else if (can_use_VOP3(ctx
, instr
)) {
2238 to_VOP3(ctx
, instr
);
2239 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2245 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2246 ctx
.uses
[sgpr_info_id
]--;
2247 ctx
.uses
[sgpr
.id()]++;
2251 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2253 /* check if we could apply omod on predecessor */
2254 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2255 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2256 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2258 unsigned idx
= op0
? 0 : 1;
2259 /* omod was successfully applied */
2260 /* if the omod instruction is v_mad, we also have to change the original add */
2261 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2262 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2263 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2264 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2265 add_instr
->definitions
[0] = instr
->definitions
[0];
2268 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2269 /* check if we have an additional clamp modifier */
2270 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2271 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2272 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2273 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2275 /* change definition ssa-id of modified instruction */
2276 omod_instr
->definitions
[0] = instr
->definitions
[0];
2278 /* change the definition of instr to something unused, e.g. the original omod def */
2279 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2280 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2283 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2284 /* in all other cases, label this instruction as option for multiply-add */
2285 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2289 /* check if we could apply clamp on predecessor */
2290 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2292 bool found_zero
= false, found_one
= false;
2293 for (unsigned i
= 0; i
< 3; i
++)
2295 if (instr
->operands
[i
].constantEquals(0))
2297 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2302 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2303 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2304 /* clamp was successfully applied */
2305 /* if the clamp instruction is v_mad, we also have to change the original add */
2306 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2307 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2308 add_instr
->definitions
[0] = instr
->definitions
[0];
2310 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2311 /* change definition ssa-id of modified instruction */
2312 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2314 /* change the definition of instr to something unused, e.g. the original omod def */
2315 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2316 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2321 /* omod has no effect if denormals are enabled */
2322 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2324 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2325 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2326 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2327 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2328 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2329 to_VOP3(ctx
, instr
);
2330 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2331 def_info
.set_omod_success(instr
.get());
2332 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2333 to_VOP3(ctx
, instr
);
2334 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2335 def_info
.set_omod_success(instr
.get());
2336 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2337 to_VOP3(ctx
, instr
);
2338 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2339 def_info
.set_omod_success(instr
.get());
2340 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2341 to_VOP3(ctx
, instr
);
2342 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2343 def_info
.set_clamp_success(instr
.get());
2350 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2351 // this would mean that we'd have to fix the instruction uses while value propagation
2353 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2355 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2358 if (instr
->isVALU()) {
2359 if (can_apply_sgprs(instr
))
2360 apply_sgprs(ctx
, instr
);
2361 if (apply_omod_clamp(ctx
, block
, instr
))
2365 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2366 instr
->definitions
[0].setHint(vcc
);
2369 /* TODO: There are still some peephole optimizations that could be done:
2370 * - abs(a - b) -> s_absdiff_i32
2371 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2372 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2373 * These aren't probably too interesting though.
2374 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2375 * probably more useful than the previously mentioned optimizations.
2376 * The various comparison optimizations also currently only work with 32-bit
2379 /* neg(mul(a, b)) -> mul(neg(a), b) */
2380 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2381 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2383 if (!ctx
.info
[val
.id()].is_mul())
2386 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2388 if (mul_instr
->operands
[0].isLiteral())
2390 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2393 /* convert to mul(neg(a), b) */
2394 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2395 Definition def
= instr
->definitions
[0];
2396 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2397 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2398 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2399 instr
->operands
[0] = mul_instr
->operands
[0];
2400 instr
->operands
[1] = mul_instr
->operands
[1];
2401 instr
->definitions
[0] = def
;
2402 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2403 if (mul_instr
->isVOP3()) {
2404 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2405 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2406 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2407 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2408 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2409 new_mul
->omod
= mul
->omod
;
2411 new_mul
->neg
[0] ^= true;
2412 new_mul
->clamp
= false;
2414 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2418 /* combine mul+add -> mad */
2419 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2420 instr
->opcode
== aco_opcode::v_sub_f32
||
2421 instr
->opcode
== aco_opcode::v_subrev_f32
;
2422 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2423 instr
->opcode
== aco_opcode::v_sub_f16
||
2424 instr
->opcode
== aco_opcode::v_subrev_f16
;
2425 if (mad16
|| mad32
) {
2426 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2427 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2428 if (need_fma
&& instr
->definitions
[0].isPrecise())
2430 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2433 uint32_t uses_src0
= UINT32_MAX
;
2434 uint32_t uses_src1
= UINT32_MAX
;
2435 Instruction
* mul_instr
= nullptr;
2436 unsigned add_op_idx
;
2437 /* check if any of the operands is a multiplication */
2438 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2439 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2440 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2441 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2442 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2443 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2445 /* find the 'best' mul instruction to combine with the add */
2446 if (uses_src0
< uses_src1
) {
2447 mul_instr
= op0_info
->instr
;
2449 } else if (uses_src1
< uses_src0
) {
2450 mul_instr
= op1_info
->instr
;
2452 } else if (uses_src0
!= UINT32_MAX
) {
2453 /* tiebreaker: quite random what to pick */
2454 if (op0_info
->instr
->operands
[0].isLiteral()) {
2455 mul_instr
= op1_info
->instr
;
2458 mul_instr
= op0_info
->instr
;
2463 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2464 bool neg
[3] = {false, false, false};
2465 bool abs
[3] = {false, false, false};
2468 op
[0] = mul_instr
->operands
[0];
2469 op
[1] = mul_instr
->operands
[1];
2470 op
[2] = instr
->operands
[add_op_idx
];
2471 // TODO: would be better to check this before selecting a mul instr?
2472 if (!check_vop3_operands(ctx
, 3, op
))
2475 if (mul_instr
->isVOP3()) {
2476 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2477 neg
[0] = vop3
->neg
[0];
2478 neg
[1] = vop3
->neg
[1];
2479 abs
[0] = vop3
->abs
[0];
2480 abs
[1] = vop3
->abs
[1];
2481 /* we cannot use these modifiers between mul and add */
2482 if (vop3
->clamp
|| vop3
->omod
)
2486 /* convert to mad */
2487 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2488 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2490 ctx
.uses
[op
[0].tempId()]++;
2492 ctx
.uses
[op
[1].tempId()]++;
2495 if (instr
->isVOP3()) {
2496 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2497 neg
[2] = vop3
->neg
[add_op_idx
];
2498 abs
[2] = vop3
->abs
[add_op_idx
];
2500 clamp
= vop3
->clamp
;
2501 /* abs of the multiplication result */
2502 if (vop3
->abs
[1 - add_op_idx
]) {
2508 /* neg of the multiplication result */
2509 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2511 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2512 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2513 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2514 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2516 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2518 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2519 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2521 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2522 for (unsigned i
= 0; i
< 3; i
++)
2524 mad
->operands
[i
] = op
[i
];
2525 mad
->neg
[i
] = neg
[i
];
2526 mad
->abs
[i
] = abs
[i
];
2530 mad
->definitions
[0] = instr
->definitions
[0];
2532 /* mark this ssa_def to be re-checked for profitability and literals */
2533 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2534 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2535 instr
.reset(mad
.release());
2539 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2540 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2541 for (unsigned i
= 0; i
< 2; i
++) {
2542 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2543 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2544 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2545 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2546 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2548 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2549 new_instr
->operands
[0] = Operand(0u);
2550 new_instr
->operands
[1] = instr
->operands
[!i
];
2551 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2552 new_instr
->definitions
[0] = instr
->definitions
[0];
2553 instr
.reset(new_instr
.release());
2554 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2558 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2559 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2560 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2561 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2562 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2563 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2564 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2565 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2566 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2567 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2568 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2569 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2570 else if (ctx
.program
->chip_class
>= GFX9
) {
2571 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2572 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2573 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2574 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2575 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2576 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2577 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2579 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2580 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2581 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2582 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2583 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2584 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2585 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2586 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2587 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2588 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2589 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2590 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2591 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2592 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2593 combine_salu_lshl_add(ctx
, instr
);
2594 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2595 combine_salu_not_bitwise(ctx
, instr
);
2596 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2597 if (combine_inverse_comparison(ctx
, instr
)) ;
2598 else combine_salu_not_bitwise(ctx
, instr
);
2599 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2600 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2601 if (combine_ordering_test(ctx
, instr
)) ;
2602 else if (combine_comparison_ordering(ctx
, instr
)) ;
2603 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2604 else combine_salu_n2(ctx
, instr
);
2606 aco_opcode min
, max
, min3
, max3
, med3
;
2607 bool some_gfx9_only
;
2608 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2609 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2610 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2611 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2616 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2618 switch (instr
->opcode
) {
2619 case aco_opcode::s_and_b32
:
2620 case aco_opcode::s_and_b64
:
2621 instr
->opcode
= aco_opcode::s_and_b32
;
2623 case aco_opcode::s_or_b32
:
2624 case aco_opcode::s_or_b64
:
2625 instr
->opcode
= aco_opcode::s_or_b32
;
2627 case aco_opcode::s_xor_b32
:
2628 case aco_opcode::s_xor_b64
:
2629 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2632 /* Don't transform other instructions. They are very unlikely to appear here. */
2636 for (Operand
&op
: instr
->operands
) {
2637 ctx
.uses
[op
.tempId()]--;
2639 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2640 /* Just use the uniform boolean temp. */
2641 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2642 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2643 /* Use the SCC definition of the predecessor instruction.
2644 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2645 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2647 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2648 assert(pred_instr
->definitions
.size() >= 2);
2649 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2650 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2652 unreachable("Invalid operand on uniform bitwise instruction.");
2655 ctx
.uses
[op
.tempId()]++;
2658 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2659 assert(instr
->operands
[0].regClass() == s1
);
2660 assert(instr
->operands
[1].regClass() == s1
);
2664 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2666 const uint32_t threshold
= 4;
2668 if (is_dead(ctx
.uses
, instr
.get())) {
2673 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2674 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2675 unsigned num_used
= 0;
2677 unsigned split_offset
= 0;
2678 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2679 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2682 split_offset
= offset
;
2686 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2687 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2688 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2692 for (Operand
& vec_op
: vec
->operands
) {
2693 if (off
== split_offset
) {
2697 off
+= vec_op
.bytes();
2699 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2700 ctx
.uses
[instr
->operands
[0].tempId()]--;
2701 for (Operand
& vec_op
: vec
->operands
) {
2702 if (vec_op
.isTemp())
2703 ctx
.uses
[vec_op
.tempId()]--;
2706 ctx
.uses
[op
.tempId()]++;
2708 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2709 extract
->operands
[0] = op
;
2710 extract
->definitions
[0] = instr
->definitions
[idx
];
2711 instr
.reset(extract
.release());
2717 if (!done
&& num_used
== 1 &&
2718 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2719 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2720 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2721 extract
->operands
[0] = instr
->operands
[0];
2722 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2723 extract
->definitions
[0] = instr
->definitions
[idx
];
2724 instr
.reset(extract
.release());
2728 mad_info
* mad_info
= NULL
;
2729 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2730 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2731 /* re-check mad instructions */
2732 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2733 ctx
.uses
[mad_info
->mul_temp_id
]++;
2734 if (instr
->operands
[0].isTemp())
2735 ctx
.uses
[instr
->operands
[0].tempId()]--;
2736 if (instr
->operands
[1].isTemp())
2737 ctx
.uses
[instr
->operands
[1].tempId()]--;
2738 instr
.swap(mad_info
->add_instr
);
2741 /* check literals */
2742 else if (!instr
->usesModifiers()) {
2743 /* FMA can only take literals on GFX10+ */
2744 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2745 ctx
.program
->chip_class
< GFX10
)
2748 bool sgpr_used
= false;
2749 uint32_t literal_idx
= 0;
2750 uint32_t literal_uses
= UINT32_MAX
;
2751 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2753 if (instr
->operands
[i
].isConstant() && i
> 0) {
2754 literal_uses
= UINT32_MAX
;
2757 if (!instr
->operands
[i
].isTemp())
2759 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2760 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2761 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2762 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2765 literal_uses
= UINT32_MAX
;
2768 /* don't break because we still need to check constants */
2769 } else if (!sgpr_used
&&
2770 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2771 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2772 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2777 /* Limit the number of literals to apply to not increase the code
2778 * size too much, but always apply literals for v_mad->v_madak
2779 * because both instructions are 64-bit and this doesn't increase
2781 * TODO: try to apply the literals earlier to lower the number of
2782 * uses below threshold
2784 if (literal_uses
< threshold
|| literal_idx
== 2) {
2785 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2786 mad_info
->check_literal
= true;
2787 mad_info
->literal_idx
= literal_idx
;
2793 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2794 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2795 instr
->operands
.size() &&
2796 instr
->operands
[0].isTemp()) {
2797 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2799 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2800 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2801 instr
->operands
[2].isTemp()) {
2802 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2805 /* check for literals */
2806 if (!instr
->isSALU() && !instr
->isVALU())
2809 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2810 if (instr
->definitions
.size() &&
2811 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2812 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2813 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2815 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2816 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2817 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2818 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2819 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2820 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2826 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2827 return; /* some encodings can't ever take literals */
2829 /* we do not apply the literals yet as we don't know if it is profitable */
2830 Operand
current_literal(s1
);
2832 unsigned literal_id
= 0;
2833 unsigned literal_uses
= UINT32_MAX
;
2834 Operand
literal(s1
);
2835 unsigned num_operands
= 1;
2836 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2837 num_operands
= instr
->operands
.size();
2838 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2839 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2842 unsigned sgpr_ids
[2] = {0, 0};
2843 bool is_literal_sgpr
= false;
2846 /* choose a literal to apply */
2847 for (unsigned i
= 0; i
< num_operands
; i
++) {
2848 Operand op
= instr
->operands
[i
];
2850 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2851 op
.tempId() != sgpr_ids
[0])
2852 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2854 if (op
.isLiteral()) {
2855 current_literal
= op
;
2857 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2861 if (!alu_can_accept_constant(instr
->opcode
, i
))
2864 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2865 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2867 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2868 literal_uses
= ctx
.uses
[op
.tempId()];
2869 literal_id
= op
.tempId();
2872 mask
|= (op
.tempId() == literal_id
) << i
;
2876 /* don't go over the constant bus limit */
2877 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2878 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2879 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2880 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2881 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2882 const_bus_limit
= 2;
2884 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2885 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2888 if (literal_id
&& literal_uses
< threshold
&&
2889 (current_literal
.isUndefined() ||
2890 (current_literal
.size() == literal
.size() &&
2891 current_literal
.constantValue() == literal
.constantValue()))) {
2892 /* mark the literal to be applied */
2894 unsigned i
= u_bit_scan(&mask
);
2895 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2896 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2902 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2904 /* Cleanup Dead Instructions */
2908 /* apply literals on MAD */
2909 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2910 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2911 if (info
->check_literal
&&
2912 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2913 aco_ptr
<Instruction
> new_mad
;
2915 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
2916 if (instr
->opcode
== aco_opcode::v_fma_f32
)
2917 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
2918 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
2919 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
2920 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
2921 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
2923 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
2924 if (info
->literal_idx
== 2) { /* add literal -> madak */
2925 new_mad
->operands
[0] = instr
->operands
[0];
2926 new_mad
->operands
[1] = instr
->operands
[1];
2927 } else { /* mul literal -> madmk */
2928 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2929 new_mad
->operands
[1] = instr
->operands
[2];
2931 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2932 new_mad
->definitions
[0] = instr
->definitions
[0];
2933 ctx
.instructions
.emplace_back(std::move(new_mad
));
2938 /* apply literals on other SALU/VALU */
2939 if (instr
->isSALU() || instr
->isVALU()) {
2940 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2941 Operand op
= instr
->operands
[i
];
2942 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2943 Operand
literal(ctx
.info
[op
.tempId()].val
);
2944 if (instr
->isVALU() && i
> 0)
2945 to_VOP3(ctx
, instr
);
2946 instr
->operands
[i
] = literal
;
2951 ctx
.instructions
.emplace_back(std::move(instr
));
2955 void optimize(Program
* program
)
2958 ctx
.program
= program
;
2959 std::vector
<ssa_info
> info(program
->peekAllocationId());
2960 ctx
.info
= info
.data();
2962 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2963 for (Block
& block
: program
->blocks
) {
2964 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2965 label_instruction(ctx
, block
, instr
);
2968 ctx
.uses
= dead_code_analysis(program
);
2970 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2971 for (Block
& block
: program
->blocks
) {
2972 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2973 combine_instruction(ctx
, block
, instr
);
2976 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2977 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2978 Block
* block
= &(*it
);
2979 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2980 select_instruction(ctx
, *it
);
2983 /* 4. Add literals to instructions */
2984 for (Block
& block
: program
->blocks
) {
2985 ctx
.instructions
.clear();
2986 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2987 apply_literals(ctx
, instr
);
2988 block
.instructions
.swap(ctx
.instructions
);