2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
85 label_uniform_bool
= 1 << 21,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
| label_omod2
| label_omod4
| label_omod5
| label_clamp
;
90 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_abs(Temp abs_temp
)
143 add_label(label_abs
);
149 return label
& label_abs
;
152 void set_neg(Temp neg_temp
)
154 add_label(label_neg
);
160 return label
& label_neg
;
163 void set_neg_abs(Temp neg_abs_temp
)
165 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
169 void set_mul(Instruction
* mul
)
171 add_label(label_mul
);
177 return label
& label_mul
;
180 void set_temp(Temp tmp
)
182 add_label(label_temp
);
188 return label
& label_temp
;
191 void set_literal(uint32_t lit
)
193 add_label(label_literal
);
199 return label
& label_literal
;
202 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
204 add_label(label_mad
);
211 return label
& label_mad
;
214 void set_omod2(Temp def
)
216 add_label(label_omod2
);
222 return label
& label_omod2
;
225 void set_omod4(Temp def
)
227 add_label(label_omod4
);
233 return label
& label_omod4
;
236 void set_omod5(Temp def
)
238 add_label(label_omod5
);
244 return label
& label_omod5
;
247 void set_omod_success(Instruction
* omod_instr
)
249 add_label(label_omod_success
);
253 bool is_omod_success()
255 return label
& label_omod_success
;
258 void set_clamp(Temp def
)
260 add_label(label_clamp
);
266 return label
& label_clamp
;
269 void set_clamp_success(Instruction
* clamp_instr
)
271 add_label(label_clamp_success
);
275 bool is_clamp_success()
277 return label
& label_clamp_success
;
282 add_label(label_undefined
);
287 return label
& label_undefined
;
290 void set_vcc(Temp vcc
)
292 add_label(label_vcc
);
298 return label
& label_vcc
;
301 bool is_constant_or_literal()
303 return is_constant() || is_literal();
306 void set_b2f(Temp val
)
308 add_label(label_b2f
);
314 return label
& label_b2f
;
317 void set_add_sub(Instruction
*add_sub_instr
)
319 add_label(label_add_sub
);
320 instr
= add_sub_instr
;
325 return label
& label_add_sub
;
328 void set_bitwise(Instruction
*bitwise_instr
)
330 add_label(label_bitwise
);
331 instr
= bitwise_instr
;
336 return label
& label_bitwise
;
339 void set_minmax(Instruction
*minmax_instr
)
341 add_label(label_minmax
);
342 instr
= minmax_instr
;
347 return label
& label_minmax
;
350 void set_fcmp(Instruction
*fcmp_instr
)
352 add_label(label_fcmp
);
358 return label
& label_fcmp
;
361 void set_uniform_bool(Temp uniform_bool
)
363 add_label(label_uniform_bool
);
367 bool is_uniform_bool()
369 return label
& label_uniform_bool
;
376 std::vector
<aco_ptr
<Instruction
>> instructions
;
378 std::pair
<uint32_t,Temp
> last_literal
;
379 std::vector
<mad_info
> mad_infos
;
380 std::vector
<uint16_t> uses
;
383 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
385 if (instr
->operands
[0].isConstant() ||
386 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
389 switch (instr
->opcode
) {
390 case aco_opcode::v_add_f32
:
391 case aco_opcode::v_mul_f32
:
392 case aco_opcode::v_or_b32
:
393 case aco_opcode::v_and_b32
:
394 case aco_opcode::v_xor_b32
:
395 case aco_opcode::v_max_f32
:
396 case aco_opcode::v_min_f32
:
397 case aco_opcode::v_cmp_eq_f32
:
398 case aco_opcode::v_cmp_lg_f32
:
400 case aco_opcode::v_sub_f32
:
401 instr
->opcode
= aco_opcode::v_subrev_f32
;
403 case aco_opcode::v_cmp_lt_f32
:
404 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
406 case aco_opcode::v_cmp_ge_f32
:
407 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
409 case aco_opcode::v_cmp_lt_i32
:
410 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
417 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
422 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
425 if (instr
->isDPP() || instr
->isSDWA())
428 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
429 instr
->opcode
!= aco_opcode::v_madak_f32
&&
430 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
431 instr
->opcode
!= aco_opcode::v_madak_f16
&&
432 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
433 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
434 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
435 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
436 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
437 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
438 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
441 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
443 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
444 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
445 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
446 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
447 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
450 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
455 aco_ptr
<Instruction
> tmp
= std::move(instr
);
456 Format format
= asVOP3(tmp
->format
);
457 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
458 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
459 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
460 instr
->definitions
[i
] = tmp
->definitions
[i
];
461 if (instr
->definitions
[i
].isTemp()) {
462 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
463 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
464 info
.instr
= instr
.get();
469 /* only covers special cases */
470 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
472 switch (instr
->opcode
) {
473 case aco_opcode::v_interp_p2_f32
:
474 case aco_opcode::v_mac_f32
:
475 case aco_opcode::v_writelane_b32
:
476 case aco_opcode::v_writelane_b32_e64
:
477 case aco_opcode::v_cndmask_b32
:
479 case aco_opcode::s_addk_i32
:
480 case aco_opcode::s_mulk_i32
:
481 case aco_opcode::p_wqm
:
482 case aco_opcode::p_extract_vector
:
483 case aco_opcode::p_split_vector
:
484 case aco_opcode::v_readlane_b32
:
485 case aco_opcode::v_readlane_b32_e64
:
486 case aco_opcode::v_readfirstlane_b32
:
489 if ((instr
->format
== Format::MUBUF
||
490 instr
->format
== Format::MIMG
) &&
491 instr
->definitions
.size() == 1 &&
492 instr
->operands
.size() == 4) {
499 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
501 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
502 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
507 /* check constant bus and literal limitations */
508 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
510 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
511 Operand
literal32(s1
);
512 Operand
literal64(s2
);
513 unsigned num_sgprs
= 0;
514 unsigned sgpr
[] = {0, 0};
516 for (unsigned i
= 0; i
< num_operands
; i
++) {
517 Operand op
= operands
[i
];
519 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
520 /* two reads of the same SGPR count as 1 to the limit */
521 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
523 sgpr
[num_sgprs
++] = op
.tempId();
528 } else if (op
.isLiteral()) {
529 if (ctx
.program
->chip_class
< GFX10
)
532 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
534 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
537 /* Any number of 32-bit literals counts as only 1 to the limit. Same
538 * (but separately) for 64-bit literals. */
539 if (op
.size() == 1 && literal32
.isUndefined()) {
542 } else if (op
.size() == 2 && literal64
.isUndefined()) {
555 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
557 Operand op
= instr
->operands
[op_index
];
561 Temp tmp
= op
.getTemp();
562 if (!ctx
.info
[tmp
.id()].is_add_sub())
565 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
567 switch (add_instr
->opcode
) {
568 case aco_opcode::v_add_u32
:
569 case aco_opcode::v_add_co_u32
:
570 case aco_opcode::s_add_i32
:
571 case aco_opcode::s_add_u32
:
577 if (add_instr
->usesModifiers())
580 for (unsigned i
= 0; i
< 2; i
++) {
581 if (add_instr
->operands
[i
].isConstant()) {
582 *offset
= add_instr
->operands
[i
].constantValue();
583 } else if (add_instr
->operands
[i
].isTemp() &&
584 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
585 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
589 if (!add_instr
->operands
[!i
].isTemp())
592 uint32_t offset2
= 0;
593 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
596 *base
= add_instr
->operands
[!i
].getTemp();
604 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
)
606 // TODO: this functions shouldn't be needed if we store Operand instead of value.
608 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
609 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
613 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
615 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
616 ASSERTED
bool all_const
= false;
617 for (Operand
& op
: instr
->operands
)
618 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
619 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
622 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
624 if (!instr
->operands
[i
].isTemp())
627 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
628 /* propagate undef */
629 if (info
.is_undefined() && is_phi(instr
))
630 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
631 /* propagate reg->reg of same type */
632 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
633 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
634 info
= ctx
.info
[info
.temp
.id()];
637 /* SALU / PSEUDO: propagate inline constants */
638 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
639 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
640 instr
->operands
[i
].setTemp(info
.temp
);
641 info
= ctx
.info
[info
.temp
.id()];
642 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
643 /* propagate vgpr if it can take it */
644 switch (instr
->opcode
) {
645 case aco_opcode::p_create_vector
:
646 case aco_opcode::p_split_vector
:
647 case aco_opcode::p_extract_vector
:
648 case aco_opcode::p_phi
: {
649 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
650 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
652 instr
->operands
[i
] = Operand(info
.temp
);
653 info
= ctx
.info
[info
.temp
.id()];
661 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
662 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
667 /* VALU: propagate neg, abs & inline constants */
668 else if (instr
->isVALU()) {
669 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
670 instr
->operands
[i
].setTemp(info
.temp
);
671 info
= ctx
.info
[info
.temp
.id()];
673 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
676 instr
->operands
[i
] = Operand(info
.temp
);
678 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
680 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
682 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
683 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
684 instr
->operands
[i
].setTemp(info
.temp
);
686 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
689 instr
->operands
[i
].setTemp(info
.temp
);
691 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
693 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
696 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
697 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
698 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
699 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
701 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
702 instr
->operands
[i
] = instr
->operands
[0];
703 instr
->operands
[0] = get_constant_op(ctx
, info
.val
);
705 } else if (can_use_VOP3(ctx
, instr
)) {
707 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
713 /* MUBUF: propagate constants and combine additions */
714 else if (instr
->format
== Format::MUBUF
) {
715 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
718 while (info
.is_temp())
719 info
= ctx
.info
[info
.temp
.id()];
721 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
722 assert(!mubuf
->idxen
);
723 instr
->operands
[i
] = Operand(v1
);
724 mubuf
->offset
+= info
.val
;
725 mubuf
->offen
= false;
727 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
728 instr
->operands
[2] = Operand((uint32_t) 0);
729 mubuf
->offset
+= info
.val
;
731 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
732 assert(!mubuf
->idxen
);
733 instr
->operands
[i
].setTemp(base
);
734 mubuf
->offset
+= offset
;
736 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
737 instr
->operands
[i
].setTemp(base
);
738 mubuf
->offset
+= offset
;
743 /* DS: combine additions */
744 else if (instr
->format
== Format::DS
) {
746 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
749 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
750 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
751 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
752 if (offset
% 4 == 0 &&
753 ds
->offset0
+ (offset
>> 2) <= 255 &&
754 ds
->offset1
+ (offset
>> 2) <= 255) {
755 instr
->operands
[i
].setTemp(base
);
756 ds
->offset0
+= offset
>> 2;
757 ds
->offset1
+= offset
>> 2;
760 if (ds
->offset0
+ offset
<= 65535) {
761 instr
->operands
[i
].setTemp(base
);
762 ds
->offset0
+= offset
;
768 /* SMEM: propagate constants and combine additions */
769 else if (instr
->format
== Format::SMEM
) {
771 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
774 if (i
== 1 && info
.is_constant_or_literal() &&
775 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
776 instr
->operands
[i
] = Operand(info
.val
);
778 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
779 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
781 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
782 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
786 smem
->operands
[1] = Operand(offset
);
787 smem
->operands
.back() = Operand(base
);
789 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
790 new_instr
->operands
[0] = smem
->operands
[0];
791 new_instr
->operands
[1] = Operand(offset
);
792 if (smem
->definitions
.empty())
793 new_instr
->operands
[2] = smem
->operands
[2];
794 new_instr
->operands
.back() = Operand(base
);
795 if (!smem
->definitions
.empty())
796 new_instr
->definitions
[0] = smem
->definitions
[0];
797 new_instr
->can_reorder
= smem
->can_reorder
;
798 new_instr
->barrier
= smem
->barrier
;
799 instr
.reset(new_instr
);
800 smem
= static_cast<SMEM_instruction
*>(instr
.get());
807 /* if this instruction doesn't define anything, return */
808 if (instr
->definitions
.empty())
811 switch (instr
->opcode
) {
812 case aco_opcode::p_create_vector
: {
813 unsigned num_ops
= instr
->operands
.size();
814 for (const Operand
& op
: instr
->operands
) {
815 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
816 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
818 if (num_ops
!= instr
->operands
.size()) {
819 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
820 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
821 instr
->definitions
[0] = old_vec
->definitions
[0];
823 for (Operand
& old_op
: old_vec
->operands
) {
824 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
825 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
826 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
827 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
828 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
829 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
830 instr
->operands
[k
++] = op
;
833 instr
->operands
[k
++] = old_op
;
836 assert(k
== num_ops
);
838 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
839 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
840 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
841 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
844 case aco_opcode::p_split_vector
: {
845 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
847 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
848 assert(instr
->definitions
.size() == vec
->operands
.size());
849 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
850 Operand vec_op
= vec
->operands
[i
];
851 if (vec_op
.isConstant()) {
852 if (vec_op
.isLiteral())
853 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
854 else if (vec_op
.size() == 1)
855 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
857 assert(vec_op
.isTemp());
858 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
863 case aco_opcode::p_extract_vector
: { /* mov */
864 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
866 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
867 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
868 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
870 /* convert this extract into a mov instruction */
871 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
872 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
873 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
874 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
875 instr
->opcode
= opcode
;
876 instr
->format
= format
;
877 while (instr
->operands
.size() > 1)
878 instr
->operands
.pop_back();
879 instr
->operands
[0] = vec_op
;
881 if (vec_op
.isConstant()) {
882 if (vec_op
.isLiteral())
883 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
884 else if (vec_op
.size() == 1)
885 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
887 assert(vec_op
.isTemp());
888 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
893 case aco_opcode::s_mov_b32
: /* propagate */
894 case aco_opcode::s_mov_b64
:
895 case aco_opcode::v_mov_b32
:
896 case aco_opcode::p_as_uniform
:
897 if (instr
->definitions
[0].isFixed()) {
898 /* don't copy-propagate copies into fixed registers */
899 } else if (instr
->usesModifiers()) {
901 } else if (instr
->operands
[0].isConstant()) {
902 if (instr
->operands
[0].isLiteral())
903 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
904 else if (instr
->operands
[0].size() == 1)
905 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
906 } else if (instr
->operands
[0].isTemp()) {
907 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
909 assert(instr
->operands
[0].isFixed());
912 case aco_opcode::p_is_helper
:
913 if (!ctx
.program
->needs_wqm
)
914 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
916 case aco_opcode::s_movk_i32
: {
917 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
918 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
919 if (v
<= 64 || v
>= 0xfffffff0)
920 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
922 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
925 case aco_opcode::v_bfrev_b32
:
926 case aco_opcode::s_brev_b32
: {
927 if (instr
->operands
[0].isConstant()) {
928 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
929 if (v
<= 64 || v
>= 0xfffffff0)
930 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
932 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
936 case aco_opcode::s_bfm_b32
: {
937 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
938 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
939 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
940 uint32_t v
= ((1u << size
) - 1u) << start
;
941 if (v
<= 64 || v
>= 0xfffffff0)
942 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
944 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
947 case aco_opcode::v_mul_f32
: { /* omod */
948 /* TODO: try to move the negate/abs modifier to the consumer instead */
949 if (instr
->usesModifiers())
952 for (unsigned i
= 0; i
< 2; i
++) {
953 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
954 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
955 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
956 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
957 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
958 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
959 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
960 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
961 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
962 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
971 case aco_opcode::v_and_b32
: /* abs */
972 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
973 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
974 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
976 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
978 case aco_opcode::v_xor_b32
: { /* neg */
979 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
980 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
981 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
982 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
983 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
984 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
985 instr
->opcode
= aco_opcode::v_or_b32
;
986 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
988 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
992 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
996 case aco_opcode::v_med3_f32
: { /* clamp */
997 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
998 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
999 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1000 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1004 bool found_zero
= false, found_one
= false;
1005 for (unsigned i
= 0; i
< 3; i
++)
1007 if (instr
->operands
[i
].constantEquals(0))
1009 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1014 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1015 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1019 case aco_opcode::v_cndmask_b32
:
1020 if (instr
->operands
[0].constantEquals(0) &&
1021 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1022 instr
->operands
[2].isTemp())
1023 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1024 else if (instr
->operands
[0].constantEquals(0) &&
1025 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1026 instr
->operands
[2].isTemp())
1027 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1029 case aco_opcode::v_cmp_lg_u32
:
1030 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1031 instr
->operands
[0].constantEquals(0) &&
1032 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1033 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1035 case aco_opcode::p_phi
:
1036 case aco_opcode::p_linear_phi
: {
1037 /* lower_bool_phis() can create phis like this */
1038 bool all_same_temp
= instr
->operands
[0].isTemp();
1039 /* this check is needed when moving uniform loop counters out of a divergent loop */
1041 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1042 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1043 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1044 all_same_temp
= false;
1046 if (all_same_temp
) {
1047 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1049 bool all_undef
= instr
->operands
[0].isUndefined();
1050 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1051 if (!instr
->operands
[i
].isUndefined())
1055 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1059 case aco_opcode::v_add_u32
:
1060 case aco_opcode::v_add_co_u32
:
1061 case aco_opcode::s_add_i32
:
1062 case aco_opcode::s_add_u32
:
1063 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1065 case aco_opcode::s_and_b32
:
1066 case aco_opcode::s_and_b64
:
1067 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1068 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1069 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1072 case aco_opcode::s_not_b32
:
1073 case aco_opcode::s_not_b64
:
1074 case aco_opcode::s_or_b32
:
1075 case aco_opcode::s_or_b64
:
1076 case aco_opcode::s_xor_b32
:
1077 case aco_opcode::s_xor_b64
:
1078 case aco_opcode::s_lshl_b32
:
1079 case aco_opcode::v_or_b32
:
1080 case aco_opcode::v_lshlrev_b32
:
1081 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1083 case aco_opcode::v_min_f32
:
1084 case aco_opcode::v_min_f16
:
1085 case aco_opcode::v_min_u32
:
1086 case aco_opcode::v_min_i32
:
1087 case aco_opcode::v_min_u16
:
1088 case aco_opcode::v_min_i16
:
1089 case aco_opcode::v_max_f32
:
1090 case aco_opcode::v_max_f16
:
1091 case aco_opcode::v_max_u32
:
1092 case aco_opcode::v_max_i32
:
1093 case aco_opcode::v_max_u16
:
1094 case aco_opcode::v_max_i16
:
1095 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1097 case aco_opcode::v_cmp_lt_f32
:
1098 case aco_opcode::v_cmp_eq_f32
:
1099 case aco_opcode::v_cmp_le_f32
:
1100 case aco_opcode::v_cmp_gt_f32
:
1101 case aco_opcode::v_cmp_lg_f32
:
1102 case aco_opcode::v_cmp_ge_f32
:
1103 case aco_opcode::v_cmp_o_f32
:
1104 case aco_opcode::v_cmp_u_f32
:
1105 case aco_opcode::v_cmp_nge_f32
:
1106 case aco_opcode::v_cmp_nlg_f32
:
1107 case aco_opcode::v_cmp_ngt_f32
:
1108 case aco_opcode::v_cmp_nle_f32
:
1109 case aco_opcode::v_cmp_neq_f32
:
1110 case aco_opcode::v_cmp_nlt_f32
:
1111 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1113 case aco_opcode::s_cselect_b64
:
1114 case aco_opcode::s_cselect_b32
:
1115 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1116 instr
->operands
[1].constantEquals(0)) {
1117 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1118 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1126 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1128 *ordered
= *unordered
= op
;
1130 #define CMP(ord, unord) \
1131 case aco_opcode::v_cmp_##ord##_f32:\
1132 case aco_opcode::v_cmp_n##unord##_f32:\
1133 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1134 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1135 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1149 aco_opcode
get_ordered(aco_opcode op
)
1151 aco_opcode ordered
, unordered
, inverse
;
1152 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1155 aco_opcode
get_unordered(aco_opcode op
)
1157 aco_opcode ordered
, unordered
, inverse
;
1158 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1161 aco_opcode
get_inverse(aco_opcode op
)
1163 aco_opcode ordered
, unordered
, inverse
;
1164 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1167 bool is_cmp(aco_opcode op
)
1169 aco_opcode ordered
, unordered
, inverse
;
1170 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1173 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1175 if (ctx
.info
[tmp
.id()].is_temp())
1176 return ctx
.info
[tmp
.id()].temp
.id();
1181 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1183 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1184 for (const Operand
& op
: instr
->operands
) {
1186 ctx
.uses
[op
.tempId()]--;
1191 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1193 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1195 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1198 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1200 if (instr
->definitions
.size() == 2) {
1201 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1202 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1209 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1210 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1211 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1213 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1215 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1218 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1220 bool neg
[2] = {false, false};
1221 bool abs
[2] = {false, false};
1223 Instruction
*op_instr
[2];
1226 for (unsigned i
= 0; i
< 2; i
++) {
1227 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1231 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1233 if (op_instr
[i
]->opcode
!= expected_cmp
)
1235 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1238 if (op_instr
[i
]->isVOP3()) {
1239 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1240 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1242 neg
[i
] = vop3
->neg
[0];
1243 abs
[i
] = vop3
->abs
[0];
1244 opsel
|= (vop3
->opsel
& 1) << i
;
1247 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1248 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1249 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1255 if (op
[1].type() == RegType::sgpr
)
1256 std::swap(op
[0], op
[1]);
1257 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1258 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1261 ctx
.uses
[op
[0].id()]++;
1262 ctx
.uses
[op
[1].id()]++;
1263 decrease_uses(ctx
, op_instr
[0]);
1264 decrease_uses(ctx
, op_instr
[1]);
1266 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1267 Instruction
*new_instr
;
1268 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1269 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1270 for (unsigned i
= 0; i
< 2; i
++) {
1271 vop3
->neg
[i
] = neg
[i
];
1272 vop3
->abs
[i
] = abs
[i
];
1274 vop3
->opsel
= opsel
;
1275 new_instr
= static_cast<Instruction
*>(vop3
);
1277 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1279 new_instr
->operands
[0] = Operand(op
[0]);
1280 new_instr
->operands
[1] = Operand(op
[1]);
1281 new_instr
->definitions
[0] = instr
->definitions
[0];
1283 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1284 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1286 instr
.reset(new_instr
);
1291 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1292 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1293 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1295 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1297 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1300 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1301 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1303 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1304 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1305 if (!nan_test
|| !cmp
)
1308 if (cmp
->opcode
== expected_nan_test
)
1309 std::swap(nan_test
, cmp
);
1310 else if (nan_test
->opcode
!= expected_nan_test
)
1313 if (!is_cmp(cmp
->opcode
))
1316 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1318 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1321 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1322 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1323 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1324 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1325 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1327 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1330 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1331 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1332 decrease_uses(ctx
, nan_test
);
1333 decrease_uses(ctx
, cmp
);
1335 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1336 Instruction
*new_instr
;
1337 if (cmp
->isVOP3()) {
1338 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1339 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1340 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1341 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1342 new_vop3
->clamp
= cmp_vop3
->clamp
;
1343 new_vop3
->omod
= cmp_vop3
->omod
;
1344 new_vop3
->opsel
= cmp_vop3
->opsel
;
1345 new_instr
= new_vop3
;
1347 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1349 new_instr
->operands
[0] = cmp
->operands
[0];
1350 new_instr
->operands
[1] = cmp
->operands
[1];
1351 new_instr
->definitions
[0] = instr
->definitions
[0];
1353 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1354 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1356 instr
.reset(new_instr
);
1361 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1362 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1363 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1365 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1367 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1370 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1372 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1373 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1375 if (!nan_test
|| !cmp
)
1378 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1379 if (cmp
->opcode
== expected_nan_test
)
1380 std::swap(nan_test
, cmp
);
1381 else if (nan_test
->opcode
!= expected_nan_test
)
1384 if (!is_cmp(cmp
->opcode
))
1387 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1389 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1392 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1393 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1394 if (prop_nan0
!= prop_nan1
)
1397 if (nan_test
->isVOP3()) {
1398 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1399 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1403 int constant_operand
= -1;
1404 for (unsigned i
= 0; i
< 2; i
++) {
1405 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1406 constant_operand
= !i
;
1410 if (constant_operand
== -1)
1414 if (cmp
->operands
[constant_operand
].isConstant()) {
1415 constant
= cmp
->operands
[constant_operand
].constantValue();
1416 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1417 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1418 unsigned id
= original_temp_id(ctx
, tmp
);
1419 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1421 constant
= ctx
.info
[id
].val
;
1427 memcpy(&constantf
, &constant
, 4);
1428 if (isnan(constantf
))
1431 if (cmp
->operands
[0].isTemp())
1432 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1433 if (cmp
->operands
[1].isTemp())
1434 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1435 decrease_uses(ctx
, nan_test
);
1436 decrease_uses(ctx
, cmp
);
1438 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1439 Instruction
*new_instr
;
1440 if (cmp
->isVOP3()) {
1441 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1442 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1443 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1444 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1445 new_vop3
->clamp
= cmp_vop3
->clamp
;
1446 new_vop3
->omod
= cmp_vop3
->omod
;
1447 new_vop3
->opsel
= cmp_vop3
->opsel
;
1448 new_instr
= new_vop3
;
1450 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1452 new_instr
->operands
[0] = cmp
->operands
[0];
1453 new_instr
->operands
[1] = cmp
->operands
[1];
1454 new_instr
->definitions
[0] = instr
->definitions
[0];
1456 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1457 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1459 instr
.reset(new_instr
);
1464 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1465 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1467 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1469 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1471 if (!instr
->operands
[0].isTemp())
1474 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1478 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1479 if (new_opcode
== aco_opcode::last_opcode
)
1482 if (cmp
->operands
[0].isTemp())
1483 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1484 if (cmp
->operands
[1].isTemp())
1485 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1486 decrease_uses(ctx
, cmp
);
1488 Instruction
*new_instr
;
1489 if (cmp
->isVOP3()) {
1490 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1491 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1492 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1493 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1494 new_vop3
->clamp
= cmp_vop3
->clamp
;
1495 new_vop3
->omod
= cmp_vop3
->omod
;
1496 new_vop3
->opsel
= cmp_vop3
->opsel
;
1497 new_instr
= new_vop3
;
1499 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1501 new_instr
->operands
[0] = cmp
->operands
[0];
1502 new_instr
->operands
[1] = cmp
->operands
[1];
1503 new_instr
->definitions
[0] = instr
->definitions
[0];
1505 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1506 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1508 instr
.reset(new_instr
);
1513 /* op1(op2(1, 2), 0) if swap = false
1514 * op1(0, op2(1, 2)) if swap = true */
1515 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1516 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1517 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1518 bool *op1_clamp
, uint8_t *op1_omod
,
1519 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1522 if (op1_instr
->opcode
!= op1
)
1525 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1526 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1529 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1530 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1532 /* don't support inbetween clamp/omod */
1533 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1536 /* get operands and modifiers and check inbetween modifiers */
1537 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1538 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1541 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1542 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1546 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1547 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1550 if (inbetween_opsel
)
1551 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1552 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1556 shuffle
[shuffle_str
[0] - '0'] = 0;
1557 shuffle
[shuffle_str
[1] - '0'] = 1;
1558 shuffle
[shuffle_str
[2] - '0'] = 2;
1560 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1561 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1562 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1563 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1564 *opsel
|= 1 << shuffle
[0];
1566 for (unsigned i
= 0; i
< 2; i
++) {
1567 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1568 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1569 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1570 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1571 *opsel
|= 1 << shuffle
[i
+ 1];
1574 /* check operands */
1575 if (!check_vop3_operands(ctx
, 3, operands
))
1581 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1582 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1583 bool clamp
, unsigned omod
)
1585 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1586 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1587 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1588 new_instr
->clamp
= clamp
;
1589 new_instr
->omod
= omod
;
1590 new_instr
->opsel
= opsel
;
1591 new_instr
->operands
[0] = operands
[0];
1592 new_instr
->operands
[1] = operands
[1];
1593 new_instr
->operands
[2] = operands
[2];
1594 new_instr
->definitions
[0] = instr
->definitions
[0];
1595 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1597 instr
.reset(new_instr
);
1600 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1602 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1603 (label_omod_success
| label_clamp_success
);
1605 for (unsigned swap
= 0; swap
< 2; swap
++) {
1606 if (!((1 << swap
) & ops
))
1609 Operand operands
[3];
1610 bool neg
[3], abs
[3], clamp
;
1611 uint8_t opsel
= 0, omod
= 0;
1612 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1613 instr
.get(), swap
, shuffle
,
1614 operands
, neg
, abs
, &opsel
,
1615 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1616 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1617 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1618 if (omod_clamp
& label_omod_success
)
1619 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1620 if (omod_clamp
& label_clamp_success
)
1621 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1628 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1629 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1630 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1631 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1632 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1633 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1634 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1637 if (!instr
->operands
[0].isTemp())
1639 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1642 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1645 switch (op2_instr
->opcode
) {
1646 case aco_opcode::s_and_b32
:
1647 case aco_opcode::s_or_b32
:
1648 case aco_opcode::s_xor_b32
:
1649 case aco_opcode::s_and_b64
:
1650 case aco_opcode::s_or_b64
:
1651 case aco_opcode::s_xor_b64
:
1657 /* create instruction */
1658 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1659 ctx
.uses
[instr
->operands
[0].tempId()]--;
1660 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1662 switch (op2_instr
->opcode
) {
1663 case aco_opcode::s_and_b32
:
1664 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1666 case aco_opcode::s_or_b32
:
1667 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1669 case aco_opcode::s_xor_b32
:
1670 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1672 case aco_opcode::s_and_b64
:
1673 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1675 case aco_opcode::s_or_b64
:
1676 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1678 case aco_opcode::s_xor_b64
:
1679 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1688 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1689 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1690 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1691 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1692 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1694 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1697 for (unsigned i
= 0; i
< 2; i
++) {
1698 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1699 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1702 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1703 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1706 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1707 instr
->operands
[0] = instr
->operands
[!i
];
1708 instr
->operands
[1] = op2_instr
->operands
[0];
1709 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1711 switch (instr
->opcode
) {
1712 case aco_opcode::s_and_b32
:
1713 instr
->opcode
= aco_opcode::s_andn2_b32
;
1715 case aco_opcode::s_or_b32
:
1716 instr
->opcode
= aco_opcode::s_orn2_b32
;
1718 case aco_opcode::s_and_b64
:
1719 instr
->opcode
= aco_opcode::s_andn2_b64
;
1721 case aco_opcode::s_or_b64
:
1722 instr
->opcode
= aco_opcode::s_orn2_b64
;
1733 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1734 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1736 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1739 for (unsigned i
= 0; i
< 2; i
++) {
1740 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1741 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1744 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1745 if (shift
< 1 || shift
> 4)
1748 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1749 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1752 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1753 instr
->operands
[1] = instr
->operands
[!i
];
1754 instr
->operands
[0] = op2_instr
->operands
[0];
1755 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1757 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1758 aco_opcode::s_lshl2_add_u32
,
1759 aco_opcode::s_lshl3_add_u32
,
1760 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1767 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1770 #define MINMAX(type, gfx9) \
1771 case aco_opcode::v_min_##type:\
1772 case aco_opcode::v_max_##type:\
1773 case aco_opcode::v_med3_##type:\
1774 *min = aco_opcode::v_min_##type;\
1775 *max = aco_opcode::v_max_##type;\
1776 *med3 = aco_opcode::v_med3_##type;\
1777 *min3 = aco_opcode::v_min3_##type;\
1778 *max3 = aco_opcode::v_max3_##type;\
1779 *some_gfx9_only = gfx9;\
1793 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1794 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1795 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1796 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1798 aco_opcode other_op
;
1799 if (instr
->opcode
== min
)
1801 else if (instr
->opcode
== max
)
1806 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1807 (label_omod_success
| label_clamp_success
);
1809 for (unsigned swap
= 0; swap
< 2; swap
++) {
1810 Operand operands
[3];
1811 bool neg
[3], abs
[3], clamp
, inbetween_neg
, inbetween_abs
;
1812 uint8_t opsel
= 0, omod
= 0;
1813 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1814 "012", operands
, neg
, abs
, &opsel
,
1815 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1816 int const0_idx
= -1, const1_idx
= -1;
1817 uint32_t const0
= 0, const1
= 0;
1818 for (int i
= 0; i
< 3; i
++) {
1820 if (operands
[i
].isConstant()) {
1821 val
= operands
[i
].constantValue();
1822 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1823 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1824 val
= ctx
.info
[operands
[i
].tempId()].val
;
1828 if (const0_idx
>= 0) {
1836 if (const0_idx
< 0 || const1_idx
< 0)
1839 if (opsel
& (1 << const0_idx
))
1841 if (opsel
& (1 << const1_idx
))
1844 int lower_idx
= const0_idx
;
1846 case aco_opcode::v_min_f32
:
1847 case aco_opcode::v_min_f16
: {
1848 float const0_f
, const1_f
;
1849 if (min
== aco_opcode::v_min_f32
) {
1850 memcpy(&const0_f
, &const0
, 4);
1851 memcpy(&const1_f
, &const1
, 4);
1853 const0_f
= _mesa_half_to_float(const0
);
1854 const1_f
= _mesa_half_to_float(const1
);
1856 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1857 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1858 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1859 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1860 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1863 case aco_opcode::v_min_u32
: {
1864 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1867 case aco_opcode::v_min_u16
: {
1868 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1871 case aco_opcode::v_min_i32
: {
1872 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1873 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1874 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1877 case aco_opcode::v_min_i16
: {
1878 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1879 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1880 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1886 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1888 if (instr
->opcode
== min
) {
1889 if (upper_idx
!= 0 || lower_idx
== 0)
1892 if (upper_idx
== 0 || lower_idx
!= 0)
1896 neg
[1] ^= inbetween_neg
;
1897 neg
[2] ^= inbetween_neg
;
1898 abs
[1] |= inbetween_abs
;
1899 abs
[2] |= inbetween_abs
;
1901 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1902 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1903 if (omod_clamp
& label_omod_success
)
1904 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1905 if (omod_clamp
& label_clamp_success
)
1906 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1916 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1918 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
1919 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
1920 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
1922 /* find candidates and create the set of sgprs already read */
1923 unsigned sgpr_ids
[2] = {0, 0};
1924 uint32_t operand_mask
= 0;
1925 bool has_literal
= false;
1926 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1927 if (instr
->operands
[i
].isLiteral())
1929 if (!instr
->operands
[i
].isTemp())
1931 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1932 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
1933 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
1935 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1936 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
1937 operand_mask
|= 1u << i
;
1939 unsigned max_sgprs
= 1;
1940 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
1945 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
1947 /* keep on applying sgprs until there is nothing left to be done */
1948 while (operand_mask
) {
1949 uint32_t sgpr_idx
= 0;
1950 uint32_t sgpr_info_id
= 0;
1951 uint32_t mask
= operand_mask
;
1954 unsigned i
= u_bit_scan(&mask
);
1955 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1956 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1958 sgpr_info_id
= instr
->operands
[i
].tempId();
1961 operand_mask
&= ~(1u << sgpr_idx
);
1963 /* Applying two sgprs require making it VOP3, so don't do it unless it's
1964 * definitively beneficial.
1965 * TODO: this is too conservative because later the use count could be reduced to 1 */
1966 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
1969 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
1970 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
1971 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
1974 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1975 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
1976 } else if (can_swap_operands(instr
)) {
1977 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1978 instr
->operands
[0] = Operand(sgpr
);
1979 /* swap bits using a 4-entry LUT */
1980 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
1981 operand_mask
= (operand_mask
& ~0x3) | swapped
;
1982 } else if (can_use_VOP3(ctx
, instr
)) {
1983 to_VOP3(ctx
, instr
);
1984 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
1989 sgpr_ids
[num_sgprs
++] = sgpr
.id();
1990 ctx
.uses
[sgpr_info_id
]--;
1991 ctx
.uses
[sgpr
.id()]++;
1995 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1997 /* check if we could apply omod on predecessor */
1998 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1999 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2000 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2002 unsigned idx
= op0
? 0 : 1;
2003 /* omod was successfully applied */
2004 /* if the omod instruction is v_mad, we also have to change the original add */
2005 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2006 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2007 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2008 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2009 add_instr
->definitions
[0] = instr
->definitions
[0];
2012 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2013 /* check if we have an additional clamp modifier */
2014 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2015 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2016 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2017 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2019 /* change definition ssa-id of modified instruction */
2020 omod_instr
->definitions
[0] = instr
->definitions
[0];
2022 /* change the definition of instr to something unused, e.g. the original omod def */
2023 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2024 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2027 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2028 /* in all other cases, label this instruction as option for multiply-add */
2029 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2033 /* check if we could apply clamp on predecessor */
2034 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2036 bool found_zero
= false, found_one
= false;
2037 for (unsigned i
= 0; i
< 3; i
++)
2039 if (instr
->operands
[i
].constantEquals(0))
2041 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2046 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2047 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2048 /* clamp was successfully applied */
2049 /* if the clamp instruction is v_mad, we also have to change the original add */
2050 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2051 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2052 add_instr
->definitions
[0] = instr
->definitions
[0];
2054 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2055 /* change definition ssa-id of modified instruction */
2056 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2058 /* change the definition of instr to something unused, e.g. the original omod def */
2059 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2060 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2065 /* omod has no effect if denormals are enabled */
2066 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2068 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2069 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2070 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2071 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2072 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2073 to_VOP3(ctx
, instr
);
2074 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2075 def_info
.set_omod_success(instr
.get());
2076 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2077 to_VOP3(ctx
, instr
);
2078 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2079 def_info
.set_omod_success(instr
.get());
2080 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2081 to_VOP3(ctx
, instr
);
2082 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2083 def_info
.set_omod_success(instr
.get());
2084 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2085 to_VOP3(ctx
, instr
);
2086 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2087 def_info
.set_clamp_success(instr
.get());
2094 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2095 // this would mean that we'd have to fix the instruction uses while value propagation
2097 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2099 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2102 if (instr
->isVALU()) {
2103 if (can_apply_sgprs(instr
))
2104 apply_sgprs(ctx
, instr
);
2105 if (apply_omod_clamp(ctx
, block
, instr
))
2109 /* TODO: There are still some peephole optimizations that could be done:
2110 * - abs(a - b) -> s_absdiff_i32
2111 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2112 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2113 * These aren't probably too interesting though.
2114 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2115 * probably more useful than the previously mentioned optimizations.
2116 * The various comparison optimizations also currently only work with 32-bit
2119 /* neg(mul(a, b)) -> mul(neg(a), b) */
2120 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2121 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2123 if (!ctx
.info
[val
.id()].is_mul())
2126 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2128 if (mul_instr
->operands
[0].isLiteral())
2130 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2133 /* convert to mul(neg(a), b) */
2134 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2135 Definition def
= instr
->definitions
[0];
2136 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2137 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2138 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2139 instr
->operands
[0] = mul_instr
->operands
[0];
2140 instr
->operands
[1] = mul_instr
->operands
[1];
2141 instr
->definitions
[0] = def
;
2142 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2143 if (mul_instr
->isVOP3()) {
2144 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2145 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2146 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2147 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2148 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2149 new_mul
->omod
= mul
->omod
;
2151 new_mul
->neg
[0] ^= true;
2152 new_mul
->clamp
= false;
2154 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2157 /* combine mul+add -> mad */
2158 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2159 instr
->opcode
== aco_opcode::v_sub_f32
||
2160 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2161 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2162 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2164 uint32_t uses_src0
= UINT32_MAX
;
2165 uint32_t uses_src1
= UINT32_MAX
;
2166 Instruction
* mul_instr
= nullptr;
2167 unsigned add_op_idx
;
2168 /* check if any of the operands is a multiplication */
2169 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2170 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2171 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2172 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2174 /* find the 'best' mul instruction to combine with the add */
2175 if (uses_src0
< uses_src1
) {
2176 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2178 } else if (uses_src1
< uses_src0
) {
2179 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2181 } else if (uses_src0
!= UINT32_MAX
) {
2182 /* tiebreaker: quite random what to pick */
2183 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2184 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2187 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2192 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2193 bool neg
[3] = {false, false, false};
2194 bool abs
[3] = {false, false, false};
2197 bool need_vop3
= false;
2198 op
[0] = mul_instr
->operands
[0];
2199 op
[1] = mul_instr
->operands
[1];
2200 op
[2] = instr
->operands
[add_op_idx
];
2201 // TODO: would be better to check this before selecting a mul instr?
2202 if (!check_vop3_operands(ctx
, 3, op
))
2205 for (unsigned i
= 0; i
< 3; i
++) {
2206 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2210 if (mul_instr
->isVOP3()) {
2211 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2212 neg
[0] = vop3
->neg
[0];
2213 neg
[1] = vop3
->neg
[1];
2214 abs
[0] = vop3
->abs
[0];
2215 abs
[1] = vop3
->abs
[1];
2217 /* we cannot use these modifiers between mul and add */
2218 if (vop3
->clamp
|| vop3
->omod
)
2222 /* convert to mad */
2223 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2224 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2226 ctx
.uses
[op
[0].tempId()]++;
2228 ctx
.uses
[op
[1].tempId()]++;
2231 if (instr
->isVOP3()) {
2232 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2233 neg
[2] = vop3
->neg
[add_op_idx
];
2234 abs
[2] = vop3
->abs
[add_op_idx
];
2236 clamp
= vop3
->clamp
;
2237 /* abs of the multiplication result */
2238 if (vop3
->abs
[1 - add_op_idx
]) {
2244 /* neg of the multiplication result */
2245 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2248 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2249 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2251 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2252 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2256 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2257 for (unsigned i
= 0; i
< 3; i
++)
2259 mad
->operands
[i
] = op
[i
];
2260 mad
->neg
[i
] = neg
[i
];
2261 mad
->abs
[i
] = abs
[i
];
2265 mad
->definitions
[0] = instr
->definitions
[0];
2267 /* mark this ssa_def to be re-checked for profitability and literals */
2268 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2269 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2270 instr
.reset(mad
.release());
2274 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2275 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2276 for (unsigned i
= 0; i
< 2; i
++) {
2277 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2278 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2279 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2280 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2281 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2283 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2284 new_instr
->operands
[0] = Operand(0u);
2285 new_instr
->operands
[1] = instr
->operands
[!i
];
2286 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2287 new_instr
->definitions
[0] = instr
->definitions
[0];
2288 instr
.reset(new_instr
.release());
2289 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2293 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2294 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2295 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2296 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2297 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2298 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2299 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2300 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2301 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2302 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2303 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2304 combine_salu_lshl_add(ctx
, instr
);
2305 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2306 combine_salu_not_bitwise(ctx
, instr
);
2307 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2308 if (combine_inverse_comparison(ctx
, instr
)) ;
2309 else combine_salu_not_bitwise(ctx
, instr
);
2310 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2311 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2312 if (combine_ordering_test(ctx
, instr
)) ;
2313 else if (combine_comparison_ordering(ctx
, instr
)) ;
2314 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2315 else combine_salu_n2(ctx
, instr
);
2317 aco_opcode min
, max
, min3
, max3
, med3
;
2318 bool some_gfx9_only
;
2319 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2320 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2321 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2322 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2328 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2330 const uint32_t threshold
= 4;
2332 if (is_dead(ctx
.uses
, instr
.get())) {
2337 /* convert split_vector into extract_vector if only one definition is ever used */
2338 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2339 unsigned num_used
= 0;
2341 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2342 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2347 if (num_used
== 1) {
2348 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2349 extract
->operands
[0] = instr
->operands
[0];
2350 extract
->operands
[1] = Operand((uint32_t) idx
);
2351 extract
->definitions
[0] = instr
->definitions
[idx
];
2352 instr
.reset(extract
.release());
2356 /* re-check mad instructions */
2357 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2358 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2359 /* first, check profitability */
2360 if (ctx
.uses
[info
->mul_temp_id
]) {
2361 ctx
.uses
[info
->mul_temp_id
]++;
2362 if (instr
->operands
[0].isTemp())
2363 ctx
.uses
[instr
->operands
[0].tempId()]--;
2364 if (instr
->operands
[1].isTemp())
2365 ctx
.uses
[instr
->operands
[1].tempId()]--;
2366 instr
.swap(info
->add_instr
);
2368 /* second, check possible literals */
2369 } else if (!info
->needs_vop3
) {
2370 uint32_t literal_idx
= 0;
2371 uint32_t literal_uses
= UINT32_MAX
;
2372 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2374 if (!instr
->operands
[i
].isTemp())
2376 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2377 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2378 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2379 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2382 literal_uses
= UINT32_MAX
;
2386 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2387 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2388 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2392 if (literal_uses
< threshold
) {
2393 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2394 info
->check_literal
= true;
2395 info
->literal_idx
= literal_idx
;
2401 /* check for literals */
2402 if (!instr
->isSALU() && !instr
->isVALU())
2405 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2406 return; /* some encodings can't ever take literals */
2408 /* we do not apply the literals yet as we don't know if it is profitable */
2409 Operand
current_literal(s1
);
2411 unsigned literal_id
= 0;
2412 unsigned literal_uses
= UINT32_MAX
;
2413 Operand
literal(s1
);
2414 unsigned num_operands
= 1;
2415 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2416 num_operands
= instr
->operands
.size();
2418 unsigned sgpr_ids
[2] = {0, 0};
2419 bool is_literal_sgpr
= false;
2422 /* choose a literal to apply */
2423 for (unsigned i
= 0; i
< num_operands
; i
++) {
2424 Operand op
= instr
->operands
[i
];
2425 if (op
.isLiteral()) {
2426 current_literal
= op
;
2428 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2429 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2430 op
.tempId() != sgpr_ids
[0])
2431 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2435 if (!can_accept_constant(instr
, i
))
2438 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2439 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2441 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2442 literal_uses
= ctx
.uses
[op
.tempId()];
2443 literal_id
= op
.tempId();
2446 mask
|= (op
.tempId() == literal_id
) << i
;
2450 /* don't go over the constant bus limit */
2451 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2452 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2453 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2454 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2455 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2456 const_bus_limit
= 2;
2458 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2459 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2462 if (literal_id
&& literal_uses
< threshold
&&
2463 (current_literal
.isUndefined() ||
2464 (current_literal
.size() == literal
.size() &&
2465 current_literal
.constantValue() == literal
.constantValue()))) {
2466 /* mark the literal to be applied */
2468 unsigned i
= u_bit_scan(&mask
);
2469 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2470 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2476 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2478 /* Cleanup Dead Instructions */
2482 /* apply literals on MAD */
2483 bool literals_applied
= false;
2484 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2485 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2486 if (!info
->needs_vop3
) {
2487 aco_ptr
<Instruction
> new_mad
;
2488 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2489 if (info
->literal_idx
== 2) { /* add literal -> madak */
2490 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2491 new_mad
->operands
[0] = instr
->operands
[0];
2492 new_mad
->operands
[1] = instr
->operands
[1];
2493 } else { /* mul literal -> madmk */
2494 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2495 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2496 new_mad
->operands
[1] = instr
->operands
[2];
2498 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2499 new_mad
->definitions
[0] = instr
->definitions
[0];
2500 instr
.swap(new_mad
);
2502 literals_applied
= true;
2506 /* apply literals on SALU/VALU */
2507 if (!literals_applied
&& (instr
->isSALU() || instr
->isVALU())) {
2508 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2509 Operand op
= instr
->operands
[i
];
2510 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2511 Operand
literal(ctx
.info
[op
.tempId()].val
);
2512 if (instr
->isVALU() && i
> 0)
2513 to_VOP3(ctx
, instr
);
2514 instr
->operands
[i
] = literal
;
2519 ctx
.instructions
.emplace_back(std::move(instr
));
2523 void optimize(Program
* program
)
2526 ctx
.program
= program
;
2527 std::vector
<ssa_info
> info(program
->peekAllocationId());
2528 ctx
.info
= info
.data();
2530 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2531 for (Block
& block
: program
->blocks
) {
2532 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2533 label_instruction(ctx
, block
, instr
);
2536 ctx
.uses
= std::move(dead_code_analysis(program
));
2538 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2539 for (Block
& block
: program
->blocks
) {
2540 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2541 combine_instruction(ctx
, block
, instr
);
2544 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2545 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2546 Block
* block
= &(*it
);
2547 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2548 select_instruction(ctx
, *it
);
2551 /* 4. Add literals to instructions */
2552 for (Block
& block
: program
->blocks
) {
2553 ctx
.instructions
.clear();
2554 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2555 apply_literals(ctx
, instr
);
2556 block
.instructions
.swap(ctx
.instructions
);