2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
87 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
88 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
;
89 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
99 void add_label(Label new_label
)
101 /* Since all labels which use "instr" use it for the same thing
102 * (indicating the defining instruction), there is no need to clear
103 * any other instr labels. */
104 if (new_label
& instr_labels
)
105 label
&= ~temp_labels
; /* instr and temp alias */
107 if (new_label
& temp_labels
) {
108 label
&= ~temp_labels
;
109 label
&= ~instr_labels
; /* instr and temp alias */
112 if (new_label
& val_labels
)
113 label
&= ~val_labels
;
118 void set_vec(Instruction
* vec
)
120 add_label(label_vec
);
126 return label
& label_vec
;
129 void set_constant(uint32_t constant
)
131 add_label(label_constant
);
137 return label
& label_constant
;
140 void set_abs(Temp abs_temp
)
142 add_label(label_abs
);
148 return label
& label_abs
;
151 void set_neg(Temp neg_temp
)
153 add_label(label_neg
);
159 return label
& label_neg
;
162 void set_neg_abs(Temp neg_abs_temp
)
164 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
168 void set_mul(Instruction
* mul
)
170 add_label(label_mul
);
176 return label
& label_mul
;
179 void set_temp(Temp tmp
)
181 add_label(label_temp
);
187 return label
& label_temp
;
190 void set_literal(uint32_t lit
)
192 add_label(label_literal
);
198 return label
& label_literal
;
201 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
203 add_label(label_mad
);
210 return label
& label_mad
;
215 add_label(label_omod2
);
220 return label
& label_omod2
;
225 add_label(label_omod4
);
230 return label
& label_omod4
;
235 add_label(label_omod5
);
240 return label
& label_omod5
;
243 void set_omod_success(Instruction
* omod_instr
)
245 add_label(label_omod_success
);
249 bool is_omod_success()
251 return label
& label_omod_success
;
256 add_label(label_clamp
);
261 return label
& label_clamp
;
264 void set_clamp_success(Instruction
* clamp_instr
)
266 add_label(label_clamp_success
);
270 bool is_clamp_success()
272 return label
& label_clamp_success
;
277 add_label(label_undefined
);
282 return label
& label_undefined
;
285 void set_vcc(Temp vcc
)
287 add_label(label_vcc
);
293 return label
& label_vcc
;
296 bool is_constant_or_literal()
298 return is_constant() || is_literal();
301 void set_b2f(Temp val
)
303 add_label(label_b2f
);
309 return label
& label_b2f
;
312 void set_add_sub(Instruction
*add_sub_instr
)
314 add_label(label_add_sub
);
315 instr
= add_sub_instr
;
320 return label
& label_add_sub
;
323 void set_bitwise(Instruction
*bitwise_instr
)
325 add_label(label_bitwise
);
326 instr
= bitwise_instr
;
331 return label
& label_bitwise
;
334 void set_minmax(Instruction
*minmax_instr
)
336 add_label(label_minmax
);
337 instr
= minmax_instr
;
342 return label
& label_minmax
;
345 void set_fcmp(Instruction
*fcmp_instr
)
347 add_label(label_fcmp
);
353 return label
& label_fcmp
;
360 std::vector
<aco_ptr
<Instruction
>> instructions
;
362 std::pair
<uint32_t,Temp
> last_literal
;
363 std::vector
<mad_info
> mad_infos
;
364 std::vector
<uint16_t> uses
;
367 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
369 if (instr
->operands
[0].isConstant() ||
370 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
373 switch (instr
->opcode
) {
374 case aco_opcode::v_add_f32
:
375 case aco_opcode::v_mul_f32
:
376 case aco_opcode::v_or_b32
:
377 case aco_opcode::v_and_b32
:
378 case aco_opcode::v_xor_b32
:
379 case aco_opcode::v_max_f32
:
380 case aco_opcode::v_min_f32
:
381 case aco_opcode::v_cmp_eq_f32
:
382 case aco_opcode::v_cmp_lg_f32
:
384 case aco_opcode::v_sub_f32
:
385 instr
->opcode
= aco_opcode::v_subrev_f32
;
387 case aco_opcode::v_cmp_lt_f32
:
388 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
390 case aco_opcode::v_cmp_ge_f32
:
391 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
393 case aco_opcode::v_cmp_lt_i32
:
394 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
401 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
403 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
406 if (instr
->isDPP() || instr
->isSDWA())
409 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
410 instr
->opcode
!= aco_opcode::v_madak_f32
&&
411 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
412 instr
->opcode
!= aco_opcode::v_madak_f16
;
415 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
417 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
418 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
419 instr
->opcode
!= aco_opcode::v_writelane_b32
;
422 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
427 assert(!instr
->operands
[0].isLiteral());
428 aco_ptr
<Instruction
> tmp
= std::move(instr
);
429 Format format
= asVOP3(tmp
->format
);
430 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
431 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
432 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
433 instr
->definitions
[i
] = tmp
->definitions
[i
];
434 if (instr
->definitions
[i
].isTemp()) {
435 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
436 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
437 info
.instr
= instr
.get();
442 /* only covers special cases */
443 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
445 switch (instr
->opcode
) {
446 case aco_opcode::v_interp_p2_f32
:
447 case aco_opcode::v_mac_f32
:
448 case aco_opcode::v_writelane_b32
:
449 case aco_opcode::v_cndmask_b32
:
451 case aco_opcode::s_addk_i32
:
452 case aco_opcode::s_mulk_i32
:
453 case aco_opcode::p_wqm
:
454 case aco_opcode::p_extract_vector
:
455 case aco_opcode::p_split_vector
:
456 case aco_opcode::v_readlane_b32
:
457 case aco_opcode::v_readfirstlane_b32
:
460 if ((instr
->format
== Format::MUBUF
||
461 instr
->format
== Format::MIMG
) &&
462 instr
->definitions
.size() == 1 &&
463 instr
->operands
.size() == 4) {
470 bool valu_can_accept_literal(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, unsigned operand
)
472 // TODO: VOP3 can take a literal on GFX10
473 return !instr
->isSDWA() && !instr
->isDPP() && !instr
->isVOP3() &&
474 operand
== 0 && can_accept_constant(instr
, operand
);
477 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
479 Operand op
= instr
->operands
[op_index
];
483 Temp tmp
= op
.getTemp();
484 if (!ctx
.info
[tmp
.id()].is_add_sub())
487 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
489 switch (add_instr
->opcode
) {
490 case aco_opcode::v_add_u32
:
491 case aco_opcode::v_add_co_u32
:
492 case aco_opcode::s_add_i32
:
493 case aco_opcode::s_add_u32
:
499 for (unsigned i
= 0; i
< 2; i
++) {
500 if (add_instr
->operands
[i
].isConstant()) {
501 *offset
= add_instr
->operands
[i
].constantValue();
502 } else if (add_instr
->operands
[i
].isTemp() &&
503 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
504 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
508 if (!add_instr
->operands
[!i
].isTemp())
511 uint32_t offset2
= 0;
512 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
515 *base
= add_instr
->operands
[!i
].getTemp();
523 void label_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
525 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
526 ASSERTED
bool all_const
= false;
527 for (Operand
& op
: instr
->operands
)
528 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
529 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
532 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
534 if (!instr
->operands
[i
].isTemp())
537 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
538 /* propagate undef */
539 if (info
.is_undefined() && is_phi(instr
))
540 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
541 /* propagate reg->reg of same type */
542 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
543 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
544 info
= ctx
.info
[info
.temp
.id()];
547 /* SALU / PSEUDO: propagate inline constants */
548 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
549 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
550 instr
->operands
[i
].setTemp(info
.temp
);
551 info
= ctx
.info
[info
.temp
.id()];
552 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
553 /* propagate vgpr if it can take it */
554 switch (instr
->opcode
) {
555 case aco_opcode::p_create_vector
:
556 case aco_opcode::p_split_vector
:
557 case aco_opcode::p_extract_vector
:
558 case aco_opcode::p_phi
: {
559 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
560 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
562 instr
->operands
[i
] = Operand(info
.temp
);
563 info
= ctx
.info
[info
.temp
.id()];
571 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
572 instr
->operands
[i
] = Operand(info
.val
);
577 /* VALU: propagate neg, abs & inline constants */
578 else if (instr
->isVALU()) {
579 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
580 instr
->operands
[i
].setTemp(info
.temp
);
581 info
= ctx
.info
[info
.temp
.id()];
583 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
586 instr
->operands
[i
] = Operand(info
.temp
);
588 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
590 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
592 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
593 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
594 instr
->operands
[i
].setTemp(info
.temp
);
596 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
599 instr
->operands
[i
].setTemp(info
.temp
);
601 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
603 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
606 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
607 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
609 instr
->operands
[i
] = Operand(info
.val
);
611 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
612 instr
->operands
[i
] = instr
->operands
[0];
613 instr
->operands
[0] = Operand(info
.val
);
615 } else if (can_use_VOP3(instr
)) {
617 instr
->operands
[i
] = Operand(info
.val
);
623 /* MUBUF: propagate constants and combine additions */
624 else if (instr
->format
== Format::MUBUF
) {
625 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
628 while (info
.is_temp())
629 info
= ctx
.info
[info
.temp
.id()];
631 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
632 assert(!mubuf
->idxen
);
633 instr
->operands
[i
] = Operand(v1
);
634 mubuf
->offset
+= info
.val
;
635 mubuf
->offen
= false;
637 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
638 instr
->operands
[2] = Operand((uint32_t) 0);
639 mubuf
->offset
+= info
.val
;
641 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
642 assert(!mubuf
->idxen
);
643 instr
->operands
[i
].setTemp(base
);
644 mubuf
->offset
+= offset
;
646 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
647 instr
->operands
[i
].setTemp(base
);
648 mubuf
->offset
+= offset
;
653 /* DS: combine additions */
654 else if (instr
->format
== Format::DS
) {
656 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
659 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass()) {
660 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
) {
661 if (offset
% 4 == 0 &&
662 ds
->offset0
+ (offset
>> 2) <= 255 &&
663 ds
->offset1
+ (offset
>> 2) <= 255) {
664 instr
->operands
[i
].setTemp(base
);
665 ds
->offset0
+= offset
>> 2;
666 ds
->offset1
+= offset
>> 2;
669 if (ds
->offset0
+ offset
<= 65535) {
670 instr
->operands
[i
].setTemp(base
);
671 ds
->offset0
+= offset
;
677 /* SMEM: propagate constants and combine additions */
678 else if (instr
->format
== Format::SMEM
) {
680 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
683 if (i
== 1 && info
.is_constant_or_literal() && info
.val
<= 0xFFFFF) {
684 instr
->operands
[i
] = Operand(info
.val
);
686 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
687 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
689 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
690 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
694 smem
->operands
[1] = Operand(offset
);
695 smem
->operands
.back() = Operand(base
);
697 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
698 new_instr
->operands
[0] = smem
->operands
[0];
699 new_instr
->operands
[1] = Operand(offset
);
700 if (smem
->definitions
.empty())
701 new_instr
->operands
[2] = smem
->operands
[2];
702 new_instr
->operands
.back() = Operand(base
);
703 if (!smem
->definitions
.empty())
704 new_instr
->definitions
[0] = smem
->definitions
[0];
705 instr
.reset(new_instr
);
706 smem
= static_cast<SMEM_instruction
*>(instr
.get());
713 /* if this instruction doesn't define anything, return */
714 if (instr
->definitions
.empty())
717 switch (instr
->opcode
) {
718 case aco_opcode::p_create_vector
: {
719 unsigned num_ops
= instr
->operands
.size();
720 for (const Operand
& op
: instr
->operands
) {
721 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
722 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
724 if (num_ops
!= instr
->operands
.size()) {
725 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
726 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
727 instr
->definitions
[0] = old_vec
->definitions
[0];
729 for (Operand
& old_op
: old_vec
->operands
) {
730 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
731 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++)
732 instr
->operands
[k
++] = ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
734 instr
->operands
[k
++] = old_op
;
737 assert(k
== num_ops
);
739 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
740 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
741 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
742 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
745 case aco_opcode::p_split_vector
: {
746 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
748 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
749 assert(instr
->definitions
.size() == vec
->operands
.size());
750 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
751 Operand vec_op
= vec
->operands
[i
];
752 if (vec_op
.isConstant()) {
753 if (vec_op
.isLiteral())
754 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
756 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
758 assert(vec_op
.isTemp());
759 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
764 case aco_opcode::p_extract_vector
: { /* mov */
765 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
767 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
768 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size()) { /* TODO: what about 64bit or other combinations? */
770 /* convert this extract into a mov instruction */
771 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
772 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
773 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
774 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
775 instr
->opcode
= opcode
;
776 instr
->format
= format
;
777 instr
->operands
= {instr
->operands
.begin(), 1 };
778 instr
->operands
[0] = vec_op
;
780 if (vec_op
.isConstant()) {
781 if (vec_op
.isLiteral())
782 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
784 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
786 assert(vec_op
.isTemp());
787 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
792 case aco_opcode::s_mov_b32
: /* propagate */
793 case aco_opcode::s_mov_b64
:
794 case aco_opcode::v_mov_b32
:
795 case aco_opcode::p_as_uniform
:
796 if (instr
->definitions
[0].isFixed()) {
797 /* don't copy-propagate copies into fixed registers */
798 } else if (instr
->operands
[0].isConstant()) {
799 if (instr
->operands
[0].isLiteral())
800 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
802 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
803 } else if (instr
->isDPP()) {
805 } else if (instr
->operands
[0].isTemp()) {
806 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
808 assert(instr
->operands
[0].isFixed());
811 case aco_opcode::p_is_helper
:
812 if (!ctx
.program
->needs_wqm
)
813 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
815 case aco_opcode::s_movk_i32
: {
816 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
817 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
818 if (v
<= 64 || v
>= 0xfffffff0)
819 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
821 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
824 case aco_opcode::v_bfrev_b32
:
825 case aco_opcode::s_brev_b32
: {
826 if (instr
->operands
[0].isConstant()) {
827 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
828 if (v
<= 64 || v
>= 0xfffffff0)
829 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
831 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
835 case aco_opcode::s_bfm_b32
: {
836 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
837 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
838 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
839 uint32_t v
= ((1u << size
) - 1u) << start
;
840 if (v
<= 64 || v
>= 0xfffffff0)
841 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
843 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
846 case aco_opcode::v_mul_f32
: { /* omod */
847 /* TODO: try to move the negate/abs modifier to the consumer instead */
848 if (instr
->isVOP3()) {
849 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
850 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->neg
[0] || vop3
->neg
[1] || vop3
->omod
|| vop3
->clamp
)
854 for (unsigned i
= 0; i
< 2; i
++) {
855 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
856 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
857 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2();
858 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
859 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4();
860 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
861 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5();
862 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000) { /* 1.0 */
863 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
872 case aco_opcode::v_and_b32
: /* abs */
873 if (instr
->operands
[0].constantEquals(0x7FFFFFFF) && instr
->operands
[1].isTemp())
874 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
876 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
878 case aco_opcode::v_xor_b32
: { /* neg */
879 if (instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
880 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
881 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
883 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
884 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
885 instr
->opcode
= aco_opcode::v_or_b32
;
886 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
888 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
892 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
896 case aco_opcode::v_med3_f32
: { /* clamp */
897 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
898 if (vop3
->abs
[0] || vop3
->neg
[0] || vop3
->opsel
[0] ||
899 vop3
->abs
[1] || vop3
->neg
[1] || vop3
->opsel
[1] ||
900 vop3
->abs
[2] || vop3
->neg
[2] || vop3
->opsel
[2] ||
905 bool found_zero
= false, found_one
= false;
906 for (unsigned i
= 0; i
< 3; i
++)
908 if (instr
->operands
[i
].constantEquals(0))
910 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
915 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
916 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp();
920 case aco_opcode::v_cndmask_b32
:
921 if (instr
->operands
[0].constantEquals(0) &&
922 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
923 instr
->operands
[2].isTemp())
924 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
925 else if (instr
->operands
[0].constantEquals(0) &&
926 instr
->operands
[1].constantEquals(0x3f800000u
) &&
927 instr
->operands
[2].isTemp())
928 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
930 case aco_opcode::v_cmp_lg_u32
:
931 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
932 instr
->operands
[0].constantEquals(0) &&
933 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
934 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
936 case aco_opcode::p_phi
:
937 case aco_opcode::p_linear_phi
: {
938 /* lower_bool_phis() can create phis like this */
939 bool all_same_temp
= instr
->operands
[0].isTemp();
940 /* this check is needed when moving uniform loop counters out of a divergent loop */
942 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
943 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
944 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
945 all_same_temp
= false;
948 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
950 bool all_undef
= instr
->operands
[0].isUndefined();
951 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
952 if (!instr
->operands
[i
].isUndefined())
956 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
960 case aco_opcode::v_add_u32
:
961 case aco_opcode::v_add_co_u32
:
962 case aco_opcode::s_add_i32
:
963 case aco_opcode::s_add_u32
:
964 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
966 case aco_opcode::s_not_b32
:
967 case aco_opcode::s_not_b64
:
968 case aco_opcode::s_and_b32
:
969 case aco_opcode::s_and_b64
:
970 case aco_opcode::s_or_b32
:
971 case aco_opcode::s_or_b64
:
972 case aco_opcode::s_xor_b32
:
973 case aco_opcode::s_xor_b64
:
974 case aco_opcode::s_lshl_b32
:
975 case aco_opcode::v_or_b32
:
976 case aco_opcode::v_lshlrev_b32
:
977 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
979 case aco_opcode::v_min_f32
:
980 case aco_opcode::v_min_f16
:
981 case aco_opcode::v_min_u32
:
982 case aco_opcode::v_min_i32
:
983 case aco_opcode::v_min_u16
:
984 case aco_opcode::v_min_i16
:
985 case aco_opcode::v_max_f32
:
986 case aco_opcode::v_max_f16
:
987 case aco_opcode::v_max_u32
:
988 case aco_opcode::v_max_i32
:
989 case aco_opcode::v_max_u16
:
990 case aco_opcode::v_max_i16
:
991 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
993 case aco_opcode::v_cmp_lt_f32
:
994 case aco_opcode::v_cmp_eq_f32
:
995 case aco_opcode::v_cmp_le_f32
:
996 case aco_opcode::v_cmp_gt_f32
:
997 case aco_opcode::v_cmp_lg_f32
:
998 case aco_opcode::v_cmp_ge_f32
:
999 case aco_opcode::v_cmp_o_f32
:
1000 case aco_opcode::v_cmp_u_f32
:
1001 case aco_opcode::v_cmp_nge_f32
:
1002 case aco_opcode::v_cmp_nlg_f32
:
1003 case aco_opcode::v_cmp_ngt_f32
:
1004 case aco_opcode::v_cmp_nle_f32
:
1005 case aco_opcode::v_cmp_neq_f32
:
1006 case aco_opcode::v_cmp_nlt_f32
:
1007 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1014 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1016 *ordered
= *unordered
= op
;
1018 #define CMP(ord, unord) \
1019 case aco_opcode::v_cmp_##ord##_f32:\
1020 case aco_opcode::v_cmp_n##unord##_f32:\
1021 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1022 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1023 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1037 aco_opcode
get_ordered(aco_opcode op
)
1039 aco_opcode ordered
, unordered
, inverse
;
1040 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1043 aco_opcode
get_unordered(aco_opcode op
)
1045 aco_opcode ordered
, unordered
, inverse
;
1046 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1049 aco_opcode
get_inverse(aco_opcode op
)
1051 aco_opcode ordered
, unordered
, inverse
;
1052 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1055 bool is_cmp(aco_opcode op
)
1057 aco_opcode ordered
, unordered
, inverse
;
1058 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1061 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1063 if (ctx
.info
[tmp
.id()].is_temp())
1064 return ctx
.info
[tmp
.id()].temp
.id();
1069 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1071 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1072 for (const Operand
& op
: instr
->operands
) {
1074 ctx
.uses
[op
.tempId()]--;
1079 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1081 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1083 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1086 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1088 if (instr
->definitions
.size() == 2) {
1089 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1090 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1097 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1098 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1099 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1101 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1103 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1106 bool neg
[2] = {false, false};
1107 bool abs
[2] = {false, false};
1108 bool opsel
[2] = {false, false};
1109 Instruction
*op_instr
[2];
1112 for (unsigned i
= 0; i
< 2; i
++) {
1113 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1117 aco_opcode expected_cmp
= instr
->opcode
== aco_opcode::s_or_b64
?
1118 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1120 if (op_instr
[i
]->opcode
!= expected_cmp
)
1122 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1125 if (op_instr
[i
]->isVOP3()) {
1126 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1127 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
[0] != vop3
->opsel
[1])
1129 neg
[i
] = vop3
->neg
[0];
1130 abs
[i
] = vop3
->abs
[0];
1131 opsel
[i
] = vop3
->opsel
[0];
1134 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1135 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1136 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1138 /* shouldn't happen yet, but best to be safe */
1139 if (op1
.type() != RegType::vgpr
)
1145 ctx
.uses
[op
[0].id()]++;
1146 ctx
.uses
[op
[1].id()]++;
1147 decrease_uses(ctx
, op_instr
[0]);
1148 decrease_uses(ctx
, op_instr
[1]);
1150 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1151 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1152 Instruction
*new_instr
;
1153 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
[0] || opsel
[1]) {
1154 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1155 for (unsigned i
= 0; i
< 2; i
++) {
1156 vop3
->neg
[i
] = neg
[i
];
1157 vop3
->abs
[i
] = abs
[i
];
1158 vop3
->opsel
[i
] = opsel
[i
];
1160 new_instr
= static_cast<Instruction
*>(vop3
);
1162 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1164 new_instr
->operands
[0] = Operand(op
[0]);
1165 new_instr
->operands
[1] = Operand(op
[1]);
1166 new_instr
->definitions
[0] = instr
->definitions
[0];
1168 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1169 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1171 instr
.reset(new_instr
);
1176 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1177 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1178 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1180 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1182 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1185 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1186 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1188 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1189 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1190 if (!nan_test
|| !cmp
)
1193 if (cmp
->opcode
== expected_nan_test
)
1194 std::swap(nan_test
, cmp
);
1195 else if (nan_test
->opcode
!= expected_nan_test
)
1198 if (!is_cmp(cmp
->opcode
))
1201 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1203 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1206 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1207 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1208 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1209 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1210 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1212 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1215 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1216 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1217 decrease_uses(ctx
, nan_test
);
1218 decrease_uses(ctx
, cmp
);
1220 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1221 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1222 Instruction
*new_instr
;
1223 if (cmp
->isVOP3()) {
1224 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1225 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1226 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1227 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1228 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1229 new_vop3
->clamp
= cmp_vop3
->clamp
;
1230 new_vop3
->omod
= cmp_vop3
->omod
;
1231 new_instr
= new_vop3
;
1233 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1235 new_instr
->operands
[0] = cmp
->operands
[0];
1236 new_instr
->operands
[1] = cmp
->operands
[1];
1237 new_instr
->definitions
[0] = instr
->definitions
[0];
1239 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1240 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1242 instr
.reset(new_instr
);
1247 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1248 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1249 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1251 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1253 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1256 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1257 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1259 if (!nan_test
|| !cmp
)
1262 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1263 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1264 if (cmp
->opcode
== expected_nan_test
)
1265 std::swap(nan_test
, cmp
);
1266 else if (nan_test
->opcode
!= expected_nan_test
)
1269 if (!is_cmp(cmp
->opcode
))
1272 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1274 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1277 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1278 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1279 if (prop_nan0
!= prop_nan1
)
1282 int constant_operand
= -1;
1283 for (unsigned i
= 0; i
< 2; i
++) {
1284 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1285 constant_operand
= !i
;
1289 if (constant_operand
== -1)
1293 if (cmp
->operands
[constant_operand
].isConstant()) {
1294 constant
= cmp
->operands
[constant_operand
].constantValue();
1295 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1296 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1297 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1299 constant
= ctx
.info
[id
].val
;
1305 memcpy(&constantf
, &constant
, 4);
1306 if (isnan(constantf
))
1309 if (cmp
->operands
[0].isTemp())
1310 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1311 if (cmp
->operands
[1].isTemp())
1312 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1313 decrease_uses(ctx
, nan_test
);
1314 decrease_uses(ctx
, cmp
);
1316 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1317 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1318 Instruction
*new_instr
;
1319 if (cmp
->isVOP3()) {
1320 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1321 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1322 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1323 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1324 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1325 new_vop3
->clamp
= cmp_vop3
->clamp
;
1326 new_vop3
->omod
= cmp_vop3
->omod
;
1327 new_instr
= new_vop3
;
1329 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1331 new_instr
->operands
[0] = cmp
->operands
[0];
1332 new_instr
->operands
[1] = cmp
->operands
[1];
1333 new_instr
->definitions
[0] = instr
->definitions
[0];
1335 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1336 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1338 instr
.reset(new_instr
);
1343 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1344 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1346 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1348 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1350 if (!instr
->operands
[0].isTemp())
1353 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1357 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1358 if (new_opcode
== aco_opcode::last_opcode
)
1361 if (cmp
->operands
[0].isTemp())
1362 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1363 if (cmp
->operands
[1].isTemp())
1364 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1365 decrease_uses(ctx
, cmp
);
1367 Instruction
*new_instr
;
1368 if (cmp
->isVOP3()) {
1369 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1370 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1371 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1372 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1373 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1374 new_vop3
->clamp
= cmp_vop3
->clamp
;
1375 new_vop3
->omod
= cmp_vop3
->omod
;
1376 new_instr
= new_vop3
;
1378 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1380 new_instr
->operands
[0] = cmp
->operands
[0];
1381 new_instr
->operands
[1] = cmp
->operands
[1];
1382 new_instr
->definitions
[0] = instr
->definitions
[0];
1384 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1385 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1387 instr
.reset(new_instr
);
1392 /* op1(op2(1, 2), 0) if swap = false
1393 * op1(0, op2(1, 2)) if swap = true */
1394 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1395 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1396 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1397 bool *op1_clamp
, unsigned *op1_omod
,
1398 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1401 if (op1_instr
->opcode
!= op1
)
1404 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1405 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1408 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1409 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1411 /* don't support inbetween clamp/omod */
1412 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1415 /* get operands and modifiers and check inbetween modifiers */
1416 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1417 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1420 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1421 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1425 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1426 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1429 if (inbetween_opsel
)
1430 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
[swap
] : false;
1431 else if (op1_vop3
&& op1_vop3
->opsel
[swap
])
1435 shuffle
[shuffle_str
[0] - '0'] = 0;
1436 shuffle
[shuffle_str
[1] - '0'] = 1;
1437 shuffle
[shuffle_str
[2] - '0'] = 2;
1439 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1440 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1441 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1442 opsel
[shuffle
[0]] = op1_vop3
? op1_vop3
->opsel
[!swap
] : false;
1444 for (unsigned i
= 0; i
< 2; i
++) {
1445 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1446 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1447 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1448 opsel
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->opsel
[i
] : false;
1451 /* check operands */
1452 unsigned sgpr_id
= 0;
1453 for (unsigned i
= 0; i
< 3; i
++) {
1454 Operand op
= operands
[i
];
1455 if (op
.isLiteral()) {
1457 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1458 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1460 sgpr_id
= op
.tempId();
1467 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1468 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1469 bool clamp
, unsigned omod
)
1471 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1472 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1473 memcpy(new_instr
->opsel
, opsel
, sizeof(bool[3]));
1474 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1475 new_instr
->clamp
= clamp
;
1476 new_instr
->omod
= omod
;
1477 new_instr
->operands
[0] = operands
[0];
1478 new_instr
->operands
[1] = operands
[1];
1479 new_instr
->operands
[2] = operands
[2];
1480 new_instr
->definitions
[0] = instr
->definitions
[0];
1481 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1483 instr
.reset(new_instr
);
1486 bool combine_minmax3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
)
1488 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1489 (label_omod_success
| label_clamp_success
);
1491 for (unsigned swap
= 0; swap
< 2; swap
++) {
1492 Operand operands
[3];
1493 bool neg
[3], abs
[3], opsel
[3], clamp
, inbetween_neg
, inbetween_abs
;
1495 if (match_op3_for_vop3(ctx
, instr
->opcode
, instr
->opcode
, instr
.get(), swap
,
1496 "012", operands
, neg
, abs
, opsel
,
1497 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1498 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1499 neg
[1] ^= inbetween_neg
;
1500 neg
[2] ^= inbetween_neg
;
1501 abs
[1] |= inbetween_abs
;
1502 abs
[2] |= inbetween_abs
;
1503 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1504 if (omod_clamp
& label_omod_success
)
1505 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1506 if (omod_clamp
& label_clamp_success
)
1507 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1514 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1516 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1517 (label_omod_success
| label_clamp_success
);
1519 for (unsigned swap
= 0; swap
< 2; swap
++) {
1520 if (!((1 << swap
) & ops
))
1523 Operand operands
[3];
1524 bool neg
[3], abs
[3], opsel
[3], clamp
;
1526 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1527 instr
.get(), swap
, shuffle
,
1528 operands
, neg
, abs
, opsel
,
1529 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1530 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1531 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1532 if (omod_clamp
& label_omod_success
)
1533 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1534 if (omod_clamp
& label_clamp_success
)
1535 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1542 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1543 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1544 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1545 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1546 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1547 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1548 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1551 if (!instr
->operands
[0].isTemp())
1553 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1556 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1559 switch (op2_instr
->opcode
) {
1560 case aco_opcode::s_and_b32
:
1561 case aco_opcode::s_or_b32
:
1562 case aco_opcode::s_xor_b32
:
1563 case aco_opcode::s_and_b64
:
1564 case aco_opcode::s_or_b64
:
1565 case aco_opcode::s_xor_b64
:
1571 /* create instruction */
1572 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1573 ctx
.uses
[instr
->operands
[0].tempId()]--;
1574 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1576 switch (op2_instr
->opcode
) {
1577 case aco_opcode::s_and_b32
:
1578 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1580 case aco_opcode::s_or_b32
:
1581 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1583 case aco_opcode::s_xor_b32
:
1584 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1586 case aco_opcode::s_and_b64
:
1587 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1589 case aco_opcode::s_or_b64
:
1590 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1592 case aco_opcode::s_xor_b64
:
1593 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1602 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1603 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1604 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1605 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1606 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1608 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1611 for (unsigned i
= 0; i
< 2; i
++) {
1612 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1613 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1616 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1617 instr
->operands
[0] = instr
->operands
[!i
];
1618 instr
->operands
[1] = op2_instr
->operands
[0];
1619 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1621 switch (instr
->opcode
) {
1622 case aco_opcode::s_and_b32
:
1623 instr
->opcode
= aco_opcode::s_andn2_b32
;
1625 case aco_opcode::s_or_b32
:
1626 instr
->opcode
= aco_opcode::s_orn2_b32
;
1628 case aco_opcode::s_and_b64
:
1629 instr
->opcode
= aco_opcode::s_andn2_b64
;
1631 case aco_opcode::s_or_b64
:
1632 instr
->opcode
= aco_opcode::s_orn2_b64
;
1643 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1644 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1646 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1649 for (unsigned i
= 0; i
< 2; i
++) {
1650 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1651 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1654 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1655 if (shift
< 1 || shift
> 4)
1658 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1659 instr
->operands
[1] = instr
->operands
[!i
];
1660 instr
->operands
[0] = op2_instr
->operands
[0];
1661 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1663 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1664 aco_opcode::s_lshl2_add_u32
,
1665 aco_opcode::s_lshl3_add_u32
,
1666 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1673 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1676 #define MINMAX(type, gfx9) \
1677 case aco_opcode::v_min_##type:\
1678 case aco_opcode::v_max_##type:\
1679 case aco_opcode::v_med3_##type:\
1680 *min = aco_opcode::v_min_##type;\
1681 *max = aco_opcode::v_max_##type;\
1682 *med3 = aco_opcode::v_med3_##type;\
1683 *min3 = aco_opcode::v_min3_##type;\
1684 *max3 = aco_opcode::v_max3_##type;\
1685 *some_gfx9_only = gfx9;\
1699 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1700 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1701 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1702 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1704 aco_opcode other_op
;
1705 if (instr
->opcode
== min
)
1707 else if (instr
->opcode
== max
)
1712 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1713 (label_omod_success
| label_clamp_success
);
1715 for (unsigned swap
= 0; swap
< 2; swap
++) {
1716 Operand operands
[3];
1717 bool neg
[3], abs
[3], opsel
[3], clamp
, inbetween_neg
, inbetween_abs
;
1719 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1720 "012", operands
, neg
, abs
, opsel
,
1721 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1722 int const0_idx
= -1, const1_idx
= -1;
1723 uint32_t const0
= 0, const1
= 0;
1724 for (int i
= 0; i
< 3; i
++) {
1726 if (operands
[i
].isConstant()) {
1727 val
= operands
[i
].constantValue();
1728 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1729 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1730 val
= ctx
.info
[operands
[i
].tempId()].val
;
1734 if (const0_idx
>= 0) {
1742 if (const0_idx
< 0 || const1_idx
< 0)
1745 if (opsel
[const0_idx
])
1747 if (opsel
[const1_idx
])
1750 int lower_idx
= const0_idx
;
1752 case aco_opcode::v_min_f32
:
1753 case aco_opcode::v_min_f16
: {
1754 float const0_f
, const1_f
;
1755 if (min
== aco_opcode::v_min_f32
) {
1756 memcpy(&const0_f
, &const0
, 4);
1757 memcpy(&const1_f
, &const1
, 4);
1759 const0_f
= _mesa_half_to_float(const0
);
1760 const1_f
= _mesa_half_to_float(const1
);
1762 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1763 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1764 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1765 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1766 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1769 case aco_opcode::v_min_u32
: {
1770 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1773 case aco_opcode::v_min_u16
: {
1774 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1777 case aco_opcode::v_min_i32
: {
1778 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1779 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1780 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1783 case aco_opcode::v_min_i16
: {
1784 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1785 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1786 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1792 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1794 if (instr
->opcode
== min
) {
1795 if (upper_idx
!= 0 || lower_idx
== 0)
1798 if (upper_idx
== 0 || lower_idx
!= 0)
1802 neg
[1] ^= inbetween_neg
;
1803 neg
[2] ^= inbetween_neg
;
1804 abs
[1] |= inbetween_abs
;
1805 abs
[2] |= inbetween_abs
;
1807 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1808 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1809 if (omod_clamp
& label_omod_success
)
1810 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1811 if (omod_clamp
& label_clamp_success
)
1812 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1822 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1825 uint32_t sgpr_idx
= 0;
1826 uint32_t sgpr_info_id
= 0;
1827 bool has_sgpr
= false;
1828 uint32_t sgpr_ssa_id
= 0;
1829 /* find 'best' possible sgpr */
1830 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
1832 if (instr
->operands
[i
].isLiteral()) {
1836 if (!instr
->operands
[i
].isTemp())
1838 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1840 sgpr_ssa_id
= instr
->operands
[i
].tempId();
1843 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1844 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
1845 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1846 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1848 sgpr_info_id
= instr
->operands
[i
].tempId();
1852 if (!has_sgpr
&& sgpr_info_id
!= 0) {
1853 ssa_info
& info
= ctx
.info
[sgpr_info_id
];
1854 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1855 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1856 ctx
.uses
[sgpr_info_id
]--;
1857 ctx
.uses
[info
.temp
.id()]++;
1858 } else if (can_swap_operands(instr
)) {
1859 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1860 instr
->operands
[0] = Operand(info
.temp
);
1861 ctx
.uses
[sgpr_info_id
]--;
1862 ctx
.uses
[info
.temp
.id()]++;
1863 } else if (can_use_VOP3(instr
)) {
1864 to_VOP3(ctx
, instr
);
1865 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1866 ctx
.uses
[sgpr_info_id
]--;
1867 ctx
.uses
[info
.temp
.id()]++;
1870 /* we can have two sgprs on one instruction if it is the same sgpr! */
1871 } else if (sgpr_info_id
!= 0 &&
1872 sgpr_ssa_id
== sgpr_info_id
&&
1873 ctx
.uses
[sgpr_info_id
] == 1 &&
1874 can_use_VOP3(instr
)) {
1875 to_VOP3(ctx
, instr
);
1876 instr
->operands
[sgpr_idx
] = Operand(ctx
.info
[sgpr_info_id
].temp
);
1877 ctx
.uses
[sgpr_info_id
]--;
1878 ctx
.uses
[ctx
.info
[sgpr_info_id
].temp
.id()]++;
1882 bool apply_omod_clamp(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1884 /* check if we could apply omod on predecessor */
1885 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1886 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success()) {
1888 /* omod was successfully applied */
1889 /* if the omod instruction is v_mad, we also have to change the original add */
1890 if (ctx
.info
[instr
->operands
[1].tempId()].is_mad()) {
1891 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[1].tempId()].val
].add_instr
.get();
1892 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1893 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1894 add_instr
->definitions
[0] = instr
->definitions
[0];
1897 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
1898 /* check if we have an additional clamp modifier */
1899 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1) {
1900 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1901 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1903 /* change definition ssa-id of modified instruction */
1904 omod_instr
->definitions
[0] = instr
->definitions
[0];
1906 /* change the definition of instr to something unused, e.g. the original omod def */
1907 instr
->definitions
[0] = Definition(instr
->operands
[1].getTemp());
1908 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1911 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1912 /* in all other cases, label this instruction as option for multiply-add */
1913 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1917 /* check if we could apply clamp on predecessor */
1918 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1920 bool found_zero
= false, found_one
= false;
1921 for (unsigned i
= 0; i
< 3; i
++)
1923 if (instr
->operands
[i
].constantEquals(0))
1925 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1930 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1931 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1932 /* clamp was successfully applied */
1933 /* if the clamp instruction is v_mad, we also have to change the original add */
1934 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1935 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1936 add_instr
->definitions
[0] = instr
->definitions
[0];
1938 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1939 /* change definition ssa-id of modified instruction */
1940 clamp_instr
->definitions
[0] = instr
->definitions
[0];
1942 /* change the definition of instr to something unused, e.g. the original omod def */
1943 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1944 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1949 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
1950 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1951 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
1952 if(ctx
.info
[instr
->definitions
[0].tempId()].is_omod2()) {
1953 to_VOP3(ctx
, instr
);
1954 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
1955 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1956 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_omod4()) {
1957 to_VOP3(ctx
, instr
);
1958 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
1959 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1960 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_omod5()) {
1961 to_VOP3(ctx
, instr
);
1962 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
1963 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1964 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp()) {
1965 to_VOP3(ctx
, instr
);
1966 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
1967 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1974 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
1975 // this would mean that we'd have to fix the instruction uses while value propagation
1977 void combine_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1979 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
1982 if (instr
->isVALU()) {
1983 if (can_apply_sgprs(instr
))
1984 apply_sgprs(ctx
, instr
);
1985 if (apply_omod_clamp(ctx
, instr
))
1989 /* TODO: There are still some peephole optimizations that could be done:
1990 * - abs(a - b) -> s_absdiff_i32
1991 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
1992 * - patterns for v_alignbit_b32 and v_alignbyte_b32
1993 * These aren't probably too interesting though.
1994 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
1995 * probably more useful than the previously mentioned optimizations.
1996 * The various comparison optimizations also currently only work with 32-bit
1999 /* neg(mul(a, b)) -> mul(neg(a), b) */
2000 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2001 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2003 if (!ctx
.info
[val
.id()].is_mul())
2006 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2008 if (mul_instr
->operands
[0].isLiteral())
2010 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2013 /* convert to mul(neg(a), b) */
2014 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2015 Definition def
= instr
->definitions
[0];
2016 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2017 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2018 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2019 instr
->operands
[0] = mul_instr
->operands
[0];
2020 instr
->operands
[1] = mul_instr
->operands
[1];
2021 instr
->definitions
[0] = def
;
2022 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2023 if (mul_instr
->isVOP3()) {
2024 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2025 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2026 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2027 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2028 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2029 new_mul
->omod
= mul
->omod
;
2031 new_mul
->neg
[0] ^= true;
2032 new_mul
->clamp
= false;
2034 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2037 /* combine mul+add -> mad */
2038 else if (instr
->opcode
== aco_opcode::v_add_f32
||
2039 instr
->opcode
== aco_opcode::v_sub_f32
||
2040 instr
->opcode
== aco_opcode::v_subrev_f32
) {
2042 uint32_t uses_src0
= UINT32_MAX
;
2043 uint32_t uses_src1
= UINT32_MAX
;
2044 Instruction
* mul_instr
= nullptr;
2045 unsigned add_op_idx
;
2046 /* check if any of the operands is a multiplication */
2047 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2048 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2049 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2050 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2052 /* find the 'best' mul instruction to combine with the add */
2053 if (uses_src0
< uses_src1
) {
2054 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2056 } else if (uses_src1
< uses_src0
) {
2057 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2059 } else if (uses_src0
!= UINT32_MAX
) {
2060 /* tiebreaker: quite random what to pick */
2061 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2062 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2065 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2070 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2071 bool neg
[3] = {false, false, false};
2072 bool abs
[3] = {false, false, false};
2075 bool need_vop3
= false;
2077 op
[0] = mul_instr
->operands
[0];
2078 op
[1] = mul_instr
->operands
[1];
2079 op
[2] = instr
->operands
[add_op_idx
];
2080 for (unsigned i
= 0; i
< 3; i
++)
2082 if (op
[i
].isLiteral())
2084 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
)
2086 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2089 // TODO: would be better to check this before selecting a mul instr?
2093 if (mul_instr
->isVOP3()) {
2094 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2095 neg
[0] = vop3
->neg
[0];
2096 neg
[1] = vop3
->neg
[1];
2097 abs
[0] = vop3
->abs
[0];
2098 abs
[1] = vop3
->abs
[1];
2100 /* we cannot use these modifiers between mul and add */
2101 if (vop3
->clamp
|| vop3
->omod
)
2105 /* convert to mad */
2106 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2107 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2109 ctx
.uses
[op
[0].tempId()]++;
2111 ctx
.uses
[op
[1].tempId()]++;
2114 if (instr
->isVOP3()) {
2115 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2116 neg
[2] = vop3
->neg
[add_op_idx
];
2117 abs
[2] = vop3
->abs
[add_op_idx
];
2119 clamp
= vop3
->clamp
;
2120 /* abs of the multiplication result */
2121 if (vop3
->abs
[1 - add_op_idx
]) {
2127 /* neg of the multiplication result */
2128 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2131 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2132 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2134 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2135 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2139 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2140 for (unsigned i
= 0; i
< 3; i
++)
2142 mad
->operands
[i
] = op
[i
];
2143 mad
->neg
[i
] = neg
[i
];
2144 mad
->abs
[i
] = abs
[i
];
2148 mad
->definitions
[0] = instr
->definitions
[0];
2150 /* mark this ssa_def to be re-checked for profitability and literals */
2151 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2152 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2153 instr
.reset(mad
.release());
2157 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2158 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2159 for (unsigned i
= 0; i
< 2; i
++) {
2160 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2161 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2162 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2163 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2164 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2166 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2167 new_instr
->operands
[0] = Operand(0u);
2168 new_instr
->operands
[1] = instr
->operands
[!i
];
2169 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2170 new_instr
->definitions
[0] = instr
->definitions
[0];
2171 instr
.reset(new_instr
.release());
2172 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2176 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2177 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2178 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2179 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2180 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2181 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2182 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2183 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2184 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2185 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2186 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2187 combine_salu_lshl_add(ctx
, instr
);
2188 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2189 combine_salu_not_bitwise(ctx
, instr
);
2190 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2191 if (combine_inverse_comparison(ctx
, instr
)) ;
2192 else combine_salu_not_bitwise(ctx
, instr
);
2193 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
) {
2194 combine_salu_n2(ctx
, instr
);
2195 } else if (instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2196 if (combine_ordering_test(ctx
, instr
)) ;
2197 else if (combine_comparison_ordering(ctx
, instr
)) ;
2198 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2199 else combine_salu_n2(ctx
, instr
);
2201 aco_opcode min
, max
, min3
, max3
, med3
;
2202 bool some_gfx9_only
;
2203 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2204 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2205 if (combine_minmax3(ctx
, instr
, instr
->opcode
== min
? min3
: max3
)) ;
2206 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2212 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2214 const uint32_t threshold
= 4;
2216 /* Dead Code Elimination:
2217 * We remove instructions if they define temporaries which all are unused */
2218 const bool is_used
= instr
->definitions
.empty() ||
2219 std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
2220 [&ctx
](const Definition
& def
) { return ctx
.uses
[def
.tempId()]; });
2226 /* convert split_vector into extract_vector if only one definition is ever used */
2227 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2228 unsigned num_used
= 0;
2230 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2231 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2236 if (num_used
== 1) {
2237 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2238 extract
->operands
[0] = instr
->operands
[0];
2239 extract
->operands
[1] = Operand((uint32_t) idx
);
2240 extract
->definitions
[0] = instr
->definitions
[idx
];
2241 instr
.reset(extract
.release());
2245 /* re-check mad instructions */
2246 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2247 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2248 /* first, check profitability */
2249 if (ctx
.uses
[info
->mul_temp_id
]) {
2250 ctx
.uses
[info
->mul_temp_id
]++;
2251 instr
.swap(info
->add_instr
);
2253 /* second, check possible literals */
2254 } else if (!info
->needs_vop3
) {
2255 uint32_t literal_idx
= 0;
2256 uint32_t literal_uses
= UINT32_MAX
;
2257 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2259 if (!instr
->operands
[i
].isTemp())
2261 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2262 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2263 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2264 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2267 literal_uses
= UINT32_MAX
;
2271 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2272 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2273 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2277 if (literal_uses
< threshold
) {
2278 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2279 info
->check_literal
= true;
2280 info
->literal_idx
= literal_idx
;
2286 /* check for literals */
2287 /* we do not apply the literals yet as we don't know if it is profitable */
2288 if (instr
->isSALU()) {
2289 uint32_t literal_idx
= 0;
2290 uint32_t literal_uses
= UINT32_MAX
;
2291 bool has_literal
= false;
2292 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2294 if (instr
->operands
[i
].isLiteral()) {
2298 if (!instr
->operands
[i
].isTemp())
2300 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2301 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2302 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2306 if (!has_literal
&& literal_uses
< threshold
) {
2307 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2308 if (ctx
.uses
[instr
->operands
[literal_idx
].tempId()] == 0)
2309 instr
->operands
[literal_idx
] = Operand(ctx
.info
[instr
->operands
[literal_idx
].tempId()].val
);
2311 } else if (instr
->isVALU() && valu_can_accept_literal(ctx
, instr
, 0) &&
2312 instr
->operands
[0].isTemp() &&
2313 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2314 ctx
.uses
[instr
->operands
[0].tempId()] < threshold
) {
2315 ctx
.uses
[instr
->operands
[0].tempId()]--;
2316 if (ctx
.uses
[instr
->operands
[0].tempId()] == 0)
2317 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2323 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2325 /* Cleanup Dead Instructions */
2329 /* apply literals on SALU */
2330 if (instr
->isSALU()) {
2331 for (Operand
& op
: instr
->operands
) {
2336 if (ctx
.info
[op
.tempId()].is_literal() &&
2337 ctx
.uses
[op
.tempId()] == 0)
2338 op
= Operand(ctx
.info
[op
.tempId()].val
);
2342 /* apply literals on VALU */
2343 else if (instr
->isVALU() && !instr
->isVOP3() &&
2344 instr
->operands
[0].isTemp() &&
2345 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2346 ctx
.uses
[instr
->operands
[0].tempId()] == 0) {
2347 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2350 /* apply literals on MAD */
2351 else if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2352 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2353 aco_ptr
<Instruction
> new_mad
;
2354 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2355 if (info
->literal_idx
== 2) { /* add literal -> madak */
2356 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2357 new_mad
->operands
[0] = instr
->operands
[0];
2358 new_mad
->operands
[1] = instr
->operands
[1];
2359 } else { /* mul literal -> madmk */
2360 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2361 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2362 new_mad
->operands
[1] = instr
->operands
[2];
2364 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2365 new_mad
->definitions
[0] = instr
->definitions
[0];
2366 instr
.swap(new_mad
);
2370 ctx
.instructions
.emplace_back(std::move(instr
));
2374 void optimize(Program
* program
)
2377 ctx
.program
= program
;
2378 std::vector
<ssa_info
> info(program
->peekAllocationId());
2379 ctx
.info
= info
.data();
2381 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2382 for (Block
& block
: program
->blocks
) {
2383 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2384 label_instruction(ctx
, instr
);
2387 ctx
.uses
= std::move(dead_code_analysis(program
));
2389 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2390 for (Block
& block
: program
->blocks
) {
2391 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2392 combine_instruction(ctx
, instr
);
2395 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2396 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2397 Block
* block
= &(*it
);
2398 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2399 select_instruction(ctx
, *it
);
2402 /* 4. Add literals to instructions */
2403 for (Block
& block
: program
->blocks
) {
2404 ctx
.instructions
.clear();
2405 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2406 apply_literals(ctx
, instr
);
2407 block
.instructions
.swap(ctx
.instructions
);