2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant_32bit
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
94 label_constant_16bit
= 1 << 29,
97 static constexpr uint64_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
98 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_vopc
;
99 static constexpr uint64_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
100 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
101 static constexpr uint32_t val_labels
= label_constant_32bit
| label_constant_64bit
| label_constant_16bit
| label_literal
;
111 ssa_info() : label(0) {}
113 void add_label(Label new_label
)
115 /* Since all labels which use "instr" use it for the same thing
116 * (indicating the defining instruction), there is no need to clear
117 * any other instr labels. */
118 if (new_label
& instr_labels
)
119 label
&= ~(temp_labels
| val_labels
); /* instr, temp and val alias */
121 if (new_label
& temp_labels
) {
122 label
&= ~temp_labels
;
123 label
&= ~(instr_labels
| val_labels
); /* instr, temp and val alias */
126 uint32_t const_labels
= label_literal
| label_constant_32bit
| label_constant_64bit
| label_constant_16bit
;
127 if (new_label
& const_labels
) {
128 label
&= ~val_labels
| const_labels
;
129 label
&= ~(instr_labels
| temp_labels
); /* instr, temp and val alias */
130 } else if (new_label
& val_labels
) {
131 label
&= ~val_labels
;
132 label
&= ~(instr_labels
| temp_labels
); /* instr, temp and val alias */
138 void set_vec(Instruction
* vec
)
140 add_label(label_vec
);
146 return label
& label_vec
;
149 void set_constant(chip_class chip
, uint64_t constant
)
151 Operand
op16((uint16_t)constant
);
152 Operand
op32((uint32_t)constant
);
153 add_label(label_literal
);
156 if (chip
>= GFX8
&& !op16
.isLiteral())
157 add_label(label_constant_16bit
);
159 if (!op32
.isLiteral() || ((uint32_t)constant
== 0x3e22f983 && chip
>= GFX8
))
160 add_label(label_constant_32bit
);
162 if (constant
<= 64) {
163 add_label(label_constant_64bit
);
164 } else if (constant
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
165 add_label(label_constant_64bit
);
166 } else if (constant
== 0x3FE0000000000000) { /* 0.5 */
167 add_label(label_constant_64bit
);
168 } else if (constant
== 0xBFE0000000000000) { /* -0.5 */
169 add_label(label_constant_64bit
);
170 } else if (constant
== 0x3FF0000000000000) { /* 1.0 */
171 add_label(label_constant_64bit
);
172 } else if (constant
== 0xBFF0000000000000) { /* -1.0 */
173 add_label(label_constant_64bit
);
174 } else if (constant
== 0x4000000000000000) { /* 2.0 */
175 add_label(label_constant_64bit
);
176 } else if (constant
== 0xC000000000000000) { /* -2.0 */
177 add_label(label_constant_64bit
);
178 } else if (constant
== 0x4010000000000000) { /* 4.0 */
179 add_label(label_constant_64bit
);
180 } else if (constant
== 0xC010000000000000) { /* -4.0 */
181 add_label(label_constant_64bit
);
184 if (label
& label_constant_64bit
) {
185 val
= Operand(constant
).constantValue();
187 label
&= ~(label_literal
| label_constant_16bit
| label_constant_32bit
);
191 bool is_constant(unsigned bits
)
195 return label
& label_literal
;
197 return label
& label_constant_16bit
;
199 return label
& label_constant_32bit
;
201 return label
& label_constant_64bit
;
206 bool is_literal(unsigned bits
)
208 bool is_lit
= label
& label_literal
;
213 return is_lit
&& ~(label
& label_constant_16bit
);
215 return is_lit
&& ~(label
& label_constant_32bit
);
222 bool is_constant_or_literal(unsigned bits
)
225 return label
& label_constant_64bit
;
227 return label
& label_literal
;
230 void set_abs(Temp abs_temp
)
232 add_label(label_abs
);
238 return label
& label_abs
;
241 void set_neg(Temp neg_temp
)
243 add_label(label_neg
);
249 return label
& label_neg
;
252 void set_neg_abs(Temp neg_abs_temp
)
254 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
258 void set_mul(Instruction
* mul
)
260 add_label(label_mul
);
266 return label
& label_mul
;
269 void set_temp(Temp tmp
)
271 add_label(label_temp
);
277 return label
& label_temp
;
280 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
282 add_label(label_mad
);
283 mad
->pass_flags
= mad_info_idx
;
289 return label
& label_mad
;
292 void set_omod2(Temp def
)
294 add_label(label_omod2
);
300 return label
& label_omod2
;
303 void set_omod4(Temp def
)
305 add_label(label_omod4
);
311 return label
& label_omod4
;
314 void set_omod5(Temp def
)
316 add_label(label_omod5
);
322 return label
& label_omod5
;
325 void set_omod_success(Instruction
* omod_instr
)
327 add_label(label_omod_success
);
331 bool is_omod_success()
333 return label
& label_omod_success
;
336 void set_clamp(Temp def
)
338 add_label(label_clamp
);
344 return label
& label_clamp
;
347 void set_clamp_success(Instruction
* clamp_instr
)
349 add_label(label_clamp_success
);
353 bool is_clamp_success()
355 return label
& label_clamp_success
;
360 add_label(label_undefined
);
365 return label
& label_undefined
;
368 void set_vcc(Temp vcc
)
370 add_label(label_vcc
);
376 return label
& label_vcc
;
379 void set_b2f(Temp val
)
381 add_label(label_b2f
);
387 return label
& label_b2f
;
390 void set_add_sub(Instruction
*add_sub_instr
)
392 add_label(label_add_sub
);
393 instr
= add_sub_instr
;
398 return label
& label_add_sub
;
401 void set_bitwise(Instruction
*bitwise_instr
)
403 add_label(label_bitwise
);
404 instr
= bitwise_instr
;
409 return label
& label_bitwise
;
412 void set_uniform_bitwise()
414 add_label(label_uniform_bitwise
);
417 bool is_uniform_bitwise()
419 return label
& label_uniform_bitwise
;
422 void set_minmax(Instruction
*minmax_instr
)
424 add_label(label_minmax
);
425 instr
= minmax_instr
;
430 return label
& label_minmax
;
433 void set_vopc(Instruction
*vopc_instr
)
435 add_label(label_vopc
);
441 return label
& label_vopc
;
444 void set_scc_needed()
446 add_label(label_scc_needed
);
451 return label
& label_scc_needed
;
454 void set_scc_invert(Temp scc_inv
)
456 add_label(label_scc_invert
);
462 return label
& label_scc_invert
;
465 void set_uniform_bool(Temp uniform_bool
)
467 add_label(label_uniform_bool
);
471 bool is_uniform_bool()
473 return label
& label_uniform_bool
;
478 add_label(label_vcc_hint
);
483 return label
& label_vcc_hint
;
486 void set_b2i(Temp val
)
488 add_label(label_b2i
);
494 return label
& label_b2i
;
501 std::vector
<aco_ptr
<Instruction
>> instructions
;
503 std::pair
<uint32_t,Temp
> last_literal
;
504 std::vector
<mad_info
> mad_infos
;
505 std::vector
<uint16_t> uses
;
510 aco_opcode unordered
;
511 aco_opcode ordered_swapped
;
512 aco_opcode unordered_swapped
;
518 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
);
520 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
522 if (instr
->operands
[0].isConstant() ||
523 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
526 switch (instr
->opcode
) {
527 case aco_opcode::v_add_u32
:
528 case aco_opcode::v_add_co_u32
:
529 case aco_opcode::v_add_co_u32_e64
:
530 case aco_opcode::v_add_i32
:
531 case aco_opcode::v_add_f16
:
532 case aco_opcode::v_add_f32
:
533 case aco_opcode::v_mul_f16
:
534 case aco_opcode::v_mul_f32
:
535 case aco_opcode::v_or_b32
:
536 case aco_opcode::v_and_b32
:
537 case aco_opcode::v_xor_b32
:
538 case aco_opcode::v_max_f16
:
539 case aco_opcode::v_max_f32
:
540 case aco_opcode::v_min_f16
:
541 case aco_opcode::v_min_f32
:
542 case aco_opcode::v_max_i32
:
543 case aco_opcode::v_min_i32
:
544 case aco_opcode::v_max_u32
:
545 case aco_opcode::v_min_u32
:
546 case aco_opcode::v_max_i16
:
547 case aco_opcode::v_min_i16
:
548 case aco_opcode::v_max_u16
:
549 case aco_opcode::v_min_u16
:
550 case aco_opcode::v_max_i16_e64
:
551 case aco_opcode::v_min_i16_e64
:
552 case aco_opcode::v_max_u16_e64
:
553 case aco_opcode::v_min_u16_e64
:
555 case aco_opcode::v_sub_f16
:
556 instr
->opcode
= aco_opcode::v_subrev_f16
;
558 case aco_opcode::v_sub_f32
:
559 instr
->opcode
= aco_opcode::v_subrev_f32
;
561 case aco_opcode::v_sub_co_u32
:
562 instr
->opcode
= aco_opcode::v_subrev_co_u32
;
564 case aco_opcode::v_sub_u16
:
565 instr
->opcode
= aco_opcode::v_subrev_u16
;
567 case aco_opcode::v_sub_u32
:
568 instr
->opcode
= aco_opcode::v_subrev_u32
;
572 get_cmp_info(instr
->opcode
, &info
);
573 if (info
.ordered
== instr
->opcode
) {
574 instr
->opcode
= info
.ordered_swapped
;
577 if (info
.unordered
== instr
->opcode
) {
578 instr
->opcode
= info
.unordered_swapped
;
586 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
591 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
594 if (instr
->isDPP() || instr
->isSDWA())
597 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
598 instr
->opcode
!= aco_opcode::v_madak_f32
&&
599 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
600 instr
->opcode
!= aco_opcode::v_madak_f16
&&
601 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
602 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
603 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
604 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
605 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
606 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
607 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
610 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
612 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
613 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
614 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
615 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
616 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
619 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
624 aco_ptr
<Instruction
> tmp
= std::move(instr
);
625 Format format
= asVOP3(tmp
->format
);
626 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
627 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
628 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
629 instr
->definitions
[i
] = tmp
->definitions
[i
];
630 if (instr
->definitions
[i
].isTemp()) {
631 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
632 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
633 info
.instr
= instr
.get();
638 /* only covers special cases */
639 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
642 case aco_opcode::v_interp_p2_f32
:
643 case aco_opcode::v_mac_f32
:
644 case aco_opcode::v_writelane_b32
:
645 case aco_opcode::v_writelane_b32_e64
:
646 case aco_opcode::v_cndmask_b32
:
648 case aco_opcode::s_addk_i32
:
649 case aco_opcode::s_mulk_i32
:
650 case aco_opcode::p_wqm
:
651 case aco_opcode::p_extract_vector
:
652 case aco_opcode::p_split_vector
:
653 case aco_opcode::v_readlane_b32
:
654 case aco_opcode::v_readlane_b32_e64
:
655 case aco_opcode::v_readfirstlane_b32
:
662 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
664 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
665 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
670 /* check constant bus and literal limitations */
671 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
673 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
674 Operand
literal32(s1
);
675 Operand
literal64(s2
);
676 unsigned num_sgprs
= 0;
677 unsigned sgpr
[] = {0, 0};
679 for (unsigned i
= 0; i
< num_operands
; i
++) {
680 Operand op
= operands
[i
];
682 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
683 /* two reads of the same SGPR count as 1 to the limit */
684 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
686 sgpr
[num_sgprs
++] = op
.tempId();
691 } else if (op
.isLiteral()) {
692 if (ctx
.program
->chip_class
< GFX10
)
695 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
697 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
700 /* Any number of 32-bit literals counts as only 1 to the limit. Same
701 * (but separately) for 64-bit literals. */
702 if (op
.size() == 1 && literal32
.isUndefined()) {
705 } else if (op
.size() == 2 && literal64
.isUndefined()) {
718 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
, bool prevent_overflow
)
720 Operand op
= instr
->operands
[op_index
];
724 Temp tmp
= op
.getTemp();
725 if (!ctx
.info
[tmp
.id()].is_add_sub())
728 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
730 switch (add_instr
->opcode
) {
731 case aco_opcode::v_add_u32
:
732 case aco_opcode::v_add_co_u32
:
733 case aco_opcode::v_add_co_u32_e64
:
734 case aco_opcode::s_add_i32
:
735 case aco_opcode::s_add_u32
:
740 if (prevent_overflow
&& !add_instr
->definitions
[0].isNUW())
743 if (add_instr
->usesModifiers())
746 for (unsigned i
= 0; i
< 2; i
++) {
747 if (add_instr
->operands
[i
].isConstant()) {
748 *offset
= add_instr
->operands
[i
].constantValue();
749 } else if (add_instr
->operands
[i
].isTemp() &&
750 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal(32)) {
751 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
755 if (!add_instr
->operands
[!i
].isTemp())
758 uint32_t offset2
= 0;
759 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
, prevent_overflow
)) {
762 *base
= add_instr
->operands
[!i
].getTemp();
770 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
772 if (instr
->format
== Format::PSEUDO
)
773 return instr
->operands
[index
].bytes() * 8u;
774 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
775 return index
== 2 ? 64 : 32;
776 else if (instr
->isVALU() || instr
->isSALU())
777 return instr_info
.operand_size
[(int)instr
->opcode
];
782 Operand
get_constant_op(opt_ctx
&ctx
, ssa_info info
, uint32_t bits
)
785 return Operand((uint8_t)info
.val
);
787 return Operand((uint16_t)info
.val
);
788 // TODO: this functions shouldn't be needed if we store Operand instead of value.
789 Operand
op(info
.val
, bits
== 64);
790 if (info
.is_literal(32) && info
.val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
791 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
795 bool fixed_to_exec(Operand op
)
797 return op
.isFixed() && op
.physReg() == exec
;
800 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
802 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
803 ASSERTED
bool all_const
= false;
804 for (Operand
& op
: instr
->operands
)
805 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal(32));
806 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
809 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
811 if (!instr
->operands
[i
].isTemp())
814 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
815 /* propagate undef */
816 if (info
.is_undefined() && is_phi(instr
))
817 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
818 /* propagate reg->reg of same type */
819 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
820 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
821 info
= ctx
.info
[info
.temp
.id()];
824 /* SALU / PSEUDO: propagate inline constants */
825 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
826 bool is_subdword
= false;
827 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
828 if (instr
->format
== Format::PSEUDO
) {
829 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
830 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
831 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
832 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
833 if (is_subdword
&& ctx
.program
->chip_class
< GFX9
)
837 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
838 instr
->operands
[i
].setTemp(info
.temp
);
839 info
= ctx
.info
[info
.temp
.id()];
840 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
841 /* propagate vgpr if it can take it */
842 switch (instr
->opcode
) {
843 case aco_opcode::p_create_vector
:
844 case aco_opcode::p_split_vector
:
845 case aco_opcode::p_extract_vector
:
846 case aco_opcode::p_phi
: {
847 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
848 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
850 instr
->operands
[i
] = Operand(info
.temp
);
851 info
= ctx
.info
[info
.temp
.id()];
859 unsigned bits
= get_operand_size(instr
, i
);
860 if ((info
.is_constant(bits
) || (!is_subdword
&& info
.is_literal(bits
) && instr
->format
== Format::PSEUDO
)) &&
861 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
862 instr
->operands
[i
] = get_constant_op(ctx
, info
, bits
);
867 /* VALU: propagate neg, abs & inline constants */
868 else if (instr
->isVALU()) {
869 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
870 instr
->operands
[i
].setTemp(info
.temp
);
871 info
= ctx
.info
[info
.temp
.id()];
874 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
875 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
876 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
878 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
881 instr
->operands
[i
] = Operand(info
.temp
);
883 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
885 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
887 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
888 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
889 instr
->operands
[i
].setTemp(info
.temp
);
891 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
892 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
893 instr
->operands
[i
].setTemp(info
.temp
);
895 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
898 instr
->operands
[i
].setTemp(info
.temp
);
900 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
902 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
905 unsigned bits
= get_operand_size(instr
, i
);
906 if (info
.is_constant(bits
) && alu_can_accept_constant(instr
->opcode
, i
)) {
907 Operand op
= get_constant_op(ctx
, info
, bits
);
908 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
909 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
910 instr
->operands
[i
] = op
;
912 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
913 instr
->operands
[i
] = instr
->operands
[0];
914 instr
->operands
[0] = op
;
916 } else if (can_use_VOP3(ctx
, instr
)) {
918 instr
->operands
[i
] = op
;
924 /* MUBUF: propagate constants and combine additions */
925 else if (instr
->format
== Format::MUBUF
) {
926 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
929 while (info
.is_temp())
930 info
= ctx
.info
[info
.temp
.id()];
932 /* According to AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(), vaddr
933 * overflow for scratch accesses works only on GFX9+ and saddr overflow
934 * never works. Since swizzling is the only thing that separates
935 * scratch accesses and other accesses and swizzling changing how
936 * addressing works significantly, this probably applies to swizzled
938 bool vaddr_prevent_overflow
= mubuf
->swizzled
&& ctx
.program
->chip_class
< GFX9
;
939 bool saddr_prevent_overflow
= mubuf
->swizzled
;
941 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
942 assert(!mubuf
->idxen
);
943 instr
->operands
[1] = Operand(v1
);
944 mubuf
->offset
+= info
.val
;
945 mubuf
->offen
= false;
947 } else if (i
== 2 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
948 instr
->operands
[2] = Operand((uint32_t) 0);
949 mubuf
->offset
+= info
.val
;
951 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
, vaddr_prevent_overflow
) &&
952 base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
953 assert(!mubuf
->idxen
);
954 instr
->operands
[1].setTemp(base
);
955 mubuf
->offset
+= offset
;
957 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
, saddr_prevent_overflow
) &&
958 base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
959 instr
->operands
[i
].setTemp(base
);
960 mubuf
->offset
+= offset
;
965 /* DS: combine additions */
966 else if (instr
->format
== Format::DS
) {
968 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
971 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
972 if (has_usable_ds_offset
&&
973 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
, false) &&
974 base
.regClass() == instr
->operands
[i
].regClass() &&
975 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
976 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
977 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
978 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
979 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
981 if ((offset
& mask
) == 0 &&
982 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
983 ds
->offset1
+ (offset
>> shifts
) <= 255) {
984 instr
->operands
[i
].setTemp(base
);
985 ds
->offset0
+= offset
>> shifts
;
986 ds
->offset1
+= offset
>> shifts
;
989 if (ds
->offset0
+ offset
<= 65535) {
990 instr
->operands
[i
].setTemp(base
);
991 ds
->offset0
+= offset
;
997 /* SMEM: propagate constants and combine additions */
998 else if (instr
->format
== Format::SMEM
) {
1000 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
1003 bool prevent_overflow
= smem
->operands
[0].size() > 2 || smem
->prevent_overflow
;
1004 if (i
== 1 && info
.is_constant_or_literal(32) &&
1005 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
1006 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
1007 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
1008 instr
->operands
[i
] = Operand(info
.val
);
1010 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
, prevent_overflow
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
1011 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
1013 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal(32) ||
1014 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
1018 smem
->operands
[1] = Operand(offset
);
1019 smem
->operands
.back() = Operand(base
);
1021 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
1022 new_instr
->operands
[0] = smem
->operands
[0];
1023 new_instr
->operands
[1] = Operand(offset
);
1024 if (smem
->definitions
.empty())
1025 new_instr
->operands
[2] = smem
->operands
[2];
1026 new_instr
->operands
.back() = Operand(base
);
1027 if (!smem
->definitions
.empty())
1028 new_instr
->definitions
[0] = smem
->definitions
[0];
1029 new_instr
->sync
= smem
->sync
;
1030 new_instr
->glc
= smem
->glc
;
1031 new_instr
->dlc
= smem
->dlc
;
1032 new_instr
->nv
= smem
->nv
;
1033 new_instr
->disable_wqm
= smem
->disable_wqm
;
1034 instr
.reset(new_instr
);
1035 smem
= static_cast<SMEM_instruction
*>(instr
.get());
1041 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
1042 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1043 /* Flip the branch instruction to get rid of the scc_invert instruction */
1044 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
1045 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1050 /* if this instruction doesn't define anything, return */
1051 if (instr
->definitions
.empty())
1054 if ((uint16_t) instr
->format
& (uint16_t) Format::VOPC
) {
1055 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(instr
.get());
1059 switch (instr
->opcode
) {
1060 case aco_opcode::p_create_vector
: {
1061 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
1062 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
1064 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1068 unsigned num_ops
= instr
->operands
.size();
1069 for (const Operand
& op
: instr
->operands
) {
1070 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
1071 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
1073 if (num_ops
!= instr
->operands
.size()) {
1074 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
1075 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
1076 instr
->definitions
[0] = old_vec
->definitions
[0];
1078 for (Operand
& old_op
: old_vec
->operands
) {
1079 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
1080 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
1081 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
1082 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
1083 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
1084 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
1085 instr
->operands
[k
++] = op
;
1088 instr
->operands
[k
++] = old_op
;
1091 assert(k
== num_ops
);
1094 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
1097 case aco_opcode::p_split_vector
: {
1098 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1100 if (info
.is_constant_or_literal(32)) {
1101 uint32_t val
= info
.val
;
1102 for (Definition def
: instr
->definitions
) {
1103 uint32_t mask
= u_bit_consecutive(0, def
.bytes() * 8u);
1104 ctx
.info
[def
.tempId()].set_constant(ctx
.program
->chip_class
, val
& mask
);
1105 val
>>= def
.bytes() * 8u;
1108 } else if (!info
.is_vec()) {
1112 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1113 unsigned split_offset
= 0;
1114 unsigned vec_offset
= 0;
1115 unsigned vec_index
= 0;
1116 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
1117 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
1118 vec_offset
+= vec
->operands
[vec_index
++].bytes();
1120 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
1123 Operand vec_op
= vec
->operands
[vec_index
];
1124 if (vec_op
.isConstant()) {
1125 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(ctx
.program
->chip_class
, vec_op
.constantValue64());
1126 } else if (vec_op
.isUndefined()) {
1127 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1129 assert(vec_op
.isTemp());
1130 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1135 case aco_opcode::p_extract_vector
: { /* mov */
1136 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1137 const unsigned index
= instr
->operands
[1].constantValue();
1138 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1140 if (info
.is_constant_or_literal(32)) {
1141 uint32_t mask
= u_bit_consecutive(0, instr
->definitions
[0].bytes() * 8u);
1142 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, (info
.val
>> (dst_offset
* 8u)) & mask
);
1144 } else if (!info
.is_vec()) {
1148 /* check if we index directly into a vector element */
1149 Instruction
* vec
= info
.instr
;
1150 unsigned offset
= 0;
1152 for (const Operand
& op
: vec
->operands
) {
1153 if (offset
< dst_offset
) {
1154 offset
+= op
.bytes();
1156 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1160 /* convert this extract into a copy instruction */
1161 instr
->opcode
= aco_opcode::p_parallelcopy
;
1162 instr
->operands
.pop_back();
1163 instr
->operands
[0] = op
;
1165 if (op
.isConstant()) {
1166 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, op
.constantValue64());
1167 } else if (op
.isUndefined()) {
1168 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1170 assert(op
.isTemp());
1171 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1177 case aco_opcode::s_mov_b32
: /* propagate */
1178 case aco_opcode::s_mov_b64
:
1179 case aco_opcode::v_mov_b32
:
1180 case aco_opcode::p_as_uniform
:
1181 if (instr
->definitions
[0].isFixed()) {
1182 /* don't copy-propagate copies into fixed registers */
1183 } else if (instr
->usesModifiers()) {
1185 } else if (instr
->operands
[0].isConstant()) {
1186 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, instr
->operands
[0].constantValue64());
1187 } else if (instr
->operands
[0].isTemp()) {
1188 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1190 assert(instr
->operands
[0].isFixed());
1193 case aco_opcode::p_is_helper
:
1194 if (!ctx
.program
->needs_wqm
)
1195 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, 0u);
1197 case aco_opcode::s_movk_i32
: {
1198 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1199 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1200 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1203 case aco_opcode::v_bfrev_b32
:
1204 case aco_opcode::s_brev_b32
: {
1205 if (instr
->operands
[0].isConstant()) {
1206 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1207 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1211 case aco_opcode::s_bfm_b32
: {
1212 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1213 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1214 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1215 uint32_t v
= ((1u << size
) - 1u) << start
;
1216 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1220 case aco_opcode::v_mul_f16
:
1221 case aco_opcode::v_mul_f32
: { /* omod */
1222 /* TODO: try to move the negate/abs modifier to the consumer instead */
1223 if (instr
->usesModifiers())
1226 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1228 for (unsigned i
= 0; i
< 2; i
++) {
1229 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1230 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1231 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1232 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1233 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1234 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1235 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1236 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1237 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1238 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1247 case aco_opcode::v_and_b32
: { /* abs */
1248 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1249 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1250 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1251 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1252 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1254 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1257 case aco_opcode::v_xor_b32
: { /* neg */
1258 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1259 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1260 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1261 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1262 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1263 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1264 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1265 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1266 instr
->opcode
= aco_opcode::v_or_b32
;
1267 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1269 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1273 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1277 case aco_opcode::v_med3_f16
:
1278 case aco_opcode::v_med3_f32
: { /* clamp */
1279 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1280 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1281 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1282 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1286 bool found_zero
= false, found_one
= false;
1287 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1288 for (unsigned i
= 0; i
< 3; i
++)
1290 if (instr
->operands
[i
].constantEquals(0))
1292 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1297 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1298 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1302 case aco_opcode::v_cndmask_b32
:
1303 if (instr
->operands
[0].constantEquals(0) &&
1304 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1305 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1306 else if (instr
->operands
[0].constantEquals(0) &&
1307 instr
->operands
[1].constantEquals(0x3f800000u
))
1308 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1309 else if (instr
->operands
[0].constantEquals(0) &&
1310 instr
->operands
[1].constantEquals(1))
1311 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1313 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1315 case aco_opcode::v_cmp_lg_u32
:
1316 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1317 instr
->operands
[0].constantEquals(0) &&
1318 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1319 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1321 case aco_opcode::p_phi
:
1322 case aco_opcode::p_linear_phi
: {
1323 /* lower_bool_phis() can create phis like this */
1324 bool all_same_temp
= instr
->operands
[0].isTemp();
1325 /* this check is needed when moving uniform loop counters out of a divergent loop */
1327 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1328 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1329 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1330 all_same_temp
= false;
1332 if (all_same_temp
) {
1333 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1335 bool all_undef
= instr
->operands
[0].isUndefined();
1336 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1337 if (!instr
->operands
[i
].isUndefined())
1341 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1345 case aco_opcode::v_add_u32
:
1346 case aco_opcode::v_add_co_u32
:
1347 case aco_opcode::v_add_co_u32_e64
:
1348 case aco_opcode::s_add_i32
:
1349 case aco_opcode::s_add_u32
:
1350 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1352 case aco_opcode::s_not_b32
:
1353 case aco_opcode::s_not_b64
:
1354 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1355 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1356 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1357 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1358 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1359 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1361 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1363 case aco_opcode::s_and_b32
:
1364 case aco_opcode::s_and_b64
:
1365 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1366 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1367 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1368 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1369 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1371 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1372 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1373 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1374 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1376 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_vopc()) {
1377 Instruction
* vopc_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1378 /* Remove superfluous s_and when the VOPC instruction uses the same exec and thus already produces the same result */
1379 if (vopc_instr
->pass_flags
== instr
->pass_flags
) {
1380 assert(instr
->pass_flags
> 0);
1381 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vopc_instr
->definitions
[0].getTemp());
1387 case aco_opcode::s_or_b32
:
1388 case aco_opcode::s_or_b64
:
1389 case aco_opcode::s_xor_b32
:
1390 case aco_opcode::s_xor_b64
:
1391 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1392 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1394 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1397 case aco_opcode::s_lshl_b32
:
1398 case aco_opcode::v_or_b32
:
1399 case aco_opcode::v_lshlrev_b32
:
1400 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1402 case aco_opcode::v_min_f32
:
1403 case aco_opcode::v_min_f16
:
1404 case aco_opcode::v_min_u32
:
1405 case aco_opcode::v_min_i32
:
1406 case aco_opcode::v_min_u16
:
1407 case aco_opcode::v_min_i16
:
1408 case aco_opcode::v_max_f32
:
1409 case aco_opcode::v_max_f16
:
1410 case aco_opcode::v_max_u32
:
1411 case aco_opcode::v_max_i32
:
1412 case aco_opcode::v_max_u16
:
1413 case aco_opcode::v_max_i16
:
1414 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1416 case aco_opcode::s_cselect_b64
:
1417 case aco_opcode::s_cselect_b32
:
1418 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1419 instr
->operands
[1].constantEquals(0)) {
1420 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1421 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1423 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1424 /* Flip the operands to get rid of the scc_invert instruction */
1425 std::swap(instr
->operands
[0], instr
->operands
[1]);
1426 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1429 case aco_opcode::p_wqm
:
1430 if (instr
->operands
[0].isTemp() &&
1431 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1432 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1440 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
)
1442 info
->ordered
= aco_opcode::num_opcodes
;
1443 info
->unordered
= aco_opcode::num_opcodes
;
1444 info
->ordered_swapped
= aco_opcode::num_opcodes
;
1445 info
->unordered_swapped
= aco_opcode::num_opcodes
;
1447 #define CMP2(ord, unord, ord_swap, unord_swap, sz) \
1448 case aco_opcode::v_cmp_##ord##_f##sz:\
1449 case aco_opcode::v_cmp_n##unord##_f##sz:\
1450 info->ordered = aco_opcode::v_cmp_##ord##_f##sz;\
1451 info->unordered = aco_opcode::v_cmp_n##unord##_f##sz;\
1452 info->ordered_swapped = aco_opcode::v_cmp_##ord_swap##_f##sz;\
1453 info->unordered_swapped = aco_opcode::v_cmp_n##unord_swap##_f##sz;\
1454 info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz : aco_opcode::v_cmp_n##ord##_f##sz;\
1455 info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 : aco_opcode::v_cmp_n##unord##_f32;\
1458 #define CMP(ord, unord, ord_swap, unord_swap) \
1459 CMP2(ord, unord, ord_swap, unord_swap, 16)\
1460 CMP2(ord, unord, ord_swap, unord_swap, 32)\
1461 CMP2(ord, unord, ord_swap, unord_swap, 64)
1462 CMP(lt
, /*n*/ge
, gt
, /*n*/le
)
1463 CMP(eq
, /*n*/lg
, eq
, /*n*/lg
)
1464 CMP(le
, /*n*/gt
, ge
, /*n*/lt
)
1465 CMP(gt
, /*n*/le
, lt
, /*n*/le
)
1466 CMP(lg
, /*n*/eq
, lg
, /*n*/eq
)
1467 CMP(ge
, /*n*/lt
, le
, /*n*/gt
)
1470 #define ORD_TEST(sz) \
1471 case aco_opcode::v_cmp_u_f##sz:\
1472 info->f32 = aco_opcode::v_cmp_u_f32;\
1473 info->inverse = aco_opcode::v_cmp_o_f##sz;\
1476 case aco_opcode::v_cmp_o_f##sz:\
1477 info->f32 = aco_opcode::v_cmp_o_f32;\
1478 info->inverse = aco_opcode::v_cmp_u_f##sz;\
1490 aco_opcode
get_ordered(aco_opcode op
)
1493 return get_cmp_info(op
, &info
) ? info
.ordered
: aco_opcode::num_opcodes
;
1496 aco_opcode
get_unordered(aco_opcode op
)
1499 return get_cmp_info(op
, &info
) ? info
.unordered
: aco_opcode::num_opcodes
;
1502 aco_opcode
get_inverse(aco_opcode op
)
1505 return get_cmp_info(op
, &info
) ? info
.inverse
: aco_opcode::num_opcodes
;
1508 aco_opcode
get_f32_cmp(aco_opcode op
)
1511 return get_cmp_info(op
, &info
) ? info
.f32
: aco_opcode::num_opcodes
;
1514 unsigned get_cmp_bitsize(aco_opcode op
)
1517 return get_cmp_info(op
, &info
) ? info
.size
: 0;
1520 bool is_cmp(aco_opcode op
)
1523 return get_cmp_info(op
, &info
) && info
.ordered
!= aco_opcode::num_opcodes
;
1526 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1528 if (ctx
.info
[tmp
.id()].is_temp())
1529 return ctx
.info
[tmp
.id()].temp
.id();
1534 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1536 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1537 for (const Operand
& op
: instr
->operands
) {
1539 ctx
.uses
[op
.tempId()]--;
1544 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1546 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1548 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1551 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1553 if (instr
->definitions
.size() == 2) {
1554 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1555 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1562 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1563 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1564 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1566 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1568 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1571 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1573 bool neg
[2] = {false, false};
1574 bool abs
[2] = {false, false};
1576 Instruction
*op_instr
[2];
1579 unsigned bitsize
= 0;
1580 for (unsigned i
= 0; i
< 2; i
++) {
1581 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1585 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1586 unsigned op_bitsize
= get_cmp_bitsize(op_instr
[i
]->opcode
);
1588 if (get_f32_cmp(op_instr
[i
]->opcode
) != expected_cmp
)
1590 if (bitsize
&& op_bitsize
!= bitsize
)
1592 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1595 if (op_instr
[i
]->isVOP3()) {
1596 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1597 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1599 neg
[i
] = vop3
->neg
[0];
1600 abs
[i
] = vop3
->abs
[0];
1601 opsel
|= (vop3
->opsel
& 1) << i
;
1604 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1605 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1606 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1610 bitsize
= op_bitsize
;
1613 if (op
[1].type() == RegType::sgpr
)
1614 std::swap(op
[0], op
[1]);
1615 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1616 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1619 ctx
.uses
[op
[0].id()]++;
1620 ctx
.uses
[op
[1].id()]++;
1621 decrease_uses(ctx
, op_instr
[0]);
1622 decrease_uses(ctx
, op_instr
[1]);
1624 aco_opcode new_op
= aco_opcode::num_opcodes
;
1627 new_op
= is_or
? aco_opcode::v_cmp_u_f16
: aco_opcode::v_cmp_o_f16
;
1630 new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1633 new_op
= is_or
? aco_opcode::v_cmp_u_f64
: aco_opcode::v_cmp_o_f64
;
1636 Instruction
*new_instr
;
1637 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1638 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1639 for (unsigned i
= 0; i
< 2; i
++) {
1640 vop3
->neg
[i
] = neg
[i
];
1641 vop3
->abs
[i
] = abs
[i
];
1643 vop3
->opsel
= opsel
;
1644 new_instr
= static_cast<Instruction
*>(vop3
);
1646 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1648 new_instr
->operands
[0] = Operand(op
[0]);
1649 new_instr
->operands
[1] = Operand(op
[1]);
1650 new_instr
->definitions
[0] = instr
->definitions
[0];
1652 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1653 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1655 instr
.reset(new_instr
);
1660 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1661 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1662 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1664 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1666 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1669 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1670 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1672 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1673 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1674 if (!nan_test
|| !cmp
)
1677 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1678 std::swap(nan_test
, cmp
);
1679 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1682 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1685 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1687 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1690 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1691 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1692 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1693 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1694 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1696 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1699 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1700 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1701 decrease_uses(ctx
, nan_test
);
1702 decrease_uses(ctx
, cmp
);
1704 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1705 Instruction
*new_instr
;
1706 if (cmp
->isVOP3()) {
1707 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1708 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1709 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1710 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1711 new_vop3
->clamp
= cmp_vop3
->clamp
;
1712 new_vop3
->omod
= cmp_vop3
->omod
;
1713 new_vop3
->opsel
= cmp_vop3
->opsel
;
1714 new_instr
= new_vop3
;
1716 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1718 new_instr
->operands
[0] = cmp
->operands
[0];
1719 new_instr
->operands
[1] = cmp
->operands
[1];
1720 new_instr
->definitions
[0] = instr
->definitions
[0];
1722 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1723 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1725 instr
.reset(new_instr
);
1730 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1731 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1732 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1734 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1736 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1739 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1741 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1742 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1744 if (!nan_test
|| !cmp
)
1747 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1748 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1749 std::swap(nan_test
, cmp
);
1750 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1753 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1756 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1758 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1761 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1762 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1763 if (prop_nan0
!= prop_nan1
)
1766 if (nan_test
->isVOP3()) {
1767 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1768 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1772 int constant_operand
= -1;
1773 for (unsigned i
= 0; i
< 2; i
++) {
1774 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1775 constant_operand
= !i
;
1779 if (constant_operand
== -1)
1783 if (cmp
->operands
[constant_operand
].isConstant()) {
1784 constant
= cmp
->operands
[constant_operand
].constantValue();
1785 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1786 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1787 unsigned id
= original_temp_id(ctx
, tmp
);
1788 if (!ctx
.info
[id
].is_constant_or_literal(32))
1790 constant
= ctx
.info
[id
].val
;
1796 memcpy(&constantf
, &constant
, 4);
1797 if (isnan(constantf
))
1800 if (cmp
->operands
[0].isTemp())
1801 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1802 if (cmp
->operands
[1].isTemp())
1803 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1804 decrease_uses(ctx
, nan_test
);
1805 decrease_uses(ctx
, cmp
);
1807 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1808 Instruction
*new_instr
;
1809 if (cmp
->isVOP3()) {
1810 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1811 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1812 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1813 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1814 new_vop3
->clamp
= cmp_vop3
->clamp
;
1815 new_vop3
->omod
= cmp_vop3
->omod
;
1816 new_vop3
->opsel
= cmp_vop3
->opsel
;
1817 new_instr
= new_vop3
;
1819 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1821 new_instr
->operands
[0] = cmp
->operands
[0];
1822 new_instr
->operands
[1] = cmp
->operands
[1];
1823 new_instr
->definitions
[0] = instr
->definitions
[0];
1825 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1826 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1828 instr
.reset(new_instr
);
1833 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1834 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1836 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1838 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1840 if (!instr
->operands
[0].isTemp())
1843 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1847 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1848 if (new_opcode
== aco_opcode::num_opcodes
)
1851 if (cmp
->operands
[0].isTemp())
1852 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1853 if (cmp
->operands
[1].isTemp())
1854 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1855 decrease_uses(ctx
, cmp
);
1857 Instruction
*new_instr
;
1858 if (cmp
->isVOP3()) {
1859 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1860 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1861 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1862 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1863 new_vop3
->clamp
= cmp_vop3
->clamp
;
1864 new_vop3
->omod
= cmp_vop3
->omod
;
1865 new_vop3
->opsel
= cmp_vop3
->opsel
;
1866 new_instr
= new_vop3
;
1868 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1870 new_instr
->operands
[0] = cmp
->operands
[0];
1871 new_instr
->operands
[1] = cmp
->operands
[1];
1872 new_instr
->definitions
[0] = instr
->definitions
[0];
1874 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1875 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1877 instr
.reset(new_instr
);
1882 /* op1(op2(1, 2), 0) if swap = false
1883 * op1(0, op2(1, 2)) if swap = true */
1884 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1885 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1886 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1887 bool *op1_clamp
, uint8_t *op1_omod
,
1888 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1891 if (op1_instr
->opcode
!= op1
)
1894 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1895 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1897 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1900 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1901 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1903 /* don't support inbetween clamp/omod */
1904 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1907 /* get operands and modifiers and check inbetween modifiers */
1908 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1909 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1912 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1913 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1917 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1918 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1921 if (inbetween_opsel
)
1922 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1923 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1927 shuffle
[shuffle_str
[0] - '0'] = 0;
1928 shuffle
[shuffle_str
[1] - '0'] = 1;
1929 shuffle
[shuffle_str
[2] - '0'] = 2;
1931 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1932 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1933 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1934 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1935 *opsel
|= 1 << shuffle
[0];
1937 for (unsigned i
= 0; i
< 2; i
++) {
1938 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1939 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1940 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1941 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1942 *opsel
|= 1 << shuffle
[i
+ 1];
1945 /* check operands */
1946 if (!check_vop3_operands(ctx
, 3, operands
))
1952 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1953 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1954 bool clamp
, unsigned omod
)
1956 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1957 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1958 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1959 new_instr
->clamp
= clamp
;
1960 new_instr
->omod
= omod
;
1961 new_instr
->opsel
= opsel
;
1962 new_instr
->operands
[0] = operands
[0];
1963 new_instr
->operands
[1] = operands
[1];
1964 new_instr
->operands
[2] = operands
[2];
1965 new_instr
->definitions
[0] = instr
->definitions
[0];
1966 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1968 instr
.reset(new_instr
);
1971 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1973 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1974 (label_omod_success
| label_clamp_success
);
1976 for (unsigned swap
= 0; swap
< 2; swap
++) {
1977 if (!((1 << swap
) & ops
))
1980 Operand operands
[3];
1981 bool neg
[3], abs
[3], clamp
;
1982 uint8_t opsel
= 0, omod
= 0;
1983 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1984 instr
.get(), swap
, shuffle
,
1985 operands
, neg
, abs
, &opsel
,
1986 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1987 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1988 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1989 if (omod_clamp
& label_omod_success
)
1990 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1991 if (omod_clamp
& label_clamp_success
)
1992 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1999 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
2001 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
2004 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2005 (label_omod_success
| label_clamp_success
);
2007 /* min(-max(a, b), c) -> min3(-a, -b, c) *
2008 * max(-min(a, b), c) -> max3(-a, -b, c) */
2009 for (unsigned swap
= 0; swap
< 2; swap
++) {
2010 Operand operands
[3];
2011 bool neg
[3], abs
[3], clamp
;
2012 uint8_t opsel
= 0, omod
= 0;
2014 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
2015 instr
.get(), swap
, "012",
2016 operands
, neg
, abs
, &opsel
,
2017 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
2019 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2022 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2023 if (omod_clamp
& label_omod_success
)
2024 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2025 if (omod_clamp
& label_clamp_success
)
2026 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2033 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
2034 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
2035 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
2036 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
2037 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
2038 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
2039 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2042 if (!instr
->operands
[0].isTemp())
2044 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
2047 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
2050 switch (op2_instr
->opcode
) {
2051 case aco_opcode::s_and_b32
:
2052 case aco_opcode::s_or_b32
:
2053 case aco_opcode::s_xor_b32
:
2054 case aco_opcode::s_and_b64
:
2055 case aco_opcode::s_or_b64
:
2056 case aco_opcode::s_xor_b64
:
2062 /* create instruction */
2063 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
2064 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
2065 ctx
.uses
[instr
->operands
[0].tempId()]--;
2066 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
2068 switch (op2_instr
->opcode
) {
2069 case aco_opcode::s_and_b32
:
2070 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
2072 case aco_opcode::s_or_b32
:
2073 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
2075 case aco_opcode::s_xor_b32
:
2076 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
2078 case aco_opcode::s_and_b64
:
2079 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
2081 case aco_opcode::s_or_b64
:
2082 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
2084 case aco_opcode::s_xor_b64
:
2085 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
2094 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
2095 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
2096 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
2097 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
2098 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2100 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
2103 for (unsigned i
= 0; i
< 2; i
++) {
2104 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2105 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
2107 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
2110 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2111 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2114 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2115 instr
->operands
[0] = instr
->operands
[!i
];
2116 instr
->operands
[1] = op2_instr
->operands
[0];
2117 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2119 switch (instr
->opcode
) {
2120 case aco_opcode::s_and_b32
:
2121 instr
->opcode
= aco_opcode::s_andn2_b32
;
2123 case aco_opcode::s_or_b32
:
2124 instr
->opcode
= aco_opcode::s_orn2_b32
;
2126 case aco_opcode::s_and_b64
:
2127 instr
->opcode
= aco_opcode::s_andn2_b64
;
2129 case aco_opcode::s_or_b64
:
2130 instr
->opcode
= aco_opcode::s_orn2_b64
;
2141 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2142 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2144 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
2147 for (unsigned i
= 0; i
< 2; i
++) {
2148 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2149 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
2150 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
2152 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
2155 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2156 if (shift
< 1 || shift
> 4)
2159 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2160 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2163 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2164 instr
->operands
[1] = instr
->operands
[!i
];
2165 instr
->operands
[0] = op2_instr
->operands
[0];
2166 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2168 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2169 aco_opcode::s_lshl2_add_u32
,
2170 aco_opcode::s_lshl3_add_u32
,
2171 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2178 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2180 if (instr
->usesModifiers())
2183 for (unsigned i
= 0; i
< 2; i
++) {
2184 if (!((1 << i
) & ops
))
2186 if (instr
->operands
[i
].isTemp() &&
2187 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2188 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2190 aco_ptr
<Instruction
> new_instr
;
2191 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2192 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2193 } else if (ctx
.program
->chip_class
>= GFX10
||
2194 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2195 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2199 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2200 new_instr
->definitions
[0] = instr
->definitions
[0];
2201 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2202 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2203 new_instr
->definitions
[1].setHint(vcc
);
2204 new_instr
->operands
[0] = Operand(0u);
2205 new_instr
->operands
[1] = instr
->operands
[!i
];
2206 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2207 instr
= std::move(new_instr
);
2208 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2216 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2219 #define MINMAX(type, gfx9) \
2220 case aco_opcode::v_min_##type:\
2221 case aco_opcode::v_max_##type:\
2222 case aco_opcode::v_med3_##type:\
2223 *min = aco_opcode::v_min_##type;\
2224 *max = aco_opcode::v_max_##type;\
2225 *med3 = aco_opcode::v_med3_##type;\
2226 *min3 = aco_opcode::v_min3_##type;\
2227 *max3 = aco_opcode::v_max3_##type;\
2228 *some_gfx9_only = gfx9;\
2242 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2243 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2244 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2245 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2247 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2248 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2249 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2250 aco_opcode other_op
;
2251 if (instr
->opcode
== min
)
2253 else if (instr
->opcode
== max
)
2258 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2259 (label_omod_success
| label_clamp_success
);
2261 for (unsigned swap
= 0; swap
< 2; swap
++) {
2262 Operand operands
[3];
2263 bool neg
[3], abs
[3], clamp
;
2264 uint8_t opsel
= 0, omod
= 0;
2265 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2266 "012", operands
, neg
, abs
, &opsel
,
2267 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2268 int const0_idx
= -1, const1_idx
= -1;
2269 uint32_t const0
= 0, const1
= 0;
2270 for (int i
= 0; i
< 3; i
++) {
2272 if (operands
[i
].isConstant()) {
2273 val
= operands
[i
].constantValue();
2274 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal(32)) {
2275 val
= ctx
.info
[operands
[i
].tempId()].val
;
2279 if (const0_idx
>= 0) {
2287 if (const0_idx
< 0 || const1_idx
< 0)
2290 if (opsel
& (1 << const0_idx
))
2292 if (opsel
& (1 << const1_idx
))
2295 int lower_idx
= const0_idx
;
2297 case aco_opcode::v_min_f32
:
2298 case aco_opcode::v_min_f16
: {
2299 float const0_f
, const1_f
;
2300 if (min
== aco_opcode::v_min_f32
) {
2301 memcpy(&const0_f
, &const0
, 4);
2302 memcpy(&const1_f
, &const1
, 4);
2304 const0_f
= _mesa_half_to_float(const0
);
2305 const1_f
= _mesa_half_to_float(const1
);
2307 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2308 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2309 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2310 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2311 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2314 case aco_opcode::v_min_u32
: {
2315 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2318 case aco_opcode::v_min_u16
: {
2319 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2322 case aco_opcode::v_min_i32
: {
2323 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2324 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2325 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2328 case aco_opcode::v_min_i16
: {
2329 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2330 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2331 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2337 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2339 if (instr
->opcode
== min
) {
2340 if (upper_idx
!= 0 || lower_idx
== 0)
2343 if (upper_idx
== 0 || lower_idx
!= 0)
2347 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2348 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2349 if (omod_clamp
& label_omod_success
)
2350 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2351 if (omod_clamp
& label_clamp_success
)
2352 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2362 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2364 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2365 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2366 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2368 /* find candidates and create the set of sgprs already read */
2369 unsigned sgpr_ids
[2] = {0, 0};
2370 uint32_t operand_mask
= 0;
2371 bool has_literal
= false;
2372 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2373 if (instr
->operands
[i
].isLiteral())
2375 if (!instr
->operands
[i
].isTemp())
2377 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2378 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2379 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2381 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2382 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2383 operand_mask
|= 1u << i
;
2385 unsigned max_sgprs
= 1;
2386 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2391 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2393 /* keep on applying sgprs until there is nothing left to be done */
2394 while (operand_mask
) {
2395 uint32_t sgpr_idx
= 0;
2396 uint32_t sgpr_info_id
= 0;
2397 uint32_t mask
= operand_mask
;
2400 unsigned i
= u_bit_scan(&mask
);
2401 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2402 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2404 sgpr_info_id
= instr
->operands
[i
].tempId();
2407 operand_mask
&= ~(1u << sgpr_idx
);
2409 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2410 * definitively beneficial.
2411 * TODO: this is too conservative because later the use count could be reduced to 1 */
2412 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2415 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2416 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2417 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2420 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2421 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2422 } else if (can_swap_operands(instr
)) {
2423 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2424 instr
->operands
[0] = Operand(sgpr
);
2425 /* swap bits using a 4-entry LUT */
2426 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2427 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2428 } else if (can_use_VOP3(ctx
, instr
)) {
2429 to_VOP3(ctx
, instr
);
2430 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2436 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2437 ctx
.uses
[sgpr_info_id
]--;
2438 ctx
.uses
[sgpr
.id()]++;
2442 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2444 /* check if we could apply omod on predecessor */
2445 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2446 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2447 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2449 unsigned idx
= op0
? 0 : 1;
2450 /* omod was successfully applied */
2451 /* if the omod instruction is v_mad, we also have to change the original add */
2452 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2453 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].instr
->pass_flags
].add_instr
.get();
2454 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2455 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2456 add_instr
->definitions
[0] = instr
->definitions
[0];
2459 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2460 /* check if we have an additional clamp modifier */
2461 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2462 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2463 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2464 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2466 /* change definition ssa-id of modified instruction */
2467 omod_instr
->definitions
[0] = instr
->definitions
[0];
2469 /* change the definition of instr to something unused, e.g. the original omod def */
2470 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2471 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2474 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2475 /* in all other cases, label this instruction as option for multiply-add */
2476 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2480 /* check if we could apply clamp on predecessor */
2481 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2482 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2484 bool found_zero
= false, found_one
= false;
2485 for (unsigned i
= 0; i
< 3; i
++)
2487 if (instr
->operands
[i
].constantEquals(0))
2489 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2494 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2495 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2496 /* clamp was successfully applied */
2497 /* if the clamp instruction is v_mad, we also have to change the original add */
2498 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2499 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].instr
->pass_flags
].add_instr
.get();
2500 add_instr
->definitions
[0] = instr
->definitions
[0];
2502 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2503 /* change definition ssa-id of modified instruction */
2504 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2506 /* change the definition of instr to something unused, e.g. the original omod def */
2507 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2508 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2513 /* omod has no effect if denormals are enabled */
2514 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2515 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2516 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2517 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2518 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2519 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2520 to_VOP3(ctx
, instr
);
2521 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2522 def_info
.set_omod_success(instr
.get());
2523 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2524 to_VOP3(ctx
, instr
);
2525 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2526 def_info
.set_omod_success(instr
.get());
2527 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2528 to_VOP3(ctx
, instr
);
2529 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2530 def_info
.set_omod_success(instr
.get());
2531 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2532 to_VOP3(ctx
, instr
);
2533 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2534 def_info
.set_clamp_success(instr
.get());
2541 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2542 // this would mean that we'd have to fix the instruction uses while value propagation
2544 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2546 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2549 if (instr
->isVALU()) {
2550 if (can_apply_sgprs(instr
))
2551 apply_sgprs(ctx
, instr
);
2552 if (apply_omod_clamp(ctx
, block
, instr
))
2556 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2557 instr
->definitions
[0].setHint(vcc
);
2560 /* TODO: There are still some peephole optimizations that could be done:
2561 * - abs(a - b) -> s_absdiff_i32
2562 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2563 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2564 * These aren't probably too interesting though.
2565 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2566 * probably more useful than the previously mentioned optimizations.
2567 * The various comparison optimizations also currently only work with 32-bit
2570 /* neg(mul(a, b)) -> mul(neg(a), b) */
2571 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2572 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2574 if (!ctx
.info
[val
.id()].is_mul())
2577 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2579 if (mul_instr
->operands
[0].isLiteral())
2581 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2584 /* convert to mul(neg(a), b) */
2585 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2586 Definition def
= instr
->definitions
[0];
2587 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2588 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2589 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2590 instr
->operands
[0] = mul_instr
->operands
[0];
2591 instr
->operands
[1] = mul_instr
->operands
[1];
2592 instr
->definitions
[0] = def
;
2593 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2594 if (mul_instr
->isVOP3()) {
2595 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2596 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2597 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2598 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2599 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2600 new_mul
->omod
= mul
->omod
;
2602 new_mul
->neg
[0] ^= true;
2603 new_mul
->clamp
= false;
2605 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2609 /* combine mul+add -> mad */
2610 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2611 instr
->opcode
== aco_opcode::v_sub_f32
||
2612 instr
->opcode
== aco_opcode::v_subrev_f32
;
2613 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2614 instr
->opcode
== aco_opcode::v_sub_f16
||
2615 instr
->opcode
== aco_opcode::v_subrev_f16
;
2616 if (mad16
|| mad32
) {
2617 bool need_fma
= mad32
? (block
.fp_mode
.denorm32
!= 0 || ctx
.program
->chip_class
>= GFX10_3
) :
2618 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2619 if (need_fma
&& instr
->definitions
[0].isPrecise())
2621 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2624 uint32_t uses_src0
= UINT32_MAX
;
2625 uint32_t uses_src1
= UINT32_MAX
;
2626 Instruction
* mul_instr
= nullptr;
2627 unsigned add_op_idx
;
2628 /* check if any of the operands is a multiplication */
2629 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2630 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2631 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2632 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2633 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2634 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2636 /* find the 'best' mul instruction to combine with the add */
2637 if (uses_src0
< uses_src1
) {
2638 mul_instr
= op0_info
->instr
;
2640 } else if (uses_src1
< uses_src0
) {
2641 mul_instr
= op1_info
->instr
;
2643 } else if (uses_src0
!= UINT32_MAX
) {
2644 /* tiebreaker: quite random what to pick */
2645 if (op0_info
->instr
->operands
[0].isLiteral()) {
2646 mul_instr
= op1_info
->instr
;
2649 mul_instr
= op0_info
->instr
;
2654 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2655 bool neg
[3] = {false, false, false};
2656 bool abs
[3] = {false, false, false};
2659 op
[0] = mul_instr
->operands
[0];
2660 op
[1] = mul_instr
->operands
[1];
2661 op
[2] = instr
->operands
[add_op_idx
];
2662 // TODO: would be better to check this before selecting a mul instr?
2663 if (!check_vop3_operands(ctx
, 3, op
))
2666 if (mul_instr
->isVOP3()) {
2667 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2668 neg
[0] = vop3
->neg
[0];
2669 neg
[1] = vop3
->neg
[1];
2670 abs
[0] = vop3
->abs
[0];
2671 abs
[1] = vop3
->abs
[1];
2672 /* we cannot use these modifiers between mul and add */
2673 if (vop3
->clamp
|| vop3
->omod
)
2677 /* convert to mad */
2678 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2679 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2681 ctx
.uses
[op
[0].tempId()]++;
2683 ctx
.uses
[op
[1].tempId()]++;
2686 if (instr
->isVOP3()) {
2687 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2688 neg
[2] = vop3
->neg
[add_op_idx
];
2689 abs
[2] = vop3
->abs
[add_op_idx
];
2691 clamp
= vop3
->clamp
;
2692 /* abs of the multiplication result */
2693 if (vop3
->abs
[1 - add_op_idx
]) {
2699 /* neg of the multiplication result */
2700 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2702 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2703 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2704 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2705 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2707 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2709 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2710 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2712 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2713 for (unsigned i
= 0; i
< 3; i
++)
2715 mad
->operands
[i
] = op
[i
];
2716 mad
->neg
[i
] = neg
[i
];
2717 mad
->abs
[i
] = abs
[i
];
2721 mad
->definitions
[0] = instr
->definitions
[0];
2723 /* mark this ssa_def to be re-checked for profitability and literals */
2724 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2725 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2726 instr
.reset(mad
.release());
2730 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2731 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2732 for (unsigned i
= 0; i
< 2; i
++) {
2733 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2734 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2735 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2736 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2737 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2739 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2740 new_instr
->operands
[0] = Operand(0u);
2741 new_instr
->operands
[1] = instr
->operands
[!i
];
2742 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2743 new_instr
->definitions
[0] = instr
->definitions
[0];
2744 instr
.reset(new_instr
.release());
2745 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2749 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2750 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2751 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2752 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2753 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2754 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2755 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2756 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2757 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2758 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2759 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2760 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2761 else if (ctx
.program
->chip_class
>= GFX9
) {
2762 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2763 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2764 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2765 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2766 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2767 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2768 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2770 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2771 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2772 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2773 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2774 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2775 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2776 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2777 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2778 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2779 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2780 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2781 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2782 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2783 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2784 combine_salu_lshl_add(ctx
, instr
);
2785 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2786 combine_salu_not_bitwise(ctx
, instr
);
2787 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2788 if (combine_inverse_comparison(ctx
, instr
)) ;
2789 else combine_salu_not_bitwise(ctx
, instr
);
2790 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2791 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2792 if (combine_ordering_test(ctx
, instr
)) ;
2793 else if (combine_comparison_ordering(ctx
, instr
)) ;
2794 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2795 else combine_salu_n2(ctx
, instr
);
2797 aco_opcode min
, max
, min3
, max3
, med3
;
2798 bool some_gfx9_only
;
2799 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2800 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2801 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2802 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2807 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2809 switch (instr
->opcode
) {
2810 case aco_opcode::s_and_b32
:
2811 case aco_opcode::s_and_b64
:
2812 instr
->opcode
= aco_opcode::s_and_b32
;
2814 case aco_opcode::s_or_b32
:
2815 case aco_opcode::s_or_b64
:
2816 instr
->opcode
= aco_opcode::s_or_b32
;
2818 case aco_opcode::s_xor_b32
:
2819 case aco_opcode::s_xor_b64
:
2820 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2823 /* Don't transform other instructions. They are very unlikely to appear here. */
2827 for (Operand
&op
: instr
->operands
) {
2828 ctx
.uses
[op
.tempId()]--;
2830 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2831 /* Just use the uniform boolean temp. */
2832 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2833 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2834 /* Use the SCC definition of the predecessor instruction.
2835 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2836 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2838 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2839 assert(pred_instr
->definitions
.size() >= 2);
2840 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2841 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2843 unreachable("Invalid operand on uniform bitwise instruction.");
2846 ctx
.uses
[op
.tempId()]++;
2849 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2850 assert(instr
->operands
[0].regClass() == s1
);
2851 assert(instr
->operands
[1].regClass() == s1
);
2855 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2857 const uint32_t threshold
= 4;
2859 if (is_dead(ctx
.uses
, instr
.get())) {
2864 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2865 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2866 unsigned num_used
= 0;
2868 unsigned split_offset
= 0;
2869 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2870 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2873 split_offset
= offset
;
2877 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2878 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2879 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2883 for (Operand
& vec_op
: vec
->operands
) {
2884 if (off
== split_offset
) {
2888 off
+= vec_op
.bytes();
2890 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2891 ctx
.uses
[instr
->operands
[0].tempId()]--;
2892 for (Operand
& vec_op
: vec
->operands
) {
2893 if (vec_op
.isTemp())
2894 ctx
.uses
[vec_op
.tempId()]--;
2897 ctx
.uses
[op
.tempId()]++;
2899 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2900 extract
->operands
[0] = op
;
2901 extract
->definitions
[0] = instr
->definitions
[idx
];
2902 instr
.reset(extract
.release());
2908 if (!done
&& num_used
== 1 &&
2909 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2910 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2911 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2912 extract
->operands
[0] = instr
->operands
[0];
2913 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2914 extract
->definitions
[0] = instr
->definitions
[idx
];
2915 instr
.reset(extract
.release());
2919 mad_info
* mad_info
= NULL
;
2920 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2921 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].instr
->pass_flags
];
2922 /* re-check mad instructions */
2923 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2924 ctx
.uses
[mad_info
->mul_temp_id
]++;
2925 if (instr
->operands
[0].isTemp())
2926 ctx
.uses
[instr
->operands
[0].tempId()]--;
2927 if (instr
->operands
[1].isTemp())
2928 ctx
.uses
[instr
->operands
[1].tempId()]--;
2929 instr
.swap(mad_info
->add_instr
);
2932 /* check literals */
2933 else if (!instr
->usesModifiers()) {
2934 /* FMA can only take literals on GFX10+ */
2935 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2936 ctx
.program
->chip_class
< GFX10
)
2939 bool sgpr_used
= false;
2940 uint32_t literal_idx
= 0;
2941 uint32_t literal_uses
= UINT32_MAX
;
2942 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2944 if (instr
->operands
[i
].isConstant() && i
> 0) {
2945 literal_uses
= UINT32_MAX
;
2948 if (!instr
->operands
[i
].isTemp())
2950 unsigned bits
= get_operand_size(instr
, i
);
2951 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2952 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2953 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
)) {
2954 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2957 literal_uses
= UINT32_MAX
;
2960 /* don't break because we still need to check constants */
2961 } else if (!sgpr_used
&&
2962 ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
) &&
2963 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2964 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2969 /* Limit the number of literals to apply to not increase the code
2970 * size too much, but always apply literals for v_mad->v_madak
2971 * because both instructions are 64-bit and this doesn't increase
2973 * TODO: try to apply the literals earlier to lower the number of
2974 * uses below threshold
2976 if (literal_uses
< threshold
|| literal_idx
== 2) {
2977 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2978 mad_info
->check_literal
= true;
2979 mad_info
->literal_idx
= literal_idx
;
2985 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2986 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2987 instr
->operands
.size() &&
2988 instr
->operands
[0].isTemp()) {
2989 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2991 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2992 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2993 instr
->operands
[2].isTemp()) {
2994 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2997 /* check for literals */
2998 if (!instr
->isSALU() && !instr
->isVALU())
3001 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
3002 if (instr
->definitions
.size() &&
3003 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
3004 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
3005 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
3007 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
3008 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
3009 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
3010 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
3011 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
3012 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
3018 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
3019 return; /* some encodings can't ever take literals */
3021 /* we do not apply the literals yet as we don't know if it is profitable */
3022 Operand
current_literal(s1
);
3024 unsigned literal_id
= 0;
3025 unsigned literal_uses
= UINT32_MAX
;
3026 Operand
literal(s1
);
3027 unsigned num_operands
= 1;
3028 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
3029 num_operands
= instr
->operands
.size();
3030 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
3031 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
3034 unsigned sgpr_ids
[2] = {0, 0};
3035 bool is_literal_sgpr
= false;
3038 /* choose a literal to apply */
3039 for (unsigned i
= 0; i
< num_operands
; i
++) {
3040 Operand op
= instr
->operands
[i
];
3041 unsigned bits
= get_operand_size(instr
, i
);
3043 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
3044 op
.tempId() != sgpr_ids
[0])
3045 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
3047 if (op
.isLiteral()) {
3048 current_literal
= op
;
3050 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal(bits
)) {
3054 if (!alu_can_accept_constant(instr
->opcode
, i
))
3057 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
3058 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
3060 literal
= Operand(ctx
.info
[op
.tempId()].val
);
3061 literal_uses
= ctx
.uses
[op
.tempId()];
3062 literal_id
= op
.tempId();
3065 mask
|= (op
.tempId() == literal_id
) << i
;
3069 /* don't go over the constant bus limit */
3070 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
3071 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
3072 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
3073 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
3074 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
3075 const_bus_limit
= 2;
3077 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
3078 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
3081 if (literal_id
&& literal_uses
< threshold
&&
3082 (current_literal
.isUndefined() ||
3083 (current_literal
.size() == literal
.size() &&
3084 current_literal
.constantValue() == literal
.constantValue()))) {
3085 /* mark the literal to be applied */
3087 unsigned i
= u_bit_scan(&mask
);
3088 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
3089 ctx
.uses
[instr
->operands
[i
].tempId()]--;
3095 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
3097 /* Cleanup Dead Instructions */
3101 /* apply literals on MAD */
3102 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
3103 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].instr
->pass_flags
];
3104 if (info
->check_literal
&&
3105 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
3106 aco_ptr
<Instruction
> new_mad
;
3108 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
3109 if (instr
->opcode
== aco_opcode::v_fma_f32
)
3110 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
3111 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
3112 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
3113 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
3114 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
3116 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
3117 if (info
->literal_idx
== 2) { /* add literal -> madak */
3118 new_mad
->operands
[0] = instr
->operands
[0];
3119 new_mad
->operands
[1] = instr
->operands
[1];
3120 } else { /* mul literal -> madmk */
3121 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
3122 new_mad
->operands
[1] = instr
->operands
[2];
3124 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
3125 new_mad
->definitions
[0] = instr
->definitions
[0];
3126 ctx
.instructions
.emplace_back(std::move(new_mad
));
3131 /* apply literals on other SALU/VALU */
3132 if (instr
->isSALU() || instr
->isVALU()) {
3133 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
3134 Operand op
= instr
->operands
[i
];
3135 unsigned bits
= get_operand_size(instr
, i
);
3136 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal(bits
) && ctx
.uses
[op
.tempId()] == 0) {
3137 Operand
literal(ctx
.info
[op
.tempId()].val
);
3138 if (instr
->isVALU() && i
> 0)
3139 to_VOP3(ctx
, instr
);
3140 instr
->operands
[i
] = literal
;
3145 ctx
.instructions
.emplace_back(std::move(instr
));
3149 void optimize(Program
* program
)
3152 ctx
.program
= program
;
3153 std::vector
<ssa_info
> info(program
->peekAllocationId());
3154 ctx
.info
= info
.data();
3156 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
3157 for (Block
& block
: program
->blocks
) {
3158 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3159 label_instruction(ctx
, block
, instr
);
3162 ctx
.uses
= dead_code_analysis(program
);
3164 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3165 for (Block
& block
: program
->blocks
) {
3166 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3167 combine_instruction(ctx
, block
, instr
);
3170 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3171 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3172 Block
* block
= &(*it
);
3173 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3174 select_instruction(ctx
, *it
);
3177 /* 4. Add literals to instructions */
3178 for (Block
& block
: program
->blocks
) {
3179 ctx
.instructions
.clear();
3180 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3181 apply_literals(ctx
, instr
);
3182 block
.instructions
.swap(ctx
.instructions
);