2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
85 label_uniform_bool
= 1 << 21,
88 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
89 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
;
90 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
100 void add_label(Label new_label
)
102 /* Since all labels which use "instr" use it for the same thing
103 * (indicating the defining instruction), there is no need to clear
104 * any other instr labels. */
105 if (new_label
& instr_labels
)
106 label
&= ~temp_labels
; /* instr and temp alias */
108 if (new_label
& temp_labels
) {
109 label
&= ~temp_labels
;
110 label
&= ~instr_labels
; /* instr and temp alias */
113 if (new_label
& val_labels
)
114 label
&= ~val_labels
;
119 void set_vec(Instruction
* vec
)
121 add_label(label_vec
);
127 return label
& label_vec
;
130 void set_constant(uint32_t constant
)
132 add_label(label_constant
);
138 return label
& label_constant
;
141 void set_abs(Temp abs_temp
)
143 add_label(label_abs
);
149 return label
& label_abs
;
152 void set_neg(Temp neg_temp
)
154 add_label(label_neg
);
160 return label
& label_neg
;
163 void set_neg_abs(Temp neg_abs_temp
)
165 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
169 void set_mul(Instruction
* mul
)
171 add_label(label_mul
);
177 return label
& label_mul
;
180 void set_temp(Temp tmp
)
182 add_label(label_temp
);
188 return label
& label_temp
;
191 void set_literal(uint32_t lit
)
193 add_label(label_literal
);
199 return label
& label_literal
;
202 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
204 add_label(label_mad
);
211 return label
& label_mad
;
216 add_label(label_omod2
);
221 return label
& label_omod2
;
226 add_label(label_omod4
);
231 return label
& label_omod4
;
236 add_label(label_omod5
);
241 return label
& label_omod5
;
244 void set_omod_success(Instruction
* omod_instr
)
246 add_label(label_omod_success
);
250 bool is_omod_success()
252 return label
& label_omod_success
;
257 add_label(label_clamp
);
262 return label
& label_clamp
;
265 void set_clamp_success(Instruction
* clamp_instr
)
267 add_label(label_clamp_success
);
271 bool is_clamp_success()
273 return label
& label_clamp_success
;
278 add_label(label_undefined
);
283 return label
& label_undefined
;
286 void set_vcc(Temp vcc
)
288 add_label(label_vcc
);
294 return label
& label_vcc
;
297 bool is_constant_or_literal()
299 return is_constant() || is_literal();
302 void set_b2f(Temp val
)
304 add_label(label_b2f
);
310 return label
& label_b2f
;
313 void set_add_sub(Instruction
*add_sub_instr
)
315 add_label(label_add_sub
);
316 instr
= add_sub_instr
;
321 return label
& label_add_sub
;
324 void set_bitwise(Instruction
*bitwise_instr
)
326 add_label(label_bitwise
);
327 instr
= bitwise_instr
;
332 return label
& label_bitwise
;
335 void set_minmax(Instruction
*minmax_instr
)
337 add_label(label_minmax
);
338 instr
= minmax_instr
;
343 return label
& label_minmax
;
346 void set_fcmp(Instruction
*fcmp_instr
)
348 add_label(label_fcmp
);
354 return label
& label_fcmp
;
357 void set_uniform_bool(Temp uniform_bool
)
359 add_label(label_uniform_bool
);
363 bool is_uniform_bool()
365 return label
& label_uniform_bool
;
372 std::vector
<aco_ptr
<Instruction
>> instructions
;
374 std::pair
<uint32_t,Temp
> last_literal
;
375 std::vector
<mad_info
> mad_infos
;
376 std::vector
<uint16_t> uses
;
379 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
381 if (instr
->operands
[0].isConstant() ||
382 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
385 switch (instr
->opcode
) {
386 case aco_opcode::v_add_f32
:
387 case aco_opcode::v_mul_f32
:
388 case aco_opcode::v_or_b32
:
389 case aco_opcode::v_and_b32
:
390 case aco_opcode::v_xor_b32
:
391 case aco_opcode::v_max_f32
:
392 case aco_opcode::v_min_f32
:
393 case aco_opcode::v_cmp_eq_f32
:
394 case aco_opcode::v_cmp_lg_f32
:
396 case aco_opcode::v_sub_f32
:
397 instr
->opcode
= aco_opcode::v_subrev_f32
;
399 case aco_opcode::v_cmp_lt_f32
:
400 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
402 case aco_opcode::v_cmp_ge_f32
:
403 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
405 case aco_opcode::v_cmp_lt_i32
:
406 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
413 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
415 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
418 if (instr
->isDPP() || instr
->isSDWA())
421 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
422 instr
->opcode
!= aco_opcode::v_madak_f32
&&
423 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
424 instr
->opcode
!= aco_opcode::v_madak_f16
&&
425 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
426 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
427 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
430 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
432 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
433 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
434 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
435 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
436 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
439 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
444 assert(!instr
->operands
[0].isLiteral());
445 aco_ptr
<Instruction
> tmp
= std::move(instr
);
446 Format format
= asVOP3(tmp
->format
);
447 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
448 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
449 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
450 instr
->definitions
[i
] = tmp
->definitions
[i
];
451 if (instr
->definitions
[i
].isTemp()) {
452 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
453 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
454 info
.instr
= instr
.get();
459 /* only covers special cases */
460 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
462 switch (instr
->opcode
) {
463 case aco_opcode::v_interp_p2_f32
:
464 case aco_opcode::v_mac_f32
:
465 case aco_opcode::v_writelane_b32
:
466 case aco_opcode::v_writelane_b32_e64
:
467 case aco_opcode::v_cndmask_b32
:
469 case aco_opcode::s_addk_i32
:
470 case aco_opcode::s_mulk_i32
:
471 case aco_opcode::p_wqm
:
472 case aco_opcode::p_extract_vector
:
473 case aco_opcode::p_split_vector
:
474 case aco_opcode::v_readlane_b32
:
475 case aco_opcode::v_readlane_b32_e64
:
476 case aco_opcode::v_readfirstlane_b32
:
479 if ((instr
->format
== Format::MUBUF
||
480 instr
->format
== Format::MIMG
) &&
481 instr
->definitions
.size() == 1 &&
482 instr
->operands
.size() == 4) {
489 bool valu_can_accept_literal(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, unsigned operand
)
491 /* instructions like v_cndmask_b32 can't take a literal because they always
493 if (instr
->operands
.size() >= 3 &&
494 instr
->operands
[2].isTemp() && instr
->operands
[2].regClass().type() == RegType::sgpr
)
497 // TODO: VOP3 can take a literal on GFX10
498 return !instr
->isSDWA() && !instr
->isDPP() && !instr
->isVOP3() &&
499 operand
== 0 && can_accept_constant(instr
, operand
);
502 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
504 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
505 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
510 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
512 Operand op
= instr
->operands
[op_index
];
516 Temp tmp
= op
.getTemp();
517 if (!ctx
.info
[tmp
.id()].is_add_sub())
520 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
522 switch (add_instr
->opcode
) {
523 case aco_opcode::v_add_u32
:
524 case aco_opcode::v_add_co_u32
:
525 case aco_opcode::s_add_i32
:
526 case aco_opcode::s_add_u32
:
532 if (add_instr
->usesModifiers())
535 for (unsigned i
= 0; i
< 2; i
++) {
536 if (add_instr
->operands
[i
].isConstant()) {
537 *offset
= add_instr
->operands
[i
].constantValue();
538 } else if (add_instr
->operands
[i
].isTemp() &&
539 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
540 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
544 if (!add_instr
->operands
[!i
].isTemp())
547 uint32_t offset2
= 0;
548 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
551 *base
= add_instr
->operands
[!i
].getTemp();
559 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
)
561 // TODO: this functions shouldn't be needed if we store Operand instead of value.
563 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
564 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
568 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
570 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
571 ASSERTED
bool all_const
= false;
572 for (Operand
& op
: instr
->operands
)
573 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
574 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
577 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
579 if (!instr
->operands
[i
].isTemp())
582 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
583 /* propagate undef */
584 if (info
.is_undefined() && is_phi(instr
))
585 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
586 /* propagate reg->reg of same type */
587 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
588 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
589 info
= ctx
.info
[info
.temp
.id()];
592 /* SALU / PSEUDO: propagate inline constants */
593 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
594 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
595 instr
->operands
[i
].setTemp(info
.temp
);
596 info
= ctx
.info
[info
.temp
.id()];
597 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
598 /* propagate vgpr if it can take it */
599 switch (instr
->opcode
) {
600 case aco_opcode::p_create_vector
:
601 case aco_opcode::p_split_vector
:
602 case aco_opcode::p_extract_vector
:
603 case aco_opcode::p_phi
: {
604 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
605 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
607 instr
->operands
[i
] = Operand(info
.temp
);
608 info
= ctx
.info
[info
.temp
.id()];
616 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
617 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
622 /* VALU: propagate neg, abs & inline constants */
623 else if (instr
->isVALU()) {
624 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
625 instr
->operands
[i
].setTemp(info
.temp
);
626 info
= ctx
.info
[info
.temp
.id()];
628 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
631 instr
->operands
[i
] = Operand(info
.temp
);
633 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
635 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
637 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
638 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
639 instr
->operands
[i
].setTemp(info
.temp
);
641 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
644 instr
->operands
[i
].setTemp(info
.temp
);
646 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
648 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
651 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
652 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
653 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
654 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
656 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
657 instr
->operands
[i
] = instr
->operands
[0];
658 instr
->operands
[0] = get_constant_op(ctx
, info
.val
);
660 } else if (can_use_VOP3(instr
)) {
662 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
);
668 /* MUBUF: propagate constants and combine additions */
669 else if (instr
->format
== Format::MUBUF
) {
670 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
673 while (info
.is_temp())
674 info
= ctx
.info
[info
.temp
.id()];
676 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
677 assert(!mubuf
->idxen
);
678 instr
->operands
[i
] = Operand(v1
);
679 mubuf
->offset
+= info
.val
;
680 mubuf
->offen
= false;
682 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
683 instr
->operands
[2] = Operand((uint32_t) 0);
684 mubuf
->offset
+= info
.val
;
686 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
687 assert(!mubuf
->idxen
);
688 instr
->operands
[i
].setTemp(base
);
689 mubuf
->offset
+= offset
;
691 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
692 instr
->operands
[i
].setTemp(base
);
693 mubuf
->offset
+= offset
;
698 /* DS: combine additions */
699 else if (instr
->format
== Format::DS
) {
701 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
704 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass()) {
705 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
706 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
707 if (offset
% 4 == 0 &&
708 ds
->offset0
+ (offset
>> 2) <= 255 &&
709 ds
->offset1
+ (offset
>> 2) <= 255) {
710 instr
->operands
[i
].setTemp(base
);
711 ds
->offset0
+= offset
>> 2;
712 ds
->offset1
+= offset
>> 2;
715 if (ds
->offset0
+ offset
<= 65535) {
716 instr
->operands
[i
].setTemp(base
);
717 ds
->offset0
+= offset
;
723 /* SMEM: propagate constants and combine additions */
724 else if (instr
->format
== Format::SMEM
) {
726 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
729 if (i
== 1 && info
.is_constant_or_literal() &&
730 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
731 instr
->operands
[i
] = Operand(info
.val
);
733 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
734 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
736 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
737 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
741 smem
->operands
[1] = Operand(offset
);
742 smem
->operands
.back() = Operand(base
);
744 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
745 new_instr
->operands
[0] = smem
->operands
[0];
746 new_instr
->operands
[1] = Operand(offset
);
747 if (smem
->definitions
.empty())
748 new_instr
->operands
[2] = smem
->operands
[2];
749 new_instr
->operands
.back() = Operand(base
);
750 if (!smem
->definitions
.empty())
751 new_instr
->definitions
[0] = smem
->definitions
[0];
752 new_instr
->can_reorder
= smem
->can_reorder
;
753 new_instr
->barrier
= smem
->barrier
;
754 instr
.reset(new_instr
);
755 smem
= static_cast<SMEM_instruction
*>(instr
.get());
762 /* if this instruction doesn't define anything, return */
763 if (instr
->definitions
.empty())
766 switch (instr
->opcode
) {
767 case aco_opcode::p_create_vector
: {
768 unsigned num_ops
= instr
->operands
.size();
769 for (const Operand
& op
: instr
->operands
) {
770 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
771 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
773 if (num_ops
!= instr
->operands
.size()) {
774 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
775 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
776 instr
->definitions
[0] = old_vec
->definitions
[0];
778 for (Operand
& old_op
: old_vec
->operands
) {
779 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
780 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
781 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
782 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
783 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
784 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
785 instr
->operands
[k
++] = op
;
788 instr
->operands
[k
++] = old_op
;
791 assert(k
== num_ops
);
793 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
794 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
795 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
796 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
799 case aco_opcode::p_split_vector
: {
800 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
802 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
803 assert(instr
->definitions
.size() == vec
->operands
.size());
804 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
805 Operand vec_op
= vec
->operands
[i
];
806 if (vec_op
.isConstant()) {
807 if (vec_op
.isLiteral())
808 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
809 else if (vec_op
.size() == 1)
810 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
812 assert(vec_op
.isTemp());
813 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
818 case aco_opcode::p_extract_vector
: { /* mov */
819 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
821 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
822 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
823 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
825 /* convert this extract into a mov instruction */
826 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
827 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
828 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
829 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
830 instr
->opcode
= opcode
;
831 instr
->format
= format
;
832 instr
->operands
= {instr
->operands
.begin(), 1 };
833 instr
->operands
[0] = vec_op
;
835 if (vec_op
.isConstant()) {
836 if (vec_op
.isLiteral())
837 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
838 else if (vec_op
.size() == 1)
839 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
841 assert(vec_op
.isTemp());
842 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
847 case aco_opcode::s_mov_b32
: /* propagate */
848 case aco_opcode::s_mov_b64
:
849 case aco_opcode::v_mov_b32
:
850 case aco_opcode::p_as_uniform
:
851 if (instr
->definitions
[0].isFixed()) {
852 /* don't copy-propagate copies into fixed registers */
853 } else if (instr
->usesModifiers()) {
855 } else if (instr
->operands
[0].isConstant()) {
856 if (instr
->operands
[0].isLiteral())
857 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
858 else if (instr
->operands
[0].size() == 1)
859 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
860 } else if (instr
->operands
[0].isTemp()) {
861 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
863 assert(instr
->operands
[0].isFixed());
866 case aco_opcode::p_is_helper
:
867 if (!ctx
.program
->needs_wqm
)
868 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
870 case aco_opcode::s_movk_i32
: {
871 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
872 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
873 if (v
<= 64 || v
>= 0xfffffff0)
874 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
876 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
879 case aco_opcode::v_bfrev_b32
:
880 case aco_opcode::s_brev_b32
: {
881 if (instr
->operands
[0].isConstant()) {
882 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
883 if (v
<= 64 || v
>= 0xfffffff0)
884 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
886 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
890 case aco_opcode::s_bfm_b32
: {
891 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
892 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
893 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
894 uint32_t v
= ((1u << size
) - 1u) << start
;
895 if (v
<= 64 || v
>= 0xfffffff0)
896 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
898 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
901 case aco_opcode::v_mul_f32
: { /* omod */
902 /* TODO: try to move the negate/abs modifier to the consumer instead */
903 if (instr
->usesModifiers())
906 for (unsigned i
= 0; i
< 2; i
++) {
907 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
908 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
909 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2();
910 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
911 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4();
912 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
913 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5();
914 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
915 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
916 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
925 case aco_opcode::v_and_b32
: /* abs */
926 if (instr
->operands
[0].constantEquals(0x7FFFFFFF) && instr
->operands
[1].isTemp())
927 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
929 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
931 case aco_opcode::v_xor_b32
: { /* neg */
932 if (instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
933 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
934 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
936 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
937 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
938 instr
->opcode
= aco_opcode::v_or_b32
;
939 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
941 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
945 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
949 case aco_opcode::v_med3_f32
: { /* clamp */
950 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
951 if (vop3
->abs
[0] || vop3
->neg
[0] || vop3
->opsel
[0] ||
952 vop3
->abs
[1] || vop3
->neg
[1] || vop3
->opsel
[1] ||
953 vop3
->abs
[2] || vop3
->neg
[2] || vop3
->opsel
[2] ||
958 bool found_zero
= false, found_one
= false;
959 for (unsigned i
= 0; i
< 3; i
++)
961 if (instr
->operands
[i
].constantEquals(0))
963 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
968 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
969 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp();
973 case aco_opcode::v_cndmask_b32
:
974 if (instr
->operands
[0].constantEquals(0) &&
975 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
976 instr
->operands
[2].isTemp())
977 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
978 else if (instr
->operands
[0].constantEquals(0) &&
979 instr
->operands
[1].constantEquals(0x3f800000u
) &&
980 instr
->operands
[2].isTemp())
981 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
983 case aco_opcode::v_cmp_lg_u32
:
984 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
985 instr
->operands
[0].constantEquals(0) &&
986 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
987 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
989 case aco_opcode::p_phi
:
990 case aco_opcode::p_linear_phi
: {
991 /* lower_bool_phis() can create phis like this */
992 bool all_same_temp
= instr
->operands
[0].isTemp();
993 /* this check is needed when moving uniform loop counters out of a divergent loop */
995 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
996 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
997 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
998 all_same_temp
= false;
1000 if (all_same_temp
) {
1001 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1003 bool all_undef
= instr
->operands
[0].isUndefined();
1004 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1005 if (!instr
->operands
[i
].isUndefined())
1009 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1013 case aco_opcode::v_add_u32
:
1014 case aco_opcode::v_add_co_u32
:
1015 case aco_opcode::s_add_i32
:
1016 case aco_opcode::s_add_u32
:
1017 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1019 case aco_opcode::s_and_b32
:
1020 case aco_opcode::s_and_b64
:
1021 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&&
1022 instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1023 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1026 case aco_opcode::s_not_b32
:
1027 case aco_opcode::s_not_b64
:
1028 case aco_opcode::s_or_b32
:
1029 case aco_opcode::s_or_b64
:
1030 case aco_opcode::s_xor_b32
:
1031 case aco_opcode::s_xor_b64
:
1032 case aco_opcode::s_lshl_b32
:
1033 case aco_opcode::v_or_b32
:
1034 case aco_opcode::v_lshlrev_b32
:
1035 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1037 case aco_opcode::v_min_f32
:
1038 case aco_opcode::v_min_f16
:
1039 case aco_opcode::v_min_u32
:
1040 case aco_opcode::v_min_i32
:
1041 case aco_opcode::v_min_u16
:
1042 case aco_opcode::v_min_i16
:
1043 case aco_opcode::v_max_f32
:
1044 case aco_opcode::v_max_f16
:
1045 case aco_opcode::v_max_u32
:
1046 case aco_opcode::v_max_i32
:
1047 case aco_opcode::v_max_u16
:
1048 case aco_opcode::v_max_i16
:
1049 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1051 case aco_opcode::v_cmp_lt_f32
:
1052 case aco_opcode::v_cmp_eq_f32
:
1053 case aco_opcode::v_cmp_le_f32
:
1054 case aco_opcode::v_cmp_gt_f32
:
1055 case aco_opcode::v_cmp_lg_f32
:
1056 case aco_opcode::v_cmp_ge_f32
:
1057 case aco_opcode::v_cmp_o_f32
:
1058 case aco_opcode::v_cmp_u_f32
:
1059 case aco_opcode::v_cmp_nge_f32
:
1060 case aco_opcode::v_cmp_nlg_f32
:
1061 case aco_opcode::v_cmp_ngt_f32
:
1062 case aco_opcode::v_cmp_nle_f32
:
1063 case aco_opcode::v_cmp_neq_f32
:
1064 case aco_opcode::v_cmp_nlt_f32
:
1065 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1067 case aco_opcode::s_cselect_b64
:
1068 case aco_opcode::s_cselect_b32
:
1069 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1070 instr
->operands
[1].constantEquals(0)) {
1071 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1072 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1080 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1082 *ordered
= *unordered
= op
;
1084 #define CMP(ord, unord) \
1085 case aco_opcode::v_cmp_##ord##_f32:\
1086 case aco_opcode::v_cmp_n##unord##_f32:\
1087 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1088 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1089 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1103 aco_opcode
get_ordered(aco_opcode op
)
1105 aco_opcode ordered
, unordered
, inverse
;
1106 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1109 aco_opcode
get_unordered(aco_opcode op
)
1111 aco_opcode ordered
, unordered
, inverse
;
1112 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1115 aco_opcode
get_inverse(aco_opcode op
)
1117 aco_opcode ordered
, unordered
, inverse
;
1118 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1121 bool is_cmp(aco_opcode op
)
1123 aco_opcode ordered
, unordered
, inverse
;
1124 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1127 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1129 if (ctx
.info
[tmp
.id()].is_temp())
1130 return ctx
.info
[tmp
.id()].temp
.id();
1135 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1137 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1138 for (const Operand
& op
: instr
->operands
) {
1140 ctx
.uses
[op
.tempId()]--;
1145 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1147 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1149 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1152 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1154 if (instr
->definitions
.size() == 2) {
1155 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1156 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1163 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1164 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1165 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1167 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1169 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1172 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1174 bool neg
[2] = {false, false};
1175 bool abs
[2] = {false, false};
1176 bool opsel
[2] = {false, false};
1177 Instruction
*op_instr
[2];
1180 for (unsigned i
= 0; i
< 2; i
++) {
1181 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1185 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1187 if (op_instr
[i
]->opcode
!= expected_cmp
)
1189 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1192 if (op_instr
[i
]->isVOP3()) {
1193 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1194 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
[0] != vop3
->opsel
[1])
1196 neg
[i
] = vop3
->neg
[0];
1197 abs
[i
] = vop3
->abs
[0];
1198 opsel
[i
] = vop3
->opsel
[0];
1201 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1202 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1203 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1205 /* shouldn't happen yet, but best to be safe */
1206 if (op1
.type() != RegType::vgpr
)
1212 ctx
.uses
[op
[0].id()]++;
1213 ctx
.uses
[op
[1].id()]++;
1214 decrease_uses(ctx
, op_instr
[0]);
1215 decrease_uses(ctx
, op_instr
[1]);
1217 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1218 Instruction
*new_instr
;
1219 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
[0] || opsel
[1]) {
1220 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1221 for (unsigned i
= 0; i
< 2; i
++) {
1222 vop3
->neg
[i
] = neg
[i
];
1223 vop3
->abs
[i
] = abs
[i
];
1224 vop3
->opsel
[i
] = opsel
[i
];
1226 new_instr
= static_cast<Instruction
*>(vop3
);
1228 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1230 new_instr
->operands
[0] = Operand(op
[0]);
1231 new_instr
->operands
[1] = Operand(op
[1]);
1232 new_instr
->definitions
[0] = instr
->definitions
[0];
1234 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1235 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1237 instr
.reset(new_instr
);
1242 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1243 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1244 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1246 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1248 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1251 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1252 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1254 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1255 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1256 if (!nan_test
|| !cmp
)
1259 if (cmp
->opcode
== expected_nan_test
)
1260 std::swap(nan_test
, cmp
);
1261 else if (nan_test
->opcode
!= expected_nan_test
)
1264 if (!is_cmp(cmp
->opcode
))
1267 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1269 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1272 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1273 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1274 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1275 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1276 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1278 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1281 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1282 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1283 decrease_uses(ctx
, nan_test
);
1284 decrease_uses(ctx
, cmp
);
1286 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1287 Instruction
*new_instr
;
1288 if (cmp
->isVOP3()) {
1289 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1290 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1291 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1292 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1293 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1294 new_vop3
->clamp
= cmp_vop3
->clamp
;
1295 new_vop3
->omod
= cmp_vop3
->omod
;
1296 new_instr
= new_vop3
;
1298 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1300 new_instr
->operands
[0] = cmp
->operands
[0];
1301 new_instr
->operands
[1] = cmp
->operands
[1];
1302 new_instr
->definitions
[0] = instr
->definitions
[0];
1304 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1305 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1307 instr
.reset(new_instr
);
1312 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1313 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1314 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1316 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1318 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1321 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1323 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1324 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1326 if (!nan_test
|| !cmp
)
1329 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1330 if (cmp
->opcode
== expected_nan_test
)
1331 std::swap(nan_test
, cmp
);
1332 else if (nan_test
->opcode
!= expected_nan_test
)
1335 if (!is_cmp(cmp
->opcode
))
1338 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1340 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1343 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1344 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1345 if (prop_nan0
!= prop_nan1
)
1348 int constant_operand
= -1;
1349 for (unsigned i
= 0; i
< 2; i
++) {
1350 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1351 constant_operand
= !i
;
1355 if (constant_operand
== -1)
1359 if (cmp
->operands
[constant_operand
].isConstant()) {
1360 constant
= cmp
->operands
[constant_operand
].constantValue();
1361 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1362 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1363 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1365 constant
= ctx
.info
[id
].val
;
1371 memcpy(&constantf
, &constant
, 4);
1372 if (isnan(constantf
))
1375 if (cmp
->operands
[0].isTemp())
1376 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1377 if (cmp
->operands
[1].isTemp())
1378 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1379 decrease_uses(ctx
, nan_test
);
1380 decrease_uses(ctx
, cmp
);
1382 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1383 Instruction
*new_instr
;
1384 if (cmp
->isVOP3()) {
1385 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1386 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1387 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1388 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1389 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1390 new_vop3
->clamp
= cmp_vop3
->clamp
;
1391 new_vop3
->omod
= cmp_vop3
->omod
;
1392 new_instr
= new_vop3
;
1394 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1396 new_instr
->operands
[0] = cmp
->operands
[0];
1397 new_instr
->operands
[1] = cmp
->operands
[1];
1398 new_instr
->definitions
[0] = instr
->definitions
[0];
1400 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1401 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1403 instr
.reset(new_instr
);
1408 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1409 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1411 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1413 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1415 if (!instr
->operands
[0].isTemp())
1418 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1422 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1423 if (new_opcode
== aco_opcode::last_opcode
)
1426 if (cmp
->operands
[0].isTemp())
1427 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1428 if (cmp
->operands
[1].isTemp())
1429 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1430 decrease_uses(ctx
, cmp
);
1432 Instruction
*new_instr
;
1433 if (cmp
->isVOP3()) {
1434 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1435 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1436 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1437 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1438 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1439 new_vop3
->clamp
= cmp_vop3
->clamp
;
1440 new_vop3
->omod
= cmp_vop3
->omod
;
1441 new_instr
= new_vop3
;
1443 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1445 new_instr
->operands
[0] = cmp
->operands
[0];
1446 new_instr
->operands
[1] = cmp
->operands
[1];
1447 new_instr
->definitions
[0] = instr
->definitions
[0];
1449 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1450 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1452 instr
.reset(new_instr
);
1457 /* op1(op2(1, 2), 0) if swap = false
1458 * op1(0, op2(1, 2)) if swap = true */
1459 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1460 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1461 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1462 bool *op1_clamp
, unsigned *op1_omod
,
1463 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1466 if (op1_instr
->opcode
!= op1
)
1469 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1470 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1473 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1474 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1476 /* don't support inbetween clamp/omod */
1477 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1480 /* get operands and modifiers and check inbetween modifiers */
1481 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1482 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1485 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1486 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1490 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1491 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1494 if (inbetween_opsel
)
1495 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
[swap
] : false;
1496 else if (op1_vop3
&& op1_vop3
->opsel
[swap
])
1500 shuffle
[shuffle_str
[0] - '0'] = 0;
1501 shuffle
[shuffle_str
[1] - '0'] = 1;
1502 shuffle
[shuffle_str
[2] - '0'] = 2;
1504 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1505 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1506 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1507 opsel
[shuffle
[0]] = op1_vop3
? op1_vop3
->opsel
[!swap
] : false;
1509 for (unsigned i
= 0; i
< 2; i
++) {
1510 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1511 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1512 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1513 opsel
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->opsel
[i
] : false;
1516 /* check operands */
1517 unsigned sgpr_id
= 0;
1518 for (unsigned i
= 0; i
< 3; i
++) {
1519 Operand op
= operands
[i
];
1520 if (op
.isLiteral()) {
1522 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1523 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1525 sgpr_id
= op
.tempId();
1532 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1533 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1534 bool clamp
, unsigned omod
)
1536 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1537 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1538 memcpy(new_instr
->opsel
, opsel
, sizeof(bool[3]));
1539 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1540 new_instr
->clamp
= clamp
;
1541 new_instr
->omod
= omod
;
1542 new_instr
->operands
[0] = operands
[0];
1543 new_instr
->operands
[1] = operands
[1];
1544 new_instr
->operands
[2] = operands
[2];
1545 new_instr
->definitions
[0] = instr
->definitions
[0];
1546 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1548 instr
.reset(new_instr
);
1551 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1553 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1554 (label_omod_success
| label_clamp_success
);
1556 for (unsigned swap
= 0; swap
< 2; swap
++) {
1557 if (!((1 << swap
) & ops
))
1560 Operand operands
[3];
1561 bool neg
[3], abs
[3], opsel
[3], clamp
;
1563 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1564 instr
.get(), swap
, shuffle
,
1565 operands
, neg
, abs
, opsel
,
1566 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1567 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1568 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1569 if (omod_clamp
& label_omod_success
)
1570 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1571 if (omod_clamp
& label_clamp_success
)
1572 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1579 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1580 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1581 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1582 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1583 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1584 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1585 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1588 if (!instr
->operands
[0].isTemp())
1590 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1593 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1596 switch (op2_instr
->opcode
) {
1597 case aco_opcode::s_and_b32
:
1598 case aco_opcode::s_or_b32
:
1599 case aco_opcode::s_xor_b32
:
1600 case aco_opcode::s_and_b64
:
1601 case aco_opcode::s_or_b64
:
1602 case aco_opcode::s_xor_b64
:
1608 /* create instruction */
1609 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1610 ctx
.uses
[instr
->operands
[0].tempId()]--;
1611 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1613 switch (op2_instr
->opcode
) {
1614 case aco_opcode::s_and_b32
:
1615 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1617 case aco_opcode::s_or_b32
:
1618 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1620 case aco_opcode::s_xor_b32
:
1621 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1623 case aco_opcode::s_and_b64
:
1624 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1626 case aco_opcode::s_or_b64
:
1627 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1629 case aco_opcode::s_xor_b64
:
1630 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1639 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1640 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1641 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1642 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1643 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1645 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1648 for (unsigned i
= 0; i
< 2; i
++) {
1649 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1650 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1653 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1654 instr
->operands
[0] = instr
->operands
[!i
];
1655 instr
->operands
[1] = op2_instr
->operands
[0];
1656 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1658 switch (instr
->opcode
) {
1659 case aco_opcode::s_and_b32
:
1660 instr
->opcode
= aco_opcode::s_andn2_b32
;
1662 case aco_opcode::s_or_b32
:
1663 instr
->opcode
= aco_opcode::s_orn2_b32
;
1665 case aco_opcode::s_and_b64
:
1666 instr
->opcode
= aco_opcode::s_andn2_b64
;
1668 case aco_opcode::s_or_b64
:
1669 instr
->opcode
= aco_opcode::s_orn2_b64
;
1680 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1681 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1683 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1686 for (unsigned i
= 0; i
< 2; i
++) {
1687 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1688 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1691 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1692 if (shift
< 1 || shift
> 4)
1695 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1696 instr
->operands
[1] = instr
->operands
[!i
];
1697 instr
->operands
[0] = op2_instr
->operands
[0];
1698 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1700 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1701 aco_opcode::s_lshl2_add_u32
,
1702 aco_opcode::s_lshl3_add_u32
,
1703 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1710 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1713 #define MINMAX(type, gfx9) \
1714 case aco_opcode::v_min_##type:\
1715 case aco_opcode::v_max_##type:\
1716 case aco_opcode::v_med3_##type:\
1717 *min = aco_opcode::v_min_##type;\
1718 *max = aco_opcode::v_max_##type;\
1719 *med3 = aco_opcode::v_med3_##type;\
1720 *min3 = aco_opcode::v_min3_##type;\
1721 *max3 = aco_opcode::v_max3_##type;\
1722 *some_gfx9_only = gfx9;\
1736 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1737 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1738 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1739 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1741 aco_opcode other_op
;
1742 if (instr
->opcode
== min
)
1744 else if (instr
->opcode
== max
)
1749 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1750 (label_omod_success
| label_clamp_success
);
1752 for (unsigned swap
= 0; swap
< 2; swap
++) {
1753 Operand operands
[3];
1754 bool neg
[3], abs
[3], opsel
[3], clamp
, inbetween_neg
, inbetween_abs
;
1756 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1757 "012", operands
, neg
, abs
, opsel
,
1758 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1759 int const0_idx
= -1, const1_idx
= -1;
1760 uint32_t const0
= 0, const1
= 0;
1761 for (int i
= 0; i
< 3; i
++) {
1763 if (operands
[i
].isConstant()) {
1764 val
= operands
[i
].constantValue();
1765 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1766 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1767 val
= ctx
.info
[operands
[i
].tempId()].val
;
1771 if (const0_idx
>= 0) {
1779 if (const0_idx
< 0 || const1_idx
< 0)
1782 if (opsel
[const0_idx
])
1784 if (opsel
[const1_idx
])
1787 int lower_idx
= const0_idx
;
1789 case aco_opcode::v_min_f32
:
1790 case aco_opcode::v_min_f16
: {
1791 float const0_f
, const1_f
;
1792 if (min
== aco_opcode::v_min_f32
) {
1793 memcpy(&const0_f
, &const0
, 4);
1794 memcpy(&const1_f
, &const1
, 4);
1796 const0_f
= _mesa_half_to_float(const0
);
1797 const1_f
= _mesa_half_to_float(const1
);
1799 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1800 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1801 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1802 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1803 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1806 case aco_opcode::v_min_u32
: {
1807 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1810 case aco_opcode::v_min_u16
: {
1811 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1814 case aco_opcode::v_min_i32
: {
1815 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1816 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1817 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1820 case aco_opcode::v_min_i16
: {
1821 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1822 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1823 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1829 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1831 if (instr
->opcode
== min
) {
1832 if (upper_idx
!= 0 || lower_idx
== 0)
1835 if (upper_idx
== 0 || lower_idx
!= 0)
1839 neg
[1] ^= inbetween_neg
;
1840 neg
[2] ^= inbetween_neg
;
1841 abs
[1] |= inbetween_abs
;
1842 abs
[2] |= inbetween_abs
;
1844 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1845 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1846 if (omod_clamp
& label_omod_success
)
1847 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1848 if (omod_clamp
& label_clamp_success
)
1849 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1859 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1862 uint32_t sgpr_idx
= 0;
1863 uint32_t sgpr_info_id
= 0;
1864 bool has_sgpr
= false;
1865 uint32_t sgpr_ssa_id
= 0;
1866 /* find 'best' possible sgpr */
1867 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
1869 if (instr
->operands
[i
].isLiteral()) {
1873 if (!instr
->operands
[i
].isTemp())
1875 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1877 sgpr_ssa_id
= instr
->operands
[i
].tempId();
1880 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1881 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
1882 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1883 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1885 sgpr_info_id
= instr
->operands
[i
].tempId();
1889 if (!has_sgpr
&& sgpr_info_id
!= 0) {
1890 ssa_info
& info
= ctx
.info
[sgpr_info_id
];
1891 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1892 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1893 ctx
.uses
[sgpr_info_id
]--;
1894 ctx
.uses
[info
.temp
.id()]++;
1895 } else if (can_swap_operands(instr
)) {
1896 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1897 instr
->operands
[0] = Operand(info
.temp
);
1898 ctx
.uses
[sgpr_info_id
]--;
1899 ctx
.uses
[info
.temp
.id()]++;
1900 } else if (can_use_VOP3(instr
)) {
1901 to_VOP3(ctx
, instr
);
1902 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1903 ctx
.uses
[sgpr_info_id
]--;
1904 ctx
.uses
[info
.temp
.id()]++;
1907 /* we can have two sgprs on one instruction if it is the same sgpr! */
1908 } else if (sgpr_info_id
!= 0 &&
1909 sgpr_ssa_id
== sgpr_info_id
&&
1910 ctx
.uses
[sgpr_info_id
] == 1 &&
1911 can_use_VOP3(instr
)) {
1912 to_VOP3(ctx
, instr
);
1913 instr
->operands
[sgpr_idx
] = Operand(ctx
.info
[sgpr_info_id
].temp
);
1914 ctx
.uses
[sgpr_info_id
]--;
1915 ctx
.uses
[ctx
.info
[sgpr_info_id
].temp
.id()]++;
1919 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
1921 /* check if we could apply omod on predecessor */
1922 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1923 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success()) {
1925 /* omod was successfully applied */
1926 /* if the omod instruction is v_mad, we also have to change the original add */
1927 if (ctx
.info
[instr
->operands
[1].tempId()].is_mad()) {
1928 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[1].tempId()].val
].add_instr
.get();
1929 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1930 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1931 add_instr
->definitions
[0] = instr
->definitions
[0];
1934 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
1935 /* check if we have an additional clamp modifier */
1936 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1) {
1937 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1938 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1940 /* change definition ssa-id of modified instruction */
1941 omod_instr
->definitions
[0] = instr
->definitions
[0];
1943 /* change the definition of instr to something unused, e.g. the original omod def */
1944 instr
->definitions
[0] = Definition(instr
->operands
[1].getTemp());
1945 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1948 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1949 /* in all other cases, label this instruction as option for multiply-add */
1950 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1954 /* check if we could apply clamp on predecessor */
1955 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1957 bool found_zero
= false, found_one
= false;
1958 for (unsigned i
= 0; i
< 3; i
++)
1960 if (instr
->operands
[i
].constantEquals(0))
1962 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1967 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1968 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1969 /* clamp was successfully applied */
1970 /* if the clamp instruction is v_mad, we also have to change the original add */
1971 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1972 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1973 add_instr
->definitions
[0] = instr
->definitions
[0];
1975 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1976 /* change definition ssa-id of modified instruction */
1977 clamp_instr
->definitions
[0] = instr
->definitions
[0];
1979 /* change the definition of instr to something unused, e.g. the original omod def */
1980 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1981 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1986 /* omod has no effect if denormals are enabled */
1987 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
1989 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
1990 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1991 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
1992 if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod2()) {
1993 to_VOP3(ctx
, instr
);
1994 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
1995 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1996 } else if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod4()) {
1997 to_VOP3(ctx
, instr
);
1998 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
1999 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2000 } else if (can_use_omod
&& ctx
.info
[instr
->definitions
[0].tempId()].is_omod5()) {
2001 to_VOP3(ctx
, instr
);
2002 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2003 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2004 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp()) {
2005 to_VOP3(ctx
, instr
);
2006 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2007 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2014 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2015 // this would mean that we'd have to fix the instruction uses while value propagation
2017 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2019 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
2022 if (instr
->isVALU()) {
2023 if (can_apply_sgprs(instr
))
2024 apply_sgprs(ctx
, instr
);
2025 if (apply_omod_clamp(ctx
, block
, instr
))
2029 /* TODO: There are still some peephole optimizations that could be done:
2030 * - abs(a - b) -> s_absdiff_i32
2031 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2032 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2033 * These aren't probably too interesting though.
2034 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2035 * probably more useful than the previously mentioned optimizations.
2036 * The various comparison optimizations also currently only work with 32-bit
2039 /* neg(mul(a, b)) -> mul(neg(a), b) */
2040 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2041 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2043 if (!ctx
.info
[val
.id()].is_mul())
2046 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2048 if (mul_instr
->operands
[0].isLiteral())
2050 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2053 /* convert to mul(neg(a), b) */
2054 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2055 Definition def
= instr
->definitions
[0];
2056 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2057 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2058 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2059 instr
->operands
[0] = mul_instr
->operands
[0];
2060 instr
->operands
[1] = mul_instr
->operands
[1];
2061 instr
->definitions
[0] = def
;
2062 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2063 if (mul_instr
->isVOP3()) {
2064 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2065 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2066 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2067 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2068 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2069 new_mul
->omod
= mul
->omod
;
2071 new_mul
->neg
[0] ^= true;
2072 new_mul
->clamp
= false;
2074 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2077 /* combine mul+add -> mad */
2078 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2079 instr
->opcode
== aco_opcode::v_sub_f32
||
2080 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2081 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2082 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2084 uint32_t uses_src0
= UINT32_MAX
;
2085 uint32_t uses_src1
= UINT32_MAX
;
2086 Instruction
* mul_instr
= nullptr;
2087 unsigned add_op_idx
;
2088 /* check if any of the operands is a multiplication */
2089 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2090 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2091 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2092 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2094 /* find the 'best' mul instruction to combine with the add */
2095 if (uses_src0
< uses_src1
) {
2096 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2098 } else if (uses_src1
< uses_src0
) {
2099 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2101 } else if (uses_src0
!= UINT32_MAX
) {
2102 /* tiebreaker: quite random what to pick */
2103 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2104 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2107 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2112 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2113 bool neg
[3] = {false, false, false};
2114 bool abs
[3] = {false, false, false};
2117 bool need_vop3
= false;
2119 op
[0] = mul_instr
->operands
[0];
2120 op
[1] = mul_instr
->operands
[1];
2121 op
[2] = instr
->operands
[add_op_idx
];
2122 for (unsigned i
= 0; i
< 3; i
++)
2124 if (op
[i
].isLiteral())
2126 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
)
2128 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2131 // TODO: would be better to check this before selecting a mul instr?
2135 if (mul_instr
->isVOP3()) {
2136 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2137 neg
[0] = vop3
->neg
[0];
2138 neg
[1] = vop3
->neg
[1];
2139 abs
[0] = vop3
->abs
[0];
2140 abs
[1] = vop3
->abs
[1];
2142 /* we cannot use these modifiers between mul and add */
2143 if (vop3
->clamp
|| vop3
->omod
)
2147 /* convert to mad */
2148 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2149 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2151 ctx
.uses
[op
[0].tempId()]++;
2153 ctx
.uses
[op
[1].tempId()]++;
2156 if (instr
->isVOP3()) {
2157 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2158 neg
[2] = vop3
->neg
[add_op_idx
];
2159 abs
[2] = vop3
->abs
[add_op_idx
];
2161 clamp
= vop3
->clamp
;
2162 /* abs of the multiplication result */
2163 if (vop3
->abs
[1 - add_op_idx
]) {
2169 /* neg of the multiplication result */
2170 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2173 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2174 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2176 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2177 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2181 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2182 for (unsigned i
= 0; i
< 3; i
++)
2184 mad
->operands
[i
] = op
[i
];
2185 mad
->neg
[i
] = neg
[i
];
2186 mad
->abs
[i
] = abs
[i
];
2190 mad
->definitions
[0] = instr
->definitions
[0];
2192 /* mark this ssa_def to be re-checked for profitability and literals */
2193 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2194 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2195 instr
.reset(mad
.release());
2199 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2200 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2201 for (unsigned i
= 0; i
< 2; i
++) {
2202 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2203 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2204 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2205 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2206 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2208 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2209 new_instr
->operands
[0] = Operand(0u);
2210 new_instr
->operands
[1] = instr
->operands
[!i
];
2211 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2212 new_instr
->definitions
[0] = instr
->definitions
[0];
2213 instr
.reset(new_instr
.release());
2214 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2218 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2219 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2220 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2221 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2222 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2223 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2224 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2225 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2226 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2227 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2228 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2229 combine_salu_lshl_add(ctx
, instr
);
2230 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2231 combine_salu_not_bitwise(ctx
, instr
);
2232 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2233 if (combine_inverse_comparison(ctx
, instr
)) ;
2234 else combine_salu_not_bitwise(ctx
, instr
);
2235 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2236 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2237 if (combine_ordering_test(ctx
, instr
)) ;
2238 else if (combine_comparison_ordering(ctx
, instr
)) ;
2239 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2240 else combine_salu_n2(ctx
, instr
);
2242 aco_opcode min
, max
, min3
, max3
, med3
;
2243 bool some_gfx9_only
;
2244 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2245 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2246 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, instr
->opcode
== min
? min3
: max3
, "012", 1 | 2));
2247 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2253 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2255 const uint32_t threshold
= 4;
2257 /* Dead Code Elimination:
2258 * We remove instructions if they define temporaries which all are unused */
2259 const bool is_used
= instr
->definitions
.empty() ||
2260 std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
2261 [&ctx
](const Definition
& def
) { return ctx
.uses
[def
.tempId()]; });
2267 /* convert split_vector into extract_vector if only one definition is ever used */
2268 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2269 unsigned num_used
= 0;
2271 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2272 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2277 if (num_used
== 1) {
2278 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2279 extract
->operands
[0] = instr
->operands
[0];
2280 extract
->operands
[1] = Operand((uint32_t) idx
);
2281 extract
->definitions
[0] = instr
->definitions
[idx
];
2282 instr
.reset(extract
.release());
2286 /* re-check mad instructions */
2287 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2288 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2289 /* first, check profitability */
2290 if (ctx
.uses
[info
->mul_temp_id
]) {
2291 ctx
.uses
[info
->mul_temp_id
]++;
2292 instr
.swap(info
->add_instr
);
2294 /* second, check possible literals */
2295 } else if (!info
->needs_vop3
) {
2296 uint32_t literal_idx
= 0;
2297 uint32_t literal_uses
= UINT32_MAX
;
2298 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2300 if (!instr
->operands
[i
].isTemp())
2302 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2303 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2304 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2305 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2308 literal_uses
= UINT32_MAX
;
2312 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2313 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2314 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2318 if (literal_uses
< threshold
) {
2319 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2320 info
->check_literal
= true;
2321 info
->literal_idx
= literal_idx
;
2327 /* check for literals */
2328 /* we do not apply the literals yet as we don't know if it is profitable */
2329 if (instr
->isSALU()) {
2330 uint32_t literal_idx
= 0;
2331 uint32_t literal_uses
= UINT32_MAX
;
2332 bool has_literal
= false;
2333 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2335 if (instr
->operands
[i
].isLiteral()) {
2339 if (!instr
->operands
[i
].isTemp())
2341 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2342 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2343 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2347 if (!has_literal
&& literal_uses
< threshold
) {
2348 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2349 if (ctx
.uses
[instr
->operands
[literal_idx
].tempId()] == 0)
2350 instr
->operands
[literal_idx
] = Operand(ctx
.info
[instr
->operands
[literal_idx
].tempId()].val
);
2352 } else if (instr
->isVALU() && valu_can_accept_literal(ctx
, instr
, 0) &&
2353 instr
->operands
[0].isTemp() &&
2354 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2355 ctx
.uses
[instr
->operands
[0].tempId()] < threshold
) {
2356 ctx
.uses
[instr
->operands
[0].tempId()]--;
2357 if (ctx
.uses
[instr
->operands
[0].tempId()] == 0)
2358 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2364 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2366 /* Cleanup Dead Instructions */
2370 /* apply literals on SALU */
2371 if (instr
->isSALU()) {
2372 for (Operand
& op
: instr
->operands
) {
2377 if (ctx
.info
[op
.tempId()].is_literal() &&
2378 ctx
.uses
[op
.tempId()] == 0)
2379 op
= Operand(ctx
.info
[op
.tempId()].val
);
2383 /* apply literals on VALU */
2384 else if (instr
->isVALU() && !instr
->isVOP3() &&
2385 instr
->operands
[0].isTemp() &&
2386 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2387 ctx
.uses
[instr
->operands
[0].tempId()] == 0) {
2388 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2391 /* apply literals on MAD */
2392 else if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2393 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2394 aco_ptr
<Instruction
> new_mad
;
2395 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2396 if (info
->literal_idx
== 2) { /* add literal -> madak */
2397 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2398 new_mad
->operands
[0] = instr
->operands
[0];
2399 new_mad
->operands
[1] = instr
->operands
[1];
2400 } else { /* mul literal -> madmk */
2401 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2402 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2403 new_mad
->operands
[1] = instr
->operands
[2];
2405 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2406 new_mad
->definitions
[0] = instr
->definitions
[0];
2407 instr
.swap(new_mad
);
2411 ctx
.instructions
.emplace_back(std::move(instr
));
2415 void optimize(Program
* program
)
2418 ctx
.program
= program
;
2419 std::vector
<ssa_info
> info(program
->peekAllocationId());
2420 ctx
.info
= info
.data();
2422 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2423 for (Block
& block
: program
->blocks
) {
2424 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2425 label_instruction(ctx
, block
, instr
);
2428 ctx
.uses
= std::move(dead_code_analysis(program
));
2430 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2431 for (Block
& block
: program
->blocks
) {
2432 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2433 combine_instruction(ctx
, block
, instr
);
2436 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2437 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2438 Block
* block
= &(*it
);
2439 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2440 select_instruction(ctx
, *it
);
2443 /* 4. Add literals to instructions */
2444 for (Block
& block
: program
->blocks
) {
2445 ctx
.instructions
.clear();
2446 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2447 apply_literals(ctx
, instr
);
2448 block
.instructions
.swap(ctx
.instructions
);