2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant_32bit
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
94 label_constant_16bit
= 1 << 29,
97 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
98 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
99 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
100 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
101 static constexpr uint32_t val_labels
= label_constant_32bit
| label_constant_64bit
| label_constant_16bit
| label_literal
| label_mad
;
111 ssa_info() : label(0) {}
113 void add_label(Label new_label
)
115 /* Since all labels which use "instr" use it for the same thing
116 * (indicating the defining instruction), there is no need to clear
117 * any other instr labels. */
118 if (new_label
& instr_labels
)
119 label
&= ~temp_labels
; /* instr and temp alias */
121 if (new_label
& temp_labels
) {
122 label
&= ~temp_labels
;
123 label
&= ~instr_labels
; /* instr and temp alias */
126 uint32_t const_labels
= label_literal
| label_constant_32bit
| label_constant_64bit
| label_constant_16bit
;
127 if (new_label
& const_labels
)
128 label
&= ~val_labels
| const_labels
;
129 else if (new_label
& val_labels
)
130 label
&= ~val_labels
;
135 void set_vec(Instruction
* vec
)
137 add_label(label_vec
);
143 return label
& label_vec
;
146 void set_constant(chip_class chip
, uint64_t constant
)
148 Operand
op16((uint16_t)constant
);
149 Operand
op32((uint32_t)constant
);
150 add_label(label_literal
);
153 if (chip
>= GFX8
&& !op16
.isLiteral())
154 add_label(label_constant_16bit
);
156 if (!op32
.isLiteral() || ((uint32_t)constant
== 0x3e22f983 && chip
>= GFX8
))
157 add_label(label_constant_32bit
);
159 if (constant
<= 64) {
160 add_label(label_constant_64bit
);
161 } else if (constant
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
162 add_label(label_constant_64bit
);
163 } else if (constant
== 0x3FE0000000000000) { /* 0.5 */
164 add_label(label_constant_64bit
);
165 } else if (constant
== 0xBFE0000000000000) { /* -0.5 */
166 add_label(label_constant_64bit
);
167 } else if (constant
== 0x3FF0000000000000) { /* 1.0 */
168 add_label(label_constant_64bit
);
169 } else if (constant
== 0xBFF0000000000000) { /* -1.0 */
170 add_label(label_constant_64bit
);
171 } else if (constant
== 0x4000000000000000) { /* 2.0 */
172 add_label(label_constant_64bit
);
173 } else if (constant
== 0xC000000000000000) { /* -2.0 */
174 add_label(label_constant_64bit
);
175 } else if (constant
== 0x4010000000000000) { /* 4.0 */
176 add_label(label_constant_64bit
);
177 } else if (constant
== 0xC010000000000000) { /* -4.0 */
178 add_label(label_constant_64bit
);
181 if (label
& label_constant_64bit
) {
182 val
= Operand(constant
).constantValue();
184 label
&= ~(label_literal
| label_constant_16bit
| label_constant_32bit
);
188 bool is_constant(unsigned bits
)
192 return label
& label_literal
;
194 return label
& label_constant_16bit
;
196 return label
& label_constant_32bit
;
198 return label
& label_constant_64bit
;
203 bool is_literal(unsigned bits
)
205 bool is_lit
= label
& label_literal
;
210 return is_lit
&& ~(label
& label_constant_16bit
);
212 return is_lit
&& ~(label
& label_constant_32bit
);
219 bool is_constant_or_literal(unsigned bits
)
222 return label
& label_constant_64bit
;
224 return label
& label_literal
;
227 void set_abs(Temp abs_temp
)
229 add_label(label_abs
);
235 return label
& label_abs
;
238 void set_neg(Temp neg_temp
)
240 add_label(label_neg
);
246 return label
& label_neg
;
249 void set_neg_abs(Temp neg_abs_temp
)
251 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
255 void set_mul(Instruction
* mul
)
257 add_label(label_mul
);
263 return label
& label_mul
;
266 void set_temp(Temp tmp
)
268 add_label(label_temp
);
274 return label
& label_temp
;
277 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
279 add_label(label_mad
);
286 return label
& label_mad
;
289 void set_omod2(Temp def
)
291 add_label(label_omod2
);
297 return label
& label_omod2
;
300 void set_omod4(Temp def
)
302 add_label(label_omod4
);
308 return label
& label_omod4
;
311 void set_omod5(Temp def
)
313 add_label(label_omod5
);
319 return label
& label_omod5
;
322 void set_omod_success(Instruction
* omod_instr
)
324 add_label(label_omod_success
);
328 bool is_omod_success()
330 return label
& label_omod_success
;
333 void set_clamp(Temp def
)
335 add_label(label_clamp
);
341 return label
& label_clamp
;
344 void set_clamp_success(Instruction
* clamp_instr
)
346 add_label(label_clamp_success
);
350 bool is_clamp_success()
352 return label
& label_clamp_success
;
357 add_label(label_undefined
);
362 return label
& label_undefined
;
365 void set_vcc(Temp vcc
)
367 add_label(label_vcc
);
373 return label
& label_vcc
;
376 void set_b2f(Temp val
)
378 add_label(label_b2f
);
384 return label
& label_b2f
;
387 void set_add_sub(Instruction
*add_sub_instr
)
389 add_label(label_add_sub
);
390 instr
= add_sub_instr
;
395 return label
& label_add_sub
;
398 void set_bitwise(Instruction
*bitwise_instr
)
400 add_label(label_bitwise
);
401 instr
= bitwise_instr
;
406 return label
& label_bitwise
;
409 void set_uniform_bitwise()
411 add_label(label_uniform_bitwise
);
414 bool is_uniform_bitwise()
416 return label
& label_uniform_bitwise
;
419 void set_minmax(Instruction
*minmax_instr
)
421 add_label(label_minmax
);
422 instr
= minmax_instr
;
427 return label
& label_minmax
;
430 void set_fcmp(Instruction
*fcmp_instr
)
432 add_label(label_fcmp
);
438 return label
& label_fcmp
;
441 void set_scc_needed()
443 add_label(label_scc_needed
);
448 return label
& label_scc_needed
;
451 void set_scc_invert(Temp scc_inv
)
453 add_label(label_scc_invert
);
459 return label
& label_scc_invert
;
462 void set_uniform_bool(Temp uniform_bool
)
464 add_label(label_uniform_bool
);
468 bool is_uniform_bool()
470 return label
& label_uniform_bool
;
475 add_label(label_vcc_hint
);
480 return label
& label_vcc_hint
;
483 void set_b2i(Temp val
)
485 add_label(label_b2i
);
491 return label
& label_b2i
;
498 std::vector
<aco_ptr
<Instruction
>> instructions
;
500 std::pair
<uint32_t,Temp
> last_literal
;
501 std::vector
<mad_info
> mad_infos
;
502 std::vector
<uint16_t> uses
;
507 aco_opcode unordered
;
508 aco_opcode ordered_swapped
;
509 aco_opcode unordered_swapped
;
515 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
);
517 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
519 if (instr
->operands
[0].isConstant() ||
520 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
523 switch (instr
->opcode
) {
524 case aco_opcode::v_add_f16
:
525 case aco_opcode::v_add_f32
:
526 case aco_opcode::v_mul_f16
:
527 case aco_opcode::v_mul_f32
:
528 case aco_opcode::v_or_b32
:
529 case aco_opcode::v_and_b32
:
530 case aco_opcode::v_xor_b32
:
531 case aco_opcode::v_max_f16
:
532 case aco_opcode::v_max_f32
:
533 case aco_opcode::v_min_f16
:
534 case aco_opcode::v_min_f32
:
535 case aco_opcode::v_max_i32
:
536 case aco_opcode::v_min_i32
:
537 case aco_opcode::v_max_u32
:
538 case aco_opcode::v_min_u32
:
539 case aco_opcode::v_max_i16
:
540 case aco_opcode::v_min_i16
:
541 case aco_opcode::v_max_u16
:
542 case aco_opcode::v_min_u16
:
543 case aco_opcode::v_max_i16_e64
:
544 case aco_opcode::v_min_i16_e64
:
545 case aco_opcode::v_max_u16_e64
:
546 case aco_opcode::v_min_u16_e64
:
548 case aco_opcode::v_sub_f16
:
549 instr
->opcode
= aco_opcode::v_subrev_f16
;
551 case aco_opcode::v_sub_f32
:
552 instr
->opcode
= aco_opcode::v_subrev_f32
;
554 case aco_opcode::v_sub_co_u32
:
555 instr
->opcode
= aco_opcode::v_subrev_co_u32
;
557 case aco_opcode::v_sub_u16
:
558 instr
->opcode
= aco_opcode::v_subrev_u16
;
560 case aco_opcode::v_sub_u32
:
561 instr
->opcode
= aco_opcode::v_subrev_u32
;
565 get_cmp_info(instr
->opcode
, &info
);
566 if (info
.ordered
== instr
->opcode
) {
567 instr
->opcode
= info
.ordered_swapped
;
570 if (info
.unordered
== instr
->opcode
) {
571 instr
->opcode
= info
.unordered_swapped
;
579 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
584 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
587 if (instr
->isDPP() || instr
->isSDWA())
590 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
591 instr
->opcode
!= aco_opcode::v_madak_f32
&&
592 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
593 instr
->opcode
!= aco_opcode::v_madak_f16
&&
594 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
595 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
596 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
597 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
598 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
599 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
600 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
603 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
605 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
606 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
607 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
608 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
609 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
612 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
617 aco_ptr
<Instruction
> tmp
= std::move(instr
);
618 Format format
= asVOP3(tmp
->format
);
619 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
620 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
621 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
622 instr
->definitions
[i
] = tmp
->definitions
[i
];
623 if (instr
->definitions
[i
].isTemp()) {
624 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
625 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
626 info
.instr
= instr
.get();
631 /* only covers special cases */
632 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
635 case aco_opcode::v_interp_p2_f32
:
636 case aco_opcode::v_mac_f32
:
637 case aco_opcode::v_writelane_b32
:
638 case aco_opcode::v_writelane_b32_e64
:
639 case aco_opcode::v_cndmask_b32
:
641 case aco_opcode::s_addk_i32
:
642 case aco_opcode::s_mulk_i32
:
643 case aco_opcode::p_wqm
:
644 case aco_opcode::p_extract_vector
:
645 case aco_opcode::p_split_vector
:
646 case aco_opcode::v_readlane_b32
:
647 case aco_opcode::v_readlane_b32_e64
:
648 case aco_opcode::v_readfirstlane_b32
:
655 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
657 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
658 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
663 /* check constant bus and literal limitations */
664 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
666 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
667 Operand
literal32(s1
);
668 Operand
literal64(s2
);
669 unsigned num_sgprs
= 0;
670 unsigned sgpr
[] = {0, 0};
672 for (unsigned i
= 0; i
< num_operands
; i
++) {
673 Operand op
= operands
[i
];
675 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
676 /* two reads of the same SGPR count as 1 to the limit */
677 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
679 sgpr
[num_sgprs
++] = op
.tempId();
684 } else if (op
.isLiteral()) {
685 if (ctx
.program
->chip_class
< GFX10
)
688 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
690 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
693 /* Any number of 32-bit literals counts as only 1 to the limit. Same
694 * (but separately) for 64-bit literals. */
695 if (op
.size() == 1 && literal32
.isUndefined()) {
698 } else if (op
.size() == 2 && literal64
.isUndefined()) {
711 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
713 Operand op
= instr
->operands
[op_index
];
717 Temp tmp
= op
.getTemp();
718 if (!ctx
.info
[tmp
.id()].is_add_sub())
721 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
723 switch (add_instr
->opcode
) {
724 case aco_opcode::v_add_u32
:
725 case aco_opcode::v_add_co_u32
:
726 case aco_opcode::v_add_co_u32_e64
:
727 case aco_opcode::s_add_i32
:
728 case aco_opcode::s_add_u32
:
734 if (add_instr
->usesModifiers())
737 for (unsigned i
= 0; i
< 2; i
++) {
738 if (add_instr
->operands
[i
].isConstant()) {
739 *offset
= add_instr
->operands
[i
].constantValue();
740 } else if (add_instr
->operands
[i
].isTemp() &&
741 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal(32)) {
742 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
746 if (!add_instr
->operands
[!i
].isTemp())
749 uint32_t offset2
= 0;
750 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
753 *base
= add_instr
->operands
[!i
].getTemp();
761 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
763 if (instr
->format
== Format::PSEUDO
)
764 return instr
->operands
[index
].bytes() * 8u;
765 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
766 return index
== 2 ? 64 : 32;
767 else if (instr
->isVALU() || instr
->isSALU())
768 return instr_info
.operand_size
[(int)instr
->opcode
];
773 Operand
get_constant_op(opt_ctx
&ctx
, ssa_info info
, uint32_t bits
)
776 return Operand((uint8_t)info
.val
);
778 return Operand((uint16_t)info
.val
);
779 // TODO: this functions shouldn't be needed if we store Operand instead of value.
780 Operand
op(info
.val
, bits
== 64);
781 if (info
.is_literal(32) && info
.val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
782 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
786 bool fixed_to_exec(Operand op
)
788 return op
.isFixed() && op
.physReg() == exec
;
791 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
793 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
794 ASSERTED
bool all_const
= false;
795 for (Operand
& op
: instr
->operands
)
796 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal(32));
797 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
800 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
802 if (!instr
->operands
[i
].isTemp())
805 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
806 /* propagate undef */
807 if (info
.is_undefined() && is_phi(instr
))
808 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
809 /* propagate reg->reg of same type */
810 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
811 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
812 info
= ctx
.info
[info
.temp
.id()];
815 /* SALU / PSEUDO: propagate inline constants */
816 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
817 bool is_subdword
= false;
818 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
819 if (instr
->format
== Format::PSEUDO
) {
820 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
821 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
822 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
823 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
824 if (is_subdword
&& ctx
.program
->chip_class
< GFX9
)
828 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
829 instr
->operands
[i
].setTemp(info
.temp
);
830 info
= ctx
.info
[info
.temp
.id()];
831 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
832 /* propagate vgpr if it can take it */
833 switch (instr
->opcode
) {
834 case aco_opcode::p_create_vector
:
835 case aco_opcode::p_split_vector
:
836 case aco_opcode::p_extract_vector
:
837 case aco_opcode::p_phi
: {
838 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
839 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
841 instr
->operands
[i
] = Operand(info
.temp
);
842 info
= ctx
.info
[info
.temp
.id()];
850 unsigned bits
= get_operand_size(instr
, i
);
851 if ((info
.is_constant(bits
) || (!is_subdword
&& info
.is_literal(bits
) && instr
->format
== Format::PSEUDO
)) &&
852 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
853 instr
->operands
[i
] = get_constant_op(ctx
, info
, bits
);
858 /* VALU: propagate neg, abs & inline constants */
859 else if (instr
->isVALU()) {
860 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
861 instr
->operands
[i
].setTemp(info
.temp
);
862 info
= ctx
.info
[info
.temp
.id()];
865 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
866 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
867 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
869 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
872 instr
->operands
[i
] = Operand(info
.temp
);
874 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
876 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
878 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
879 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
880 instr
->operands
[i
].setTemp(info
.temp
);
882 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
883 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
884 instr
->operands
[i
].setTemp(info
.temp
);
886 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
889 instr
->operands
[i
].setTemp(info
.temp
);
891 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
893 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
896 unsigned bits
= get_operand_size(instr
, i
);
897 if (info
.is_constant(bits
) && alu_can_accept_constant(instr
->opcode
, i
)) {
898 Operand op
= get_constant_op(ctx
, info
, bits
);
899 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
900 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
901 instr
->operands
[i
] = op
;
903 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
904 instr
->operands
[i
] = instr
->operands
[0];
905 instr
->operands
[0] = op
;
907 } else if (can_use_VOP3(ctx
, instr
)) {
909 instr
->operands
[i
] = op
;
915 /* MUBUF: propagate constants and combine additions */
916 else if (instr
->format
== Format::MUBUF
) {
917 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
920 while (info
.is_temp())
921 info
= ctx
.info
[info
.temp
.id()];
923 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
924 assert(!mubuf
->idxen
);
925 instr
->operands
[1] = Operand(v1
);
926 mubuf
->offset
+= info
.val
;
927 mubuf
->offen
= false;
929 } else if (i
== 2 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
930 instr
->operands
[2] = Operand((uint32_t) 0);
931 mubuf
->offset
+= info
.val
;
933 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
934 assert(!mubuf
->idxen
);
935 instr
->operands
[1].setTemp(base
);
936 mubuf
->offset
+= offset
;
938 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
939 instr
->operands
[i
].setTemp(base
);
940 mubuf
->offset
+= offset
;
945 /* DS: combine additions */
946 else if (instr
->format
== Format::DS
) {
948 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
951 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
952 if (has_usable_ds_offset
&&
953 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
954 base
.regClass() == instr
->operands
[i
].regClass() &&
955 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
956 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
957 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
958 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
959 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
961 if ((offset
& mask
) == 0 &&
962 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
963 ds
->offset1
+ (offset
>> shifts
) <= 255) {
964 instr
->operands
[i
].setTemp(base
);
965 ds
->offset0
+= offset
>> shifts
;
966 ds
->offset1
+= offset
>> shifts
;
969 if (ds
->offset0
+ offset
<= 65535) {
970 instr
->operands
[i
].setTemp(base
);
971 ds
->offset0
+= offset
;
977 /* SMEM: propagate constants and combine additions */
978 else if (instr
->format
== Format::SMEM
) {
980 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
983 if (i
== 1 && info
.is_constant_or_literal(32) &&
984 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
985 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
986 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
987 instr
->operands
[i
] = Operand(info
.val
);
989 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
990 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
992 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal(32) ||
993 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
997 smem
->operands
[1] = Operand(offset
);
998 smem
->operands
.back() = Operand(base
);
1000 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
1001 new_instr
->operands
[0] = smem
->operands
[0];
1002 new_instr
->operands
[1] = Operand(offset
);
1003 if (smem
->definitions
.empty())
1004 new_instr
->operands
[2] = smem
->operands
[2];
1005 new_instr
->operands
.back() = Operand(base
);
1006 if (!smem
->definitions
.empty())
1007 new_instr
->definitions
[0] = smem
->definitions
[0];
1008 new_instr
->can_reorder
= smem
->can_reorder
;
1009 new_instr
->barrier
= smem
->barrier
;
1010 new_instr
->glc
= smem
->glc
;
1011 new_instr
->dlc
= smem
->dlc
;
1012 new_instr
->nv
= smem
->nv
;
1013 new_instr
->disable_wqm
= smem
->disable_wqm
;
1014 instr
.reset(new_instr
);
1015 smem
= static_cast<SMEM_instruction
*>(instr
.get());
1021 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
1022 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1023 /* Flip the branch instruction to get rid of the scc_invert instruction */
1024 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
1025 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1030 /* if this instruction doesn't define anything, return */
1031 if (instr
->definitions
.empty())
1034 switch (instr
->opcode
) {
1035 case aco_opcode::p_create_vector
: {
1036 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
1037 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
1039 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1043 unsigned num_ops
= instr
->operands
.size();
1044 for (const Operand
& op
: instr
->operands
) {
1045 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
1046 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
1048 if (num_ops
!= instr
->operands
.size()) {
1049 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
1050 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
1051 instr
->definitions
[0] = old_vec
->definitions
[0];
1053 for (Operand
& old_op
: old_vec
->operands
) {
1054 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
1055 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
1056 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
1057 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
1058 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
1059 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
1060 instr
->operands
[k
++] = op
;
1063 instr
->operands
[k
++] = old_op
;
1066 assert(k
== num_ops
);
1069 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
1072 case aco_opcode::p_split_vector
: {
1073 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1075 if (info
.is_constant_or_literal(32)) {
1076 uint32_t val
= info
.val
;
1077 for (Definition def
: instr
->definitions
) {
1078 uint32_t mask
= u_bit_consecutive(0, def
.bytes() * 8u);
1079 ctx
.info
[def
.tempId()].set_constant(ctx
.program
->chip_class
, val
& mask
);
1080 val
>>= def
.bytes() * 8u;
1083 } else if (!info
.is_vec()) {
1087 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1088 unsigned split_offset
= 0;
1089 unsigned vec_offset
= 0;
1090 unsigned vec_index
= 0;
1091 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
1092 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
1093 vec_offset
+= vec
->operands
[vec_index
++].bytes();
1095 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
1098 Operand vec_op
= vec
->operands
[vec_index
];
1099 if (vec_op
.isConstant()) {
1100 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(ctx
.program
->chip_class
, vec_op
.constantValue64());
1101 } else if (vec_op
.isUndefined()) {
1102 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1104 assert(vec_op
.isTemp());
1105 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1110 case aco_opcode::p_extract_vector
: { /* mov */
1111 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1112 const unsigned index
= instr
->operands
[1].constantValue();
1113 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1115 if (info
.is_constant_or_literal(32)) {
1116 uint32_t mask
= u_bit_consecutive(0, instr
->definitions
[0].bytes() * 8u);
1117 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, (info
.val
>> (dst_offset
* 8u)) & mask
);
1119 } else if (!info
.is_vec()) {
1123 /* check if we index directly into a vector element */
1124 Instruction
* vec
= info
.instr
;
1125 unsigned offset
= 0;
1127 for (const Operand
& op
: vec
->operands
) {
1128 if (offset
< dst_offset
) {
1129 offset
+= op
.bytes();
1131 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1135 /* convert this extract into a copy instruction */
1136 instr
->opcode
= aco_opcode::p_parallelcopy
;
1137 instr
->operands
.pop_back();
1138 instr
->operands
[0] = op
;
1140 if (op
.isConstant()) {
1141 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, op
.constantValue64());
1142 } else if (op
.isUndefined()) {
1143 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1145 assert(op
.isTemp());
1146 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1152 case aco_opcode::s_mov_b32
: /* propagate */
1153 case aco_opcode::s_mov_b64
:
1154 case aco_opcode::v_mov_b32
:
1155 case aco_opcode::p_as_uniform
:
1156 if (instr
->definitions
[0].isFixed()) {
1157 /* don't copy-propagate copies into fixed registers */
1158 } else if (instr
->usesModifiers()) {
1160 } else if (instr
->operands
[0].isConstant()) {
1161 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, instr
->operands
[0].constantValue64());
1162 } else if (instr
->operands
[0].isTemp()) {
1163 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1165 assert(instr
->operands
[0].isFixed());
1168 case aco_opcode::p_is_helper
:
1169 if (!ctx
.program
->needs_wqm
)
1170 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, 0u);
1172 case aco_opcode::s_movk_i32
: {
1173 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1174 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1175 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1178 case aco_opcode::v_bfrev_b32
:
1179 case aco_opcode::s_brev_b32
: {
1180 if (instr
->operands
[0].isConstant()) {
1181 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1182 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1186 case aco_opcode::s_bfm_b32
: {
1187 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1188 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1189 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1190 uint32_t v
= ((1u << size
) - 1u) << start
;
1191 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1195 case aco_opcode::v_mul_f16
:
1196 case aco_opcode::v_mul_f32
: { /* omod */
1197 /* TODO: try to move the negate/abs modifier to the consumer instead */
1198 if (instr
->usesModifiers())
1201 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1203 for (unsigned i
= 0; i
< 2; i
++) {
1204 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1205 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1206 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1207 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1208 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1209 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1210 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1211 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1212 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1213 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1222 case aco_opcode::v_and_b32
: { /* abs */
1223 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1224 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1225 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1226 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1227 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1229 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1232 case aco_opcode::v_xor_b32
: { /* neg */
1233 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1234 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1235 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1236 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1237 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1238 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1239 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1240 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1241 instr
->opcode
= aco_opcode::v_or_b32
;
1242 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1244 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1248 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1252 case aco_opcode::v_med3_f16
:
1253 case aco_opcode::v_med3_f32
: { /* clamp */
1254 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1255 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1256 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1257 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1261 bool found_zero
= false, found_one
= false;
1262 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1263 for (unsigned i
= 0; i
< 3; i
++)
1265 if (instr
->operands
[i
].constantEquals(0))
1267 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1272 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1273 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1277 case aco_opcode::v_cndmask_b32
:
1278 if (instr
->operands
[0].constantEquals(0) &&
1279 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1280 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1281 else if (instr
->operands
[0].constantEquals(0) &&
1282 instr
->operands
[1].constantEquals(0x3f800000u
))
1283 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1284 else if (instr
->operands
[0].constantEquals(0) &&
1285 instr
->operands
[1].constantEquals(1))
1286 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1288 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1290 case aco_opcode::v_cmp_lg_u32
:
1291 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1292 instr
->operands
[0].constantEquals(0) &&
1293 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1294 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1296 case aco_opcode::p_phi
:
1297 case aco_opcode::p_linear_phi
: {
1298 /* lower_bool_phis() can create phis like this */
1299 bool all_same_temp
= instr
->operands
[0].isTemp();
1300 /* this check is needed when moving uniform loop counters out of a divergent loop */
1302 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1303 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1304 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1305 all_same_temp
= false;
1307 if (all_same_temp
) {
1308 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1310 bool all_undef
= instr
->operands
[0].isUndefined();
1311 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1312 if (!instr
->operands
[i
].isUndefined())
1316 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1320 case aco_opcode::v_add_u32
:
1321 case aco_opcode::v_add_co_u32
:
1322 case aco_opcode::v_add_co_u32_e64
:
1323 case aco_opcode::s_add_i32
:
1324 case aco_opcode::s_add_u32
:
1325 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1327 case aco_opcode::s_not_b32
:
1328 case aco_opcode::s_not_b64
:
1329 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1330 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1331 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1332 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1333 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1334 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1336 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1338 case aco_opcode::s_and_b32
:
1339 case aco_opcode::s_and_b64
:
1340 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1341 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1342 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1343 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1344 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1346 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1347 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1348 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1349 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1354 case aco_opcode::s_or_b32
:
1355 case aco_opcode::s_or_b64
:
1356 case aco_opcode::s_xor_b32
:
1357 case aco_opcode::s_xor_b64
:
1358 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1359 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1361 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1364 case aco_opcode::s_lshl_b32
:
1365 case aco_opcode::v_or_b32
:
1366 case aco_opcode::v_lshlrev_b32
:
1367 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1369 case aco_opcode::v_min_f32
:
1370 case aco_opcode::v_min_f16
:
1371 case aco_opcode::v_min_u32
:
1372 case aco_opcode::v_min_i32
:
1373 case aco_opcode::v_min_u16
:
1374 case aco_opcode::v_min_i16
:
1375 case aco_opcode::v_max_f32
:
1376 case aco_opcode::v_max_f16
:
1377 case aco_opcode::v_max_u32
:
1378 case aco_opcode::v_max_i32
:
1379 case aco_opcode::v_max_u16
:
1380 case aco_opcode::v_max_i16
:
1381 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1384 case aco_opcode::v_cmp_##cmp##_f16:\
1385 case aco_opcode::v_cmp_##cmp##_f32:\
1386 case aco_opcode::v_cmp_##cmp##_f64:\
1387 case aco_opcode::v_cmp_n##cmp##_f16:\
1388 case aco_opcode::v_cmp_n##cmp##_f32:\
1389 case aco_opcode::v_cmp_n##cmp##_f64:
1396 case aco_opcode::v_cmp_o_f16
:
1397 case aco_opcode::v_cmp_u_f16
:
1398 case aco_opcode::v_cmp_o_f32
:
1399 case aco_opcode::v_cmp_u_f32
:
1400 case aco_opcode::v_cmp_o_f64
:
1401 case aco_opcode::v_cmp_u_f64
:
1403 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1405 case aco_opcode::s_cselect_b64
:
1406 case aco_opcode::s_cselect_b32
:
1407 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1408 instr
->operands
[1].constantEquals(0)) {
1409 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1410 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1412 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1413 /* Flip the operands to get rid of the scc_invert instruction */
1414 std::swap(instr
->operands
[0], instr
->operands
[1]);
1415 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1418 case aco_opcode::p_wqm
:
1419 if (instr
->operands
[0].isTemp() &&
1420 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1421 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1429 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
)
1431 info
->ordered
= aco_opcode::num_opcodes
;
1432 info
->unordered
= aco_opcode::num_opcodes
;
1433 info
->ordered_swapped
= aco_opcode::num_opcodes
;
1434 info
->unordered_swapped
= aco_opcode::num_opcodes
;
1436 #define CMP2(ord, unord, ord_swap, unord_swap, sz) \
1437 case aco_opcode::v_cmp_##ord##_f##sz:\
1438 case aco_opcode::v_cmp_n##unord##_f##sz:\
1439 info->ordered = aco_opcode::v_cmp_##ord##_f##sz;\
1440 info->unordered = aco_opcode::v_cmp_n##unord##_f##sz;\
1441 info->ordered_swapped = aco_opcode::v_cmp_##ord_swap##_f##sz;\
1442 info->unordered_swapped = aco_opcode::v_cmp_n##unord_swap##_f##sz;\
1443 info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz : aco_opcode::v_cmp_n##ord##_f##sz;\
1444 info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 : aco_opcode::v_cmp_n##unord##_f32;\
1447 #define CMP(ord, unord, ord_swap, unord_swap) \
1448 CMP2(ord, unord, ord_swap, unord_swap, 16)\
1449 CMP2(ord, unord, ord_swap, unord_swap, 32)\
1450 CMP2(ord, unord, ord_swap, unord_swap, 64)
1451 CMP(lt
, /*n*/ge
, gt
, /*n*/le
)
1452 CMP(eq
, /*n*/lg
, eq
, /*n*/lg
)
1453 CMP(le
, /*n*/gt
, ge
, /*n*/lt
)
1454 CMP(gt
, /*n*/le
, lt
, /*n*/le
)
1455 CMP(lg
, /*n*/eq
, lg
, /*n*/eq
)
1456 CMP(ge
, /*n*/lt
, le
, /*n*/gt
)
1459 #define ORD_TEST(sz) \
1460 case aco_opcode::v_cmp_u_f##sz:\
1461 info->f32 = aco_opcode::v_cmp_u_f32;\
1462 info->inverse = aco_opcode::v_cmp_o_f##sz;\
1465 case aco_opcode::v_cmp_o_f##sz:\
1466 info->f32 = aco_opcode::v_cmp_o_f32;\
1467 info->inverse = aco_opcode::v_cmp_u_f##sz;\
1479 aco_opcode
get_ordered(aco_opcode op
)
1482 return get_cmp_info(op
, &info
) ? info
.ordered
: aco_opcode::num_opcodes
;
1485 aco_opcode
get_unordered(aco_opcode op
)
1488 return get_cmp_info(op
, &info
) ? info
.unordered
: aco_opcode::num_opcodes
;
1491 aco_opcode
get_inverse(aco_opcode op
)
1494 return get_cmp_info(op
, &info
) ? info
.inverse
: aco_opcode::num_opcodes
;
1497 aco_opcode
get_f32_cmp(aco_opcode op
)
1500 return get_cmp_info(op
, &info
) ? info
.f32
: aco_opcode::num_opcodes
;
1503 unsigned get_cmp_bitsize(aco_opcode op
)
1506 return get_cmp_info(op
, &info
) ? info
.size
: 0;
1509 bool is_cmp(aco_opcode op
)
1512 return get_cmp_info(op
, &info
) && info
.ordered
!= aco_opcode::num_opcodes
;
1515 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1517 if (ctx
.info
[tmp
.id()].is_temp())
1518 return ctx
.info
[tmp
.id()].temp
.id();
1523 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1525 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1526 for (const Operand
& op
: instr
->operands
) {
1528 ctx
.uses
[op
.tempId()]--;
1533 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1535 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1537 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1540 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1542 if (instr
->definitions
.size() == 2) {
1543 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1544 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1551 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1552 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1553 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1555 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1557 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1560 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1562 bool neg
[2] = {false, false};
1563 bool abs
[2] = {false, false};
1565 Instruction
*op_instr
[2];
1568 unsigned bitsize
= 0;
1569 for (unsigned i
= 0; i
< 2; i
++) {
1570 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1574 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1575 unsigned op_bitsize
= get_cmp_bitsize(op_instr
[i
]->opcode
);
1577 if (get_f32_cmp(op_instr
[i
]->opcode
) != expected_cmp
)
1579 if (bitsize
&& op_bitsize
!= bitsize
)
1581 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1584 if (op_instr
[i
]->isVOP3()) {
1585 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1586 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1588 neg
[i
] = vop3
->neg
[0];
1589 abs
[i
] = vop3
->abs
[0];
1590 opsel
|= (vop3
->opsel
& 1) << i
;
1593 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1594 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1595 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1599 bitsize
= op_bitsize
;
1602 if (op
[1].type() == RegType::sgpr
)
1603 std::swap(op
[0], op
[1]);
1604 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1605 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1608 ctx
.uses
[op
[0].id()]++;
1609 ctx
.uses
[op
[1].id()]++;
1610 decrease_uses(ctx
, op_instr
[0]);
1611 decrease_uses(ctx
, op_instr
[1]);
1613 aco_opcode new_op
= aco_opcode::num_opcodes
;
1616 new_op
= is_or
? aco_opcode::v_cmp_u_f16
: aco_opcode::v_cmp_o_f16
;
1619 new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1622 new_op
= is_or
? aco_opcode::v_cmp_u_f64
: aco_opcode::v_cmp_o_f64
;
1625 Instruction
*new_instr
;
1626 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1627 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1628 for (unsigned i
= 0; i
< 2; i
++) {
1629 vop3
->neg
[i
] = neg
[i
];
1630 vop3
->abs
[i
] = abs
[i
];
1632 vop3
->opsel
= opsel
;
1633 new_instr
= static_cast<Instruction
*>(vop3
);
1635 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1637 new_instr
->operands
[0] = Operand(op
[0]);
1638 new_instr
->operands
[1] = Operand(op
[1]);
1639 new_instr
->definitions
[0] = instr
->definitions
[0];
1641 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1642 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1644 instr
.reset(new_instr
);
1649 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1650 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1651 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1653 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1655 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1658 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1659 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1661 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1662 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1663 if (!nan_test
|| !cmp
)
1666 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1667 std::swap(nan_test
, cmp
);
1668 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1671 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1674 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1676 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1679 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1680 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1681 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1682 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1683 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1685 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1688 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1689 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1690 decrease_uses(ctx
, nan_test
);
1691 decrease_uses(ctx
, cmp
);
1693 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1694 Instruction
*new_instr
;
1695 if (cmp
->isVOP3()) {
1696 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1697 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1698 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1699 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1700 new_vop3
->clamp
= cmp_vop3
->clamp
;
1701 new_vop3
->omod
= cmp_vop3
->omod
;
1702 new_vop3
->opsel
= cmp_vop3
->opsel
;
1703 new_instr
= new_vop3
;
1705 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1707 new_instr
->operands
[0] = cmp
->operands
[0];
1708 new_instr
->operands
[1] = cmp
->operands
[1];
1709 new_instr
->definitions
[0] = instr
->definitions
[0];
1711 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1712 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1714 instr
.reset(new_instr
);
1719 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1720 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1721 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1723 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1725 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1728 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1730 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1731 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1733 if (!nan_test
|| !cmp
)
1736 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1737 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1738 std::swap(nan_test
, cmp
);
1739 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1742 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1745 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1747 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1750 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1751 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1752 if (prop_nan0
!= prop_nan1
)
1755 if (nan_test
->isVOP3()) {
1756 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1757 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1761 int constant_operand
= -1;
1762 for (unsigned i
= 0; i
< 2; i
++) {
1763 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1764 constant_operand
= !i
;
1768 if (constant_operand
== -1)
1772 if (cmp
->operands
[constant_operand
].isConstant()) {
1773 constant
= cmp
->operands
[constant_operand
].constantValue();
1774 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1775 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1776 unsigned id
= original_temp_id(ctx
, tmp
);
1777 if (!ctx
.info
[id
].is_constant_or_literal(32))
1779 constant
= ctx
.info
[id
].val
;
1785 memcpy(&constantf
, &constant
, 4);
1786 if (isnan(constantf
))
1789 if (cmp
->operands
[0].isTemp())
1790 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1791 if (cmp
->operands
[1].isTemp())
1792 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1793 decrease_uses(ctx
, nan_test
);
1794 decrease_uses(ctx
, cmp
);
1796 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1797 Instruction
*new_instr
;
1798 if (cmp
->isVOP3()) {
1799 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1800 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1801 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1802 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1803 new_vop3
->clamp
= cmp_vop3
->clamp
;
1804 new_vop3
->omod
= cmp_vop3
->omod
;
1805 new_vop3
->opsel
= cmp_vop3
->opsel
;
1806 new_instr
= new_vop3
;
1808 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1810 new_instr
->operands
[0] = cmp
->operands
[0];
1811 new_instr
->operands
[1] = cmp
->operands
[1];
1812 new_instr
->definitions
[0] = instr
->definitions
[0];
1814 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1815 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1817 instr
.reset(new_instr
);
1822 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1823 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1825 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1827 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1829 if (!instr
->operands
[0].isTemp())
1832 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1836 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1837 if (new_opcode
== aco_opcode::num_opcodes
)
1840 if (cmp
->operands
[0].isTemp())
1841 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1842 if (cmp
->operands
[1].isTemp())
1843 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1844 decrease_uses(ctx
, cmp
);
1846 Instruction
*new_instr
;
1847 if (cmp
->isVOP3()) {
1848 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1849 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1850 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1851 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1852 new_vop3
->clamp
= cmp_vop3
->clamp
;
1853 new_vop3
->omod
= cmp_vop3
->omod
;
1854 new_vop3
->opsel
= cmp_vop3
->opsel
;
1855 new_instr
= new_vop3
;
1857 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1859 new_instr
->operands
[0] = cmp
->operands
[0];
1860 new_instr
->operands
[1] = cmp
->operands
[1];
1861 new_instr
->definitions
[0] = instr
->definitions
[0];
1863 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1864 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1866 instr
.reset(new_instr
);
1871 /* op1(op2(1, 2), 0) if swap = false
1872 * op1(0, op2(1, 2)) if swap = true */
1873 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1874 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1875 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1876 bool *op1_clamp
, uint8_t *op1_omod
,
1877 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1880 if (op1_instr
->opcode
!= op1
)
1883 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1884 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1886 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1889 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1890 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1892 /* don't support inbetween clamp/omod */
1893 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1896 /* get operands and modifiers and check inbetween modifiers */
1897 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1898 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1901 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1902 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1906 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1907 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1910 if (inbetween_opsel
)
1911 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1912 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1916 shuffle
[shuffle_str
[0] - '0'] = 0;
1917 shuffle
[shuffle_str
[1] - '0'] = 1;
1918 shuffle
[shuffle_str
[2] - '0'] = 2;
1920 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1921 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1922 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1923 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1924 *opsel
|= 1 << shuffle
[0];
1926 for (unsigned i
= 0; i
< 2; i
++) {
1927 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1928 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1929 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1930 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1931 *opsel
|= 1 << shuffle
[i
+ 1];
1934 /* check operands */
1935 if (!check_vop3_operands(ctx
, 3, operands
))
1941 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1942 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1943 bool clamp
, unsigned omod
)
1945 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1946 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1947 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1948 new_instr
->clamp
= clamp
;
1949 new_instr
->omod
= omod
;
1950 new_instr
->opsel
= opsel
;
1951 new_instr
->operands
[0] = operands
[0];
1952 new_instr
->operands
[1] = operands
[1];
1953 new_instr
->operands
[2] = operands
[2];
1954 new_instr
->definitions
[0] = instr
->definitions
[0];
1955 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1957 instr
.reset(new_instr
);
1960 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1962 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1963 (label_omod_success
| label_clamp_success
);
1965 for (unsigned swap
= 0; swap
< 2; swap
++) {
1966 if (!((1 << swap
) & ops
))
1969 Operand operands
[3];
1970 bool neg
[3], abs
[3], clamp
;
1971 uint8_t opsel
= 0, omod
= 0;
1972 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1973 instr
.get(), swap
, shuffle
,
1974 operands
, neg
, abs
, &opsel
,
1975 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1976 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1977 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1978 if (omod_clamp
& label_omod_success
)
1979 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1980 if (omod_clamp
& label_clamp_success
)
1981 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1988 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1990 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1993 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1994 (label_omod_success
| label_clamp_success
);
1996 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1997 * max(-min(a, b), c) -> max3(-a, -b, c) */
1998 for (unsigned swap
= 0; swap
< 2; swap
++) {
1999 Operand operands
[3];
2000 bool neg
[3], abs
[3], clamp
;
2001 uint8_t opsel
= 0, omod
= 0;
2003 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
2004 instr
.get(), swap
, "012",
2005 operands
, neg
, abs
, &opsel
,
2006 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
2008 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2011 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2012 if (omod_clamp
& label_omod_success
)
2013 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2014 if (omod_clamp
& label_clamp_success
)
2015 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2022 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
2023 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
2024 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
2025 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
2026 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
2027 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
2028 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2031 if (!instr
->operands
[0].isTemp())
2033 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
2036 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
2039 switch (op2_instr
->opcode
) {
2040 case aco_opcode::s_and_b32
:
2041 case aco_opcode::s_or_b32
:
2042 case aco_opcode::s_xor_b32
:
2043 case aco_opcode::s_and_b64
:
2044 case aco_opcode::s_or_b64
:
2045 case aco_opcode::s_xor_b64
:
2051 /* create instruction */
2052 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
2053 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
2054 ctx
.uses
[instr
->operands
[0].tempId()]--;
2055 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
2057 switch (op2_instr
->opcode
) {
2058 case aco_opcode::s_and_b32
:
2059 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
2061 case aco_opcode::s_or_b32
:
2062 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
2064 case aco_opcode::s_xor_b32
:
2065 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
2067 case aco_opcode::s_and_b64
:
2068 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
2070 case aco_opcode::s_or_b64
:
2071 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
2073 case aco_opcode::s_xor_b64
:
2074 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
2083 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
2084 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
2085 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
2086 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
2087 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2089 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
2092 for (unsigned i
= 0; i
< 2; i
++) {
2093 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2094 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
2096 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
2099 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2100 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2103 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2104 instr
->operands
[0] = instr
->operands
[!i
];
2105 instr
->operands
[1] = op2_instr
->operands
[0];
2106 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2108 switch (instr
->opcode
) {
2109 case aco_opcode::s_and_b32
:
2110 instr
->opcode
= aco_opcode::s_andn2_b32
;
2112 case aco_opcode::s_or_b32
:
2113 instr
->opcode
= aco_opcode::s_orn2_b32
;
2115 case aco_opcode::s_and_b64
:
2116 instr
->opcode
= aco_opcode::s_andn2_b64
;
2118 case aco_opcode::s_or_b64
:
2119 instr
->opcode
= aco_opcode::s_orn2_b64
;
2130 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2131 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2133 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
2136 for (unsigned i
= 0; i
< 2; i
++) {
2137 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2138 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
2139 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
2141 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
2144 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2145 if (shift
< 1 || shift
> 4)
2148 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2149 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2152 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2153 instr
->operands
[1] = instr
->operands
[!i
];
2154 instr
->operands
[0] = op2_instr
->operands
[0];
2155 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2157 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2158 aco_opcode::s_lshl2_add_u32
,
2159 aco_opcode::s_lshl3_add_u32
,
2160 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2167 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2169 if (instr
->usesModifiers())
2172 for (unsigned i
= 0; i
< 2; i
++) {
2173 if (!((1 << i
) & ops
))
2175 if (instr
->operands
[i
].isTemp() &&
2176 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2177 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2179 aco_ptr
<Instruction
> new_instr
;
2180 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2181 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2182 } else if (ctx
.program
->chip_class
>= GFX10
||
2183 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2184 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2188 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2189 new_instr
->definitions
[0] = instr
->definitions
[0];
2190 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2191 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2192 new_instr
->definitions
[1].setHint(vcc
);
2193 new_instr
->operands
[0] = Operand(0u);
2194 new_instr
->operands
[1] = instr
->operands
[!i
];
2195 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2196 instr
= std::move(new_instr
);
2197 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2205 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2208 #define MINMAX(type, gfx9) \
2209 case aco_opcode::v_min_##type:\
2210 case aco_opcode::v_max_##type:\
2211 case aco_opcode::v_med3_##type:\
2212 *min = aco_opcode::v_min_##type;\
2213 *max = aco_opcode::v_max_##type;\
2214 *med3 = aco_opcode::v_med3_##type;\
2215 *min3 = aco_opcode::v_min3_##type;\
2216 *max3 = aco_opcode::v_max3_##type;\
2217 *some_gfx9_only = gfx9;\
2231 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2232 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2233 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2234 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2236 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2237 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2238 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2239 aco_opcode other_op
;
2240 if (instr
->opcode
== min
)
2242 else if (instr
->opcode
== max
)
2247 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2248 (label_omod_success
| label_clamp_success
);
2250 for (unsigned swap
= 0; swap
< 2; swap
++) {
2251 Operand operands
[3];
2252 bool neg
[3], abs
[3], clamp
;
2253 uint8_t opsel
= 0, omod
= 0;
2254 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2255 "012", operands
, neg
, abs
, &opsel
,
2256 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2257 int const0_idx
= -1, const1_idx
= -1;
2258 uint32_t const0
= 0, const1
= 0;
2259 for (int i
= 0; i
< 3; i
++) {
2261 if (operands
[i
].isConstant()) {
2262 val
= operands
[i
].constantValue();
2263 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal(32)) {
2264 val
= ctx
.info
[operands
[i
].tempId()].val
;
2268 if (const0_idx
>= 0) {
2276 if (const0_idx
< 0 || const1_idx
< 0)
2279 if (opsel
& (1 << const0_idx
))
2281 if (opsel
& (1 << const1_idx
))
2284 int lower_idx
= const0_idx
;
2286 case aco_opcode::v_min_f32
:
2287 case aco_opcode::v_min_f16
: {
2288 float const0_f
, const1_f
;
2289 if (min
== aco_opcode::v_min_f32
) {
2290 memcpy(&const0_f
, &const0
, 4);
2291 memcpy(&const1_f
, &const1
, 4);
2293 const0_f
= _mesa_half_to_float(const0
);
2294 const1_f
= _mesa_half_to_float(const1
);
2296 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2297 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2298 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2299 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2300 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2303 case aco_opcode::v_min_u32
: {
2304 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2307 case aco_opcode::v_min_u16
: {
2308 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2311 case aco_opcode::v_min_i32
: {
2312 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2313 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2314 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2317 case aco_opcode::v_min_i16
: {
2318 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2319 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2320 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2326 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2328 if (instr
->opcode
== min
) {
2329 if (upper_idx
!= 0 || lower_idx
== 0)
2332 if (upper_idx
== 0 || lower_idx
!= 0)
2336 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2337 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2338 if (omod_clamp
& label_omod_success
)
2339 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2340 if (omod_clamp
& label_clamp_success
)
2341 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2351 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2353 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2354 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2355 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2357 /* find candidates and create the set of sgprs already read */
2358 unsigned sgpr_ids
[2] = {0, 0};
2359 uint32_t operand_mask
= 0;
2360 bool has_literal
= false;
2361 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2362 if (instr
->operands
[i
].isLiteral())
2364 if (!instr
->operands
[i
].isTemp())
2366 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2367 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2368 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2370 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2371 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2372 operand_mask
|= 1u << i
;
2374 unsigned max_sgprs
= 1;
2375 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2380 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2382 /* keep on applying sgprs until there is nothing left to be done */
2383 while (operand_mask
) {
2384 uint32_t sgpr_idx
= 0;
2385 uint32_t sgpr_info_id
= 0;
2386 uint32_t mask
= operand_mask
;
2389 unsigned i
= u_bit_scan(&mask
);
2390 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2391 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2393 sgpr_info_id
= instr
->operands
[i
].tempId();
2396 operand_mask
&= ~(1u << sgpr_idx
);
2398 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2399 * definitively beneficial.
2400 * TODO: this is too conservative because later the use count could be reduced to 1 */
2401 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2404 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2405 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2406 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2409 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2410 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2411 } else if (can_swap_operands(instr
)) {
2412 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2413 instr
->operands
[0] = Operand(sgpr
);
2414 /* swap bits using a 4-entry LUT */
2415 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2416 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2417 } else if (can_use_VOP3(ctx
, instr
)) {
2418 to_VOP3(ctx
, instr
);
2419 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2425 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2426 ctx
.uses
[sgpr_info_id
]--;
2427 ctx
.uses
[sgpr
.id()]++;
2431 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2433 /* check if we could apply omod on predecessor */
2434 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2435 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2436 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2438 unsigned idx
= op0
? 0 : 1;
2439 /* omod was successfully applied */
2440 /* if the omod instruction is v_mad, we also have to change the original add */
2441 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2442 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2443 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2444 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2445 add_instr
->definitions
[0] = instr
->definitions
[0];
2448 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2449 /* check if we have an additional clamp modifier */
2450 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2451 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2452 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2453 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2455 /* change definition ssa-id of modified instruction */
2456 omod_instr
->definitions
[0] = instr
->definitions
[0];
2458 /* change the definition of instr to something unused, e.g. the original omod def */
2459 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2460 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2463 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2464 /* in all other cases, label this instruction as option for multiply-add */
2465 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2469 /* check if we could apply clamp on predecessor */
2470 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2471 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2473 bool found_zero
= false, found_one
= false;
2474 for (unsigned i
= 0; i
< 3; i
++)
2476 if (instr
->operands
[i
].constantEquals(0))
2478 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2483 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2484 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2485 /* clamp was successfully applied */
2486 /* if the clamp instruction is v_mad, we also have to change the original add */
2487 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2488 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2489 add_instr
->definitions
[0] = instr
->definitions
[0];
2491 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2492 /* change definition ssa-id of modified instruction */
2493 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2495 /* change the definition of instr to something unused, e.g. the original omod def */
2496 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2497 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2502 /* omod has no effect if denormals are enabled */
2503 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2504 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2505 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2506 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2507 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2508 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2509 to_VOP3(ctx
, instr
);
2510 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2511 def_info
.set_omod_success(instr
.get());
2512 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2513 to_VOP3(ctx
, instr
);
2514 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2515 def_info
.set_omod_success(instr
.get());
2516 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2517 to_VOP3(ctx
, instr
);
2518 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2519 def_info
.set_omod_success(instr
.get());
2520 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2521 to_VOP3(ctx
, instr
);
2522 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2523 def_info
.set_clamp_success(instr
.get());
2530 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2531 // this would mean that we'd have to fix the instruction uses while value propagation
2533 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2535 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2538 if (instr
->isVALU()) {
2539 if (can_apply_sgprs(instr
))
2540 apply_sgprs(ctx
, instr
);
2541 if (apply_omod_clamp(ctx
, block
, instr
))
2545 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2546 instr
->definitions
[0].setHint(vcc
);
2549 /* TODO: There are still some peephole optimizations that could be done:
2550 * - abs(a - b) -> s_absdiff_i32
2551 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2552 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2553 * These aren't probably too interesting though.
2554 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2555 * probably more useful than the previously mentioned optimizations.
2556 * The various comparison optimizations also currently only work with 32-bit
2559 /* neg(mul(a, b)) -> mul(neg(a), b) */
2560 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2561 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2563 if (!ctx
.info
[val
.id()].is_mul())
2566 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2568 if (mul_instr
->operands
[0].isLiteral())
2570 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2573 /* convert to mul(neg(a), b) */
2574 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2575 Definition def
= instr
->definitions
[0];
2576 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2577 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2578 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2579 instr
->operands
[0] = mul_instr
->operands
[0];
2580 instr
->operands
[1] = mul_instr
->operands
[1];
2581 instr
->definitions
[0] = def
;
2582 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2583 if (mul_instr
->isVOP3()) {
2584 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2585 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2586 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2587 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2588 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2589 new_mul
->omod
= mul
->omod
;
2591 new_mul
->neg
[0] ^= true;
2592 new_mul
->clamp
= false;
2594 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2598 /* combine mul+add -> mad */
2599 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2600 instr
->opcode
== aco_opcode::v_sub_f32
||
2601 instr
->opcode
== aco_opcode::v_subrev_f32
;
2602 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2603 instr
->opcode
== aco_opcode::v_sub_f16
||
2604 instr
->opcode
== aco_opcode::v_subrev_f16
;
2605 if (mad16
|| mad32
) {
2606 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2607 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2608 if (need_fma
&& instr
->definitions
[0].isPrecise())
2610 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2613 uint32_t uses_src0
= UINT32_MAX
;
2614 uint32_t uses_src1
= UINT32_MAX
;
2615 Instruction
* mul_instr
= nullptr;
2616 unsigned add_op_idx
;
2617 /* check if any of the operands is a multiplication */
2618 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2619 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2620 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2621 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2622 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2623 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2625 /* find the 'best' mul instruction to combine with the add */
2626 if (uses_src0
< uses_src1
) {
2627 mul_instr
= op0_info
->instr
;
2629 } else if (uses_src1
< uses_src0
) {
2630 mul_instr
= op1_info
->instr
;
2632 } else if (uses_src0
!= UINT32_MAX
) {
2633 /* tiebreaker: quite random what to pick */
2634 if (op0_info
->instr
->operands
[0].isLiteral()) {
2635 mul_instr
= op1_info
->instr
;
2638 mul_instr
= op0_info
->instr
;
2643 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2644 bool neg
[3] = {false, false, false};
2645 bool abs
[3] = {false, false, false};
2648 op
[0] = mul_instr
->operands
[0];
2649 op
[1] = mul_instr
->operands
[1];
2650 op
[2] = instr
->operands
[add_op_idx
];
2651 // TODO: would be better to check this before selecting a mul instr?
2652 if (!check_vop3_operands(ctx
, 3, op
))
2655 if (mul_instr
->isVOP3()) {
2656 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2657 neg
[0] = vop3
->neg
[0];
2658 neg
[1] = vop3
->neg
[1];
2659 abs
[0] = vop3
->abs
[0];
2660 abs
[1] = vop3
->abs
[1];
2661 /* we cannot use these modifiers between mul and add */
2662 if (vop3
->clamp
|| vop3
->omod
)
2666 /* convert to mad */
2667 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2668 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2670 ctx
.uses
[op
[0].tempId()]++;
2672 ctx
.uses
[op
[1].tempId()]++;
2675 if (instr
->isVOP3()) {
2676 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2677 neg
[2] = vop3
->neg
[add_op_idx
];
2678 abs
[2] = vop3
->abs
[add_op_idx
];
2680 clamp
= vop3
->clamp
;
2681 /* abs of the multiplication result */
2682 if (vop3
->abs
[1 - add_op_idx
]) {
2688 /* neg of the multiplication result */
2689 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2691 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2692 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2693 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2694 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2696 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2698 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2699 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2701 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2702 for (unsigned i
= 0; i
< 3; i
++)
2704 mad
->operands
[i
] = op
[i
];
2705 mad
->neg
[i
] = neg
[i
];
2706 mad
->abs
[i
] = abs
[i
];
2710 mad
->definitions
[0] = instr
->definitions
[0];
2712 /* mark this ssa_def to be re-checked for profitability and literals */
2713 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2714 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2715 instr
.reset(mad
.release());
2719 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2720 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2721 for (unsigned i
= 0; i
< 2; i
++) {
2722 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2723 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2724 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2725 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2726 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2728 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2729 new_instr
->operands
[0] = Operand(0u);
2730 new_instr
->operands
[1] = instr
->operands
[!i
];
2731 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2732 new_instr
->definitions
[0] = instr
->definitions
[0];
2733 instr
.reset(new_instr
.release());
2734 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2738 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2739 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2740 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2741 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2742 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2743 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2744 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2745 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2746 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2747 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2748 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2749 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2750 else if (ctx
.program
->chip_class
>= GFX9
) {
2751 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2752 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2753 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2754 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2755 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2756 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2757 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2759 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2760 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2761 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2762 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2763 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2764 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2765 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2766 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2767 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2768 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2769 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2770 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2771 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2772 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2773 combine_salu_lshl_add(ctx
, instr
);
2774 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2775 combine_salu_not_bitwise(ctx
, instr
);
2776 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2777 if (combine_inverse_comparison(ctx
, instr
)) ;
2778 else combine_salu_not_bitwise(ctx
, instr
);
2779 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2780 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2781 if (combine_ordering_test(ctx
, instr
)) ;
2782 else if (combine_comparison_ordering(ctx
, instr
)) ;
2783 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2784 else combine_salu_n2(ctx
, instr
);
2786 aco_opcode min
, max
, min3
, max3
, med3
;
2787 bool some_gfx9_only
;
2788 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2789 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2790 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2791 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2796 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2798 switch (instr
->opcode
) {
2799 case aco_opcode::s_and_b32
:
2800 case aco_opcode::s_and_b64
:
2801 instr
->opcode
= aco_opcode::s_and_b32
;
2803 case aco_opcode::s_or_b32
:
2804 case aco_opcode::s_or_b64
:
2805 instr
->opcode
= aco_opcode::s_or_b32
;
2807 case aco_opcode::s_xor_b32
:
2808 case aco_opcode::s_xor_b64
:
2809 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2812 /* Don't transform other instructions. They are very unlikely to appear here. */
2816 for (Operand
&op
: instr
->operands
) {
2817 ctx
.uses
[op
.tempId()]--;
2819 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2820 /* Just use the uniform boolean temp. */
2821 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2822 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2823 /* Use the SCC definition of the predecessor instruction.
2824 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2825 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2827 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2828 assert(pred_instr
->definitions
.size() >= 2);
2829 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2830 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2832 unreachable("Invalid operand on uniform bitwise instruction.");
2835 ctx
.uses
[op
.tempId()]++;
2838 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2839 assert(instr
->operands
[0].regClass() == s1
);
2840 assert(instr
->operands
[1].regClass() == s1
);
2844 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2846 const uint32_t threshold
= 4;
2848 if (is_dead(ctx
.uses
, instr
.get())) {
2853 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2854 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2855 unsigned num_used
= 0;
2857 unsigned split_offset
= 0;
2858 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2859 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2862 split_offset
= offset
;
2866 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2867 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2868 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2872 for (Operand
& vec_op
: vec
->operands
) {
2873 if (off
== split_offset
) {
2877 off
+= vec_op
.bytes();
2879 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2880 ctx
.uses
[instr
->operands
[0].tempId()]--;
2881 for (Operand
& vec_op
: vec
->operands
) {
2882 if (vec_op
.isTemp())
2883 ctx
.uses
[vec_op
.tempId()]--;
2886 ctx
.uses
[op
.tempId()]++;
2888 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2889 extract
->operands
[0] = op
;
2890 extract
->definitions
[0] = instr
->definitions
[idx
];
2891 instr
.reset(extract
.release());
2897 if (!done
&& num_used
== 1 &&
2898 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2899 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2900 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2901 extract
->operands
[0] = instr
->operands
[0];
2902 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2903 extract
->definitions
[0] = instr
->definitions
[idx
];
2904 instr
.reset(extract
.release());
2908 mad_info
* mad_info
= NULL
;
2909 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2910 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2911 /* re-check mad instructions */
2912 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2913 ctx
.uses
[mad_info
->mul_temp_id
]++;
2914 if (instr
->operands
[0].isTemp())
2915 ctx
.uses
[instr
->operands
[0].tempId()]--;
2916 if (instr
->operands
[1].isTemp())
2917 ctx
.uses
[instr
->operands
[1].tempId()]--;
2918 instr
.swap(mad_info
->add_instr
);
2921 /* check literals */
2922 else if (!instr
->usesModifiers()) {
2923 /* FMA can only take literals on GFX10+ */
2924 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2925 ctx
.program
->chip_class
< GFX10
)
2928 bool sgpr_used
= false;
2929 uint32_t literal_idx
= 0;
2930 uint32_t literal_uses
= UINT32_MAX
;
2931 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2933 if (instr
->operands
[i
].isConstant() && i
> 0) {
2934 literal_uses
= UINT32_MAX
;
2937 if (!instr
->operands
[i
].isTemp())
2939 unsigned bits
= get_operand_size(instr
, i
);
2940 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2941 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2942 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
)) {
2943 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2946 literal_uses
= UINT32_MAX
;
2949 /* don't break because we still need to check constants */
2950 } else if (!sgpr_used
&&
2951 ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
) &&
2952 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2953 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2958 /* Limit the number of literals to apply to not increase the code
2959 * size too much, but always apply literals for v_mad->v_madak
2960 * because both instructions are 64-bit and this doesn't increase
2962 * TODO: try to apply the literals earlier to lower the number of
2963 * uses below threshold
2965 if (literal_uses
< threshold
|| literal_idx
== 2) {
2966 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2967 mad_info
->check_literal
= true;
2968 mad_info
->literal_idx
= literal_idx
;
2974 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2975 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2976 instr
->operands
.size() &&
2977 instr
->operands
[0].isTemp()) {
2978 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2980 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2981 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2982 instr
->operands
[2].isTemp()) {
2983 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2986 /* check for literals */
2987 if (!instr
->isSALU() && !instr
->isVALU())
2990 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2991 if (instr
->definitions
.size() &&
2992 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2993 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2994 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2996 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2997 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2998 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2999 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
3000 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
3001 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
3007 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
3008 return; /* some encodings can't ever take literals */
3010 /* we do not apply the literals yet as we don't know if it is profitable */
3011 Operand
current_literal(s1
);
3013 unsigned literal_id
= 0;
3014 unsigned literal_uses
= UINT32_MAX
;
3015 Operand
literal(s1
);
3016 unsigned num_operands
= 1;
3017 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
3018 num_operands
= instr
->operands
.size();
3019 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
3020 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
3023 unsigned sgpr_ids
[2] = {0, 0};
3024 bool is_literal_sgpr
= false;
3027 /* choose a literal to apply */
3028 for (unsigned i
= 0; i
< num_operands
; i
++) {
3029 Operand op
= instr
->operands
[i
];
3030 unsigned bits
= get_operand_size(instr
, i
);
3032 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
3033 op
.tempId() != sgpr_ids
[0])
3034 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
3036 if (op
.isLiteral()) {
3037 current_literal
= op
;
3039 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal(bits
)) {
3043 if (!alu_can_accept_constant(instr
->opcode
, i
))
3046 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
3047 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
3049 literal
= Operand(ctx
.info
[op
.tempId()].val
);
3050 literal_uses
= ctx
.uses
[op
.tempId()];
3051 literal_id
= op
.tempId();
3054 mask
|= (op
.tempId() == literal_id
) << i
;
3058 /* don't go over the constant bus limit */
3059 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
3060 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
3061 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
3062 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
3063 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
3064 const_bus_limit
= 2;
3066 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
3067 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
3070 if (literal_id
&& literal_uses
< threshold
&&
3071 (current_literal
.isUndefined() ||
3072 (current_literal
.size() == literal
.size() &&
3073 current_literal
.constantValue() == literal
.constantValue()))) {
3074 /* mark the literal to be applied */
3076 unsigned i
= u_bit_scan(&mask
);
3077 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
3078 ctx
.uses
[instr
->operands
[i
].tempId()]--;
3084 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
3086 /* Cleanup Dead Instructions */
3090 /* apply literals on MAD */
3091 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
3092 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
3093 if (info
->check_literal
&&
3094 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
3095 aco_ptr
<Instruction
> new_mad
;
3097 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
3098 if (instr
->opcode
== aco_opcode::v_fma_f32
)
3099 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
3100 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
3101 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
3102 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
3103 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
3105 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
3106 if (info
->literal_idx
== 2) { /* add literal -> madak */
3107 new_mad
->operands
[0] = instr
->operands
[0];
3108 new_mad
->operands
[1] = instr
->operands
[1];
3109 } else { /* mul literal -> madmk */
3110 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
3111 new_mad
->operands
[1] = instr
->operands
[2];
3113 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
3114 new_mad
->definitions
[0] = instr
->definitions
[0];
3115 ctx
.instructions
.emplace_back(std::move(new_mad
));
3120 /* apply literals on other SALU/VALU */
3121 if (instr
->isSALU() || instr
->isVALU()) {
3122 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
3123 Operand op
= instr
->operands
[i
];
3124 unsigned bits
= get_operand_size(instr
, i
);
3125 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal(bits
) && ctx
.uses
[op
.tempId()] == 0) {
3126 Operand
literal(ctx
.info
[op
.tempId()].val
);
3127 if (instr
->isVALU() && i
> 0)
3128 to_VOP3(ctx
, instr
);
3129 instr
->operands
[i
] = literal
;
3134 ctx
.instructions
.emplace_back(std::move(instr
));
3138 void optimize(Program
* program
)
3141 ctx
.program
= program
;
3142 std::vector
<ssa_info
> info(program
->peekAllocationId());
3143 ctx
.info
= info
.data();
3145 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
3146 for (Block
& block
: program
->blocks
) {
3147 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3148 label_instruction(ctx
, block
, instr
);
3151 ctx
.uses
= dead_code_analysis(program
);
3153 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3154 for (Block
& block
: program
->blocks
) {
3155 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3156 combine_instruction(ctx
, block
, instr
);
3159 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3160 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3161 Block
* block
= &(*it
);
3162 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3163 select_instruction(ctx
, *it
);
3166 /* 4. Add literals to instructions */
3167 for (Block
& block
: program
->blocks
) {
3168 ctx
.instructions
.clear();
3169 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3170 apply_literals(ctx
, instr
);
3171 block
.instructions
.swap(ctx
.instructions
);