2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
59 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
, bool vop3
)
60 : add_instr(std::move(instr
)), mul_temp_id(id
), needs_vop3(vop3
), check_literal(false) {}
65 label_constant
= 1 << 1,
70 label_literal
= 1 << 6,
74 label_omod5
= 1 << 10,
75 label_omod_success
= 1 << 11,
76 label_clamp
= 1 << 12,
77 label_clamp_success
= 1 << 13,
78 label_undefined
= 1 << 14,
81 label_add_sub
= 1 << 17,
82 label_bitwise
= 1 << 18,
83 label_minmax
= 1 << 19,
87 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
| label_add_sub
| label_bitwise
| label_minmax
| label_fcmp
;
88 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
;
89 static constexpr uint32_t val_labels
= label_constant
| label_literal
| label_mad
;
99 void add_label(Label new_label
)
101 /* Since all labels which use "instr" use it for the same thing
102 * (indicating the defining instruction), there is no need to clear
103 * any other instr labels. */
104 if (new_label
& instr_labels
)
105 label
&= ~temp_labels
; /* instr and temp alias */
107 if (new_label
& temp_labels
) {
108 label
&= ~temp_labels
;
109 label
&= ~instr_labels
; /* instr and temp alias */
112 if (new_label
& val_labels
)
113 label
&= ~val_labels
;
118 void set_vec(Instruction
* vec
)
120 add_label(label_vec
);
126 return label
& label_vec
;
129 void set_constant(uint32_t constant
)
131 add_label(label_constant
);
137 return label
& label_constant
;
140 void set_abs(Temp abs_temp
)
142 add_label(label_abs
);
148 return label
& label_abs
;
151 void set_neg(Temp neg_temp
)
153 add_label(label_neg
);
159 return label
& label_neg
;
162 void set_neg_abs(Temp neg_abs_temp
)
164 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
168 void set_mul(Instruction
* mul
)
170 add_label(label_mul
);
176 return label
& label_mul
;
179 void set_temp(Temp tmp
)
181 add_label(label_temp
);
187 return label
& label_temp
;
190 void set_literal(uint32_t lit
)
192 add_label(label_literal
);
198 return label
& label_literal
;
201 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
203 add_label(label_mad
);
210 return label
& label_mad
;
215 add_label(label_omod2
);
220 return label
& label_omod2
;
225 add_label(label_omod4
);
230 return label
& label_omod4
;
235 add_label(label_omod5
);
240 return label
& label_omod5
;
243 void set_omod_success(Instruction
* omod_instr
)
245 add_label(label_omod_success
);
249 bool is_omod_success()
251 return label
& label_omod_success
;
256 add_label(label_clamp
);
261 return label
& label_clamp
;
264 void set_clamp_success(Instruction
* clamp_instr
)
266 add_label(label_clamp_success
);
270 bool is_clamp_success()
272 return label
& label_clamp_success
;
277 add_label(label_undefined
);
282 return label
& label_undefined
;
285 void set_vcc(Temp vcc
)
287 add_label(label_vcc
);
293 return label
& label_vcc
;
296 bool is_constant_or_literal()
298 return is_constant() || is_literal();
301 void set_b2f(Temp val
)
303 add_label(label_b2f
);
309 return label
& label_b2f
;
312 void set_add_sub(Instruction
*add_sub_instr
)
314 add_label(label_add_sub
);
315 instr
= add_sub_instr
;
320 return label
& label_add_sub
;
323 void set_bitwise(Instruction
*bitwise_instr
)
325 add_label(label_bitwise
);
326 instr
= bitwise_instr
;
331 return label
& label_bitwise
;
334 void set_minmax(Instruction
*minmax_instr
)
336 add_label(label_minmax
);
337 instr
= minmax_instr
;
342 return label
& label_minmax
;
345 void set_fcmp(Instruction
*fcmp_instr
)
347 add_label(label_fcmp
);
353 return label
& label_fcmp
;
360 std::vector
<aco_ptr
<Instruction
>> instructions
;
362 std::pair
<uint32_t,Temp
> last_literal
;
363 std::vector
<mad_info
> mad_infos
;
364 std::vector
<uint16_t> uses
;
367 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
369 if (instr
->operands
[0].isConstant() ||
370 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
373 switch (instr
->opcode
) {
374 case aco_opcode::v_add_f32
:
375 case aco_opcode::v_mul_f32
:
376 case aco_opcode::v_or_b32
:
377 case aco_opcode::v_and_b32
:
378 case aco_opcode::v_xor_b32
:
379 case aco_opcode::v_max_f32
:
380 case aco_opcode::v_min_f32
:
381 case aco_opcode::v_cmp_eq_f32
:
382 case aco_opcode::v_cmp_lg_f32
:
384 case aco_opcode::v_sub_f32
:
385 instr
->opcode
= aco_opcode::v_subrev_f32
;
387 case aco_opcode::v_cmp_lt_f32
:
388 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
390 case aco_opcode::v_cmp_ge_f32
:
391 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
393 case aco_opcode::v_cmp_lt_i32
:
394 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
401 bool can_use_VOP3(aco_ptr
<Instruction
>& instr
)
403 if (instr
->operands
.size() && instr
->operands
[0].isLiteral())
406 if (instr
->isDPP() || instr
->isSDWA())
409 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
410 instr
->opcode
!= aco_opcode::v_madak_f32
&&
411 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
412 instr
->opcode
!= aco_opcode::v_madak_f16
;
415 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
417 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
418 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
419 instr
->opcode
!= aco_opcode::v_writelane_b32
;
422 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
427 assert(!instr
->operands
[0].isLiteral());
428 aco_ptr
<Instruction
> tmp
= std::move(instr
);
429 Format format
= asVOP3(tmp
->format
);
430 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
431 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
432 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
433 instr
->definitions
[i
] = tmp
->definitions
[i
];
434 if (instr
->definitions
[i
].isTemp()) {
435 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
436 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
437 info
.instr
= instr
.get();
442 bool valu_can_accept_literal(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
444 // TODO: VOP3 can take a literal on GFX10
445 return !instr
->isSDWA() && !instr
->isDPP() && !instr
->isVOP3();
448 /* only covers special cases */
449 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
451 switch (instr
->opcode
) {
452 case aco_opcode::v_interp_p2_f32
:
453 case aco_opcode::v_mac_f32
:
454 case aco_opcode::v_writelane_b32
:
455 case aco_opcode::v_cndmask_b32
:
457 case aco_opcode::s_addk_i32
:
458 case aco_opcode::s_mulk_i32
:
459 case aco_opcode::p_wqm
:
460 case aco_opcode::p_extract_vector
:
461 case aco_opcode::p_split_vector
:
462 case aco_opcode::v_readlane_b32
:
463 case aco_opcode::v_readfirstlane_b32
:
466 if ((instr
->format
== Format::MUBUF
||
467 instr
->format
== Format::MIMG
) &&
468 instr
->definitions
.size() == 1 &&
469 instr
->operands
.size() == 4) {
476 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
478 Operand op
= instr
->operands
[op_index
];
482 Temp tmp
= op
.getTemp();
483 if (!ctx
.info
[tmp
.id()].is_add_sub())
486 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
488 switch (add_instr
->opcode
) {
489 case aco_opcode::v_add_u32
:
490 case aco_opcode::v_add_co_u32
:
491 case aco_opcode::s_add_i32
:
492 case aco_opcode::s_add_u32
:
498 for (unsigned i
= 0; i
< 2; i
++) {
499 if (add_instr
->operands
[i
].isConstant()) {
500 *offset
= add_instr
->operands
[i
].constantValue();
501 } else if (add_instr
->operands
[i
].isTemp() &&
502 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
503 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
507 if (!add_instr
->operands
[!i
].isTemp())
510 uint32_t offset2
= 0;
511 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
514 *base
= add_instr
->operands
[!i
].getTemp();
522 void label_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
524 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
525 ASSERTED
bool all_const
= false;
526 for (Operand
& op
: instr
->operands
)
527 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
528 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
531 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
533 if (!instr
->operands
[i
].isTemp())
536 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
537 /* propagate undef */
538 if (info
.is_undefined() && is_phi(instr
))
539 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
540 /* propagate reg->reg of same type */
541 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
542 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
543 info
= ctx
.info
[info
.temp
.id()];
546 /* SALU / PSEUDO: propagate inline constants */
547 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
548 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
549 instr
->operands
[i
].setTemp(info
.temp
);
550 info
= ctx
.info
[info
.temp
.id()];
551 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
552 /* propagate vgpr if it can take it */
553 switch (instr
->opcode
) {
554 case aco_opcode::p_create_vector
:
555 case aco_opcode::p_split_vector
:
556 case aco_opcode::p_extract_vector
:
557 case aco_opcode::p_phi
: {
558 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
559 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
561 instr
->operands
[i
] = Operand(info
.temp
);
562 info
= ctx
.info
[info
.temp
.id()];
570 if ((info
.is_constant() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
571 instr
->operands
[i
] = Operand(info
.val
);
576 /* VALU: propagate neg, abs & inline constants */
577 else if (instr
->isVALU()) {
578 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
579 instr
->operands
[i
].setTemp(info
.temp
);
580 info
= ctx
.info
[info
.temp
.id()];
582 if (info
.is_abs() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
585 instr
->operands
[i
] = Operand(info
.temp
);
587 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
589 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
591 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
592 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
593 instr
->operands
[i
].setTemp(info
.temp
);
595 } else if (info
.is_neg() && (can_use_VOP3(instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
598 instr
->operands
[i
].setTemp(info
.temp
);
600 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
602 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
605 if (info
.is_constant() && can_accept_constant(instr
, i
)) {
606 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
608 instr
->operands
[i
] = Operand(info
.val
);
610 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
611 instr
->operands
[i
] = instr
->operands
[0];
612 instr
->operands
[0] = Operand(info
.val
);
614 } else if (can_use_VOP3(instr
)) {
616 instr
->operands
[i
] = Operand(info
.val
);
622 /* MUBUF: propagate constants and combine additions */
623 else if (instr
->format
== Format::MUBUF
) {
624 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
627 while (info
.is_temp())
628 info
= ctx
.info
[info
.temp
.id()];
630 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
631 assert(!mubuf
->idxen
);
632 instr
->operands
[i
] = Operand(v1
);
633 mubuf
->offset
+= info
.val
;
634 mubuf
->offen
= false;
636 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
637 instr
->operands
[2] = Operand((uint32_t) 0);
638 mubuf
->offset
+= info
.val
;
640 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
641 assert(!mubuf
->idxen
);
642 instr
->operands
[i
].setTemp(base
);
643 mubuf
->offset
+= offset
;
645 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
646 instr
->operands
[i
].setTemp(base
);
647 mubuf
->offset
+= offset
;
652 /* DS: combine additions */
653 else if (instr
->format
== Format::DS
) {
655 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
658 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass()) {
659 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
) {
660 if (offset
% 4 == 0 &&
661 ds
->offset0
+ (offset
>> 2) <= 255 &&
662 ds
->offset1
+ (offset
>> 2) <= 255) {
663 instr
->operands
[i
].setTemp(base
);
664 ds
->offset0
+= offset
>> 2;
665 ds
->offset1
+= offset
>> 2;
668 if (ds
->offset0
+ offset
<= 65535) {
669 instr
->operands
[i
].setTemp(base
);
670 ds
->offset0
+= offset
;
676 /* SMEM: propagate constants and combine additions */
677 else if (instr
->format
== Format::SMEM
) {
679 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
682 if (i
== 1 && info
.is_constant_or_literal() && info
.val
<= 0xFFFFF) {
683 instr
->operands
[i
] = Operand(info
.val
);
685 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
686 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
688 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
689 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
693 smem
->operands
[1] = Operand(offset
);
694 smem
->operands
.back() = Operand(base
);
696 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
697 new_instr
->operands
[0] = smem
->operands
[0];
698 new_instr
->operands
[1] = Operand(offset
);
699 if (smem
->definitions
.empty())
700 new_instr
->operands
[2] = smem
->operands
[2];
701 new_instr
->operands
.back() = Operand(base
);
702 if (!smem
->definitions
.empty())
703 new_instr
->definitions
[0] = smem
->definitions
[0];
704 instr
.reset(new_instr
);
705 smem
= static_cast<SMEM_instruction
*>(instr
.get());
712 /* if this instruction doesn't define anything, return */
713 if (instr
->definitions
.empty())
716 switch (instr
->opcode
) {
717 case aco_opcode::p_create_vector
: {
718 unsigned num_ops
= instr
->operands
.size();
719 for (const Operand
& op
: instr
->operands
) {
720 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
721 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
723 if (num_ops
!= instr
->operands
.size()) {
724 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
725 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
726 instr
->definitions
[0] = old_vec
->definitions
[0];
728 for (Operand
& old_op
: old_vec
->operands
) {
729 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
730 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++)
731 instr
->operands
[k
++] = ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
733 instr
->operands
[k
++] = old_op
;
736 assert(k
== num_ops
);
738 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
739 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
740 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
741 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
744 case aco_opcode::p_split_vector
: {
745 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
747 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
748 assert(instr
->definitions
.size() == vec
->operands
.size());
749 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
750 Operand vec_op
= vec
->operands
[i
];
751 if (vec_op
.isConstant()) {
752 if (vec_op
.isLiteral())
753 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
755 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
757 assert(vec_op
.isTemp());
758 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
763 case aco_opcode::p_extract_vector
: { /* mov */
764 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
766 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
767 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size()) { /* TODO: what about 64bit or other combinations? */
769 /* convert this extract into a mov instruction */
770 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
771 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
772 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
773 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
774 instr
->opcode
= opcode
;
775 instr
->format
= format
;
776 instr
->operands
= {instr
->operands
.begin(), 1 };
777 instr
->operands
[0] = vec_op
;
779 if (vec_op
.isConstant()) {
780 if (vec_op
.isLiteral())
781 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
783 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
785 assert(vec_op
.isTemp());
786 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
791 case aco_opcode::s_mov_b32
: /* propagate */
792 case aco_opcode::s_mov_b64
:
793 case aco_opcode::v_mov_b32
:
794 case aco_opcode::p_as_uniform
:
795 if (instr
->definitions
[0].isFixed()) {
796 /* don't copy-propagate copies into fixed registers */
797 } else if (instr
->operands
[0].isConstant()) {
798 if (instr
->operands
[0].isLiteral())
799 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
801 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
802 } else if (instr
->isDPP()) {
804 } else if (instr
->operands
[0].isTemp()) {
805 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
807 assert(instr
->operands
[0].isFixed());
810 case aco_opcode::p_is_helper
:
811 if (!ctx
.program
->needs_wqm
)
812 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
814 case aco_opcode::s_movk_i32
: {
815 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
816 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
817 if (v
<= 64 || v
>= 0xfffffff0)
818 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
820 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
823 case aco_opcode::v_bfrev_b32
:
824 case aco_opcode::s_brev_b32
: {
825 if (instr
->operands
[0].isConstant()) {
826 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
827 if (v
<= 64 || v
>= 0xfffffff0)
828 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
830 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
834 case aco_opcode::s_bfm_b32
: {
835 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
836 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
837 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
838 uint32_t v
= ((1u << size
) - 1u) << start
;
839 if (v
<= 64 || v
>= 0xfffffff0)
840 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
842 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
845 case aco_opcode::v_mul_f32
: { /* omod */
846 /* TODO: try to move the negate/abs modifier to the consumer instead */
847 if (instr
->isVOP3()) {
848 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
849 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->neg
[0] || vop3
->neg
[1] || vop3
->omod
|| vop3
->clamp
)
853 for (unsigned i
= 0; i
< 2; i
++) {
854 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
855 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
856 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2();
857 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
858 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4();
859 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
860 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5();
861 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000) { /* 1.0 */
862 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
871 case aco_opcode::v_and_b32
: /* abs */
872 if (instr
->operands
[0].constantEquals(0x7FFFFFFF) && instr
->operands
[1].isTemp())
873 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
875 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
877 case aco_opcode::v_xor_b32
: { /* neg */
878 if (instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
879 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
880 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
882 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
883 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
884 instr
->opcode
= aco_opcode::v_or_b32
;
885 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
887 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
891 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
895 case aco_opcode::v_med3_f32
: { /* clamp */
896 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
897 if (vop3
->abs
[0] || vop3
->neg
[0] || vop3
->opsel
[0] ||
898 vop3
->abs
[1] || vop3
->neg
[1] || vop3
->opsel
[1] ||
899 vop3
->abs
[2] || vop3
->neg
[2] || vop3
->opsel
[2] ||
904 bool found_zero
= false, found_one
= false;
905 for (unsigned i
= 0; i
< 3; i
++)
907 if (instr
->operands
[i
].constantEquals(0))
909 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
914 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
915 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp();
919 case aco_opcode::v_cndmask_b32
:
920 if (instr
->operands
[0].constantEquals(0) &&
921 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
922 instr
->operands
[2].isTemp())
923 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
924 else if (instr
->operands
[0].constantEquals(0) &&
925 instr
->operands
[1].constantEquals(0x3f800000u
) &&
926 instr
->operands
[2].isTemp())
927 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
929 case aco_opcode::v_cmp_lg_u32
:
930 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
931 instr
->operands
[0].constantEquals(0) &&
932 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
933 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
935 case aco_opcode::p_phi
:
936 case aco_opcode::p_linear_phi
: {
937 /* lower_bool_phis() can create phis like this */
938 bool all_same_temp
= instr
->operands
[0].isTemp();
939 /* this check is needed when moving uniform loop counters out of a divergent loop */
941 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
942 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
943 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
944 all_same_temp
= false;
947 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
949 bool all_undef
= instr
->operands
[0].isUndefined();
950 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
951 if (!instr
->operands
[i
].isUndefined())
955 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
959 case aco_opcode::v_add_u32
:
960 case aco_opcode::v_add_co_u32
:
961 case aco_opcode::s_add_i32
:
962 case aco_opcode::s_add_u32
:
963 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
965 case aco_opcode::s_not_b32
:
966 case aco_opcode::s_not_b64
:
967 case aco_opcode::s_and_b32
:
968 case aco_opcode::s_and_b64
:
969 case aco_opcode::s_or_b32
:
970 case aco_opcode::s_or_b64
:
971 case aco_opcode::s_xor_b32
:
972 case aco_opcode::s_xor_b64
:
973 case aco_opcode::s_lshl_b32
:
974 case aco_opcode::v_or_b32
:
975 case aco_opcode::v_lshlrev_b32
:
976 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
978 case aco_opcode::v_min_f32
:
979 case aco_opcode::v_min_f16
:
980 case aco_opcode::v_min_u32
:
981 case aco_opcode::v_min_i32
:
982 case aco_opcode::v_min_u16
:
983 case aco_opcode::v_min_i16
:
984 case aco_opcode::v_max_f32
:
985 case aco_opcode::v_max_f16
:
986 case aco_opcode::v_max_u32
:
987 case aco_opcode::v_max_i32
:
988 case aco_opcode::v_max_u16
:
989 case aco_opcode::v_max_i16
:
990 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
992 case aco_opcode::v_cmp_lt_f32
:
993 case aco_opcode::v_cmp_eq_f32
:
994 case aco_opcode::v_cmp_le_f32
:
995 case aco_opcode::v_cmp_gt_f32
:
996 case aco_opcode::v_cmp_lg_f32
:
997 case aco_opcode::v_cmp_ge_f32
:
998 case aco_opcode::v_cmp_o_f32
:
999 case aco_opcode::v_cmp_u_f32
:
1000 case aco_opcode::v_cmp_nge_f32
:
1001 case aco_opcode::v_cmp_nlg_f32
:
1002 case aco_opcode::v_cmp_ngt_f32
:
1003 case aco_opcode::v_cmp_nle_f32
:
1004 case aco_opcode::v_cmp_neq_f32
:
1005 case aco_opcode::v_cmp_nlt_f32
:
1006 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1013 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1015 *ordered
= *unordered
= op
;
1017 #define CMP(ord, unord) \
1018 case aco_opcode::v_cmp_##ord##_f32:\
1019 case aco_opcode::v_cmp_n##unord##_f32:\
1020 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1021 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1022 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1036 aco_opcode
get_ordered(aco_opcode op
)
1038 aco_opcode ordered
, unordered
, inverse
;
1039 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1042 aco_opcode
get_unordered(aco_opcode op
)
1044 aco_opcode ordered
, unordered
, inverse
;
1045 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1048 aco_opcode
get_inverse(aco_opcode op
)
1050 aco_opcode ordered
, unordered
, inverse
;
1051 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1054 bool is_cmp(aco_opcode op
)
1056 aco_opcode ordered
, unordered
, inverse
;
1057 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1060 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1062 if (ctx
.info
[tmp
.id()].is_temp())
1063 return ctx
.info
[tmp
.id()].temp
.id();
1068 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1070 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1071 for (const Operand
& op
: instr
->operands
) {
1073 ctx
.uses
[op
.tempId()]--;
1078 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1080 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1082 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1085 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1087 if (instr
->definitions
.size() == 2) {
1088 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1089 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1096 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1097 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1098 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1100 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1102 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1105 bool neg
[2] = {false, false};
1106 bool abs
[2] = {false, false};
1107 bool opsel
[2] = {false, false};
1108 Instruction
*op_instr
[2];
1111 for (unsigned i
= 0; i
< 2; i
++) {
1112 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1116 aco_opcode expected_cmp
= instr
->opcode
== aco_opcode::s_or_b64
?
1117 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1119 if (op_instr
[i
]->opcode
!= expected_cmp
)
1121 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1124 if (op_instr
[i
]->isVOP3()) {
1125 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1126 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
[0] != vop3
->opsel
[1])
1128 neg
[i
] = vop3
->neg
[0];
1129 abs
[i
] = vop3
->abs
[0];
1130 opsel
[i
] = vop3
->opsel
[0];
1133 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1134 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1135 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1137 /* shouldn't happen yet, but best to be safe */
1138 if (op1
.type() != RegType::vgpr
)
1144 ctx
.uses
[op
[0].id()]++;
1145 ctx
.uses
[op
[1].id()]++;
1146 decrease_uses(ctx
, op_instr
[0]);
1147 decrease_uses(ctx
, op_instr
[1]);
1149 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1150 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1151 Instruction
*new_instr
;
1152 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
[0] || opsel
[1]) {
1153 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1154 for (unsigned i
= 0; i
< 2; i
++) {
1155 vop3
->neg
[i
] = neg
[i
];
1156 vop3
->abs
[i
] = abs
[i
];
1157 vop3
->opsel
[i
] = opsel
[i
];
1159 new_instr
= static_cast<Instruction
*>(vop3
);
1161 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1163 new_instr
->operands
[0] = Operand(op
[0]);
1164 new_instr
->operands
[1] = Operand(op
[1]);
1165 new_instr
->definitions
[0] = instr
->definitions
[0];
1167 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1168 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1170 instr
.reset(new_instr
);
1175 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1176 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1177 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1179 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1181 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1184 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1185 aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1187 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1188 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1189 if (!nan_test
|| !cmp
)
1192 if (cmp
->opcode
== expected_nan_test
)
1193 std::swap(nan_test
, cmp
);
1194 else if (nan_test
->opcode
!= expected_nan_test
)
1197 if (!is_cmp(cmp
->opcode
))
1200 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1202 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1205 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1206 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1207 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1208 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1209 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1211 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1214 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1215 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1216 decrease_uses(ctx
, nan_test
);
1217 decrease_uses(ctx
, cmp
);
1219 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1220 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1221 Instruction
*new_instr
;
1222 if (cmp
->isVOP3()) {
1223 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1224 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1225 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1226 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1227 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1228 new_vop3
->clamp
= cmp_vop3
->clamp
;
1229 new_vop3
->omod
= cmp_vop3
->omod
;
1230 new_instr
= new_vop3
;
1232 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1234 new_instr
->operands
[0] = cmp
->operands
[0];
1235 new_instr
->operands
[1] = cmp
->operands
[1];
1236 new_instr
->definitions
[0] = instr
->definitions
[0];
1238 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1239 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1241 instr
.reset(new_instr
);
1246 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1247 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1248 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1250 if (instr
->opcode
!= aco_opcode::s_or_b64
&& instr
->opcode
!= aco_opcode::s_and_b64
)
1252 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1255 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1256 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1258 if (!nan_test
|| !cmp
)
1261 aco_opcode expected_nan_test
= instr
->opcode
== aco_opcode::s_or_b64
?
1262 aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1263 if (cmp
->opcode
== expected_nan_test
)
1264 std::swap(nan_test
, cmp
);
1265 else if (nan_test
->opcode
!= expected_nan_test
)
1268 if (!is_cmp(cmp
->opcode
))
1271 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1273 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1276 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1277 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1278 if (prop_nan0
!= prop_nan1
)
1281 int constant_operand
= -1;
1282 for (unsigned i
= 0; i
< 2; i
++) {
1283 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1284 constant_operand
= !i
;
1288 if (constant_operand
== -1)
1292 if (cmp
->operands
[constant_operand
].isConstant()) {
1293 constant
= cmp
->operands
[constant_operand
].constantValue();
1294 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1295 unsigned id
= cmp
->operands
[constant_operand
].tempId();
1296 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1298 constant
= ctx
.info
[id
].val
;
1304 memcpy(&constantf
, &constant
, 4);
1305 if (isnan(constantf
))
1308 if (cmp
->operands
[0].isTemp())
1309 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1310 if (cmp
->operands
[1].isTemp())
1311 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1312 decrease_uses(ctx
, nan_test
);
1313 decrease_uses(ctx
, cmp
);
1315 aco_opcode new_op
= instr
->opcode
== aco_opcode::s_or_b64
?
1316 get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1317 Instruction
*new_instr
;
1318 if (cmp
->isVOP3()) {
1319 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1320 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1321 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1322 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1323 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1324 new_vop3
->clamp
= cmp_vop3
->clamp
;
1325 new_vop3
->omod
= cmp_vop3
->omod
;
1326 new_instr
= new_vop3
;
1328 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1330 new_instr
->operands
[0] = cmp
->operands
[0];
1331 new_instr
->operands
[1] = cmp
->operands
[1];
1332 new_instr
->definitions
[0] = instr
->definitions
[0];
1334 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1335 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1337 instr
.reset(new_instr
);
1342 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1343 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1345 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1347 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1349 if (!instr
->operands
[0].isTemp())
1352 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1356 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1357 if (new_opcode
== aco_opcode::last_opcode
)
1360 if (cmp
->operands
[0].isTemp())
1361 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1362 if (cmp
->operands
[1].isTemp())
1363 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1364 decrease_uses(ctx
, cmp
);
1366 Instruction
*new_instr
;
1367 if (cmp
->isVOP3()) {
1368 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1369 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1370 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1371 memcpy(new_vop3
->opsel
, cmp_vop3
->opsel
, sizeof(new_vop3
->opsel
));
1372 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1373 new_vop3
->clamp
= cmp_vop3
->clamp
;
1374 new_vop3
->omod
= cmp_vop3
->omod
;
1375 new_instr
= new_vop3
;
1377 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1379 new_instr
->operands
[0] = cmp
->operands
[0];
1380 new_instr
->operands
[1] = cmp
->operands
[1];
1381 new_instr
->definitions
[0] = instr
->definitions
[0];
1383 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1384 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1386 instr
.reset(new_instr
);
1391 /* op1(op2(1, 2), 0) if swap = false
1392 * op1(0, op2(1, 2)) if swap = true */
1393 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1394 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1395 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1396 bool *op1_clamp
, unsigned *op1_omod
,
1397 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1400 if (op1_instr
->opcode
!= op1
)
1403 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1404 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1407 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1408 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1410 /* don't support inbetween clamp/omod */
1411 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1414 /* get operands and modifiers and check inbetween modifiers */
1415 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1416 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1419 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1420 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1424 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1425 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1428 if (inbetween_opsel
)
1429 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
[swap
] : false;
1430 else if (op1_vop3
&& op1_vop3
->opsel
[swap
])
1434 shuffle
[shuffle_str
[0] - '0'] = 0;
1435 shuffle
[shuffle_str
[1] - '0'] = 1;
1436 shuffle
[shuffle_str
[2] - '0'] = 2;
1438 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1439 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1440 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1441 opsel
[shuffle
[0]] = op1_vop3
? op1_vop3
->opsel
[!swap
] : false;
1443 for (unsigned i
= 0; i
< 2; i
++) {
1444 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1445 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1446 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1447 opsel
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->opsel
[i
] : false;
1450 /* check operands */
1451 unsigned sgpr_id
= 0;
1452 for (unsigned i
= 0; i
< 3; i
++) {
1453 Operand op
= operands
[i
];
1454 if (op
.isLiteral()) {
1456 } else if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1457 if (sgpr_id
&& sgpr_id
!= op
.tempId())
1459 sgpr_id
= op
.tempId();
1466 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1467 Operand operands
[3], bool neg
[3], bool abs
[3], bool opsel
[3],
1468 bool clamp
, unsigned omod
)
1470 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1471 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1472 memcpy(new_instr
->opsel
, opsel
, sizeof(bool[3]));
1473 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1474 new_instr
->clamp
= clamp
;
1475 new_instr
->omod
= omod
;
1476 new_instr
->operands
[0] = operands
[0];
1477 new_instr
->operands
[1] = operands
[1];
1478 new_instr
->operands
[2] = operands
[2];
1479 new_instr
->definitions
[0] = instr
->definitions
[0];
1480 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1482 instr
.reset(new_instr
);
1485 bool combine_minmax3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
)
1487 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1488 (label_omod_success
| label_clamp_success
);
1490 for (unsigned swap
= 0; swap
< 2; swap
++) {
1491 Operand operands
[3];
1492 bool neg
[3], abs
[3], opsel
[3], clamp
, inbetween_neg
, inbetween_abs
;
1494 if (match_op3_for_vop3(ctx
, instr
->opcode
, instr
->opcode
, instr
.get(), swap
,
1495 "012", operands
, neg
, abs
, opsel
,
1496 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1497 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1498 neg
[1] ^= inbetween_neg
;
1499 neg
[2] ^= inbetween_neg
;
1500 abs
[1] |= inbetween_abs
;
1501 abs
[2] |= inbetween_abs
;
1502 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1503 if (omod_clamp
& label_omod_success
)
1504 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1505 if (omod_clamp
& label_clamp_success
)
1506 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1513 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1515 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1516 (label_omod_success
| label_clamp_success
);
1518 for (unsigned swap
= 0; swap
< 2; swap
++) {
1519 if (!((1 << swap
) & ops
))
1522 Operand operands
[3];
1523 bool neg
[3], abs
[3], opsel
[3], clamp
;
1525 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1526 instr
.get(), swap
, shuffle
,
1527 operands
, neg
, abs
, opsel
,
1528 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1529 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1530 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1531 if (omod_clamp
& label_omod_success
)
1532 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1533 if (omod_clamp
& label_clamp_success
)
1534 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1541 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1542 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1543 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1544 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1545 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1546 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1547 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1550 if (!instr
->operands
[0].isTemp())
1552 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1555 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1558 switch (op2_instr
->opcode
) {
1559 case aco_opcode::s_and_b32
:
1560 case aco_opcode::s_or_b32
:
1561 case aco_opcode::s_xor_b32
:
1562 case aco_opcode::s_and_b64
:
1563 case aco_opcode::s_or_b64
:
1564 case aco_opcode::s_xor_b64
:
1570 /* create instruction */
1571 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1572 ctx
.uses
[instr
->operands
[0].tempId()]--;
1573 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1575 switch (op2_instr
->opcode
) {
1576 case aco_opcode::s_and_b32
:
1577 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1579 case aco_opcode::s_or_b32
:
1580 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1582 case aco_opcode::s_xor_b32
:
1583 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1585 case aco_opcode::s_and_b64
:
1586 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1588 case aco_opcode::s_or_b64
:
1589 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1591 case aco_opcode::s_xor_b64
:
1592 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1601 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1602 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1603 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1604 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1605 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1607 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1610 for (unsigned i
= 0; i
< 2; i
++) {
1611 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1612 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1615 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1616 instr
->operands
[0] = instr
->operands
[!i
];
1617 instr
->operands
[1] = op2_instr
->operands
[0];
1618 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1620 switch (instr
->opcode
) {
1621 case aco_opcode::s_and_b32
:
1622 instr
->opcode
= aco_opcode::s_andn2_b32
;
1624 case aco_opcode::s_or_b32
:
1625 instr
->opcode
= aco_opcode::s_orn2_b32
;
1627 case aco_opcode::s_and_b64
:
1628 instr
->opcode
= aco_opcode::s_andn2_b64
;
1630 case aco_opcode::s_or_b64
:
1631 instr
->opcode
= aco_opcode::s_orn2_b64
;
1642 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1643 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1645 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1648 for (unsigned i
= 0; i
< 2; i
++) {
1649 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1650 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1653 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1654 if (shift
< 1 || shift
> 4)
1657 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1658 instr
->operands
[1] = instr
->operands
[!i
];
1659 instr
->operands
[0] = op2_instr
->operands
[0];
1660 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1662 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1663 aco_opcode::s_lshl2_add_u32
,
1664 aco_opcode::s_lshl3_add_u32
,
1665 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1672 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1675 #define MINMAX(type, gfx9) \
1676 case aco_opcode::v_min_##type:\
1677 case aco_opcode::v_max_##type:\
1678 case aco_opcode::v_med3_##type:\
1679 *min = aco_opcode::v_min_##type;\
1680 *max = aco_opcode::v_max_##type;\
1681 *med3 = aco_opcode::v_med3_##type;\
1682 *min3 = aco_opcode::v_min3_##type;\
1683 *max3 = aco_opcode::v_max3_##type;\
1684 *some_gfx9_only = gfx9;\
1698 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1699 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1700 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1701 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1703 aco_opcode other_op
;
1704 if (instr
->opcode
== min
)
1706 else if (instr
->opcode
== max
)
1711 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1712 (label_omod_success
| label_clamp_success
);
1714 for (unsigned swap
= 0; swap
< 2; swap
++) {
1715 Operand operands
[3];
1716 bool neg
[3], abs
[3], opsel
[3], clamp
, inbetween_neg
, inbetween_abs
;
1718 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1719 "012", operands
, neg
, abs
, opsel
,
1720 &clamp
, &omod
, &inbetween_neg
, &inbetween_abs
, NULL
)) {
1721 int const0_idx
= -1, const1_idx
= -1;
1722 uint32_t const0
= 0, const1
= 0;
1723 for (int i
= 0; i
< 3; i
++) {
1725 if (operands
[i
].isConstant()) {
1726 val
= operands
[i
].constantValue();
1727 } else if (operands
[i
].isTemp() && ctx
.uses
[operands
[i
].tempId()] == 1 &&
1728 ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1729 val
= ctx
.info
[operands
[i
].tempId()].val
;
1733 if (const0_idx
>= 0) {
1741 if (const0_idx
< 0 || const1_idx
< 0)
1744 if (opsel
[const0_idx
])
1746 if (opsel
[const1_idx
])
1749 int lower_idx
= const0_idx
;
1751 case aco_opcode::v_min_f32
:
1752 case aco_opcode::v_min_f16
: {
1753 float const0_f
, const1_f
;
1754 if (min
== aco_opcode::v_min_f32
) {
1755 memcpy(&const0_f
, &const0
, 4);
1756 memcpy(&const1_f
, &const1
, 4);
1758 const0_f
= _mesa_half_to_float(const0
);
1759 const1_f
= _mesa_half_to_float(const1
);
1761 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1762 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1763 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1764 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1765 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1768 case aco_opcode::v_min_u32
: {
1769 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1772 case aco_opcode::v_min_u16
: {
1773 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1776 case aco_opcode::v_min_i32
: {
1777 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
1778 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
1779 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1782 case aco_opcode::v_min_i16
: {
1783 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
1784 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
1785 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
1791 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
1793 if (instr
->opcode
== min
) {
1794 if (upper_idx
!= 0 || lower_idx
== 0)
1797 if (upper_idx
== 0 || lower_idx
!= 0)
1801 neg
[1] ^= inbetween_neg
;
1802 neg
[2] ^= inbetween_neg
;
1803 abs
[1] |= inbetween_abs
;
1804 abs
[2] |= inbetween_abs
;
1806 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1807 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1808 if (omod_clamp
& label_omod_success
)
1809 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1810 if (omod_clamp
& label_clamp_success
)
1811 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1821 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1824 uint32_t sgpr_idx
= 0;
1825 uint32_t sgpr_info_id
= 0;
1826 bool has_sgpr
= false;
1827 uint32_t sgpr_ssa_id
= 0;
1828 /* find 'best' possible sgpr */
1829 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
1831 if (instr
->operands
[i
].isLiteral()) {
1835 if (!instr
->operands
[i
].isTemp())
1837 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
1839 sgpr_ssa_id
= instr
->operands
[i
].tempId();
1842 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
1843 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
1844 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
1845 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
1847 sgpr_info_id
= instr
->operands
[i
].tempId();
1851 if (!has_sgpr
&& sgpr_info_id
!= 0) {
1852 ssa_info
& info
= ctx
.info
[sgpr_info_id
];
1853 if (sgpr_idx
== 0 || instr
->isVOP3()) {
1854 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1855 ctx
.uses
[sgpr_info_id
]--;
1856 ctx
.uses
[info
.temp
.id()]++;
1857 } else if (can_swap_operands(instr
)) {
1858 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
1859 instr
->operands
[0] = Operand(info
.temp
);
1860 ctx
.uses
[sgpr_info_id
]--;
1861 ctx
.uses
[info
.temp
.id()]++;
1862 } else if (can_use_VOP3(instr
)) {
1863 to_VOP3(ctx
, instr
);
1864 instr
->operands
[sgpr_idx
] = Operand(info
.temp
);
1865 ctx
.uses
[sgpr_info_id
]--;
1866 ctx
.uses
[info
.temp
.id()]++;
1869 /* we can have two sgprs on one instruction if it is the same sgpr! */
1870 } else if (sgpr_info_id
!= 0 &&
1871 sgpr_ssa_id
== sgpr_info_id
&&
1872 ctx
.uses
[sgpr_info_id
] == 1 &&
1873 can_use_VOP3(instr
)) {
1874 to_VOP3(ctx
, instr
);
1875 instr
->operands
[sgpr_idx
] = Operand(ctx
.info
[sgpr_info_id
].temp
);
1876 ctx
.uses
[sgpr_info_id
]--;
1877 ctx
.uses
[ctx
.info
[sgpr_info_id
].temp
.id()]++;
1881 bool apply_omod_clamp(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1883 /* check if we could apply omod on predecessor */
1884 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
1885 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success()) {
1887 /* omod was successfully applied */
1888 /* if the omod instruction is v_mad, we also have to change the original add */
1889 if (ctx
.info
[instr
->operands
[1].tempId()].is_mad()) {
1890 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[1].tempId()].val
].add_instr
.get();
1891 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
1892 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
1893 add_instr
->definitions
[0] = instr
->definitions
[0];
1896 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
1897 /* check if we have an additional clamp modifier */
1898 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1) {
1899 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
1900 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
1902 /* change definition ssa-id of modified instruction */
1903 omod_instr
->definitions
[0] = instr
->definitions
[0];
1905 /* change the definition of instr to something unused, e.g. the original omod def */
1906 instr
->definitions
[0] = Definition(instr
->operands
[1].getTemp());
1907 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1910 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
1911 /* in all other cases, label this instruction as option for multiply-add */
1912 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
1916 /* check if we could apply clamp on predecessor */
1917 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
1919 bool found_zero
= false, found_one
= false;
1920 for (unsigned i
= 0; i
< 3; i
++)
1922 if (instr
->operands
[i
].constantEquals(0))
1924 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1929 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
1930 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
1931 /* clamp was successfully applied */
1932 /* if the clamp instruction is v_mad, we also have to change the original add */
1933 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
1934 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
1935 add_instr
->definitions
[0] = instr
->definitions
[0];
1937 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
1938 /* change definition ssa-id of modified instruction */
1939 clamp_instr
->definitions
[0] = instr
->definitions
[0];
1941 /* change the definition of instr to something unused, e.g. the original omod def */
1942 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
1943 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
1948 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
1949 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
1950 can_use_VOP3(instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
1951 if(ctx
.info
[instr
->definitions
[0].tempId()].is_omod2()) {
1952 to_VOP3(ctx
, instr
);
1953 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
1954 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1955 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_omod4()) {
1956 to_VOP3(ctx
, instr
);
1957 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
1958 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1959 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_omod5()) {
1960 to_VOP3(ctx
, instr
);
1961 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
1962 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1963 } else if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp()) {
1964 to_VOP3(ctx
, instr
);
1965 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
1966 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1973 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
1974 // this would mean that we'd have to fix the instruction uses while value propagation
1976 void combine_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1978 if (instr
->definitions
.empty() || !ctx
.uses
[instr
->definitions
[0].tempId()])
1981 if (instr
->isVALU()) {
1982 if (can_apply_sgprs(instr
))
1983 apply_sgprs(ctx
, instr
);
1984 if (apply_omod_clamp(ctx
, instr
))
1988 /* TODO: There are still some peephole optimizations that could be done:
1989 * - abs(a - b) -> s_absdiff_i32
1990 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
1991 * - patterns for v_alignbit_b32 and v_alignbyte_b32
1992 * These aren't probably too interesting though.
1993 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
1994 * probably more useful than the previously mentioned optimizations.
1995 * The various comparison optimizations also currently only work with 32-bit
1998 /* neg(mul(a, b)) -> mul(neg(a), b) */
1999 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2000 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2002 if (!ctx
.info
[val
.id()].is_mul())
2005 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2007 if (mul_instr
->operands
[0].isLiteral())
2009 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2012 /* convert to mul(neg(a), b) */
2013 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2014 Definition def
= instr
->definitions
[0];
2015 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2016 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2017 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2018 instr
->operands
[0] = mul_instr
->operands
[0];
2019 instr
->operands
[1] = mul_instr
->operands
[1];
2020 instr
->definitions
[0] = def
;
2021 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2022 if (mul_instr
->isVOP3()) {
2023 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2024 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2025 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2026 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2027 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2028 new_mul
->omod
= mul
->omod
;
2030 new_mul
->neg
[0] ^= true;
2031 new_mul
->clamp
= false;
2033 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2036 /* combine mul+add -> mad */
2037 else if (instr
->opcode
== aco_opcode::v_add_f32
||
2038 instr
->opcode
== aco_opcode::v_sub_f32
||
2039 instr
->opcode
== aco_opcode::v_subrev_f32
) {
2041 uint32_t uses_src0
= UINT32_MAX
;
2042 uint32_t uses_src1
= UINT32_MAX
;
2043 Instruction
* mul_instr
= nullptr;
2044 unsigned add_op_idx
;
2045 /* check if any of the operands is a multiplication */
2046 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2047 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2048 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2049 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2051 /* find the 'best' mul instruction to combine with the add */
2052 if (uses_src0
< uses_src1
) {
2053 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2055 } else if (uses_src1
< uses_src0
) {
2056 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2058 } else if (uses_src0
!= UINT32_MAX
) {
2059 /* tiebreaker: quite random what to pick */
2060 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2061 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2064 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2069 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2070 bool neg
[3] = {false, false, false};
2071 bool abs
[3] = {false, false, false};
2074 bool need_vop3
= false;
2076 op
[0] = mul_instr
->operands
[0];
2077 op
[1] = mul_instr
->operands
[1];
2078 op
[2] = instr
->operands
[add_op_idx
];
2079 for (unsigned i
= 0; i
< 3; i
++)
2081 if (op
[i
].isLiteral())
2083 if (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::sgpr
)
2085 if (!(i
== 0 || (op
[i
].isTemp() && op
[i
].getTemp().type() == RegType::vgpr
)))
2088 // TODO: would be better to check this before selecting a mul instr?
2092 if (mul_instr
->isVOP3()) {
2093 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2094 neg
[0] = vop3
->neg
[0];
2095 neg
[1] = vop3
->neg
[1];
2096 abs
[0] = vop3
->abs
[0];
2097 abs
[1] = vop3
->abs
[1];
2099 /* we cannot use these modifiers between mul and add */
2100 if (vop3
->clamp
|| vop3
->omod
)
2104 /* convert to mad */
2105 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2106 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2108 ctx
.uses
[op
[0].tempId()]++;
2110 ctx
.uses
[op
[1].tempId()]++;
2113 if (instr
->isVOP3()) {
2114 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2115 neg
[2] = vop3
->neg
[add_op_idx
];
2116 abs
[2] = vop3
->abs
[add_op_idx
];
2118 clamp
= vop3
->clamp
;
2119 /* abs of the multiplication result */
2120 if (vop3
->abs
[1 - add_op_idx
]) {
2126 /* neg of the multiplication result */
2127 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2130 if (instr
->opcode
== aco_opcode::v_sub_f32
) {
2131 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2133 } else if (instr
->opcode
== aco_opcode::v_subrev_f32
) {
2134 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2138 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2139 for (unsigned i
= 0; i
< 3; i
++)
2141 mad
->operands
[i
] = op
[i
];
2142 mad
->neg
[i
] = neg
[i
];
2143 mad
->abs
[i
] = abs
[i
];
2147 mad
->definitions
[0] = instr
->definitions
[0];
2149 /* mark this ssa_def to be re-checked for profitability and literals */
2150 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId(), need_vop3
);
2151 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2152 instr
.reset(mad
.release());
2156 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2157 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2158 for (unsigned i
= 0; i
< 2; i
++) {
2159 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2160 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2161 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2162 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2163 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2165 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2166 new_instr
->operands
[0] = Operand(0u);
2167 new_instr
->operands
[1] = instr
->operands
[!i
];
2168 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2169 new_instr
->definitions
[0] = instr
->definitions
[0];
2170 instr
.reset(new_instr
.release());
2171 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2175 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2176 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2177 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2178 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2179 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2180 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2181 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2182 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2183 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2184 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2185 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2186 combine_salu_lshl_add(ctx
, instr
);
2187 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2188 combine_salu_not_bitwise(ctx
, instr
);
2189 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2190 if (combine_inverse_comparison(ctx
, instr
)) ;
2191 else combine_salu_not_bitwise(ctx
, instr
);
2192 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
) {
2193 combine_salu_n2(ctx
, instr
);
2194 } else if (instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2195 if (combine_ordering_test(ctx
, instr
)) ;
2196 else if (combine_comparison_ordering(ctx
, instr
)) ;
2197 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2198 else combine_salu_n2(ctx
, instr
);
2200 aco_opcode min
, max
, min3
, max3
, med3
;
2201 bool some_gfx9_only
;
2202 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2203 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2204 if (combine_minmax3(ctx
, instr
, instr
->opcode
== min
? min3
: max3
)) ;
2205 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2211 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2213 const uint32_t threshold
= 4;
2215 /* Dead Code Elimination:
2216 * We remove instructions if they define temporaries which all are unused */
2217 const bool is_used
= instr
->definitions
.empty() ||
2218 std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
2219 [&ctx
](const Definition
& def
) { return ctx
.uses
[def
.tempId()]; });
2225 /* convert split_vector into extract_vector if only one definition is ever used */
2226 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2227 unsigned num_used
= 0;
2229 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2230 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2235 if (num_used
== 1) {
2236 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2237 extract
->operands
[0] = instr
->operands
[0];
2238 extract
->operands
[1] = Operand((uint32_t) idx
);
2239 extract
->definitions
[0] = instr
->definitions
[idx
];
2240 instr
.reset(extract
.release());
2244 /* re-check mad instructions */
2245 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2246 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2247 /* first, check profitability */
2248 if (ctx
.uses
[info
->mul_temp_id
]) {
2249 ctx
.uses
[info
->mul_temp_id
]++;
2250 instr
.swap(info
->add_instr
);
2252 /* second, check possible literals */
2253 } else if (!info
->needs_vop3
) {
2254 uint32_t literal_idx
= 0;
2255 uint32_t literal_uses
= UINT32_MAX
;
2256 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2258 if (!instr
->operands
[i
].isTemp())
2260 /* if one of the operands is sgpr, we cannot add a literal somewhere else */
2261 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2262 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2263 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2266 literal_uses
= UINT32_MAX
;
2270 else if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2271 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2272 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2276 if (literal_uses
< threshold
) {
2277 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2278 info
->check_literal
= true;
2279 info
->literal_idx
= literal_idx
;
2285 /* check for literals */
2286 /* we do not apply the literals yet as we don't know if it is profitable */
2287 if (instr
->isSALU()) {
2288 uint32_t literal_idx
= 0;
2289 uint32_t literal_uses
= UINT32_MAX
;
2290 bool has_literal
= false;
2291 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2293 if (instr
->operands
[i
].isLiteral()) {
2297 if (!instr
->operands
[i
].isTemp())
2299 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2300 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2301 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2305 if (!has_literal
&& literal_uses
< threshold
) {
2306 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2307 if (ctx
.uses
[instr
->operands
[literal_idx
].tempId()] == 0)
2308 instr
->operands
[literal_idx
] = Operand(ctx
.info
[instr
->operands
[literal_idx
].tempId()].val
);
2310 } else if (instr
->isVALU() && valu_can_accept_literal(ctx
, instr
) &&
2311 instr
->operands
[0].isTemp() &&
2312 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2313 ctx
.uses
[instr
->operands
[0].tempId()] < threshold
) {
2314 ctx
.uses
[instr
->operands
[0].tempId()]--;
2315 if (ctx
.uses
[instr
->operands
[0].tempId()] == 0)
2316 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2322 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2324 /* Cleanup Dead Instructions */
2328 /* apply literals on SALU */
2329 if (instr
->isSALU()) {
2330 for (Operand
& op
: instr
->operands
) {
2335 if (ctx
.info
[op
.tempId()].is_literal() &&
2336 ctx
.uses
[op
.tempId()] == 0)
2337 op
= Operand(ctx
.info
[op
.tempId()].val
);
2341 /* apply literals on VALU */
2342 else if (instr
->isVALU() && !instr
->isVOP3() &&
2343 instr
->operands
[0].isTemp() &&
2344 ctx
.info
[instr
->operands
[0].tempId()].is_literal() &&
2345 ctx
.uses
[instr
->operands
[0].tempId()] == 0) {
2346 instr
->operands
[0] = Operand(ctx
.info
[instr
->operands
[0].tempId()].val
);
2349 /* apply literals on MAD */
2350 else if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2351 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2352 aco_ptr
<Instruction
> new_mad
;
2353 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2354 if (info
->literal_idx
== 2) { /* add literal -> madak */
2355 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2356 new_mad
->operands
[0] = instr
->operands
[0];
2357 new_mad
->operands
[1] = instr
->operands
[1];
2358 } else { /* mul literal -> madmk */
2359 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2360 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2361 new_mad
->operands
[1] = instr
->operands
[2];
2363 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2364 new_mad
->definitions
[0] = instr
->definitions
[0];
2365 instr
.swap(new_mad
);
2369 ctx
.instructions
.emplace_back(std::move(instr
));
2373 void optimize(Program
* program
)
2376 ctx
.program
= program
;
2377 std::vector
<ssa_info
> info(program
->peekAllocationId());
2378 ctx
.info
= info
.data();
2380 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2381 for (Block
& block
: program
->blocks
) {
2382 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2383 label_instruction(ctx
, instr
);
2386 ctx
.uses
= std::move(dead_code_analysis(program
));
2388 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2389 for (Block
& block
: program
->blocks
) {
2390 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2391 combine_instruction(ctx
, instr
);
2394 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2395 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2396 Block
* block
= &(*it
);
2397 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2398 select_instruction(ctx
, *it
);
2401 /* 4. Add literals to instructions */
2402 for (Block
& block
: program
->blocks
) {
2403 ctx
.instructions
.clear();
2404 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2405 apply_literals(ctx
, instr
);
2406 block
.instructions
.swap(ctx
.instructions
);