2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
90 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
91 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
92 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
93 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
;
94 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
104 void add_label(Label new_label
)
106 /* Since all labels which use "instr" use it for the same thing
107 * (indicating the defining instruction), there is no need to clear
108 * any other instr labels. */
109 if (new_label
& instr_labels
)
110 label
&= ~temp_labels
; /* instr and temp alias */
112 if (new_label
& temp_labels
) {
113 label
&= ~temp_labels
;
114 label
&= ~instr_labels
; /* instr and temp alias */
117 if (new_label
& val_labels
)
118 label
&= ~val_labels
;
123 void set_vec(Instruction
* vec
)
125 add_label(label_vec
);
131 return label
& label_vec
;
134 void set_constant(uint32_t constant
)
136 add_label(label_constant
);
142 return label
& label_constant
;
145 void set_constant_64bit(uint32_t constant
)
147 add_label(label_constant_64bit
);
151 bool is_constant_64bit()
153 return label
& label_constant_64bit
;
156 void set_abs(Temp abs_temp
)
158 add_label(label_abs
);
164 return label
& label_abs
;
167 void set_neg(Temp neg_temp
)
169 add_label(label_neg
);
175 return label
& label_neg
;
178 void set_neg_abs(Temp neg_abs_temp
)
180 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
184 void set_mul(Instruction
* mul
)
186 add_label(label_mul
);
192 return label
& label_mul
;
195 void set_temp(Temp tmp
)
197 add_label(label_temp
);
203 return label
& label_temp
;
206 void set_literal(uint32_t lit
)
208 add_label(label_literal
);
214 return label
& label_literal
;
217 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
219 add_label(label_mad
);
226 return label
& label_mad
;
229 void set_omod2(Temp def
)
231 add_label(label_omod2
);
237 return label
& label_omod2
;
240 void set_omod4(Temp def
)
242 add_label(label_omod4
);
248 return label
& label_omod4
;
251 void set_omod5(Temp def
)
253 add_label(label_omod5
);
259 return label
& label_omod5
;
262 void set_omod_success(Instruction
* omod_instr
)
264 add_label(label_omod_success
);
268 bool is_omod_success()
270 return label
& label_omod_success
;
273 void set_clamp(Temp def
)
275 add_label(label_clamp
);
281 return label
& label_clamp
;
284 void set_clamp_success(Instruction
* clamp_instr
)
286 add_label(label_clamp_success
);
290 bool is_clamp_success()
292 return label
& label_clamp_success
;
297 add_label(label_undefined
);
302 return label
& label_undefined
;
305 void set_vcc(Temp vcc
)
307 add_label(label_vcc
);
313 return label
& label_vcc
;
316 bool is_constant_or_literal()
318 return is_constant() || is_literal();
321 void set_b2f(Temp val
)
323 add_label(label_b2f
);
329 return label
& label_b2f
;
332 void set_add_sub(Instruction
*add_sub_instr
)
334 add_label(label_add_sub
);
335 instr
= add_sub_instr
;
340 return label
& label_add_sub
;
343 void set_bitwise(Instruction
*bitwise_instr
)
345 add_label(label_bitwise
);
346 instr
= bitwise_instr
;
351 return label
& label_bitwise
;
354 void set_uniform_bitwise()
356 add_label(label_uniform_bitwise
);
359 bool is_uniform_bitwise()
361 return label
& label_uniform_bitwise
;
364 void set_minmax(Instruction
*minmax_instr
)
366 add_label(label_minmax
);
367 instr
= minmax_instr
;
372 return label
& label_minmax
;
375 void set_fcmp(Instruction
*fcmp_instr
)
377 add_label(label_fcmp
);
383 return label
& label_fcmp
;
386 void set_scc_invert(Temp scc_inv
)
388 add_label(label_scc_invert
);
394 return label
& label_scc_invert
;
397 void set_uniform_bool(Temp uniform_bool
)
399 add_label(label_uniform_bool
);
403 bool is_uniform_bool()
405 return label
& label_uniform_bool
;
412 std::vector
<aco_ptr
<Instruction
>> instructions
;
414 std::pair
<uint32_t,Temp
> last_literal
;
415 std::vector
<mad_info
> mad_infos
;
416 std::vector
<uint16_t> uses
;
419 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
421 if (instr
->operands
[0].isConstant() ||
422 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
425 switch (instr
->opcode
) {
426 case aco_opcode::v_add_f32
:
427 case aco_opcode::v_mul_f32
:
428 case aco_opcode::v_or_b32
:
429 case aco_opcode::v_and_b32
:
430 case aco_opcode::v_xor_b32
:
431 case aco_opcode::v_max_f32
:
432 case aco_opcode::v_min_f32
:
433 case aco_opcode::v_max_i32
:
434 case aco_opcode::v_min_i32
:
435 case aco_opcode::v_max_u32
:
436 case aco_opcode::v_min_u32
:
437 case aco_opcode::v_cmp_eq_f32
:
438 case aco_opcode::v_cmp_lg_f32
:
440 case aco_opcode::v_sub_f32
:
441 instr
->opcode
= aco_opcode::v_subrev_f32
;
443 case aco_opcode::v_cmp_lt_f32
:
444 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
446 case aco_opcode::v_cmp_ge_f32
:
447 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
449 case aco_opcode::v_cmp_lt_i32
:
450 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
457 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
462 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
465 if (instr
->isDPP() || instr
->isSDWA())
468 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
469 instr
->opcode
!= aco_opcode::v_madak_f32
&&
470 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
471 instr
->opcode
!= aco_opcode::v_madak_f16
&&
472 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
473 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
474 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
475 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
476 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
477 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
478 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
481 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
483 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
484 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
485 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
486 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
487 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
490 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
495 aco_ptr
<Instruction
> tmp
= std::move(instr
);
496 Format format
= asVOP3(tmp
->format
);
497 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
498 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
499 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
500 instr
->definitions
[i
] = tmp
->definitions
[i
];
501 if (instr
->definitions
[i
].isTemp()) {
502 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
503 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
504 info
.instr
= instr
.get();
509 /* only covers special cases */
510 bool can_accept_constant(aco_ptr
<Instruction
>& instr
, unsigned operand
)
512 switch (instr
->opcode
) {
513 case aco_opcode::v_interp_p2_f32
:
514 case aco_opcode::v_mac_f32
:
515 case aco_opcode::v_writelane_b32
:
516 case aco_opcode::v_writelane_b32_e64
:
517 case aco_opcode::v_cndmask_b32
:
519 case aco_opcode::s_addk_i32
:
520 case aco_opcode::s_mulk_i32
:
521 case aco_opcode::p_wqm
:
522 case aco_opcode::p_extract_vector
:
523 case aco_opcode::p_split_vector
:
524 case aco_opcode::v_readlane_b32
:
525 case aco_opcode::v_readlane_b32_e64
:
526 case aco_opcode::v_readfirstlane_b32
:
529 if ((instr
->format
== Format::MUBUF
||
530 instr
->format
== Format::MIMG
) &&
531 instr
->definitions
.size() == 1 &&
532 instr
->operands
.size() == 4) {
539 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
541 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
542 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
547 /* check constant bus and literal limitations */
548 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
550 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
551 Operand
literal32(s1
);
552 Operand
literal64(s2
);
553 unsigned num_sgprs
= 0;
554 unsigned sgpr
[] = {0, 0};
556 for (unsigned i
= 0; i
< num_operands
; i
++) {
557 Operand op
= operands
[i
];
559 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
560 /* two reads of the same SGPR count as 1 to the limit */
561 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
563 sgpr
[num_sgprs
++] = op
.tempId();
568 } else if (op
.isLiteral()) {
569 if (ctx
.program
->chip_class
< GFX10
)
572 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
574 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
577 /* Any number of 32-bit literals counts as only 1 to the limit. Same
578 * (but separately) for 64-bit literals. */
579 if (op
.size() == 1 && literal32
.isUndefined()) {
582 } else if (op
.size() == 2 && literal64
.isUndefined()) {
595 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
597 Operand op
= instr
->operands
[op_index
];
601 Temp tmp
= op
.getTemp();
602 if (!ctx
.info
[tmp
.id()].is_add_sub())
605 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
607 switch (add_instr
->opcode
) {
608 case aco_opcode::v_add_u32
:
609 case aco_opcode::v_add_co_u32
:
610 case aco_opcode::s_add_i32
:
611 case aco_opcode::s_add_u32
:
617 if (add_instr
->usesModifiers())
620 for (unsigned i
= 0; i
< 2; i
++) {
621 if (add_instr
->operands
[i
].isConstant()) {
622 *offset
= add_instr
->operands
[i
].constantValue();
623 } else if (add_instr
->operands
[i
].isTemp() &&
624 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
625 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
629 if (!add_instr
->operands
[!i
].isTemp())
632 uint32_t offset2
= 0;
633 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
636 *base
= add_instr
->operands
[!i
].getTemp();
644 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
646 // TODO: this functions shouldn't be needed if we store Operand instead of value.
647 Operand
op(val
, is64bit
);
648 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
649 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
653 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
655 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
656 ASSERTED
bool all_const
= false;
657 for (Operand
& op
: instr
->operands
)
658 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
659 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
662 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
664 if (!instr
->operands
[i
].isTemp())
667 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
668 /* propagate undef */
669 if (info
.is_undefined() && is_phi(instr
))
670 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
671 /* propagate reg->reg of same type */
672 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
673 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
674 info
= ctx
.info
[info
.temp
.id()];
677 /* SALU / PSEUDO: propagate inline constants */
678 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
679 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
680 instr
->operands
[i
].setTemp(info
.temp
);
681 info
= ctx
.info
[info
.temp
.id()];
682 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
683 /* propagate vgpr if it can take it */
684 switch (instr
->opcode
) {
685 case aco_opcode::p_create_vector
:
686 case aco_opcode::p_split_vector
:
687 case aco_opcode::p_extract_vector
:
688 case aco_opcode::p_phi
: {
689 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
690 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
692 instr
->operands
[i
] = Operand(info
.temp
);
693 info
= ctx
.info
[info
.temp
.id()];
701 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) && !instr
->operands
[i
].isFixed() && can_accept_constant(instr
, i
)) {
702 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
707 /* VALU: propagate neg, abs & inline constants */
708 else if (instr
->isVALU()) {
709 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
710 instr
->operands
[i
].setTemp(info
.temp
);
711 info
= ctx
.info
[info
.temp
.id()];
713 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
716 instr
->operands
[i
] = Operand(info
.temp
);
718 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
720 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
722 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
723 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
724 instr
->operands
[i
].setTemp(info
.temp
);
726 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
729 instr
->operands
[i
].setTemp(info
.temp
);
731 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
733 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
736 if ((info
.is_constant() || info
.is_constant_64bit()) && can_accept_constant(instr
, i
)) {
737 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
738 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
739 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
740 instr
->operands
[i
] = op
;
742 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
743 instr
->operands
[i
] = instr
->operands
[0];
744 instr
->operands
[0] = op
;
746 } else if (can_use_VOP3(ctx
, instr
)) {
748 instr
->operands
[i
] = op
;
754 /* MUBUF: propagate constants and combine additions */
755 else if (instr
->format
== Format::MUBUF
) {
756 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
759 while (info
.is_temp())
760 info
= ctx
.info
[info
.temp
.id()];
762 if (mubuf
->offen
&& i
== 0 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
763 assert(!mubuf
->idxen
);
764 instr
->operands
[i
] = Operand(v1
);
765 mubuf
->offset
+= info
.val
;
766 mubuf
->offen
= false;
768 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
769 instr
->operands
[2] = Operand((uint32_t) 0);
770 mubuf
->offset
+= info
.val
;
772 } else if (mubuf
->offen
&& i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
773 assert(!mubuf
->idxen
);
774 instr
->operands
[i
].setTemp(base
);
775 mubuf
->offset
+= offset
;
777 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
778 instr
->operands
[i
].setTemp(base
);
779 mubuf
->offset
+= offset
;
784 /* DS: combine additions */
785 else if (instr
->format
== Format::DS
) {
787 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
790 if (i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == instr
->operands
[i
].regClass() && instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
791 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
792 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
793 if (offset
% 4 == 0 &&
794 ds
->offset0
+ (offset
>> 2) <= 255 &&
795 ds
->offset1
+ (offset
>> 2) <= 255) {
796 instr
->operands
[i
].setTemp(base
);
797 ds
->offset0
+= offset
>> 2;
798 ds
->offset1
+= offset
>> 2;
801 if (ds
->offset0
+ offset
<= 65535) {
802 instr
->operands
[i
].setTemp(base
);
803 ds
->offset0
+= offset
;
809 /* SMEM: propagate constants and combine additions */
810 else if (instr
->format
== Format::SMEM
) {
812 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
815 if (i
== 1 && info
.is_constant_or_literal() &&
816 (ctx
.program
->chip_class
< GFX8
|| info
.val
<= 0xFFFFF)) {
817 instr
->operands
[i
] = Operand(info
.val
);
819 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
820 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
822 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
823 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
827 smem
->operands
[1] = Operand(offset
);
828 smem
->operands
.back() = Operand(base
);
830 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
831 new_instr
->operands
[0] = smem
->operands
[0];
832 new_instr
->operands
[1] = Operand(offset
);
833 if (smem
->definitions
.empty())
834 new_instr
->operands
[2] = smem
->operands
[2];
835 new_instr
->operands
.back() = Operand(base
);
836 if (!smem
->definitions
.empty())
837 new_instr
->definitions
[0] = smem
->definitions
[0];
838 new_instr
->can_reorder
= smem
->can_reorder
;
839 new_instr
->barrier
= smem
->barrier
;
840 instr
.reset(new_instr
);
841 smem
= static_cast<SMEM_instruction
*>(instr
.get());
847 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
848 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
849 /* Flip the branch instruction to get rid of the scc_invert instruction */
850 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
851 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
856 /* if this instruction doesn't define anything, return */
857 if (instr
->definitions
.empty())
860 switch (instr
->opcode
) {
861 case aco_opcode::p_create_vector
: {
862 unsigned num_ops
= instr
->operands
.size();
863 for (const Operand
& op
: instr
->operands
) {
864 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
865 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
867 if (num_ops
!= instr
->operands
.size()) {
868 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
869 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
870 instr
->definitions
[0] = old_vec
->definitions
[0];
872 for (Operand
& old_op
: old_vec
->operands
) {
873 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
874 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
875 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
876 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
877 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
878 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
879 instr
->operands
[k
++] = op
;
882 instr
->operands
[k
++] = old_op
;
885 assert(k
== num_ops
);
887 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
888 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
889 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
890 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
893 case aco_opcode::p_split_vector
: {
894 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
896 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
897 assert(instr
->definitions
.size() == vec
->operands
.size());
898 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
899 Operand vec_op
= vec
->operands
[i
];
900 if (vec_op
.isConstant()) {
901 if (vec_op
.isLiteral())
902 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
903 else if (vec_op
.size() == 1)
904 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
905 else if (vec_op
.size() == 2)
906 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
908 assert(vec_op
.isTemp());
909 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
914 case aco_opcode::p_extract_vector
: { /* mov */
915 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
917 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
918 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
919 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
921 /* convert this extract into a mov instruction */
922 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
923 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
924 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
925 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
926 instr
->opcode
= opcode
;
927 instr
->format
= format
;
928 while (instr
->operands
.size() > 1)
929 instr
->operands
.pop_back();
930 instr
->operands
[0] = vec_op
;
932 if (vec_op
.isConstant()) {
933 if (vec_op
.isLiteral())
934 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
935 else if (vec_op
.size() == 1)
936 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
937 else if (vec_op
.size() == 2)
938 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(vec_op
.constantValue());
941 assert(vec_op
.isTemp());
942 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
947 case aco_opcode::s_mov_b32
: /* propagate */
948 case aco_opcode::s_mov_b64
:
949 case aco_opcode::v_mov_b32
:
950 case aco_opcode::p_as_uniform
:
951 if (instr
->definitions
[0].isFixed()) {
952 /* don't copy-propagate copies into fixed registers */
953 } else if (instr
->usesModifiers()) {
955 } else if (instr
->operands
[0].isConstant()) {
956 if (instr
->operands
[0].isLiteral())
957 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
958 else if (instr
->operands
[0].size() == 1)
959 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
960 else if (instr
->operands
[0].size() == 2)
961 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
962 } else if (instr
->operands
[0].isTemp()) {
963 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
965 assert(instr
->operands
[0].isFixed());
968 case aco_opcode::p_is_helper
:
969 if (!ctx
.program
->needs_wqm
)
970 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
972 case aco_opcode::s_movk_i32
: {
973 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
974 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
975 if (v
<= 64 || v
>= 0xfffffff0)
976 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
978 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
981 case aco_opcode::v_bfrev_b32
:
982 case aco_opcode::s_brev_b32
: {
983 if (instr
->operands
[0].isConstant()) {
984 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
985 if (v
<= 64 || v
>= 0xfffffff0)
986 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
988 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
992 case aco_opcode::s_bfm_b32
: {
993 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
994 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
995 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
996 uint32_t v
= ((1u << size
) - 1u) << start
;
997 if (v
<= 64 || v
>= 0xfffffff0)
998 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1000 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1003 case aco_opcode::v_mul_f32
: { /* omod */
1004 /* TODO: try to move the negate/abs modifier to the consumer instead */
1005 if (instr
->usesModifiers())
1008 for (unsigned i
= 0; i
< 2; i
++) {
1009 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1010 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1011 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1012 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1013 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1014 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1015 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1016 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1017 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1018 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1027 case aco_opcode::v_and_b32
: /* abs */
1028 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1029 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1030 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1032 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1034 case aco_opcode::v_xor_b32
: { /* neg */
1035 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1036 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1037 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1038 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1039 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1040 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1041 instr
->opcode
= aco_opcode::v_or_b32
;
1042 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1044 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1048 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1052 case aco_opcode::v_med3_f32
: { /* clamp */
1053 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1054 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1055 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1056 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1060 bool found_zero
= false, found_one
= false;
1061 for (unsigned i
= 0; i
< 3; i
++)
1063 if (instr
->operands
[i
].constantEquals(0))
1065 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1070 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1071 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1075 case aco_opcode::v_cndmask_b32
:
1076 if (instr
->operands
[0].constantEquals(0) &&
1077 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1078 instr
->operands
[2].isTemp())
1079 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1080 else if (instr
->operands
[0].constantEquals(0) &&
1081 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1082 instr
->operands
[2].isTemp())
1083 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1085 case aco_opcode::v_cmp_lg_u32
:
1086 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1087 instr
->operands
[0].constantEquals(0) &&
1088 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1089 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1091 case aco_opcode::p_phi
:
1092 case aco_opcode::p_linear_phi
: {
1093 /* lower_bool_phis() can create phis like this */
1094 bool all_same_temp
= instr
->operands
[0].isTemp();
1095 /* this check is needed when moving uniform loop counters out of a divergent loop */
1097 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1098 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1099 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1100 all_same_temp
= false;
1102 if (all_same_temp
) {
1103 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1105 bool all_undef
= instr
->operands
[0].isUndefined();
1106 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1107 if (!instr
->operands
[i
].isUndefined())
1111 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1115 case aco_opcode::v_add_u32
:
1116 case aco_opcode::v_add_co_u32
:
1117 case aco_opcode::s_add_i32
:
1118 case aco_opcode::s_add_u32
:
1119 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1121 case aco_opcode::s_not_b32
:
1122 case aco_opcode::s_not_b64
:
1123 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1124 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1125 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1126 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1127 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1128 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1130 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1132 case aco_opcode::s_and_b32
:
1133 case aco_opcode::s_and_b64
:
1134 if (instr
->operands
[1].isFixed() && instr
->operands
[1].physReg() == exec
&& instr
->operands
[0].isTemp()) {
1135 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1136 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1137 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1138 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1140 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1141 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1142 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1143 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1148 case aco_opcode::s_or_b32
:
1149 case aco_opcode::s_or_b64
:
1150 case aco_opcode::s_xor_b32
:
1151 case aco_opcode::s_xor_b64
:
1152 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1153 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1155 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1158 case aco_opcode::s_lshl_b32
:
1159 case aco_opcode::v_or_b32
:
1160 case aco_opcode::v_lshlrev_b32
:
1161 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1163 case aco_opcode::v_min_f32
:
1164 case aco_opcode::v_min_f16
:
1165 case aco_opcode::v_min_u32
:
1166 case aco_opcode::v_min_i32
:
1167 case aco_opcode::v_min_u16
:
1168 case aco_opcode::v_min_i16
:
1169 case aco_opcode::v_max_f32
:
1170 case aco_opcode::v_max_f16
:
1171 case aco_opcode::v_max_u32
:
1172 case aco_opcode::v_max_i32
:
1173 case aco_opcode::v_max_u16
:
1174 case aco_opcode::v_max_i16
:
1175 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1177 case aco_opcode::v_cmp_lt_f32
:
1178 case aco_opcode::v_cmp_eq_f32
:
1179 case aco_opcode::v_cmp_le_f32
:
1180 case aco_opcode::v_cmp_gt_f32
:
1181 case aco_opcode::v_cmp_lg_f32
:
1182 case aco_opcode::v_cmp_ge_f32
:
1183 case aco_opcode::v_cmp_o_f32
:
1184 case aco_opcode::v_cmp_u_f32
:
1185 case aco_opcode::v_cmp_nge_f32
:
1186 case aco_opcode::v_cmp_nlg_f32
:
1187 case aco_opcode::v_cmp_ngt_f32
:
1188 case aco_opcode::v_cmp_nle_f32
:
1189 case aco_opcode::v_cmp_neq_f32
:
1190 case aco_opcode::v_cmp_nlt_f32
:
1191 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1193 case aco_opcode::s_cselect_b64
:
1194 case aco_opcode::s_cselect_b32
:
1195 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1196 instr
->operands
[1].constantEquals(0)) {
1197 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1198 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1200 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1201 /* Flip the operands to get rid of the scc_invert instruction */
1202 std::swap(instr
->operands
[0], instr
->operands
[1]);
1203 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1206 case aco_opcode::p_wqm
:
1207 if (instr
->operands
[0].isTemp() &&
1208 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1209 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1217 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1219 *ordered
= *unordered
= op
;
1221 #define CMP(ord, unord) \
1222 case aco_opcode::v_cmp_##ord##_f32:\
1223 case aco_opcode::v_cmp_n##unord##_f32:\
1224 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1225 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1226 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1240 aco_opcode
get_ordered(aco_opcode op
)
1242 aco_opcode ordered
, unordered
, inverse
;
1243 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1246 aco_opcode
get_unordered(aco_opcode op
)
1248 aco_opcode ordered
, unordered
, inverse
;
1249 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1252 aco_opcode
get_inverse(aco_opcode op
)
1254 aco_opcode ordered
, unordered
, inverse
;
1255 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1258 bool is_cmp(aco_opcode op
)
1260 aco_opcode ordered
, unordered
, inverse
;
1261 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1264 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1266 if (ctx
.info
[tmp
.id()].is_temp())
1267 return ctx
.info
[tmp
.id()].temp
.id();
1272 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1274 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1275 for (const Operand
& op
: instr
->operands
) {
1277 ctx
.uses
[op
.tempId()]--;
1282 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1284 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1286 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1289 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1291 if (instr
->definitions
.size() == 2) {
1292 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1293 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1300 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1301 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1302 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1304 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1306 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1309 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1311 bool neg
[2] = {false, false};
1312 bool abs
[2] = {false, false};
1314 Instruction
*op_instr
[2];
1317 for (unsigned i
= 0; i
< 2; i
++) {
1318 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1322 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1324 if (op_instr
[i
]->opcode
!= expected_cmp
)
1326 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1329 if (op_instr
[i
]->isVOP3()) {
1330 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1331 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1333 neg
[i
] = vop3
->neg
[0];
1334 abs
[i
] = vop3
->abs
[0];
1335 opsel
|= (vop3
->opsel
& 1) << i
;
1338 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1339 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1340 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1346 if (op
[1].type() == RegType::sgpr
)
1347 std::swap(op
[0], op
[1]);
1348 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1349 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1352 ctx
.uses
[op
[0].id()]++;
1353 ctx
.uses
[op
[1].id()]++;
1354 decrease_uses(ctx
, op_instr
[0]);
1355 decrease_uses(ctx
, op_instr
[1]);
1357 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1358 Instruction
*new_instr
;
1359 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1360 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1361 for (unsigned i
= 0; i
< 2; i
++) {
1362 vop3
->neg
[i
] = neg
[i
];
1363 vop3
->abs
[i
] = abs
[i
];
1365 vop3
->opsel
= opsel
;
1366 new_instr
= static_cast<Instruction
*>(vop3
);
1368 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1370 new_instr
->operands
[0] = Operand(op
[0]);
1371 new_instr
->operands
[1] = Operand(op
[1]);
1372 new_instr
->definitions
[0] = instr
->definitions
[0];
1374 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1375 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1377 instr
.reset(new_instr
);
1382 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1383 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1384 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1386 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1388 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1391 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1392 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1394 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1395 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1396 if (!nan_test
|| !cmp
)
1399 if (cmp
->opcode
== expected_nan_test
)
1400 std::swap(nan_test
, cmp
);
1401 else if (nan_test
->opcode
!= expected_nan_test
)
1404 if (!is_cmp(cmp
->opcode
))
1407 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1409 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1412 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1413 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1414 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1415 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1416 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1418 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1421 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1422 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1423 decrease_uses(ctx
, nan_test
);
1424 decrease_uses(ctx
, cmp
);
1426 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1427 Instruction
*new_instr
;
1428 if (cmp
->isVOP3()) {
1429 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1430 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1431 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1432 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1433 new_vop3
->clamp
= cmp_vop3
->clamp
;
1434 new_vop3
->omod
= cmp_vop3
->omod
;
1435 new_vop3
->opsel
= cmp_vop3
->opsel
;
1436 new_instr
= new_vop3
;
1438 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1440 new_instr
->operands
[0] = cmp
->operands
[0];
1441 new_instr
->operands
[1] = cmp
->operands
[1];
1442 new_instr
->definitions
[0] = instr
->definitions
[0];
1444 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1445 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1447 instr
.reset(new_instr
);
1452 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1453 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1454 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1456 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1458 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1461 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1463 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1464 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1466 if (!nan_test
|| !cmp
)
1469 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1470 if (cmp
->opcode
== expected_nan_test
)
1471 std::swap(nan_test
, cmp
);
1472 else if (nan_test
->opcode
!= expected_nan_test
)
1475 if (!is_cmp(cmp
->opcode
))
1478 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1480 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1483 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1484 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1485 if (prop_nan0
!= prop_nan1
)
1488 if (nan_test
->isVOP3()) {
1489 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1490 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1494 int constant_operand
= -1;
1495 for (unsigned i
= 0; i
< 2; i
++) {
1496 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1497 constant_operand
= !i
;
1501 if (constant_operand
== -1)
1505 if (cmp
->operands
[constant_operand
].isConstant()) {
1506 constant
= cmp
->operands
[constant_operand
].constantValue();
1507 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1508 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1509 unsigned id
= original_temp_id(ctx
, tmp
);
1510 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1512 constant
= ctx
.info
[id
].val
;
1518 memcpy(&constantf
, &constant
, 4);
1519 if (isnan(constantf
))
1522 if (cmp
->operands
[0].isTemp())
1523 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1524 if (cmp
->operands
[1].isTemp())
1525 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1526 decrease_uses(ctx
, nan_test
);
1527 decrease_uses(ctx
, cmp
);
1529 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1530 Instruction
*new_instr
;
1531 if (cmp
->isVOP3()) {
1532 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1533 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1534 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1535 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1536 new_vop3
->clamp
= cmp_vop3
->clamp
;
1537 new_vop3
->omod
= cmp_vop3
->omod
;
1538 new_vop3
->opsel
= cmp_vop3
->opsel
;
1539 new_instr
= new_vop3
;
1541 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1543 new_instr
->operands
[0] = cmp
->operands
[0];
1544 new_instr
->operands
[1] = cmp
->operands
[1];
1545 new_instr
->definitions
[0] = instr
->definitions
[0];
1547 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1548 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1550 instr
.reset(new_instr
);
1555 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1556 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1558 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1560 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1562 if (!instr
->operands
[0].isTemp())
1565 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1569 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1570 if (new_opcode
== aco_opcode::last_opcode
)
1573 if (cmp
->operands
[0].isTemp())
1574 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1575 if (cmp
->operands
[1].isTemp())
1576 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1577 decrease_uses(ctx
, cmp
);
1579 Instruction
*new_instr
;
1580 if (cmp
->isVOP3()) {
1581 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1582 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1583 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1584 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1585 new_vop3
->clamp
= cmp_vop3
->clamp
;
1586 new_vop3
->omod
= cmp_vop3
->omod
;
1587 new_vop3
->opsel
= cmp_vop3
->opsel
;
1588 new_instr
= new_vop3
;
1590 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1592 new_instr
->operands
[0] = cmp
->operands
[0];
1593 new_instr
->operands
[1] = cmp
->operands
[1];
1594 new_instr
->definitions
[0] = instr
->definitions
[0];
1596 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1597 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1599 instr
.reset(new_instr
);
1604 /* op1(op2(1, 2), 0) if swap = false
1605 * op1(0, op2(1, 2)) if swap = true */
1606 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1607 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1608 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1609 bool *op1_clamp
, uint8_t *op1_omod
,
1610 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1613 if (op1_instr
->opcode
!= op1
)
1616 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1617 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1620 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1621 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1623 /* don't support inbetween clamp/omod */
1624 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1627 /* get operands and modifiers and check inbetween modifiers */
1628 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1629 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1632 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1633 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1637 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1638 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1641 if (inbetween_opsel
)
1642 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1643 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1647 shuffle
[shuffle_str
[0] - '0'] = 0;
1648 shuffle
[shuffle_str
[1] - '0'] = 1;
1649 shuffle
[shuffle_str
[2] - '0'] = 2;
1651 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1652 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1653 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1654 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1655 *opsel
|= 1 << shuffle
[0];
1657 for (unsigned i
= 0; i
< 2; i
++) {
1658 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1659 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1660 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1661 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1662 *opsel
|= 1 << shuffle
[i
+ 1];
1665 /* check operands */
1666 if (!check_vop3_operands(ctx
, 3, operands
))
1672 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1673 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1674 bool clamp
, unsigned omod
)
1676 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1677 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1678 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1679 new_instr
->clamp
= clamp
;
1680 new_instr
->omod
= omod
;
1681 new_instr
->opsel
= opsel
;
1682 new_instr
->operands
[0] = operands
[0];
1683 new_instr
->operands
[1] = operands
[1];
1684 new_instr
->operands
[2] = operands
[2];
1685 new_instr
->definitions
[0] = instr
->definitions
[0];
1686 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1688 instr
.reset(new_instr
);
1691 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1693 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1694 (label_omod_success
| label_clamp_success
);
1696 for (unsigned swap
= 0; swap
< 2; swap
++) {
1697 if (!((1 << swap
) & ops
))
1700 Operand operands
[3];
1701 bool neg
[3], abs
[3], clamp
;
1702 uint8_t opsel
= 0, omod
= 0;
1703 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1704 instr
.get(), swap
, shuffle
,
1705 operands
, neg
, abs
, &opsel
,
1706 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1707 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1708 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1709 if (omod_clamp
& label_omod_success
)
1710 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1711 if (omod_clamp
& label_clamp_success
)
1712 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1719 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1721 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1724 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1725 (label_omod_success
| label_clamp_success
);
1727 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1728 * max(-min(a, b), c) -> max3(-a, -b, c) */
1729 for (unsigned swap
= 0; swap
< 2; swap
++) {
1730 Operand operands
[3];
1731 bool neg
[3], abs
[3], clamp
;
1732 uint8_t opsel
= 0, omod
= 0;
1734 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1735 instr
.get(), swap
, "012",
1736 operands
, neg
, abs
, &opsel
,
1737 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1739 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1742 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1743 if (omod_clamp
& label_omod_success
)
1744 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1745 if (omod_clamp
& label_clamp_success
)
1746 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1753 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1754 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1755 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1756 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1757 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1758 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1759 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1762 if (!instr
->operands
[0].isTemp())
1764 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1767 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1770 switch (op2_instr
->opcode
) {
1771 case aco_opcode::s_and_b32
:
1772 case aco_opcode::s_or_b32
:
1773 case aco_opcode::s_xor_b32
:
1774 case aco_opcode::s_and_b64
:
1775 case aco_opcode::s_or_b64
:
1776 case aco_opcode::s_xor_b64
:
1782 /* create instruction */
1783 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1784 ctx
.uses
[instr
->operands
[0].tempId()]--;
1785 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1787 switch (op2_instr
->opcode
) {
1788 case aco_opcode::s_and_b32
:
1789 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1791 case aco_opcode::s_or_b32
:
1792 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1794 case aco_opcode::s_xor_b32
:
1795 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1797 case aco_opcode::s_and_b64
:
1798 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1800 case aco_opcode::s_or_b64
:
1801 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1803 case aco_opcode::s_xor_b64
:
1804 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1813 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1814 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1815 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1816 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1817 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1819 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1822 for (unsigned i
= 0; i
< 2; i
++) {
1823 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1824 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1827 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1828 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1831 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1832 instr
->operands
[0] = instr
->operands
[!i
];
1833 instr
->operands
[1] = op2_instr
->operands
[0];
1834 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1836 switch (instr
->opcode
) {
1837 case aco_opcode::s_and_b32
:
1838 instr
->opcode
= aco_opcode::s_andn2_b32
;
1840 case aco_opcode::s_or_b32
:
1841 instr
->opcode
= aco_opcode::s_orn2_b32
;
1843 case aco_opcode::s_and_b64
:
1844 instr
->opcode
= aco_opcode::s_andn2_b64
;
1846 case aco_opcode::s_or_b64
:
1847 instr
->opcode
= aco_opcode::s_orn2_b64
;
1858 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1859 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1861 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1864 for (unsigned i
= 0; i
< 2; i
++) {
1865 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1866 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
|| !op2_instr
->operands
[1].isConstant())
1869 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1870 if (shift
< 1 || shift
> 4)
1873 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1874 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1877 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1878 instr
->operands
[1] = instr
->operands
[!i
];
1879 instr
->operands
[0] = op2_instr
->operands
[0];
1880 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1882 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1883 aco_opcode::s_lshl2_add_u32
,
1884 aco_opcode::s_lshl3_add_u32
,
1885 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1892 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1895 #define MINMAX(type, gfx9) \
1896 case aco_opcode::v_min_##type:\
1897 case aco_opcode::v_max_##type:\
1898 case aco_opcode::v_med3_##type:\
1899 *min = aco_opcode::v_min_##type;\
1900 *max = aco_opcode::v_max_##type;\
1901 *med3 = aco_opcode::v_med3_##type;\
1902 *min3 = aco_opcode::v_min3_##type;\
1903 *max3 = aco_opcode::v_max3_##type;\
1904 *some_gfx9_only = gfx9;\
1918 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1919 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1920 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1921 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1923 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1924 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1925 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1926 aco_opcode other_op
;
1927 if (instr
->opcode
== min
)
1929 else if (instr
->opcode
== max
)
1934 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1935 (label_omod_success
| label_clamp_success
);
1937 for (unsigned swap
= 0; swap
< 2; swap
++) {
1938 Operand operands
[3];
1939 bool neg
[3], abs
[3], clamp
;
1940 uint8_t opsel
= 0, omod
= 0;
1941 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1942 "012", operands
, neg
, abs
, &opsel
,
1943 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1944 int const0_idx
= -1, const1_idx
= -1;
1945 uint32_t const0
= 0, const1
= 0;
1946 for (int i
= 0; i
< 3; i
++) {
1948 if (operands
[i
].isConstant()) {
1949 val
= operands
[i
].constantValue();
1950 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
1951 val
= ctx
.info
[operands
[i
].tempId()].val
;
1955 if (const0_idx
>= 0) {
1963 if (const0_idx
< 0 || const1_idx
< 0)
1966 if (opsel
& (1 << const0_idx
))
1968 if (opsel
& (1 << const1_idx
))
1971 int lower_idx
= const0_idx
;
1973 case aco_opcode::v_min_f32
:
1974 case aco_opcode::v_min_f16
: {
1975 float const0_f
, const1_f
;
1976 if (min
== aco_opcode::v_min_f32
) {
1977 memcpy(&const0_f
, &const0
, 4);
1978 memcpy(&const1_f
, &const1
, 4);
1980 const0_f
= _mesa_half_to_float(const0
);
1981 const1_f
= _mesa_half_to_float(const1
);
1983 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
1984 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
1985 if (neg
[const0_idx
]) const0_f
= -const0_f
;
1986 if (neg
[const1_idx
]) const1_f
= -const1_f
;
1987 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
1990 case aco_opcode::v_min_u32
: {
1991 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
1994 case aco_opcode::v_min_u16
: {
1995 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
1998 case aco_opcode::v_min_i32
: {
1999 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2000 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2001 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2004 case aco_opcode::v_min_i16
: {
2005 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2006 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2007 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2013 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2015 if (instr
->opcode
== min
) {
2016 if (upper_idx
!= 0 || lower_idx
== 0)
2019 if (upper_idx
== 0 || lower_idx
!= 0)
2023 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2024 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2025 if (omod_clamp
& label_omod_success
)
2026 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2027 if (omod_clamp
& label_clamp_success
)
2028 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2038 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2040 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2041 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2042 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2044 /* find candidates and create the set of sgprs already read */
2045 unsigned sgpr_ids
[2] = {0, 0};
2046 uint32_t operand_mask
= 0;
2047 bool has_literal
= false;
2048 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2049 if (instr
->operands
[i
].isLiteral())
2051 if (!instr
->operands
[i
].isTemp())
2053 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2054 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2055 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2057 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2058 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2059 operand_mask
|= 1u << i
;
2061 unsigned max_sgprs
= 1;
2062 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2067 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2069 /* keep on applying sgprs until there is nothing left to be done */
2070 while (operand_mask
) {
2071 uint32_t sgpr_idx
= 0;
2072 uint32_t sgpr_info_id
= 0;
2073 uint32_t mask
= operand_mask
;
2076 unsigned i
= u_bit_scan(&mask
);
2077 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2078 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2080 sgpr_info_id
= instr
->operands
[i
].tempId();
2083 operand_mask
&= ~(1u << sgpr_idx
);
2085 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2086 * definitively beneficial.
2087 * TODO: this is too conservative because later the use count could be reduced to 1 */
2088 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2091 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2092 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2093 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2096 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2097 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2098 } else if (can_swap_operands(instr
)) {
2099 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2100 instr
->operands
[0] = Operand(sgpr
);
2101 /* swap bits using a 4-entry LUT */
2102 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2103 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2104 } else if (can_use_VOP3(ctx
, instr
)) {
2105 to_VOP3(ctx
, instr
);
2106 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2111 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2112 ctx
.uses
[sgpr_info_id
]--;
2113 ctx
.uses
[sgpr
.id()]++;
2117 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2119 /* check if we could apply omod on predecessor */
2120 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2121 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2122 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2124 unsigned idx
= op0
? 0 : 1;
2125 /* omod was successfully applied */
2126 /* if the omod instruction is v_mad, we also have to change the original add */
2127 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2128 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2129 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2130 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2131 add_instr
->definitions
[0] = instr
->definitions
[0];
2134 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2135 /* check if we have an additional clamp modifier */
2136 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2137 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2138 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2139 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2141 /* change definition ssa-id of modified instruction */
2142 omod_instr
->definitions
[0] = instr
->definitions
[0];
2144 /* change the definition of instr to something unused, e.g. the original omod def */
2145 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2146 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2149 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2150 /* in all other cases, label this instruction as option for multiply-add */
2151 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2155 /* check if we could apply clamp on predecessor */
2156 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2158 bool found_zero
= false, found_one
= false;
2159 for (unsigned i
= 0; i
< 3; i
++)
2161 if (instr
->operands
[i
].constantEquals(0))
2163 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2168 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2169 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2170 /* clamp was successfully applied */
2171 /* if the clamp instruction is v_mad, we also have to change the original add */
2172 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2173 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2174 add_instr
->definitions
[0] = instr
->definitions
[0];
2176 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2177 /* change definition ssa-id of modified instruction */
2178 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2180 /* change the definition of instr to something unused, e.g. the original omod def */
2181 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2182 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2187 /* omod has no effect if denormals are enabled */
2188 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2190 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2191 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2192 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2193 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2194 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2195 to_VOP3(ctx
, instr
);
2196 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2197 def_info
.set_omod_success(instr
.get());
2198 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2199 to_VOP3(ctx
, instr
);
2200 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2201 def_info
.set_omod_success(instr
.get());
2202 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2203 to_VOP3(ctx
, instr
);
2204 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2205 def_info
.set_omod_success(instr
.get());
2206 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2207 to_VOP3(ctx
, instr
);
2208 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2209 def_info
.set_clamp_success(instr
.get());
2216 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2217 // this would mean that we'd have to fix the instruction uses while value propagation
2219 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2221 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2224 if (instr
->isVALU()) {
2225 if (can_apply_sgprs(instr
))
2226 apply_sgprs(ctx
, instr
);
2227 if (apply_omod_clamp(ctx
, block
, instr
))
2231 /* TODO: There are still some peephole optimizations that could be done:
2232 * - abs(a - b) -> s_absdiff_i32
2233 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2234 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2235 * These aren't probably too interesting though.
2236 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2237 * probably more useful than the previously mentioned optimizations.
2238 * The various comparison optimizations also currently only work with 32-bit
2241 /* neg(mul(a, b)) -> mul(neg(a), b) */
2242 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2243 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2245 if (!ctx
.info
[val
.id()].is_mul())
2248 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2250 if (mul_instr
->operands
[0].isLiteral())
2252 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2255 /* convert to mul(neg(a), b) */
2256 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2257 Definition def
= instr
->definitions
[0];
2258 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2259 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2260 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2261 instr
->operands
[0] = mul_instr
->operands
[0];
2262 instr
->operands
[1] = mul_instr
->operands
[1];
2263 instr
->definitions
[0] = def
;
2264 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2265 if (mul_instr
->isVOP3()) {
2266 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2267 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2268 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2269 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2270 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2271 new_mul
->omod
= mul
->omod
;
2273 new_mul
->neg
[0] ^= true;
2274 new_mul
->clamp
= false;
2276 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2279 /* combine mul+add -> mad */
2280 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2281 instr
->opcode
== aco_opcode::v_sub_f32
||
2282 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2283 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2284 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2286 uint32_t uses_src0
= UINT32_MAX
;
2287 uint32_t uses_src1
= UINT32_MAX
;
2288 Instruction
* mul_instr
= nullptr;
2289 unsigned add_op_idx
;
2290 /* check if any of the operands is a multiplication */
2291 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2292 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2293 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2294 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2296 /* find the 'best' mul instruction to combine with the add */
2297 if (uses_src0
< uses_src1
) {
2298 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2300 } else if (uses_src1
< uses_src0
) {
2301 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2303 } else if (uses_src0
!= UINT32_MAX
) {
2304 /* tiebreaker: quite random what to pick */
2305 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2306 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2309 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2314 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2315 bool neg
[3] = {false, false, false};
2316 bool abs
[3] = {false, false, false};
2319 op
[0] = mul_instr
->operands
[0];
2320 op
[1] = mul_instr
->operands
[1];
2321 op
[2] = instr
->operands
[add_op_idx
];
2322 // TODO: would be better to check this before selecting a mul instr?
2323 if (!check_vop3_operands(ctx
, 3, op
))
2326 if (mul_instr
->isVOP3()) {
2327 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2328 neg
[0] = vop3
->neg
[0];
2329 neg
[1] = vop3
->neg
[1];
2330 abs
[0] = vop3
->abs
[0];
2331 abs
[1] = vop3
->abs
[1];
2332 /* we cannot use these modifiers between mul and add */
2333 if (vop3
->clamp
|| vop3
->omod
)
2337 /* convert to mad */
2338 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2339 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2341 ctx
.uses
[op
[0].tempId()]++;
2343 ctx
.uses
[op
[1].tempId()]++;
2346 if (instr
->isVOP3()) {
2347 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2348 neg
[2] = vop3
->neg
[add_op_idx
];
2349 abs
[2] = vop3
->abs
[add_op_idx
];
2351 clamp
= vop3
->clamp
;
2352 /* abs of the multiplication result */
2353 if (vop3
->abs
[1 - add_op_idx
]) {
2359 /* neg of the multiplication result */
2360 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2362 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2363 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2364 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2365 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2367 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2368 for (unsigned i
= 0; i
< 3; i
++)
2370 mad
->operands
[i
] = op
[i
];
2371 mad
->neg
[i
] = neg
[i
];
2372 mad
->abs
[i
] = abs
[i
];
2376 mad
->definitions
[0] = instr
->definitions
[0];
2378 /* mark this ssa_def to be re-checked for profitability and literals */
2379 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2380 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2381 instr
.reset(mad
.release());
2385 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2386 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2387 for (unsigned i
= 0; i
< 2; i
++) {
2388 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2389 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2390 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2391 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2392 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2394 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2395 new_instr
->operands
[0] = Operand(0u);
2396 new_instr
->operands
[1] = instr
->operands
[!i
];
2397 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2398 new_instr
->definitions
[0] = instr
->definitions
[0];
2399 instr
.reset(new_instr
.release());
2400 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2404 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2405 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2406 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2407 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2408 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2409 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2410 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2411 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2412 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2413 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2414 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2415 combine_salu_lshl_add(ctx
, instr
);
2416 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2417 combine_salu_not_bitwise(ctx
, instr
);
2418 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2419 if (combine_inverse_comparison(ctx
, instr
)) ;
2420 else combine_salu_not_bitwise(ctx
, instr
);
2421 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2422 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2423 if (combine_ordering_test(ctx
, instr
)) ;
2424 else if (combine_comparison_ordering(ctx
, instr
)) ;
2425 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2426 else combine_salu_n2(ctx
, instr
);
2428 aco_opcode min
, max
, min3
, max3
, med3
;
2429 bool some_gfx9_only
;
2430 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2431 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2432 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2433 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2439 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2441 const uint32_t threshold
= 4;
2443 if (is_dead(ctx
.uses
, instr
.get())) {
2448 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2449 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2450 unsigned num_used
= 0;
2452 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2453 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2459 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2460 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2461 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2465 for (Operand
& vec_op
: vec
->operands
) {
2466 if (off
== idx
* instr
->definitions
[0].size()) {
2470 off
+= vec_op
.size();
2472 if (off
!= instr
->operands
[0].size()) {
2473 ctx
.uses
[instr
->operands
[0].tempId()]--;
2474 for (Operand
& vec_op
: vec
->operands
) {
2475 if (vec_op
.isTemp())
2476 ctx
.uses
[vec_op
.tempId()]--;
2479 ctx
.uses
[op
.tempId()]++;
2481 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2482 extract
->operands
[0] = op
;
2483 extract
->definitions
[0] = instr
->definitions
[idx
];
2484 instr
.reset(extract
.release());
2490 if (!done
&& num_used
== 1) {
2491 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2492 extract
->operands
[0] = instr
->operands
[0];
2493 extract
->operands
[1] = Operand((uint32_t) idx
);
2494 extract
->definitions
[0] = instr
->definitions
[idx
];
2495 instr
.reset(extract
.release());
2499 mad_info
* mad_info
= NULL
;
2500 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2501 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2502 /* re-check mad instructions */
2503 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2504 ctx
.uses
[mad_info
->mul_temp_id
]++;
2505 if (instr
->operands
[0].isTemp())
2506 ctx
.uses
[instr
->operands
[0].tempId()]--;
2507 if (instr
->operands
[1].isTemp())
2508 ctx
.uses
[instr
->operands
[1].tempId()]--;
2509 instr
.swap(mad_info
->add_instr
);
2512 /* check literals */
2513 else if (!instr
->usesModifiers()) {
2514 bool sgpr_used
= false;
2515 uint32_t literal_idx
= 0;
2516 uint32_t literal_uses
= UINT32_MAX
;
2517 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2519 if (instr
->operands
[i
].isConstant() && i
> 0) {
2520 literal_uses
= UINT32_MAX
;
2523 if (!instr
->operands
[i
].isTemp())
2525 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2526 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2527 if (ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2528 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2531 literal_uses
= UINT32_MAX
;
2534 /* don't break because we still need to check constants */
2535 } else if (!sgpr_used
&&
2536 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2537 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2538 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2542 if (literal_uses
< threshold
) {
2543 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2544 mad_info
->check_literal
= true;
2545 mad_info
->literal_idx
= literal_idx
;
2551 /* check for literals */
2552 if (!instr
->isSALU() && !instr
->isVALU())
2555 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2556 return; /* some encodings can't ever take literals */
2558 /* we do not apply the literals yet as we don't know if it is profitable */
2559 Operand
current_literal(s1
);
2561 unsigned literal_id
= 0;
2562 unsigned literal_uses
= UINT32_MAX
;
2563 Operand
literal(s1
);
2564 unsigned num_operands
= 1;
2565 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2566 num_operands
= instr
->operands
.size();
2568 unsigned sgpr_ids
[2] = {0, 0};
2569 bool is_literal_sgpr
= false;
2572 /* choose a literal to apply */
2573 for (unsigned i
= 0; i
< num_operands
; i
++) {
2574 Operand op
= instr
->operands
[i
];
2575 if (op
.isLiteral()) {
2576 current_literal
= op
;
2578 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2579 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2580 op
.tempId() != sgpr_ids
[0])
2581 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2585 if (!can_accept_constant(instr
, i
))
2588 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2589 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2591 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2592 literal_uses
= ctx
.uses
[op
.tempId()];
2593 literal_id
= op
.tempId();
2596 mask
|= (op
.tempId() == literal_id
) << i
;
2600 /* don't go over the constant bus limit */
2601 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2602 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2603 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2604 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2605 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2606 const_bus_limit
= 2;
2608 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2609 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2612 if (literal_id
&& literal_uses
< threshold
&&
2613 (current_literal
.isUndefined() ||
2614 (current_literal
.size() == literal
.size() &&
2615 current_literal
.constantValue() == literal
.constantValue()))) {
2616 /* mark the literal to be applied */
2618 unsigned i
= u_bit_scan(&mask
);
2619 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2620 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2626 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2628 /* Cleanup Dead Instructions */
2632 /* apply literals on MAD */
2633 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2634 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2635 if (info
->check_literal
&& ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0) {
2636 aco_ptr
<Instruction
> new_mad
;
2637 if (info
->literal_idx
== 2) { /* add literal -> madak */
2638 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2639 new_mad
->operands
[0] = instr
->operands
[0];
2640 new_mad
->operands
[1] = instr
->operands
[1];
2641 } else { /* mul literal -> madmk */
2642 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2643 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2644 new_mad
->operands
[1] = instr
->operands
[2];
2646 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2647 new_mad
->definitions
[0] = instr
->definitions
[0];
2648 ctx
.instructions
.emplace_back(std::move(new_mad
));
2653 /* apply literals on other SALU/VALU */
2654 if (instr
->isSALU() || instr
->isVALU()) {
2655 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2656 Operand op
= instr
->operands
[i
];
2657 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2658 Operand
literal(ctx
.info
[op
.tempId()].val
);
2659 if (instr
->isVALU() && i
> 0)
2660 to_VOP3(ctx
, instr
);
2661 instr
->operands
[i
] = literal
;
2666 ctx
.instructions
.emplace_back(std::move(instr
));
2670 void optimize(Program
* program
)
2673 ctx
.program
= program
;
2674 std::vector
<ssa_info
> info(program
->peekAllocationId());
2675 ctx
.info
= info
.data();
2677 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2678 for (Block
& block
: program
->blocks
) {
2679 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2680 label_instruction(ctx
, block
, instr
);
2683 ctx
.uses
= std::move(dead_code_analysis(program
));
2685 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2686 for (Block
& block
: program
->blocks
) {
2687 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2688 combine_instruction(ctx
, block
, instr
);
2691 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2692 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2693 Block
* block
= &(*it
);
2694 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2695 select_instruction(ctx
, *it
);
2698 /* 4. Add literals to instructions */
2699 for (Block
& block
: program
->blocks
) {
2700 ctx
.instructions
.clear();
2701 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2702 apply_literals(ctx
, instr
);
2703 block
.instructions
.swap(ctx
.instructions
);