2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
25 * Bas Nieuwenhuizen (bas@basnieuwenhuizen.nl)
32 #include <unordered_map>
37 #include "util/u_math.h"
43 std::bitset
<512> war_hint
;
45 std::unordered_map
<unsigned, std::pair
<PhysReg
, RegClass
>> assignments
;
46 std::map
<unsigned, Temp
> orig_names
;
47 unsigned max_used_sgpr
= 0;
48 unsigned max_used_vgpr
= 0;
49 std::bitset
<64> defs_done
; /* see MAX_ARGS in aco_instruction_selection_setup.cpp */
51 ra_ctx(Program
* program
) : program(program
) {}
55 /* helper function for debugging */
57 void print_regs(ra_ctx
& ctx
, bool vgprs
, std::array
<uint32_t, 512>& reg_file
)
59 unsigned max
= vgprs
? ctx
.program
->max_reg_demand
.vgpr
: ctx
.program
->max_reg_demand
.sgpr
;
60 unsigned lb
= vgprs
? 256 : 0;
61 unsigned ub
= lb
+ max
;
62 char reg_char
= vgprs
? 'v' : 's';
66 for (unsigned i
= lb
; i
< ub
; i
+= 3) {
67 printf("%.2u ", i
- lb
);
72 printf("%cgprs: ", reg_char
);
73 unsigned free_regs
= 0;
75 bool char_select
= false;
76 for (unsigned i
= lb
; i
< ub
; i
++) {
77 if (reg_file
[i
] == 0xFFFF) {
79 } else if (reg_file
[i
]) {
80 if (reg_file
[i
] != prev
) {
82 char_select
= !char_select
;
84 printf(char_select
? "#" : "@");
92 printf("%u/%u used, %u/%u free\n", max
- free_regs
, max
, free_regs
, max
);
94 /* print assignments */
97 for (unsigned i
= lb
; i
< ub
; i
++) {
98 if (reg_file
[i
] != prev
) {
100 printf("-%d]\n", i
- 1 - lb
);
104 if (prev
&& prev
!= 0xFFFF) {
105 if (ctx
.orig_names
.count(reg_file
[i
]) && ctx
.orig_names
[reg_file
[i
]].id() != reg_file
[i
])
106 printf("%%%u (was %%%d) = %c[%d", reg_file
[i
], ctx
.orig_names
[reg_file
[i
]].id(), reg_char
, i
- lb
);
108 printf("%%%u = %c[%d", reg_file
[i
], reg_char
, i
- lb
);
115 if (prev
&& size
> 1)
116 printf("-%d]\n", ub
- lb
- 1);
123 void adjust_max_used_regs(ra_ctx
& ctx
, RegClass rc
, unsigned reg
)
125 unsigned max_addressible_sgpr
= ctx
.program
->sgpr_limit
;
126 unsigned size
= rc
.size();
127 if (rc
.type() == RegType::vgpr
) {
129 unsigned hi
= reg
- 256 + size
- 1;
130 ctx
.max_used_vgpr
= std::max(ctx
.max_used_vgpr
, hi
);
131 } else if (reg
+ rc
.size() <= max_addressible_sgpr
) {
132 unsigned hi
= reg
+ size
- 1;
133 ctx
.max_used_sgpr
= std::max(ctx
.max_used_sgpr
, std::min(hi
, max_addressible_sgpr
));
138 void update_renames(ra_ctx
& ctx
, std::array
<uint32_t, 512>& reg_file
,
139 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
140 aco_ptr
<Instruction
>& instr
)
142 /* allocate id's and rename operands: this is done transparently here */
143 for (std::pair
<Operand
, Definition
>& copy
: parallelcopies
) {
144 /* the definitions with id are not from this function and already handled */
145 if (copy
.second
.isTemp())
148 // FIXME: if a definition got moved, change the target location and remove the parallelcopy
149 copy
.second
.setTemp(Temp(ctx
.program
->allocateId(), copy
.second
.regClass()));
150 ctx
.assignments
[copy
.second
.tempId()] = {copy
.second
.physReg(), copy
.second
.regClass()};
151 for (unsigned i
= copy
.second
.physReg().reg
; i
< copy
.second
.physReg() + copy
.second
.size(); i
++)
152 reg_file
[i
] = copy
.second
.tempId();
153 /* check if we moved an operand */
154 for (Operand
& op
: instr
->operands
) {
157 if (op
.tempId() == copy
.first
.tempId()) {
158 bool omit_renaming
= instr
->opcode
== aco_opcode::p_create_vector
&& !op
.isKill();
159 for (std::pair
<Operand
, Definition
>& pc
: parallelcopies
) {
160 PhysReg def_reg
= pc
.second
.physReg();
161 omit_renaming
&= def_reg
> copy
.first
.physReg() ?
162 (copy
.first
.physReg() + copy
.first
.size() <= def_reg
.reg
) :
163 (def_reg
+ pc
.second
.size() <= copy
.first
.physReg().reg
);
167 op
.setTemp(copy
.second
.getTemp());
168 op
.setFixed(copy
.second
.physReg());
174 std::pair
<PhysReg
, bool> get_reg_simple(ra_ctx
& ctx
,
175 std::array
<uint32_t, 512>& reg_file
,
176 uint32_t lb
, uint32_t ub
,
177 uint32_t size
, uint32_t stride
,
180 /* best fit algorithm: find the smallest gap to fit in the variable */
182 unsigned best_pos
= 0xFFFF;
183 unsigned gap_size
= 0xFFFF;
184 unsigned next_pos
= 0xFFFF;
186 for (unsigned current_reg
= lb
; current_reg
< ub
; current_reg
++) {
187 if (reg_file
[current_reg
] != 0 || ctx
.war_hint
[current_reg
]) {
188 if (next_pos
== 0xFFFF)
191 /* check if the variable fits */
192 if (next_pos
+ size
> current_reg
) {
197 /* check if the tested gap is smaller */
198 if (current_reg
- next_pos
< gap_size
) {
200 gap_size
= current_reg
- next_pos
;
206 if (next_pos
== 0xFFFF)
207 next_pos
= current_reg
;
211 if (next_pos
!= 0xFFFF &&
212 next_pos
+ size
<= ub
&&
213 ub
- next_pos
< gap_size
) {
215 gap_size
= ub
- next_pos
;
217 if (best_pos
!= 0xFFFF) {
218 adjust_max_used_regs(ctx
, rc
, best_pos
);
219 return {PhysReg
{best_pos
}, true};
225 unsigned reg_lo
= lb
;
226 unsigned reg_hi
= lb
+ size
- 1;
227 while (!found
&& reg_lo
+ size
<= ub
) {
228 if (reg_file
[reg_lo
] != 0) {
232 reg_hi
= reg_lo
+ size
- 1;
234 for (unsigned reg
= reg_lo
+ 1; found
&& reg
<= reg_hi
; reg
++) {
235 if (reg_file
[reg
] != 0 || ctx
.war_hint
[reg
])
239 adjust_max_used_regs(ctx
, rc
, reg_lo
);
240 return {PhysReg
{reg_lo
}, true};
249 bool get_regs_for_copies(ra_ctx
& ctx
,
250 std::array
<uint32_t, 512>& reg_file
,
251 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
252 std::set
<std::pair
<unsigned, unsigned>> vars
,
253 uint32_t lb
, uint32_t ub
,
254 aco_ptr
<Instruction
>& instr
,
259 /* variables are sorted from small sized to large */
260 /* NOTE: variables are also sorted by ID. this only affects a very small number of shaders slightly though. */
261 for (std::set
<std::pair
<unsigned, unsigned>>::reverse_iterator it
= vars
.rbegin(); it
!= vars
.rend(); ++it
) {
262 unsigned id
= it
->second
;
263 std::pair
<PhysReg
, RegClass
> var
= ctx
.assignments
[id
];
264 uint32_t size
= it
->first
;
266 if (var
.second
.type() == RegType::sgpr
) {
273 /* check if this is a dead operand, then we can re-use the space from the definition */
274 bool is_dead_operand
= false;
275 for (unsigned i
= 0; !is_phi(instr
) && !is_dead_operand
&& i
< instr
->operands
.size(); i
++) {
276 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].isKill() && instr
->operands
[i
].tempId() == id
)
277 is_dead_operand
= true;
280 std::pair
<PhysReg
, bool> res
;
281 if (is_dead_operand
) {
282 if (instr
->opcode
== aco_opcode::p_create_vector
) {
283 for (unsigned i
= 0, offset
= 0; i
< instr
->operands
.size(); offset
+= instr
->operands
[i
].size(), i
++) {
284 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == id
) {
285 for (unsigned j
= 0; j
< size
; j
++)
286 assert(reg_file
[def_reg_lo
+ offset
+ j
] == 0);
287 res
= {PhysReg
{def_reg_lo
+ offset
}, true};
292 res
= get_reg_simple(ctx
, reg_file
, def_reg_lo
, def_reg_hi
+ 1, size
, stride
, var
.second
);
295 res
= get_reg_simple(ctx
, reg_file
, lb
, def_reg_lo
, size
, stride
, var
.second
);
297 unsigned lb
= (def_reg_hi
+ stride
) & ~(stride
- 1);
298 res
= get_reg_simple(ctx
, reg_file
, lb
, ub
, size
, stride
, var
.second
);
303 /* mark the area as blocked */
304 for (unsigned i
= res
.first
.reg
; i
< res
.first
+ size
; i
++)
305 reg_file
[i
] = 0xFFFFFFFF;
306 /* create parallelcopy pair (without definition id) */
307 Temp tmp
= Temp(id
, var
.second
);
308 Operand pc_op
= Operand(tmp
);
309 pc_op
.setFixed(var
.first
);
310 Definition pc_def
= Definition(res
.first
, pc_op
.regClass());
311 parallelcopies
.emplace_back(pc_op
, pc_def
);
315 unsigned best_pos
= lb
;
316 unsigned num_moves
= 0xFF;
317 unsigned num_vars
= 0;
319 /* we use a sliding window to find potential positions */
320 unsigned reg_lo
= lb
;
321 unsigned reg_hi
= lb
+ size
- 1;
322 for (reg_lo
= lb
, reg_hi
= lb
+ size
- 1; reg_hi
< ub
; reg_lo
+= stride
, reg_hi
+= stride
) {
323 if (!is_dead_operand
&& ((reg_lo
>= def_reg_lo
&& reg_lo
<= def_reg_hi
) ||
324 (reg_hi
>= def_reg_lo
&& reg_hi
<= def_reg_hi
)))
327 /* second, check that we have at most k=num_moves elements in the window
328 * and no element is larger than the currently processed one */
331 unsigned last_var
= 0;
333 for (unsigned j
= reg_lo
; found
&& j
<= reg_hi
; j
++) {
334 if (reg_file
[j
] == 0 || reg_file
[j
] == last_var
)
337 /* 0xFFFF signals that this area is already blocked! */
338 if (reg_file
[j
] == 0xFFFFFFFF || k
> num_moves
) {
342 /* we cannot split live ranges of linear vgprs */
343 if (ctx
.assignments
[reg_file
[j
]].second
& (1 << 6)) {
347 bool is_kill
= false;
348 for (const Operand
& op
: instr
->operands
) {
349 if (op
.isTemp() && op
.isKill() && op
.tempId() == reg_file
[j
]) {
354 if (!is_kill
&& ctx
.assignments
[reg_file
[j
]].second
.size() >= size
) {
359 k
+= ctx
.assignments
[reg_file
[j
]].second
.size();
360 last_var
= reg_file
[j
];
362 if (k
> num_moves
|| (k
== num_moves
&& n
<= num_vars
)) {
375 /* FIXME: we messed up and couldn't find space for the variables to be copied */
376 if (num_moves
== 0xFF)
380 reg_hi
= best_pos
+ size
- 1;
382 /* collect variables and block reg file */
383 std::set
<std::pair
<unsigned, unsigned>> new_vars
;
384 for (unsigned j
= reg_lo
; j
<= reg_hi
; j
++) {
385 if (reg_file
[j
] != 0) {
386 unsigned size
= ctx
.assignments
[reg_file
[j
]].second
.size();
387 unsigned id
= reg_file
[j
];
388 new_vars
.emplace(size
, id
);
389 for (unsigned k
= 0; k
< size
; k
++)
390 reg_file
[ctx
.assignments
[id
].first
+ k
] = 0;
394 /* mark the area as blocked */
395 for (unsigned i
= reg_lo
; i
<= reg_hi
; i
++)
396 reg_file
[i
] = 0xFFFFFFFF;
398 if (!get_regs_for_copies(ctx
, reg_file
, parallelcopies
, new_vars
, lb
, ub
, instr
, def_reg_lo
, def_reg_hi
))
401 adjust_max_used_regs(ctx
, var
.second
, reg_lo
);
403 /* create parallelcopy pair (without definition id) */
404 Temp tmp
= Temp(id
, var
.second
);
405 Operand pc_op
= Operand(tmp
);
406 pc_op
.setFixed(var
.first
);
407 Definition pc_def
= Definition(PhysReg
{reg_lo
}, pc_op
.regClass());
408 parallelcopies
.emplace_back(pc_op
, pc_def
);
415 std::pair
<PhysReg
, bool> get_reg_impl(ra_ctx
& ctx
,
416 std::array
<uint32_t, 512>& reg_file
,
417 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
418 uint32_t lb
, uint32_t ub
,
419 uint32_t size
, uint32_t stride
,
421 aco_ptr
<Instruction
>& instr
)
423 unsigned regs_free
= 0;
424 /* check how many free regs we have */
425 for (unsigned j
= lb
; j
< ub
; j
++) {
426 if (reg_file
[j
] == 0)
430 /* mark and count killed operands */
431 unsigned killed_ops
= 0;
432 for (unsigned j
= 0; !is_phi(instr
) && j
< instr
->operands
.size(); j
++) {
433 if (instr
->operands
[j
].isTemp() &&
434 instr
->operands
[j
].isFirstKill() &&
435 instr
->operands
[j
].physReg() >= lb
&&
436 instr
->operands
[j
].physReg() < ub
) {
437 assert(instr
->operands
[j
].isFixed());
438 assert(reg_file
[instr
->operands
[j
].physReg().reg
] == 0);
439 for (unsigned k
= 0; k
< instr
->operands
[j
].size(); k
++)
440 reg_file
[instr
->operands
[j
].physReg() + k
] = 0xFFFFFFFF;
441 killed_ops
+= instr
->operands
[j
].getTemp().size();
445 assert(regs_free
>= size
);
446 /* we might have to move dead operands to dst in order to make space */
447 unsigned op_moves
= 0;
449 if (size
> (regs_free
- killed_ops
))
450 op_moves
= size
- (regs_free
- killed_ops
);
452 /* find the best position to place the definition */
453 unsigned best_pos
= lb
;
454 unsigned num_moves
= 0xFF;
455 unsigned num_vars
= 0;
457 /* we use a sliding window to check potential positions */
458 unsigned reg_lo
= lb
;
459 unsigned reg_hi
= lb
+ size
- 1;
460 for (reg_lo
= lb
, reg_hi
= lb
+ size
- 1; reg_hi
< ub
; reg_lo
+= stride
, reg_hi
+= stride
) {
461 /* first check the edges: this is what we have to fix to allow for num_moves > size */
462 if (reg_lo
> lb
&& reg_file
[reg_lo
] != 0 && reg_file
[reg_lo
] == reg_file
[reg_lo
- 1])
464 if (reg_hi
< ub
- 1 && reg_file
[reg_hi
] != 0 && reg_file
[reg_hi
] == reg_file
[reg_hi
+ 1])
467 /* second, check that we have at most k=num_moves elements in the window
468 * and no element is larger than the currently processed one */
469 unsigned k
= op_moves
;
471 unsigned remaining_op_moves
= op_moves
;
472 unsigned last_var
= 0;
474 bool aligned
= rc
== RegClass::v4
&& reg_lo
% 4 == 0;
475 for (unsigned j
= reg_lo
; found
&& j
<= reg_hi
; j
++) {
476 if (reg_file
[j
] == 0 || reg_file
[j
] == last_var
)
479 /* dead operands effectively reduce the number of estimated moves */
480 if (remaining_op_moves
&& reg_file
[j
] == 0xFFFFFFFF) {
482 remaining_op_moves
--;
486 if (ctx
.assignments
[reg_file
[j
]].second
.size() >= size
) {
492 /* we cannot split live ranges of linear vgprs */
493 if (ctx
.assignments
[reg_file
[j
]].second
& (1 << 6)) {
498 k
+= ctx
.assignments
[reg_file
[j
]].second
.size();
500 last_var
= reg_file
[j
];
503 if (!found
|| k
> num_moves
)
505 if (k
== num_moves
&& n
< num_vars
)
507 if (!aligned
&& k
== num_moves
&& n
== num_vars
)
517 if (num_moves
== 0xFF) {
518 /* remove killed operands from reg_file once again */
519 for (unsigned i
= 0; !is_phi(instr
) && i
< instr
->operands
.size(); i
++) {
520 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].isFirstKill()) {
521 for (unsigned k
= 0; k
< instr
->operands
[i
].getTemp().size(); k
++)
522 reg_file
[instr
->operands
[i
].physReg() + k
] = 0;
525 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
526 Definition def
= instr
->definitions
[i
];
527 if (def
.isTemp() && def
.isFixed() && ctx
.defs_done
.test(i
)) {
528 for (unsigned k
= 0; k
< def
.getTemp().size(); k
++)
529 reg_file
[def
.physReg() + k
] = def
.tempId();
535 std::array
<uint32_t, 512> register_file
= reg_file
;
537 /* now, we figured the placement for our definition */
538 std::set
<std::pair
<unsigned, unsigned>> vars
;
539 for (unsigned j
= best_pos
; j
< best_pos
+ size
; j
++) {
540 if (reg_file
[j
] != 0xFFFFFFFF && reg_file
[j
] != 0)
541 vars
.emplace(ctx
.assignments
[reg_file
[j
]].second
.size(), reg_file
[j
]);
545 if (instr
->opcode
== aco_opcode::p_create_vector
) {
546 /* move killed operands which aren't yet at the correct position */
547 for (unsigned i
= 0, offset
= 0; i
< instr
->operands
.size(); offset
+= instr
->operands
[i
].size(), i
++) {
548 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].isFirstKill() &&
549 instr
->operands
[i
].getTemp().type() == rc
.type()) {
551 if (instr
->operands
[i
].physReg() != best_pos
+ offset
) {
552 vars
.emplace(instr
->operands
[i
].size(), instr
->operands
[i
].tempId());
553 for (unsigned j
= 0; j
< instr
->operands
[i
].size(); j
++)
554 reg_file
[instr
->operands
[i
].physReg() + j
] = 0;
556 for (unsigned j
= 0; j
< instr
->operands
[i
].size(); j
++)
557 reg_file
[instr
->operands
[i
].physReg() + j
] = instr
->operands
[i
].tempId();
562 /* re-enable the killed operands */
563 for (unsigned j
= 0; !is_phi(instr
) && j
< instr
->operands
.size(); j
++) {
564 if (instr
->operands
[j
].isTemp() && instr
->operands
[j
].isFirstKill()) {
565 for (unsigned k
= 0; k
< instr
->operands
[j
].getTemp().size(); k
++)
566 reg_file
[instr
->operands
[j
].physReg() + k
] = instr
->operands
[j
].tempId();
571 std::vector
<std::pair
<Operand
, Definition
>> pc
;
572 if (!get_regs_for_copies(ctx
, reg_file
, pc
, vars
, lb
, ub
, instr
, best_pos
, best_pos
+ size
- 1)) {
573 reg_file
= std::move(register_file
);
574 /* remove killed operands from reg_file once again */
575 if (!is_phi(instr
)) {
576 for (const Operand
& op
: instr
->operands
) {
577 if (op
.isTemp() && op
.isFirstKill()) {
578 for (unsigned k
= 0; k
< op
.getTemp().size(); k
++)
579 reg_file
[op
.physReg() + k
] = 0;
583 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
584 Definition
& def
= instr
->definitions
[i
];
585 if (def
.isTemp() && def
.isFixed() && ctx
.defs_done
.test(i
)) {
586 for (unsigned k
= 0; k
< def
.getTemp().size(); k
++)
587 reg_file
[def
.physReg() + k
] = def
.tempId();
593 parallelcopies
.insert(parallelcopies
.end(), pc
.begin(), pc
.end());
595 /* we set the definition regs == 0. the actual caller is responsible for correct setting */
596 for (unsigned i
= 0; i
< size
; i
++)
597 reg_file
[best_pos
+ i
] = 0;
599 update_renames(ctx
, reg_file
, parallelcopies
, instr
);
601 /* remove killed operands from reg_file once again */
602 for (unsigned i
= 0; !is_phi(instr
) && i
< instr
->operands
.size(); i
++) {
603 if (!instr
->operands
[i
].isTemp() || !instr
->operands
[i
].isFixed())
605 assert(!instr
->operands
[i
].isUndefined());
606 if (instr
->operands
[i
].isFirstKill()) {
607 for (unsigned j
= 0; j
< instr
->operands
[i
].getTemp().size(); j
++)
608 reg_file
[instr
->operands
[i
].physReg() + j
] = 0;
611 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
612 Definition def
= instr
->definitions
[i
];
613 if (def
.isTemp() && def
.isFixed() && ctx
.defs_done
.test(i
)) {
614 for (unsigned k
= 0; k
< def
.getTemp().size(); k
++)
615 reg_file
[def
.physReg() + k
] = def
.tempId();
619 adjust_max_used_regs(ctx
, rc
, best_pos
);
620 return {PhysReg
{best_pos
}, true};
623 PhysReg
get_reg(ra_ctx
& ctx
,
624 std::array
<uint32_t, 512>& reg_file
,
626 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
627 aco_ptr
<Instruction
>& instr
)
629 uint32_t size
= rc
.size();
632 if (rc
.type() == RegType::vgpr
) {
634 ub
= 256 + ctx
.program
->max_reg_demand
.vgpr
;
637 ub
= ctx
.program
->max_reg_demand
.sgpr
;
644 std::pair
<PhysReg
, bool> res
= {{}, false};
645 /* try to find space without live-range splits */
646 if (rc
.type() == RegType::vgpr
&& (size
== 4 || size
== 8))
647 res
= get_reg_simple(ctx
, reg_file
, lb
, ub
, size
, 4, rc
);
649 res
= get_reg_simple(ctx
, reg_file
, lb
, ub
, size
, stride
, rc
);
653 /* try to find space with live-range splits */
654 res
= get_reg_impl(ctx
, reg_file
, parallelcopies
, lb
, ub
, size
, stride
, rc
, instr
);
659 unsigned regs_free
= 0;
660 for (unsigned i
= lb
; i
< ub
; i
++) {
665 /* We should only fail here because keeping under the limit would require
667 assert(regs_free
>= size
);
669 /* try using more registers */
670 uint16_t max_addressible_sgpr
= ctx
.program
->sgpr_limit
;
671 uint16_t max_addressible_vgpr
= ctx
.program
->vgpr_limit
;
672 if (rc
.type() == RegType::vgpr
&& ctx
.program
->max_reg_demand
.vgpr
< max_addressible_vgpr
) {
673 update_vgpr_sgpr_demand(ctx
.program
, RegisterDemand(ctx
.program
->max_reg_demand
.vgpr
+ 1, ctx
.program
->max_reg_demand
.sgpr
));
674 return get_reg(ctx
, reg_file
, rc
, parallelcopies
, instr
);
675 } else if (rc
.type() == RegType::sgpr
&& ctx
.program
->max_reg_demand
.sgpr
< max_addressible_sgpr
) {
676 update_vgpr_sgpr_demand(ctx
.program
, RegisterDemand(ctx
.program
->max_reg_demand
.vgpr
, ctx
.program
->max_reg_demand
.sgpr
+ 1));
677 return get_reg(ctx
, reg_file
, rc
, parallelcopies
, instr
);
680 //FIXME: if nothing helps, shift-rotate the registers to make space
682 unreachable("did not find a register");
686 std::pair
<PhysReg
, bool> get_reg_vec(ra_ctx
& ctx
,
687 std::array
<uint32_t, 512>& reg_file
,
690 uint32_t size
= rc
.size();
693 if (rc
.type() == RegType::vgpr
) {
695 ub
= 256 + ctx
.program
->max_reg_demand
.vgpr
;
698 ub
= ctx
.program
->max_reg_demand
.sgpr
;
704 return get_reg_simple(ctx
, reg_file
, lb
, ub
, size
, stride
, rc
);
708 PhysReg
get_reg_create_vector(ra_ctx
& ctx
,
709 std::array
<uint32_t, 512>& reg_file
,
711 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
712 aco_ptr
<Instruction
>& instr
)
714 /* create_vector instructions have different costs w.r.t. register coalescing */
715 uint32_t size
= rc
.size();
718 if (rc
.type() == RegType::vgpr
) {
720 ub
= 256 + ctx
.program
->max_reg_demand
.vgpr
;
723 ub
= ctx
.program
->max_reg_demand
.sgpr
;
730 unsigned best_pos
= -1;
731 unsigned num_moves
= 0xFF;
732 bool best_war_hint
= true;
734 /* test for each operand which definition placement causes the least shuffle instructions */
735 for (unsigned i
= 0, offset
= 0; i
< instr
->operands
.size(); offset
+= instr
->operands
[i
].size(), i
++) {
736 // TODO: think about, if we can alias live operands on the same register
737 if (!instr
->operands
[i
].isTemp() || !instr
->operands
[i
].isKill() || instr
->operands
[i
].getTemp().type() != rc
.type())
740 if (offset
> instr
->operands
[i
].physReg())
743 unsigned reg_lo
= instr
->operands
[i
].physReg() - offset
;
744 unsigned reg_hi
= reg_lo
+ size
- 1;
747 /* no need to check multiple times */
748 if (reg_lo
== best_pos
)
752 // TODO: this can be improved */
753 if (reg_lo
< lb
|| reg_hi
>= ub
|| reg_lo
% stride
!= 0)
755 if (reg_lo
> lb
&& reg_file
[reg_lo
] != 0 && reg_file
[reg_lo
] == reg_file
[reg_lo
- 1])
757 if (reg_hi
< ub
- 1 && reg_file
[reg_hi
] != 0 && reg_file
[reg_hi
] == reg_file
[reg_hi
+ 1])
760 /* count variables to be moved and check war_hint */
761 bool war_hint
= false;
762 bool linear_vgpr
= false;
763 for (unsigned j
= reg_lo
; j
<= reg_hi
&& !linear_vgpr
; j
++) {
764 if (reg_file
[j
] != 0) {
766 /* we cannot split live ranges of linear vgprs */
767 if (ctx
.assignments
[reg_file
[j
]].second
& (1 << 6))
770 war_hint
|= ctx
.war_hint
[j
];
772 if (linear_vgpr
|| (war_hint
&& !best_war_hint
))
775 /* count operands in wrong positions */
776 for (unsigned j
= 0, offset
= 0; j
< instr
->operands
.size(); offset
+= instr
->operands
[j
].size(), j
++) {
778 !instr
->operands
[j
].isTemp() ||
779 instr
->operands
[j
].getTemp().type() != rc
.type())
781 if (instr
->operands
[j
].physReg() != reg_lo
+ offset
)
782 k
+= instr
->operands
[j
].size();
784 bool aligned
= rc
== RegClass::v4
&& reg_lo
% 4 == 0;
785 if (k
> num_moves
|| (!aligned
&& k
== num_moves
))
790 best_war_hint
= war_hint
;
793 if (num_moves
>= size
)
794 return get_reg(ctx
, reg_file
, rc
, parallelcopies
, instr
);
796 /* collect variables to be moved */
797 std::set
<std::pair
<unsigned, unsigned>> vars
;
798 for (unsigned i
= best_pos
; i
< best_pos
+ size
; i
++) {
799 if (reg_file
[i
] != 0)
800 vars
.emplace(ctx
.assignments
[reg_file
[i
]].second
.size(), reg_file
[i
]);
804 /* move killed operands which aren't yet at the correct position */
805 for (unsigned i
= 0, offset
= 0; i
< instr
->operands
.size(); offset
+= instr
->operands
[i
].size(), i
++) {
806 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].isFirstKill() && instr
->operands
[i
].getTemp().type() == rc
.type()) {
807 if (instr
->operands
[i
].physReg() != best_pos
+ offset
) {
808 vars
.emplace(instr
->operands
[i
].size(), instr
->operands
[i
].tempId());
810 for (unsigned j
= 0; j
< instr
->operands
[i
].size(); j
++)
811 reg_file
[instr
->operands
[i
].physReg() + j
] = instr
->operands
[i
].tempId();
816 ASSERTED
bool success
= false;
817 success
= get_regs_for_copies(ctx
, reg_file
, parallelcopies
, vars
, lb
, ub
, instr
, best_pos
, best_pos
+ size
- 1);
820 update_renames(ctx
, reg_file
, parallelcopies
, instr
);
821 adjust_max_used_regs(ctx
, rc
, best_pos
);
822 return PhysReg
{best_pos
};
825 bool get_reg_specified(ra_ctx
& ctx
,
826 std::array
<uint32_t, 512>& reg_file
,
828 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
829 aco_ptr
<Instruction
>& instr
,
832 uint32_t size
= rc
.size();
836 if (rc
.type() == RegType::vgpr
) {
838 ub
= 256 + ctx
.program
->max_reg_demand
.vgpr
;
844 if (reg
% stride
!= 0)
847 ub
= ctx
.program
->max_reg_demand
.sgpr
;
850 uint32_t reg_lo
= reg
.reg
;
851 uint32_t reg_hi
= reg
+ (size
- 1);
853 if (reg_lo
< lb
|| reg_hi
>= ub
|| reg_lo
> reg_hi
)
856 for (unsigned i
= reg_lo
; i
<= reg_hi
; i
++) {
857 if (reg_file
[i
] != 0)
860 adjust_max_used_regs(ctx
, rc
, reg_lo
);
864 void handle_pseudo(ra_ctx
& ctx
,
865 const std::array
<uint32_t, 512>& reg_file
,
868 if (instr
->format
!= Format::PSEUDO
)
871 /* all instructions which use handle_operands() need this information */
872 switch (instr
->opcode
) {
873 case aco_opcode::p_extract_vector
:
874 case aco_opcode::p_create_vector
:
875 case aco_opcode::p_split_vector
:
876 case aco_opcode::p_parallelcopy
:
877 case aco_opcode::p_wqm
:
883 /* if all definitions are vgpr, no need to care for SCC */
884 bool writes_sgpr
= false;
885 for (Definition
& def
: instr
->definitions
) {
886 if (def
.getTemp().type() == RegType::sgpr
) {
891 /* if all operands are constant, no need to care either */
892 bool reads_sgpr
= false;
893 for (Operand
& op
: instr
->operands
) {
894 if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
899 if (!(writes_sgpr
&& reads_sgpr
))
902 Pseudo_instruction
*pi
= (Pseudo_instruction
*)instr
;
903 if (reg_file
[scc
.reg
]) {
904 pi
->tmp_in_scc
= true;
906 int reg
= ctx
.max_used_sgpr
;
907 for (; reg
>= 0 && reg_file
[reg
]; reg
--)
910 reg
= ctx
.max_used_sgpr
+ 1;
911 for (; reg
< ctx
.program
->max_reg_demand
.sgpr
&& reg_file
[reg
]; reg
++)
913 assert(reg
< ctx
.program
->max_reg_demand
.sgpr
);
916 adjust_max_used_regs(ctx
, s1
, reg
);
917 pi
->scratch_sgpr
= PhysReg
{(unsigned)reg
};
919 pi
->tmp_in_scc
= false;
923 bool operand_can_use_reg(aco_ptr
<Instruction
>& instr
, unsigned idx
, PhysReg reg
)
925 switch (instr
->format
) {
929 (reg
!= m0
|| idx
== 1 || idx
== 3) && /* offset can be m0 */
930 (reg
!= vcc
|| (instr
->definitions
.empty() && idx
== 2)); /* sdata can be vcc */
932 // TODO: there are more instructions with restrictions on registers
937 } /* end namespace */
940 void register_allocation(Program
*program
, std::vector
<std::set
<Temp
>> live_out_per_block
)
944 std::vector
<std::unordered_map
<unsigned, Temp
>> renames(program
->blocks
.size());
949 std::set
<Instruction
*> uses
;
952 bool filled
[program
->blocks
.size()];
953 bool sealed
[program
->blocks
.size()];
954 memset(filled
, 0, sizeof filled
);
955 memset(sealed
, 0, sizeof sealed
);
956 std::vector
<std::vector
<Instruction
*>> incomplete_phis(program
->blocks
.size());
957 std::map
<unsigned, phi_info
> phi_map
;
958 std::map
<unsigned, unsigned> affinities
;
959 std::function
<Temp(Temp
,unsigned)> read_variable
;
960 std::function
<Temp(Temp
,Block
*)> handle_live_in
;
961 std::function
<Temp(std::map
<unsigned, phi_info
>::iterator
)> try_remove_trivial_phi
;
963 read_variable
= [&](Temp val
, unsigned block_idx
) -> Temp
{
964 std::unordered_map
<unsigned, Temp
>::iterator it
= renames
[block_idx
].find(val
.id());
965 assert(it
!= renames
[block_idx
].end());
969 handle_live_in
= [&](Temp val
, Block
*block
) -> Temp
{
970 std::vector
<unsigned>& preds
= val
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
971 if (preds
.size() == 0 || val
.regClass() == val
.regClass().as_linear()) {
972 renames
[block
->index
][val
.id()] = val
;
975 assert(preds
.size() > 0);
978 if (!sealed
[block
->index
]) {
979 /* consider rename from already processed predecessor */
980 Temp tmp
= read_variable(val
, preds
[0]);
982 /* if the block is not sealed yet, we create an incomplete phi (which might later get removed again) */
983 new_val
= Temp
{program
->allocateId(), val
.regClass()};
984 aco_opcode opcode
= val
.is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
985 aco_ptr
<Instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
986 phi
->definitions
[0] = Definition(new_val
);
987 for (unsigned i
= 0; i
< preds
.size(); i
++)
988 phi
->operands
[i
] = Operand(val
);
989 if (tmp
.regClass() == new_val
.regClass())
990 affinities
[new_val
.id()] = tmp
.id();
992 phi_map
.emplace(new_val
.id(), phi_info
{phi
.get(), block
->index
});
993 incomplete_phis
[block
->index
].emplace_back(phi
.get());
994 block
->instructions
.insert(block
->instructions
.begin(), std::move(phi
));
996 } else if (preds
.size() == 1) {
997 /* if the block has only one predecessor, just look there for the name */
998 new_val
= read_variable(val
, preds
[0]);
1000 /* there are multiple predecessors and the block is sealed */
1001 Temp ops
[preds
.size()];
1003 /* we start assuming that the name is the same from all predecessors */
1004 renames
[block
->index
][val
.id()] = val
;
1005 bool needs_phi
= false;
1007 /* get the rename from each predecessor and check if they are the same */
1008 for (unsigned i
= 0; i
< preds
.size(); i
++) {
1009 ops
[i
] = read_variable(val
, preds
[i
]);
1013 needs_phi
|= !(new_val
== ops
[i
]);
1017 /* the variable has been renamed differently in the predecessors: we need to insert a phi */
1018 aco_opcode opcode
= val
.is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
1019 aco_ptr
<Instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
1020 new_val
= Temp
{program
->allocateId(), val
.regClass()};
1021 phi
->definitions
[0] = Definition(new_val
);
1022 for (unsigned i
= 0; i
< preds
.size(); i
++) {
1023 phi
->operands
[i
] = Operand(ops
[i
]);
1024 phi
->operands
[i
].setFixed(ctx
.assignments
[ops
[i
].id()].first
);
1025 if (ops
[i
].regClass() == new_val
.regClass())
1026 affinities
[new_val
.id()] = ops
[i
].id();
1028 phi_map
.emplace(new_val
.id(), phi_info
{phi
.get(), block
->index
});
1029 block
->instructions
.insert(block
->instructions
.begin(), std::move(phi
));
1033 renames
[block
->index
][val
.id()] = new_val
;
1034 renames
[block
->index
][new_val
.id()] = new_val
;
1035 ctx
.orig_names
[new_val
.id()] = val
;
1039 try_remove_trivial_phi
= [&] (std::map
<unsigned, phi_info
>::iterator info
) -> Temp
{
1040 assert(info
->second
.block_idx
!= 0);
1041 Instruction
* phi
= info
->second
.phi
;
1044 Definition def
= phi
->definitions
[0];
1045 /* a phi node is trivial if all operands are the same as the definition of the phi */
1046 for (const Operand
& op
: phi
->operands
) {
1047 const Temp t
= op
.getTemp();
1048 if (t
== same
|| t
== def
.getTemp())
1050 if (!(same
== Temp()) || !(op
.physReg() == def
.physReg())) {
1051 /* phi is not trivial */
1052 return def
.getTemp();
1056 assert(!(same
== Temp() || same
== def
.getTemp()));
1058 /* reroute all uses to same and remove phi */
1059 std::vector
<std::map
<unsigned, phi_info
>::iterator
> phi_users
;
1060 std::map
<unsigned, phi_info
>::iterator same_phi_info
= phi_map
.find(same
.id());
1061 for (Instruction
* instr
: info
->second
.uses
) {
1062 assert(phi
!= instr
);
1063 /* recursively try to remove trivial phis */
1064 if (is_phi(instr
)) {
1065 /* ignore if the phi was already flagged trivial */
1066 if (instr
->definitions
.empty())
1069 std::map
<unsigned, phi_info
>::iterator it
= phi_map
.find(instr
->definitions
[0].tempId());
1070 if (it
!= phi_map
.end() && it
!= info
)
1071 phi_users
.emplace_back(it
);
1073 for (Operand
& op
: instr
->operands
) {
1074 if (op
.isTemp() && op
.tempId() == def
.tempId()) {
1076 if (same_phi_info
!= phi_map
.end())
1077 same_phi_info
->second
.uses
.emplace(instr
);
1082 auto it
= ctx
.orig_names
.find(same
.id());
1083 unsigned orig_var
= it
!= ctx
.orig_names
.end() ? it
->second
.id() : same
.id();
1084 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++) {
1085 auto it
= renames
[i
].find(orig_var
);
1086 if (it
!= renames
[i
].end() && it
->second
== def
.getTemp())
1087 renames
[i
][orig_var
] = same
;
1090 unsigned block_idx
= info
->second
.block_idx
;
1091 phi
->definitions
.clear(); /* this indicates that the phi can be removed */
1092 phi_map
.erase(info
);
1093 for (auto it
: phi_users
) {
1094 if (sealed
[it
->second
.block_idx
])
1095 try_remove_trivial_phi(it
);
1098 /* due to the removal of other phis, the name might have changed once again! */
1099 return renames
[block_idx
][orig_var
];
1102 std::map
<unsigned, Instruction
*> vectors
;
1103 std::vector
<std::vector
<Temp
>> phi_ressources
;
1104 std::map
<unsigned, unsigned> temp_to_phi_ressources
;
1106 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); it
++) {
1109 /* first, compute the death points of all live vars within the block */
1110 std::set
<Temp
>& live
= live_out_per_block
[block
.index
];
1112 std::vector
<aco_ptr
<Instruction
>>::reverse_iterator rit
;
1113 for (rit
= block
.instructions
.rbegin(); rit
!= block
.instructions
.rend(); ++rit
) {
1114 aco_ptr
<Instruction
>& instr
= *rit
;
1115 if (!is_phi(instr
)) {
1116 for (const Operand
& op
: instr
->operands
) {
1118 live
.emplace(op
.getTemp());
1120 if (instr
->opcode
== aco_opcode::p_create_vector
) {
1121 for (const Operand
& op
: instr
->operands
) {
1122 if (op
.isTemp() && op
.getTemp().type() == instr
->definitions
[0].getTemp().type())
1123 vectors
[op
.tempId()] = instr
.get();
1126 } else if (!instr
->definitions
[0].isKill() && !instr
->definitions
[0].isFixed()) {
1127 /* collect information about affinity-related temporaries */
1128 std::vector
<Temp
> affinity_related
;
1129 /* affinity_related[0] is the last seen affinity-related temp */
1130 affinity_related
.emplace_back(instr
->definitions
[0].getTemp());
1131 affinity_related
.emplace_back(instr
->definitions
[0].getTemp());
1132 for (const Operand
& op
: instr
->operands
) {
1133 if (op
.isTemp() && op
.regClass() == instr
->definitions
[0].regClass()) {
1134 affinity_related
.emplace_back(op
.getTemp());
1135 temp_to_phi_ressources
[op
.tempId()] = phi_ressources
.size();
1138 phi_ressources
.emplace_back(std::move(affinity_related
));
1141 /* erase from live */
1142 for (const Definition
& def
: instr
->definitions
) {
1144 live
.erase(def
.getTemp());
1145 std::map
<unsigned, unsigned>::iterator it
= temp_to_phi_ressources
.find(def
.tempId());
1146 if (it
!= temp_to_phi_ressources
.end() && def
.regClass() == phi_ressources
[it
->second
][0].regClass())
1147 phi_ressources
[it
->second
][0] = def
.getTemp();
1152 /* create affinities */
1153 for (std::vector
<Temp
>& vec
: phi_ressources
) {
1154 assert(vec
.size() > 1);
1155 for (unsigned i
= 1; i
< vec
.size(); i
++)
1156 if (vec
[i
].id() != vec
[0].id())
1157 affinities
[vec
[i
].id()] = vec
[0].id();
1160 /* state of register file after phis */
1161 std::vector
<std::bitset
<128>> sgpr_live_in(program
->blocks
.size());
1163 for (Block
& block
: program
->blocks
) {
1164 std::set
<Temp
>& live
= live_out_per_block
[block
.index
];
1165 /* initialize register file */
1166 assert(block
.index
!= 0 || live
.empty());
1167 std::array
<uint32_t, 512> register_file
= {0};
1168 ctx
.war_hint
.reset();
1170 for (Temp t
: live
) {
1171 Temp renamed
= handle_live_in(t
, &block
);
1172 if (ctx
.assignments
.find(renamed
.id()) != ctx
.assignments
.end()) {
1173 for (unsigned i
= 0; i
< t
.size(); i
++)
1174 register_file
[ctx
.assignments
[renamed
.id()].first
+ i
] = renamed
.id();
1178 std::vector
<aco_ptr
<Instruction
>> instructions
;
1179 std::vector
<aco_ptr
<Instruction
>>::iterator it
;
1181 /* this is a slight adjustment from the paper as we already have phi nodes:
1182 * We consider them incomplete phis and only handle the definition. */
1184 /* handle fixed phi definitions */
1185 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1186 aco_ptr
<Instruction
>& phi
= *it
;
1189 Definition
& definition
= phi
->definitions
[0];
1190 if (!definition
.isFixed())
1193 /* check if a dead exec mask phi is needed */
1194 if (definition
.isKill()) {
1195 for (Operand
& op
: phi
->operands
) {
1196 assert(op
.isTemp());
1197 if (ctx
.assignments
.find(op
.tempId()) == ctx
.assignments
.end() ||
1198 ctx
.assignments
[op
.tempId()].first
!= exec
) {
1199 definition
.setKill(false);
1205 if (definition
.isKill())
1208 assert(definition
.physReg() == exec
);
1209 for (unsigned i
= 0; i
< definition
.size(); i
++) {
1210 assert(register_file
[definition
.physReg() + i
] == 0);
1211 register_file
[definition
.physReg() + i
] = definition
.tempId();
1213 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1216 /* look up the affinities */
1217 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1218 aco_ptr
<Instruction
>& phi
= *it
;
1221 Definition
& definition
= phi
->definitions
[0];
1222 if (definition
.isKill() || definition
.isFixed())
1225 if (affinities
.find(definition
.tempId()) != affinities
.end() &&
1226 ctx
.assignments
.find(affinities
[definition
.tempId()]) != ctx
.assignments
.end()) {
1227 assert(ctx
.assignments
[affinities
[definition
.tempId()]].second
== definition
.regClass());
1228 PhysReg reg
= ctx
.assignments
[affinities
[definition
.tempId()]].first
;
1229 bool try_use_special_reg
= reg
== scc
|| reg
== exec
;
1230 if (try_use_special_reg
) {
1231 for (const Operand
& op
: phi
->operands
) {
1233 ctx
.assignments
.find(op
.tempId()) == ctx
.assignments
.end() ||
1234 !(ctx
.assignments
[op
.tempId()].first
== reg
)) {
1235 try_use_special_reg
= false;
1239 if (!try_use_special_reg
)
1242 bool reg_free
= true;
1243 for (unsigned i
= reg
.reg
; reg_free
&& i
< reg
+ definition
.size(); i
++) {
1244 if (register_file
[i
] != 0)
1247 /* only assign if register is still free */
1249 definition
.setFixed(reg
);
1250 for (unsigned i
= 0; i
< definition
.size(); i
++)
1251 register_file
[definition
.physReg() + i
] = definition
.tempId();
1252 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1257 /* find registers for phis without affinity or where the register was blocked */
1258 for (it
= block
.instructions
.begin();it
!= block
.instructions
.end(); ++it
) {
1259 aco_ptr
<Instruction
>& phi
= *it
;
1263 Definition
& definition
= phi
->definitions
[0];
1264 if (definition
.isKill())
1267 renames
[block
.index
][definition
.tempId()] = definition
.getTemp();
1269 if (!definition
.isFixed()) {
1270 std::vector
<std::pair
<Operand
, Definition
>> parallelcopy
;
1271 /* try to find a register that is used by at least one operand */
1272 for (const Operand
& op
: phi
->operands
) {
1274 ctx
.assignments
.find(op
.tempId()) == ctx
.assignments
.end())
1276 PhysReg reg
= ctx
.assignments
[op
.tempId()].first
;
1277 /* we tried this already on the previous loop */
1278 if (reg
== scc
|| reg
== exec
)
1280 if (get_reg_specified(ctx
, register_file
, definition
.regClass(), parallelcopy
, phi
, reg
)) {
1281 definition
.setFixed(reg
);
1285 if (!definition
.isFixed())
1286 definition
.setFixed(get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, phi
));
1288 /* process parallelcopy */
1289 for (std::pair
<Operand
, Definition
> pc
: parallelcopy
) {
1290 /* see if it's a copy from a different phi */
1291 //TODO: prefer moving some previous phis over live-ins
1292 //TODO: somehow prevent phis fixed before the RA from being updated (shouldn't be a problem in practice since they can only be fixed to exec)
1293 Instruction
*prev_phi
= NULL
;
1294 std::vector
<aco_ptr
<Instruction
>>::iterator phi_it
;
1295 for (phi_it
= instructions
.begin(); phi_it
!= instructions
.end(); ++phi_it
) {
1296 if ((*phi_it
)->definitions
[0].tempId() == pc
.first
.tempId())
1297 prev_phi
= phi_it
->get();
1300 while (!prev_phi
&& is_phi(*++phi_it
)) {
1301 if ((*phi_it
)->definitions
[0].tempId() == pc
.first
.tempId())
1302 prev_phi
= phi_it
->get();
1305 /* if so, just update that phi's register */
1306 prev_phi
->definitions
[0].setFixed(pc
.second
.physReg());
1307 ctx
.assignments
[prev_phi
->definitions
[0].tempId()] = {pc
.second
.physReg(), pc
.second
.regClass()};
1308 for (unsigned reg
= pc
.second
.physReg(); reg
< pc
.second
.physReg() + pc
.second
.size(); reg
++)
1309 register_file
[reg
] = prev_phi
->definitions
[0].tempId();
1314 std::map
<unsigned, Temp
>::iterator orig_it
= ctx
.orig_names
.find(pc
.first
.tempId());
1315 Temp orig
= pc
.first
.getTemp();
1316 if (orig_it
!= ctx
.orig_names
.end())
1317 orig
= orig_it
->second
;
1319 ctx
.orig_names
[pc
.second
.tempId()] = orig
;
1320 renames
[block
.index
][orig
.id()] = pc
.second
.getTemp();
1321 renames
[block
.index
][pc
.second
.tempId()] = pc
.second
.getTemp();
1323 /* otherwise, this is a live-in and we need to create a new phi
1324 * to move it in this block's predecessors */
1325 aco_opcode opcode
= pc
.first
.getTemp().is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
1326 std::vector
<unsigned>& preds
= pc
.first
.getTemp().is_linear() ? block
.linear_preds
: block
.logical_preds
;
1327 aco_ptr
<Instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
1328 new_phi
->definitions
[0] = pc
.second
;
1329 for (unsigned i
= 0; i
< preds
.size(); i
++)
1330 new_phi
->operands
[i
] = Operand(pc
.first
);
1331 instructions
.emplace_back(std::move(new_phi
));
1334 for (unsigned i
= 0; i
< definition
.size(); i
++)
1335 register_file
[definition
.physReg() + i
] = definition
.tempId();
1336 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1338 live
.emplace(definition
.getTemp());
1340 /* update phi affinities */
1341 for (const Operand
& op
: phi
->operands
) {
1342 if (op
.isTemp() && op
.regClass() == phi
->definitions
[0].regClass())
1343 affinities
[op
.tempId()] = definition
.tempId();
1346 instructions
.emplace_back(std::move(*it
));
1349 /* fill in sgpr_live_in */
1350 for (unsigned i
= 0; i
< ctx
.max_used_sgpr
; i
++)
1351 sgpr_live_in
[block
.index
][i
] = register_file
[i
];
1352 sgpr_live_in
[block
.index
][127] = register_file
[scc
.reg
];
1354 /* Handle all other instructions of the block */
1355 for (; it
!= block
.instructions
.end(); ++it
) {
1356 aco_ptr
<Instruction
>& instr
= *it
;
1358 /* parallelcopies from p_phi are inserted here which means
1359 * live ranges of killed operands end here as well */
1360 if (instr
->opcode
== aco_opcode::p_logical_end
) {
1361 /* no need to process this instruction any further */
1362 if (block
.logical_succs
.size() != 1) {
1363 instructions
.emplace_back(std::move(instr
));
1367 Block
& succ
= program
->blocks
[block
.logical_succs
[0]];
1369 for (; idx
< succ
.logical_preds
.size(); idx
++) {
1370 if (succ
.logical_preds
[idx
] == block
.index
)
1373 for (aco_ptr
<Instruction
>& phi
: succ
.instructions
) {
1374 if (phi
->opcode
== aco_opcode::p_phi
) {
1375 if (phi
->operands
[idx
].isTemp() &&
1376 phi
->operands
[idx
].getTemp().type() == RegType::sgpr
&&
1377 phi
->operands
[idx
].isFirstKill()) {
1378 Temp phi_op
= read_variable(phi
->operands
[idx
].getTemp(), block
.index
);
1379 PhysReg reg
= ctx
.assignments
[phi_op
.id()].first
;
1380 assert(register_file
[reg
] == phi_op
.id());
1381 register_file
[reg
] = 0;
1383 } else if (phi
->opcode
!= aco_opcode::p_linear_phi
) {
1387 instructions
.emplace_back(std::move(instr
));
1391 std::vector
<std::pair
<Operand
, Definition
>> parallelcopy
;
1393 assert(!is_phi(instr
));
1395 /* handle operands */
1396 for (unsigned i
= 0; i
< instr
->operands
.size(); ++i
) {
1397 auto& operand
= instr
->operands
[i
];
1398 if (!operand
.isTemp())
1401 /* rename operands */
1402 operand
.setTemp(read_variable(operand
.getTemp(), block
.index
));
1404 /* check if the operand is fixed */
1405 if (operand
.isFixed()) {
1407 if (operand
.physReg() == ctx
.assignments
[operand
.tempId()].first
) {
1408 /* we are fine: the operand is already assigned the correct reg */
1411 /* check if target reg is blocked, and move away the blocking var */
1412 if (register_file
[operand
.physReg().reg
]) {
1413 uint32_t blocking_id
= register_file
[operand
.physReg().reg
];
1414 RegClass rc
= ctx
.assignments
[blocking_id
].second
;
1415 Operand pc_op
= Operand(Temp
{blocking_id
, rc
});
1416 pc_op
.setFixed(operand
.physReg());
1417 Definition pc_def
= Definition(Temp
{program
->allocateId(), pc_op
.regClass()});
1419 PhysReg reg
= get_reg(ctx
, register_file
, pc_op
.regClass(), parallelcopy
, instr
);
1420 pc_def
.setFixed(reg
);
1421 ctx
.assignments
[pc_def
.tempId()] = {reg
, pc_def
.regClass()};
1422 for (unsigned i
= 0; i
< operand
.size(); i
++) {
1423 register_file
[pc_op
.physReg() + i
] = 0;
1424 register_file
[pc_def
.physReg() + i
] = pc_def
.tempId();
1426 parallelcopy
.emplace_back(pc_op
, pc_def
);
1428 /* handle renames of previous operands */
1429 for (unsigned j
= 0; j
< i
; j
++) {
1430 Operand
& op
= instr
->operands
[j
];
1431 if (op
.isTemp() && op
.tempId() == blocking_id
) {
1432 op
.setTemp(pc_def
.getTemp());
1437 /* move operand to fixed reg and create parallelcopy pair */
1438 Operand pc_op
= operand
;
1439 Temp tmp
= Temp
{program
->allocateId(), operand
.regClass()};
1440 Definition pc_def
= Definition(tmp
);
1441 pc_def
.setFixed(operand
.physReg());
1442 pc_op
.setFixed(ctx
.assignments
[operand
.tempId()].first
);
1443 operand
.setTemp(tmp
);
1444 ctx
.assignments
[tmp
.id()] = {pc_def
.physReg(), pc_def
.regClass()};
1445 operand
.setFixed(pc_def
.physReg());
1446 for (unsigned i
= 0; i
< operand
.size(); i
++) {
1447 register_file
[pc_op
.physReg() + i
] = 0;
1448 register_file
[pc_def
.physReg() + i
] = tmp
.id();
1450 parallelcopy
.emplace_back(pc_op
, pc_def
);
1453 assert(ctx
.assignments
.find(operand
.tempId()) != ctx
.assignments
.end());
1454 PhysReg reg
= ctx
.assignments
[operand
.tempId()].first
;
1456 if (operand_can_use_reg(instr
, i
, reg
)) {
1457 operand
.setFixed(ctx
.assignments
[operand
.tempId()].first
);
1459 Operand pc_op
= operand
;
1460 pc_op
.setFixed(reg
);
1461 PhysReg new_reg
= get_reg(ctx
, register_file
, operand
.regClass(), parallelcopy
, instr
);
1462 Definition pc_def
= Definition(program
->allocateId(), new_reg
, pc_op
.regClass());
1463 ctx
.assignments
[pc_def
.tempId()] = {reg
, pc_def
.regClass()};
1464 for (unsigned i
= 0; i
< operand
.size(); i
++) {
1465 register_file
[pc_op
.physReg() + i
] = 0;
1466 register_file
[pc_def
.physReg() + i
] = pc_def
.tempId();
1468 parallelcopy
.emplace_back(pc_op
, pc_def
);
1469 operand
.setFixed(new_reg
);
1472 if (instr
->format
== Format::EXP
||
1473 (instr
->isVMEM() && i
== 3 && program
->chip_class
== GFX6
) ||
1474 (instr
->format
== Format::DS
&& static_cast<DS_instruction
*>(instr
.get())->gds
)) {
1475 for (unsigned j
= 0; j
< operand
.size(); j
++)
1476 ctx
.war_hint
.set(operand
.physReg().reg
+ j
);
1479 std::map
<unsigned, phi_info
>::iterator phi
= phi_map
.find(operand
.getTemp().id());
1480 if (phi
!= phi_map
.end())
1481 phi
->second
.uses
.emplace(instr
.get());
1484 /* remove dead vars from register file */
1485 for (const Operand
& op
: instr
->operands
) {
1486 if (op
.isTemp() && op
.isFirstKill())
1487 for (unsigned j
= 0; j
< op
.size(); j
++)
1488 register_file
[op
.physReg() + j
] = 0;
1491 /* try to optimize v_mad_f32 -> v_mac_f32 */
1492 if (instr
->opcode
== aco_opcode::v_mad_f32
&&
1493 instr
->operands
[2].isTemp() &&
1494 instr
->operands
[2].isKill() &&
1495 instr
->operands
[2].getTemp().type() == RegType::vgpr
&&
1496 instr
->operands
[1].isTemp() &&
1497 instr
->operands
[1].getTemp().type() == RegType::vgpr
) { /* TODO: swap src0 and src1 in this case */
1498 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1499 bool can_use_mac
= !(vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1500 vop3
->opsel
[0] || vop3
->opsel
[1] || vop3
->opsel
[2] ||
1501 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1502 vop3
->clamp
|| vop3
->omod
);
1504 instr
->format
= Format::VOP2
;
1505 instr
->opcode
= aco_opcode::v_mac_f32
;
1509 /* handle definitions which must have the same register as an operand */
1510 if (instr
->opcode
== aco_opcode::v_interp_p2_f32
||
1511 instr
->opcode
== aco_opcode::v_mac_f32
||
1512 instr
->opcode
== aco_opcode::v_writelane_b32
||
1513 instr
->opcode
== aco_opcode::v_writelane_b32_e64
) {
1514 instr
->definitions
[0].setFixed(instr
->operands
[2].physReg());
1515 } else if (instr
->opcode
== aco_opcode::s_addk_i32
||
1516 instr
->opcode
== aco_opcode::s_mulk_i32
) {
1517 instr
->definitions
[0].setFixed(instr
->operands
[0].physReg());
1518 } else if ((instr
->format
== Format::MUBUF
||
1519 instr
->format
== Format::MIMG
) &&
1520 instr
->definitions
.size() == 1 &&
1521 instr
->operands
.size() == 4) {
1522 instr
->definitions
[0].setFixed(instr
->operands
[3].physReg());
1525 ctx
.defs_done
.reset();
1527 /* handle fixed definitions first */
1528 for (unsigned i
= 0; i
< instr
->definitions
.size(); ++i
) {
1529 auto& definition
= instr
->definitions
[i
];
1530 if (!definition
.isFixed())
1533 adjust_max_used_regs(ctx
, definition
.regClass(), definition
.physReg());
1534 /* check if the target register is blocked */
1535 if (register_file
[definition
.physReg().reg
] != 0) {
1536 /* create parallelcopy pair to move blocking var */
1537 Temp tmp
= {register_file
[definition
.physReg()], ctx
.assignments
[register_file
[definition
.physReg()]].second
};
1538 Operand pc_op
= Operand(tmp
);
1539 pc_op
.setFixed(ctx
.assignments
[register_file
[definition
.physReg().reg
]].first
);
1540 RegClass rc
= pc_op
.regClass();
1541 tmp
= Temp
{program
->allocateId(), rc
};
1542 Definition pc_def
= Definition(tmp
);
1544 /* re-enable the killed operands, so that we don't move the blocking var there */
1545 for (const Operand
& op
: instr
->operands
) {
1546 if (op
.isTemp() && op
.isFirstKill())
1547 for (unsigned j
= 0; j
< op
.size(); j
++)
1548 register_file
[op
.physReg() + j
] = 0xFFFF;
1551 /* find a new register for the blocking variable */
1552 PhysReg reg
= get_reg(ctx
, register_file
, rc
, parallelcopy
, instr
);
1553 /* once again, disable killed operands */
1554 for (const Operand
& op
: instr
->operands
) {
1555 if (op
.isTemp() && op
.isFirstKill())
1556 for (unsigned j
= 0; j
< op
.size(); j
++)
1557 register_file
[op
.physReg() + j
] = 0;
1559 for (unsigned k
= 0; k
< i
; k
++) {
1560 if (instr
->definitions
[k
].isTemp() && ctx
.defs_done
.test(k
) && !instr
->definitions
[k
].isKill())
1561 for (unsigned j
= 0; j
< instr
->definitions
[k
].size(); j
++)
1562 register_file
[instr
->definitions
[k
].physReg() + j
] = instr
->definitions
[k
].tempId();
1564 pc_def
.setFixed(reg
);
1566 /* finish assignment of parallelcopy */
1567 ctx
.assignments
[pc_def
.tempId()] = {reg
, pc_def
.regClass()};
1568 parallelcopy
.emplace_back(pc_op
, pc_def
);
1570 /* add changes to reg_file */
1571 for (unsigned i
= 0; i
< pc_op
.size(); i
++) {
1572 register_file
[pc_op
.physReg() + i
] = 0x0;
1573 register_file
[pc_def
.physReg() + i
] = pc_def
.tempId();
1576 ctx
.defs_done
.set(i
);
1578 if (!definition
.isTemp())
1581 /* set live if it has a kill point */
1582 if (!definition
.isKill())
1583 live
.emplace(definition
.getTemp());
1585 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1586 renames
[block
.index
][definition
.tempId()] = definition
.getTemp();
1587 for (unsigned j
= 0; j
< definition
.size(); j
++)
1588 register_file
[definition
.physReg() + j
] = definition
.tempId();
1591 /* handle all other definitions */
1592 for (unsigned i
= 0; i
< instr
->definitions
.size(); ++i
) {
1593 auto& definition
= instr
->definitions
[i
];
1595 if (definition
.isFixed() || !definition
.isTemp())
1599 if (definition
.hasHint() && register_file
[definition
.physReg().reg
] == 0)
1600 definition
.setFixed(definition
.physReg());
1601 else if (instr
->opcode
== aco_opcode::p_split_vector
) {
1602 PhysReg reg
= PhysReg
{instr
->operands
[0].physReg() + i
* definition
.size()};
1603 if (!get_reg_specified(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
, reg
))
1604 reg
= get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
);
1605 definition
.setFixed(reg
);
1606 } else if (instr
->opcode
== aco_opcode::p_wqm
) {
1608 if (instr
->operands
[0].isKill() && instr
->operands
[0].getTemp().type() == definition
.getTemp().type()) {
1609 reg
= instr
->operands
[0].physReg();
1610 assert(register_file
[reg
.reg
] == 0);
1612 reg
= get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
);
1614 definition
.setFixed(reg
);
1615 } else if (instr
->opcode
== aco_opcode::p_extract_vector
) {
1617 if (instr
->operands
[0].isKill() &&
1618 instr
->operands
[0].getTemp().type() == definition
.getTemp().type()) {
1619 reg
= instr
->operands
[0].physReg();
1620 reg
.reg
+= definition
.size() * instr
->operands
[1].constantValue();
1621 assert(register_file
[reg
.reg
] == 0);
1623 reg
= get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
);
1625 definition
.setFixed(reg
);
1626 } else if (instr
->opcode
== aco_opcode::p_create_vector
) {
1627 PhysReg reg
= get_reg_create_vector(ctx
, register_file
, definition
.regClass(),
1628 parallelcopy
, instr
);
1629 definition
.setFixed(reg
);
1630 } else if (affinities
.find(definition
.tempId()) != affinities
.end() &&
1631 ctx
.assignments
.find(affinities
[definition
.tempId()]) != ctx
.assignments
.end()) {
1632 PhysReg reg
= ctx
.assignments
[affinities
[definition
.tempId()]].first
;
1633 if (get_reg_specified(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
, reg
))
1634 definition
.setFixed(reg
);
1636 definition
.setFixed(get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
));
1638 } else if (vectors
.find(definition
.tempId()) != vectors
.end()) {
1639 Instruction
* vec
= vectors
[definition
.tempId()];
1640 unsigned offset
= 0;
1641 for (const Operand
& op
: vec
->operands
) {
1642 if (op
.isTemp() && op
.tempId() == definition
.tempId())
1645 offset
+= op
.size();
1648 for (const Operand
& op
: vec
->operands
) {
1650 op
.tempId() != definition
.tempId() &&
1651 op
.getTemp().type() == definition
.getTemp().type() &&
1652 ctx
.assignments
.find(op
.tempId()) != ctx
.assignments
.end()) {
1653 PhysReg reg
= ctx
.assignments
[op
.tempId()].first
;
1654 reg
.reg
= reg
- k
+ offset
;
1655 if (get_reg_specified(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
, reg
)) {
1656 definition
.setFixed(reg
);
1662 if (!definition
.isFixed()) {
1663 std::pair
<PhysReg
, bool> res
= get_reg_vec(ctx
, register_file
, vec
->definitions
[0].regClass());
1664 PhysReg reg
= res
.first
;
1668 reg
= get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
);
1670 definition
.setFixed(reg
);
1673 definition
.setFixed(get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
));
1675 assert(definition
.isFixed() && ((definition
.getTemp().type() == RegType::vgpr
&& definition
.physReg() >= 256) ||
1676 (definition
.getTemp().type() != RegType::vgpr
&& definition
.physReg() < 256)));
1677 ctx
.defs_done
.set(i
);
1679 /* set live if it has a kill point */
1680 if (!definition
.isKill())
1681 live
.emplace(definition
.getTemp());
1683 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1684 renames
[block
.index
][definition
.tempId()] = definition
.getTemp();
1685 for (unsigned j
= 0; j
< definition
.size(); j
++)
1686 register_file
[definition
.physReg() + j
] = definition
.tempId();
1689 handle_pseudo(ctx
, register_file
, instr
.get());
1691 /* kill definitions */
1692 for (const Definition
& def
: instr
->definitions
) {
1693 if (def
.isTemp() && def
.isKill()) {
1694 for (unsigned j
= 0; j
< def
.size(); j
++) {
1695 register_file
[def
.physReg() + j
] = 0;
1700 /* emit parallelcopy */
1701 if (!parallelcopy
.empty()) {
1702 aco_ptr
<Pseudo_instruction
> pc
;
1703 pc
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_parallelcopy
, Format::PSEUDO
, parallelcopy
.size(), parallelcopy
.size()));
1704 bool temp_in_scc
= register_file
[scc
.reg
];
1705 bool sgpr_operands_alias_defs
= false;
1706 uint64_t sgpr_operands
[4] = {0, 0, 0, 0};
1707 for (unsigned i
= 0; i
< parallelcopy
.size(); i
++) {
1708 if (temp_in_scc
&& parallelcopy
[i
].first
.isTemp() && parallelcopy
[i
].first
.getTemp().type() == RegType::sgpr
) {
1709 if (!sgpr_operands_alias_defs
) {
1710 unsigned reg
= parallelcopy
[i
].first
.physReg().reg
;
1711 unsigned size
= parallelcopy
[i
].first
.getTemp().size();
1712 sgpr_operands
[reg
/ 64u] |= ((1u << size
) - 1) << (reg
% 64u);
1714 reg
= parallelcopy
[i
].second
.physReg().reg
;
1715 size
= parallelcopy
[i
].second
.getTemp().size();
1716 if (sgpr_operands
[reg
/ 64u] & ((1u << size
) - 1) << (reg
% 64u))
1717 sgpr_operands_alias_defs
= true;
1721 pc
->operands
[i
] = parallelcopy
[i
].first
;
1722 pc
->definitions
[i
] = parallelcopy
[i
].second
;
1723 assert(pc
->operands
[i
].size() == pc
->definitions
[i
].size());
1725 /* it might happen that the operand is already renamed. we have to restore the original name. */
1726 std::map
<unsigned, Temp
>::iterator it
= ctx
.orig_names
.find(pc
->operands
[i
].tempId());
1727 if (it
!= ctx
.orig_names
.end())
1728 pc
->operands
[i
].setTemp(it
->second
);
1729 unsigned orig_id
= pc
->operands
[i
].tempId();
1730 ctx
.orig_names
[pc
->definitions
[i
].tempId()] = pc
->operands
[i
].getTemp();
1732 pc
->operands
[i
].setTemp(read_variable(pc
->operands
[i
].getTemp(), block
.index
));
1733 renames
[block
.index
][orig_id
] = pc
->definitions
[i
].getTemp();
1734 renames
[block
.index
][pc
->definitions
[i
].tempId()] = pc
->definitions
[i
].getTemp();
1735 std::map
<unsigned, phi_info
>::iterator phi
= phi_map
.find(pc
->operands
[i
].tempId());
1736 if (phi
!= phi_map
.end())
1737 phi
->second
.uses
.emplace(pc
.get());
1740 if (temp_in_scc
&& sgpr_operands_alias_defs
) {
1741 /* disable definitions and re-enable operands */
1742 for (const Definition
& def
: instr
->definitions
) {
1743 if (def
.isTemp() && !def
.isKill()) {
1744 for (unsigned j
= 0; j
< def
.size(); j
++) {
1745 register_file
[def
.physReg() + j
] = 0x0;
1749 for (const Operand
& op
: instr
->operands
) {
1750 if (op
.isTemp() && op
.isFirstKill()) {
1751 for (unsigned j
= 0; j
< op
.size(); j
++)
1752 register_file
[op
.physReg() + j
] = 0xFFFF;
1756 handle_pseudo(ctx
, register_file
, pc
.get());
1758 /* re-enable live vars */
1759 for (const Operand
& op
: instr
->operands
) {
1760 if (op
.isTemp() && op
.isFirstKill())
1761 for (unsigned j
= 0; j
< op
.size(); j
++)
1762 register_file
[op
.physReg() + j
] = 0x0;
1764 for (const Definition
& def
: instr
->definitions
) {
1765 if (def
.isTemp() && !def
.isKill()) {
1766 for (unsigned j
= 0; j
< def
.size(); j
++) {
1767 register_file
[def
.physReg() + j
] = def
.tempId();
1772 pc
->tmp_in_scc
= false;
1775 instructions
.emplace_back(std::move(pc
));
1778 /* some instructions need VOP3 encoding if operand/definition is not assigned to VCC */
1779 bool instr_needs_vop3
= !instr
->isVOP3() &&
1780 ((instr
->format
== Format::VOPC
&& !(instr
->definitions
[0].physReg() == vcc
)) ||
1781 (instr
->opcode
== aco_opcode::v_cndmask_b32
&& !(instr
->operands
[2].physReg() == vcc
)) ||
1782 ((instr
->opcode
== aco_opcode::v_add_co_u32
||
1783 instr
->opcode
== aco_opcode::v_addc_co_u32
||
1784 instr
->opcode
== aco_opcode::v_sub_co_u32
||
1785 instr
->opcode
== aco_opcode::v_subb_co_u32
||
1786 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
1787 instr
->opcode
== aco_opcode::v_subbrev_co_u32
) &&
1788 !(instr
->definitions
[1].physReg() == vcc
)) ||
1789 ((instr
->opcode
== aco_opcode::v_addc_co_u32
||
1790 instr
->opcode
== aco_opcode::v_subb_co_u32
||
1791 instr
->opcode
== aco_opcode::v_subbrev_co_u32
) &&
1792 !(instr
->operands
[2].physReg() == vcc
)));
1793 if (instr_needs_vop3
) {
1795 /* if the first operand is a literal, we have to move it to a reg */
1796 if (instr
->operands
.size() && instr
->operands
[0].isLiteral()) {
1797 bool can_sgpr
= true;
1798 /* check, if we have to move to vgpr */
1799 for (const Operand
& op
: instr
->operands
) {
1800 if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1805 aco_ptr
<Instruction
> mov
;
1807 mov
.reset(create_instruction
<SOP1_instruction
>(aco_opcode::s_mov_b32
, Format::SOP1
, 1, 1));
1809 mov
.reset(create_instruction
<VOP1_instruction
>(aco_opcode::v_mov_b32
, Format::VOP1
, 1, 1));
1810 mov
->operands
[0] = instr
->operands
[0];
1811 Temp tmp
= {program
->allocateId(), can_sgpr
? s1
: v1
};
1812 mov
->definitions
[0] = Definition(tmp
);
1813 /* disable definitions and re-enable operands */
1814 for (const Definition
& def
: instr
->definitions
) {
1815 for (unsigned j
= 0; j
< def
.size(); j
++) {
1816 register_file
[def
.physReg() + j
] = 0x0;
1819 for (const Operand
& op
: instr
->operands
) {
1820 if (op
.isTemp() && op
.isFirstKill()) {
1821 for (unsigned j
= 0; j
< op
.size(); j
++)
1822 register_file
[op
.physReg() + j
] = 0xFFFF;
1825 mov
->definitions
[0].setFixed(get_reg(ctx
, register_file
, tmp
.regClass(), parallelcopy
, mov
));
1826 instr
->operands
[0] = Operand(tmp
);
1827 instr
->operands
[0].setFixed(mov
->definitions
[0].physReg());
1828 instructions
.emplace_back(std::move(mov
));
1829 /* re-enable live vars */
1830 for (const Operand
& op
: instr
->operands
) {
1831 if (op
.isTemp() && op
.isFirstKill())
1832 for (unsigned j
= 0; j
< op
.size(); j
++)
1833 register_file
[op
.physReg() + j
] = 0x0;
1835 for (const Definition
& def
: instr
->definitions
) {
1836 if (def
.isTemp() && !def
.isKill()) {
1837 for (unsigned j
= 0; j
< def
.size(); j
++) {
1838 register_file
[def
.physReg() + j
] = def
.tempId();
1844 /* change the instruction to VOP3 to enable an arbitrary register pair as dst */
1845 aco_ptr
<Instruction
> tmp
= std::move(instr
);
1846 Format format
= asVOP3(tmp
->format
);
1847 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
1848 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1849 Operand
& operand
= tmp
->operands
[i
];
1850 instr
->operands
[i
] = operand
;
1851 /* keep phi_map up to date */
1852 if (operand
.isTemp()) {
1853 std::map
<unsigned, phi_info
>::iterator phi
= phi_map
.find(operand
.tempId());
1854 if (phi
!= phi_map
.end()) {
1855 phi
->second
.uses
.erase(tmp
.get());
1856 phi
->second
.uses
.emplace(instr
.get());
1860 std::copy(tmp
->definitions
.begin(), tmp
->definitions
.end(), instr
->definitions
.begin());
1862 instructions
.emplace_back(std::move(*it
));
1864 } /* end for Instr */
1866 block
.instructions
= std::move(instructions
);
1868 filled
[block
.index
] = true;
1869 for (unsigned succ_idx
: block
.linear_succs
) {
1870 Block
& succ
= program
->blocks
[succ_idx
];
1871 /* seal block if all predecessors are filled */
1872 bool all_filled
= true;
1873 for (unsigned pred_idx
: succ
.linear_preds
) {
1874 if (!filled
[pred_idx
]) {
1880 /* finish incomplete phis and check if they became trivial */
1881 for (Instruction
* phi
: incomplete_phis
[succ_idx
]) {
1882 std::vector
<unsigned> preds
= phi
->definitions
[0].getTemp().is_linear() ? succ
.linear_preds
: succ
.logical_preds
;
1883 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
1884 phi
->operands
[i
].setTemp(read_variable(phi
->operands
[i
].getTemp(), preds
[i
]));
1885 phi
->operands
[i
].setFixed(ctx
.assignments
[phi
->operands
[i
].tempId()].first
);
1887 try_remove_trivial_phi(phi_map
.find(phi
->definitions
[0].tempId()));
1889 /* complete the original phi nodes, but no need to check triviality */
1890 for (aco_ptr
<Instruction
>& instr
: succ
.instructions
) {
1893 std::vector
<unsigned> preds
= instr
->opcode
== aco_opcode::p_phi
? succ
.logical_preds
: succ
.linear_preds
;
1895 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1896 auto& operand
= instr
->operands
[i
];
1897 if (!operand
.isTemp())
1899 operand
.setTemp(read_variable(operand
.getTemp(), preds
[i
]));
1900 operand
.setFixed(ctx
.assignments
[operand
.tempId()].first
);
1901 std::map
<unsigned, phi_info
>::iterator phi
= phi_map
.find(operand
.getTemp().id());
1902 if (phi
!= phi_map
.end())
1903 phi
->second
.uses
.emplace(instr
.get());
1906 sealed
[succ_idx
] = true;
1911 /* remove trivial phis */
1912 for (Block
& block
: program
->blocks
) {
1913 auto end
= std::find_if(block
.instructions
.begin(), block
.instructions
.end(),
1914 [](aco_ptr
<Instruction
>& instr
) { return !is_phi(instr
);});
1915 auto middle
= std::remove_if(block
.instructions
.begin(), end
,
1916 [](const aco_ptr
<Instruction
>& instr
) { return instr
->definitions
.empty();});
1917 block
.instructions
.erase(middle
, end
);
1920 /* find scc spill registers which may be needed for parallelcopies created by phis */
1921 for (Block
& block
: program
->blocks
) {
1922 if (block
.linear_preds
.size() <= 1)
1925 std::bitset
<128> regs
= sgpr_live_in
[block
.index
];
1929 /* choose a register */
1931 for (; reg
< ctx
.program
->max_reg_demand
.sgpr
&& regs
[reg
]; reg
++)
1933 assert(reg
< ctx
.program
->max_reg_demand
.sgpr
);
1934 adjust_max_used_regs(ctx
, s1
, reg
);
1936 /* update predecessors */
1937 for (unsigned& pred_index
: block
.linear_preds
) {
1938 Block
& pred
= program
->blocks
[pred_index
];
1939 pred
.scc_live_out
= true;
1940 pred
.scratch_sgpr
= PhysReg
{(uint16_t)reg
};
1944 /* num_gpr = rnd_up(max_used_gpr + 1) */
1945 program
->config
->num_vgprs
= align(ctx
.max_used_vgpr
+ 1, 4);
1946 if (program
->family
== CHIP_TONGA
|| program
->family
== CHIP_ICELAND
) /* workaround hardware bug */
1947 program
->config
->num_sgprs
= get_sgpr_alloc(program
, program
->sgpr_limit
);
1949 program
->config
->num_sgprs
= align(ctx
.max_used_sgpr
+ 1 + get_extra_sgprs(program
), 8);