2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
25 * Bas Nieuwenhuizen (bas@basnieuwenhuizen.nl)
32 #include <unordered_map>
37 #include "util/u_math.h"
43 std::bitset
<512> war_hint
;
45 std::unordered_map
<unsigned, std::pair
<PhysReg
, RegClass
>> assignments
;
46 std::map
<unsigned, Temp
> orig_names
;
47 unsigned max_used_sgpr
= 0;
48 unsigned max_used_vgpr
= 0;
49 std::bitset
<64> defs_done
; /* see MAX_ARGS in aco_instruction_selection_setup.cpp */
51 ra_ctx(Program
* program
) : program(program
) {}
56 RegisterFile() {regs
.fill(0);}
58 std::array
<uint32_t, 512> regs
;
60 const uint32_t& operator [] (unsigned index
) const {
64 uint32_t& operator [] (unsigned index
) {
68 unsigned count_zero(PhysReg start
, unsigned size
) {
70 for (unsigned i
= 0; i
< size
; i
++)
71 res
+= !regs
[start
+ i
];
75 bool test(PhysReg start
, unsigned size
) {
76 for (unsigned i
= 0; i
< size
; i
++) {
83 void fill(PhysReg start
, unsigned size
, uint32_t val
) {
84 for (unsigned i
= 0; i
< size
; i
++)
85 regs
[start
+ i
] = val
;
88 void clear(PhysReg start
, unsigned size
) {
92 void fill(Operand op
) {
93 fill(op
.physReg(), op
.size(), op
.tempId());
96 void clear(Operand op
) {
97 fill(op
.physReg(), op
.size(), 0);
100 void fill(Definition def
) {
101 fill(def
.physReg(), def
.size(), def
.tempId());
104 void clear(Definition def
) {
105 fill(def
.physReg(), def
.size(), 0);
110 /* helper function for debugging */
112 void print_regs(ra_ctx
& ctx
, bool vgprs
, RegisterFile
& reg_file
)
114 unsigned max
= vgprs
? ctx
.program
->max_reg_demand
.vgpr
: ctx
.program
->max_reg_demand
.sgpr
;
115 unsigned lb
= vgprs
? 256 : 0;
116 unsigned ub
= lb
+ max
;
117 char reg_char
= vgprs
? 'v' : 's';
121 for (unsigned i
= lb
; i
< ub
; i
+= 3) {
122 printf("%.2u ", i
- lb
);
127 printf("%cgprs: ", reg_char
);
128 unsigned free_regs
= 0;
130 bool char_select
= false;
131 for (unsigned i
= lb
; i
< ub
; i
++) {
132 if (reg_file
[i
] == 0xFFFF) {
134 } else if (reg_file
[i
]) {
135 if (reg_file
[i
] != prev
) {
137 char_select
= !char_select
;
139 printf(char_select
? "#" : "@");
147 printf("%u/%u used, %u/%u free\n", max
- free_regs
, max
, free_regs
, max
);
149 /* print assignments */
152 for (unsigned i
= lb
; i
< ub
; i
++) {
153 if (reg_file
[i
] != prev
) {
154 if (prev
&& size
> 1)
155 printf("-%d]\n", i
- 1 - lb
);
159 if (prev
&& prev
!= 0xFFFF) {
160 if (ctx
.orig_names
.count(reg_file
[i
]) && ctx
.orig_names
[reg_file
[i
]].id() != reg_file
[i
])
161 printf("%%%u (was %%%d) = %c[%d", reg_file
[i
], ctx
.orig_names
[reg_file
[i
]].id(), reg_char
, i
- lb
);
163 printf("%%%u = %c[%d", reg_file
[i
], reg_char
, i
- lb
);
170 if (prev
&& size
> 1)
171 printf("-%d]\n", ub
- lb
- 1);
178 void adjust_max_used_regs(ra_ctx
& ctx
, RegClass rc
, unsigned reg
)
180 unsigned max_addressible_sgpr
= ctx
.program
->sgpr_limit
;
181 unsigned size
= rc
.size();
182 if (rc
.type() == RegType::vgpr
) {
184 unsigned hi
= reg
- 256 + size
- 1;
185 ctx
.max_used_vgpr
= std::max(ctx
.max_used_vgpr
, hi
);
186 } else if (reg
+ rc
.size() <= max_addressible_sgpr
) {
187 unsigned hi
= reg
+ size
- 1;
188 ctx
.max_used_sgpr
= std::max(ctx
.max_used_sgpr
, std::min(hi
, max_addressible_sgpr
));
193 void update_renames(ra_ctx
& ctx
, RegisterFile
& reg_file
,
194 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
195 aco_ptr
<Instruction
>& instr
)
197 /* allocate id's and rename operands: this is done transparently here */
198 for (std::pair
<Operand
, Definition
>& copy
: parallelcopies
) {
199 /* the definitions with id are not from this function and already handled */
200 if (copy
.second
.isTemp())
203 /* check if we we moved another parallelcopy definition */
204 for (std::pair
<Operand
, Definition
>& other
: parallelcopies
) {
205 if (!other
.second
.isTemp())
207 if (copy
.first
.getTemp() == other
.second
.getTemp()) {
208 copy
.first
.setTemp(other
.first
.getTemp());
209 copy
.first
.setFixed(other
.first
.physReg());
212 // FIXME: if a definition got moved, change the target location and remove the parallelcopy
213 copy
.second
.setTemp(Temp(ctx
.program
->allocateId(), copy
.second
.regClass()));
214 ctx
.assignments
[copy
.second
.tempId()] = {copy
.second
.physReg(), copy
.second
.regClass()};
215 for (unsigned i
= copy
.second
.physReg().reg
; i
< copy
.second
.physReg() + copy
.second
.size(); i
++)
216 reg_file
[i
] = copy
.second
.tempId();
217 /* check if we moved an operand */
218 for (Operand
& op
: instr
->operands
) {
221 if (op
.tempId() == copy
.first
.tempId()) {
222 bool omit_renaming
= instr
->opcode
== aco_opcode::p_create_vector
&& !op
.isKill();
223 for (std::pair
<Operand
, Definition
>& pc
: parallelcopies
) {
224 PhysReg def_reg
= pc
.second
.physReg();
225 omit_renaming
&= def_reg
> copy
.first
.physReg() ?
226 (copy
.first
.physReg() + copy
.first
.size() <= def_reg
.reg
) :
227 (def_reg
+ pc
.second
.size() <= copy
.first
.physReg().reg
);
231 op
.setTemp(copy
.second
.getTemp());
232 op
.setFixed(copy
.second
.physReg());
238 std::pair
<PhysReg
, bool> get_reg_simple(ra_ctx
& ctx
,
239 RegisterFile
& reg_file
,
240 uint32_t lb
, uint32_t ub
,
241 uint32_t size
, uint32_t stride
,
244 /* best fit algorithm: find the smallest gap to fit in the variable */
246 unsigned best_pos
= 0xFFFF;
247 unsigned gap_size
= 0xFFFF;
248 unsigned next_pos
= 0xFFFF;
250 for (unsigned current_reg
= lb
; current_reg
< ub
; current_reg
++) {
251 if (reg_file
[current_reg
] != 0 || ctx
.war_hint
[current_reg
]) {
252 if (next_pos
== 0xFFFF)
255 /* check if the variable fits */
256 if (next_pos
+ size
> current_reg
) {
261 /* check if the tested gap is smaller */
262 if (current_reg
- next_pos
< gap_size
) {
264 gap_size
= current_reg
- next_pos
;
270 if (next_pos
== 0xFFFF)
271 next_pos
= current_reg
;
275 if (next_pos
!= 0xFFFF &&
276 next_pos
+ size
<= ub
&&
277 ub
- next_pos
< gap_size
) {
279 gap_size
= ub
- next_pos
;
281 if (best_pos
!= 0xFFFF) {
282 adjust_max_used_regs(ctx
, rc
, best_pos
);
283 return {PhysReg
{best_pos
}, true};
289 unsigned reg_lo
= lb
;
290 unsigned reg_hi
= lb
+ size
- 1;
291 while (!found
&& reg_lo
+ size
<= ub
) {
292 if (reg_file
[reg_lo
] != 0) {
296 reg_hi
= reg_lo
+ size
- 1;
298 for (unsigned reg
= reg_lo
+ 1; found
&& reg
<= reg_hi
; reg
++) {
299 if (reg_file
[reg
] != 0 || ctx
.war_hint
[reg
])
303 adjust_max_used_regs(ctx
, rc
, reg_lo
);
304 return {PhysReg
{reg_lo
}, true};
313 bool get_regs_for_copies(ra_ctx
& ctx
,
314 RegisterFile
& reg_file
,
315 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
316 std::set
<std::pair
<unsigned, unsigned>> vars
,
317 uint32_t lb
, uint32_t ub
,
318 aco_ptr
<Instruction
>& instr
,
323 /* variables are sorted from small sized to large */
324 /* NOTE: variables are also sorted by ID. this only affects a very small number of shaders slightly though. */
325 for (std::set
<std::pair
<unsigned, unsigned>>::reverse_iterator it
= vars
.rbegin(); it
!= vars
.rend(); ++it
) {
326 unsigned id
= it
->second
;
327 std::pair
<PhysReg
, RegClass
> var
= ctx
.assignments
[id
];
328 uint32_t size
= it
->first
;
330 if (var
.second
.type() == RegType::sgpr
) {
337 /* check if this is a dead operand, then we can re-use the space from the definition */
338 bool is_dead_operand
= false;
339 for (unsigned i
= 0; !is_phi(instr
) && !is_dead_operand
&& i
< instr
->operands
.size(); i
++) {
340 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].isKill() && instr
->operands
[i
].tempId() == id
)
341 is_dead_operand
= true;
344 std::pair
<PhysReg
, bool> res
;
345 if (is_dead_operand
) {
346 if (instr
->opcode
== aco_opcode::p_create_vector
) {
347 for (unsigned i
= 0, offset
= 0; i
< instr
->operands
.size(); offset
+= instr
->operands
[i
].size(), i
++) {
348 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == id
) {
349 for (unsigned j
= 0; j
< size
; j
++)
350 assert(reg_file
[def_reg_lo
+ offset
+ j
] == 0);
351 res
= {PhysReg
{def_reg_lo
+ offset
}, true};
356 res
= get_reg_simple(ctx
, reg_file
, def_reg_lo
, def_reg_hi
+ 1, size
, stride
, var
.second
);
359 res
= get_reg_simple(ctx
, reg_file
, lb
, def_reg_lo
, size
, stride
, var
.second
);
361 unsigned lb
= (def_reg_hi
+ stride
) & ~(stride
- 1);
362 res
= get_reg_simple(ctx
, reg_file
, lb
, ub
, size
, stride
, var
.second
);
367 /* mark the area as blocked */
368 reg_file
.fill(res
.first
, size
, 0xFFFFFFFF);
369 /* create parallelcopy pair (without definition id) */
370 Temp tmp
= Temp(id
, var
.second
);
371 Operand pc_op
= Operand(tmp
);
372 pc_op
.setFixed(var
.first
);
373 Definition pc_def
= Definition(res
.first
, pc_op
.regClass());
374 parallelcopies
.emplace_back(pc_op
, pc_def
);
378 unsigned best_pos
= lb
;
379 unsigned num_moves
= 0xFF;
380 unsigned num_vars
= 0;
382 /* we use a sliding window to find potential positions */
383 unsigned reg_lo
= lb
;
384 unsigned reg_hi
= lb
+ size
- 1;
385 for (reg_lo
= lb
, reg_hi
= lb
+ size
- 1; reg_hi
< ub
; reg_lo
+= stride
, reg_hi
+= stride
) {
386 if (!is_dead_operand
&& ((reg_lo
>= def_reg_lo
&& reg_lo
<= def_reg_hi
) ||
387 (reg_hi
>= def_reg_lo
&& reg_hi
<= def_reg_hi
)))
390 /* second, check that we have at most k=num_moves elements in the window
391 * and no element is larger than the currently processed one */
394 unsigned last_var
= 0;
396 for (unsigned j
= reg_lo
; found
&& j
<= reg_hi
; j
++) {
397 if (reg_file
[j
] == 0 || reg_file
[j
] == last_var
)
400 /* 0xFFFF signals that this area is already blocked! */
401 if (reg_file
[j
] == 0xFFFFFFFF || k
> num_moves
) {
405 /* we cannot split live ranges of linear vgprs */
406 if (ctx
.assignments
[reg_file
[j
]].second
& (1 << 6)) {
410 bool is_kill
= false;
411 for (const Operand
& op
: instr
->operands
) {
412 if (op
.isTemp() && op
.isKill() && op
.tempId() == reg_file
[j
]) {
417 if (!is_kill
&& ctx
.assignments
[reg_file
[j
]].second
.size() >= size
) {
422 k
+= ctx
.assignments
[reg_file
[j
]].second
.size();
423 last_var
= reg_file
[j
];
425 if (k
> num_moves
|| (k
== num_moves
&& n
<= num_vars
)) {
438 /* FIXME: we messed up and couldn't find space for the variables to be copied */
439 if (num_moves
== 0xFF)
443 reg_hi
= best_pos
+ size
- 1;
445 /* collect variables and block reg file */
446 std::set
<std::pair
<unsigned, unsigned>> new_vars
;
447 for (unsigned j
= reg_lo
; j
<= reg_hi
; j
++) {
448 if (reg_file
[j
] != 0) {
449 unsigned size
= ctx
.assignments
[reg_file
[j
]].second
.size();
450 unsigned id
= reg_file
[j
];
451 new_vars
.emplace(size
, id
);
452 reg_file
.clear(ctx
.assignments
[id
].first
, size
);
456 /* mark the area as blocked */
457 reg_file
.fill(PhysReg
{reg_lo
}, size
, 0xFFFFFFFF);
459 if (!get_regs_for_copies(ctx
, reg_file
, parallelcopies
, new_vars
, lb
, ub
, instr
, def_reg_lo
, def_reg_hi
))
462 adjust_max_used_regs(ctx
, var
.second
, reg_lo
);
464 /* create parallelcopy pair (without definition id) */
465 Temp tmp
= Temp(id
, var
.second
);
466 Operand pc_op
= Operand(tmp
);
467 pc_op
.setFixed(var
.first
);
468 Definition pc_def
= Definition(PhysReg
{reg_lo
}, pc_op
.regClass());
469 parallelcopies
.emplace_back(pc_op
, pc_def
);
476 std::pair
<PhysReg
, bool> get_reg_impl(ra_ctx
& ctx
,
477 RegisterFile
& reg_file
,
478 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
479 uint32_t lb
, uint32_t ub
,
480 uint32_t size
, uint32_t stride
,
482 aco_ptr
<Instruction
>& instr
)
484 /* check how many free regs we have */
485 unsigned regs_free
= reg_file
.count_zero(PhysReg
{lb
}, ub
-lb
);
487 /* mark and count killed operands */
488 unsigned killed_ops
= 0;
489 for (unsigned j
= 0; !is_phi(instr
) && j
< instr
->operands
.size(); j
++) {
490 if (instr
->operands
[j
].isTemp() &&
491 instr
->operands
[j
].isFirstKill() &&
492 instr
->operands
[j
].physReg() >= lb
&&
493 instr
->operands
[j
].physReg() < ub
) {
494 assert(instr
->operands
[j
].isFixed());
495 assert(reg_file
[instr
->operands
[j
].physReg().reg
] == 0);
496 reg_file
.fill(instr
->operands
[j
].physReg(), instr
->operands
[j
].size(), 0xFFFFFFFF);
497 killed_ops
+= instr
->operands
[j
].getTemp().size();
501 assert(regs_free
>= size
);
502 /* we might have to move dead operands to dst in order to make space */
503 unsigned op_moves
= 0;
505 if (size
> (regs_free
- killed_ops
))
506 op_moves
= size
- (regs_free
- killed_ops
);
508 /* find the best position to place the definition */
509 unsigned best_pos
= lb
;
510 unsigned num_moves
= 0xFF;
511 unsigned num_vars
= 0;
513 /* we use a sliding window to check potential positions */
514 unsigned reg_lo
= lb
;
515 unsigned reg_hi
= lb
+ size
- 1;
516 for (reg_lo
= lb
, reg_hi
= lb
+ size
- 1; reg_hi
< ub
; reg_lo
+= stride
, reg_hi
+= stride
) {
517 /* first check the edges: this is what we have to fix to allow for num_moves > size */
518 if (reg_lo
> lb
&& reg_file
[reg_lo
] != 0 && reg_file
[reg_lo
] == reg_file
[reg_lo
- 1])
520 if (reg_hi
< ub
- 1 && reg_file
[reg_hi
] != 0 && reg_file
[reg_hi
] == reg_file
[reg_hi
+ 1])
523 /* second, check that we have at most k=num_moves elements in the window
524 * and no element is larger than the currently processed one */
525 unsigned k
= op_moves
;
527 unsigned remaining_op_moves
= op_moves
;
528 unsigned last_var
= 0;
530 bool aligned
= rc
== RegClass::v4
&& reg_lo
% 4 == 0;
531 for (unsigned j
= reg_lo
; found
&& j
<= reg_hi
; j
++) {
532 if (reg_file
[j
] == 0 || reg_file
[j
] == last_var
)
535 /* dead operands effectively reduce the number of estimated moves */
536 if (remaining_op_moves
&& reg_file
[j
] == 0xFFFFFFFF) {
538 remaining_op_moves
--;
542 if (ctx
.assignments
[reg_file
[j
]].second
.size() >= size
) {
548 /* we cannot split live ranges of linear vgprs */
549 if (ctx
.assignments
[reg_file
[j
]].second
& (1 << 6)) {
554 k
+= ctx
.assignments
[reg_file
[j
]].second
.size();
556 last_var
= reg_file
[j
];
559 if (!found
|| k
> num_moves
)
561 if (k
== num_moves
&& n
< num_vars
)
563 if (!aligned
&& k
== num_moves
&& n
== num_vars
)
573 if (num_moves
== 0xFF) {
574 /* remove killed operands from reg_file once again */
575 for (unsigned i
= 0; !is_phi(instr
) && i
< instr
->operands
.size(); i
++) {
576 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].isFirstKill())
577 reg_file
.clear(instr
->operands
[i
]);
579 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
580 Definition def
= instr
->definitions
[i
];
581 if (def
.isTemp() && def
.isFixed() && ctx
.defs_done
.test(i
))
587 RegisterFile register_file
= reg_file
;
589 /* now, we figured the placement for our definition */
590 std::set
<std::pair
<unsigned, unsigned>> vars
;
591 for (unsigned j
= best_pos
; j
< best_pos
+ size
; j
++) {
592 if (reg_file
[j
] != 0xFFFFFFFF && reg_file
[j
] != 0)
593 vars
.emplace(ctx
.assignments
[reg_file
[j
]].second
.size(), reg_file
[j
]);
597 if (instr
->opcode
== aco_opcode::p_create_vector
) {
598 /* move killed operands which aren't yet at the correct position */
599 for (unsigned i
= 0, offset
= 0; i
< instr
->operands
.size(); offset
+= instr
->operands
[i
].size(), i
++) {
600 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].isFirstKill() &&
601 instr
->operands
[i
].getTemp().type() == rc
.type()) {
603 if (instr
->operands
[i
].physReg() != best_pos
+ offset
) {
604 vars
.emplace(instr
->operands
[i
].size(), instr
->operands
[i
].tempId());
605 reg_file
.clear(instr
->operands
[i
]);
607 reg_file
.fill(instr
->operands
[i
]);
612 /* re-enable the killed operands */
613 for (unsigned j
= 0; !is_phi(instr
) && j
< instr
->operands
.size(); j
++) {
614 if (instr
->operands
[j
].isTemp() && instr
->operands
[j
].isFirstKill())
615 reg_file
.fill(instr
->operands
[j
]);
619 std::vector
<std::pair
<Operand
, Definition
>> pc
;
620 if (!get_regs_for_copies(ctx
, reg_file
, pc
, vars
, lb
, ub
, instr
, best_pos
, best_pos
+ size
- 1)) {
621 reg_file
= std::move(register_file
);
622 /* remove killed operands from reg_file once again */
623 if (!is_phi(instr
)) {
624 for (const Operand
& op
: instr
->operands
) {
625 if (op
.isTemp() && op
.isFirstKill())
629 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
630 Definition
& def
= instr
->definitions
[i
];
631 if (def
.isTemp() && def
.isFixed() && ctx
.defs_done
.test(i
))
637 parallelcopies
.insert(parallelcopies
.end(), pc
.begin(), pc
.end());
639 /* we set the definition regs == 0. the actual caller is responsible for correct setting */
640 reg_file
.clear(PhysReg
{best_pos
}, size
);
642 update_renames(ctx
, reg_file
, parallelcopies
, instr
);
644 /* remove killed operands from reg_file once again */
645 for (unsigned i
= 0; !is_phi(instr
) && i
< instr
->operands
.size(); i
++) {
646 if (!instr
->operands
[i
].isTemp() || !instr
->operands
[i
].isFixed())
648 assert(!instr
->operands
[i
].isUndefined());
649 if (instr
->operands
[i
].isFirstKill())
650 reg_file
.clear(instr
->operands
[i
]);
652 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
653 Definition def
= instr
->definitions
[i
];
654 if (def
.isTemp() && def
.isFixed() && ctx
.defs_done
.test(i
))
658 adjust_max_used_regs(ctx
, rc
, best_pos
);
659 return {PhysReg
{best_pos
}, true};
662 PhysReg
get_reg(ra_ctx
& ctx
,
663 RegisterFile
& reg_file
,
665 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
666 aco_ptr
<Instruction
>& instr
)
668 uint32_t size
= rc
.size();
671 if (rc
.type() == RegType::vgpr
) {
673 ub
= 256 + ctx
.program
->max_reg_demand
.vgpr
;
676 ub
= ctx
.program
->max_reg_demand
.sgpr
;
683 std::pair
<PhysReg
, bool> res
= {{}, false};
684 /* try to find space without live-range splits */
685 if (rc
.type() == RegType::vgpr
&& (size
== 4 || size
== 8))
686 res
= get_reg_simple(ctx
, reg_file
, lb
, ub
, size
, 4, rc
);
688 res
= get_reg_simple(ctx
, reg_file
, lb
, ub
, size
, stride
, rc
);
692 /* try to find space with live-range splits */
693 res
= get_reg_impl(ctx
, reg_file
, parallelcopies
, lb
, ub
, size
, stride
, rc
, instr
);
698 /* We should only fail here because keeping under the limit would require
700 assert(reg_file
.count_zero(PhysReg
{lb
}, ub
-lb
) >= size
);
702 /* try using more registers */
703 uint16_t max_addressible_sgpr
= ctx
.program
->sgpr_limit
;
704 uint16_t max_addressible_vgpr
= ctx
.program
->vgpr_limit
;
705 if (rc
.type() == RegType::vgpr
&& ctx
.program
->max_reg_demand
.vgpr
< max_addressible_vgpr
) {
706 update_vgpr_sgpr_demand(ctx
.program
, RegisterDemand(ctx
.program
->max_reg_demand
.vgpr
+ 1, ctx
.program
->max_reg_demand
.sgpr
));
707 return get_reg(ctx
, reg_file
, rc
, parallelcopies
, instr
);
708 } else if (rc
.type() == RegType::sgpr
&& ctx
.program
->max_reg_demand
.sgpr
< max_addressible_sgpr
) {
709 update_vgpr_sgpr_demand(ctx
.program
, RegisterDemand(ctx
.program
->max_reg_demand
.vgpr
, ctx
.program
->max_reg_demand
.sgpr
+ 1));
710 return get_reg(ctx
, reg_file
, rc
, parallelcopies
, instr
);
713 //FIXME: if nothing helps, shift-rotate the registers to make space
715 unreachable("did not find a register");
719 std::pair
<PhysReg
, bool> get_reg_vec(ra_ctx
& ctx
,
720 RegisterFile
& reg_file
,
723 uint32_t size
= rc
.size();
726 if (rc
.type() == RegType::vgpr
) {
728 ub
= 256 + ctx
.program
->max_reg_demand
.vgpr
;
731 ub
= ctx
.program
->max_reg_demand
.sgpr
;
737 return get_reg_simple(ctx
, reg_file
, lb
, ub
, size
, stride
, rc
);
741 PhysReg
get_reg_create_vector(ra_ctx
& ctx
,
742 RegisterFile
& reg_file
,
744 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
745 aco_ptr
<Instruction
>& instr
)
747 /* create_vector instructions have different costs w.r.t. register coalescing */
748 uint32_t size
= rc
.size();
751 if (rc
.type() == RegType::vgpr
) {
753 ub
= 256 + ctx
.program
->max_reg_demand
.vgpr
;
756 ub
= ctx
.program
->max_reg_demand
.sgpr
;
763 unsigned best_pos
= -1;
764 unsigned num_moves
= 0xFF;
765 bool best_war_hint
= true;
767 /* test for each operand which definition placement causes the least shuffle instructions */
768 for (unsigned i
= 0, offset
= 0; i
< instr
->operands
.size(); offset
+= instr
->operands
[i
].size(), i
++) {
769 // TODO: think about, if we can alias live operands on the same register
770 if (!instr
->operands
[i
].isTemp() || !instr
->operands
[i
].isKill() || instr
->operands
[i
].getTemp().type() != rc
.type())
773 if (offset
> instr
->operands
[i
].physReg())
776 unsigned reg_lo
= instr
->operands
[i
].physReg() - offset
;
777 unsigned reg_hi
= reg_lo
+ size
- 1;
780 /* no need to check multiple times */
781 if (reg_lo
== best_pos
)
785 // TODO: this can be improved */
786 if (reg_lo
< lb
|| reg_hi
>= ub
|| reg_lo
% stride
!= 0)
788 if (reg_lo
> lb
&& reg_file
[reg_lo
] != 0 && reg_file
[reg_lo
] == reg_file
[reg_lo
- 1])
790 if (reg_hi
< ub
- 1 && reg_file
[reg_hi
] != 0 && reg_file
[reg_hi
] == reg_file
[reg_hi
+ 1])
793 /* count variables to be moved and check war_hint */
794 bool war_hint
= false;
795 bool linear_vgpr
= false;
796 for (unsigned j
= reg_lo
; j
<= reg_hi
&& !linear_vgpr
; j
++) {
797 if (reg_file
[j
] != 0) {
799 /* we cannot split live ranges of linear vgprs */
800 if (ctx
.assignments
[reg_file
[j
]].second
& (1 << 6))
803 war_hint
|= ctx
.war_hint
[j
];
805 if (linear_vgpr
|| (war_hint
&& !best_war_hint
))
808 /* count operands in wrong positions */
809 for (unsigned j
= 0, offset
= 0; j
< instr
->operands
.size(); offset
+= instr
->operands
[j
].size(), j
++) {
811 !instr
->operands
[j
].isTemp() ||
812 instr
->operands
[j
].getTemp().type() != rc
.type())
814 if (instr
->operands
[j
].physReg() != reg_lo
+ offset
)
815 k
+= instr
->operands
[j
].size();
817 bool aligned
= rc
== RegClass::v4
&& reg_lo
% 4 == 0;
818 if (k
> num_moves
|| (!aligned
&& k
== num_moves
))
823 best_war_hint
= war_hint
;
826 if (num_moves
>= size
)
827 return get_reg(ctx
, reg_file
, rc
, parallelcopies
, instr
);
829 /* collect variables to be moved */
830 std::set
<std::pair
<unsigned, unsigned>> vars
;
831 for (unsigned i
= best_pos
; i
< best_pos
+ size
; i
++) {
832 if (reg_file
[i
] != 0)
833 vars
.emplace(ctx
.assignments
[reg_file
[i
]].second
.size(), reg_file
[i
]);
837 /* move killed operands which aren't yet at the correct position */
838 for (unsigned i
= 0, offset
= 0; i
< instr
->operands
.size(); offset
+= instr
->operands
[i
].size(), i
++) {
839 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].isFirstKill() && instr
->operands
[i
].getTemp().type() == rc
.type()) {
840 if (instr
->operands
[i
].physReg() != best_pos
+ offset
)
841 vars
.emplace(instr
->operands
[i
].size(), instr
->operands
[i
].tempId());
843 reg_file
.fill(instr
->operands
[i
]);
847 ASSERTED
bool success
= false;
848 success
= get_regs_for_copies(ctx
, reg_file
, parallelcopies
, vars
, lb
, ub
, instr
, best_pos
, best_pos
+ size
- 1);
851 update_renames(ctx
, reg_file
, parallelcopies
, instr
);
852 adjust_max_used_regs(ctx
, rc
, best_pos
);
853 return PhysReg
{best_pos
};
856 bool get_reg_specified(ra_ctx
& ctx
,
857 RegisterFile
& reg_file
,
859 std::vector
<std::pair
<Operand
, Definition
>>& parallelcopies
,
860 aco_ptr
<Instruction
>& instr
,
863 uint32_t size
= rc
.size();
867 if (rc
.type() == RegType::vgpr
) {
869 ub
= 256 + ctx
.program
->max_reg_demand
.vgpr
;
875 if (reg
% stride
!= 0)
878 ub
= ctx
.program
->max_reg_demand
.sgpr
;
881 uint32_t reg_lo
= reg
.reg
;
882 uint32_t reg_hi
= reg
+ (size
- 1);
884 if (reg_lo
< lb
|| reg_hi
>= ub
|| reg_lo
> reg_hi
)
887 if (reg_file
.test(reg
, size
))
889 adjust_max_used_regs(ctx
, rc
, reg_lo
);
893 void handle_pseudo(ra_ctx
& ctx
,
894 const RegisterFile
& reg_file
,
897 if (instr
->format
!= Format::PSEUDO
)
900 /* all instructions which use handle_operands() need this information */
901 switch (instr
->opcode
) {
902 case aco_opcode::p_extract_vector
:
903 case aco_opcode::p_create_vector
:
904 case aco_opcode::p_split_vector
:
905 case aco_opcode::p_parallelcopy
:
906 case aco_opcode::p_wqm
:
912 /* if all definitions are vgpr, no need to care for SCC */
913 bool writes_sgpr
= false;
914 for (Definition
& def
: instr
->definitions
) {
915 if (def
.getTemp().type() == RegType::sgpr
) {
920 /* if all operands are constant, no need to care either */
921 bool reads_sgpr
= false;
922 for (Operand
& op
: instr
->operands
) {
923 if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
928 if (!(writes_sgpr
&& reads_sgpr
))
931 Pseudo_instruction
*pi
= (Pseudo_instruction
*)instr
;
932 if (reg_file
[scc
.reg
]) {
933 pi
->tmp_in_scc
= true;
935 int reg
= ctx
.max_used_sgpr
;
936 for (; reg
>= 0 && reg_file
[reg
]; reg
--)
939 reg
= ctx
.max_used_sgpr
+ 1;
940 for (; reg
< ctx
.program
->max_reg_demand
.sgpr
&& reg_file
[reg
]; reg
++)
942 assert(reg
< ctx
.program
->max_reg_demand
.sgpr
);
945 adjust_max_used_regs(ctx
, s1
, reg
);
946 pi
->scratch_sgpr
= PhysReg
{(unsigned)reg
};
948 pi
->tmp_in_scc
= false;
952 bool operand_can_use_reg(aco_ptr
<Instruction
>& instr
, unsigned idx
, PhysReg reg
)
954 switch (instr
->format
) {
958 (reg
!= m0
|| idx
== 1 || idx
== 3) && /* offset can be m0 */
959 (reg
!= vcc
|| (instr
->definitions
.empty() && idx
== 2)); /* sdata can be vcc */
961 // TODO: there are more instructions with restrictions on registers
966 } /* end namespace */
969 void register_allocation(Program
*program
, std::vector
<std::set
<Temp
>> live_out_per_block
)
973 std::vector
<std::unordered_map
<unsigned, Temp
>> renames(program
->blocks
.size());
978 std::set
<Instruction
*> uses
;
981 bool filled
[program
->blocks
.size()];
982 bool sealed
[program
->blocks
.size()];
983 memset(filled
, 0, sizeof filled
);
984 memset(sealed
, 0, sizeof sealed
);
985 std::vector
<std::vector
<Instruction
*>> incomplete_phis(program
->blocks
.size());
986 std::map
<unsigned, phi_info
> phi_map
;
987 std::map
<unsigned, unsigned> affinities
;
988 std::function
<Temp(Temp
,unsigned)> read_variable
;
989 std::function
<Temp(Temp
,Block
*)> handle_live_in
;
990 std::function
<Temp(std::map
<unsigned, phi_info
>::iterator
)> try_remove_trivial_phi
;
992 read_variable
= [&](Temp val
, unsigned block_idx
) -> Temp
{
993 std::unordered_map
<unsigned, Temp
>::iterator it
= renames
[block_idx
].find(val
.id());
994 assert(it
!= renames
[block_idx
].end());
998 handle_live_in
= [&](Temp val
, Block
*block
) -> Temp
{
999 std::vector
<unsigned>& preds
= val
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
1000 if (preds
.size() == 0 || val
.regClass() == val
.regClass().as_linear()) {
1001 renames
[block
->index
][val
.id()] = val
;
1004 assert(preds
.size() > 0);
1007 if (!sealed
[block
->index
]) {
1008 /* consider rename from already processed predecessor */
1009 Temp tmp
= read_variable(val
, preds
[0]);
1011 /* if the block is not sealed yet, we create an incomplete phi (which might later get removed again) */
1012 new_val
= Temp
{program
->allocateId(), val
.regClass()};
1013 aco_opcode opcode
= val
.is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
1014 aco_ptr
<Instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
1015 phi
->definitions
[0] = Definition(new_val
);
1016 for (unsigned i
= 0; i
< preds
.size(); i
++)
1017 phi
->operands
[i
] = Operand(val
);
1018 if (tmp
.regClass() == new_val
.regClass())
1019 affinities
[new_val
.id()] = tmp
.id();
1021 phi_map
.emplace(new_val
.id(), phi_info
{phi
.get(), block
->index
});
1022 incomplete_phis
[block
->index
].emplace_back(phi
.get());
1023 block
->instructions
.insert(block
->instructions
.begin(), std::move(phi
));
1025 } else if (preds
.size() == 1) {
1026 /* if the block has only one predecessor, just look there for the name */
1027 new_val
= read_variable(val
, preds
[0]);
1029 /* there are multiple predecessors and the block is sealed */
1030 Temp ops
[preds
.size()];
1032 /* we start assuming that the name is the same from all predecessors */
1033 renames
[block
->index
][val
.id()] = val
;
1034 bool needs_phi
= false;
1036 /* get the rename from each predecessor and check if they are the same */
1037 for (unsigned i
= 0; i
< preds
.size(); i
++) {
1038 ops
[i
] = read_variable(val
, preds
[i
]);
1042 needs_phi
|= !(new_val
== ops
[i
]);
1046 /* the variable has been renamed differently in the predecessors: we need to insert a phi */
1047 aco_opcode opcode
= val
.is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
1048 aco_ptr
<Instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
1049 new_val
= Temp
{program
->allocateId(), val
.regClass()};
1050 phi
->definitions
[0] = Definition(new_val
);
1051 for (unsigned i
= 0; i
< preds
.size(); i
++) {
1052 phi
->operands
[i
] = Operand(ops
[i
]);
1053 phi
->operands
[i
].setFixed(ctx
.assignments
[ops
[i
].id()].first
);
1054 if (ops
[i
].regClass() == new_val
.regClass())
1055 affinities
[new_val
.id()] = ops
[i
].id();
1057 phi_map
.emplace(new_val
.id(), phi_info
{phi
.get(), block
->index
});
1058 block
->instructions
.insert(block
->instructions
.begin(), std::move(phi
));
1062 renames
[block
->index
][val
.id()] = new_val
;
1063 renames
[block
->index
][new_val
.id()] = new_val
;
1064 ctx
.orig_names
[new_val
.id()] = val
;
1068 try_remove_trivial_phi
= [&] (std::map
<unsigned, phi_info
>::iterator info
) -> Temp
{
1069 assert(info
->second
.block_idx
!= 0);
1070 Instruction
* phi
= info
->second
.phi
;
1073 Definition def
= phi
->definitions
[0];
1074 /* a phi node is trivial if all operands are the same as the definition of the phi */
1075 for (const Operand
& op
: phi
->operands
) {
1076 const Temp t
= op
.getTemp();
1077 if (t
== same
|| t
== def
.getTemp())
1079 if (!(same
== Temp()) || !(op
.physReg() == def
.physReg())) {
1080 /* phi is not trivial */
1081 return def
.getTemp();
1085 assert(!(same
== Temp() || same
== def
.getTemp()));
1087 /* reroute all uses to same and remove phi */
1088 std::vector
<std::map
<unsigned, phi_info
>::iterator
> phi_users
;
1089 std::map
<unsigned, phi_info
>::iterator same_phi_info
= phi_map
.find(same
.id());
1090 for (Instruction
* instr
: info
->second
.uses
) {
1091 assert(phi
!= instr
);
1092 /* recursively try to remove trivial phis */
1093 if (is_phi(instr
)) {
1094 /* ignore if the phi was already flagged trivial */
1095 if (instr
->definitions
.empty())
1098 std::map
<unsigned, phi_info
>::iterator it
= phi_map
.find(instr
->definitions
[0].tempId());
1099 if (it
!= phi_map
.end() && it
!= info
)
1100 phi_users
.emplace_back(it
);
1102 for (Operand
& op
: instr
->operands
) {
1103 if (op
.isTemp() && op
.tempId() == def
.tempId()) {
1105 if (same_phi_info
!= phi_map
.end())
1106 same_phi_info
->second
.uses
.emplace(instr
);
1111 auto it
= ctx
.orig_names
.find(same
.id());
1112 unsigned orig_var
= it
!= ctx
.orig_names
.end() ? it
->second
.id() : same
.id();
1113 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++) {
1114 auto it
= renames
[i
].find(orig_var
);
1115 if (it
!= renames
[i
].end() && it
->second
== def
.getTemp())
1116 renames
[i
][orig_var
] = same
;
1119 unsigned block_idx
= info
->second
.block_idx
;
1120 phi
->definitions
.clear(); /* this indicates that the phi can be removed */
1121 phi_map
.erase(info
);
1122 for (auto it
: phi_users
) {
1123 if (sealed
[it
->second
.block_idx
])
1124 try_remove_trivial_phi(it
);
1127 /* due to the removal of other phis, the name might have changed once again! */
1128 return renames
[block_idx
][orig_var
];
1131 std::map
<unsigned, Instruction
*> vectors
;
1132 std::vector
<std::vector
<Temp
>> phi_ressources
;
1133 std::map
<unsigned, unsigned> temp_to_phi_ressources
;
1135 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); it
++) {
1138 /* first, compute the death points of all live vars within the block */
1139 std::set
<Temp
>& live
= live_out_per_block
[block
.index
];
1141 std::vector
<aco_ptr
<Instruction
>>::reverse_iterator rit
;
1142 for (rit
= block
.instructions
.rbegin(); rit
!= block
.instructions
.rend(); ++rit
) {
1143 aco_ptr
<Instruction
>& instr
= *rit
;
1144 if (is_phi(instr
)) {
1145 live
.erase(instr
->definitions
[0].getTemp());
1146 if (instr
->definitions
[0].isKill() || instr
->definitions
[0].isFixed())
1148 /* collect information about affinity-related temporaries */
1149 std::vector
<Temp
> affinity_related
;
1150 /* affinity_related[0] is the last seen affinity-related temp */
1151 affinity_related
.emplace_back(instr
->definitions
[0].getTemp());
1152 affinity_related
.emplace_back(instr
->definitions
[0].getTemp());
1153 for (const Operand
& op
: instr
->operands
) {
1154 if (op
.isTemp() && op
.regClass() == instr
->definitions
[0].regClass()) {
1155 affinity_related
.emplace_back(op
.getTemp());
1156 temp_to_phi_ressources
[op
.tempId()] = phi_ressources
.size();
1159 phi_ressources
.emplace_back(std::move(affinity_related
));
1163 /* add vector affinities */
1164 if (instr
->opcode
== aco_opcode::p_create_vector
) {
1165 for (const Operand
& op
: instr
->operands
) {
1166 if (op
.isTemp() && op
.getTemp().type() == instr
->definitions
[0].getTemp().type())
1167 vectors
[op
.tempId()] = instr
.get();
1171 /* add operands to live variables */
1172 for (const Operand
& op
: instr
->operands
) {
1174 live
.emplace(op
.getTemp());
1177 /* erase definitions from live */
1178 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
1179 const Definition
& def
= instr
->definitions
[i
];
1182 live
.erase(def
.getTemp());
1183 /* mark last-seen phi operand */
1184 std::map
<unsigned, unsigned>::iterator it
= temp_to_phi_ressources
.find(def
.tempId());
1185 if (it
!= temp_to_phi_ressources
.end() && def
.regClass() == phi_ressources
[it
->second
][0].regClass()) {
1186 phi_ressources
[it
->second
][0] = def
.getTemp();
1187 /* try to coalesce phi affinities with parallelcopies */
1188 if (!def
.isFixed() && instr
->opcode
== aco_opcode::p_parallelcopy
) {
1189 Operand op
= instr
->operands
[i
];
1190 if (op
.isTemp() && op
.isFirstKill() && def
.regClass() == op
.regClass()) {
1191 phi_ressources
[it
->second
].emplace_back(op
.getTemp());
1192 temp_to_phi_ressources
[op
.tempId()] = it
->second
;
1199 /* create affinities */
1200 for (std::vector
<Temp
>& vec
: phi_ressources
) {
1201 assert(vec
.size() > 1);
1202 for (unsigned i
= 1; i
< vec
.size(); i
++)
1203 if (vec
[i
].id() != vec
[0].id())
1204 affinities
[vec
[i
].id()] = vec
[0].id();
1207 /* state of register file after phis */
1208 std::vector
<std::bitset
<128>> sgpr_live_in(program
->blocks
.size());
1210 for (Block
& block
: program
->blocks
) {
1211 std::set
<Temp
>& live
= live_out_per_block
[block
.index
];
1212 /* initialize register file */
1213 assert(block
.index
!= 0 || live
.empty());
1214 RegisterFile register_file
;
1215 ctx
.war_hint
.reset();
1217 for (Temp t
: live
) {
1218 Temp renamed
= handle_live_in(t
, &block
);
1219 if (ctx
.assignments
.find(renamed
.id()) != ctx
.assignments
.end())
1220 register_file
.fill(ctx
.assignments
[renamed
.id()].first
, t
.size(), renamed
.id());
1223 std::vector
<aco_ptr
<Instruction
>> instructions
;
1224 std::vector
<aco_ptr
<Instruction
>>::iterator it
;
1226 /* this is a slight adjustment from the paper as we already have phi nodes:
1227 * We consider them incomplete phis and only handle the definition. */
1229 /* handle fixed phi definitions */
1230 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1231 aco_ptr
<Instruction
>& phi
= *it
;
1234 Definition
& definition
= phi
->definitions
[0];
1235 if (!definition
.isFixed())
1238 /* check if a dead exec mask phi is needed */
1239 if (definition
.isKill()) {
1240 for (Operand
& op
: phi
->operands
) {
1241 assert(op
.isTemp());
1242 if (ctx
.assignments
.find(op
.tempId()) == ctx
.assignments
.end() ||
1243 ctx
.assignments
[op
.tempId()].first
!= exec
) {
1244 definition
.setKill(false);
1250 if (definition
.isKill())
1253 assert(definition
.physReg() == exec
);
1254 assert(!register_file
.test(definition
.physReg(), definition
.size()));
1255 register_file
.fill(definition
);
1256 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1259 /* look up the affinities */
1260 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1261 aco_ptr
<Instruction
>& phi
= *it
;
1264 Definition
& definition
= phi
->definitions
[0];
1265 if (definition
.isKill() || definition
.isFixed())
1268 if (affinities
.find(definition
.tempId()) != affinities
.end() &&
1269 ctx
.assignments
.find(affinities
[definition
.tempId()]) != ctx
.assignments
.end()) {
1270 assert(ctx
.assignments
[affinities
[definition
.tempId()]].second
== definition
.regClass());
1271 PhysReg reg
= ctx
.assignments
[affinities
[definition
.tempId()]].first
;
1272 bool try_use_special_reg
= reg
== scc
|| reg
== exec
;
1273 if (try_use_special_reg
) {
1274 for (const Operand
& op
: phi
->operands
) {
1276 ctx
.assignments
.find(op
.tempId()) == ctx
.assignments
.end() ||
1277 !(ctx
.assignments
[op
.tempId()].first
== reg
)) {
1278 try_use_special_reg
= false;
1282 if (!try_use_special_reg
)
1285 /* only assign if register is still free */
1286 if (!register_file
.test(reg
, definition
.size())) {
1287 definition
.setFixed(reg
);
1288 register_file
.fill(definition
);
1289 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1294 /* find registers for phis without affinity or where the register was blocked */
1295 for (it
= block
.instructions
.begin();it
!= block
.instructions
.end(); ++it
) {
1296 aco_ptr
<Instruction
>& phi
= *it
;
1300 Definition
& definition
= phi
->definitions
[0];
1301 if (definition
.isKill())
1304 renames
[block
.index
][definition
.tempId()] = definition
.getTemp();
1306 if (!definition
.isFixed()) {
1307 std::vector
<std::pair
<Operand
, Definition
>> parallelcopy
;
1308 /* try to find a register that is used by at least one operand */
1309 for (const Operand
& op
: phi
->operands
) {
1311 ctx
.assignments
.find(op
.tempId()) == ctx
.assignments
.end())
1313 PhysReg reg
= ctx
.assignments
[op
.tempId()].first
;
1314 /* we tried this already on the previous loop */
1315 if (reg
== scc
|| reg
== exec
)
1317 if (get_reg_specified(ctx
, register_file
, definition
.regClass(), parallelcopy
, phi
, reg
)) {
1318 definition
.setFixed(reg
);
1322 if (!definition
.isFixed())
1323 definition
.setFixed(get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, phi
));
1325 /* process parallelcopy */
1326 for (std::pair
<Operand
, Definition
> pc
: parallelcopy
) {
1327 /* see if it's a copy from a different phi */
1328 //TODO: prefer moving some previous phis over live-ins
1329 //TODO: somehow prevent phis fixed before the RA from being updated (shouldn't be a problem in practice since they can only be fixed to exec)
1330 Instruction
*prev_phi
= NULL
;
1331 std::vector
<aco_ptr
<Instruction
>>::iterator phi_it
;
1332 for (phi_it
= instructions
.begin(); phi_it
!= instructions
.end(); ++phi_it
) {
1333 if ((*phi_it
)->definitions
[0].tempId() == pc
.first
.tempId())
1334 prev_phi
= phi_it
->get();
1337 while (!prev_phi
&& is_phi(*++phi_it
)) {
1338 if ((*phi_it
)->definitions
[0].tempId() == pc
.first
.tempId())
1339 prev_phi
= phi_it
->get();
1342 /* if so, just update that phi's register */
1343 prev_phi
->definitions
[0].setFixed(pc
.second
.physReg());
1344 ctx
.assignments
[prev_phi
->definitions
[0].tempId()] = {pc
.second
.physReg(), pc
.second
.regClass()};
1345 register_file
.fill(pc
.second
.physReg(), pc
.second
.size(), prev_phi
->definitions
[0].tempId());
1350 std::map
<unsigned, Temp
>::iterator orig_it
= ctx
.orig_names
.find(pc
.first
.tempId());
1351 Temp orig
= pc
.first
.getTemp();
1352 if (orig_it
!= ctx
.orig_names
.end())
1353 orig
= orig_it
->second
;
1355 ctx
.orig_names
[pc
.second
.tempId()] = orig
;
1356 renames
[block
.index
][orig
.id()] = pc
.second
.getTemp();
1357 renames
[block
.index
][pc
.second
.tempId()] = pc
.second
.getTemp();
1359 /* otherwise, this is a live-in and we need to create a new phi
1360 * to move it in this block's predecessors */
1361 aco_opcode opcode
= pc
.first
.getTemp().is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
1362 std::vector
<unsigned>& preds
= pc
.first
.getTemp().is_linear() ? block
.linear_preds
: block
.logical_preds
;
1363 aco_ptr
<Instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
1364 new_phi
->definitions
[0] = pc
.second
;
1365 for (unsigned i
= 0; i
< preds
.size(); i
++)
1366 new_phi
->operands
[i
] = Operand(pc
.first
);
1367 instructions
.emplace_back(std::move(new_phi
));
1370 register_file
.fill(definition
);
1371 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1373 live
.emplace(definition
.getTemp());
1375 /* update phi affinities */
1376 for (const Operand
& op
: phi
->operands
) {
1377 if (op
.isTemp() && op
.regClass() == phi
->definitions
[0].regClass())
1378 affinities
[op
.tempId()] = definition
.tempId();
1381 instructions
.emplace_back(std::move(*it
));
1384 /* fill in sgpr_live_in */
1385 for (unsigned i
= 0; i
<= ctx
.max_used_sgpr
; i
++)
1386 sgpr_live_in
[block
.index
][i
] = register_file
[i
];
1387 sgpr_live_in
[block
.index
][127] = register_file
[scc
.reg
];
1389 /* Handle all other instructions of the block */
1390 for (; it
!= block
.instructions
.end(); ++it
) {
1391 aco_ptr
<Instruction
>& instr
= *it
;
1393 /* parallelcopies from p_phi are inserted here which means
1394 * live ranges of killed operands end here as well */
1395 if (instr
->opcode
== aco_opcode::p_logical_end
) {
1396 /* no need to process this instruction any further */
1397 if (block
.logical_succs
.size() != 1) {
1398 instructions
.emplace_back(std::move(instr
));
1402 Block
& succ
= program
->blocks
[block
.logical_succs
[0]];
1404 for (; idx
< succ
.logical_preds
.size(); idx
++) {
1405 if (succ
.logical_preds
[idx
] == block
.index
)
1408 for (aco_ptr
<Instruction
>& phi
: succ
.instructions
) {
1409 if (phi
->opcode
== aco_opcode::p_phi
) {
1410 if (phi
->operands
[idx
].isTemp() &&
1411 phi
->operands
[idx
].getTemp().type() == RegType::sgpr
&&
1412 phi
->operands
[idx
].isFirstKill()) {
1413 Temp phi_op
= read_variable(phi
->operands
[idx
].getTemp(), block
.index
);
1414 PhysReg reg
= ctx
.assignments
[phi_op
.id()].first
;
1415 assert(register_file
[reg
] == phi_op
.id());
1416 register_file
[reg
] = 0;
1418 } else if (phi
->opcode
!= aco_opcode::p_linear_phi
) {
1422 instructions
.emplace_back(std::move(instr
));
1426 std::vector
<std::pair
<Operand
, Definition
>> parallelcopy
;
1428 assert(!is_phi(instr
));
1430 /* handle operands */
1431 for (unsigned i
= 0; i
< instr
->operands
.size(); ++i
) {
1432 auto& operand
= instr
->operands
[i
];
1433 if (!operand
.isTemp())
1436 /* rename operands */
1437 operand
.setTemp(read_variable(operand
.getTemp(), block
.index
));
1439 /* check if the operand is fixed */
1440 if (operand
.isFixed()) {
1442 if (operand
.physReg() == ctx
.assignments
[operand
.tempId()].first
) {
1443 /* we are fine: the operand is already assigned the correct reg */
1446 /* check if target reg is blocked, and move away the blocking var */
1447 if (register_file
[operand
.physReg().reg
]) {
1448 uint32_t blocking_id
= register_file
[operand
.physReg().reg
];
1449 RegClass rc
= ctx
.assignments
[blocking_id
].second
;
1450 Operand pc_op
= Operand(Temp
{blocking_id
, rc
});
1451 pc_op
.setFixed(operand
.physReg());
1452 Definition pc_def
= Definition(Temp
{program
->allocateId(), pc_op
.regClass()});
1454 PhysReg reg
= get_reg(ctx
, register_file
, pc_op
.regClass(), parallelcopy
, instr
);
1455 pc_def
.setFixed(reg
);
1456 ctx
.assignments
[pc_def
.tempId()] = {reg
, pc_def
.regClass()};
1457 register_file
.clear(pc_op
);
1458 register_file
.fill(pc_def
);
1459 parallelcopy
.emplace_back(pc_op
, pc_def
);
1461 /* handle renames of previous operands */
1462 for (unsigned j
= 0; j
< i
; j
++) {
1463 Operand
& op
= instr
->operands
[j
];
1464 if (op
.isTemp() && op
.tempId() == blocking_id
) {
1465 op
.setTemp(pc_def
.getTemp());
1470 /* move operand to fixed reg and create parallelcopy pair */
1471 Operand pc_op
= operand
;
1472 Temp tmp
= Temp
{program
->allocateId(), operand
.regClass()};
1473 Definition pc_def
= Definition(tmp
);
1474 pc_def
.setFixed(operand
.physReg());
1475 pc_op
.setFixed(ctx
.assignments
[operand
.tempId()].first
);
1476 operand
.setTemp(tmp
);
1477 ctx
.assignments
[tmp
.id()] = {pc_def
.physReg(), pc_def
.regClass()};
1478 operand
.setFixed(pc_def
.physReg());
1479 register_file
.clear(pc_op
);
1480 register_file
.fill(pc_def
);
1481 parallelcopy
.emplace_back(pc_op
, pc_def
);
1484 assert(ctx
.assignments
.find(operand
.tempId()) != ctx
.assignments
.end());
1485 PhysReg reg
= ctx
.assignments
[operand
.tempId()].first
;
1487 if (operand_can_use_reg(instr
, i
, reg
)) {
1488 operand
.setFixed(ctx
.assignments
[operand
.tempId()].first
);
1490 Operand pc_op
= operand
;
1491 pc_op
.setFixed(reg
);
1492 PhysReg new_reg
= get_reg(ctx
, register_file
, operand
.regClass(), parallelcopy
, instr
);
1493 Definition pc_def
= Definition(program
->allocateId(), new_reg
, pc_op
.regClass());
1494 ctx
.assignments
[pc_def
.tempId()] = {reg
, pc_def
.regClass()};
1495 register_file
.clear(pc_op
);
1496 register_file
.fill(pc_def
);
1497 parallelcopy
.emplace_back(pc_op
, pc_def
);
1498 operand
.setFixed(new_reg
);
1501 if (instr
->format
== Format::EXP
||
1502 (instr
->isVMEM() && i
== 3 && program
->chip_class
== GFX6
) ||
1503 (instr
->format
== Format::DS
&& static_cast<DS_instruction
*>(instr
.get())->gds
)) {
1504 for (unsigned j
= 0; j
< operand
.size(); j
++)
1505 ctx
.war_hint
.set(operand
.physReg().reg
+ j
);
1508 std::map
<unsigned, phi_info
>::iterator phi
= phi_map
.find(operand
.getTemp().id());
1509 if (phi
!= phi_map
.end())
1510 phi
->second
.uses
.emplace(instr
.get());
1513 /* remove dead vars from register file */
1514 for (const Operand
& op
: instr
->operands
) {
1515 if (op
.isTemp() && op
.isFirstKill())
1516 register_file
.clear(op
);
1519 /* try to optimize v_mad_f32 -> v_mac_f32 */
1520 if (instr
->opcode
== aco_opcode::v_mad_f32
&&
1521 instr
->operands
[2].isTemp() &&
1522 instr
->operands
[2].isKill() &&
1523 instr
->operands
[2].getTemp().type() == RegType::vgpr
&&
1524 instr
->operands
[1].isTemp() &&
1525 instr
->operands
[1].getTemp().type() == RegType::vgpr
) { /* TODO: swap src0 and src1 in this case */
1526 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1527 bool can_use_mac
= !(vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1528 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1529 vop3
->clamp
|| vop3
->omod
|| vop3
->opsel
);
1531 instr
->format
= Format::VOP2
;
1532 instr
->opcode
= aco_opcode::v_mac_f32
;
1536 /* handle definitions which must have the same register as an operand */
1537 if (instr
->opcode
== aco_opcode::v_interp_p2_f32
||
1538 instr
->opcode
== aco_opcode::v_mac_f32
||
1539 instr
->opcode
== aco_opcode::v_writelane_b32
||
1540 instr
->opcode
== aco_opcode::v_writelane_b32_e64
) {
1541 instr
->definitions
[0].setFixed(instr
->operands
[2].physReg());
1542 } else if (instr
->opcode
== aco_opcode::s_addk_i32
||
1543 instr
->opcode
== aco_opcode::s_mulk_i32
) {
1544 instr
->definitions
[0].setFixed(instr
->operands
[0].physReg());
1545 } else if (instr
->format
== Format::MUBUF
&&
1546 instr
->definitions
.size() == 1 &&
1547 instr
->operands
.size() == 4) {
1548 instr
->definitions
[0].setFixed(instr
->operands
[3].physReg());
1549 } else if (instr
->format
== Format::MIMG
&&
1550 instr
->definitions
.size() == 1 &&
1551 instr
->operands
[1].regClass().type() == RegType::vgpr
) {
1552 instr
->definitions
[0].setFixed(instr
->operands
[1].physReg());
1555 ctx
.defs_done
.reset();
1557 /* handle fixed definitions first */
1558 for (unsigned i
= 0; i
< instr
->definitions
.size(); ++i
) {
1559 auto& definition
= instr
->definitions
[i
];
1560 if (!definition
.isFixed())
1563 adjust_max_used_regs(ctx
, definition
.regClass(), definition
.physReg());
1564 /* check if the target register is blocked */
1565 if (register_file
[definition
.physReg().reg
] != 0) {
1566 /* create parallelcopy pair to move blocking var */
1567 Temp tmp
= {register_file
[definition
.physReg()], ctx
.assignments
[register_file
[definition
.physReg()]].second
};
1568 Operand pc_op
= Operand(tmp
);
1569 pc_op
.setFixed(ctx
.assignments
[register_file
[definition
.physReg().reg
]].first
);
1570 RegClass rc
= pc_op
.regClass();
1571 tmp
= Temp
{program
->allocateId(), rc
};
1572 Definition pc_def
= Definition(tmp
);
1574 /* re-enable the killed operands, so that we don't move the blocking var there */
1575 for (const Operand
& op
: instr
->operands
) {
1576 if (op
.isTemp() && op
.isFirstKill())
1577 register_file
.fill(op
.physReg(), op
.size(), 0xFFFF);
1580 /* find a new register for the blocking variable */
1581 PhysReg reg
= get_reg(ctx
, register_file
, rc
, parallelcopy
, instr
);
1582 /* once again, disable killed operands */
1583 for (const Operand
& op
: instr
->operands
) {
1584 if (op
.isTemp() && op
.isFirstKill())
1585 register_file
.clear(op
);
1587 for (unsigned k
= 0; k
< i
; k
++) {
1588 if (instr
->definitions
[k
].isTemp() && ctx
.defs_done
.test(k
) && !instr
->definitions
[k
].isKill())
1589 register_file
.fill(instr
->definitions
[k
]);
1591 pc_def
.setFixed(reg
);
1593 /* finish assignment of parallelcopy */
1594 ctx
.assignments
[pc_def
.tempId()] = {reg
, pc_def
.regClass()};
1595 parallelcopy
.emplace_back(pc_op
, pc_def
);
1597 /* add changes to reg_file */
1598 register_file
.clear(pc_op
);
1599 register_file
.fill(pc_def
);
1601 ctx
.defs_done
.set(i
);
1603 if (!definition
.isTemp())
1606 /* set live if it has a kill point */
1607 if (!definition
.isKill())
1608 live
.emplace(definition
.getTemp());
1610 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1611 renames
[block
.index
][definition
.tempId()] = definition
.getTemp();
1612 register_file
.fill(definition
);
1615 /* handle all other definitions */
1616 for (unsigned i
= 0; i
< instr
->definitions
.size(); ++i
) {
1617 auto& definition
= instr
->definitions
[i
];
1619 if (definition
.isFixed() || !definition
.isTemp())
1623 if (definition
.hasHint() && register_file
[definition
.physReg().reg
] == 0)
1624 definition
.setFixed(definition
.physReg());
1625 else if (instr
->opcode
== aco_opcode::p_split_vector
) {
1626 PhysReg reg
= PhysReg
{instr
->operands
[0].physReg() + i
* definition
.size()};
1627 if (!get_reg_specified(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
, reg
))
1628 reg
= get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
);
1629 definition
.setFixed(reg
);
1630 } else if (instr
->opcode
== aco_opcode::p_wqm
) {
1632 if (instr
->operands
[0].isKill() && instr
->operands
[0].getTemp().type() == definition
.getTemp().type()) {
1633 reg
= instr
->operands
[0].physReg();
1634 assert(register_file
[reg
.reg
] == 0);
1636 reg
= get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
);
1638 definition
.setFixed(reg
);
1639 } else if (instr
->opcode
== aco_opcode::p_extract_vector
) {
1641 if (instr
->operands
[0].isKill() &&
1642 instr
->operands
[0].getTemp().type() == definition
.getTemp().type()) {
1643 reg
= instr
->operands
[0].physReg();
1644 reg
.reg
+= definition
.size() * instr
->operands
[1].constantValue();
1645 assert(register_file
[reg
.reg
] == 0);
1647 reg
= get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
);
1649 definition
.setFixed(reg
);
1650 } else if (instr
->opcode
== aco_opcode::p_create_vector
) {
1651 PhysReg reg
= get_reg_create_vector(ctx
, register_file
, definition
.regClass(),
1652 parallelcopy
, instr
);
1653 definition
.setFixed(reg
);
1654 } else if (affinities
.find(definition
.tempId()) != affinities
.end() &&
1655 ctx
.assignments
.find(affinities
[definition
.tempId()]) != ctx
.assignments
.end()) {
1656 PhysReg reg
= ctx
.assignments
[affinities
[definition
.tempId()]].first
;
1657 if (get_reg_specified(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
, reg
))
1658 definition
.setFixed(reg
);
1660 definition
.setFixed(get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
));
1662 } else if (vectors
.find(definition
.tempId()) != vectors
.end()) {
1663 Instruction
* vec
= vectors
[definition
.tempId()];
1664 unsigned offset
= 0;
1665 for (const Operand
& op
: vec
->operands
) {
1666 if (op
.isTemp() && op
.tempId() == definition
.tempId())
1669 offset
+= op
.size();
1672 for (const Operand
& op
: vec
->operands
) {
1674 op
.tempId() != definition
.tempId() &&
1675 op
.getTemp().type() == definition
.getTemp().type() &&
1676 ctx
.assignments
.find(op
.tempId()) != ctx
.assignments
.end()) {
1677 PhysReg reg
= ctx
.assignments
[op
.tempId()].first
;
1678 reg
.reg
= reg
- k
+ offset
;
1679 if (get_reg_specified(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
, reg
)) {
1680 definition
.setFixed(reg
);
1686 if (!definition
.isFixed()) {
1687 std::pair
<PhysReg
, bool> res
= get_reg_vec(ctx
, register_file
, vec
->definitions
[0].regClass());
1688 PhysReg reg
= res
.first
;
1692 reg
= get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
);
1694 definition
.setFixed(reg
);
1697 definition
.setFixed(get_reg(ctx
, register_file
, definition
.regClass(), parallelcopy
, instr
));
1699 assert(definition
.isFixed() && ((definition
.getTemp().type() == RegType::vgpr
&& definition
.physReg() >= 256) ||
1700 (definition
.getTemp().type() != RegType::vgpr
&& definition
.physReg() < 256)));
1701 ctx
.defs_done
.set(i
);
1703 /* set live if it has a kill point */
1704 if (!definition
.isKill())
1705 live
.emplace(definition
.getTemp());
1707 ctx
.assignments
[definition
.tempId()] = {definition
.physReg(), definition
.regClass()};
1708 renames
[block
.index
][definition
.tempId()] = definition
.getTemp();
1709 register_file
.fill(definition
);
1712 handle_pseudo(ctx
, register_file
, instr
.get());
1714 /* kill definitions */
1715 for (const Definition
& def
: instr
->definitions
) {
1716 if (def
.isTemp() && def
.isKill())
1717 register_file
.clear(def
);
1720 /* emit parallelcopy */
1721 if (!parallelcopy
.empty()) {
1722 aco_ptr
<Pseudo_instruction
> pc
;
1723 pc
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_parallelcopy
, Format::PSEUDO
, parallelcopy
.size(), parallelcopy
.size()));
1724 bool temp_in_scc
= register_file
[scc
.reg
];
1725 bool sgpr_operands_alias_defs
= false;
1726 uint64_t sgpr_operands
[4] = {0, 0, 0, 0};
1727 for (unsigned i
= 0; i
< parallelcopy
.size(); i
++) {
1728 if (temp_in_scc
&& parallelcopy
[i
].first
.isTemp() && parallelcopy
[i
].first
.getTemp().type() == RegType::sgpr
) {
1729 if (!sgpr_operands_alias_defs
) {
1730 unsigned reg
= parallelcopy
[i
].first
.physReg().reg
;
1731 unsigned size
= parallelcopy
[i
].first
.getTemp().size();
1732 sgpr_operands
[reg
/ 64u] |= ((1u << size
) - 1) << (reg
% 64u);
1734 reg
= parallelcopy
[i
].second
.physReg().reg
;
1735 size
= parallelcopy
[i
].second
.getTemp().size();
1736 if (sgpr_operands
[reg
/ 64u] & ((1u << size
) - 1) << (reg
% 64u))
1737 sgpr_operands_alias_defs
= true;
1741 pc
->operands
[i
] = parallelcopy
[i
].first
;
1742 pc
->definitions
[i
] = parallelcopy
[i
].second
;
1743 assert(pc
->operands
[i
].size() == pc
->definitions
[i
].size());
1745 /* it might happen that the operand is already renamed. we have to restore the original name. */
1746 std::map
<unsigned, Temp
>::iterator it
= ctx
.orig_names
.find(pc
->operands
[i
].tempId());
1747 Temp orig
= it
!= ctx
.orig_names
.end() ? it
->second
: pc
->operands
[i
].getTemp();
1748 ctx
.orig_names
[pc
->definitions
[i
].tempId()] = orig
;
1749 renames
[block
.index
][orig
.id()] = pc
->definitions
[i
].getTemp();
1750 renames
[block
.index
][pc
->definitions
[i
].tempId()] = pc
->definitions
[i
].getTemp();
1752 std::map
<unsigned, phi_info
>::iterator phi
= phi_map
.find(pc
->operands
[i
].tempId());
1753 if (phi
!= phi_map
.end())
1754 phi
->second
.uses
.emplace(pc
.get());
1757 if (temp_in_scc
&& sgpr_operands_alias_defs
) {
1758 /* disable definitions and re-enable operands */
1759 for (const Definition
& def
: instr
->definitions
) {
1760 if (def
.isTemp() && !def
.isKill())
1761 register_file
.clear(def
);
1763 for (const Operand
& op
: instr
->operands
) {
1764 if (op
.isTemp() && op
.isFirstKill())
1765 register_file
.fill(op
.physReg(), op
.size(), 0xFFFF);
1768 handle_pseudo(ctx
, register_file
, pc
.get());
1770 /* re-enable live vars */
1771 for (const Operand
& op
: instr
->operands
) {
1772 if (op
.isTemp() && op
.isFirstKill())
1773 register_file
.clear(op
);
1775 for (const Definition
& def
: instr
->definitions
) {
1776 if (def
.isTemp() && !def
.isKill())
1777 register_file
.fill(def
);
1780 pc
->tmp_in_scc
= false;
1783 instructions
.emplace_back(std::move(pc
));
1786 /* some instructions need VOP3 encoding if operand/definition is not assigned to VCC */
1787 bool instr_needs_vop3
= !instr
->isVOP3() &&
1788 ((instr
->format
== Format::VOPC
&& !(instr
->definitions
[0].physReg() == vcc
)) ||
1789 (instr
->opcode
== aco_opcode::v_cndmask_b32
&& !(instr
->operands
[2].physReg() == vcc
)) ||
1790 ((instr
->opcode
== aco_opcode::v_add_co_u32
||
1791 instr
->opcode
== aco_opcode::v_addc_co_u32
||
1792 instr
->opcode
== aco_opcode::v_sub_co_u32
||
1793 instr
->opcode
== aco_opcode::v_subb_co_u32
||
1794 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
1795 instr
->opcode
== aco_opcode::v_subbrev_co_u32
) &&
1796 !(instr
->definitions
[1].physReg() == vcc
)) ||
1797 ((instr
->opcode
== aco_opcode::v_addc_co_u32
||
1798 instr
->opcode
== aco_opcode::v_subb_co_u32
||
1799 instr
->opcode
== aco_opcode::v_subbrev_co_u32
) &&
1800 !(instr
->operands
[2].physReg() == vcc
)));
1801 if (instr_needs_vop3
) {
1803 /* if the first operand is a literal, we have to move it to a reg */
1804 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && program
->chip_class
< GFX10
) {
1805 bool can_sgpr
= true;
1806 /* check, if we have to move to vgpr */
1807 for (const Operand
& op
: instr
->operands
) {
1808 if (op
.isTemp() && op
.getTemp().type() == RegType::sgpr
) {
1813 aco_ptr
<Instruction
> mov
;
1815 mov
.reset(create_instruction
<SOP1_instruction
>(aco_opcode::s_mov_b32
, Format::SOP1
, 1, 1));
1817 mov
.reset(create_instruction
<VOP1_instruction
>(aco_opcode::v_mov_b32
, Format::VOP1
, 1, 1));
1818 mov
->operands
[0] = instr
->operands
[0];
1819 Temp tmp
= {program
->allocateId(), can_sgpr
? s1
: v1
};
1820 mov
->definitions
[0] = Definition(tmp
);
1821 /* disable definitions and re-enable operands */
1822 for (const Definition
& def
: instr
->definitions
)
1823 register_file
.clear(def
);
1824 for (const Operand
& op
: instr
->operands
) {
1825 if (op
.isTemp() && op
.isFirstKill())
1826 register_file
.fill(op
.physReg(), op
.size(), 0xFFFF);
1828 mov
->definitions
[0].setFixed(get_reg(ctx
, register_file
, tmp
.regClass(), parallelcopy
, mov
));
1829 instr
->operands
[0] = Operand(tmp
);
1830 instr
->operands
[0].setFixed(mov
->definitions
[0].physReg());
1831 instructions
.emplace_back(std::move(mov
));
1832 /* re-enable live vars */
1833 for (const Operand
& op
: instr
->operands
) {
1834 if (op
.isTemp() && op
.isFirstKill())
1835 register_file
.clear(op
);
1837 for (const Definition
& def
: instr
->definitions
) {
1838 if (def
.isTemp() && !def
.isKill())
1839 register_file
.fill(def
);
1843 /* change the instruction to VOP3 to enable an arbitrary register pair as dst */
1844 aco_ptr
<Instruction
> tmp
= std::move(instr
);
1845 Format format
= asVOP3(tmp
->format
);
1846 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
1847 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1848 Operand
& operand
= tmp
->operands
[i
];
1849 instr
->operands
[i
] = operand
;
1850 /* keep phi_map up to date */
1851 if (operand
.isTemp()) {
1852 std::map
<unsigned, phi_info
>::iterator phi
= phi_map
.find(operand
.tempId());
1853 if (phi
!= phi_map
.end()) {
1854 phi
->second
.uses
.erase(tmp
.get());
1855 phi
->second
.uses
.emplace(instr
.get());
1859 std::copy(tmp
->definitions
.begin(), tmp
->definitions
.end(), instr
->definitions
.begin());
1861 instructions
.emplace_back(std::move(*it
));
1863 } /* end for Instr */
1865 block
.instructions
= std::move(instructions
);
1867 filled
[block
.index
] = true;
1868 for (unsigned succ_idx
: block
.linear_succs
) {
1869 Block
& succ
= program
->blocks
[succ_idx
];
1870 /* seal block if all predecessors are filled */
1871 bool all_filled
= true;
1872 for (unsigned pred_idx
: succ
.linear_preds
) {
1873 if (!filled
[pred_idx
]) {
1879 /* finish incomplete phis and check if they became trivial */
1880 for (Instruction
* phi
: incomplete_phis
[succ_idx
]) {
1881 std::vector
<unsigned> preds
= phi
->definitions
[0].getTemp().is_linear() ? succ
.linear_preds
: succ
.logical_preds
;
1882 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
1883 phi
->operands
[i
].setTemp(read_variable(phi
->operands
[i
].getTemp(), preds
[i
]));
1884 phi
->operands
[i
].setFixed(ctx
.assignments
[phi
->operands
[i
].tempId()].first
);
1886 try_remove_trivial_phi(phi_map
.find(phi
->definitions
[0].tempId()));
1888 /* complete the original phi nodes, but no need to check triviality */
1889 for (aco_ptr
<Instruction
>& instr
: succ
.instructions
) {
1892 std::vector
<unsigned> preds
= instr
->opcode
== aco_opcode::p_phi
? succ
.logical_preds
: succ
.linear_preds
;
1894 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
1895 auto& operand
= instr
->operands
[i
];
1896 if (!operand
.isTemp())
1898 operand
.setTemp(read_variable(operand
.getTemp(), preds
[i
]));
1899 operand
.setFixed(ctx
.assignments
[operand
.tempId()].first
);
1900 std::map
<unsigned, phi_info
>::iterator phi
= phi_map
.find(operand
.getTemp().id());
1901 if (phi
!= phi_map
.end())
1902 phi
->second
.uses
.emplace(instr
.get());
1905 sealed
[succ_idx
] = true;
1910 /* remove trivial phis */
1911 for (Block
& block
: program
->blocks
) {
1912 auto end
= std::find_if(block
.instructions
.begin(), block
.instructions
.end(),
1913 [](aco_ptr
<Instruction
>& instr
) { return !is_phi(instr
);});
1914 auto middle
= std::remove_if(block
.instructions
.begin(), end
,
1915 [](const aco_ptr
<Instruction
>& instr
) { return instr
->definitions
.empty();});
1916 block
.instructions
.erase(middle
, end
);
1919 /* find scc spill registers which may be needed for parallelcopies created by phis */
1920 for (Block
& block
: program
->blocks
) {
1921 if (block
.linear_preds
.size() <= 1)
1924 std::bitset
<128> regs
= sgpr_live_in
[block
.index
];
1928 /* choose a register */
1930 for (; reg
< ctx
.program
->max_reg_demand
.sgpr
&& regs
[reg
]; reg
++)
1932 assert(reg
< ctx
.program
->max_reg_demand
.sgpr
);
1933 adjust_max_used_regs(ctx
, s1
, reg
);
1935 /* update predecessors */
1936 for (unsigned& pred_index
: block
.linear_preds
) {
1937 Block
& pred
= program
->blocks
[pred_index
];
1938 pred
.scc_live_out
= true;
1939 pred
.scratch_sgpr
= PhysReg
{(uint16_t)reg
};
1943 /* num_gpr = rnd_up(max_used_gpr + 1) */
1944 program
->config
->num_vgprs
= align(ctx
.max_used_vgpr
+ 1, 4);
1945 if (program
->family
== CHIP_TONGA
|| program
->family
== CHIP_ICELAND
) /* workaround hardware bug */
1946 program
->config
->num_sgprs
= get_sgpr_alloc(program
, program
->sgpr_limit
);
1948 program
->config
->num_sgprs
= align(ctx
.max_used_sgpr
+ 1 + get_extra_sgprs(program
), 8);