2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "aco_builder.h"
27 #include <unordered_set>
30 #include "vulkan/radv_shader.h" // for radv_nir_compiler_options
31 #include "amdgfxregs.h"
33 #define SMEM_WINDOW_SIZE (350 - ctx.num_waves * 35)
34 #define VMEM_WINDOW_SIZE (1024 - ctx.num_waves * 64)
35 #define POS_EXP_WINDOW_SIZE 512
36 #define SMEM_MAX_MOVES (64 - ctx.num_waves * 4)
37 #define VMEM_MAX_MOVES (128 - ctx.num_waves * 8)
38 /* creating clauses decreases def-use distances, so make it less aggressive the lower num_waves is */
39 #define VMEM_CLAUSE_MAX_GRAB_DIST ((ctx.num_waves - 1) * 8)
40 #define POS_EXP_MAX_MOVES 512
52 RegisterDemand max_registers
;
56 RegisterDemand
*register_demand
;
59 std::vector
<bool> depends_on
;
60 /* Two are needed because, for downwards VMEM scheduling, one needs to
61 * exclude the instructions in the clause, since new instructions in the
62 * clause are not moved past any other instructions in the clause. */
63 std::vector
<bool> RAR_dependencies
;
64 std::vector
<bool> RAR_dependencies_clause
;
67 int insert_idx
, insert_idx_clause
;
68 RegisterDemand total_demand
, total_demand_clause
;
70 /* for moving instructions before the current instruction to after it */
71 void downwards_init(int current_idx
, bool improved_rar
, bool may_form_clauses
);
72 MoveResult
downwards_move(bool clause
);
73 void downwards_skip();
75 /* for moving instructions after the first use of the current instruction upwards */
76 void upwards_init(int source_idx
, bool improved_rar
);
77 bool upwards_check_deps();
78 void upwards_set_insert_idx(int before
);
79 MoveResult
upwards_move();
83 void downwards_advance_helper();
88 int16_t last_SMEM_stall
;
89 int last_SMEM_dep_idx
;
93 /* This scheduler is a simple bottom-up pass based on ideas from
94 * "A Novel Lightweight Instruction Scheduling Algorithm for Just-In-Time Compiler"
95 * from Xiaohua Shi and Peng Guo.
96 * The basic approach is to iterate over all instructions. When a memory instruction
97 * is encountered it tries to move independent instructions from above and below
98 * between the memory instruction and it's first user.
99 * The novelty is that this scheduler cares for the current register pressure:
100 * Instructions will only be moved if the register pressure won't exceed a certain bound.
103 template <typename T
>
104 void move_element(T begin_it
, size_t idx
, size_t before
) {
106 auto begin
= std::next(begin_it
, idx
);
107 auto end
= std::next(begin_it
, before
);
108 std::rotate(begin
, begin
+ 1, end
);
109 } else if (idx
> before
) {
110 auto begin
= std::next(begin_it
, before
);
111 auto end
= std::next(begin_it
, idx
+ 1);
112 std::rotate(begin
, end
- 1, end
);
116 void MoveState::downwards_advance_helper()
119 total_demand
.update(register_demand
[source_idx
]);
122 void MoveState::downwards_init(int current_idx
, bool improved_rar_
, bool may_form_clauses
)
124 improved_rar
= improved_rar_
;
125 source_idx
= current_idx
;
127 insert_idx
= current_idx
+ 1;
128 insert_idx_clause
= current_idx
;
130 total_demand
= total_demand_clause
= register_demand
[current_idx
];
132 std::fill(depends_on
.begin(), depends_on
.end(), false);
134 std::fill(RAR_dependencies
.begin(), RAR_dependencies
.end(), false);
135 if (may_form_clauses
)
136 std::fill(RAR_dependencies_clause
.begin(), RAR_dependencies_clause
.end(), false);
139 for (const Operand
& op
: current
->operands
) {
141 depends_on
[op
.tempId()] = true;
142 if (improved_rar
&& op
.isFirstKill())
143 RAR_dependencies
[op
.tempId()] = true;
147 /* update total_demand/source_idx */
148 downwards_advance_helper();
151 MoveResult
MoveState::downwards_move(bool clause
)
153 aco_ptr
<Instruction
>& instr
= block
->instructions
[source_idx
];
155 for (const Definition
& def
: instr
->definitions
)
156 if (def
.isTemp() && depends_on
[def
.tempId()])
157 return move_fail_ssa
;
159 /* check if one of candidate's operands is killed by depending instruction */
160 std::vector
<bool>& RAR_deps
= improved_rar
? (clause
? RAR_dependencies_clause
: RAR_dependencies
) : depends_on
;
161 for (const Operand
& op
: instr
->operands
) {
162 if (op
.isTemp() && RAR_deps
[op
.tempId()]) {
163 // FIXME: account for difference in register pressure
164 return move_fail_rar
;
169 for (const Operand
& op
: instr
->operands
) {
171 depends_on
[op
.tempId()] = true;
172 if (op
.isFirstKill())
173 RAR_dependencies
[op
.tempId()] = true;
178 int dest_insert_idx
= clause
? insert_idx_clause
: insert_idx
;
179 RegisterDemand register_pressure
= clause
? total_demand_clause
: total_demand
;
181 const RegisterDemand candidate_diff
= get_live_changes(instr
);
182 const RegisterDemand temp
= get_temp_registers(instr
);
183 if (RegisterDemand(register_pressure
- candidate_diff
).exceeds(max_registers
))
184 return move_fail_pressure
;
185 const RegisterDemand temp2
= get_temp_registers(block
->instructions
[dest_insert_idx
- 1]);
186 const RegisterDemand new_demand
= register_demand
[dest_insert_idx
- 1] - temp2
+ temp
;
187 if (new_demand
.exceeds(max_registers
))
188 return move_fail_pressure
;
190 /* move the candidate below the memory load */
191 move_element(block
->instructions
.begin(), source_idx
, dest_insert_idx
);
193 /* update register pressure */
194 move_element(register_demand
, source_idx
, dest_insert_idx
);
195 for (int i
= source_idx
; i
< dest_insert_idx
- 1; i
++)
196 register_demand
[i
] -= candidate_diff
;
197 register_demand
[dest_insert_idx
- 1] = new_demand
;
198 total_demand_clause
-= candidate_diff
;
201 total_demand
-= candidate_diff
;
205 downwards_advance_helper();
209 void MoveState::downwards_skip()
211 aco_ptr
<Instruction
>& instr
= block
->instructions
[source_idx
];
213 for (const Operand
& op
: instr
->operands
) {
215 depends_on
[op
.tempId()] = true;
216 if (improved_rar
&& op
.isFirstKill()) {
217 RAR_dependencies
[op
.tempId()] = true;
218 RAR_dependencies_clause
[op
.tempId()] = true;
222 total_demand_clause
.update(register_demand
[source_idx
]);
224 downwards_advance_helper();
227 void MoveState::upwards_init(int source_idx_
, bool improved_rar_
)
229 source_idx
= source_idx_
;
230 improved_rar
= improved_rar_
;
234 std::fill(depends_on
.begin(), depends_on
.end(), false);
235 std::fill(RAR_dependencies
.begin(), RAR_dependencies
.end(), false);
237 for (const Definition
& def
: current
->definitions
) {
239 depends_on
[def
.tempId()] = true;
243 bool MoveState::upwards_check_deps()
245 aco_ptr
<Instruction
>& instr
= block
->instructions
[source_idx
];
246 for (const Operand
& op
: instr
->operands
) {
247 if (op
.isTemp() && depends_on
[op
.tempId()])
253 void MoveState::upwards_set_insert_idx(int before
)
256 total_demand
= register_demand
[before
- 1];
259 MoveResult
MoveState::upwards_move()
261 assert(insert_idx
>= 0);
263 aco_ptr
<Instruction
>& instr
= block
->instructions
[source_idx
];
264 for (const Operand
& op
: instr
->operands
) {
265 if (op
.isTemp() && depends_on
[op
.tempId()])
266 return move_fail_ssa
;
269 /* check if candidate uses/kills an operand which is used by a dependency */
270 for (const Operand
& op
: instr
->operands
) {
271 if (op
.isTemp() && (!improved_rar
|| op
.isFirstKill()) && RAR_dependencies
[op
.tempId()])
272 return move_fail_rar
;
275 /* check if register pressure is low enough: the diff is negative if register pressure is decreased */
276 const RegisterDemand candidate_diff
= get_live_changes(instr
);
277 const RegisterDemand temp
= get_temp_registers(instr
);
278 if (RegisterDemand(total_demand
+ candidate_diff
).exceeds(max_registers
))
279 return move_fail_pressure
;
280 const RegisterDemand temp2
= get_temp_registers(block
->instructions
[insert_idx
- 1]);
281 const RegisterDemand new_demand
= register_demand
[insert_idx
- 1] - temp2
+ candidate_diff
+ temp
;
282 if (new_demand
.exceeds(max_registers
))
283 return move_fail_pressure
;
285 /* move the candidate above the insert_idx */
286 move_element(block
->instructions
.begin(), source_idx
, insert_idx
);
288 /* update register pressure */
289 move_element(register_demand
, source_idx
, insert_idx
);
290 for (int i
= insert_idx
+ 1; i
<= source_idx
; i
++)
291 register_demand
[i
] += candidate_diff
;
292 register_demand
[insert_idx
] = new_demand
;
293 total_demand
+= candidate_diff
;
297 total_demand
.update(register_demand
[source_idx
]);
303 void MoveState::upwards_skip()
305 if (insert_idx
>= 0) {
306 aco_ptr
<Instruction
>& instr
= block
->instructions
[source_idx
];
307 for (const Definition
& def
: instr
->definitions
) {
309 depends_on
[def
.tempId()] = true;
311 for (const Operand
& op
: instr
->operands
) {
313 RAR_dependencies
[op
.tempId()] = true;
315 total_demand
.update(register_demand
[source_idx
]);
321 bool can_reorder(Instruction
* candidate
)
323 switch (candidate
->format
) {
325 return static_cast<SMEM_instruction
*>(candidate
)->can_reorder
;
327 return static_cast<MUBUF_instruction
*>(candidate
)->can_reorder
;
329 return static_cast<MIMG_instruction
*>(candidate
)->can_reorder
;
331 return static_cast<MTBUF_instruction
*>(candidate
)->can_reorder
;
334 case Format::SCRATCH
:
335 return static_cast<FLAT_instruction
*>(candidate
)->can_reorder
;
341 bool is_gs_or_done_sendmsg(Instruction
*instr
)
343 if (instr
->opcode
== aco_opcode::s_sendmsg
) {
344 uint16_t imm
= static_cast<SOPP_instruction
*>(instr
)->imm
;
345 return (imm
& sendmsg_id_mask
) == _sendmsg_gs
||
346 (imm
& sendmsg_id_mask
) == _sendmsg_gs_done
;
351 bool is_done_sendmsg(Instruction
*instr
)
353 if (instr
->opcode
== aco_opcode::s_sendmsg
) {
354 uint16_t imm
= static_cast<SOPP_instruction
*>(instr
)->imm
;
355 return (imm
& sendmsg_id_mask
) == _sendmsg_gs_done
;
360 barrier_interaction
get_barrier_interaction(Instruction
* instr
)
362 switch (instr
->format
) {
364 return static_cast<SMEM_instruction
*>(instr
)->barrier
;
366 return static_cast<MUBUF_instruction
*>(instr
)->barrier
;
368 return static_cast<MIMG_instruction
*>(instr
)->barrier
;
370 return static_cast<MTBUF_instruction
*>(instr
)->barrier
;
373 case Format::SCRATCH
:
374 return static_cast<FLAT_instruction
*>(instr
)->barrier
;
376 return barrier_shared
;
378 if (is_done_sendmsg(instr
))
379 return (barrier_interaction
)(barrier_gs_data
| barrier_gs_sendmsg
);
380 else if (is_gs_or_done_sendmsg(instr
))
381 return barrier_gs_sendmsg
;
384 case Format::PSEUDO_BARRIER
:
385 return barrier_barrier
;
391 barrier_interaction
parse_barrier(Instruction
*instr
)
393 if (instr
->format
== Format::PSEUDO_BARRIER
) {
394 switch (instr
->opcode
) {
395 case aco_opcode::p_memory_barrier_atomic
:
396 return barrier_atomic
;
397 /* For now, buffer and image barriers are treated the same. this is because of
398 * dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.buffer.guard_nonlocal.image.comp
399 * which seems to use an image load to determine if the result of a buffer load is valid. So the ordering of the two loads is important.
400 * I /think/ we should probably eventually expand the meaning of a buffer barrier so that all buffer operations before it, must stay before it
401 * and that both image and buffer operations after it, must stay after it. We should also do the same for image barriers.
402 * Or perhaps the problem is that we don't have a combined barrier instruction for both buffers and images, but the CTS test expects us to?
403 * Either way, this solution should work. */
404 case aco_opcode::p_memory_barrier_buffer
:
405 case aco_opcode::p_memory_barrier_image
:
406 return (barrier_interaction
)(barrier_image
| barrier_buffer
);
407 case aco_opcode::p_memory_barrier_shared
:
408 return barrier_shared
;
409 case aco_opcode::p_memory_barrier_common
:
410 return (barrier_interaction
)(barrier_image
| barrier_buffer
| barrier_shared
| barrier_atomic
);
411 case aco_opcode::p_memory_barrier_gs_data
:
412 return barrier_gs_data
;
413 case aco_opcode::p_memory_barrier_gs_sendmsg
:
414 return barrier_gs_sendmsg
;
418 } else if (instr
->opcode
== aco_opcode::s_barrier
) {
419 return (barrier_interaction
)(barrier_barrier
| barrier_image
| barrier_buffer
| barrier_shared
| barrier_atomic
);
424 struct hazard_query
{
427 int barrier_interaction
;
428 bool can_reorder_vmem
;
429 bool can_reorder_smem
;
432 void init_hazard_query(hazard_query
*query
) {
433 query
->contains_spill
= false;
435 query
->barrier_interaction
= 0;
436 query
->can_reorder_vmem
= true;
437 query
->can_reorder_smem
= true;
440 void add_to_hazard_query(hazard_query
*query
, Instruction
*instr
)
442 query
->barriers
|= parse_barrier(instr
);
443 query
->barrier_interaction
|= get_barrier_interaction(instr
);
444 if (instr
->opcode
== aco_opcode::p_spill
|| instr
->opcode
== aco_opcode::p_reload
)
445 query
->contains_spill
= true;
447 bool can_reorder_instr
= can_reorder(instr
);
448 query
->can_reorder_smem
&= instr
->format
!= Format::SMEM
|| can_reorder_instr
;
449 query
->can_reorder_vmem
&= !(instr
->isVMEM() || instr
->isFlatOrGlobal()) || can_reorder_instr
;
454 hazard_fail_reorder_vmem_smem
,
455 hazard_fail_reorder_ds
,
456 hazard_fail_reorder_sendmsg
,
460 /* Must stop at these failures. The hazard query code doesn't consider them
463 hazard_fail_unreorderable
,
466 HazardResult
perform_hazard_query(hazard_query
*query
, Instruction
*instr
)
468 bool can_reorder_candidate
= can_reorder(instr
);
470 if (instr
->opcode
== aco_opcode::p_exit_early_if
)
471 return hazard_fail_exec
;
472 for (const Definition
& def
: instr
->definitions
) {
473 if (def
.isFixed() && def
.physReg() == exec
)
474 return hazard_fail_exec
;
477 /* don't move exports so that they stay closer together */
478 if (instr
->format
== Format::EXP
)
479 return hazard_fail_export
;
481 /* don't move non-reorderable instructions */
482 if (instr
->opcode
== aco_opcode::s_memtime
||
483 instr
->opcode
== aco_opcode::s_memrealtime
||
484 instr
->opcode
== aco_opcode::s_setprio
)
485 return hazard_fail_unreorderable
;
487 if (query
->barrier_interaction
&& (query
->barrier_interaction
& parse_barrier(instr
)))
488 return hazard_fail_barrier
;
489 if (query
->barriers
&& (query
->barriers
& get_barrier_interaction(instr
)))
490 return hazard_fail_barrier
;
492 if (!query
->can_reorder_smem
&& instr
->format
== Format::SMEM
&& !can_reorder_candidate
)
493 return hazard_fail_reorder_vmem_smem
;
494 if (!query
->can_reorder_vmem
&& (instr
->isVMEM() || instr
->isFlatOrGlobal()) && !can_reorder_candidate
)
495 return hazard_fail_reorder_vmem_smem
;
496 if ((query
->barrier_interaction
& barrier_shared
) && instr
->format
== Format::DS
)
497 return hazard_fail_reorder_ds
;
498 if (is_gs_or_done_sendmsg(instr
) && (query
->barrier_interaction
& get_barrier_interaction(instr
)))
499 return hazard_fail_reorder_sendmsg
;
501 if ((instr
->opcode
== aco_opcode::p_spill
|| instr
->opcode
== aco_opcode::p_reload
) &&
502 query
->contains_spill
)
503 return hazard_fail_spill
;
505 return hazard_success
;
508 void schedule_SMEM(sched_ctx
& ctx
, Block
* block
,
509 std::vector
<RegisterDemand
>& register_demand
,
510 Instruction
* current
, int idx
)
513 int window_size
= SMEM_WINDOW_SIZE
;
514 int max_moves
= SMEM_MAX_MOVES
;
517 /* don't move s_memtime/s_memrealtime */
518 if (current
->opcode
== aco_opcode::s_memtime
|| current
->opcode
== aco_opcode::s_memrealtime
)
521 /* first, check if we have instructions before current to move down */
523 init_hazard_query(&hq
);
524 add_to_hazard_query(&hq
, current
);
526 ctx
.mv
.downwards_init(idx
, false, false);
528 for (int candidate_idx
= idx
- 1; k
< max_moves
&& candidate_idx
> (int) idx
- window_size
; candidate_idx
--) {
529 assert(candidate_idx
>= 0);
530 assert(candidate_idx
== ctx
.mv
.source_idx
);
531 aco_ptr
<Instruction
>& candidate
= block
->instructions
[candidate_idx
];
533 /* break if we'd make the previous SMEM instruction stall */
534 bool can_stall_prev_smem
= idx
<= ctx
.last_SMEM_dep_idx
&& candidate_idx
< ctx
.last_SMEM_dep_idx
;
535 if (can_stall_prev_smem
&& ctx
.last_SMEM_stall
>= 0)
538 /* break when encountering another MEM instruction, logical_start or barriers */
539 if (candidate
->opcode
== aco_opcode::p_logical_start
)
541 if (candidate
->isVMEM())
544 bool can_move_down
= true;
546 HazardResult haz
= perform_hazard_query(&hq
, candidate
.get());
547 if (haz
== hazard_fail_reorder_ds
|| haz
== hazard_fail_spill
|| haz
== hazard_fail_reorder_sendmsg
|| haz
== hazard_fail_barrier
|| haz
== hazard_fail_export
)
548 can_move_down
= false;
549 else if (haz
!= hazard_success
)
552 /* don't use LDS/GDS instructions to hide latency since it can
553 * significanly worsen LDS scheduling */
554 if (candidate
->format
== Format::DS
|| !can_move_down
) {
555 add_to_hazard_query(&hq
, candidate
.get());
556 ctx
.mv
.downwards_skip();
560 MoveResult res
= ctx
.mv
.downwards_move(false);
561 if (res
== move_fail_ssa
|| res
== move_fail_rar
) {
562 add_to_hazard_query(&hq
, candidate
.get());
563 ctx
.mv
.downwards_skip();
565 } else if (res
== move_fail_pressure
) {
569 if (candidate_idx
< ctx
.last_SMEM_dep_idx
)
570 ctx
.last_SMEM_stall
++;
574 /* find the first instruction depending on current or find another MEM */
575 ctx
.mv
.upwards_init(idx
+ 1, false);
577 bool found_dependency
= false;
578 /* second, check if we have instructions after current to move up */
579 for (int candidate_idx
= idx
+ 1; k
< max_moves
&& candidate_idx
< (int) idx
+ window_size
; candidate_idx
++) {
580 assert(candidate_idx
== ctx
.mv
.source_idx
);
581 assert(candidate_idx
< (int) block
->instructions
.size());
582 aco_ptr
<Instruction
>& candidate
= block
->instructions
[candidate_idx
];
584 if (candidate
->opcode
== aco_opcode::p_logical_end
)
587 /* check if candidate depends on current */
588 bool is_dependency
= !found_dependency
&& !ctx
.mv
.upwards_check_deps();
589 /* no need to steal from following VMEM instructions */
590 if (is_dependency
&& candidate
->isVMEM())
593 if (found_dependency
) {
594 HazardResult haz
= perform_hazard_query(&hq
, candidate
.get());
595 if (haz
== hazard_fail_reorder_ds
|| haz
== hazard_fail_spill
||
596 haz
== hazard_fail_reorder_sendmsg
|| haz
== hazard_fail_barrier
||
597 haz
== hazard_fail_export
)
598 is_dependency
= true;
599 else if (haz
!= hazard_success
)
604 if (!found_dependency
) {
605 ctx
.mv
.upwards_set_insert_idx(candidate_idx
);
606 init_hazard_query(&hq
);
607 found_dependency
= true;
611 if (is_dependency
|| !found_dependency
) {
612 if (found_dependency
)
613 add_to_hazard_query(&hq
, candidate
.get());
616 ctx
.mv
.upwards_skip();
620 MoveResult res
= ctx
.mv
.upwards_move();
621 if (res
== move_fail_ssa
|| res
== move_fail_rar
) {
622 /* no need to steal from following VMEM instructions */
623 if (res
== move_fail_ssa
&& candidate
->isVMEM())
625 add_to_hazard_query(&hq
, candidate
.get());
626 ctx
.mv
.upwards_skip();
628 } else if (res
== move_fail_pressure
) {
634 ctx
.last_SMEM_dep_idx
= found_dependency
? ctx
.mv
.insert_idx
: 0;
635 ctx
.last_SMEM_stall
= 10 - ctx
.num_waves
- k
;
638 void schedule_VMEM(sched_ctx
& ctx
, Block
* block
,
639 std::vector
<RegisterDemand
>& register_demand
,
640 Instruction
* current
, int idx
)
643 int window_size
= VMEM_WINDOW_SIZE
;
644 int max_moves
= VMEM_MAX_MOVES
;
645 int clause_max_grab_dist
= VMEM_CLAUSE_MAX_GRAB_DIST
;
648 /* first, check if we have instructions before current to move down */
649 hazard_query indep_hq
;
650 hazard_query clause_hq
;
651 init_hazard_query(&indep_hq
);
652 init_hazard_query(&clause_hq
);
653 add_to_hazard_query(&indep_hq
, current
);
655 ctx
.mv
.downwards_init(idx
, true, true);
657 for (int candidate_idx
= idx
- 1; k
< max_moves
&& candidate_idx
> (int) idx
- window_size
; candidate_idx
--) {
658 assert(candidate_idx
== ctx
.mv
.source_idx
);
659 assert(candidate_idx
>= 0);
660 aco_ptr
<Instruction
>& candidate
= block
->instructions
[candidate_idx
];
661 bool is_vmem
= candidate
->isVMEM() || candidate
->isFlatOrGlobal();
663 /* break when encountering another VMEM instruction, logical_start or barriers */
664 if (candidate
->opcode
== aco_opcode::p_logical_start
)
667 /* break if we'd make the previous SMEM instruction stall */
668 bool can_stall_prev_smem
= idx
<= ctx
.last_SMEM_dep_idx
&& candidate_idx
< ctx
.last_SMEM_dep_idx
;
669 if (can_stall_prev_smem
&& ctx
.last_SMEM_stall
>= 0)
672 bool part_of_clause
= false;
673 if (current
->isVMEM() == candidate
->isVMEM()) {
674 bool same_resource
= true;
675 if (current
->isVMEM())
676 same_resource
= candidate
->operands
[0].tempId() == current
->operands
[0].tempId();
677 int grab_dist
= ctx
.mv
.insert_idx_clause
- candidate_idx
;
678 /* We can't easily tell how much this will decrease the def-to-use
679 * distances, so just use how far it will be moved as a heuristic. */
680 part_of_clause
= same_resource
&& grab_dist
< clause_max_grab_dist
;
683 /* if current depends on candidate, add additional dependencies and continue */
684 bool can_move_down
= !is_vmem
|| part_of_clause
;
686 HazardResult haz
= perform_hazard_query(part_of_clause
? &clause_hq
: &indep_hq
, candidate
.get());
687 if (haz
== hazard_fail_reorder_ds
|| haz
== hazard_fail_spill
||
688 haz
== hazard_fail_reorder_sendmsg
|| haz
== hazard_fail_barrier
||
689 haz
== hazard_fail_export
)
690 can_move_down
= false;
691 else if (haz
!= hazard_success
)
694 if (!can_move_down
) {
695 add_to_hazard_query(&indep_hq
, candidate
.get());
696 add_to_hazard_query(&clause_hq
, candidate
.get());
697 ctx
.mv
.downwards_skip();
701 MoveResult res
= ctx
.mv
.downwards_move(part_of_clause
);
702 if (res
== move_fail_ssa
|| res
== move_fail_rar
) {
703 add_to_hazard_query(&indep_hq
, candidate
.get());
704 add_to_hazard_query(&clause_hq
, candidate
.get());
705 ctx
.mv
.downwards_skip();
707 } else if (res
== move_fail_pressure
) {
711 if (candidate_idx
< ctx
.last_SMEM_dep_idx
)
712 ctx
.last_SMEM_stall
++;
715 /* find the first instruction depending on current or find another VMEM */
716 ctx
.mv
.upwards_init(idx
+ 1, true);
718 bool found_dependency
= false;
719 /* second, check if we have instructions after current to move up */
720 for (int candidate_idx
= idx
+ 1; k
< max_moves
&& candidate_idx
< (int) idx
+ window_size
; candidate_idx
++) {
721 assert(candidate_idx
== ctx
.mv
.source_idx
);
722 assert(candidate_idx
< (int) block
->instructions
.size());
723 aco_ptr
<Instruction
>& candidate
= block
->instructions
[candidate_idx
];
724 bool is_vmem
= candidate
->isVMEM() || candidate
->isFlatOrGlobal();
726 if (candidate
->opcode
== aco_opcode::p_logical_end
)
729 /* check if candidate depends on current */
730 bool is_dependency
= false;
731 if (found_dependency
) {
732 HazardResult haz
= perform_hazard_query(&indep_hq
, candidate
.get());
733 if (haz
== hazard_fail_reorder_ds
|| haz
== hazard_fail_spill
||
734 haz
== hazard_fail_reorder_vmem_smem
|| haz
== hazard_fail_reorder_sendmsg
||
735 haz
== hazard_fail_barrier
|| haz
== hazard_fail_export
)
736 is_dependency
= true;
737 else if (haz
!= hazard_success
)
741 is_dependency
|= !found_dependency
&& !ctx
.mv
.upwards_check_deps();
743 if (!found_dependency
) {
744 ctx
.mv
.upwards_set_insert_idx(candidate_idx
);
745 init_hazard_query(&indep_hq
);
746 found_dependency
= true;
748 } else if (is_vmem
) {
749 /* don't move up dependencies of other VMEM instructions */
750 for (const Definition
& def
: candidate
->definitions
) {
752 ctx
.mv
.depends_on
[def
.tempId()] = true;
756 if (is_dependency
|| !found_dependency
) {
757 if (found_dependency
)
758 add_to_hazard_query(&indep_hq
, candidate
.get());
759 ctx
.mv
.upwards_skip();
763 MoveResult res
= ctx
.mv
.upwards_move();
764 if (res
== move_fail_ssa
|| res
== move_fail_rar
) {
765 add_to_hazard_query(&indep_hq
, candidate
.get());
766 ctx
.mv
.upwards_skip();
768 } else if (res
== move_fail_pressure
) {
775 void schedule_position_export(sched_ctx
& ctx
, Block
* block
,
776 std::vector
<RegisterDemand
>& register_demand
,
777 Instruction
* current
, int idx
)
780 int window_size
= POS_EXP_WINDOW_SIZE
;
781 int max_moves
= POS_EXP_MAX_MOVES
;
784 ctx
.mv
.downwards_init(idx
, true, false);
787 init_hazard_query(&hq
);
788 add_to_hazard_query(&hq
, current
);
790 for (int candidate_idx
= idx
- 1; k
< max_moves
&& candidate_idx
> (int) idx
- window_size
; candidate_idx
--) {
791 assert(candidate_idx
>= 0);
792 aco_ptr
<Instruction
>& candidate
= block
->instructions
[candidate_idx
];
794 if (candidate
->opcode
== aco_opcode::p_logical_start
)
796 if (candidate
->isVMEM() || candidate
->format
== Format::SMEM
|| candidate
->isFlatOrGlobal())
799 HazardResult haz
= perform_hazard_query(&hq
, candidate
.get());
800 if (haz
== hazard_fail_exec
|| haz
== hazard_fail_unreorderable
)
803 if (haz
!= hazard_success
) {
804 add_to_hazard_query(&hq
, candidate
.get());
805 ctx
.mv
.downwards_skip();
809 MoveResult res
= ctx
.mv
.downwards_move(false);
810 if (res
== move_fail_ssa
|| res
== move_fail_rar
) {
811 add_to_hazard_query(&hq
, candidate
.get());
812 ctx
.mv
.downwards_skip();
814 } else if (res
== move_fail_pressure
) {
821 void schedule_block(sched_ctx
& ctx
, Program
*program
, Block
* block
, live
& live_vars
)
823 ctx
.last_SMEM_dep_idx
= 0;
824 ctx
.last_SMEM_stall
= INT16_MIN
;
825 ctx
.mv
.block
= block
;
826 ctx
.mv
.register_demand
= live_vars
.register_demand
[block
->index
].data();
828 /* go through all instructions and find memory loads */
829 for (unsigned idx
= 0; idx
< block
->instructions
.size(); idx
++) {
830 Instruction
* current
= block
->instructions
[idx
].get();
832 if (current
->definitions
.empty())
835 if (current
->isVMEM() || current
->isFlatOrGlobal()) {
836 ctx
.mv
.current
= current
;
837 schedule_VMEM(ctx
, block
, live_vars
.register_demand
[block
->index
], current
, idx
);
840 if (current
->format
== Format::SMEM
) {
841 ctx
.mv
.current
= current
;
842 schedule_SMEM(ctx
, block
, live_vars
.register_demand
[block
->index
], current
, idx
);
846 if ((program
->stage
& (hw_vs
| hw_ngg_gs
)) && (block
->kind
& block_kind_export_end
)) {
847 /* Try to move position exports as far up as possible, to reduce register
848 * usage and because ISA reference guides say so. */
849 for (unsigned idx
= 0; idx
< block
->instructions
.size(); idx
++) {
850 Instruction
* current
= block
->instructions
[idx
].get();
852 if (current
->format
== Format::EXP
) {
853 unsigned target
= static_cast<Export_instruction
*>(current
)->dest
;
854 if (target
>= V_008DFC_SQ_EXP_POS
&& target
< V_008DFC_SQ_EXP_PARAM
) {
855 ctx
.mv
.current
= current
;
856 schedule_position_export(ctx
, block
, live_vars
.register_demand
[block
->index
], current
, idx
);
862 /* resummarize the block's register demand */
863 block
->register_demand
= RegisterDemand();
864 for (unsigned idx
= 0; idx
< block
->instructions
.size(); idx
++) {
865 block
->register_demand
.update(live_vars
.register_demand
[block
->index
][idx
]);
870 void schedule_program(Program
*program
, live
& live_vars
)
873 ctx
.mv
.depends_on
.resize(program
->peekAllocationId());
874 ctx
.mv
.RAR_dependencies
.resize(program
->peekAllocationId());
875 ctx
.mv
.RAR_dependencies_clause
.resize(program
->peekAllocationId());
876 /* Allowing the scheduler to reduce the number of waves to as low as 5
877 * improves performance of Thrones of Britannia significantly and doesn't
878 * seem to hurt anything else. */
879 if (program
->num_waves
<= 5)
880 ctx
.num_waves
= program
->num_waves
;
881 else if (program
->max_reg_demand
.vgpr
>= 32)
883 else if (program
->max_reg_demand
.vgpr
>= 28)
885 else if (program
->max_reg_demand
.vgpr
>= 24)
889 ctx
.num_waves
= std::max
<uint16_t>(ctx
.num_waves
, program
->min_waves
);
891 assert(ctx
.num_waves
> 0 && ctx
.num_waves
<= program
->num_waves
);
892 ctx
.mv
.max_registers
= { int16_t(get_addr_vgpr_from_waves(program
, ctx
.num_waves
) - 2),
893 int16_t(get_addr_sgpr_from_waves(program
, ctx
.num_waves
))};
895 for (Block
& block
: program
->blocks
)
896 schedule_block(ctx
, program
, &block
, live_vars
);
898 /* update max_reg_demand and num_waves */
899 RegisterDemand new_demand
;
900 for (Block
& block
: program
->blocks
) {
901 new_demand
.update(block
.register_demand
);
903 update_vgpr_sgpr_demand(program
, new_demand
);
905 /* if enabled, this code asserts that register_demand is updated correctly */
907 int prev_num_waves
= program
->num_waves
;
908 const RegisterDemand prev_max_demand
= program
->max_reg_demand
;
910 std::vector
<RegisterDemand
> demands(program
->blocks
.size());
911 for (unsigned j
= 0; j
< program
->blocks
.size(); j
++) {
912 demands
[j
] = program
->blocks
[j
].register_demand
;
915 struct radv_nir_compiler_options options
;
916 options
.chip_class
= program
->chip_class
;
917 live live_vars2
= aco::live_var_analysis(program
, &options
);
919 for (unsigned j
= 0; j
< program
->blocks
.size(); j
++) {
920 Block
&b
= program
->blocks
[j
];
921 for (unsigned i
= 0; i
< b
.instructions
.size(); i
++)
922 assert(live_vars
.register_demand
[b
.index
][i
] == live_vars2
.register_demand
[b
.index
][i
]);
923 assert(b
.register_demand
== demands
[j
]);
926 assert(program
->max_reg_demand
== prev_max_demand
);
927 assert(program
->num_waves
== prev_num_waves
);