src/amd/compiler/aco_validate.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "aco_ir.h"
  26
  27 #include <array>
  28 #include <map>
  29
  30 namespace aco {
  31
  32 #ifndef NDEBUG
  33 void perfwarn(bool cond, const char *msg, Instruction *instr)
  34 {
  35    if (cond) {
  36       fprintf(stderr, "ACO performance warning: %s\n", msg);
  37       if (instr) {
  38          fprintf(stderr, "instruction: ");
  39          aco_print_instr(instr, stderr);
  40          fprintf(stderr, "\n");
  41       }
  42
  43       if (debug_flags & DEBUG_PERFWARN)
  44          exit(1);
  45    }
  46 }
  47 #endif
  48
  49 void validate(Program* program, FILE * output)
  50 {
  51    if (!(debug_flags & DEBUG_VALIDATE))
  52       return;
  53
  54    bool is_valid = true;
  55    auto check = [&output, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void {
  56       if (!check) {
  57          fprintf(output, "%s: ", msg);
  58          aco_print_instr(instr, output);
  59          fprintf(output, "\n");
  60          is_valid = false;
  61       }
  62    };
  63    auto check_block = [&output, &is_valid](bool check, const char * msg, aco::Block * block) -> void {
  64       if (!check) {
  65          fprintf(output, "%s: BB%u\n", msg, block->index);
  66          is_valid = false;
  67       }
  68    };
  69
  70    for (Block& block : program->blocks) {
  71       for (aco_ptr<Instruction>& instr : block.instructions) {
  72
  73          /* check base format */
  74          Format base_format = instr->format;
  75          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::SDWA);
  76          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::DPP);
  77          if ((uint32_t)base_format & (uint32_t)Format::VOP1)
  78             base_format = Format::VOP1;
  79          else if ((uint32_t)base_format & (uint32_t)Format::VOP2)
  80             base_format = Format::VOP2;
  81          else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
  82             base_format = Format::VOPC;
  83          else if ((uint32_t)base_format & (uint32_t)Format::VINTRP)
  84             base_format = Format::VINTRP;
  85          check(base_format == instr_info.format[(int)instr->opcode], "Wrong base format for instruction", instr.get());
  86
  87          /* check VOP3 modifiers */
  88          if (((uint32_t)instr->format & (uint32_t)Format::VOP3) && instr->format != Format::VOP3) {
  89             check(base_format == Format::VOP2 ||
  90                   base_format == Format::VOP1 ||
  91                   base_format == Format::VOPC ||
  92                   base_format == Format::VINTRP,
  93                   "Format cannot have VOP3A/VOP3B applied", instr.get());
  94          }
  95
  96          /* check SDWA */
  97          if (instr->isSDWA()) {
  98             check(base_format == Format::VOP2 ||
  99                   base_format == Format::VOP1 ||
 100                   base_format == Format::VOPC,
 101                   "Format cannot have SDWA applied", instr.get());
 102
 103             check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
 104
 105             SDWA_instruction *sdwa = static_cast<SDWA_instruction*>(instr.get());
 106             check(sdwa->omod == 0 || program->chip_class >= GFX9, "SDWA omod only supported on GFX9+", instr.get());
 107             if (base_format == Format::VOPC) {
 108                check(sdwa->clamp == false || program->chip_class == GFX8, "SDWA VOPC clamp only supported on GFX8", instr.get());
 109                check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
 110                      program->chip_class >= GFX9,
 111                      "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
 112             }
 113
 114             if (instr->operands.size() >= 3) {
 115                check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
 116                      "3rd operand must be fixed to vcc with SDWA", instr.get());
 117             }
 118             if (instr->definitions.size() >= 2) {
 119                check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
 120                      "2nd definition must be fixed to vcc with SDWA", instr.get());
 121             }
 122
 123             check(instr->opcode != aco_opcode::v_madmk_f32 &&
 124                   instr->opcode != aco_opcode::v_madak_f32 &&
 125                   instr->opcode != aco_opcode::v_madmk_f16 &&
 126                   instr->opcode != aco_opcode::v_madak_f16 &&
 127                   instr->opcode != aco_opcode::v_readfirstlane_b32 &&
 128                   instr->opcode != aco_opcode::v_clrexcp &&
 129                   instr->opcode != aco_opcode::v_swap_b32,
 130                   "SDWA can't be used with this opcode", instr.get());
 131             if (program->chip_class != GFX8) {
 132                check(instr->opcode != aco_opcode::v_mac_f32 &&
 133                      instr->opcode != aco_opcode::v_mac_f16 &&
 134                      instr->opcode != aco_opcode::v_fmac_f32 &&
 135                      instr->opcode != aco_opcode::v_fmac_f16,
 136                      "SDWA can't be used with this opcode", instr.get());
 137             }
 138          }
 139
 140          /* check opsel */
 141          if (instr->isVOP3()) {
 142             VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
 143             check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get());
 144             check((vop3->opsel & ~(0x10 | ((1 << instr->operands.size()) - 1))) == 0, "Unused bits in opsel must be zeroed out", instr.get());
 145          }
 146
 147          /* check for undefs */
 148          for (unsigned i = 0; i < instr->operands.size(); i++) {
 149             if (instr->operands[i].isUndefined()) {
 150                bool flat = instr->format == Format::FLAT || instr->format == Format::SCRATCH || instr->format == Format::GLOBAL;
 151                bool can_be_undef = is_phi(instr) || instr->format == Format::EXP ||
 152                                    instr->format == Format::PSEUDO_REDUCTION ||
 153                                    instr->opcode == aco_opcode::p_create_vector ||
 154                                    (flat && i == 1) || (instr->format == Format::MIMG && i == 1) ||
 155                                    ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1);
 156                check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
 157             }
 158          }
 159
 160          /* check subdword definitions */
 161          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 162             if (instr->definitions[i].regClass().is_subdword())
 163                check(instr->isSDWA() || instr->format == Format::PSEUDO, "Only SDWA and Pseudo instructions can write subdword registers", instr.get());
 164          }
 165
 166          if (instr->isSALU() || instr->isVALU()) {
 167             /* check literals */
 168             Operand literal(s1);
 169             for (unsigned i = 0; i < instr->operands.size(); i++)
 170             {
 171                Operand op = instr->operands[i];
 172                if (!op.isLiteral())
 173                   continue;
 174
 175                check(instr->format == Format::SOP1 ||
 176                      instr->format == Format::SOP2 ||
 177                      instr->format == Format::SOPC ||
 178                      instr->format == Format::VOP1 ||
 179                      instr->format == Format::VOP2 ||
 180                      instr->format == Format::VOPC ||
 181                      (instr->isVOP3() && program->chip_class >= GFX10),
 182                      "Literal applied on wrong instruction format", instr.get());
 183
 184                check(literal.isUndefined() || (literal.size() == op.size() && literal.constantValue() == op.constantValue()), "Only 1 Literal allowed", instr.get());
 185                literal = op;
 186                check(!instr->isVALU() || instr->isVOP3() || i == 0 || i == 2, "Wrong source position for Literal argument", instr.get());
 187             }
 188
 189             /* check num sgprs for VALU */
 190             if (instr->isVALU()) {
 191                bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
 192                                  instr->opcode == aco_opcode::v_lshrrev_b64 ||
 193                                  instr->opcode == aco_opcode::v_ashrrev_i64;
 194                unsigned const_bus_limit = 1;
 195                if (program->chip_class >= GFX10 && !is_shift64)
 196                   const_bus_limit = 2;
 197
 198                uint32_t scalar_mask = instr->isVOP3() ? 0x7 : 0x5;
 199                if (instr->isSDWA())
 200                   scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4;
 201
 202                check(instr->definitions[0].getTemp().type() == RegType::vgpr ||
 203                      (int) instr->format & (int) Format::VOPC ||
 204                      instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 205                      instr->opcode == aco_opcode::v_readlane_b32 ||
 206                      instr->opcode == aco_opcode::v_readlane_b32_e64,
 207                      "Wrong Definition type for VALU instruction", instr.get());
 208                unsigned num_sgprs = 0;
 209                unsigned sgpr[] = {0, 0};
 210                for (unsigned i = 0; i < instr->operands.size(); i++)
 211                {
 212                   Operand op = instr->operands[i];
 213                   if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 214                       instr->opcode == aco_opcode::v_readlane_b32 ||
 215                       instr->opcode == aco_opcode::v_readlane_b32_e64 ||
 216                       instr->opcode == aco_opcode::v_writelane_b32 ||
 217                       instr->opcode == aco_opcode::v_writelane_b32_e64) {
 218                      check(!op.isLiteral(), "No literal allowed on VALU instruction", instr.get());
 219                      check(i == 1 || (op.isTemp() && op.regClass() == v1), "Wrong Operand type for VALU instruction", instr.get());
 220                      continue;
 221                   }
 222                   if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
 223                      check(scalar_mask & (1 << i), "Wrong source position for SGPR argument", instr.get());
 224
 225                      if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
 226                         if (num_sgprs < 2)
 227                            sgpr[num_sgprs++] = op.tempId();
 228                      }
 229                   }
 230
 231                   if (op.isConstant() && !op.isLiteral())
 232                      check(scalar_mask & (1 << i), "Wrong source position for constant argument", instr.get());
 233                }
 234                check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, "Too many SGPRs/literals", instr.get());
 235             }
 236
 237             if (instr->format == Format::SOP1 || instr->format == Format::SOP2) {
 238                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "Wrong Definition type for SALU instruction", instr.get());
 239                for (const Operand& op : instr->operands) {
 240                  check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
 241                        "Wrong Operand type for SALU instruction", instr.get());
 242             }
 243          }
 244          }
 245
 246          switch (instr->format) {
 247          case Format::PSEUDO: {
 248             if (instr->opcode == aco_opcode::p_create_vector) {
 249                unsigned size = 0;
 250                for (const Operand& op : instr->operands) {
 251                   size += op.bytes();
 252                }
 253                check(size == instr->definitions[0].bytes(), "Definition size does not match operand sizes", instr.get());
 254                if (instr->definitions[0].getTemp().type() == RegType::sgpr) {
 255                   for (const Operand& op : instr->operands) {
 256                      check(op.isConstant() || op.regClass().type() == RegType::sgpr,
 257                            "Wrong Operand type for scalar vector", instr.get());
 258                   }
 259                }
 260             } else if (instr->opcode == aco_opcode::p_extract_vector) {
 261                check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(), "Wrong Operand types", instr.get());
 262                check(instr->operands[1].constantValue() < instr->operands[0].size(), "Index out of range", instr.get());
 263                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr,
 264                      "Cannot extract SGPR value from VGPR vector", instr.get());
 265             } else if (instr->opcode == aco_opcode::p_parallelcopy) {
 266                check(instr->definitions.size() == instr->operands.size(), "Number of Operands does not match number of Definitions", instr.get());
 267                for (unsigned i = 0; i < instr->operands.size(); i++) {
 268                   if (instr->operands[i].isTemp())
 269                      check((instr->definitions[i].getTemp().type() == instr->operands[i].regClass().type()) ||
 270                            (instr->definitions[i].getTemp().type() == RegType::vgpr && instr->operands[i].regClass().type() == RegType::sgpr),
 271                            "Operand and Definition types do not match", instr.get());
 272                }
 273             } else if (instr->opcode == aco_opcode::p_phi) {
 274                check(instr->operands.size() == block.logical_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 275                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->definitions[0].getTemp().regClass() == program->lane_mask, "Logical Phi Definition must be vgpr or divergent boolean", instr.get());
 276             } else if (instr->opcode == aco_opcode::p_linear_phi) {
 277                for (const Operand& op : instr->operands)
 278                   check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type", instr.get());
 279                check(instr->operands.size() == block.linear_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 280             }
 281             break;
 282          }
 283          case Format::SMEM: {
 284             if (instr->operands.size() >= 1)
 285                check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "SMEM operands must be sgpr", instr.get());
 286             if (instr->operands.size() >= 2)
 287                check(instr->operands[1].isConstant() || (instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr),
 288                      "SMEM offset must be constant or sgpr", instr.get());
 289             if (!instr->definitions.empty())
 290                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "SMEM result must be sgpr", instr.get());
 291             break;
 292          }
 293          case Format::MTBUF:
 294          case Format::MUBUF: {
 295             check(instr->operands.size() > 1, "VMEM instructions must have at least one operand", instr.get());
 296             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr,
 297                   "VADDR must be in vgpr for VMEM instructions", instr.get());
 298             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "VMEM resource constant must be sgpr", instr.get());
 299             check(instr->operands.size() < 4 || (instr->operands[3].isTemp() && instr->operands[3].regClass().type() == RegType::vgpr), "VMEM write data must be vgpr", instr.get());
 300             break;
 301          }
 302          case Format::MIMG: {
 303             check(instr->operands.size() == 3, "MIMG instructions must have exactly 3 operands", instr.get());
 304             check(instr->operands[0].hasRegClass() && (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
 305                   "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
 306             if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr)
 307                check(instr->operands[1].regClass() == s4, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
 308             else if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr)
 309                check((instr->definitions.empty() || instr->definitions[0].regClass() == instr->operands[1].regClass() ||
 310                      instr->opcode == aco_opcode::image_atomic_cmpswap || instr->opcode == aco_opcode::image_atomic_fcmpswap),
 311                      "MIMG operands[1] (VDATA) must be the same as definitions[0] for atomics", instr.get());
 312             check(instr->operands[2].hasRegClass() && instr->operands[2].regClass().type() == RegType::vgpr,
 313                   "MIMG operands[2] (VADDR) must be VGPR", instr.get());
 314             check(instr->definitions.empty() || (instr->definitions[0].isTemp() && instr->definitions[0].regClass().type() == RegType::vgpr),
 315                   "MIMG definitions[0] (VDATA) must be VGPR", instr.get());
 316             break;
 317          }
 318          case Format::DS: {
 319             for (const Operand& op : instr->operands) {
 320                check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
 321                      "Only VGPRs are valid DS instruction operands", instr.get());
 322             }
 323             if (!instr->definitions.empty())
 324                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "DS instruction must return VGPR", instr.get());
 325             break;
 326          }
 327          case Format::EXP: {
 328             for (unsigned i = 0; i < 4; i++)
 329                check(instr->operands[i].hasRegClass() && instr->operands[i].regClass().type() == RegType::vgpr,
 330                      "Only VGPRs are valid Export arguments", instr.get());
 331             break;
 332          }
 333          case Format::FLAT:
 334             check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR", instr.get());
 335             /* fallthrough */
 336          case Format::GLOBAL:
 337          case Format::SCRATCH: {
 338             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH address must be vgpr", instr.get());
 339             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr,
 340                   "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr.get());
 341             if (!instr->definitions.empty())
 342                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH result must be vgpr", instr.get());
 343             else
 344                check(instr->operands[2].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH data must be vgpr", instr.get());
 345             break;
 346          }
 347          default:
 348             break;
 349          }
 350       }
 351    }
 352
 353    /* validate CFG */
 354    for (unsigned i = 0; i < program->blocks.size(); i++) {
 355       Block& block = program->blocks[i];
 356       check_block(block.index == i, "block.index must match actual index", &block);
 357
 358       /* predecessors/successors should be sorted */
 359       for (unsigned j = 0; j + 1 < block.linear_preds.size(); j++)
 360          check_block(block.linear_preds[j] < block.linear_preds[j + 1], "linear predecessors must be sorted", &block);
 361       for (unsigned j = 0; j + 1 < block.logical_preds.size(); j++)
 362          check_block(block.logical_preds[j] < block.logical_preds[j + 1], "logical predecessors must be sorted", &block);
 363       for (unsigned j = 0; j + 1 < block.linear_succs.size(); j++)
 364          check_block(block.linear_succs[j] < block.linear_succs[j + 1], "linear successors must be sorted", &block);
 365       for (unsigned j = 0; j + 1 < block.logical_succs.size(); j++)
 366          check_block(block.logical_succs[j] < block.logical_succs[j + 1], "logical successors must be sorted", &block);
 367
 368       /* critical edges are not allowed */
 369       if (block.linear_preds.size() > 1) {
 370          for (unsigned pred : block.linear_preds)
 371             check_block(program->blocks[pred].linear_succs.size() == 1, "linear critical edges are not allowed", &program->blocks[pred]);
 372          for (unsigned pred : block.logical_preds)
 373             check_block(program->blocks[pred].logical_succs.size() == 1, "logical critical edges are not allowed", &program->blocks[pred]);
 374       }
 375    }
 376
 377    assert(is_valid);
 378 }
 379
 380 /* RA validation */
 381 namespace {
 382
 383 struct Location {
 384    Location() : block(NULL), instr(NULL) {}
 385
 386    Block *block;
 387    Instruction *instr; //NULL if it's the block's live-in
 388 };
 389
 390 struct Assignment {
 391    Location defloc;
 392    Location firstloc;
 393    PhysReg reg;
 394 };
 395
 396 bool ra_fail(FILE *output, Location loc, Location loc2, const char *fmt, ...) {
 397    va_list args;
 398    va_start(args, fmt);
 399    char msg[1024];
 400    vsprintf(msg, fmt, args);
 401    va_end(args);
 402
 403    fprintf(stderr, "RA error found at instruction in BB%d:\n", loc.block->index);
 404    if (loc.instr) {
 405       aco_print_instr(loc.instr, stderr);
 406       fprintf(stderr, "\n%s", msg);
 407    } else {
 408       fprintf(stderr, "%s", msg);
 409    }
 410    if (loc2.block) {
 411       fprintf(stderr, " in BB%d:\n", loc2.block->index);
 412       aco_print_instr(loc2.instr, stderr);
 413    }
 414    fprintf(stderr, "\n\n");
 415
 416    return true;
 417 }
 418
 419 } /* end namespace */
 420
 421 bool validate_ra(Program *program, const struct radv_nir_compiler_options *options, FILE *output) {
 422    if (!(debug_flags & DEBUG_VALIDATE_RA))
 423       return false;
 424
 425    bool err = false;
 426    aco::live live_vars = aco::live_var_analysis(program, options);
 427    std::vector<std::vector<Temp>> phi_sgpr_ops(program->blocks.size());
 428
 429    std::map<unsigned, Assignment> assignments;
 430    for (Block& block : program->blocks) {
 431       Location loc;
 432       loc.block = &block;
 433       for (aco_ptr<Instruction>& instr : block.instructions) {
 434          if (instr->opcode == aco_opcode::p_phi) {
 435             for (unsigned i = 0; i < instr->operands.size(); i++) {
 436                if (instr->operands[i].isTemp() &&
 437                    instr->operands[i].getTemp().type() == RegType::sgpr &&
 438                    instr->operands[i].isFirstKill())
 439                   phi_sgpr_ops[block.logical_preds[i]].emplace_back(instr->operands[i].getTemp());
 440             }
 441          }
 442
 443          loc.instr = instr.get();
 444          for (unsigned i = 0; i < instr->operands.size(); i++) {
 445             Operand& op = instr->operands[i];
 446             if (!op.isTemp())
 447                continue;
 448             if (!op.isFixed())
 449                err |= ra_fail(output, loc, Location(), "Operand %d is not assigned a register", i);
 450             if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
 451                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i);
 452             if ((op.getTemp().type() == RegType::vgpr && op.physReg() + op.size() > 256 + program->config->num_vgprs) ||
 453                 (op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit))
 454                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i);
 455             if (op.physReg() == vcc && !program->needs_vcc)
 456                err |= ra_fail(output, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i);
 457             if (!(instr->isSDWA() || instr->format == Format::PSEUDO) && op.regClass().is_subdword() && op.physReg().byte())
 458                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d must be aligned to a full register", i);
 459             if (!assignments[op.tempId()].firstloc.block)
 460                assignments[op.tempId()].firstloc = loc;
 461             if (!assignments[op.tempId()].defloc.block)
 462                assignments[op.tempId()].reg = op.physReg();
 463          }
 464
 465          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 466             Definition& def = instr->definitions[i];
 467             if (!def.isTemp())
 468                continue;
 469             if (!def.isFixed())
 470                err |= ra_fail(output, loc, Location(), "Definition %d is not assigned a register", i);
 471             if (assignments[def.tempId()].defloc.block)
 472                err |= ra_fail(output, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId());
 473             if ((def.getTemp().type() == RegType::vgpr && def.physReg() + def.size() > 256 + program->config->num_vgprs) ||
 474                 (def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit))
 475                err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i);
 476             if (def.physReg() == vcc && !program->needs_vcc)
 477                err |= ra_fail(output, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i);
 478             if (!assignments[def.tempId()].firstloc.block)
 479                assignments[def.tempId()].firstloc = loc;
 480             assignments[def.tempId()].defloc = loc;
 481             assignments[def.tempId()].reg = def.physReg();
 482          }
 483       }
 484    }
 485
 486    for (Block& block : program->blocks) {
 487       Location loc;
 488       loc.block = &block;
 489
 490       std::array<unsigned, 512> regs;
 491       regs.fill(0);
 492
 493       std::set<Temp> live;
 494       live.insert(live_vars.live_out[block.index].begin(), live_vars.live_out[block.index].end());
 495       /* remove killed p_phi sgpr operands */
 496       for (Temp tmp : phi_sgpr_ops[block.index])
 497          live.erase(tmp);
 498
 499       /* check live out */
 500       for (Temp tmp : live) {
 501          PhysReg reg = assignments.at(tmp.id()).reg;
 502          for (unsigned i = 0; i < tmp.size(); i++) {
 503             if (regs[reg + i]) {
 504                err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg + i]);
 505             }
 506             regs[reg + i] = tmp.id();
 507          }
 508       }
 509       regs.fill(0);
 510
 511       for (auto it = block.instructions.rbegin(); it != block.instructions.rend(); ++it) {
 512          aco_ptr<Instruction>& instr = *it;
 513
 514          /* check killed p_phi sgpr operands */
 515          if (instr->opcode == aco_opcode::p_logical_end) {
 516             for (Temp tmp : phi_sgpr_ops[block.index]) {
 517                PhysReg reg = assignments.at(tmp.id()).reg;
 518                for (unsigned i = 0; i < tmp.size(); i++) {
 519                   if (regs[reg + i])
 520                      err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg + i]);
 521                }
 522                live.emplace(tmp);
 523             }
 524          }
 525
 526          for (const Definition& def : instr->definitions) {
 527             if (!def.isTemp())
 528                continue;
 529             live.erase(def.getTemp());
 530          }
 531
 532          /* don't count phi operands as live-in, since they are actually
 533           * killed when they are copied at the predecessor */
 534          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 535             for (const Operand& op : instr->operands) {
 536                if (!op.isTemp())
 537                   continue;
 538                live.insert(op.getTemp());
 539             }
 540          }
 541       }
 542
 543       for (Temp tmp : live) {
 544          PhysReg reg = assignments.at(tmp.id()).reg;
 545          for (unsigned i = 0; i < tmp.size(); i++)
 546             regs[reg + i] = tmp.id();
 547       }
 548
 549       for (aco_ptr<Instruction>& instr : block.instructions) {
 550          loc.instr = instr.get();
 551
 552          /* remove killed p_phi operands from regs */
 553          if (instr->opcode == aco_opcode::p_logical_end) {
 554             for (Temp tmp : phi_sgpr_ops[block.index]) {
 555                PhysReg reg = assignments.at(tmp.id()).reg;
 556                regs[reg] = 0;
 557             }
 558          }
 559
 560          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 561             for (const Operand& op : instr->operands) {
 562                if (!op.isTemp())
 563                   continue;
 564                if (op.isFirstKillBeforeDef()) {
 565                   for (unsigned j = 0; j < op.getTemp().size(); j++)
 566                      regs[op.physReg() + j] = 0;
 567                }
 568             }
 569          }
 570
 571          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 572             Definition& def = instr->definitions[i];
 573             if (!def.isTemp())
 574                continue;
 575             Temp tmp = def.getTemp();
 576             PhysReg reg = assignments.at(tmp.id()).reg;
 577             for (unsigned j = 0; j < tmp.size(); j++) {
 578                if (regs[reg + j])
 579                   err |= ra_fail(output, loc, assignments.at(regs[reg + i]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg + j]);
 580                regs[reg + j] = tmp.id();
 581             }
 582          }
 583
 584          for (const Definition& def : instr->definitions) {
 585             if (!def.isTemp())
 586                continue;
 587             if (def.isKill()) {
 588                for (unsigned j = 0; j < def.getTemp().size(); j++)
 589                   regs[def.physReg() + j] = 0;
 590             }
 591          }
 592
 593          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 594             for (const Operand& op : instr->operands) {
 595                if (!op.isTemp())
 596                   continue;
 597                if (op.isLateKill() && op.isFirstKill()) {
 598                   for (unsigned j = 0; j < op.getTemp().size(); j++)
 599                      regs[op.physReg() + j] = 0;
 600                }
 601             }
 602          }
 603       }
 604    }
 605
 606    return err;
 607 }
 608 }