src/amd/compiler/aco_validate.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "aco_ir.h"
  26
  27 #include <array>
  28 #include <map>
  29
  30 namespace aco {
  31
  32 #ifndef NDEBUG
  33 void perfwarn(bool cond, const char *msg, Instruction *instr)
  34 {
  35    if (cond) {
  36       fprintf(stderr, "ACO performance warning: %s\n", msg);
  37       if (instr) {
  38          fprintf(stderr, "instruction: ");
  39          aco_print_instr(instr, stderr);
  40          fprintf(stderr, "\n");
  41       }
  42
  43       if (debug_flags & DEBUG_PERFWARN)
  44          exit(1);
  45    }
  46 }
  47 #endif
  48
  49 bool instr_can_access_subdword(aco_ptr<Instruction>& instr)
  50 {
  51    return instr->isSDWA() || instr->format == Format::PSEUDO;
  52 }
  53
  54 void validate(Program* program, FILE * output)
  55 {
  56    if (!(debug_flags & DEBUG_VALIDATE))
  57       return;
  58
  59    bool is_valid = true;
  60    auto check = [&output, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void {
  61       if (!check) {
  62          fprintf(output, "%s: ", msg);
  63          aco_print_instr(instr, output);
  64          fprintf(output, "\n");
  65          is_valid = false;
  66       }
  67    };
  68    auto check_block = [&output, &is_valid](bool check, const char * msg, aco::Block * block) -> void {
  69       if (!check) {
  70          fprintf(output, "%s: BB%u\n", msg, block->index);
  71          is_valid = false;
  72       }
  73    };
  74
  75    for (Block& block : program->blocks) {
  76       for (aco_ptr<Instruction>& instr : block.instructions) {
  77
  78          /* check base format */
  79          Format base_format = instr->format;
  80          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::SDWA);
  81          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::DPP);
  82          if ((uint32_t)base_format & (uint32_t)Format::VOP1)
  83             base_format = Format::VOP1;
  84          else if ((uint32_t)base_format & (uint32_t)Format::VOP2)
  85             base_format = Format::VOP2;
  86          else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
  87             base_format = Format::VOPC;
  88          else if ((uint32_t)base_format & (uint32_t)Format::VINTRP)
  89             base_format = Format::VINTRP;
  90          check(base_format == instr_info.format[(int)instr->opcode], "Wrong base format for instruction", instr.get());
  91
  92          /* check VOP3 modifiers */
  93          if (((uint32_t)instr->format & (uint32_t)Format::VOP3) && instr->format != Format::VOP3) {
  94             check(base_format == Format::VOP2 ||
  95                   base_format == Format::VOP1 ||
  96                   base_format == Format::VOPC ||
  97                   base_format == Format::VINTRP,
  98                   "Format cannot have VOP3A/VOP3B applied", instr.get());
  99          }
 100
 101          /* check SDWA */
 102          if (instr->isSDWA()) {
 103             check(base_format == Format::VOP2 ||
 104                   base_format == Format::VOP1 ||
 105                   base_format == Format::VOPC,
 106                   "Format cannot have SDWA applied", instr.get());
 107
 108             check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
 109
 110             SDWA_instruction *sdwa = static_cast<SDWA_instruction*>(instr.get());
 111             check(sdwa->omod == 0 || program->chip_class >= GFX9, "SDWA omod only supported on GFX9+", instr.get());
 112             if (base_format == Format::VOPC) {
 113                check(sdwa->clamp == false || program->chip_class == GFX8, "SDWA VOPC clamp only supported on GFX8", instr.get());
 114                check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
 115                      program->chip_class >= GFX9,
 116                      "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
 117             }
 118
 119             if (instr->operands.size() >= 3) {
 120                check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
 121                      "3rd operand must be fixed to vcc with SDWA", instr.get());
 122             }
 123             if (instr->definitions.size() >= 2) {
 124                check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
 125                      "2nd definition must be fixed to vcc with SDWA", instr.get());
 126             }
 127
 128             check(instr->opcode != aco_opcode::v_madmk_f32 &&
 129                   instr->opcode != aco_opcode::v_madak_f32 &&
 130                   instr->opcode != aco_opcode::v_madmk_f16 &&
 131                   instr->opcode != aco_opcode::v_madak_f16 &&
 132                   instr->opcode != aco_opcode::v_readfirstlane_b32 &&
 133                   instr->opcode != aco_opcode::v_clrexcp &&
 134                   instr->opcode != aco_opcode::v_swap_b32,
 135                   "SDWA can't be used with this opcode", instr.get());
 136             if (program->chip_class != GFX8) {
 137                check(instr->opcode != aco_opcode::v_mac_f32 &&
 138                      instr->opcode != aco_opcode::v_mac_f16 &&
 139                      instr->opcode != aco_opcode::v_fmac_f32 &&
 140                      instr->opcode != aco_opcode::v_fmac_f16,
 141                      "SDWA can't be used with this opcode", instr.get());
 142             }
 143          }
 144
 145          /* check opsel */
 146          if (instr->isVOP3()) {
 147             VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
 148             check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get());
 149             check((vop3->opsel & ~(0x10 | ((1 << instr->operands.size()) - 1))) == 0, "Unused bits in opsel must be zeroed out", instr.get());
 150          }
 151
 152          /* check for undefs */
 153          for (unsigned i = 0; i < instr->operands.size(); i++) {
 154             if (instr->operands[i].isUndefined()) {
 155                bool flat = instr->format == Format::FLAT || instr->format == Format::SCRATCH || instr->format == Format::GLOBAL;
 156                bool can_be_undef = is_phi(instr) || instr->format == Format::EXP ||
 157                                    instr->format == Format::PSEUDO_REDUCTION ||
 158                                    instr->opcode == aco_opcode::p_create_vector ||
 159                                    (flat && i == 1) || (instr->format == Format::MIMG && i == 1) ||
 160                                    ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1);
 161                check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
 162             } else {
 163                check(instr->operands[i].isFixed() || instr->operands[i].isTemp() || instr->operands[i].isConstant(), "Uninitialized Operand", instr.get());
 164             }
 165          }
 166
 167          /* check subdword definitions */
 168          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 169             if (instr->definitions[i].regClass().is_subdword())
 170                check(instr_can_access_subdword(instr) || instr->definitions[i].bytes() <= 4, "Only SDWA and Pseudo instructions can write subdword registers larger than 4 bytes", instr.get());
 171          }
 172
 173          if (instr->isSALU() || instr->isVALU()) {
 174             /* check literals */
 175             Operand literal(s1);
 176             for (unsigned i = 0; i < instr->operands.size(); i++)
 177             {
 178                Operand op = instr->operands[i];
 179                if (!op.isLiteral())
 180                   continue;
 181
 182                check(instr->format == Format::SOP1 ||
 183                      instr->format == Format::SOP2 ||
 184                      instr->format == Format::SOPC ||
 185                      instr->format == Format::VOP1 ||
 186                      instr->format == Format::VOP2 ||
 187                      instr->format == Format::VOPC ||
 188                      (instr->isVOP3() && program->chip_class >= GFX10),
 189                      "Literal applied on wrong instruction format", instr.get());
 190
 191                check(literal.isUndefined() || (literal.size() == op.size() && literal.constantValue() == op.constantValue()), "Only 1 Literal allowed", instr.get());
 192                literal = op;
 193                check(!instr->isVALU() || instr->isVOP3() || i == 0 || i == 2, "Wrong source position for Literal argument", instr.get());
 194             }
 195
 196             /* check num sgprs for VALU */
 197             if (instr->isVALU()) {
 198                bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
 199                                  instr->opcode == aco_opcode::v_lshrrev_b64 ||
 200                                  instr->opcode == aco_opcode::v_ashrrev_i64;
 201                unsigned const_bus_limit = 1;
 202                if (program->chip_class >= GFX10 && !is_shift64)
 203                   const_bus_limit = 2;
 204
 205                uint32_t scalar_mask = instr->isVOP3() ? 0x7 : 0x5;
 206                if (instr->isSDWA())
 207                   scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4;
 208
 209                check(instr->definitions[0].getTemp().type() == RegType::vgpr ||
 210                      (int) instr->format & (int) Format::VOPC ||
 211                      instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 212                      instr->opcode == aco_opcode::v_readlane_b32 ||
 213                      instr->opcode == aco_opcode::v_readlane_b32_e64,
 214                      "Wrong Definition type for VALU instruction", instr.get());
 215                unsigned num_sgprs = 0;
 216                unsigned sgpr[] = {0, 0};
 217                for (unsigned i = 0; i < instr->operands.size(); i++)
 218                {
 219                   Operand op = instr->operands[i];
 220                   if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 221                       instr->opcode == aco_opcode::v_readlane_b32 ||
 222                       instr->opcode == aco_opcode::v_readlane_b32_e64 ||
 223                       instr->opcode == aco_opcode::v_writelane_b32 ||
 224                       instr->opcode == aco_opcode::v_writelane_b32_e64) {
 225                      check(!op.isLiteral(), "No literal allowed on VALU instruction", instr.get());
 226                      check(i == 1 || (op.isTemp() && op.regClass() == v1), "Wrong Operand type for VALU instruction", instr.get());
 227                      continue;
 228                   }
 229                   if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
 230                      check(scalar_mask & (1 << i), "Wrong source position for SGPR argument", instr.get());
 231
 232                      if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
 233                         if (num_sgprs < 2)
 234                            sgpr[num_sgprs++] = op.tempId();
 235                      }
 236                   }
 237
 238                   if (op.isConstant() && !op.isLiteral())
 239                      check(scalar_mask & (1 << i), "Wrong source position for constant argument", instr.get());
 240                }
 241                check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, "Too many SGPRs/literals", instr.get());
 242             }
 243
 244             if (instr->format == Format::SOP1 || instr->format == Format::SOP2) {
 245                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "Wrong Definition type for SALU instruction", instr.get());
 246                for (const Operand& op : instr->operands) {
 247                  check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
 248                        "Wrong Operand type for SALU instruction", instr.get());
 249             }
 250          }
 251          }
 252
 253          switch (instr->format) {
 254          case Format::PSEUDO: {
 255             if (instr->opcode == aco_opcode::p_create_vector) {
 256                unsigned size = 0;
 257                for (const Operand& op : instr->operands) {
 258                   size += op.bytes();
 259                }
 260                check(size == instr->definitions[0].bytes(), "Definition size does not match operand sizes", instr.get());
 261                if (instr->definitions[0].getTemp().type() == RegType::sgpr) {
 262                   for (const Operand& op : instr->operands) {
 263                      check(op.isConstant() || op.regClass().type() == RegType::sgpr,
 264                            "Wrong Operand type for scalar vector", instr.get());
 265                   }
 266                }
 267             } else if (instr->opcode == aco_opcode::p_extract_vector) {
 268                check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(), "Wrong Operand types", instr.get());
 269                check((instr->operands[1].constantValue() + 1) * instr->definitions[0].bytes() <= instr->operands[0].bytes(), "Index out of range", instr.get());
 270                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr,
 271                      "Cannot extract SGPR value from VGPR vector", instr.get());
 272             } else if (instr->opcode == aco_opcode::p_parallelcopy) {
 273                check(instr->definitions.size() == instr->operands.size(), "Number of Operands does not match number of Definitions", instr.get());
 274                for (unsigned i = 0; i < instr->operands.size(); i++) {
 275                   if (instr->operands[i].isTemp())
 276                      check((instr->definitions[i].getTemp().type() == instr->operands[i].regClass().type()) ||
 277                            (instr->definitions[i].getTemp().type() == RegType::vgpr && instr->operands[i].regClass().type() == RegType::sgpr),
 278                            "Operand and Definition types do not match", instr.get());
 279                }
 280             } else if (instr->opcode == aco_opcode::p_phi) {
 281                check(instr->operands.size() == block.logical_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 282                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->definitions[0].getTemp().regClass() == program->lane_mask, "Logical Phi Definition must be vgpr or divergent boolean", instr.get());
 283             } else if (instr->opcode == aco_opcode::p_linear_phi) {
 284                for (const Operand& op : instr->operands)
 285                   check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type", instr.get());
 286                check(instr->operands.size() == block.linear_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 287             }
 288             break;
 289          }
 290          case Format::SMEM: {
 291             if (instr->operands.size() >= 1)
 292                check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "SMEM operands must be sgpr", instr.get());
 293             if (instr->operands.size() >= 2)
 294                check(instr->operands[1].isConstant() || (instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr),
 295                      "SMEM offset must be constant or sgpr", instr.get());
 296             if (!instr->definitions.empty())
 297                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "SMEM result must be sgpr", instr.get());
 298             break;
 299          }
 300          case Format::MTBUF:
 301          case Format::MUBUF: {
 302             check(instr->operands.size() > 1, "VMEM instructions must have at least one operand", instr.get());
 303             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr,
 304                   "VADDR must be in vgpr for VMEM instructions", instr.get());
 305             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "VMEM resource constant must be sgpr", instr.get());
 306             check(instr->operands.size() < 4 || (instr->operands[3].isTemp() && instr->operands[3].regClass().type() == RegType::vgpr), "VMEM write data must be vgpr", instr.get());
 307             break;
 308          }
 309          case Format::MIMG: {
 310             check(instr->operands.size() == 3, "MIMG instructions must have exactly 3 operands", instr.get());
 311             check(instr->operands[0].hasRegClass() && (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
 312                   "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
 313             if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr)
 314                check(instr->operands[1].regClass() == s4, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
 315             else if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr)
 316                check((instr->definitions.empty() || instr->definitions[0].regClass() == instr->operands[1].regClass() ||
 317                      instr->opcode == aco_opcode::image_atomic_cmpswap || instr->opcode == aco_opcode::image_atomic_fcmpswap),
 318                      "MIMG operands[1] (VDATA) must be the same as definitions[0] for atomics", instr.get());
 319             check(instr->operands[2].hasRegClass() && instr->operands[2].regClass().type() == RegType::vgpr,
 320                   "MIMG operands[2] (VADDR) must be VGPR", instr.get());
 321             check(instr->definitions.empty() || (instr->definitions[0].isTemp() && instr->definitions[0].regClass().type() == RegType::vgpr),
 322                   "MIMG definitions[0] (VDATA) must be VGPR", instr.get());
 323             break;
 324          }
 325          case Format::DS: {
 326             for (const Operand& op : instr->operands) {
 327                check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
 328                      "Only VGPRs are valid DS instruction operands", instr.get());
 329             }
 330             if (!instr->definitions.empty())
 331                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "DS instruction must return VGPR", instr.get());
 332             break;
 333          }
 334          case Format::EXP: {
 335             for (unsigned i = 0; i < 4; i++)
 336                check(instr->operands[i].hasRegClass() && instr->operands[i].regClass().type() == RegType::vgpr,
 337                      "Only VGPRs are valid Export arguments", instr.get());
 338             break;
 339          }
 340          case Format::FLAT:
 341             check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR", instr.get());
 342             /* fallthrough */
 343          case Format::GLOBAL:
 344          case Format::SCRATCH: {
 345             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH address must be vgpr", instr.get());
 346             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr,
 347                   "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr.get());
 348             if (!instr->definitions.empty())
 349                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH result must be vgpr", instr.get());
 350             else
 351                check(instr->operands[2].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH data must be vgpr", instr.get());
 352             break;
 353          }
 354          default:
 355             break;
 356          }
 357       }
 358    }
 359
 360    /* validate CFG */
 361    for (unsigned i = 0; i < program->blocks.size(); i++) {
 362       Block& block = program->blocks[i];
 363       check_block(block.index == i, "block.index must match actual index", &block);
 364
 365       /* predecessors/successors should be sorted */
 366       for (unsigned j = 0; j + 1 < block.linear_preds.size(); j++)
 367          check_block(block.linear_preds[j] < block.linear_preds[j + 1], "linear predecessors must be sorted", &block);
 368       for (unsigned j = 0; j + 1 < block.logical_preds.size(); j++)
 369          check_block(block.logical_preds[j] < block.logical_preds[j + 1], "logical predecessors must be sorted", &block);
 370       for (unsigned j = 0; j + 1 < block.linear_succs.size(); j++)
 371          check_block(block.linear_succs[j] < block.linear_succs[j + 1], "linear successors must be sorted", &block);
 372       for (unsigned j = 0; j + 1 < block.logical_succs.size(); j++)
 373          check_block(block.logical_succs[j] < block.logical_succs[j + 1], "logical successors must be sorted", &block);
 374
 375       /* critical edges are not allowed */
 376       if (block.linear_preds.size() > 1) {
 377          for (unsigned pred : block.linear_preds)
 378             check_block(program->blocks[pred].linear_succs.size() == 1, "linear critical edges are not allowed", &program->blocks[pred]);
 379          for (unsigned pred : block.logical_preds)
 380             check_block(program->blocks[pred].logical_succs.size() == 1, "logical critical edges are not allowed", &program->blocks[pred]);
 381       }
 382    }
 383
 384    assert(is_valid);
 385 }
 386
 387 /* RA validation */
 388 namespace {
 389
 390 struct Location {
 391    Location() : block(NULL), instr(NULL) {}
 392
 393    Block *block;
 394    Instruction *instr; //NULL if it's the block's live-in
 395 };
 396
 397 struct Assignment {
 398    Location defloc;
 399    Location firstloc;
 400    PhysReg reg;
 401 };
 402
 403 bool ra_fail(FILE *output, Location loc, Location loc2, const char *fmt, ...) {
 404    va_list args;
 405    va_start(args, fmt);
 406    char msg[1024];
 407    vsprintf(msg, fmt, args);
 408    va_end(args);
 409
 410    fprintf(stderr, "RA error found at instruction in BB%d:\n", loc.block->index);
 411    if (loc.instr) {
 412       aco_print_instr(loc.instr, stderr);
 413       fprintf(stderr, "\n%s", msg);
 414    } else {
 415       fprintf(stderr, "%s", msg);
 416    }
 417    if (loc2.block) {
 418       fprintf(stderr, " in BB%d:\n", loc2.block->index);
 419       aco_print_instr(loc2.instr, stderr);
 420    }
 421    fprintf(stderr, "\n\n");
 422
 423    return true;
 424 }
 425
 426 } /* end namespace */
 427
 428 bool validate_ra(Program *program, const struct radv_nir_compiler_options *options, FILE *output) {
 429    if (!(debug_flags & DEBUG_VALIDATE_RA))
 430       return false;
 431
 432    bool err = false;
 433    aco::live live_vars = aco::live_var_analysis(program, options);
 434    std::vector<std::vector<Temp>> phi_sgpr_ops(program->blocks.size());
 435
 436    std::map<unsigned, Assignment> assignments;
 437    for (Block& block : program->blocks) {
 438       Location loc;
 439       loc.block = &block;
 440       for (aco_ptr<Instruction>& instr : block.instructions) {
 441          if (instr->opcode == aco_opcode::p_phi) {
 442             for (unsigned i = 0; i < instr->operands.size(); i++) {
 443                if (instr->operands[i].isTemp() &&
 444                    instr->operands[i].getTemp().type() == RegType::sgpr &&
 445                    instr->operands[i].isFirstKill())
 446                   phi_sgpr_ops[block.logical_preds[i]].emplace_back(instr->operands[i].getTemp());
 447             }
 448          }
 449
 450          loc.instr = instr.get();
 451          for (unsigned i = 0; i < instr->operands.size(); i++) {
 452             Operand& op = instr->operands[i];
 453             if (!op.isTemp())
 454                continue;
 455             if (!op.isFixed())
 456                err |= ra_fail(output, loc, Location(), "Operand %d is not assigned a register", i);
 457             if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
 458                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i);
 459             if ((op.getTemp().type() == RegType::vgpr && op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) ||
 460                 (op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit))
 461                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i);
 462             if (op.physReg() == vcc && !program->needs_vcc)
 463                err |= ra_fail(output, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i);
 464             if (!instr_can_access_subdword(instr) && op.regClass().is_subdword() && op.physReg().byte())
 465                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d must be aligned to a full register", i);
 466             if (!assignments[op.tempId()].firstloc.block)
 467                assignments[op.tempId()].firstloc = loc;
 468             if (!assignments[op.tempId()].defloc.block)
 469                assignments[op.tempId()].reg = op.physReg();
 470          }
 471
 472          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 473             Definition& def = instr->definitions[i];
 474             if (!def.isTemp())
 475                continue;
 476             if (!def.isFixed())
 477                err |= ra_fail(output, loc, Location(), "Definition %d is not assigned a register", i);
 478             if (assignments[def.tempId()].defloc.block)
 479                err |= ra_fail(output, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId());
 480             if ((def.getTemp().type() == RegType::vgpr && def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) ||
 481                 (def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit))
 482                err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i);
 483             if (def.physReg() == vcc && !program->needs_vcc)
 484                err |= ra_fail(output, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i);
 485             if (!instr_can_access_subdword(instr) && def.regClass().is_subdword() && def.physReg().byte())
 486                err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d must be aligned to a full register", i);
 487             if (!assignments[def.tempId()].firstloc.block)
 488                assignments[def.tempId()].firstloc = loc;
 489             assignments[def.tempId()].defloc = loc;
 490             assignments[def.tempId()].reg = def.physReg();
 491          }
 492       }
 493    }
 494
 495    for (Block& block : program->blocks) {
 496       Location loc;
 497       loc.block = &block;
 498
 499       std::array<unsigned, 2048> regs; /* register file in bytes */
 500       regs.fill(0);
 501
 502       std::set<Temp> live;
 503       live.insert(live_vars.live_out[block.index].begin(), live_vars.live_out[block.index].end());
 504       /* remove killed p_phi sgpr operands */
 505       for (Temp tmp : phi_sgpr_ops[block.index])
 506          live.erase(tmp);
 507
 508       /* check live out */
 509       for (Temp tmp : live) {
 510          PhysReg reg = assignments.at(tmp.id()).reg;
 511          for (unsigned i = 0; i < tmp.bytes(); i++) {
 512             if (regs[reg.reg_b + i]) {
 513                err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
 514             }
 515             regs[reg.reg_b + i] = tmp.id();
 516          }
 517       }
 518       regs.fill(0);
 519
 520       for (auto it = block.instructions.rbegin(); it != block.instructions.rend(); ++it) {
 521          aco_ptr<Instruction>& instr = *it;
 522
 523          /* check killed p_phi sgpr operands */
 524          if (instr->opcode == aco_opcode::p_logical_end) {
 525             for (Temp tmp : phi_sgpr_ops[block.index]) {
 526                PhysReg reg = assignments.at(tmp.id()).reg;
 527                for (unsigned i = 0; i < tmp.bytes(); i++) {
 528                   if (regs[reg.reg_b + i])
 529                      err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
 530                }
 531                live.emplace(tmp);
 532             }
 533          }
 534
 535          for (const Definition& def : instr->definitions) {
 536             if (!def.isTemp())
 537                continue;
 538             live.erase(def.getTemp());
 539          }
 540
 541          /* don't count phi operands as live-in, since they are actually
 542           * killed when they are copied at the predecessor */
 543          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 544             for (const Operand& op : instr->operands) {
 545                if (!op.isTemp())
 546                   continue;
 547                live.insert(op.getTemp());
 548             }
 549          }
 550       }
 551
 552       for (Temp tmp : live) {
 553          PhysReg reg = assignments.at(tmp.id()).reg;
 554          for (unsigned i = 0; i < tmp.bytes(); i++)
 555             regs[reg.reg_b + i] = tmp.id();
 556       }
 557
 558       for (aco_ptr<Instruction>& instr : block.instructions) {
 559          loc.instr = instr.get();
 560
 561          /* remove killed p_phi operands from regs */
 562          if (instr->opcode == aco_opcode::p_logical_end) {
 563             for (Temp tmp : phi_sgpr_ops[block.index]) {
 564                PhysReg reg = assignments.at(tmp.id()).reg;
 565                for (unsigned i = 0; i < tmp.bytes(); i++)
 566                   regs[reg.reg_b + i] = 0;
 567             }
 568          }
 569
 570          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 571             for (const Operand& op : instr->operands) {
 572                if (!op.isTemp())
 573                   continue;
 574                if (op.isFirstKillBeforeDef()) {
 575                   for (unsigned j = 0; j < op.getTemp().bytes(); j++)
 576                      regs[op.physReg().reg_b + j] = 0;
 577                }
 578             }
 579          }
 580
 581          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 582             Definition& def = instr->definitions[i];
 583             if (!def.isTemp())
 584                continue;
 585             Temp tmp = def.getTemp();
 586             PhysReg reg = assignments.at(tmp.id()).reg;
 587             for (unsigned j = 0; j < tmp.bytes(); j++) {
 588                if (regs[reg.reg_b + j])
 589                   err |= ra_fail(output, loc, assignments.at(regs[reg.reg_b + j]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]);
 590                regs[reg.reg_b + j] = tmp.id();
 591             }
 592             if (def.regClass().is_subdword() && !instr_can_access_subdword(instr)) {
 593                for (unsigned j = tmp.bytes(); j < 4; j++)
 594                   if (regs[reg.reg_b + j])
 595                      err |= ra_fail(output, loc, assignments.at(regs[reg.reg_b + j]).defloc, "Assignment of element %d of %%%d overwrites the full register taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]);
 596             }
 597          }
 598
 599          for (const Definition& def : instr->definitions) {
 600             if (!def.isTemp())
 601                continue;
 602             if (def.isKill()) {
 603                for (unsigned j = 0; j < def.getTemp().bytes(); j++)
 604                   regs[def.physReg().reg_b + j] = 0;
 605             }
 606          }
 607
 608          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 609             for (const Operand& op : instr->operands) {
 610                if (!op.isTemp())
 611                   continue;
 612                if (op.isLateKill() && op.isFirstKill()) {
 613                   for (unsigned j = 0; j < op.getTemp().bytes(); j++)
 614                      regs[op.physReg().reg_b + j] = 0;
 615                }
 616             }
 617          }
 618       }
 619    }
 620
 621    return err;
 622 }
 623 }