2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 void perfwarn(bool cond
, const char *msg
, Instruction
*instr
)
36 fprintf(stderr
, "ACO performance warning: %s\n", msg
);
38 fprintf(stderr
, "instruction: ");
39 aco_print_instr(instr
, stderr
);
40 fprintf(stderr
, "\n");
43 if (debug_flags
& DEBUG_PERFWARN
)
49 void validate(Program
* program
, FILE * output
)
51 if (!(debug_flags
& DEBUG_VALIDATE
))
55 auto check
= [&output
, &is_valid
](bool check
, const char * msg
, aco::Instruction
* instr
) -> void {
57 fprintf(output
, "%s: ", msg
);
58 aco_print_instr(instr
, output
);
59 fprintf(output
, "\n");
63 auto check_block
= [&output
, &is_valid
](bool check
, const char * msg
, aco::Block
* block
) -> void {
65 fprintf(output
, "%s: BB%u\n", msg
, block
->index
);
70 for (Block
& block
: program
->blocks
) {
71 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
73 /* check base format */
74 Format base_format
= instr
->format
;
75 base_format
= (Format
)((uint32_t)base_format
& ~(uint32_t)Format::SDWA
);
76 base_format
= (Format
)((uint32_t)base_format
& ~(uint32_t)Format::DPP
);
77 if ((uint32_t)base_format
& (uint32_t)Format::VOP1
)
78 base_format
= Format::VOP1
;
79 else if ((uint32_t)base_format
& (uint32_t)Format::VOP2
)
80 base_format
= Format::VOP2
;
81 else if ((uint32_t)base_format
& (uint32_t)Format::VOPC
)
82 base_format
= Format::VOPC
;
83 else if ((uint32_t)base_format
& (uint32_t)Format::VINTRP
)
84 base_format
= Format::VINTRP
;
85 check(base_format
== instr_info
.format
[(int)instr
->opcode
], "Wrong base format for instruction", instr
.get());
87 /* check VOP3 modifiers */
88 if (((uint32_t)instr
->format
& (uint32_t)Format::VOP3
) && instr
->format
!= Format::VOP3
) {
89 check(base_format
== Format::VOP2
||
90 base_format
== Format::VOP1
||
91 base_format
== Format::VOPC
||
92 base_format
== Format::VINTRP
,
93 "Format cannot have VOP3A/VOP3B applied", instr
.get());
96 /* check for undefs */
97 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
98 if (instr
->operands
[i
].isUndefined()) {
99 bool flat
= instr
->format
== Format::FLAT
|| instr
->format
== Format::SCRATCH
|| instr
->format
== Format::GLOBAL
;
100 bool can_be_undef
= is_phi(instr
) || instr
->format
== Format::EXP
||
101 instr
->format
== Format::PSEUDO_REDUCTION
||
102 (flat
&& i
== 1) || (instr
->format
== Format::MIMG
&& i
== 1) ||
103 ((instr
->format
== Format::MUBUF
|| instr
->format
== Format::MTBUF
) && i
== 1);
104 check(can_be_undef
, "Undefs can only be used in certain operands", instr
.get());
108 if (instr
->isSALU() || instr
->isVALU()) {
111 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
113 Operand op
= instr
->operands
[i
];
117 check(instr
->format
== Format::SOP1
||
118 instr
->format
== Format::SOP2
||
119 instr
->format
== Format::SOPC
||
120 instr
->format
== Format::VOP1
||
121 instr
->format
== Format::VOP2
||
122 instr
->format
== Format::VOPC
||
123 (instr
->isVOP3() && program
->chip_class
>= GFX10
),
124 "Literal applied on wrong instruction format", instr
.get());
126 check(literal
.isUndefined() || (literal
.size() == op
.size() && literal
.constantValue() == op
.constantValue()), "Only 1 Literal allowed", instr
.get());
128 check(!instr
->isVALU() || instr
->isVOP3() || i
== 0 || i
== 2, "Wrong source position for Literal argument", instr
.get());
131 /* check num sgprs for VALU */
132 if (instr
->isVALU()) {
133 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
134 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
135 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
136 unsigned const_bus_limit
= 1;
137 if (program
->chip_class
>= GFX10
&& !is_shift64
)
140 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
||
141 (int) instr
->format
& (int) Format::VOPC
||
142 instr
->opcode
== aco_opcode::v_readfirstlane_b32
||
143 instr
->opcode
== aco_opcode::v_readlane_b32
||
144 instr
->opcode
== aco_opcode::v_readlane_b32_e64
,
145 "Wrong Definition type for VALU instruction", instr
.get());
146 unsigned num_sgprs
= 0;
147 unsigned sgpr
[] = {0, 0};
148 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
150 Operand op
= instr
->operands
[i
];
151 if (instr
->opcode
== aco_opcode::v_readfirstlane_b32
||
152 instr
->opcode
== aco_opcode::v_readlane_b32
||
153 instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
154 instr
->opcode
== aco_opcode::v_writelane_b32
||
155 instr
->opcode
== aco_opcode::v_writelane_b32_e64
) {
156 check(!op
.isLiteral(), "No literal allowed on VALU instruction", instr
.get());
157 check(i
== 1 || (op
.isTemp() && op
.regClass() == v1
), "Wrong Operand type for VALU instruction", instr
.get());
160 if (op
.isTemp() && instr
->operands
[i
].regClass().type() == RegType::sgpr
) {
161 check(i
!= 1 || instr
->isVOP3(), "Wrong source position for SGPR argument", instr
.get());
163 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
165 sgpr
[num_sgprs
++] = op
.tempId();
169 if (op
.isConstant() && !op
.isLiteral())
170 check(i
== 0 || instr
->isVOP3(), "Wrong source position for constant argument", instr
.get());
172 check(num_sgprs
+ (literal
.isUndefined() ? 0 : 1) <= const_bus_limit
, "Too many SGPRs/literals", instr
.get());
175 if (instr
->format
== Format::SOP1
|| instr
->format
== Format::SOP2
) {
176 check(instr
->definitions
[0].getTemp().type() == RegType::sgpr
, "Wrong Definition type for SALU instruction", instr
.get());
177 for (const Operand
& op
: instr
->operands
) {
178 check(op
.isConstant() || op
.regClass().type() <= RegType::sgpr
,
179 "Wrong Operand type for SALU instruction", instr
.get());
184 switch (instr
->format
) {
185 case Format::PSEUDO
: {
186 if (instr
->opcode
== aco_opcode::p_create_vector
) {
188 for (const Operand
& op
: instr
->operands
) {
191 check(size
== instr
->definitions
[0].size(), "Definition size does not match operand sizes", instr
.get());
192 if (instr
->definitions
[0].getTemp().type() == RegType::sgpr
) {
193 for (const Operand
& op
: instr
->operands
) {
194 check(op
.isConstant() || op
.regClass().type() == RegType::sgpr
,
195 "Wrong Operand type for scalar vector", instr
.get());
198 } else if (instr
->opcode
== aco_opcode::p_extract_vector
) {
199 check((instr
->operands
[0].isTemp()) && instr
->operands
[1].isConstant(), "Wrong Operand types", instr
.get());
200 check(instr
->operands
[1].constantValue() < instr
->operands
[0].size(), "Index out of range", instr
.get());
201 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
|| instr
->operands
[0].regClass().type() == RegType::sgpr
,
202 "Cannot extract SGPR value from VGPR vector", instr
.get());
203 } else if (instr
->opcode
== aco_opcode::p_parallelcopy
) {
204 check(instr
->definitions
.size() == instr
->operands
.size(), "Number of Operands does not match number of Definitions", instr
.get());
205 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
206 if (instr
->operands
[i
].isTemp())
207 check((instr
->definitions
[i
].getTemp().type() == instr
->operands
[i
].regClass().type()) ||
208 (instr
->definitions
[i
].getTemp().type() == RegType::vgpr
&& instr
->operands
[i
].regClass().type() == RegType::sgpr
),
209 "Operand and Definition types do not match", instr
.get());
211 } else if (instr
->opcode
== aco_opcode::p_phi
) {
212 check(instr
->operands
.size() == block
.logical_preds
.size(), "Number of Operands does not match number of predecessors", instr
.get());
213 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
|| instr
->definitions
[0].getTemp().regClass() == program
->lane_mask
, "Logical Phi Definition must be vgpr or divergent boolean", instr
.get());
214 } else if (instr
->opcode
== aco_opcode::p_linear_phi
) {
215 for (const Operand
& op
: instr
->operands
)
216 check(!op
.isTemp() || op
.getTemp().is_linear(), "Wrong Operand type", instr
.get());
217 check(instr
->operands
.size() == block
.linear_preds
.size(), "Number of Operands does not match number of predecessors", instr
.get());
222 if (instr
->operands
.size() >= 1)
223 check(instr
->operands
[0].isTemp() && instr
->operands
[0].regClass().type() == RegType::sgpr
, "SMEM operands must be sgpr", instr
.get());
224 if (instr
->operands
.size() >= 2)
225 check(instr
->operands
[1].isConstant() || (instr
->operands
[1].isTemp() && instr
->operands
[1].regClass().type() == RegType::sgpr
),
226 "SMEM offset must be constant or sgpr", instr
.get());
227 if (!instr
->definitions
.empty())
228 check(instr
->definitions
[0].getTemp().type() == RegType::sgpr
, "SMEM result must be sgpr", instr
.get());
232 case Format::MUBUF
: {
233 check(instr
->operands
.size() > 1, "VMEM instructions must have at least one operand", instr
.get());
234 check(instr
->operands
[1].hasRegClass() && instr
->operands
[1].regClass().type() == RegType::vgpr
,
235 "VADDR must be in vgpr for VMEM instructions", instr
.get());
236 check(instr
->operands
[0].isTemp() && instr
->operands
[0].regClass().type() == RegType::sgpr
, "VMEM resource constant must be sgpr", instr
.get());
237 check(instr
->operands
.size() < 4 || (instr
->operands
[3].isTemp() && instr
->operands
[3].regClass().type() == RegType::vgpr
), "VMEM write data must be vgpr", instr
.get());
241 check(instr
->operands
.size() == 3, "MIMG instructions must have exactly 3 operands", instr
.get());
242 check(instr
->operands
[0].hasRegClass() && (instr
->operands
[0].regClass() == s4
|| instr
->operands
[0].regClass() == s8
),
243 "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr
.get());
244 if (instr
->operands
[1].hasRegClass() && instr
->operands
[1].regClass().type() == RegType::sgpr
)
245 check(instr
->operands
[1].regClass() == s4
, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr
.get());
246 else if (instr
->operands
[1].hasRegClass() && instr
->operands
[1].regClass().type() == RegType::vgpr
)
247 check(instr
->definitions
.empty() || instr
->definitions
[0].regClass() == instr
->operands
[1].regClass(),
248 "MIMG operands[1] (VDATA) must be the same as definitions[0] for atomics", instr
.get());
249 check(instr
->operands
[2].hasRegClass() && instr
->operands
[2].regClass().type() == RegType::vgpr
,
250 "MIMG operands[2] (VADDR) must be VGPR", instr
.get());
251 check(instr
->definitions
.empty() || (instr
->definitions
[0].isTemp() && instr
->definitions
[0].regClass().type() == RegType::vgpr
),
252 "MIMG definitions[0] (VDATA) must be VGPR", instr
.get());
256 for (const Operand
& op
: instr
->operands
) {
257 check((op
.isTemp() && op
.regClass().type() == RegType::vgpr
) || op
.physReg() == m0
,
258 "Only VGPRs are valid DS instruction operands", instr
.get());
260 if (!instr
->definitions
.empty())
261 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
, "DS instruction must return VGPR", instr
.get());
265 for (unsigned i
= 0; i
< 4; i
++)
266 check(instr
->operands
[i
].hasRegClass() && instr
->operands
[i
].regClass().type() == RegType::vgpr
,
267 "Only VGPRs are valid Export arguments", instr
.get());
271 check(instr
->operands
[1].isUndefined(), "Flat instructions don't support SADDR", instr
.get());
274 case Format::SCRATCH
: {
275 check(instr
->operands
[0].isTemp() && instr
->operands
[0].regClass().type() == RegType::vgpr
, "FLAT/GLOBAL/SCRATCH address must be vgpr", instr
.get());
276 check(instr
->operands
[1].hasRegClass() && instr
->operands
[1].regClass().type() == RegType::sgpr
,
277 "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr
.get());
278 if (!instr
->definitions
.empty())
279 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
, "FLAT/GLOBAL/SCRATCH result must be vgpr", instr
.get());
281 check(instr
->operands
[2].regClass().type() == RegType::vgpr
, "FLAT/GLOBAL/SCRATCH data must be vgpr", instr
.get());
291 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++) {
292 Block
& block
= program
->blocks
[i
];
293 check_block(block
.index
== i
, "block.index must match actual index", &block
);
295 /* predecessors/successors should be sorted */
296 for (unsigned j
= 0; j
+ 1 < block
.linear_preds
.size(); j
++)
297 check_block(block
.linear_preds
[j
] < block
.linear_preds
[j
+ 1], "linear predecessors must be sorted", &block
);
298 for (unsigned j
= 0; j
+ 1 < block
.logical_preds
.size(); j
++)
299 check_block(block
.logical_preds
[j
] < block
.logical_preds
[j
+ 1], "logical predecessors must be sorted", &block
);
300 for (unsigned j
= 0; j
+ 1 < block
.linear_succs
.size(); j
++)
301 check_block(block
.linear_succs
[j
] < block
.linear_succs
[j
+ 1], "linear successors must be sorted", &block
);
302 for (unsigned j
= 0; j
+ 1 < block
.logical_succs
.size(); j
++)
303 check_block(block
.logical_succs
[j
] < block
.logical_succs
[j
+ 1], "logical successors must be sorted", &block
);
305 /* critical edges are not allowed */
306 if (block
.linear_preds
.size() > 1) {
307 for (unsigned pred
: block
.linear_preds
)
308 check_block(program
->blocks
[pred
].linear_succs
.size() == 1, "linear critical edges are not allowed", &program
->blocks
[pred
]);
309 for (unsigned pred
: block
.logical_preds
)
310 check_block(program
->blocks
[pred
].logical_succs
.size() == 1, "logical critical edges are not allowed", &program
->blocks
[pred
]);
321 Location() : block(NULL
), instr(NULL
) {}
324 Instruction
*instr
; //NULL if it's the block's live-in
333 bool ra_fail(FILE *output
, Location loc
, Location loc2
, const char *fmt
, ...) {
337 vsprintf(msg
, fmt
, args
);
340 fprintf(stderr
, "RA error found at instruction in BB%d:\n", loc
.block
->index
);
342 aco_print_instr(loc
.instr
, stderr
);
343 fprintf(stderr
, "\n%s", msg
);
345 fprintf(stderr
, "%s", msg
);
348 fprintf(stderr
, " in BB%d:\n", loc2
.block
->index
);
349 aco_print_instr(loc2
.instr
, stderr
);
351 fprintf(stderr
, "\n\n");
356 } /* end namespace */
358 bool validate_ra(Program
*program
, const struct radv_nir_compiler_options
*options
, FILE *output
) {
359 if (!(debug_flags
& DEBUG_VALIDATE_RA
))
363 aco::live live_vars
= aco::live_var_analysis(program
, options
);
364 std::vector
<std::vector
<Temp
>> phi_sgpr_ops(program
->blocks
.size());
366 std::map
<unsigned, Assignment
> assignments
;
367 for (Block
& block
: program
->blocks
) {
370 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
371 if (instr
->opcode
== aco_opcode::p_phi
) {
372 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
373 if (instr
->operands
[i
].isTemp() &&
374 instr
->operands
[i
].getTemp().type() == RegType::sgpr
&&
375 instr
->operands
[i
].isFirstKill())
376 phi_sgpr_ops
[block
.logical_preds
[i
]].emplace_back(instr
->operands
[i
].getTemp());
380 loc
.instr
= instr
.get();
381 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
382 Operand
& op
= instr
->operands
[i
];
386 err
|= ra_fail(output
, loc
, Location(), "Operand %d is not assigned a register", i
);
387 if (assignments
.count(op
.tempId()) && assignments
[op
.tempId()].reg
!= op
.physReg())
388 err
|= ra_fail(output
, loc
, assignments
.at(op
.tempId()).firstloc
, "Operand %d has an inconsistent register assignment with instruction", i
);
389 if ((op
.getTemp().type() == RegType::vgpr
&& op
.physReg() + op
.size() > 256 + program
->config
->num_vgprs
) ||
390 (op
.getTemp().type() == RegType::sgpr
&& op
.physReg() + op
.size() > program
->config
->num_sgprs
&& op
.physReg() < program
->sgpr_limit
))
391 err
|= ra_fail(output
, loc
, assignments
.at(op
.tempId()).firstloc
, "Operand %d has an out-of-bounds register assignment", i
);
392 if (!assignments
[op
.tempId()].firstloc
.block
)
393 assignments
[op
.tempId()].firstloc
= loc
;
394 if (!assignments
[op
.tempId()].defloc
.block
)
395 assignments
[op
.tempId()].reg
= op
.physReg();
398 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
399 Definition
& def
= instr
->definitions
[i
];
403 err
|= ra_fail(output
, loc
, Location(), "Definition %d is not assigned a register", i
);
404 if (assignments
[def
.tempId()].defloc
.block
)
405 err
|= ra_fail(output
, loc
, assignments
.at(def
.tempId()).defloc
, "Temporary %%%d also defined by instruction", def
.tempId());
406 if ((def
.getTemp().type() == RegType::vgpr
&& def
.physReg() + def
.size() > 256 + program
->config
->num_vgprs
) ||
407 (def
.getTemp().type() == RegType::sgpr
&& def
.physReg() + def
.size() > program
->config
->num_sgprs
&& def
.physReg() < program
->sgpr_limit
))
408 err
|= ra_fail(output
, loc
, assignments
.at(def
.tempId()).firstloc
, "Definition %d has an out-of-bounds register assignment", i
);
409 if (!assignments
[def
.tempId()].firstloc
.block
)
410 assignments
[def
.tempId()].firstloc
= loc
;
411 assignments
[def
.tempId()].defloc
= loc
;
412 assignments
[def
.tempId()].reg
= def
.physReg();
417 for (Block
& block
: program
->blocks
) {
421 std::array
<unsigned, 512> regs
;
425 live
.insert(live_vars
.live_out
[block
.index
].begin(), live_vars
.live_out
[block
.index
].end());
426 /* remove killed p_phi sgpr operands */
427 for (Temp tmp
: phi_sgpr_ops
[block
.index
])
431 for (Temp tmp
: live
) {
432 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
433 for (unsigned i
= 0; i
< tmp
.size(); i
++) {
435 err
|= ra_fail(output
, loc
, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i
, tmp
.id(), regs
[reg
+ i
]);
437 regs
[reg
+ i
] = tmp
.id();
442 for (auto it
= block
.instructions
.rbegin(); it
!= block
.instructions
.rend(); ++it
) {
443 aco_ptr
<Instruction
>& instr
= *it
;
445 /* check killed p_phi sgpr operands */
446 if (instr
->opcode
== aco_opcode::p_logical_end
) {
447 for (Temp tmp
: phi_sgpr_ops
[block
.index
]) {
448 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
449 for (unsigned i
= 0; i
< tmp
.size(); i
++) {
451 err
|= ra_fail(output
, loc
, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i
, tmp
.id(), regs
[reg
+ i
]);
457 for (const Definition
& def
: instr
->definitions
) {
460 live
.erase(def
.getTemp());
463 /* don't count phi operands as live-in, since they are actually
464 * killed when they are copied at the predecessor */
465 if (instr
->opcode
!= aco_opcode::p_phi
&& instr
->opcode
!= aco_opcode::p_linear_phi
) {
466 for (const Operand
& op
: instr
->operands
) {
469 live
.insert(op
.getTemp());
474 for (Temp tmp
: live
) {
475 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
476 for (unsigned i
= 0; i
< tmp
.size(); i
++)
477 regs
[reg
+ i
] = tmp
.id();
480 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
481 loc
.instr
= instr
.get();
483 /* remove killed p_phi operands from regs */
484 if (instr
->opcode
== aco_opcode::p_logical_end
) {
485 for (Temp tmp
: phi_sgpr_ops
[block
.index
]) {
486 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
491 if (instr
->opcode
!= aco_opcode::p_phi
&& instr
->opcode
!= aco_opcode::p_linear_phi
) {
492 for (const Operand
& op
: instr
->operands
) {
495 if (op
.isFirstKill()) {
496 for (unsigned j
= 0; j
< op
.getTemp().size(); j
++)
497 regs
[op
.physReg() + j
] = 0;
502 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
503 Definition
& def
= instr
->definitions
[i
];
506 Temp tmp
= def
.getTemp();
507 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
508 for (unsigned j
= 0; j
< tmp
.size(); j
++) {
510 err
|= ra_fail(output
, loc
, assignments
.at(regs
[reg
+ i
]).defloc
, "Assignment of element %d of %%%d already taken by %%%d from instruction", i
, tmp
.id(), regs
[reg
+ j
]);
511 regs
[reg
+ j
] = tmp
.id();
515 for (const Definition
& def
: instr
->definitions
) {
519 for (unsigned j
= 0; j
< def
.getTemp().size(); j
++)
520 regs
[def
.physReg() + j
] = 0;