2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 void perfwarn(bool cond
, const char *msg
, Instruction
*instr
)
36 fprintf(stderr
, "ACO performance warning: %s\n", msg
);
38 fprintf(stderr
, "instruction: ");
39 aco_print_instr(instr
, stderr
);
40 fprintf(stderr
, "\n");
43 if (debug_flags
& DEBUG_PERFWARN
)
49 void validate(Program
* program
, FILE * output
)
51 if (!(debug_flags
& DEBUG_VALIDATE
))
55 auto check
= [&output
, &is_valid
](bool check
, const char * msg
, aco::Instruction
* instr
) -> void {
57 fprintf(output
, "%s: ", msg
);
58 aco_print_instr(instr
, output
);
59 fprintf(output
, "\n");
63 auto check_block
= [&output
, &is_valid
](bool check
, const char * msg
, aco::Block
* block
) -> void {
65 fprintf(output
, "%s: BB%u\n", msg
, block
->index
);
70 for (Block
& block
: program
->blocks
) {
71 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
73 /* check base format */
74 Format base_format
= instr
->format
;
75 base_format
= (Format
)((uint32_t)base_format
& ~(uint32_t)Format::SDWA
);
76 base_format
= (Format
)((uint32_t)base_format
& ~(uint32_t)Format::DPP
);
77 if ((uint32_t)base_format
& (uint32_t)Format::VOP1
)
78 base_format
= Format::VOP1
;
79 else if ((uint32_t)base_format
& (uint32_t)Format::VOP2
)
80 base_format
= Format::VOP2
;
81 else if ((uint32_t)base_format
& (uint32_t)Format::VOPC
)
82 base_format
= Format::VOPC
;
83 else if ((uint32_t)base_format
& (uint32_t)Format::VINTRP
) {
84 if (instr
->opcode
== aco_opcode::v_interp_p1ll_f16
||
85 instr
->opcode
== aco_opcode::v_interp_p1lv_f16
||
86 instr
->opcode
== aco_opcode::v_interp_p2_legacy_f16
||
87 instr
->opcode
== aco_opcode::v_interp_p2_f16
) {
88 /* v_interp_*_fp16 are considered VINTRP by the compiler but
89 * they are emitted as VOP3.
91 base_format
= Format::VOP3
;
93 base_format
= Format::VINTRP
;
96 check(base_format
== instr_info
.format
[(int)instr
->opcode
], "Wrong base format for instruction", instr
.get());
98 /* check VOP3 modifiers */
99 if (((uint32_t)instr
->format
& (uint32_t)Format::VOP3
) && instr
->format
!= Format::VOP3
) {
100 check(base_format
== Format::VOP2
||
101 base_format
== Format::VOP1
||
102 base_format
== Format::VOPC
||
103 base_format
== Format::VINTRP
,
104 "Format cannot have VOP3A/VOP3B applied", instr
.get());
108 if (instr
->isSDWA()) {
109 check(base_format
== Format::VOP2
||
110 base_format
== Format::VOP1
||
111 base_format
== Format::VOPC
,
112 "Format cannot have SDWA applied", instr
.get());
114 check(program
->chip_class
>= GFX8
, "SDWA is GFX8+ only", instr
.get());
116 SDWA_instruction
*sdwa
= static_cast<SDWA_instruction
*>(instr
.get());
117 check(sdwa
->omod
== 0 || program
->chip_class
>= GFX9
, "SDWA omod only supported on GFX9+", instr
.get());
118 if (base_format
== Format::VOPC
) {
119 check(sdwa
->clamp
== false || program
->chip_class
== GFX8
, "SDWA VOPC clamp only supported on GFX8", instr
.get());
120 check((instr
->definitions
[0].isFixed() && instr
->definitions
[0].physReg() == vcc
) ||
121 program
->chip_class
>= GFX9
,
122 "SDWA+VOPC definition must be fixed to vcc on GFX8", instr
.get());
125 if (instr
->operands
.size() >= 3) {
126 check(instr
->operands
[2].isFixed() && instr
->operands
[2].physReg() == vcc
,
127 "3rd operand must be fixed to vcc with SDWA", instr
.get());
129 if (instr
->definitions
.size() >= 2) {
130 check(instr
->definitions
[1].isFixed() && instr
->definitions
[1].physReg() == vcc
,
131 "2nd definition must be fixed to vcc with SDWA", instr
.get());
134 check(instr
->opcode
!= aco_opcode::v_madmk_f32
&&
135 instr
->opcode
!= aco_opcode::v_madak_f32
&&
136 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
137 instr
->opcode
!= aco_opcode::v_madak_f16
&&
138 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
139 instr
->opcode
!= aco_opcode::v_clrexcp
&&
140 instr
->opcode
!= aco_opcode::v_swap_b32
,
141 "SDWA can't be used with this opcode", instr
.get());
142 if (program
->chip_class
!= GFX8
) {
143 check(instr
->opcode
!= aco_opcode::v_mac_f32
&&
144 instr
->opcode
!= aco_opcode::v_mac_f16
&&
145 instr
->opcode
!= aco_opcode::v_fmac_f32
&&
146 instr
->opcode
!= aco_opcode::v_fmac_f16
,
147 "SDWA can't be used with this opcode", instr
.get());
150 for (unsigned i
= 0; i
< MIN2(instr
->operands
.size(), 2); i
++) {
151 if (instr
->operands
[i
].regClass().is_subdword())
152 check((sdwa
->sel
[i
] & sdwa_asuint
) == (sdwa_isra
| instr
->operands
[i
].bytes()), "Unexpected SDWA sel for sub-dword operand", instr
.get());
154 if (instr
->definitions
[0].regClass().is_subdword())
155 check((sdwa
->dst_sel
& sdwa_asuint
) == (sdwa_isra
| instr
->definitions
[0].bytes()), "Unexpected SDWA sel for sub-dword definition", instr
.get());
159 if (instr
->isVOP3()) {
160 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
161 check(vop3
->opsel
== 0 || program
->chip_class
>= GFX9
, "Opsel is only supported on GFX9+", instr
.get());
162 check((vop3
->opsel
& ~(0x10 | ((1 << instr
->operands
.size()) - 1))) == 0, "Unused bits in opsel must be zeroed out", instr
.get());
164 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
165 if (instr
->operands
[i
].regClass().is_subdword())
166 check((vop3
->opsel
& (1 << i
)) == 0, "Unexpected opsel for sub-dword operand", instr
.get());
168 if (instr
->definitions
[0].regClass().is_subdword())
169 check((vop3
->opsel
& (1 << 3)) == 0, "Unexpected opsel for sub-dword definition", instr
.get());
172 /* check for undefs */
173 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
174 if (instr
->operands
[i
].isUndefined()) {
175 bool flat
= instr
->format
== Format::FLAT
|| instr
->format
== Format::SCRATCH
|| instr
->format
== Format::GLOBAL
;
176 bool can_be_undef
= is_phi(instr
) || instr
->format
== Format::EXP
||
177 instr
->format
== Format::PSEUDO_REDUCTION
||
178 instr
->opcode
== aco_opcode::p_create_vector
||
179 (flat
&& i
== 1) || (instr
->format
== Format::MIMG
&& i
== 1) ||
180 ((instr
->format
== Format::MUBUF
|| instr
->format
== Format::MTBUF
) && i
== 1);
181 check(can_be_undef
, "Undefs can only be used in certain operands", instr
.get());
183 check(instr
->operands
[i
].isFixed() || instr
->operands
[i
].isTemp() || instr
->operands
[i
].isConstant(), "Uninitialized Operand", instr
.get());
187 /* check subdword definitions */
188 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
189 if (instr
->definitions
[i
].regClass().is_subdword())
190 check(instr
->format
== Format::PSEUDO
|| instr
->definitions
[i
].bytes() <= 4, "Only Pseudo instructions can write subdword registers larger than 4 bytes", instr
.get());
193 if (instr
->isSALU() || instr
->isVALU()) {
196 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
198 Operand op
= instr
->operands
[i
];
202 check(instr
->format
== Format::SOP1
||
203 instr
->format
== Format::SOP2
||
204 instr
->format
== Format::SOPC
||
205 instr
->format
== Format::VOP1
||
206 instr
->format
== Format::VOP2
||
207 instr
->format
== Format::VOPC
||
208 (instr
->isVOP3() && program
->chip_class
>= GFX10
),
209 "Literal applied on wrong instruction format", instr
.get());
211 check(literal
.isUndefined() || (literal
.size() == op
.size() && literal
.constantValue() == op
.constantValue()), "Only 1 Literal allowed", instr
.get());
213 check(!instr
->isVALU() || instr
->isVOP3() || i
== 0 || i
== 2, "Wrong source position for Literal argument", instr
.get());
216 /* check num sgprs for VALU */
217 if (instr
->isVALU()) {
218 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
219 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
220 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
221 unsigned const_bus_limit
= 1;
222 if (program
->chip_class
>= GFX10
&& !is_shift64
)
225 uint32_t scalar_mask
= instr
->isVOP3() ? 0x7 : 0x5;
227 scalar_mask
= program
->chip_class
>= GFX9
? 0x7 : 0x4;
229 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
||
230 (int) instr
->format
& (int) Format::VOPC
||
231 instr
->opcode
== aco_opcode::v_readfirstlane_b32
||
232 instr
->opcode
== aco_opcode::v_readlane_b32
||
233 instr
->opcode
== aco_opcode::v_readlane_b32_e64
,
234 "Wrong Definition type for VALU instruction", instr
.get());
235 unsigned num_sgprs
= 0;
236 unsigned sgpr
[] = {0, 0};
237 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
239 Operand op
= instr
->operands
[i
];
240 if (instr
->opcode
== aco_opcode::v_readfirstlane_b32
||
241 instr
->opcode
== aco_opcode::v_readlane_b32
||
242 instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
243 instr
->opcode
== aco_opcode::v_writelane_b32
||
244 instr
->opcode
== aco_opcode::v_writelane_b32_e64
) {
245 check(!op
.isLiteral(), "No literal allowed on VALU instruction", instr
.get());
246 check(i
== 1 || (op
.isTemp() && op
.regClass().type() == RegType::vgpr
&& op
.bytes() <= 4), "Wrong Operand type for VALU instruction", instr
.get());
249 if (op
.isTemp() && instr
->operands
[i
].regClass().type() == RegType::sgpr
) {
250 check(scalar_mask
& (1 << i
), "Wrong source position for SGPR argument", instr
.get());
252 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
254 sgpr
[num_sgprs
++] = op
.tempId();
258 if (op
.isConstant() && !op
.isLiteral())
259 check(scalar_mask
& (1 << i
), "Wrong source position for constant argument", instr
.get());
261 check(num_sgprs
+ (literal
.isUndefined() ? 0 : 1) <= const_bus_limit
, "Too many SGPRs/literals", instr
.get());
264 if (instr
->format
== Format::SOP1
|| instr
->format
== Format::SOP2
) {
265 check(instr
->definitions
[0].getTemp().type() == RegType::sgpr
, "Wrong Definition type for SALU instruction", instr
.get());
266 for (const Operand
& op
: instr
->operands
) {
267 check(op
.isConstant() || op
.regClass().type() <= RegType::sgpr
,
268 "Wrong Operand type for SALU instruction", instr
.get());
273 switch (instr
->format
) {
274 case Format::PSEUDO
: {
275 if (instr
->opcode
== aco_opcode::p_create_vector
) {
277 for (const Operand
& op
: instr
->operands
) {
280 check(size
== instr
->definitions
[0].bytes(), "Definition size does not match operand sizes", instr
.get());
281 if (instr
->definitions
[0].getTemp().type() == RegType::sgpr
) {
282 for (const Operand
& op
: instr
->operands
) {
283 check(op
.isConstant() || op
.regClass().type() == RegType::sgpr
,
284 "Wrong Operand type for scalar vector", instr
.get());
287 } else if (instr
->opcode
== aco_opcode::p_extract_vector
) {
288 check((instr
->operands
[0].isTemp()) && instr
->operands
[1].isConstant(), "Wrong Operand types", instr
.get());
289 check((instr
->operands
[1].constantValue() + 1) * instr
->definitions
[0].bytes() <= instr
->operands
[0].bytes(), "Index out of range", instr
.get());
290 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
|| instr
->operands
[0].regClass().type() == RegType::sgpr
,
291 "Cannot extract SGPR value from VGPR vector", instr
.get());
292 } else if (instr
->opcode
== aco_opcode::p_parallelcopy
) {
293 check(instr
->definitions
.size() == instr
->operands
.size(), "Number of Operands does not match number of Definitions", instr
.get());
294 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
295 if (instr
->operands
[i
].isTemp())
296 check((instr
->definitions
[i
].getTemp().type() == instr
->operands
[i
].regClass().type()) ||
297 (instr
->definitions
[i
].getTemp().type() == RegType::vgpr
&& instr
->operands
[i
].regClass().type() == RegType::sgpr
),
298 "Operand and Definition types do not match", instr
.get());
300 } else if (instr
->opcode
== aco_opcode::p_phi
) {
301 check(instr
->operands
.size() == block
.logical_preds
.size(), "Number of Operands does not match number of predecessors", instr
.get());
302 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
|| instr
->definitions
[0].getTemp().regClass() == program
->lane_mask
, "Logical Phi Definition must be vgpr or divergent boolean", instr
.get());
303 } else if (instr
->opcode
== aco_opcode::p_linear_phi
) {
304 for (const Operand
& op
: instr
->operands
)
305 check(!op
.isTemp() || op
.getTemp().is_linear(), "Wrong Operand type", instr
.get());
306 check(instr
->operands
.size() == block
.linear_preds
.size(), "Number of Operands does not match number of predecessors", instr
.get());
311 if (instr
->operands
.size() >= 1)
312 check(instr
->operands
[0].isTemp() && instr
->operands
[0].regClass().type() == RegType::sgpr
, "SMEM operands must be sgpr", instr
.get());
313 if (instr
->operands
.size() >= 2)
314 check(instr
->operands
[1].isConstant() || (instr
->operands
[1].isTemp() && instr
->operands
[1].regClass().type() == RegType::sgpr
),
315 "SMEM offset must be constant or sgpr", instr
.get());
316 if (!instr
->definitions
.empty())
317 check(instr
->definitions
[0].getTemp().type() == RegType::sgpr
, "SMEM result must be sgpr", instr
.get());
321 case Format::MUBUF
: {
322 check(instr
->operands
.size() > 1, "VMEM instructions must have at least one operand", instr
.get());
323 check(instr
->operands
[1].hasRegClass() && instr
->operands
[1].regClass().type() == RegType::vgpr
,
324 "VADDR must be in vgpr for VMEM instructions", instr
.get());
325 check(instr
->operands
[0].isTemp() && instr
->operands
[0].regClass().type() == RegType::sgpr
, "VMEM resource constant must be sgpr", instr
.get());
326 check(instr
->operands
.size() < 4 || (instr
->operands
[3].isTemp() && instr
->operands
[3].regClass().type() == RegType::vgpr
), "VMEM write data must be vgpr", instr
.get());
330 check(instr
->operands
.size() == 3, "MIMG instructions must have exactly 3 operands", instr
.get());
331 check(instr
->operands
[0].hasRegClass() && (instr
->operands
[0].regClass() == s4
|| instr
->operands
[0].regClass() == s8
),
332 "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr
.get());
333 if (instr
->operands
[1].hasRegClass() && instr
->operands
[1].regClass().type() == RegType::sgpr
)
334 check(instr
->operands
[1].regClass() == s4
, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr
.get());
335 else if (instr
->operands
[1].hasRegClass() && instr
->operands
[1].regClass().type() == RegType::vgpr
)
336 check((instr
->definitions
.empty() || instr
->definitions
[0].regClass() == instr
->operands
[1].regClass() ||
337 instr
->opcode
== aco_opcode::image_atomic_cmpswap
|| instr
->opcode
== aco_opcode::image_atomic_fcmpswap
),
338 "MIMG operands[1] (VDATA) must be the same as definitions[0] for atomics", instr
.get());
339 check(instr
->operands
[2].hasRegClass() && instr
->operands
[2].regClass().type() == RegType::vgpr
,
340 "MIMG operands[2] (VADDR) must be VGPR", instr
.get());
341 check(instr
->definitions
.empty() || (instr
->definitions
[0].isTemp() && instr
->definitions
[0].regClass().type() == RegType::vgpr
),
342 "MIMG definitions[0] (VDATA) must be VGPR", instr
.get());
346 for (const Operand
& op
: instr
->operands
) {
347 check((op
.isTemp() && op
.regClass().type() == RegType::vgpr
) || op
.physReg() == m0
,
348 "Only VGPRs are valid DS instruction operands", instr
.get());
350 if (!instr
->definitions
.empty())
351 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
, "DS instruction must return VGPR", instr
.get());
355 for (unsigned i
= 0; i
< 4; i
++)
356 check(instr
->operands
[i
].hasRegClass() && instr
->operands
[i
].regClass().type() == RegType::vgpr
,
357 "Only VGPRs are valid Export arguments", instr
.get());
361 check(instr
->operands
[1].isUndefined(), "Flat instructions don't support SADDR", instr
.get());
364 case Format::SCRATCH
: {
365 check(instr
->operands
[0].isTemp() && instr
->operands
[0].regClass().type() == RegType::vgpr
, "FLAT/GLOBAL/SCRATCH address must be vgpr", instr
.get());
366 check(instr
->operands
[1].hasRegClass() && instr
->operands
[1].regClass().type() == RegType::sgpr
,
367 "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr
.get());
368 if (!instr
->definitions
.empty())
369 check(instr
->definitions
[0].getTemp().type() == RegType::vgpr
, "FLAT/GLOBAL/SCRATCH result must be vgpr", instr
.get());
371 check(instr
->operands
[2].regClass().type() == RegType::vgpr
, "FLAT/GLOBAL/SCRATCH data must be vgpr", instr
.get());
381 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++) {
382 Block
& block
= program
->blocks
[i
];
383 check_block(block
.index
== i
, "block.index must match actual index", &block
);
385 /* predecessors/successors should be sorted */
386 for (unsigned j
= 0; j
+ 1 < block
.linear_preds
.size(); j
++)
387 check_block(block
.linear_preds
[j
] < block
.linear_preds
[j
+ 1], "linear predecessors must be sorted", &block
);
388 for (unsigned j
= 0; j
+ 1 < block
.logical_preds
.size(); j
++)
389 check_block(block
.logical_preds
[j
] < block
.logical_preds
[j
+ 1], "logical predecessors must be sorted", &block
);
390 for (unsigned j
= 0; j
+ 1 < block
.linear_succs
.size(); j
++)
391 check_block(block
.linear_succs
[j
] < block
.linear_succs
[j
+ 1], "linear successors must be sorted", &block
);
392 for (unsigned j
= 0; j
+ 1 < block
.logical_succs
.size(); j
++)
393 check_block(block
.logical_succs
[j
] < block
.logical_succs
[j
+ 1], "logical successors must be sorted", &block
);
395 /* critical edges are not allowed */
396 if (block
.linear_preds
.size() > 1) {
397 for (unsigned pred
: block
.linear_preds
)
398 check_block(program
->blocks
[pred
].linear_succs
.size() == 1, "linear critical edges are not allowed", &program
->blocks
[pred
]);
399 for (unsigned pred
: block
.logical_preds
)
400 check_block(program
->blocks
[pred
].logical_succs
.size() == 1, "logical critical edges are not allowed", &program
->blocks
[pred
]);
411 Location() : block(NULL
), instr(NULL
) {}
414 Instruction
*instr
; //NULL if it's the block's live-in
423 bool ra_fail(FILE *output
, Location loc
, Location loc2
, const char *fmt
, ...) {
427 vsprintf(msg
, fmt
, args
);
430 fprintf(stderr
, "RA error found at instruction in BB%d:\n", loc
.block
->index
);
432 aco_print_instr(loc
.instr
, stderr
);
433 fprintf(stderr
, "\n%s", msg
);
435 fprintf(stderr
, "%s", msg
);
438 fprintf(stderr
, " in BB%d:\n", loc2
.block
->index
);
439 aco_print_instr(loc2
.instr
, stderr
);
441 fprintf(stderr
, "\n\n");
446 bool validate_subdword_operand(chip_class chip
, const aco_ptr
<Instruction
>& instr
, unsigned index
)
448 Operand op
= instr
->operands
[index
];
449 unsigned byte
= op
.physReg().byte();
451 if (instr
->format
== Format::PSEUDO
&& chip
>= GFX8
)
453 if (instr
->isSDWA() && (static_cast<SDWA_instruction
*>(instr
.get())->sel
[index
] & sdwa_asuint
) == (sdwa_isra
| op
.bytes()))
455 if (byte
== 2 && can_use_opsel(chip
, instr
->opcode
, index
, 1))
458 switch (instr
->opcode
) {
459 case aco_opcode::v_cvt_f32_ubyte1
:
463 case aco_opcode::v_cvt_f32_ubyte2
:
467 case aco_opcode::v_cvt_f32_ubyte3
:
471 case aco_opcode::ds_write_b8_d16_hi
:
472 case aco_opcode::ds_write_b16_d16_hi
:
473 if (byte
== 2 && index
== 1)
476 case aco_opcode::buffer_store_byte_d16_hi
:
477 case aco_opcode::buffer_store_short_d16_hi
:
478 if (byte
== 2 && index
== 3)
481 case aco_opcode::flat_store_byte_d16_hi
:
482 case aco_opcode::flat_store_short_d16_hi
:
483 case aco_opcode::scratch_store_byte_d16_hi
:
484 case aco_opcode::scratch_store_short_d16_hi
:
485 case aco_opcode::global_store_byte_d16_hi
:
486 case aco_opcode::global_store_short_d16_hi
:
487 if (byte
== 2 && index
== 2)
496 bool validate_subdword_definition(chip_class chip
, const aco_ptr
<Instruction
>& instr
)
498 Definition def
= instr
->definitions
[0];
499 unsigned byte
= def
.physReg().byte();
501 if (instr
->format
== Format::PSEUDO
&& chip
>= GFX8
)
503 if (instr
->isSDWA() && static_cast<SDWA_instruction
*>(instr
.get())->dst_sel
== (sdwa_isra
| def
.bytes()))
505 if (byte
== 2 && can_use_opsel(chip
, instr
->opcode
, -1, 1))
508 switch (instr
->opcode
) {
509 case aco_opcode::buffer_load_ubyte_d16_hi
:
510 case aco_opcode::buffer_load_short_d16_hi
:
511 case aco_opcode::flat_load_ubyte_d16_hi
:
512 case aco_opcode::flat_load_short_d16_hi
:
513 case aco_opcode::scratch_load_ubyte_d16_hi
:
514 case aco_opcode::scratch_load_short_d16_hi
:
515 case aco_opcode::global_load_ubyte_d16_hi
:
516 case aco_opcode::global_load_short_d16_hi
:
517 case aco_opcode::ds_read_u8_d16_hi
:
518 case aco_opcode::ds_read_u16_d16_hi
:
527 unsigned get_subdword_bytes_written(Program
*program
, const aco_ptr
<Instruction
>& instr
, unsigned index
)
529 chip_class chip
= program
->chip_class
;
530 Definition def
= instr
->definitions
[index
];
532 if (instr
->format
== Format::PSEUDO
)
533 return chip
>= GFX8
? def
.bytes() : def
.size() * 4u;
534 if (instr
->isSDWA() && static_cast<SDWA_instruction
*>(instr
.get())->dst_sel
== (sdwa_isra
| def
.bytes()))
537 switch (instr
->opcode
) {
538 case aco_opcode::buffer_load_ubyte_d16
:
539 case aco_opcode::buffer_load_short_d16
:
540 case aco_opcode::flat_load_ubyte_d16
:
541 case aco_opcode::flat_load_short_d16
:
542 case aco_opcode::scratch_load_ubyte_d16
:
543 case aco_opcode::scratch_load_short_d16
:
544 case aco_opcode::global_load_ubyte_d16
:
545 case aco_opcode::global_load_short_d16
:
546 case aco_opcode::ds_read_u8_d16
:
547 case aco_opcode::ds_read_u16_d16
:
548 case aco_opcode::buffer_load_ubyte_d16_hi
:
549 case aco_opcode::buffer_load_short_d16_hi
:
550 case aco_opcode::flat_load_ubyte_d16_hi
:
551 case aco_opcode::flat_load_short_d16_hi
:
552 case aco_opcode::scratch_load_ubyte_d16_hi
:
553 case aco_opcode::scratch_load_short_d16_hi
:
554 case aco_opcode::global_load_ubyte_d16_hi
:
555 case aco_opcode::global_load_short_d16_hi
:
556 case aco_opcode::ds_read_u8_d16_hi
:
557 case aco_opcode::ds_read_u16_d16_hi
:
558 return program
->sram_ecc_enabled
? 4 : 2;
559 case aco_opcode::v_mad_f16
:
560 case aco_opcode::v_mad_u16
:
561 case aco_opcode::v_mad_i16
:
562 case aco_opcode::v_fma_f16
:
563 case aco_opcode::v_div_fixup_f16
:
564 case aco_opcode::v_interp_p2_f16
:
571 return MAX2(chip
>= GFX10
? def
.bytes() : 4, instr_info
.definition_size
[(int)instr
->opcode
] / 8u);
574 } /* end namespace */
576 bool validate_ra(Program
*program
, const struct radv_nir_compiler_options
*options
, FILE *output
) {
577 if (!(debug_flags
& DEBUG_VALIDATE_RA
))
581 aco::live live_vars
= aco::live_var_analysis(program
, options
);
582 std::vector
<std::vector
<Temp
>> phi_sgpr_ops(program
->blocks
.size());
584 std::map
<unsigned, Assignment
> assignments
;
585 for (Block
& block
: program
->blocks
) {
588 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
589 if (instr
->opcode
== aco_opcode::p_phi
) {
590 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
591 if (instr
->operands
[i
].isTemp() &&
592 instr
->operands
[i
].getTemp().type() == RegType::sgpr
&&
593 instr
->operands
[i
].isFirstKill())
594 phi_sgpr_ops
[block
.logical_preds
[i
]].emplace_back(instr
->operands
[i
].getTemp());
598 loc
.instr
= instr
.get();
599 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
600 Operand
& op
= instr
->operands
[i
];
604 err
|= ra_fail(output
, loc
, Location(), "Operand %d is not assigned a register", i
);
605 if (assignments
.count(op
.tempId()) && assignments
[op
.tempId()].reg
!= op
.physReg())
606 err
|= ra_fail(output
, loc
, assignments
.at(op
.tempId()).firstloc
, "Operand %d has an inconsistent register assignment with instruction", i
);
607 if ((op
.getTemp().type() == RegType::vgpr
&& op
.physReg().reg_b
+ op
.bytes() > (256 + program
->config
->num_vgprs
) * 4) ||
608 (op
.getTemp().type() == RegType::sgpr
&& op
.physReg() + op
.size() > program
->config
->num_sgprs
&& op
.physReg() < program
->sgpr_limit
))
609 err
|= ra_fail(output
, loc
, assignments
.at(op
.tempId()).firstloc
, "Operand %d has an out-of-bounds register assignment", i
);
610 if (op
.physReg() == vcc
&& !program
->needs_vcc
)
611 err
|= ra_fail(output
, loc
, Location(), "Operand %d fixed to vcc but needs_vcc=false", i
);
612 if (op
.regClass().is_subdword() && !validate_subdword_operand(program
->chip_class
, instr
, i
))
613 err
|= ra_fail(output
, loc
, Location(), "Operand %d not aligned correctly", i
);
614 if (!assignments
[op
.tempId()].firstloc
.block
)
615 assignments
[op
.tempId()].firstloc
= loc
;
616 if (!assignments
[op
.tempId()].defloc
.block
)
617 assignments
[op
.tempId()].reg
= op
.physReg();
620 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
621 Definition
& def
= instr
->definitions
[i
];
625 err
|= ra_fail(output
, loc
, Location(), "Definition %d is not assigned a register", i
);
626 if (assignments
[def
.tempId()].defloc
.block
)
627 err
|= ra_fail(output
, loc
, assignments
.at(def
.tempId()).defloc
, "Temporary %%%d also defined by instruction", def
.tempId());
628 if ((def
.getTemp().type() == RegType::vgpr
&& def
.physReg().reg_b
+ def
.bytes() > (256 + program
->config
->num_vgprs
) * 4) ||
629 (def
.getTemp().type() == RegType::sgpr
&& def
.physReg() + def
.size() > program
->config
->num_sgprs
&& def
.physReg() < program
->sgpr_limit
))
630 err
|= ra_fail(output
, loc
, assignments
.at(def
.tempId()).firstloc
, "Definition %d has an out-of-bounds register assignment", i
);
631 if (def
.physReg() == vcc
&& !program
->needs_vcc
)
632 err
|= ra_fail(output
, loc
, Location(), "Definition %d fixed to vcc but needs_vcc=false", i
);
633 if (def
.regClass().is_subdword() && !validate_subdword_definition(program
->chip_class
, instr
))
634 err
|= ra_fail(output
, loc
, Location(), "Definition %d not aligned correctly", i
);
635 if (!assignments
[def
.tempId()].firstloc
.block
)
636 assignments
[def
.tempId()].firstloc
= loc
;
637 assignments
[def
.tempId()].defloc
= loc
;
638 assignments
[def
.tempId()].reg
= def
.physReg();
643 for (Block
& block
: program
->blocks
) {
647 std::array
<unsigned, 2048> regs
; /* register file in bytes */
651 live
.insert(live_vars
.live_out
[block
.index
].begin(), live_vars
.live_out
[block
.index
].end());
652 /* remove killed p_phi sgpr operands */
653 for (Temp tmp
: phi_sgpr_ops
[block
.index
])
657 for (Temp tmp
: live
) {
658 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
659 for (unsigned i
= 0; i
< tmp
.bytes(); i
++) {
660 if (regs
[reg
.reg_b
+ i
]) {
661 err
|= ra_fail(output
, loc
, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i
, tmp
.id(), regs
[reg
.reg_b
+ i
]);
663 regs
[reg
.reg_b
+ i
] = tmp
.id();
668 for (auto it
= block
.instructions
.rbegin(); it
!= block
.instructions
.rend(); ++it
) {
669 aco_ptr
<Instruction
>& instr
= *it
;
671 /* check killed p_phi sgpr operands */
672 if (instr
->opcode
== aco_opcode::p_logical_end
) {
673 for (Temp tmp
: phi_sgpr_ops
[block
.index
]) {
674 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
675 for (unsigned i
= 0; i
< tmp
.bytes(); i
++) {
676 if (regs
[reg
.reg_b
+ i
])
677 err
|= ra_fail(output
, loc
, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i
, tmp
.id(), regs
[reg
.reg_b
+ i
]);
683 for (const Definition
& def
: instr
->definitions
) {
686 live
.erase(def
.getTemp());
689 /* don't count phi operands as live-in, since they are actually
690 * killed when they are copied at the predecessor */
691 if (instr
->opcode
!= aco_opcode::p_phi
&& instr
->opcode
!= aco_opcode::p_linear_phi
) {
692 for (const Operand
& op
: instr
->operands
) {
695 live
.insert(op
.getTemp());
700 for (Temp tmp
: live
) {
701 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
702 for (unsigned i
= 0; i
< tmp
.bytes(); i
++)
703 regs
[reg
.reg_b
+ i
] = tmp
.id();
706 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
707 loc
.instr
= instr
.get();
709 /* remove killed p_phi operands from regs */
710 if (instr
->opcode
== aco_opcode::p_logical_end
) {
711 for (Temp tmp
: phi_sgpr_ops
[block
.index
]) {
712 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
713 for (unsigned i
= 0; i
< tmp
.bytes(); i
++)
714 regs
[reg
.reg_b
+ i
] = 0;
718 if (instr
->opcode
!= aco_opcode::p_phi
&& instr
->opcode
!= aco_opcode::p_linear_phi
) {
719 for (const Operand
& op
: instr
->operands
) {
722 if (op
.isFirstKillBeforeDef()) {
723 for (unsigned j
= 0; j
< op
.getTemp().bytes(); j
++)
724 regs
[op
.physReg().reg_b
+ j
] = 0;
729 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
730 Definition
& def
= instr
->definitions
[i
];
733 Temp tmp
= def
.getTemp();
734 PhysReg reg
= assignments
.at(tmp
.id()).reg
;
735 for (unsigned j
= 0; j
< tmp
.bytes(); j
++) {
736 if (regs
[reg
.reg_b
+ j
])
737 err
|= ra_fail(output
, loc
, assignments
.at(regs
[reg
.reg_b
+ j
]).defloc
, "Assignment of element %d of %%%d already taken by %%%d from instruction", i
, tmp
.id(), regs
[reg
.reg_b
+ j
]);
738 regs
[reg
.reg_b
+ j
] = tmp
.id();
740 if (def
.regClass().is_subdword() && def
.bytes() < 4) {
741 unsigned written
= get_subdword_bytes_written(program
, instr
, i
);
742 /* If written=4, the instruction still might write the upper half. In that case, it's the lower half that isn't preserved */
743 for (unsigned j
= reg
.byte() & ~(written
- 1); j
< written
; j
++) {
744 unsigned written_reg
= reg
.reg() * 4u + j
;
745 if (regs
[written_reg
] && regs
[written_reg
] != def
.tempId())
746 err
|= ra_fail(output
, loc
, assignments
.at(regs
[written_reg
]).defloc
, "Assignment of element %d of %%%d overwrites the full register taken by %%%d from instruction", i
, tmp
.id(), regs
[written_reg
]);
751 for (const Definition
& def
: instr
->definitions
) {
755 for (unsigned j
= 0; j
< def
.getTemp().bytes(); j
++)
756 regs
[def
.physReg().reg_b
+ j
] = 0;
760 if (instr
->opcode
!= aco_opcode::p_phi
&& instr
->opcode
!= aco_opcode::p_linear_phi
) {
761 for (const Operand
& op
: instr
->operands
) {
764 if (op
.isLateKill() && op
.isFirstKill()) {
765 for (unsigned j
= 0; j
< op
.getTemp().bytes(); j
++)
766 regs
[op
.physReg().reg_b
+ j
] = 0;