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28 BEGIN_TEST(optimize
.neg
)
29 for (unsigned i
= GFX9
; i
<= GFX10
; i
++) {
30 //>> v1: %a, v1: %b, s1: %c, s1: %d, s2: %_:exec = p_startpgm
31 if (!setup_cs("v1 v1 s1 s1", (chip_class
)i
))
34 //! v1: %res0 = v_mul_f32 %a, -%b
35 //! p_unit_test 0, %res0
36 Temp neg_b
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), inputs
[1]);
37 writeout(0, bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), inputs
[0], neg_b
));
39 //! v1: %neg_a = v_xor_b32 0x80000000, %a
40 //~gfx[6-9]! v1: %res1 = v_mul_f32 0x123456, %neg_a
41 //~gfx10! v1: %res1 = v_mul_f32 0x123456, -%a
42 //! p_unit_test 1, %res1
43 Temp neg_a
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), inputs
[0]);
44 writeout(1, bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x123456u
), neg_a
));
46 //! v1: %res2 = v_mul_f32 %a, %b
47 //! p_unit_test 2, %res2
48 Temp neg_neg_a
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), neg_a
);
49 writeout(2, bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), neg_neg_a
, inputs
[1]));
51 /* we could optimize this case into just an abs(), but NIR already does this */
52 //! v1: %res3 = v_mul_f32 |%neg_a|, %b
53 //! p_unit_test 3, %res3
54 Temp abs_neg_a
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), neg_a
);
55 writeout(3, bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), abs_neg_a
, inputs
[1]));
57 //! v1: %res4 = v_mul_f32 -|%a|, %b
58 //! p_unit_test 4, %res4
59 Temp abs_a
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), inputs
[0]);
60 Temp neg_abs_a
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), abs_a
);
61 writeout(4, bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), neg_abs_a
, inputs
[1]));
63 //! v1: %res5 = v_mul_f32 -%a, %b row_shl:1 bound_ctrl:1
64 //! p_unit_test 5, %res5
65 writeout(5, bld
.vop2_dpp(aco_opcode::v_mul_f32
, bld
.def(v1
), neg_a
, inputs
[1], dpp_row_sl(1)));
67 //! v1: %res6 = v_subrev_f32 %a, %b
68 //! p_unit_test 6, %res6
69 writeout(6, bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), neg_a
, inputs
[1]));
71 //! v1: %res7 = v_sub_f32 %b, %a
72 //! p_unit_test 7, %res7
73 writeout(7, bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), inputs
[1], neg_a
));
75 //! v1: %res8 = v_mul_f32 %a, -%c
76 //! p_unit_test 8, %res8
77 Temp neg_c
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), bld
.copy(bld
.def(v1
), inputs
[2]));
78 writeout(8, bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), inputs
[0], neg_c
));