2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
25 /* based on pieces from si_pipe.c and radeon_llvm_emit.c */
26 #include "ac_llvm_util.h"
27 #include "ac_llvm_build.h"
28 #include "util/bitscan.h"
29 #include <llvm-c/Core.h>
30 #include <llvm-c/Support.h>
31 #include <llvm-c/Transforms/IPO.h>
32 #include <llvm-c/Transforms/Scalar.h>
33 #include <llvm-c/Transforms/Utils.h>
34 #include "c11/threads.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_math.h"
42 static void ac_init_llvm_target()
44 LLVMInitializeAMDGPUTargetInfo();
45 LLVMInitializeAMDGPUTarget();
46 LLVMInitializeAMDGPUTargetMC();
47 LLVMInitializeAMDGPUAsmPrinter();
49 /* For inline assembly. */
50 LLVMInitializeAMDGPUAsmParser();
52 /* For ACO disassembly. */
53 LLVMInitializeAMDGPUDisassembler();
55 /* Workaround for bug in llvm 4.0 that causes image intrinsics
57 * https://reviews.llvm.org/D26348
59 * "mesa" is the prefix for error messages.
61 * -global-isel-abort=2 is a no-op unless global isel has been enabled.
62 * This option tells the backend to fall-back to SelectionDAG and print
63 * a diagnostic message if global isel fails.
65 const char *argv
[] = {
67 "-simplifycfg-sink-common=false",
68 "-global-isel-abort=2",
69 #if LLVM_VERSION_MAJOR >= 10
70 /* Atomic optimizations require LLVM 10.0 for gfx10 support. */
71 "-amdgpu-atomic-optimizations=true",
74 LLVMParseCommandLineOptions(ARRAY_SIZE(argv
), argv
, NULL
);
77 static once_flag ac_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
79 void ac_init_llvm_once(void)
81 call_once(&ac_init_llvm_target_once_flag
, ac_init_llvm_target
);
84 static LLVMTargetRef
ac_get_llvm_target(const char *triple
)
86 LLVMTargetRef target
= NULL
;
87 char *err_message
= NULL
;
89 if (LLVMGetTargetFromTriple(triple
, &target
, &err_message
)) {
90 fprintf(stderr
, "Cannot find target for triple %s ", triple
);
92 fprintf(stderr
, "%s\n", err_message
);
94 LLVMDisposeMessage(err_message
);
100 const char *ac_get_llvm_processor_name(enum radeon_family family
)
161 static LLVMTargetMachineRef
ac_create_target_machine(enum radeon_family family
,
162 enum ac_target_machine_options tm_options
,
163 LLVMCodeGenOptLevel level
,
164 const char **out_triple
)
166 assert(family
>= CHIP_TAHITI
);
168 const char *triple
= (tm_options
& AC_TM_SUPPORTS_SPILL
) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
169 LLVMTargetRef target
= ac_get_llvm_target(triple
);
171 snprintf(features
, sizeof(features
),
172 "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s",
173 family
>= CHIP_NAVI10
&& !(tm_options
& AC_TM_WAVE32
) ?
174 ",+wavefrontsize64,-wavefrontsize32" : "",
175 tm_options
& AC_TM_SISCHED
? ",+si-scheduler" : "",
176 tm_options
& AC_TM_FORCE_ENABLE_XNACK
? ",+xnack" : "",
177 tm_options
& AC_TM_FORCE_DISABLE_XNACK
? ",-xnack" : "",
178 tm_options
& AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
? ",-promote-alloca" : "",
179 tm_options
& AC_TM_NO_LOAD_STORE_OPT
? ",-load-store-opt" : "");
181 LLVMTargetMachineRef tm
= LLVMCreateTargetMachine(
184 ac_get_llvm_processor_name(family
),
188 LLVMCodeModelDefault
);
191 *out_triple
= triple
;
192 if (tm_options
& AC_TM_ENABLE_GLOBAL_ISEL
)
193 ac_enable_global_isel(tm
);
197 static LLVMPassManagerRef
ac_create_passmgr(LLVMTargetLibraryInfoRef target_library_info
,
200 LLVMPassManagerRef passmgr
= LLVMCreatePassManager();
204 if (target_library_info
)
205 LLVMAddTargetLibraryInfo(target_library_info
,
209 LLVMAddVerifierPass(passmgr
);
210 LLVMAddAlwaysInlinerPass(passmgr
);
211 /* Normally, the pass manager runs all passes on one function before
212 * moving onto another. Adding a barrier no-op pass forces the pass
213 * manager to run the inliner on all functions first, which makes sure
214 * that the following passes are only run on the remaining non-inline
215 * function, so it removes useless work done on dead inline functions.
217 ac_llvm_add_barrier_noop_pass(passmgr
);
218 /* This pass should eliminate all the load and store instructions. */
219 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
220 LLVMAddScalarReplAggregatesPass(passmgr
);
221 LLVMAddLICMPass(passmgr
);
222 LLVMAddAggressiveDCEPass(passmgr
);
223 LLVMAddCFGSimplificationPass(passmgr
);
224 /* This is recommended by the instruction combining pass. */
225 LLVMAddEarlyCSEMemSSAPass(passmgr
);
226 LLVMAddInstructionCombiningPass(passmgr
);
230 static const char *attr_to_str(enum ac_func_attr attr
)
233 case AC_FUNC_ATTR_ALWAYSINLINE
: return "alwaysinline";
234 case AC_FUNC_ATTR_INREG
: return "inreg";
235 case AC_FUNC_ATTR_NOALIAS
: return "noalias";
236 case AC_FUNC_ATTR_NOUNWIND
: return "nounwind";
237 case AC_FUNC_ATTR_READNONE
: return "readnone";
238 case AC_FUNC_ATTR_READONLY
: return "readonly";
239 case AC_FUNC_ATTR_WRITEONLY
: return "writeonly";
240 case AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY
: return "inaccessiblememonly";
241 case AC_FUNC_ATTR_CONVERGENT
: return "convergent";
243 fprintf(stderr
, "Unhandled function attribute: %x\n", attr
);
249 ac_add_function_attr(LLVMContextRef ctx
, LLVMValueRef function
,
250 int attr_idx
, enum ac_func_attr attr
)
252 const char *attr_name
= attr_to_str(attr
);
253 unsigned kind_id
= LLVMGetEnumAttributeKindForName(attr_name
,
255 LLVMAttributeRef llvm_attr
= LLVMCreateEnumAttribute(ctx
, kind_id
, 0);
257 if (LLVMIsAFunction(function
))
258 LLVMAddAttributeAtIndex(function
, attr_idx
, llvm_attr
);
260 LLVMAddCallSiteAttribute(function
, attr_idx
, llvm_attr
);
263 void ac_add_func_attributes(LLVMContextRef ctx
, LLVMValueRef function
,
264 unsigned attrib_mask
)
266 attrib_mask
|= AC_FUNC_ATTR_NOUNWIND
;
267 attrib_mask
&= ~AC_FUNC_ATTR_LEGACY
;
269 while (attrib_mask
) {
270 enum ac_func_attr attr
= 1u << u_bit_scan(&attrib_mask
);
271 ac_add_function_attr(ctx
, function
, -1, attr
);
276 ac_dump_module(LLVMModuleRef module
)
278 char *str
= LLVMPrintModuleToString(module
);
279 fprintf(stderr
, "%s", str
);
280 LLVMDisposeMessage(str
);
284 ac_llvm_add_target_dep_function_attr(LLVMValueRef F
,
285 const char *name
, unsigned value
)
289 snprintf(str
, sizeof(str
), "0x%x", value
);
290 LLVMAddTargetDependentFunctionAttr(F
, name
, str
);
293 void ac_llvm_set_workgroup_size(LLVMValueRef F
, unsigned size
)
299 snprintf(str
, sizeof(str
), "%u,%u", size
, size
);
300 LLVMAddTargetDependentFunctionAttr(F
, "amdgpu-flat-work-group-size", str
);
304 ac_count_scratch_private_memory(LLVMValueRef function
)
306 unsigned private_mem_vgprs
= 0;
308 /* Process all LLVM instructions. */
309 LLVMBasicBlockRef bb
= LLVMGetFirstBasicBlock(function
);
311 LLVMValueRef next
= LLVMGetFirstInstruction(bb
);
314 LLVMValueRef inst
= next
;
315 next
= LLVMGetNextInstruction(next
);
317 if (LLVMGetInstructionOpcode(inst
) != LLVMAlloca
)
320 LLVMTypeRef type
= LLVMGetElementType(LLVMTypeOf(inst
));
321 /* No idea why LLVM aligns allocas to 4 elements. */
322 unsigned alignment
= LLVMGetAlignment(inst
);
323 unsigned dw_size
= align(ac_get_type_size(type
) / 4, alignment
);
324 private_mem_vgprs
+= dw_size
;
326 bb
= LLVMGetNextBasicBlock(bb
);
329 return private_mem_vgprs
;
333 ac_init_llvm_compiler(struct ac_llvm_compiler
*compiler
,
334 enum radeon_family family
,
335 enum ac_target_machine_options tm_options
)
338 memset(compiler
, 0, sizeof(*compiler
));
340 compiler
->tm
= ac_create_target_machine(family
, tm_options
,
341 LLVMCodeGenLevelDefault
,
346 if (tm_options
& AC_TM_CREATE_LOW_OPT
) {
347 compiler
->low_opt_tm
=
348 ac_create_target_machine(family
, tm_options
,
349 LLVMCodeGenLevelLess
, NULL
);
350 if (!compiler
->low_opt_tm
)
354 if (family
>= CHIP_NAVI10
) {
355 assert(!(tm_options
& AC_TM_CREATE_LOW_OPT
));
356 compiler
->tm_wave32
= ac_create_target_machine(family
,
357 tm_options
| AC_TM_WAVE32
,
358 LLVMCodeGenLevelDefault
,
360 if (!compiler
->tm_wave32
)
364 compiler
->target_library_info
=
365 ac_create_target_library_info(triple
);
366 if (!compiler
->target_library_info
)
369 compiler
->passmgr
= ac_create_passmgr(compiler
->target_library_info
,
370 tm_options
& AC_TM_CHECK_IR
);
371 if (!compiler
->passmgr
)
376 ac_destroy_llvm_compiler(compiler
);
381 ac_destroy_llvm_compiler(struct ac_llvm_compiler
*compiler
)
383 ac_destroy_llvm_passes(compiler
->passes
);
384 ac_destroy_llvm_passes(compiler
->passes_wave32
);
385 ac_destroy_llvm_passes(compiler
->low_opt_passes
);
387 if (compiler
->passmgr
)
388 LLVMDisposePassManager(compiler
->passmgr
);
389 if (compiler
->target_library_info
)
390 ac_dispose_target_library_info(compiler
->target_library_info
);
391 if (compiler
->low_opt_tm
)
392 LLVMDisposeTargetMachine(compiler
->low_opt_tm
);
394 LLVMDisposeTargetMachine(compiler
->tm
);
395 if (compiler
->tm_wave32
)
396 LLVMDisposeTargetMachine(compiler
->tm_wave32
);