src/amd/llvm/ac_llvm_util.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial portions
  22  * of the Software.
  23  *
  24  */
  25 /* based on pieces from si_pipe.c and radeon_llvm_emit.c */
  26 #include "ac_llvm_util.h"
  27 #include "ac_llvm_build.h"
  28 #include "util/bitscan.h"
  29 #include <llvm-c/Core.h>
  30 #include <llvm-c/Support.h>
  31 #include <llvm-c/Transforms/IPO.h>
  32 #include <llvm-c/Transforms/Scalar.h>
  33 #include <llvm-c/Transforms/Utils.h>
  34 #include "c11/threads.h"
  35 #include "gallivm/lp_bld_misc.h"
  36 #include "util/u_math.h"
  37
  38 #include <assert.h>
  39 #include <stdio.h>
  40 #include <string.h>
  41
  42 static void ac_init_llvm_target()
  43 {
  44         LLVMInitializeAMDGPUTargetInfo();
  45         LLVMInitializeAMDGPUTarget();
  46         LLVMInitializeAMDGPUTargetMC();
  47         LLVMInitializeAMDGPUAsmPrinter();
  48
  49         /* For inline assembly. */
  50         LLVMInitializeAMDGPUAsmParser();
  51
  52         /* For ACO disassembly. */
  53         LLVMInitializeAMDGPUDisassembler();
  54
  55         /* Workaround for bug in llvm 4.0 that causes image intrinsics
  56          * to disappear.
  57          * https://reviews.llvm.org/D26348
  58          *
  59          * "mesa" is the prefix for error messages.
  60          *
  61          * -global-isel-abort=2 is a no-op unless global isel has been enabled.
  62          * This option tells the backend to fall-back to SelectionDAG and print
  63          * a diagnostic message if global isel fails.
  64          */
  65         const char *argv[] = {
  66                 "mesa",
  67                 "-simplifycfg-sink-common=false",
  68                 "-global-isel-abort=2",
  69 #if LLVM_VERSION_MAJOR >= 10
  70                 /* Atomic optimizations require LLVM 10.0 for gfx10 support. */
  71                 "-amdgpu-atomic-optimizations=true",
  72 #endif
  73 #if LLVM_VERSION_MAJOR >= 11
  74                 /* This was disabled by default in: https://reviews.llvm.org/D77228 */
  75                 "-structurizecfg-skip-uniform-regions",
  76 #endif
  77         };
  78         LLVMParseCommandLineOptions(ARRAY_SIZE(argv), argv, NULL);
  79 }
  80
  81 static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
  82
  83 void ac_init_llvm_once(void)
  84 {
  85         call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
  86 }
  87
  88 static LLVMTargetRef ac_get_llvm_target(const char *triple)
  89 {
  90         LLVMTargetRef target = NULL;
  91         char *err_message = NULL;
  92
  93         if (LLVMGetTargetFromTriple(triple, &target, &err_message)) {
  94                 fprintf(stderr, "Cannot find target for triple %s ", triple);
  95                 if (err_message) {
  96                         fprintf(stderr, "%s\n", err_message);
  97                 }
  98                 LLVMDisposeMessage(err_message);
  99                 return NULL;
 100         }
 101         return target;
 102 }
 103
 104 const char *ac_get_llvm_processor_name(enum radeon_family family)
 105 {
 106         switch (family) {
 107         case CHIP_TAHITI:
 108                 return "tahiti";
 109         case CHIP_PITCAIRN:
 110                 return "pitcairn";
 111         case CHIP_VERDE:
 112                 return "verde";
 113         case CHIP_OLAND:
 114                 return "oland";
 115         case CHIP_HAINAN:
 116                 return "hainan";
 117         case CHIP_BONAIRE:
 118                 return "bonaire";
 119         case CHIP_KABINI:
 120                 return "kabini";
 121         case CHIP_KAVERI:
 122                 return "kaveri";
 123         case CHIP_HAWAII:
 124                 return "hawaii";
 125         case CHIP_TONGA:
 126                 return "tonga";
 127         case CHIP_ICELAND:
 128                 return "iceland";
 129         case CHIP_CARRIZO:
 130                 return "carrizo";
 131         case CHIP_FIJI:
 132                 return "fiji";
 133         case CHIP_STONEY:
 134                 return "stoney";
 135         case CHIP_POLARIS10:
 136                 return "polaris10";
 137         case CHIP_POLARIS11:
 138         case CHIP_POLARIS12:
 139         case CHIP_VEGAM:
 140                 return "polaris11";
 141         case CHIP_VEGA10:
 142                 return "gfx900";
 143         case CHIP_RAVEN:
 144                 return "gfx902";
 145         case CHIP_VEGA12:
 146                 return "gfx904";
 147         case CHIP_VEGA20:
 148                 return "gfx906";
 149         case CHIP_RAVEN2:
 150         case CHIP_RENOIR:
 151                 return "gfx909";
 152         case CHIP_ARCTURUS:
 153                 return "gfx908";
 154         case CHIP_NAVI10:
 155                 return "gfx1010";
 156         case CHIP_NAVI12:
 157                 return "gfx1011";
 158         case CHIP_NAVI14:
 159                 return "gfx1012";
 160         default:
 161                 return "";
 162         }
 163 }
 164
 165 static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
 166                                                      enum ac_target_machine_options tm_options,
 167                                                      LLVMCodeGenOptLevel level,
 168                                                      const char **out_triple)
 169 {
 170         assert(family >= CHIP_TAHITI);
 171         char features[256];
 172         const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
 173         LLVMTargetRef target = ac_get_llvm_target(triple);
 174
 175         snprintf(features, sizeof(features),
 176                  "+DumpCode%s%s%s%s%s%s",
 177                  LLVM_VERSION_MAJOR >= 11 ? "" : ",-fp32-denormals,+fp64-denormals",
 178                  family >= CHIP_NAVI10 && !(tm_options & AC_TM_WAVE32) ?
 179                          ",+wavefrontsize64,-wavefrontsize32" : "",
 180                  tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
 181                  tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
 182                  tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",
 183                  tm_options & AC_TM_NO_LOAD_STORE_OPT ? ",-load-store-opt" : "");
 184
 185         LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
 186                                      target,
 187                                      triple,
 188                                      ac_get_llvm_processor_name(family),
 189                                      features,
 190                                      level,
 191                                      LLVMRelocDefault,
 192                                      LLVMCodeModelDefault);
 193
 194         if (out_triple)
 195                 *out_triple = triple;
 196         if (tm_options & AC_TM_ENABLE_GLOBAL_ISEL)
 197                 ac_enable_global_isel(tm);
 198         return tm;
 199 }
 200
 201 static LLVMPassManagerRef ac_create_passmgr(LLVMTargetLibraryInfoRef target_library_info,
 202                                             bool check_ir)
 203 {
 204         LLVMPassManagerRef passmgr = LLVMCreatePassManager();
 205         if (!passmgr)
 206                 return NULL;
 207
 208         if (target_library_info)
 209                 LLVMAddTargetLibraryInfo(target_library_info,
 210                                          passmgr);
 211
 212         if (check_ir)
 213                 LLVMAddVerifierPass(passmgr);
 214         LLVMAddAlwaysInlinerPass(passmgr);
 215         /* Normally, the pass manager runs all passes on one function before
 216          * moving onto another. Adding a barrier no-op pass forces the pass
 217          * manager to run the inliner on all functions first, which makes sure
 218          * that the following passes are only run on the remaining non-inline
 219          * function, so it removes useless work done on dead inline functions.
 220          */
 221         ac_llvm_add_barrier_noop_pass(passmgr);
 222         /* This pass should eliminate all the load and store instructions. */
 223         LLVMAddPromoteMemoryToRegisterPass(passmgr);
 224         LLVMAddScalarReplAggregatesPass(passmgr);
 225         LLVMAddLICMPass(passmgr);
 226         LLVMAddAggressiveDCEPass(passmgr);
 227         LLVMAddCFGSimplificationPass(passmgr);
 228         /* This is recommended by the instruction combining pass. */
 229         LLVMAddEarlyCSEMemSSAPass(passmgr);
 230         LLVMAddInstructionCombiningPass(passmgr);
 231         return passmgr;
 232 }
 233
 234 static const char *attr_to_str(enum ac_func_attr attr)
 235 {
 236    switch (attr) {
 237    case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
 238    case AC_FUNC_ATTR_INREG: return "inreg";
 239    case AC_FUNC_ATTR_NOALIAS: return "noalias";
 240    case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
 241    case AC_FUNC_ATTR_READNONE: return "readnone";
 242    case AC_FUNC_ATTR_READONLY: return "readonly";
 243    case AC_FUNC_ATTR_WRITEONLY: return "writeonly";
 244    case AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return "inaccessiblememonly";
 245    case AC_FUNC_ATTR_CONVERGENT: return "convergent";
 246    default:
 247            fprintf(stderr, "Unhandled function attribute: %x\n", attr);
 248            return 0;
 249    }
 250 }
 251
 252 void
 253 ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
 254                      int attr_idx, enum ac_func_attr attr)
 255 {
 256    const char *attr_name = attr_to_str(attr);
 257    unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
 258                                                       strlen(attr_name));
 259    LLVMAttributeRef llvm_attr = LLVMCreateEnumAttribute(ctx, kind_id, 0);
 260
 261    if (LLVMIsAFunction(function))
 262       LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
 263    else
 264       LLVMAddCallSiteAttribute(function, attr_idx, llvm_attr);
 265 }
 266
 267 void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,
 268                             unsigned attrib_mask)
 269 {
 270         attrib_mask |= AC_FUNC_ATTR_NOUNWIND;
 271         attrib_mask &= ~AC_FUNC_ATTR_LEGACY;
 272
 273         while (attrib_mask) {
 274                 enum ac_func_attr attr = 1u << u_bit_scan(&attrib_mask);
 275                 ac_add_function_attr(ctx, function, -1, attr);
 276         }
 277 }
 278
 279 void
 280 ac_dump_module(LLVMModuleRef module)
 281 {
 282         char *str = LLVMPrintModuleToString(module);
 283         fprintf(stderr, "%s", str);
 284         LLVMDisposeMessage(str);
 285 }
 286
 287 void
 288 ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
 289                                      const char *name, unsigned value)
 290 {
 291         char str[16];
 292
 293         snprintf(str, sizeof(str), "0x%x", value);
 294         LLVMAddTargetDependentFunctionAttr(F, name, str);
 295 }
 296
 297 void ac_llvm_set_workgroup_size(LLVMValueRef F, unsigned size)
 298 {
 299         if (!size)
 300                 return;
 301
 302         char str[32];
 303         snprintf(str, sizeof(str), "%u,%u", size, size);
 304         LLVMAddTargetDependentFunctionAttr(F, "amdgpu-flat-work-group-size", str);
 305 }
 306
 307 unsigned
 308 ac_count_scratch_private_memory(LLVMValueRef function)
 309 {
 310         unsigned private_mem_vgprs = 0;
 311
 312         /* Process all LLVM instructions. */
 313         LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(function);
 314         while (bb) {
 315                 LLVMValueRef next = LLVMGetFirstInstruction(bb);
 316
 317                 while (next) {
 318                         LLVMValueRef inst = next;
 319                         next = LLVMGetNextInstruction(next);
 320
 321                         if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
 322                                 continue;
 323
 324                         LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
 325                         /* No idea why LLVM aligns allocas to 4 elements. */
 326                         unsigned alignment = LLVMGetAlignment(inst);
 327                         unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
 328                         private_mem_vgprs += dw_size;
 329                 }
 330                 bb = LLVMGetNextBasicBlock(bb);
 331         }
 332
 333         return private_mem_vgprs;
 334 }
 335
 336 bool
 337 ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
 338                       enum radeon_family family,
 339                       enum ac_target_machine_options tm_options)
 340 {
 341         const char *triple;
 342         memset(compiler, 0, sizeof(*compiler));
 343
 344         compiler->tm = ac_create_target_machine(family, tm_options,
 345                                                 LLVMCodeGenLevelDefault,
 346                                                 &triple);
 347         if (!compiler->tm)
 348                 return false;
 349
 350         if (tm_options & AC_TM_CREATE_LOW_OPT) {
 351                 compiler->low_opt_tm =
 352                         ac_create_target_machine(family, tm_options,
 353                                                  LLVMCodeGenLevelLess, NULL);
 354                 if (!compiler->low_opt_tm)
 355                         goto fail;
 356         }
 357
 358         if (family >= CHIP_NAVI10) {
 359                 assert(!(tm_options & AC_TM_CREATE_LOW_OPT));
 360                 compiler->tm_wave32 = ac_create_target_machine(family,
 361                                                                tm_options | AC_TM_WAVE32,
 362                                                                LLVMCodeGenLevelDefault,
 363                                                                NULL);
 364                 if (!compiler->tm_wave32)
 365                         goto fail;
 366         }
 367
 368         compiler->target_library_info =
 369                 ac_create_target_library_info(triple);
 370         if (!compiler->target_library_info)
 371                 goto fail;
 372
 373         compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
 374                                               tm_options & AC_TM_CHECK_IR);
 375         if (!compiler->passmgr)
 376                 goto fail;
 377
 378         return true;
 379 fail:
 380         ac_destroy_llvm_compiler(compiler);
 381         return false;
 382 }
 383
 384 void
 385 ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler)
 386 {
 387         ac_destroy_llvm_passes(compiler->passes);
 388         ac_destroy_llvm_passes(compiler->passes_wave32);
 389         ac_destroy_llvm_passes(compiler->low_opt_passes);
 390
 391         if (compiler->passmgr)
 392                 LLVMDisposePassManager(compiler->passmgr);
 393         if (compiler->target_library_info)
 394                 ac_dispose_target_library_info(compiler->target_library_info);
 395         if (compiler->low_opt_tm)
 396                 LLVMDisposeTargetMachine(compiler->low_opt_tm);
 397         if (compiler->tm)
 398                 LLVMDisposeTargetMachine(compiler->tm);
 399         if (compiler->tm_wave32)
 400                 LLVMDisposeTargetMachine(compiler->tm_wave32);
 401 }