5 {"name": "ARRAY_LINEAR_GENERAL", "value": 0},
6 {"name": "ARRAY_LINEAR_ALIGNED", "value": 1},
7 {"name": "ARRAY_1D_TILED_THIN1", "value": 2},
8 {"name": "ARRAY_1D_TILED_THICK", "value": 3},
9 {"name": "ARRAY_2D_TILED_THIN1", "value": 4},
10 {"name": "ARRAY_PRT_TILED_THIN1", "value": 5},
11 {"name": "ARRAY_PRT_2D_TILED_THIN1", "value": 6},
12 {"name": "ARRAY_2D_TILED_THICK", "value": 7},
13 {"name": "ARRAY_2D_TILED_XTHICK", "value": 8},
14 {"name": "ARRAY_PRT_TILED_THICK", "value": 9},
15 {"name": "ARRAY_PRT_2D_TILED_THICK", "value": 10},
16 {"name": "ARRAY_PRT_3D_TILED_THIN1", "value": 11},
17 {"name": "ARRAY_3D_TILED_THIN1", "value": 12},
18 {"name": "ARRAY_3D_TILED_THICK", "value": 13},
19 {"name": "ARRAY_3D_TILED_XTHICK", "value": 14},
20 {"name": "ARRAY_PRT_3D_TILED_THICK", "value": 15}
25 {"name": "ADDR_SURF_BANK_HEIGHT_1", "value": 0},
26 {"name": "ADDR_SURF_BANK_HEIGHT_2", "value": 1},
27 {"name": "ADDR_SURF_BANK_HEIGHT_4", "value": 2},
28 {"name": "ADDR_SURF_BANK_HEIGHT_8", "value": 3}
33 {"name": "ADDR_SURF_BANK_WIDTH_1", "value": 0},
34 {"name": "ADDR_SURF_BANK_WIDTH_2", "value": 1},
35 {"name": "ADDR_SURF_BANK_WIDTH_4", "value": 2},
36 {"name": "ADDR_SURF_BANK_WIDTH_8", "value": 3}
41 {"name": "BIN_MAP_MODE_NONE", "value": 0},
42 {"name": "BIN_MAP_MODE_RTA_INDEX", "value": 1},
43 {"name": "BIN_MAP_MODE_POPS", "value": 2}
48 {"name": "BIN_SIZE_32_PIXELS", "value": 0},
49 {"name": "BIN_SIZE_64_PIXELS", "value": 1},
50 {"name": "BIN_SIZE_128_PIXELS", "value": 2},
51 {"name": "BIN_SIZE_256_PIXELS", "value": 3},
52 {"name": "BIN_SIZE_512_PIXELS", "value": 4}
57 {"name": "BINNING_ALLOWED", "value": 0},
58 {"name": "FORCE_BINNING_ON", "value": 1},
59 {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2},
60 {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3}
65 {"name": "BLEND_ZERO", "value": 0},
66 {"name": "BLEND_ONE", "value": 1},
67 {"name": "BLEND_SRC_COLOR", "value": 2},
68 {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
69 {"name": "BLEND_SRC_ALPHA", "value": 4},
70 {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
71 {"name": "BLEND_DST_ALPHA", "value": 6},
72 {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
73 {"name": "BLEND_DST_COLOR", "value": 8},
74 {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
75 {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
76 {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
77 {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
78 {"name": "BLEND_CONSTANT_COLOR", "value": 13},
79 {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
80 {"name": "BLEND_SRC1_COLOR", "value": 15},
81 {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
82 {"name": "BLEND_SRC1_ALPHA", "value": 17},
83 {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
84 {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
85 {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
90 {"name": "FORCE_OPT_AUTO", "value": 0},
91 {"name": "FORCE_OPT_DISABLE", "value": 1},
92 {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
93 {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
94 {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
95 {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
96 {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
97 {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
102 {"name": "CB_DISABLE", "value": 0},
103 {"name": "CB_NORMAL", "value": 1},
104 {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
105 {"name": "CB_RESOLVE", "value": 3},
106 {"name": "CB_DECOMPRESS", "value": 4},
107 {"name": "CB_FMASK_DECOMPRESS", "value": 5},
108 {"name": "CB_DCC_DECOMPRESS", "value": 6},
109 {"name": "CB_RESERVED", "value": 7}
112 "CBPerfClearFilterSel": {
114 {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
115 {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}
118 "CBPerfOpFilterSel": {
120 {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},
121 {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
122 {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
123 {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
124 {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
125 {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
128 "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE": {
130 {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
131 {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
132 {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
135 "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE": {
137 {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
138 {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
143 {"name": "OUT", "value": 1},
144 {"name": "IN_0", "value": 2},
145 {"name": "IN_1", "value": 4},
146 {"name": "IN_10", "value": 8},
147 {"name": "IN_2", "value": 16},
148 {"name": "IN_20", "value": 32},
149 {"name": "IN_21", "value": 64},
150 {"name": "IN_210", "value": 128},
151 {"name": "IN_3", "value": 256},
152 {"name": "IN_30", "value": 512},
153 {"name": "IN_31", "value": 1024},
154 {"name": "IN_310", "value": 2048},
155 {"name": "IN_32", "value": 4096},
156 {"name": "IN_320", "value": 8192},
157 {"name": "IN_321", "value": 16384},
158 {"name": "IN_3210", "value": 32768}
161 "CP_PERFMON_ENABLE_MODE": {
163 {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
164 {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
165 {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
166 {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
169 "CP_PERFMON_STATE": {
171 {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
172 {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
173 {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
174 {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
175 {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
176 {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
181 {"name": "CMASK_ADDR_TILED", "value": 0},
182 {"name": "CMASK_ADDR_LINEAR", "value": 1},
183 {"name": "CMASK_ADDR_COMPATIBLE", "value": 2}
188 {"name": "COLOR_INVALID", "value": 0},
189 {"name": "COLOR_8", "value": 1},
190 {"name": "COLOR_16", "value": 2},
191 {"name": "COLOR_8_8", "value": 3},
192 {"name": "COLOR_32", "value": 4},
193 {"name": "COLOR_16_16", "value": 5},
194 {"name": "COLOR_10_11_11", "value": 6},
195 {"name": "COLOR_11_11_10", "value": 7},
196 {"name": "COLOR_10_10_10_2", "value": 8},
197 {"name": "COLOR_2_10_10_10", "value": 9},
198 {"name": "COLOR_8_8_8_8", "value": 10},
199 {"name": "COLOR_32_32", "value": 11},
200 {"name": "COLOR_16_16_16_16", "value": 12},
201 {"name": "COLOR_RESERVED_13", "value": 13},
202 {"name": "COLOR_32_32_32_32", "value": 14},
203 {"name": "COLOR_RESERVED_15", "value": 15},
204 {"name": "COLOR_5_6_5", "value": 16},
205 {"name": "COLOR_1_5_5_5", "value": 17},
206 {"name": "COLOR_5_5_5_1", "value": 18},
207 {"name": "COLOR_4_4_4_4", "value": 19},
208 {"name": "COLOR_8_24", "value": 20},
209 {"name": "COLOR_24_8", "value": 21},
210 {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
211 {"name": "COLOR_RESERVED_23", "value": 23},
212 {"name": "COLOR_RESERVED_24", "value": 24},
213 {"name": "COLOR_RESERVED_25", "value": 25},
214 {"name": "COLOR_RESERVED_26", "value": 26},
215 {"name": "COLOR_RESERVED_27", "value": 27},
216 {"name": "COLOR_RESERVED_28", "value": 28},
217 {"name": "COLOR_RESERVED_29", "value": 29},
218 {"name": "COLOR_RESERVED_30", "value": 30},
219 {"name": "COLOR_2_10_10_10_6E4", "value": 31}
224 {"name": "COMB_DST_PLUS_SRC", "value": 0},
225 {"name": "COMB_SRC_MINUS_DST", "value": 1},
226 {"name": "COMB_MIN_DST_SRC", "value": 2},
227 {"name": "COMB_MAX_DST_SRC", "value": 3},
228 {"name": "COMB_DST_MINUS_SRC", "value": 4}
233 {"name": "FRAG_NEVER", "value": 0},
234 {"name": "FRAG_LESS", "value": 1},
235 {"name": "FRAG_EQUAL", "value": 2},
236 {"name": "FRAG_LEQUAL", "value": 3},
237 {"name": "FRAG_GREATER", "value": 4},
238 {"name": "FRAG_NOTEQUAL", "value": 5},
239 {"name": "FRAG_GEQUAL", "value": 6},
240 {"name": "FRAG_ALWAYS", "value": 7}
243 "ConservativeZExport": {
245 {"name": "EXPORT_ANY_Z", "value": 0},
246 {"name": "EXPORT_LESS_THAN_Z", "value": 1},
247 {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
248 {"name": "EXPORT_RESERVED", "value": 3}
253 {"name": "INPUT_COVERAGE", "value": 0},
254 {"name": "INPUT_INNER_COVERAGE", "value": 1},
255 {"name": "INPUT_DEPTH_COVERAGE", "value": 2},
256 {"name": "RAW", "value": 3}
259 "DB_DFSM_CONTROL__PUNCHOUT_MODE": {
261 {"name": "AUTO", "value": 0},
262 {"name": "FORCE_ON", "value": 1},
263 {"name": "FORCE_OFF", "value": 2},
264 {"name": "RESERVED", "value": 3}
267 "DbPRTFaultBehavior": {
269 {"name": "FAULT_ZERO", "value": 0},
270 {"name": "FAULT_ONE", "value": 1},
271 {"name": "FAULT_FAIL", "value": 2},
272 {"name": "FAULT_PASS", "value": 3}
277 {"name": "PSLC_AUTO", "value": 0},
278 {"name": "PSLC_ON_HANG_ONLY", "value": 1},
279 {"name": "PSLC_ASAP", "value": 2},
280 {"name": "PSLC_COUNTDOWN", "value": 3}
285 {"name": "INVALID", "value": 1},
286 {"name": "INPUT_DENORMAL", "value": 2},
287 {"name": "DIVIDE_BY_ZERO", "value": 4},
288 {"name": "OVERFLOW", "value": 8},
289 {"name": "UNDERFLOW", "value": 16},
290 {"name": "INEXACT", "value": 32},
291 {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
292 {"name": "ADDRESS_WATCH", "value": 128},
293 {"name": "MEMORY_VIOLATION", "value": 256}
298 {"name": "FP_32_DENORMS", "value": 48},
299 {"name": "FP_64_DENORMS", "value": 192},
300 {"name": "FP_ALL_DENORMS", "value": 240}
305 {"name": "FORCE_OFF", "value": 0},
306 {"name": "FORCE_ENABLE", "value": 1},
307 {"name": "FORCE_DISABLE", "value": 2},
308 {"name": "FORCE_RESERVED", "value": 3}
313 {"name": "ADDR_SURF_MACRO_ASPECT_1", "value": 0},
314 {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},
315 {"name": "ADDR_SURF_MACRO_ASPECT_4", "value": 2},
316 {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}
321 {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
322 {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
323 {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
324 {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},
325 {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}
330 {"name": "ADDR_SURF_2_BANK", "value": 0},
331 {"name": "ADDR_SURF_4_BANK", "value": 1},
332 {"name": "ADDR_SURF_8_BANK", "value": 2},
333 {"name": "ADDR_SURF_16_BANK", "value": 3}
336 "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
338 {"name": "X_DRAW_POINTS", "value": 0},
339 {"name": "X_DRAW_LINES", "value": 1},
340 {"name": "X_DRAW_TRIANGLES", "value": 2}
343 "PA_SU_SC_MODE_CNTL__POLY_MODE": {
345 {"name": "X_DISABLE_POLY_MODE", "value": 0},
346 {"name": "X_DUAL_MODE", "value": 1}
349 "PA_SU_VTX_CNTL__ROUND_MODE": {
351 {"name": "X_TRUNCATE", "value": 0},
352 {"name": "X_ROUND", "value": 1},
353 {"name": "X_ROUND_TO_EVEN", "value": 2},
354 {"name": "X_ROUND_TO_ODD", "value": 3}
359 {"name": "ADDR_SURF_P2", "value": 0},
360 {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},
361 {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},
362 {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},
363 {"name": "ADDR_SURF_P4_8x16", "value": 4},
364 {"name": "ADDR_SURF_P4_16x16", "value": 5},
365 {"name": "ADDR_SURF_P4_16x32", "value": 6},
366 {"name": "ADDR_SURF_P4_32x32", "value": 7},
367 {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},
368 {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},
369 {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},
370 {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},
371 {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},
372 {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},
373 {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},
374 {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},
375 {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},
376 {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17},
377 {"name": "ADDR_SURF_P16", "value": 18}
382 {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
383 {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
384 {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
385 {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
390 {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
391 {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
392 {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
393 {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
398 {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
399 {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
400 {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
401 {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
406 {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
407 {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
408 {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
409 {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
414 {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
415 {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
416 {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
417 {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
418 {"name": "X_16_8_FIXED_POINT_1", "value": 4},
419 {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
420 {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
421 {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
426 {"name": "ROP3_CLEAR", "value": 0},
427 {"name": "X_0X05", "value": 5},
428 {"name": "X_0X0A", "value": 10},
429 {"name": "X_0X0F", "value": 15},
430 {"name": "ROP3_NOR", "value": 17},
431 {"name": "ROP3_AND_INVERTED", "value": 34},
432 {"name": "ROP3_COPY_INVERTED", "value": 51},
433 {"name": "ROP3_AND_REVERSE", "value": 68},
434 {"name": "X_0X50", "value": 80},
435 {"name": "ROP3_INVERT", "value": 85},
436 {"name": "X_0X5A", "value": 90},
437 {"name": "X_0X5F", "value": 95},
438 {"name": "ROP3_XOR", "value": 102},
439 {"name": "ROP3_NAND", "value": 119},
440 {"name": "ROP3_AND", "value": 136},
441 {"name": "ROP3_EQUIVALENT", "value": 153},
442 {"name": "X_0XA0", "value": 160},
443 {"name": "X_0XA5", "value": 165},
444 {"name": "ROP3_NO_OP", "value": 170},
445 {"name": "X_0XAF", "value": 175},
446 {"name": "ROP3_OR_INVERTED", "value": 187},
447 {"name": "ROP3_COPY", "value": 204},
448 {"name": "ROP3_OR_REVERSE", "value": 221},
449 {"name": "ROP3_OR", "value": 238},
450 {"name": "X_0XF0", "value": 240},
451 {"name": "X_0XF5", "value": 245},
452 {"name": "X_0XFA", "value": 250},
453 {"name": "ROP3_SET", "value": 255}
458 {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
459 {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
460 {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
461 {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
466 {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
467 {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
472 {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
473 {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
474 {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
475 {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
480 {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
481 {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
486 {"name": "CACHE_LRU_RD", "value": 0},
487 {"name": "CACHE_NOA", "value": 1},
488 {"name": "UNCACHED_RD", "value": 2},
489 {"name": "RESERVED_RDPOLICY", "value": 3}
492 "SPI_PNT_SPRITE_OVERRIDE": {
494 {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
495 {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
496 {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
497 {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
498 {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
501 "SPI_SHADER_EX_FORMAT": {
503 {"name": "SPI_SHADER_ZERO", "value": 0},
504 {"name": "SPI_SHADER_32_R", "value": 1},
505 {"name": "SPI_SHADER_32_GR", "value": 2},
506 {"name": "SPI_SHADER_32_AR", "value": 3},
507 {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
508 {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
509 {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
510 {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
511 {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
512 {"name": "SPI_SHADER_32_ABGR", "value": 9}
515 "SPI_SHADER_FORMAT": {
517 {"name": "SPI_SHADER_NONE", "value": 0},
518 {"name": "SPI_SHADER_1COMP", "value": 1},
519 {"name": "SPI_SHADER_2COMP", "value": 2},
520 {"name": "SPI_SHADER_4COMPRESS", "value": 3},
521 {"name": "SPI_SHADER_4COMP", "value": 4}
524 "SPM_PERFMON_STATE": {
526 {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
527 {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
528 {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
529 {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
530 {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
531 {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
536 {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
537 {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
538 {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
539 {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
540 {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
541 {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
542 {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
543 {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
546 "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
548 {"name": "EXACT", "value": 0},
549 {"name": "11BIT_FORMAT", "value": 1},
550 {"name": "10BIT_FORMAT", "value": 3},
551 {"name": "8BIT_FORMAT", "value": 6},
552 {"name": "6BIT_FORMAT", "value": 11},
553 {"name": "5BIT_FORMAT", "value": 13},
554 {"name": "4BIT_FORMAT", "value": 15}
557 "SX_DOWNCONVERT_FORMAT": {
559 {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
560 {"name": "SX_RT_EXPORT_32_R", "value": 1},
561 {"name": "SX_RT_EXPORT_32_A", "value": 2},
562 {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
563 {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
564 {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
565 {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
566 {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
567 {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
568 {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
569 {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}
574 {"name": "OPT_COMB_NONE", "value": 0},
575 {"name": "OPT_COMB_ADD", "value": 1},
576 {"name": "OPT_COMB_SUBTRACT", "value": 2},
577 {"name": "OPT_COMB_MIN", "value": 3},
578 {"name": "OPT_COMB_MAX", "value": 4},
579 {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
580 {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
581 {"name": "OPT_COMB_SAFE_ADD", "value": 7}
586 {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
587 {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
588 {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
589 {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
592 "ScUncertaintyRegionMode": {
594 {"name": "SC_HALF_LSB", "value": 0},
595 {"name": "SC_LSB_ONE_SIDED", "value": 1},
596 {"name": "SC_LSB_TWO_SIDED", "value": 2}
601 {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
602 {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
603 {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
604 {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
609 {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
610 {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
611 {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
612 {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
617 {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
618 {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
619 {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
620 {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
625 {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
626 {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
627 {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
628 {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
633 {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
634 {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
635 {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
636 {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
641 {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
642 {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
643 {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
644 {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
649 {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
650 {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
651 {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
652 {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
657 {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
658 {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
659 {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
660 {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
665 {"name": "STENCIL_INVALID", "value": 0},
666 {"name": "STENCIL_8", "value": 1}
671 {"name": "STENCIL_KEEP", "value": 0},
672 {"name": "STENCIL_ZERO", "value": 1},
673 {"name": "STENCIL_ONES", "value": 2},
674 {"name": "STENCIL_REPLACE_TEST", "value": 3},
675 {"name": "STENCIL_REPLACE_OP", "value": 4},
676 {"name": "STENCIL_ADD_CLAMP", "value": 5},
677 {"name": "STENCIL_SUB_CLAMP", "value": 6},
678 {"name": "STENCIL_INVERT", "value": 7},
679 {"name": "STENCIL_ADD_WRAP", "value": 8},
680 {"name": "STENCIL_SUB_WRAP", "value": 9},
681 {"name": "STENCIL_AND", "value": 10},
682 {"name": "STENCIL_OR", "value": 11},
683 {"name": "STENCIL_XOR", "value": 12},
684 {"name": "STENCIL_NAND", "value": 13},
685 {"name": "STENCIL_NOR", "value": 14},
686 {"name": "STENCIL_XNOR", "value": 15}
691 {"name": "ENDIAN_NONE", "value": 0},
692 {"name": "ENDIAN_8IN16", "value": 1},
693 {"name": "ENDIAN_8IN32", "value": 2},
694 {"name": "ENDIAN_8IN64", "value": 3}
699 {"name": "NUMBER_UNORM", "value": 0},
700 {"name": "NUMBER_SNORM", "value": 1},
701 {"name": "NUMBER_USCALED", "value": 2},
702 {"name": "NUMBER_SSCALED", "value": 3},
703 {"name": "NUMBER_UINT", "value": 4},
704 {"name": "NUMBER_SINT", "value": 5},
705 {"name": "NUMBER_SRGB", "value": 6},
706 {"name": "NUMBER_FLOAT", "value": 7}
711 {"name": "SWAP_STD", "value": 0},
712 {"name": "SWAP_ALT", "value": 1},
713 {"name": "SWAP_STD_REV", "value": 2},
714 {"name": "SWAP_ALT_REV", "value": 3}
717 "ThreadTraceRegInclude": {
719 {"name": "REG_INCLUDE_SQDEC", "value": 1},
720 {"name": "REG_INCLUDE_SHDEC", "value": 2},
721 {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
722 {"name": "REG_INCLUDE_COMP", "value": 8},
723 {"name": "REG_INCLUDE_CONTEXT", "value": 16},
724 {"name": "REG_INCLUDE_CONFIG", "value": 32},
725 {"name": "REG_INCLUDE_OTHER", "value": 64},
726 {"name": "REG_INCLUDE_READS", "value": 128}
729 "ThreadTraceTokenExclude": {
731 {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
732 {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
733 {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
734 {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
735 {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
736 {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
737 {"name": "TOKEN_EXCLUDE_REG", "value": 64},
738 {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
739 {"name": "TOKEN_EXCLUDE_INST", "value": 256},
740 {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
741 {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
742 {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
747 {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},
748 {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},
749 {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},
750 {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},
751 {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},
752 {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},
753 {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}
758 {"name": "PRE_CLAMP_TF1", "value": 0},
759 {"name": "POST_CLAMP_TF1", "value": 1},
760 {"name": "DISABLE_TF1", "value": 2}
765 {"name": "PRE_CLAMP_TF0", "value": 0},
766 {"name": "POST_CLAMP_TF0", "value": 1},
767 {"name": "DISABLE_TF0", "value": 2}
772 {"name": "NO_DIST", "value": 0},
773 {"name": "PATCHES", "value": 1},
774 {"name": "DONUTS", "value": 2},
775 {"name": "TRAPEZOIDS", "value": 3}
778 "VGT_DI_MAJOR_MODE_SELECT": {
780 {"name": "DI_MAJOR_MODE_0", "value": 0},
781 {"name": "DI_MAJOR_MODE_1", "value": 1}
784 "VGT_DI_PRIM_TYPE": {
786 {"name": "DI_PT_NONE", "value": 0},
787 {"name": "DI_PT_POINTLIST", "value": 1},
788 {"name": "DI_PT_LINELIST", "value": 2},
789 {"name": "DI_PT_LINESTRIP", "value": 3},
790 {"name": "DI_PT_TRILIST", "value": 4},
791 {"name": "DI_PT_TRIFAN", "value": 5},
792 {"name": "DI_PT_TRISTRIP", "value": 6},
793 {"name": "DI_PT_2D_RECTANGLE", "value": 7},
794 {"name": "DI_PT_UNUSED_1", "value": 8},
795 {"name": "DI_PT_PATCH", "value": 9},
796 {"name": "DI_PT_LINELIST_ADJ", "value": 10},
797 {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
798 {"name": "DI_PT_TRILIST_ADJ", "value": 12},
799 {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
800 {"name": "DI_PT_UNUSED_3", "value": 14},
801 {"name": "DI_PT_UNUSED_4", "value": 15},
802 {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
803 {"name": "DI_PT_RECTLIST", "value": 17},
804 {"name": "DI_PT_LINELOOP", "value": 18},
805 {"name": "DI_PT_QUADLIST", "value": 19},
806 {"name": "DI_PT_QUADSTRIP", "value": 20},
807 {"name": "DI_PT_POLYGON", "value": 21}
810 "VGT_DI_SOURCE_SELECT": {
812 {"name": "DI_SRC_SEL_DMA", "value": 0},
813 {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
814 {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
815 {"name": "DI_SRC_SEL_RESERVED", "value": 3}
818 "VGT_DMA_BUF_TYPE": {
820 {"name": "VGT_DMA_BUF_MEM", "value": 0},
821 {"name": "VGT_DMA_BUF_RING", "value": 1},
822 {"name": "VGT_DMA_BUF_SETUP", "value": 2},
823 {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
826 "VGT_DMA_SWAP_MODE": {
828 {"name": "VGT_DMA_SWAP_NONE", "value": 0},
829 {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
830 {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
831 {"name": "VGT_DMA_SWAP_WORD", "value": 3}
836 {"name": "Reserved_0x00", "value": 0},
837 {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
838 {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
839 {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
840 {"name": "CACHE_FLUSH_TS", "value": 4},
841 {"name": "CONTEXT_DONE", "value": 5},
842 {"name": "CACHE_FLUSH", "value": 6},
843 {"name": "CS_PARTIAL_FLUSH", "value": 7},
844 {"name": "VGT_STREAMOUT_SYNC", "value": 8},
845 {"name": "SET_FE_ID", "value": 9},
846 {"name": "VGT_STREAMOUT_RESET", "value": 10},
847 {"name": "END_OF_PIPE_INCR_DE", "value": 11},
848 {"name": "END_OF_PIPE_IB_END", "value": 12},
849 {"name": "RST_PIX_CNT", "value": 13},
850 {"name": "BREAK_BATCH", "value": 14},
851 {"name": "VS_PARTIAL_FLUSH", "value": 15},
852 {"name": "PS_PARTIAL_FLUSH", "value": 16},
853 {"name": "FLUSH_HS_OUTPUT", "value": 17},
854 {"name": "FLUSH_DFSM", "value": 18},
855 {"name": "RESET_TO_LOWEST_VGT", "value": 19},
856 {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
857 {"name": "ZPASS_DONE", "value": 21},
858 {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
859 {"name": "PERFCOUNTER_START", "value": 23},
860 {"name": "PERFCOUNTER_STOP", "value": 24},
861 {"name": "PIPELINESTAT_START", "value": 25},
862 {"name": "PIPELINESTAT_STOP", "value": 26},
863 {"name": "PERFCOUNTER_SAMPLE", "value": 27},
864 {"name": "FLUSH_ES_OUTPUT", "value": 28},
865 {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
866 {"name": "SAMPLE_PIPELINESTAT", "value": 30},
867 {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
868 {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
869 {"name": "RESET_VTX_CNT", "value": 33},
870 {"name": "BLOCK_CONTEXT_DONE", "value": 34},
871 {"name": "CS_CONTEXT_DONE", "value": 35},
872 {"name": "VGT_FLUSH", "value": 36},
873 {"name": "TGID_ROLLOVER", "value": 37},
874 {"name": "SQ_NON_EVENT", "value": 38},
875 {"name": "SC_SEND_DB_VPZ", "value": 39},
876 {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
877 {"name": "FLUSH_SX_TS", "value": 41},
878 {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
879 {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
880 {"name": "FLUSH_AND_INV_DB_META", "value": 44},
881 {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
882 {"name": "FLUSH_AND_INV_CB_META", "value": 46},
883 {"name": "CS_DONE", "value": 47},
884 {"name": "PS_DONE", "value": 48},
885 {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
886 {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
887 {"name": "THREAD_TRACE_START", "value": 51},
888 {"name": "THREAD_TRACE_STOP", "value": 52},
889 {"name": "THREAD_TRACE_MARKER", "value": 53},
890 {"name": "THREAD_TRACE_DRAW", "value": 54},
891 {"name": "THREAD_TRACE_FINISH", "value": 55},
892 {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
893 {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
894 {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
895 {"name": "CONTEXT_SUSPEND", "value": 59},
896 {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
897 {"name": "ENABLE_NGG_PIPELINE", "value": 61},
898 {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
899 {"name": "DRAW_DONE", "value": 63}
904 {"name": "GS_CUT_1024", "value": 0},
905 {"name": "GS_CUT_512", "value": 1},
906 {"name": "GS_CUT_256", "value": 2},
907 {"name": "GS_CUT_128", "value": 3}
910 "VGT_GS_MODE_TYPE": {
912 {"name": "GS_OFF", "value": 0},
913 {"name": "GS_SCENARIO_A", "value": 1},
914 {"name": "GS_SCENARIO_B", "value": 2},
915 {"name": "GS_SCENARIO_G", "value": 3},
916 {"name": "GS_SCENARIO_C", "value": 4},
917 {"name": "SPRITE_EN", "value": 5}
920 "VGT_GS_OUTPRIM_TYPE": {
922 {"name": "POINTLIST", "value": 0},
923 {"name": "LINESTRIP", "value": 1},
924 {"name": "TRISTRIP", "value": 2},
925 {"name": "RECTLIST", "value": 3}
928 "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
930 {"name": "X_8K_DWORDS", "value": 0},
931 {"name": "X_4K_DWORDS", "value": 1},
932 {"name": "X_2K_DWORDS", "value": 2},
933 {"name": "X_1K_DWORDS", "value": 3}
936 "VGT_INDEX_TYPE_MODE": {
938 {"name": "VGT_INDEX_16", "value": 0},
939 {"name": "VGT_INDEX_32", "value": 1},
940 {"name": "VGT_INDEX_8", "value": 2}
943 "VGT_RDREQ_POLICY": {
945 {"name": "VGT_POLICY_LRU", "value": 0},
946 {"name": "VGT_POLICY_STREAM", "value": 1},
947 {"name": "VGT_POLICY_BYPASS", "value": 2}
950 "VGT_STAGES_ES_EN": {
952 {"name": "ES_STAGE_OFF", "value": 0},
953 {"name": "ES_STAGE_DS", "value": 1},
954 {"name": "ES_STAGE_REAL", "value": 2},
955 {"name": "RESERVED_ES", "value": 3}
958 "VGT_STAGES_GS_EN": {
960 {"name": "GS_STAGE_OFF", "value": 0},
961 {"name": "GS_STAGE_ON", "value": 1}
964 "VGT_STAGES_HS_EN": {
966 {"name": "HS_STAGE_OFF", "value": 0},
967 {"name": "HS_STAGE_ON", "value": 1}
970 "VGT_STAGES_LS_EN": {
972 {"name": "LS_STAGE_OFF", "value": 0},
973 {"name": "LS_STAGE_ON", "value": 1},
974 {"name": "CS_STAGE_ON", "value": 2},
975 {"name": "RESERVED_LS", "value": 3}
978 "VGT_STAGES_VS_EN": {
980 {"name": "VS_STAGE_REAL", "value": 0},
981 {"name": "VS_STAGE_DS", "value": 1},
982 {"name": "VS_STAGE_COPY_SHADER", "value": 2},
983 {"name": "RESERVED_VS", "value": 3}
986 "VGT_TESS_PARTITION": {
988 {"name": "PART_INTEGER", "value": 0},
989 {"name": "PART_POW2", "value": 1},
990 {"name": "PART_FRAC_ODD", "value": 2},
991 {"name": "PART_FRAC_EVEN", "value": 3}
994 "VGT_TESS_TOPOLOGY": {
996 {"name": "OUTPUT_POINT", "value": 0},
997 {"name": "OUTPUT_LINE", "value": 1},
998 {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
999 {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1004 {"name": "TESS_ISOLINE", "value": 0},
1005 {"name": "TESS_TRIANGLE", "value": 1},
1006 {"name": "TESS_QUAD", "value": 2}
1011 {"name": "CACHE_LRU_WR", "value": 0},
1012 {"name": "CACHE_STREAM", "value": 1},
1013 {"name": "CACHE_BYPASS", "value": 2},
1014 {"name": "UNCACHED_WR", "value": 3}
1019 {"name": "Z_INVALID", "value": 0},
1020 {"name": "Z_16", "value": 1},
1021 {"name": "Z_24", "value": 2},
1022 {"name": "Z_32_FLOAT", "value": 3}
1027 {"name": "FORCE_SUMM_OFF", "value": 0},
1028 {"name": "FORCE_SUMM_MINZ", "value": 1},
1029 {"name": "FORCE_SUMM_MAXZ", "value": 2},
1030 {"name": "FORCE_SUMM_BOTH", "value": 3}
1035 {"name": "LATE_Z", "value": 0},
1036 {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
1037 {"name": "RE_Z", "value": 2},
1038 {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
1042 "register_mappings": [
1045 "map": {"at": 1028, "to": "mm"},
1046 "name": "SQ_WAVE_MODE",
1047 "type_ref": "SQ_WAVE_MODE"
1051 "map": {"at": 1032, "to": "mm"},
1052 "name": "SQ_WAVE_STATUS",
1053 "type_ref": "SQ_WAVE_STATUS"
1057 "map": {"at": 1036, "to": "mm"},
1058 "name": "SQ_WAVE_TRAPSTS",
1059 "type_ref": "SQ_WAVE_TRAPSTS"
1063 "map": {"at": 1040, "to": "mm"},
1064 "name": "SQ_WAVE_HW_ID_LEGACY",
1065 "type_ref": "SQ_WAVE_HW_ID_LEGACY"
1069 "map": {"at": 1044, "to": "mm"},
1070 "name": "SQ_WAVE_GPR_ALLOC",
1071 "type_ref": "SQ_WAVE_GPR_ALLOC"
1075 "map": {"at": 1048, "to": "mm"},
1076 "name": "SQ_WAVE_LDS_ALLOC",
1077 "type_ref": "SQ_WAVE_LDS_ALLOC"
1081 "map": {"at": 1052, "to": "mm"},
1082 "name": "SQ_WAVE_IB_STS",
1083 "type_ref": "SQ_WAVE_IB_STS"
1087 "map": {"at": 1056, "to": "mm"},
1088 "name": "SQ_WAVE_PC_LO",
1089 "type_ref": "SQ_WAVE_PC_LO"
1093 "map": {"at": 1060, "to": "mm"},
1094 "name": "SQ_WAVE_PC_HI",
1095 "type_ref": "SQ_WAVE_PC_HI"
1099 "map": {"at": 1064, "to": "mm"},
1100 "name": "SQ_WAVE_INST_DW0",
1101 "type_ref": "SQ_WAVE_INST_DW0"
1105 "map": {"at": 1076, "to": "mm"},
1106 "name": "SQ_WAVE_IB_DBG1",
1107 "type_ref": "SQ_WAVE_IB_DBG1"
1111 "map": {"at": 1080, "to": "mm"},
1112 "name": "SQ_WAVE_FLUSH_IB",
1113 "type_ref": "SQ_WAVE_FLUSH_IB"
1117 "map": {"at": 1116, "to": "mm"},
1118 "name": "SQ_WAVE_HW_ID1",
1119 "type_ref": "SQ_WAVE_HW_ID1"
1123 "map": {"at": 1120, "to": "mm"},
1124 "name": "SQ_WAVE_HW_ID2",
1125 "type_ref": "SQ_WAVE_HW_ID2"
1129 "map": {"at": 1124, "to": "mm"},
1130 "name": "SQ_WAVE_POPS_PACKER",
1131 "type_ref": "SQ_WAVE_POPS_PACKER"
1135 "map": {"at": 1128, "to": "mm"},
1136 "name": "SQ_WAVE_SCHED_MODE",
1137 "type_ref": "SQ_WAVE_SCHED_MODE"
1141 "map": {"at": 1132, "to": "mm"},
1142 "name": "SQ_WAVE_VGPR_OFFSET",
1143 "type_ref": "SQ_WAVE_VGPR_OFFSET"
1147 "map": {"at": 1136, "to": "mm"},
1148 "name": "SQ_WAVE_IB_STS2",
1149 "type_ref": "SQ_WAVE_IB_STS2"
1153 "map": {"at": 2480, "to": "mm"},
1154 "name": "SQ_WAVE_TTMP0",
1155 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1159 "map": {"at": 2484, "to": "mm"},
1160 "name": "SQ_WAVE_TTMP1",
1161 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1165 "map": {"at": 2488, "to": "mm"},
1166 "name": "SQ_WAVE_TTMP2",
1167 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1171 "map": {"at": 2492, "to": "mm"},
1172 "name": "SQ_WAVE_TTMP3",
1173 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1177 "map": {"at": 2496, "to": "mm"},
1178 "name": "SQ_WAVE_TTMP4",
1179 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1183 "map": {"at": 2500, "to": "mm"},
1184 "name": "SQ_WAVE_TTMP5",
1185 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1189 "map": {"at": 2504, "to": "mm"},
1190 "name": "SQ_WAVE_TTMP6",
1191 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1195 "map": {"at": 2508, "to": "mm"},
1196 "name": "SQ_WAVE_TTMP7",
1197 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1201 "map": {"at": 2512, "to": "mm"},
1202 "name": "SQ_WAVE_TTMP8",
1203 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1207 "map": {"at": 2516, "to": "mm"},
1208 "name": "SQ_WAVE_TTMP9",
1209 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1213 "map": {"at": 2520, "to": "mm"},
1214 "name": "SQ_WAVE_TTMP10",
1215 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1219 "map": {"at": 2524, "to": "mm"},
1220 "name": "SQ_WAVE_TTMP11",
1221 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1225 "map": {"at": 2528, "to": "mm"},
1226 "name": "SQ_WAVE_TTMP12",
1227 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1231 "map": {"at": 2532, "to": "mm"},
1232 "name": "SQ_WAVE_TTMP13",
1233 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1237 "map": {"at": 2536, "to": "mm"},
1238 "name": "SQ_WAVE_TTMP14",
1239 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1243 "map": {"at": 2540, "to": "mm"},
1244 "name": "SQ_WAVE_TTMP15",
1245 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1249 "map": {"at": 2544, "to": "mm"},
1250 "name": "SQ_WAVE_M0",
1251 "type_ref": "SQ_WAVE_M0"
1255 "map": {"at": 2552, "to": "mm"},
1256 "name": "SQ_WAVE_EXEC_LO",
1257 "type_ref": "SQ_WAVE_EXEC_LO"
1261 "map": {"at": 2556, "to": "mm"},
1262 "name": "SQ_WAVE_EXEC_HI",
1263 "type_ref": "SQ_WAVE_EXEC_HI"
1267 "map": {"at": 2560, "to": "mm"},
1268 "name": "SQ_WAVE_FLAT_SCRATCH_LO",
1269 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1273 "map": {"at": 2564, "to": "mm"},
1274 "name": "SQ_WAVE_FLAT_SCRATCH_HI",
1275 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1279 "map": {"at": 2568, "to": "mm"},
1280 "name": "SQ_WAVE_FLAT_XNACK_MASK",
1281 "type_ref": "SQ_WAVE_FLAT_XNACK_MASK"
1285 "map": {"at": 32776, "to": "mm"},
1286 "name": "GRBM_STATUS2",
1287 "type_ref": "GRBM_STATUS2"
1291 "map": {"at": 32784, "to": "mm"},
1292 "name": "GRBM_STATUS",
1293 "type_ref": "GRBM_STATUS"
1297 "map": {"at": 32788, "to": "mm"},
1298 "name": "GRBM_STATUS_SE0",
1299 "type_ref": "GRBM_STATUS_SE0"
1303 "map": {"at": 32792, "to": "mm"},
1304 "name": "GRBM_STATUS_SE1",
1305 "type_ref": "GRBM_STATUS_SE0"
1309 "map": {"at": 32796, "to": "mm"},
1310 "name": "GRBM_STATUS3",
1311 "type_ref": "GRBM_STATUS3"
1315 "map": {"at": 32824, "to": "mm"},
1316 "name": "GRBM_STATUS_SE2",
1317 "type_ref": "GRBM_STATUS_SE0"
1321 "map": {"at": 32828, "to": "mm"},
1322 "name": "GRBM_STATUS_SE3",
1323 "type_ref": "GRBM_STATUS_SE0"
1327 "map": {"at": 33296, "to": "mm"},
1328 "name": "CP_CPC_STATUS",
1329 "type_ref": "CP_CPC_STATUS"
1333 "map": {"at": 33300, "to": "mm"},
1334 "name": "CP_CPC_BUSY_STAT",
1335 "type_ref": "CP_CPC_BUSY_STAT"
1339 "map": {"at": 33304, "to": "mm"},
1340 "name": "CP_CPC_STALLED_STAT1",
1341 "type_ref": "CP_CPC_STALLED_STAT1"
1345 "map": {"at": 33308, "to": "mm"},
1346 "name": "CP_CPF_STATUS",
1347 "type_ref": "CP_CPF_STATUS"
1351 "map": {"at": 33312, "to": "mm"},
1352 "name": "CP_CPF_BUSY_STAT",
1353 "type_ref": "CP_CPF_BUSY_STAT"
1357 "map": {"at": 33316, "to": "mm"},
1358 "name": "CP_CPF_STALLED_STAT1",
1359 "type_ref": "CP_CPF_STALLED_STAT1"
1363 "map": {"at": 33320, "to": "mm"},
1364 "name": "CP_CPC_BUSY_STAT2",
1365 "type_ref": "CP_CPC_BUSY_STAT2"
1369 "map": {"at": 33324, "to": "mm"},
1370 "name": "CP_CPC_GRBM_FREE_COUNT",
1371 "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1375 "map": {"at": 33344, "to": "mm"},
1376 "name": "CP_CPC_SCRATCH_INDEX",
1377 "type_ref": "CP_CPC_SCRATCH_INDEX"
1381 "map": {"at": 33348, "to": "mm"},
1382 "name": "CP_CPC_SCRATCH_DATA",
1383 "type_ref": "CP_CPC_SCRATCH_DATA"
1387 "map": {"at": 33352, "to": "mm"},
1388 "name": "CP_CPF_GRBM_FREE_COUNT",
1389 "type_ref": "CP_CPF_GRBM_FREE_COUNT"
1393 "map": {"at": 33356, "to": "mm"},
1394 "name": "CP_CPF_BUSY_STAT2",
1395 "type_ref": "CP_CPF_BUSY_STAT2"
1399 "map": {"at": 33436, "to": "mm"},
1400 "name": "CP_CPC_HALT_HYST_COUNT",
1401 "type_ref": "CP_CPC_HALT_HYST_COUNT"
1405 "map": {"at": 36096, "to": "mm"},
1406 "name": "SQ_THREAD_TRACE_BUF0_BASE",
1407 "type_ref": "SQ_THREAD_TRACE_BUF0_BASE"
1411 "map": {"at": 36100, "to": "mm"},
1412 "name": "SQ_THREAD_TRACE_BUF0_SIZE",
1413 "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1417 "map": {"at": 36104, "to": "mm"},
1418 "name": "SQ_THREAD_TRACE_BUF1_BASE",
1419 "type_ref": "SQ_THREAD_TRACE_BUF0_BASE"
1423 "map": {"at": 36108, "to": "mm"},
1424 "name": "SQ_THREAD_TRACE_BUF1_SIZE",
1425 "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1429 "map": {"at": 36112, "to": "mm"},
1430 "name": "SQ_THREAD_TRACE_WPTR",
1431 "type_ref": "SQ_THREAD_TRACE_WPTR"
1435 "map": {"at": 36116, "to": "mm"},
1436 "name": "SQ_THREAD_TRACE_MASK",
1437 "type_ref": "SQ_THREAD_TRACE_MASK"
1441 "map": {"at": 36120, "to": "mm"},
1442 "name": "SQ_THREAD_TRACE_TOKEN_MASK",
1443 "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
1447 "map": {"at": 36124, "to": "mm"},
1448 "name": "SQ_THREAD_TRACE_CTRL",
1449 "type_ref": "SQ_THREAD_TRACE_CTRL"
1453 "map": {"at": 36128, "to": "mm"},
1454 "name": "SQ_THREAD_TRACE_STATUS",
1455 "type_ref": "SQ_THREAD_TRACE_STATUS"
1459 "map": {"at": 36132, "to": "mm"},
1460 "name": "SQ_THREAD_TRACE_DROPPED_CNTR",
1461 "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1465 "map": {"at": 36140, "to": "mm"},
1466 "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR",
1467 "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1471 "map": {"at": 36144, "to": "mm"},
1472 "name": "SQ_THREAD_TRACE_GFX_MARKER_CNTR",
1473 "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1477 "map": {"at": 36148, "to": "mm"},
1478 "name": "SQ_THREAD_TRACE_HP3D_DRAW_CNTR",
1479 "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1483 "map": {"at": 36152, "to": "mm"},
1484 "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR",
1485 "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1489 "map": {"at": 37120, "to": "mm"},
1490 "name": "SPI_CONFIG_CNTL",
1491 "type_ref": "SPI_CONFIG_CNTL"
1495 "map": {"at": 39160, "to": "mm"},
1496 "name": "GB_ADDR_CONFIG",
1497 "type_ref": "GB_ADDR_CONFIG"
1501 "map": {"at": 39184, "to": "mm"},
1502 "name": "GB_TILE_MODE0",
1503 "type_ref": "GB_TILE_MODE0"
1507 "map": {"at": 39188, "to": "mm"},
1508 "name": "GB_TILE_MODE1",
1509 "type_ref": "GB_TILE_MODE0"
1513 "map": {"at": 39192, "to": "mm"},
1514 "name": "GB_TILE_MODE2",
1515 "type_ref": "GB_TILE_MODE0"
1519 "map": {"at": 39196, "to": "mm"},
1520 "name": "GB_TILE_MODE3",
1521 "type_ref": "GB_TILE_MODE0"
1525 "map": {"at": 39200, "to": "mm"},
1526 "name": "GB_TILE_MODE4",
1527 "type_ref": "GB_TILE_MODE0"
1531 "map": {"at": 39204, "to": "mm"},
1532 "name": "GB_TILE_MODE5",
1533 "type_ref": "GB_TILE_MODE0"
1537 "map": {"at": 39208, "to": "mm"},
1538 "name": "GB_TILE_MODE6",
1539 "type_ref": "GB_TILE_MODE0"
1543 "map": {"at": 39212, "to": "mm"},
1544 "name": "GB_TILE_MODE7",
1545 "type_ref": "GB_TILE_MODE0"
1549 "map": {"at": 39216, "to": "mm"},
1550 "name": "GB_TILE_MODE8",
1551 "type_ref": "GB_TILE_MODE0"
1555 "map": {"at": 39220, "to": "mm"},
1556 "name": "GB_TILE_MODE9",
1557 "type_ref": "GB_TILE_MODE0"
1561 "map": {"at": 39224, "to": "mm"},
1562 "name": "GB_TILE_MODE10",
1563 "type_ref": "GB_TILE_MODE0"
1567 "map": {"at": 39228, "to": "mm"},
1568 "name": "GB_TILE_MODE11",
1569 "type_ref": "GB_TILE_MODE0"
1573 "map": {"at": 39232, "to": "mm"},
1574 "name": "GB_TILE_MODE12",
1575 "type_ref": "GB_TILE_MODE0"
1579 "map": {"at": 39236, "to": "mm"},
1580 "name": "GB_TILE_MODE13",
1581 "type_ref": "GB_TILE_MODE0"
1585 "map": {"at": 39240, "to": "mm"},
1586 "name": "GB_TILE_MODE14",
1587 "type_ref": "GB_TILE_MODE0"
1591 "map": {"at": 39244, "to": "mm"},
1592 "name": "GB_TILE_MODE15",
1593 "type_ref": "GB_TILE_MODE0"
1597 "map": {"at": 39248, "to": "mm"},
1598 "name": "GB_TILE_MODE16",
1599 "type_ref": "GB_TILE_MODE0"
1603 "map": {"at": 39252, "to": "mm"},
1604 "name": "GB_TILE_MODE17",
1605 "type_ref": "GB_TILE_MODE0"
1609 "map": {"at": 39256, "to": "mm"},
1610 "name": "GB_TILE_MODE18",
1611 "type_ref": "GB_TILE_MODE0"
1615 "map": {"at": 39260, "to": "mm"},
1616 "name": "GB_TILE_MODE19",
1617 "type_ref": "GB_TILE_MODE0"
1621 "map": {"at": 39264, "to": "mm"},
1622 "name": "GB_TILE_MODE20",
1623 "type_ref": "GB_TILE_MODE0"
1627 "map": {"at": 39268, "to": "mm"},
1628 "name": "GB_TILE_MODE21",
1629 "type_ref": "GB_TILE_MODE0"
1633 "map": {"at": 39272, "to": "mm"},
1634 "name": "GB_TILE_MODE22",
1635 "type_ref": "GB_TILE_MODE0"
1639 "map": {"at": 39276, "to": "mm"},
1640 "name": "GB_TILE_MODE23",
1641 "type_ref": "GB_TILE_MODE0"
1645 "map": {"at": 39280, "to": "mm"},
1646 "name": "GB_TILE_MODE24",
1647 "type_ref": "GB_TILE_MODE0"
1651 "map": {"at": 39284, "to": "mm"},
1652 "name": "GB_TILE_MODE25",
1653 "type_ref": "GB_TILE_MODE0"
1657 "map": {"at": 39288, "to": "mm"},
1658 "name": "GB_TILE_MODE26",
1659 "type_ref": "GB_TILE_MODE0"
1663 "map": {"at": 39292, "to": "mm"},
1664 "name": "GB_TILE_MODE27",
1665 "type_ref": "GB_TILE_MODE0"
1669 "map": {"at": 39296, "to": "mm"},
1670 "name": "GB_TILE_MODE28",
1671 "type_ref": "GB_TILE_MODE0"
1675 "map": {"at": 39300, "to": "mm"},
1676 "name": "GB_TILE_MODE29",
1677 "type_ref": "GB_TILE_MODE0"
1681 "map": {"at": 39304, "to": "mm"},
1682 "name": "GB_TILE_MODE30",
1683 "type_ref": "GB_TILE_MODE0"
1687 "map": {"at": 39308, "to": "mm"},
1688 "name": "GB_TILE_MODE31",
1689 "type_ref": "GB_TILE_MODE0"
1693 "map": {"at": 39312, "to": "mm"},
1694 "name": "GB_MACROTILE_MODE0",
1695 "type_ref": "GB_MACROTILE_MODE0"
1699 "map": {"at": 39316, "to": "mm"},
1700 "name": "GB_MACROTILE_MODE1",
1701 "type_ref": "GB_MACROTILE_MODE0"
1705 "map": {"at": 39320, "to": "mm"},
1706 "name": "GB_MACROTILE_MODE2",
1707 "type_ref": "GB_MACROTILE_MODE0"
1711 "map": {"at": 39324, "to": "mm"},
1712 "name": "GB_MACROTILE_MODE3",
1713 "type_ref": "GB_MACROTILE_MODE0"
1717 "map": {"at": 39328, "to": "mm"},
1718 "name": "GB_MACROTILE_MODE4",
1719 "type_ref": "GB_MACROTILE_MODE0"
1723 "map": {"at": 39332, "to": "mm"},
1724 "name": "GB_MACROTILE_MODE5",
1725 "type_ref": "GB_MACROTILE_MODE0"
1729 "map": {"at": 39336, "to": "mm"},
1730 "name": "GB_MACROTILE_MODE6",
1731 "type_ref": "GB_MACROTILE_MODE0"
1735 "map": {"at": 39340, "to": "mm"},
1736 "name": "GB_MACROTILE_MODE7",
1737 "type_ref": "GB_MACROTILE_MODE0"
1741 "map": {"at": 39344, "to": "mm"},
1742 "name": "GB_MACROTILE_MODE8",
1743 "type_ref": "GB_MACROTILE_MODE0"
1747 "map": {"at": 39348, "to": "mm"},
1748 "name": "GB_MACROTILE_MODE9",
1749 "type_ref": "GB_MACROTILE_MODE0"
1753 "map": {"at": 39352, "to": "mm"},
1754 "name": "GB_MACROTILE_MODE10",
1755 "type_ref": "GB_MACROTILE_MODE0"
1759 "map": {"at": 39356, "to": "mm"},
1760 "name": "GB_MACROTILE_MODE11",
1761 "type_ref": "GB_MACROTILE_MODE0"
1765 "map": {"at": 39360, "to": "mm"},
1766 "name": "GB_MACROTILE_MODE12",
1767 "type_ref": "GB_MACROTILE_MODE0"
1771 "map": {"at": 39364, "to": "mm"},
1772 "name": "GB_MACROTILE_MODE13",
1773 "type_ref": "GB_MACROTILE_MODE0"
1777 "map": {"at": 39368, "to": "mm"},
1778 "name": "GB_MACROTILE_MODE14",
1779 "type_ref": "GB_MACROTILE_MODE0"
1783 "map": {"at": 39372, "to": "mm"},
1784 "name": "GB_MACROTILE_MODE15",
1785 "type_ref": "GB_MACROTILE_MODE0"
1789 "map": {"at": 45060, "to": "mm"},
1790 "name": "SPI_SHADER_PGM_RSRC4_PS",
1791 "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1795 "map": {"at": 45080, "to": "mm"},
1796 "name": "SPI_SHADER_PGM_CHKSUM_PS",
1797 "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
1801 "map": {"at": 45084, "to": "mm"},
1802 "name": "SPI_SHADER_PGM_RSRC3_PS",
1803 "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1807 "map": {"at": 45088, "to": "mm"},
1808 "name": "SPI_SHADER_PGM_LO_PS",
1809 "type_ref": "SPI_SHADER_PGM_LO_PS"
1813 "map": {"at": 45092, "to": "mm"},
1814 "name": "SPI_SHADER_PGM_HI_PS",
1815 "type_ref": "SPI_SHADER_PGM_HI_PS"
1819 "map": {"at": 45096, "to": "mm"},
1820 "name": "SPI_SHADER_PGM_RSRC1_PS",
1821 "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1825 "map": {"at": 45100, "to": "mm"},
1826 "name": "SPI_SHADER_PGM_RSRC2_PS",
1827 "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1831 "map": {"at": 45104, "to": "mm"},
1832 "name": "SPI_SHADER_USER_DATA_PS_0",
1833 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1837 "map": {"at": 45108, "to": "mm"},
1838 "name": "SPI_SHADER_USER_DATA_PS_1",
1839 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1843 "map": {"at": 45112, "to": "mm"},
1844 "name": "SPI_SHADER_USER_DATA_PS_2",
1845 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1849 "map": {"at": 45116, "to": "mm"},
1850 "name": "SPI_SHADER_USER_DATA_PS_3",
1851 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1855 "map": {"at": 45120, "to": "mm"},
1856 "name": "SPI_SHADER_USER_DATA_PS_4",
1857 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1861 "map": {"at": 45124, "to": "mm"},
1862 "name": "SPI_SHADER_USER_DATA_PS_5",
1863 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1867 "map": {"at": 45128, "to": "mm"},
1868 "name": "SPI_SHADER_USER_DATA_PS_6",
1869 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1873 "map": {"at": 45132, "to": "mm"},
1874 "name": "SPI_SHADER_USER_DATA_PS_7",
1875 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1879 "map": {"at": 45136, "to": "mm"},
1880 "name": "SPI_SHADER_USER_DATA_PS_8",
1881 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1885 "map": {"at": 45140, "to": "mm"},
1886 "name": "SPI_SHADER_USER_DATA_PS_9",
1887 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1891 "map": {"at": 45144, "to": "mm"},
1892 "name": "SPI_SHADER_USER_DATA_PS_10",
1893 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1897 "map": {"at": 45148, "to": "mm"},
1898 "name": "SPI_SHADER_USER_DATA_PS_11",
1899 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1903 "map": {"at": 45152, "to": "mm"},
1904 "name": "SPI_SHADER_USER_DATA_PS_12",
1905 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1909 "map": {"at": 45156, "to": "mm"},
1910 "name": "SPI_SHADER_USER_DATA_PS_13",
1911 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1915 "map": {"at": 45160, "to": "mm"},
1916 "name": "SPI_SHADER_USER_DATA_PS_14",
1917 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1921 "map": {"at": 45164, "to": "mm"},
1922 "name": "SPI_SHADER_USER_DATA_PS_15",
1923 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1927 "map": {"at": 45168, "to": "mm"},
1928 "name": "SPI_SHADER_USER_DATA_PS_16",
1929 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1933 "map": {"at": 45172, "to": "mm"},
1934 "name": "SPI_SHADER_USER_DATA_PS_17",
1935 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1939 "map": {"at": 45176, "to": "mm"},
1940 "name": "SPI_SHADER_USER_DATA_PS_18",
1941 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1945 "map": {"at": 45180, "to": "mm"},
1946 "name": "SPI_SHADER_USER_DATA_PS_19",
1947 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1951 "map": {"at": 45184, "to": "mm"},
1952 "name": "SPI_SHADER_USER_DATA_PS_20",
1953 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1957 "map": {"at": 45188, "to": "mm"},
1958 "name": "SPI_SHADER_USER_DATA_PS_21",
1959 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1963 "map": {"at": 45192, "to": "mm"},
1964 "name": "SPI_SHADER_USER_DATA_PS_22",
1965 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1969 "map": {"at": 45196, "to": "mm"},
1970 "name": "SPI_SHADER_USER_DATA_PS_23",
1971 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1975 "map": {"at": 45200, "to": "mm"},
1976 "name": "SPI_SHADER_USER_DATA_PS_24",
1977 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1981 "map": {"at": 45204, "to": "mm"},
1982 "name": "SPI_SHADER_USER_DATA_PS_25",
1983 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1987 "map": {"at": 45208, "to": "mm"},
1988 "name": "SPI_SHADER_USER_DATA_PS_26",
1989 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1993 "map": {"at": 45212, "to": "mm"},
1994 "name": "SPI_SHADER_USER_DATA_PS_27",
1995 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1999 "map": {"at": 45216, "to": "mm"},
2000 "name": "SPI_SHADER_USER_DATA_PS_28",
2001 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2005 "map": {"at": 45220, "to": "mm"},
2006 "name": "SPI_SHADER_USER_DATA_PS_29",
2007 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2011 "map": {"at": 45224, "to": "mm"},
2012 "name": "SPI_SHADER_USER_DATA_PS_30",
2013 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2017 "map": {"at": 45228, "to": "mm"},
2018 "name": "SPI_SHADER_USER_DATA_PS_31",
2019 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2023 "map": {"at": 45248, "to": "mm"},
2024 "name": "SPI_SHADER_REQ_CTRL_PS",
2025 "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2029 "map": {"at": 45252, "to": "mm"},
2030 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS",
2031 "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2035 "map": {"at": 45256, "to": "mm"},
2036 "name": "SPI_SHADER_USER_ACCUM_PS_0",
2037 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2041 "map": {"at": 45260, "to": "mm"},
2042 "name": "SPI_SHADER_USER_ACCUM_PS_1",
2043 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2047 "map": {"at": 45264, "to": "mm"},
2048 "name": "SPI_SHADER_USER_ACCUM_PS_2",
2049 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2053 "map": {"at": 45268, "to": "mm"},
2054 "name": "SPI_SHADER_USER_ACCUM_PS_3",
2055 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2059 "map": {"at": 45316, "to": "mm"},
2060 "name": "SPI_SHADER_PGM_RSRC4_VS",
2061 "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2065 "map": {"at": 45332, "to": "mm"},
2066 "name": "SPI_SHADER_PGM_CHKSUM_VS",
2067 "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
2071 "map": {"at": 45336, "to": "mm"},
2072 "name": "SPI_SHADER_PGM_RSRC3_VS",
2073 "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
2077 "map": {"at": 45340, "to": "mm"},
2078 "name": "SPI_SHADER_LATE_ALLOC_VS",
2079 "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
2083 "map": {"at": 45344, "to": "mm"},
2084 "name": "SPI_SHADER_PGM_LO_VS",
2085 "type_ref": "SPI_SHADER_PGM_LO_PS"
2089 "map": {"at": 45348, "to": "mm"},
2090 "name": "SPI_SHADER_PGM_HI_VS",
2091 "type_ref": "SPI_SHADER_PGM_HI_PS"
2095 "map": {"at": 45352, "to": "mm"},
2096 "name": "SPI_SHADER_PGM_RSRC1_VS",
2097 "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
2101 "map": {"at": 45356, "to": "mm"},
2102 "name": "SPI_SHADER_PGM_RSRC2_VS",
2103 "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
2107 "map": {"at": 45360, "to": "mm"},
2108 "name": "SPI_SHADER_USER_DATA_VS_0",
2109 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2113 "map": {"at": 45364, "to": "mm"},
2114 "name": "SPI_SHADER_USER_DATA_VS_1",
2115 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2119 "map": {"at": 45368, "to": "mm"},
2120 "name": "SPI_SHADER_USER_DATA_VS_2",
2121 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2125 "map": {"at": 45372, "to": "mm"},
2126 "name": "SPI_SHADER_USER_DATA_VS_3",
2127 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2131 "map": {"at": 45376, "to": "mm"},
2132 "name": "SPI_SHADER_USER_DATA_VS_4",
2133 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2137 "map": {"at": 45380, "to": "mm"},
2138 "name": "SPI_SHADER_USER_DATA_VS_5",
2139 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2143 "map": {"at": 45384, "to": "mm"},
2144 "name": "SPI_SHADER_USER_DATA_VS_6",
2145 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2149 "map": {"at": 45388, "to": "mm"},
2150 "name": "SPI_SHADER_USER_DATA_VS_7",
2151 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2155 "map": {"at": 45392, "to": "mm"},
2156 "name": "SPI_SHADER_USER_DATA_VS_8",
2157 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2161 "map": {"at": 45396, "to": "mm"},
2162 "name": "SPI_SHADER_USER_DATA_VS_9",
2163 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2167 "map": {"at": 45400, "to": "mm"},
2168 "name": "SPI_SHADER_USER_DATA_VS_10",
2169 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2173 "map": {"at": 45404, "to": "mm"},
2174 "name": "SPI_SHADER_USER_DATA_VS_11",
2175 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2179 "map": {"at": 45408, "to": "mm"},
2180 "name": "SPI_SHADER_USER_DATA_VS_12",
2181 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2185 "map": {"at": 45412, "to": "mm"},
2186 "name": "SPI_SHADER_USER_DATA_VS_13",
2187 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2191 "map": {"at": 45416, "to": "mm"},
2192 "name": "SPI_SHADER_USER_DATA_VS_14",
2193 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2197 "map": {"at": 45420, "to": "mm"},
2198 "name": "SPI_SHADER_USER_DATA_VS_15",
2199 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2203 "map": {"at": 45424, "to": "mm"},
2204 "name": "SPI_SHADER_USER_DATA_VS_16",
2205 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2209 "map": {"at": 45428, "to": "mm"},
2210 "name": "SPI_SHADER_USER_DATA_VS_17",
2211 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2215 "map": {"at": 45432, "to": "mm"},
2216 "name": "SPI_SHADER_USER_DATA_VS_18",
2217 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2221 "map": {"at": 45436, "to": "mm"},
2222 "name": "SPI_SHADER_USER_DATA_VS_19",
2223 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2227 "map": {"at": 45440, "to": "mm"},
2228 "name": "SPI_SHADER_USER_DATA_VS_20",
2229 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2233 "map": {"at": 45444, "to": "mm"},
2234 "name": "SPI_SHADER_USER_DATA_VS_21",
2235 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2239 "map": {"at": 45448, "to": "mm"},
2240 "name": "SPI_SHADER_USER_DATA_VS_22",
2241 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2245 "map": {"at": 45452, "to": "mm"},
2246 "name": "SPI_SHADER_USER_DATA_VS_23",
2247 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2251 "map": {"at": 45456, "to": "mm"},
2252 "name": "SPI_SHADER_USER_DATA_VS_24",
2253 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2257 "map": {"at": 45460, "to": "mm"},
2258 "name": "SPI_SHADER_USER_DATA_VS_25",
2259 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2263 "map": {"at": 45464, "to": "mm"},
2264 "name": "SPI_SHADER_USER_DATA_VS_26",
2265 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2269 "map": {"at": 45468, "to": "mm"},
2270 "name": "SPI_SHADER_USER_DATA_VS_27",
2271 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2275 "map": {"at": 45472, "to": "mm"},
2276 "name": "SPI_SHADER_USER_DATA_VS_28",
2277 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2281 "map": {"at": 45476, "to": "mm"},
2282 "name": "SPI_SHADER_USER_DATA_VS_29",
2283 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2287 "map": {"at": 45480, "to": "mm"},
2288 "name": "SPI_SHADER_USER_DATA_VS_30",
2289 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2293 "map": {"at": 45484, "to": "mm"},
2294 "name": "SPI_SHADER_USER_DATA_VS_31",
2295 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2299 "map": {"at": 45504, "to": "mm"},
2300 "name": "SPI_SHADER_REQ_CTRL_VS",
2301 "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2305 "map": {"at": 45508, "to": "mm"},
2306 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_VS",
2307 "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2311 "map": {"at": 45512, "to": "mm"},
2312 "name": "SPI_SHADER_USER_ACCUM_VS_0",
2313 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2317 "map": {"at": 45516, "to": "mm"},
2318 "name": "SPI_SHADER_USER_ACCUM_VS_1",
2319 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2323 "map": {"at": 45520, "to": "mm"},
2324 "name": "SPI_SHADER_USER_ACCUM_VS_2",
2325 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2329 "map": {"at": 45524, "to": "mm"},
2330 "name": "SPI_SHADER_USER_ACCUM_VS_3",
2331 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2335 "map": {"at": 45548, "to": "mm"},
2336 "name": "SPI_SHADER_PGM_RSRC2_GS_VS",
2337 "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS"
2341 "map": {"at": 45552, "to": "mm"},
2342 "name": "SPI_SHADER_PGM_RSRC2_ES_VS",
2343 "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2347 "map": {"at": 45556, "to": "mm"},
2348 "name": "SPI_SHADER_PGM_RSRC2_LS_VS",
2349 "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2353 "map": {"at": 45568, "to": "mm"},
2354 "name": "SPI_SHADER_PGM_CHKSUM_GS",
2355 "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
2359 "map": {"at": 45572, "to": "mm"},
2360 "name": "SPI_SHADER_PGM_RSRC4_GS",
2361 "type_ref": "SPI_SHADER_PGM_RSRC4_GS"
2365 "map": {"at": 45576, "to": "mm"},
2366 "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS",
2367 "type_ref": "SPI_SHADER_PGM_LO_PS"
2371 "map": {"at": 45580, "to": "mm"},
2372 "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS",
2373 "type_ref": "SPI_SHADER_PGM_LO_PS"
2377 "map": {"at": 45584, "to": "mm"},
2378 "name": "SPI_SHADER_PGM_LO_ES_GS",
2379 "type_ref": "SPI_SHADER_PGM_LO_PS"
2383 "map": {"at": 45588, "to": "mm"},
2384 "name": "SPI_SHADER_PGM_HI_ES_GS",
2385 "type_ref": "SPI_SHADER_PGM_HI_PS"
2389 "map": {"at": 45596, "to": "mm"},
2390 "name": "SPI_SHADER_PGM_RSRC3_GS",
2391 "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2395 "map": {"at": 45600, "to": "mm"},
2396 "name": "SPI_SHADER_PGM_LO_GS",
2397 "type_ref": "SPI_SHADER_PGM_LO_PS"
2401 "map": {"at": 45604, "to": "mm"},
2402 "name": "SPI_SHADER_PGM_HI_GS",
2403 "type_ref": "SPI_SHADER_PGM_HI_PS"
2407 "map": {"at": 45608, "to": "mm"},
2408 "name": "SPI_SHADER_PGM_RSRC1_GS",
2409 "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
2413 "map": {"at": 45612, "to": "mm"},
2414 "name": "SPI_SHADER_PGM_RSRC2_GS",
2415 "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
2419 "map": {"at": 45616, "to": "mm"},
2420 "name": "SPI_SHADER_USER_DATA_GS_0",
2421 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2425 "map": {"at": 45620, "to": "mm"},
2426 "name": "SPI_SHADER_USER_DATA_GS_1",
2427 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2431 "map": {"at": 45624, "to": "mm"},
2432 "name": "SPI_SHADER_USER_DATA_GS_2",
2433 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2437 "map": {"at": 45628, "to": "mm"},
2438 "name": "SPI_SHADER_USER_DATA_GS_3",
2439 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2443 "map": {"at": 45632, "to": "mm"},
2444 "name": "SPI_SHADER_USER_DATA_GS_4",
2445 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2449 "map": {"at": 45636, "to": "mm"},
2450 "name": "SPI_SHADER_USER_DATA_GS_5",
2451 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2455 "map": {"at": 45640, "to": "mm"},
2456 "name": "SPI_SHADER_USER_DATA_GS_6",
2457 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2461 "map": {"at": 45644, "to": "mm"},
2462 "name": "SPI_SHADER_USER_DATA_GS_7",
2463 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2467 "map": {"at": 45648, "to": "mm"},
2468 "name": "SPI_SHADER_USER_DATA_GS_8",
2469 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2473 "map": {"at": 45652, "to": "mm"},
2474 "name": "SPI_SHADER_USER_DATA_GS_9",
2475 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2479 "map": {"at": 45656, "to": "mm"},
2480 "name": "SPI_SHADER_USER_DATA_GS_10",
2481 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2485 "map": {"at": 45660, "to": "mm"},
2486 "name": "SPI_SHADER_USER_DATA_GS_11",
2487 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2491 "map": {"at": 45664, "to": "mm"},
2492 "name": "SPI_SHADER_USER_DATA_GS_12",
2493 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2497 "map": {"at": 45668, "to": "mm"},
2498 "name": "SPI_SHADER_USER_DATA_GS_13",
2499 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2503 "map": {"at": 45672, "to": "mm"},
2504 "name": "SPI_SHADER_USER_DATA_GS_14",
2505 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2509 "map": {"at": 45676, "to": "mm"},
2510 "name": "SPI_SHADER_USER_DATA_GS_15",
2511 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2515 "map": {"at": 45680, "to": "mm"},
2516 "name": "SPI_SHADER_USER_DATA_GS_16",
2517 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2521 "map": {"at": 45684, "to": "mm"},
2522 "name": "SPI_SHADER_USER_DATA_GS_17",
2523 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2527 "map": {"at": 45688, "to": "mm"},
2528 "name": "SPI_SHADER_USER_DATA_GS_18",
2529 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2533 "map": {"at": 45692, "to": "mm"},
2534 "name": "SPI_SHADER_USER_DATA_GS_19",
2535 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2539 "map": {"at": 45696, "to": "mm"},
2540 "name": "SPI_SHADER_USER_DATA_GS_20",
2541 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2545 "map": {"at": 45700, "to": "mm"},
2546 "name": "SPI_SHADER_USER_DATA_GS_21",
2547 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2551 "map": {"at": 45704, "to": "mm"},
2552 "name": "SPI_SHADER_USER_DATA_GS_22",
2553 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2557 "map": {"at": 45708, "to": "mm"},
2558 "name": "SPI_SHADER_USER_DATA_GS_23",
2559 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2563 "map": {"at": 45712, "to": "mm"},
2564 "name": "SPI_SHADER_USER_DATA_GS_24",
2565 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2569 "map": {"at": 45716, "to": "mm"},
2570 "name": "SPI_SHADER_USER_DATA_GS_25",
2571 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2575 "map": {"at": 45720, "to": "mm"},
2576 "name": "SPI_SHADER_USER_DATA_GS_26",
2577 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2581 "map": {"at": 45724, "to": "mm"},
2582 "name": "SPI_SHADER_USER_DATA_GS_27",
2583 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2587 "map": {"at": 45728, "to": "mm"},
2588 "name": "SPI_SHADER_USER_DATA_GS_28",
2589 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2593 "map": {"at": 45732, "to": "mm"},
2594 "name": "SPI_SHADER_USER_DATA_GS_29",
2595 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2599 "map": {"at": 45736, "to": "mm"},
2600 "name": "SPI_SHADER_USER_DATA_GS_30",
2601 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2605 "map": {"at": 45740, "to": "mm"},
2606 "name": "SPI_SHADER_USER_DATA_GS_31",
2607 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2611 "map": {"at": 45760, "to": "mm"},
2612 "name": "SPI_SHADER_REQ_CTRL_ESGS",
2613 "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2617 "map": {"at": 45764, "to": "mm"},
2618 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS",
2619 "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2623 "map": {"at": 45768, "to": "mm"},
2624 "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
2625 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2629 "map": {"at": 45772, "to": "mm"},
2630 "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
2631 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2635 "map": {"at": 45776, "to": "mm"},
2636 "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
2637 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2641 "map": {"at": 45780, "to": "mm"},
2642 "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
2643 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2647 "map": {"at": 45808, "to": "mm"},
2648 "name": "SPI_SHADER_PGM_RSRC2_ES_GS",
2649 "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2653 "map": {"at": 45852, "to": "mm"},
2654 "name": "SPI_SHADER_PGM_RSRC3_ES",
2655 "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2659 "map": {"at": 45856, "to": "mm"},
2660 "name": "SPI_SHADER_PGM_LO_ES",
2661 "type_ref": "SPI_SHADER_PGM_LO_PS"
2665 "map": {"at": 45860, "to": "mm"},
2666 "name": "SPI_SHADER_PGM_HI_ES",
2667 "type_ref": "SPI_SHADER_PGM_HI_PS"
2671 "map": {"at": 45864, "to": "mm"},
2672 "name": "SPI_SHADER_PGM_RSRC1_ES",
2673 "type_ref": "SPI_SHADER_PGM_RSRC1_ES"
2677 "map": {"at": 45868, "to": "mm"},
2678 "name": "SPI_SHADER_PGM_RSRC2_ES",
2679 "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2683 "map": {"at": 45872, "to": "mm"},
2684 "name": "SPI_SHADER_USER_DATA_ES_0",
2685 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2689 "map": {"at": 45876, "to": "mm"},
2690 "name": "SPI_SHADER_USER_DATA_ES_1",
2691 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2695 "map": {"at": 45880, "to": "mm"},
2696 "name": "SPI_SHADER_USER_DATA_ES_2",
2697 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2701 "map": {"at": 45884, "to": "mm"},
2702 "name": "SPI_SHADER_USER_DATA_ES_3",
2703 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2707 "map": {"at": 45888, "to": "mm"},
2708 "name": "SPI_SHADER_USER_DATA_ES_4",
2709 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2713 "map": {"at": 45892, "to": "mm"},
2714 "name": "SPI_SHADER_USER_DATA_ES_5",
2715 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2719 "map": {"at": 45896, "to": "mm"},
2720 "name": "SPI_SHADER_USER_DATA_ES_6",
2721 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2725 "map": {"at": 45900, "to": "mm"},
2726 "name": "SPI_SHADER_USER_DATA_ES_7",
2727 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2731 "map": {"at": 45904, "to": "mm"},
2732 "name": "SPI_SHADER_USER_DATA_ES_8",
2733 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2737 "map": {"at": 45908, "to": "mm"},
2738 "name": "SPI_SHADER_USER_DATA_ES_9",
2739 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2743 "map": {"at": 45912, "to": "mm"},
2744 "name": "SPI_SHADER_USER_DATA_ES_10",
2745 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2749 "map": {"at": 45916, "to": "mm"},
2750 "name": "SPI_SHADER_USER_DATA_ES_11",
2751 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2755 "map": {"at": 45920, "to": "mm"},
2756 "name": "SPI_SHADER_USER_DATA_ES_12",
2757 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2761 "map": {"at": 45924, "to": "mm"},
2762 "name": "SPI_SHADER_USER_DATA_ES_13",
2763 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2767 "map": {"at": 45928, "to": "mm"},
2768 "name": "SPI_SHADER_USER_DATA_ES_14",
2769 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2773 "map": {"at": 45932, "to": "mm"},
2774 "name": "SPI_SHADER_USER_DATA_ES_15",
2775 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2779 "map": {"at": 46068, "to": "mm"},
2780 "name": "SPI_SHADER_PGM_RSRC2_LS_ES",
2781 "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2785 "map": {"at": 46080, "to": "mm"},
2786 "name": "SPI_SHADER_PGM_CHKSUM_HS",
2787 "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
2791 "map": {"at": 46084, "to": "mm"},
2792 "name": "SPI_SHADER_PGM_RSRC4_HS",
2793 "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2797 "map": {"at": 46088, "to": "mm"},
2798 "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS",
2799 "type_ref": "SPI_SHADER_PGM_LO_PS"
2803 "map": {"at": 46092, "to": "mm"},
2804 "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS",
2805 "type_ref": "SPI_SHADER_PGM_LO_PS"
2809 "map": {"at": 46096, "to": "mm"},
2810 "name": "SPI_SHADER_PGM_LO_LS_HS",
2811 "type_ref": "SPI_SHADER_PGM_LO_PS"
2815 "map": {"at": 46100, "to": "mm"},
2816 "name": "SPI_SHADER_PGM_HI_LS_HS",
2817 "type_ref": "SPI_SHADER_PGM_HI_PS"
2821 "map": {"at": 46108, "to": "mm"},
2822 "name": "SPI_SHADER_PGM_RSRC3_HS",
2823 "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2827 "map": {"at": 46112, "to": "mm"},
2828 "name": "SPI_SHADER_PGM_LO_HS",
2829 "type_ref": "SPI_SHADER_PGM_LO_PS"
2833 "map": {"at": 46116, "to": "mm"},
2834 "name": "SPI_SHADER_PGM_HI_HS",
2835 "type_ref": "SPI_SHADER_PGM_HI_PS"
2839 "map": {"at": 46120, "to": "mm"},
2840 "name": "SPI_SHADER_PGM_RSRC1_HS",
2841 "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2845 "map": {"at": 46124, "to": "mm"},
2846 "name": "SPI_SHADER_PGM_RSRC2_HS",
2847 "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2851 "map": {"at": 46128, "to": "mm"},
2852 "name": "SPI_SHADER_USER_DATA_HS_0",
2853 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2857 "map": {"at": 46132, "to": "mm"},
2858 "name": "SPI_SHADER_USER_DATA_HS_1",
2859 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2863 "map": {"at": 46136, "to": "mm"},
2864 "name": "SPI_SHADER_USER_DATA_HS_2",
2865 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2869 "map": {"at": 46140, "to": "mm"},
2870 "name": "SPI_SHADER_USER_DATA_HS_3",
2871 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2875 "map": {"at": 46144, "to": "mm"},
2876 "name": "SPI_SHADER_USER_DATA_HS_4",
2877 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2881 "map": {"at": 46148, "to": "mm"},
2882 "name": "SPI_SHADER_USER_DATA_HS_5",
2883 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2887 "map": {"at": 46152, "to": "mm"},
2888 "name": "SPI_SHADER_USER_DATA_HS_6",
2889 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2893 "map": {"at": 46156, "to": "mm"},
2894 "name": "SPI_SHADER_USER_DATA_HS_7",
2895 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2899 "map": {"at": 46160, "to": "mm"},
2900 "name": "SPI_SHADER_USER_DATA_HS_8",
2901 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2905 "map": {"at": 46164, "to": "mm"},
2906 "name": "SPI_SHADER_USER_DATA_HS_9",
2907 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2911 "map": {"at": 46168, "to": "mm"},
2912 "name": "SPI_SHADER_USER_DATA_HS_10",
2913 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2917 "map": {"at": 46172, "to": "mm"},
2918 "name": "SPI_SHADER_USER_DATA_HS_11",
2919 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2923 "map": {"at": 46176, "to": "mm"},
2924 "name": "SPI_SHADER_USER_DATA_HS_12",
2925 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2929 "map": {"at": 46180, "to": "mm"},
2930 "name": "SPI_SHADER_USER_DATA_HS_13",
2931 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2935 "map": {"at": 46184, "to": "mm"},
2936 "name": "SPI_SHADER_USER_DATA_HS_14",
2937 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2941 "map": {"at": 46188, "to": "mm"},
2942 "name": "SPI_SHADER_USER_DATA_HS_15",
2943 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2947 "map": {"at": 46192, "to": "mm"},
2948 "name": "SPI_SHADER_USER_DATA_HS_16",
2949 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2953 "map": {"at": 46196, "to": "mm"},
2954 "name": "SPI_SHADER_USER_DATA_HS_17",
2955 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2959 "map": {"at": 46200, "to": "mm"},
2960 "name": "SPI_SHADER_USER_DATA_HS_18",
2961 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2965 "map": {"at": 46204, "to": "mm"},
2966 "name": "SPI_SHADER_USER_DATA_HS_19",
2967 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2971 "map": {"at": 46208, "to": "mm"},
2972 "name": "SPI_SHADER_USER_DATA_HS_20",
2973 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2977 "map": {"at": 46212, "to": "mm"},
2978 "name": "SPI_SHADER_USER_DATA_HS_21",
2979 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2983 "map": {"at": 46216, "to": "mm"},
2984 "name": "SPI_SHADER_USER_DATA_HS_22",
2985 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2989 "map": {"at": 46220, "to": "mm"},
2990 "name": "SPI_SHADER_USER_DATA_HS_23",
2991 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2995 "map": {"at": 46224, "to": "mm"},
2996 "name": "SPI_SHADER_USER_DATA_HS_24",
2997 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3001 "map": {"at": 46228, "to": "mm"},
3002 "name": "SPI_SHADER_USER_DATA_HS_25",
3003 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3007 "map": {"at": 46232, "to": "mm"},
3008 "name": "SPI_SHADER_USER_DATA_HS_26",
3009 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3013 "map": {"at": 46236, "to": "mm"},
3014 "name": "SPI_SHADER_USER_DATA_HS_27",
3015 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3019 "map": {"at": 46240, "to": "mm"},
3020 "name": "SPI_SHADER_USER_DATA_HS_28",
3021 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3025 "map": {"at": 46244, "to": "mm"},
3026 "name": "SPI_SHADER_USER_DATA_HS_29",
3027 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3031 "map": {"at": 46248, "to": "mm"},
3032 "name": "SPI_SHADER_USER_DATA_HS_30",
3033 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3037 "map": {"at": 46252, "to": "mm"},
3038 "name": "SPI_SHADER_USER_DATA_HS_31",
3039 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3043 "map": {"at": 46272, "to": "mm"},
3044 "name": "SPI_SHADER_REQ_CTRL_LSHS",
3045 "type_ref": "SPI_SHADER_REQ_CTRL_PS"
3049 "map": {"at": 46276, "to": "mm"},
3050 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS",
3051 "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
3055 "map": {"at": 46280, "to": "mm"},
3056 "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
3057 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3061 "map": {"at": 46284, "to": "mm"},
3062 "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
3063 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3067 "map": {"at": 46288, "to": "mm"},
3068 "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
3069 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3073 "map": {"at": 46292, "to": "mm"},
3074 "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
3075 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3079 "map": {"at": 46324, "to": "mm"},
3080 "name": "SPI_SHADER_PGM_RSRC2_LS_HS",
3081 "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
3085 "map": {"at": 46364, "to": "mm"},
3086 "name": "SPI_SHADER_PGM_RSRC3_LS",
3087 "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
3091 "map": {"at": 46368, "to": "mm"},
3092 "name": "SPI_SHADER_PGM_LO_LS",
3093 "type_ref": "SPI_SHADER_PGM_LO_PS"
3097 "map": {"at": 46372, "to": "mm"},
3098 "name": "SPI_SHADER_PGM_HI_LS",
3099 "type_ref": "SPI_SHADER_PGM_HI_PS"
3103 "map": {"at": 46376, "to": "mm"},
3104 "name": "SPI_SHADER_PGM_RSRC1_LS",
3105 "type_ref": "SPI_SHADER_PGM_RSRC1_LS"
3109 "map": {"at": 46380, "to": "mm"},
3110 "name": "SPI_SHADER_PGM_RSRC2_LS",
3111 "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
3115 "map": {"at": 46384, "to": "mm"},
3116 "name": "SPI_SHADER_USER_DATA_LS_0",
3117 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3121 "map": {"at": 46388, "to": "mm"},
3122 "name": "SPI_SHADER_USER_DATA_LS_1",
3123 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3127 "map": {"at": 46392, "to": "mm"},
3128 "name": "SPI_SHADER_USER_DATA_LS_2",
3129 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3133 "map": {"at": 46396, "to": "mm"},
3134 "name": "SPI_SHADER_USER_DATA_LS_3",
3135 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3139 "map": {"at": 46400, "to": "mm"},
3140 "name": "SPI_SHADER_USER_DATA_LS_4",
3141 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3145 "map": {"at": 46404, "to": "mm"},
3146 "name": "SPI_SHADER_USER_DATA_LS_5",
3147 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3151 "map": {"at": 46408, "to": "mm"},
3152 "name": "SPI_SHADER_USER_DATA_LS_6",
3153 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3157 "map": {"at": 46412, "to": "mm"},
3158 "name": "SPI_SHADER_USER_DATA_LS_7",
3159 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3163 "map": {"at": 46416, "to": "mm"},
3164 "name": "SPI_SHADER_USER_DATA_LS_8",
3165 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3169 "map": {"at": 46420, "to": "mm"},
3170 "name": "SPI_SHADER_USER_DATA_LS_9",
3171 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3175 "map": {"at": 46424, "to": "mm"},
3176 "name": "SPI_SHADER_USER_DATA_LS_10",
3177 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3181 "map": {"at": 46428, "to": "mm"},
3182 "name": "SPI_SHADER_USER_DATA_LS_11",
3183 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3187 "map": {"at": 46432, "to": "mm"},
3188 "name": "SPI_SHADER_USER_DATA_LS_12",
3189 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3193 "map": {"at": 46436, "to": "mm"},
3194 "name": "SPI_SHADER_USER_DATA_LS_13",
3195 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3199 "map": {"at": 46440, "to": "mm"},
3200 "name": "SPI_SHADER_USER_DATA_LS_14",
3201 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3205 "map": {"at": 46444, "to": "mm"},
3206 "name": "SPI_SHADER_USER_DATA_LS_15",
3207 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3211 "map": {"at": 47104, "to": "mm"},
3212 "name": "COMPUTE_DISPATCH_INITIATOR",
3213 "type_ref": "COMPUTE_DISPATCH_INITIATOR"
3217 "map": {"at": 47108, "to": "mm"},
3218 "name": "COMPUTE_DIM_X",
3219 "type_ref": "COMPUTE_DIM_X"
3223 "map": {"at": 47112, "to": "mm"},
3224 "name": "COMPUTE_DIM_Y",
3225 "type_ref": "COMPUTE_DIM_X"
3229 "map": {"at": 47116, "to": "mm"},
3230 "name": "COMPUTE_DIM_Z",
3231 "type_ref": "COMPUTE_DIM_X"
3235 "map": {"at": 47120, "to": "mm"},
3236 "name": "COMPUTE_START_X",
3237 "type_ref": "COMPUTE_START_X"
3241 "map": {"at": 47124, "to": "mm"},
3242 "name": "COMPUTE_START_Y",
3243 "type_ref": "COMPUTE_START_X"
3247 "map": {"at": 47128, "to": "mm"},
3248 "name": "COMPUTE_START_Z",
3249 "type_ref": "COMPUTE_START_X"
3253 "map": {"at": 47132, "to": "mm"},
3254 "name": "COMPUTE_NUM_THREAD_X",
3255 "type_ref": "COMPUTE_NUM_THREAD_X"
3259 "map": {"at": 47136, "to": "mm"},
3260 "name": "COMPUTE_NUM_THREAD_Y",
3261 "type_ref": "COMPUTE_NUM_THREAD_X"
3265 "map": {"at": 47140, "to": "mm"},
3266 "name": "COMPUTE_NUM_THREAD_Z",
3267 "type_ref": "COMPUTE_NUM_THREAD_X"
3271 "map": {"at": 47144, "to": "mm"},
3272 "name": "COMPUTE_PIPELINESTAT_ENABLE",
3273 "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
3277 "map": {"at": 47148, "to": "mm"},
3278 "name": "COMPUTE_PERFCOUNT_ENABLE",
3279 "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
3283 "map": {"at": 47152, "to": "mm"},
3284 "name": "COMPUTE_PGM_LO",
3285 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3289 "map": {"at": 47156, "to": "mm"},
3290 "name": "COMPUTE_PGM_HI",
3291 "type_ref": "COMPUTE_PGM_HI"
3295 "map": {"at": 47160, "to": "mm"},
3296 "name": "COMPUTE_DISPATCH_PKT_ADDR_LO",
3297 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3301 "map": {"at": 47164, "to": "mm"},
3302 "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
3303 "type_ref": "COMPUTE_PGM_HI"
3307 "map": {"at": 47168, "to": "mm"},
3308 "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO",
3309 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3313 "map": {"at": 47172, "to": "mm"},
3314 "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
3315 "type_ref": "COMPUTE_PGM_HI"
3319 "map": {"at": 47176, "to": "mm"},
3320 "name": "COMPUTE_PGM_RSRC1",
3321 "type_ref": "COMPUTE_PGM_RSRC1"
3325 "map": {"at": 47180, "to": "mm"},
3326 "name": "COMPUTE_PGM_RSRC2",
3327 "type_ref": "COMPUTE_PGM_RSRC2"
3331 "map": {"at": 47184, "to": "mm"},
3332 "name": "COMPUTE_VMID",
3333 "type_ref": "COMPUTE_VMID"
3337 "map": {"at": 47188, "to": "mm"},
3338 "name": "COMPUTE_RESOURCE_LIMITS",
3339 "type_ref": "COMPUTE_RESOURCE_LIMITS"
3343 "map": {"at": 47192, "to": "mm"},
3344 "name": "COMPUTE_DESTINATION_EN_SE0",
3345 "type_ref": "COMPUTE_DESTINATION_EN_SE0"
3349 "map": {"at": 47196, "to": "mm"},
3350 "name": "COMPUTE_DESTINATION_EN_SE1",
3351 "type_ref": "COMPUTE_DESTINATION_EN_SE0"
3355 "map": {"at": 47200, "to": "mm"},
3356 "name": "COMPUTE_TMPRING_SIZE",
3357 "type_ref": "COMPUTE_TMPRING_SIZE"
3361 "map": {"at": 47204, "to": "mm"},
3362 "name": "COMPUTE_DESTINATION_EN_SE2",
3363 "type_ref": "COMPUTE_DESTINATION_EN_SE0"
3367 "map": {"at": 47208, "to": "mm"},
3368 "name": "COMPUTE_DESTINATION_EN_SE3",
3369 "type_ref": "COMPUTE_DESTINATION_EN_SE0"
3373 "map": {"at": 47212, "to": "mm"},
3374 "name": "COMPUTE_RESTART_X",
3375 "type_ref": "COMPUTE_RESTART_X"
3379 "map": {"at": 47216, "to": "mm"},
3380 "name": "COMPUTE_RESTART_Y",
3381 "type_ref": "COMPUTE_RESTART_X"
3385 "map": {"at": 47220, "to": "mm"},
3386 "name": "COMPUTE_RESTART_Z",
3387 "type_ref": "COMPUTE_RESTART_X"
3391 "map": {"at": 47224, "to": "mm"},
3392 "name": "COMPUTE_THREAD_TRACE_ENABLE",
3393 "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
3397 "map": {"at": 47228, "to": "mm"},
3398 "name": "COMPUTE_MISC_RESERVED",
3399 "type_ref": "COMPUTE_MISC_RESERVED"
3403 "map": {"at": 47232, "to": "mm"},
3404 "name": "COMPUTE_DISPATCH_ID",
3405 "type_ref": "COMPUTE_DISPATCH_ID"
3409 "map": {"at": 47236, "to": "mm"},
3410 "name": "COMPUTE_THREADGROUP_ID",
3411 "type_ref": "COMPUTE_THREADGROUP_ID"
3415 "map": {"at": 47240, "to": "mm"},
3416 "name": "COMPUTE_REQ_CTRL",
3417 "type_ref": "COMPUTE_REQ_CTRL"
3421 "map": {"at": 47248, "to": "mm"},
3422 "name": "COMPUTE_USER_ACCUM_0",
3423 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3427 "map": {"at": 47252, "to": "mm"},
3428 "name": "COMPUTE_USER_ACCUM_1",
3429 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3433 "map": {"at": 47256, "to": "mm"},
3434 "name": "COMPUTE_USER_ACCUM_2",
3435 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3439 "map": {"at": 47260, "to": "mm"},
3440 "name": "COMPUTE_USER_ACCUM_3",
3441 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3445 "map": {"at": 47264, "to": "mm"},
3446 "name": "COMPUTE_PGM_RSRC3",
3447 "type_ref": "COMPUTE_PGM_RSRC3"
3451 "map": {"at": 47268, "to": "mm"},
3452 "name": "COMPUTE_DDID_INDEX",
3453 "type_ref": "COMPUTE_DDID_INDEX"
3457 "map": {"at": 47272, "to": "mm"},
3458 "name": "COMPUTE_SHADER_CHKSUM",
3459 "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
3463 "map": {"at": 47276, "to": "mm"},
3464 "name": "COMPUTE_RELAUNCH",
3465 "type_ref": "COMPUTE_RELAUNCH"
3469 "map": {"at": 47280, "to": "mm"},
3470 "name": "COMPUTE_WAVE_RESTORE_ADDR_LO",
3471 "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_LO"
3475 "map": {"at": 47284, "to": "mm"},
3476 "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
3477 "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
3481 "map": {"at": 47288, "to": "mm"},
3482 "name": "COMPUTE_RELAUNCH2",
3483 "type_ref": "COMPUTE_RELAUNCH"
3487 "map": {"at": 47360, "to": "mm"},
3488 "name": "COMPUTE_USER_DATA_0",
3489 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3493 "map": {"at": 47364, "to": "mm"},
3494 "name": "COMPUTE_USER_DATA_1",
3495 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3499 "map": {"at": 47368, "to": "mm"},
3500 "name": "COMPUTE_USER_DATA_2",
3501 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3505 "map": {"at": 47372, "to": "mm"},
3506 "name": "COMPUTE_USER_DATA_3",
3507 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3511 "map": {"at": 47376, "to": "mm"},
3512 "name": "COMPUTE_USER_DATA_4",
3513 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3517 "map": {"at": 47380, "to": "mm"},
3518 "name": "COMPUTE_USER_DATA_5",
3519 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3523 "map": {"at": 47384, "to": "mm"},
3524 "name": "COMPUTE_USER_DATA_6",
3525 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3529 "map": {"at": 47388, "to": "mm"},
3530 "name": "COMPUTE_USER_DATA_7",
3531 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3535 "map": {"at": 47392, "to": "mm"},
3536 "name": "COMPUTE_USER_DATA_8",
3537 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3541 "map": {"at": 47396, "to": "mm"},
3542 "name": "COMPUTE_USER_DATA_9",
3543 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3547 "map": {"at": 47400, "to": "mm"},
3548 "name": "COMPUTE_USER_DATA_10",
3549 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3553 "map": {"at": 47404, "to": "mm"},
3554 "name": "COMPUTE_USER_DATA_11",
3555 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3559 "map": {"at": 47408, "to": "mm"},
3560 "name": "COMPUTE_USER_DATA_12",
3561 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3565 "map": {"at": 47412, "to": "mm"},
3566 "name": "COMPUTE_USER_DATA_13",
3567 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3571 "map": {"at": 47416, "to": "mm"},
3572 "name": "COMPUTE_USER_DATA_14",
3573 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3577 "map": {"at": 47420, "to": "mm"},
3578 "name": "COMPUTE_USER_DATA_15",
3579 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3583 "map": {"at": 47604, "to": "mm"},
3584 "name": "COMPUTE_DISPATCH_TUNNEL",
3585 "type_ref": "COMPUTE_DISPATCH_TUNNEL"
3589 "map": {"at": 47608, "to": "mm"},
3590 "name": "COMPUTE_DISPATCH_END",
3591 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3595 "map": {"at": 47612, "to": "mm"},
3596 "name": "COMPUTE_NOWHERE",
3597 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3601 "map": {"at": 163840, "to": "mm"},
3602 "name": "DB_RENDER_CONTROL",
3603 "type_ref": "DB_RENDER_CONTROL"
3607 "map": {"at": 163844, "to": "mm"},
3608 "name": "DB_COUNT_CONTROL",
3609 "type_ref": "DB_COUNT_CONTROL"
3613 "map": {"at": 163848, "to": "mm"},
3614 "name": "DB_DEPTH_VIEW",
3615 "type_ref": "DB_DEPTH_VIEW"
3619 "map": {"at": 163852, "to": "mm"},
3620 "name": "DB_RENDER_OVERRIDE",
3621 "type_ref": "DB_RENDER_OVERRIDE"
3625 "map": {"at": 163856, "to": "mm"},
3626 "name": "DB_RENDER_OVERRIDE2",
3627 "type_ref": "DB_RENDER_OVERRIDE2"
3631 "map": {"at": 163860, "to": "mm"},
3632 "name": "DB_HTILE_DATA_BASE",
3633 "type_ref": "DB_HTILE_DATA_BASE"
3637 "map": {"at": 163868, "to": "mm"},
3638 "name": "DB_DEPTH_SIZE_XY",
3639 "type_ref": "DB_DEPTH_SIZE_XY"
3643 "map": {"at": 163872, "to": "mm"},
3644 "name": "DB_DEPTH_BOUNDS_MIN",
3645 "type_ref": "DB_DEPTH_BOUNDS_MIN"
3649 "map": {"at": 163876, "to": "mm"},
3650 "name": "DB_DEPTH_BOUNDS_MAX",
3651 "type_ref": "DB_DEPTH_BOUNDS_MAX"
3655 "map": {"at": 163880, "to": "mm"},
3656 "name": "DB_STENCIL_CLEAR",
3657 "type_ref": "DB_STENCIL_CLEAR"
3661 "map": {"at": 163884, "to": "mm"},
3662 "name": "DB_DEPTH_CLEAR",
3663 "type_ref": "DB_DEPTH_CLEAR"
3667 "map": {"at": 163888, "to": "mm"},
3668 "name": "PA_SC_SCREEN_SCISSOR_TL",
3669 "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
3673 "map": {"at": 163892, "to": "mm"},
3674 "name": "PA_SC_SCREEN_SCISSOR_BR",
3675 "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
3679 "map": {"at": 163896, "to": "mm"},
3680 "name": "DB_DFSM_CONTROL",
3681 "type_ref": "DB_DFSM_CONTROL"
3685 "map": {"at": 163900, "to": "mm"},
3686 "name": "DB_RESERVED_REG_2",
3687 "type_ref": "DB_RESERVED_REG_2"
3691 "map": {"at": 163904, "to": "mm"},
3692 "name": "DB_Z_INFO",
3693 "type_ref": "DB_Z_INFO"
3697 "map": {"at": 163908, "to": "mm"},
3698 "name": "DB_STENCIL_INFO",
3699 "type_ref": "DB_STENCIL_INFO"
3703 "map": {"at": 163912, "to": "mm"},
3704 "name": "DB_Z_READ_BASE",
3705 "type_ref": "DB_HTILE_DATA_BASE"
3709 "map": {"at": 163916, "to": "mm"},
3710 "name": "DB_STENCIL_READ_BASE",
3711 "type_ref": "DB_HTILE_DATA_BASE"
3715 "map": {"at": 163920, "to": "mm"},
3716 "name": "DB_Z_WRITE_BASE",
3717 "type_ref": "DB_HTILE_DATA_BASE"
3721 "map": {"at": 163924, "to": "mm"},
3722 "name": "DB_STENCIL_WRITE_BASE",
3723 "type_ref": "DB_HTILE_DATA_BASE"
3727 "map": {"at": 163928, "to": "mm"},
3728 "name": "DB_RESERVED_REG_1",
3729 "type_ref": "DB_RESERVED_REG_1"
3733 "map": {"at": 163932, "to": "mm"},
3734 "name": "DB_RESERVED_REG_3",
3735 "type_ref": "DB_RESERVED_REG_3"
3739 "map": {"at": 163944, "to": "mm"},
3740 "name": "DB_Z_READ_BASE_HI",
3741 "type_ref": "DB_Z_READ_BASE_HI"
3745 "map": {"at": 163948, "to": "mm"},
3746 "name": "DB_STENCIL_READ_BASE_HI",
3747 "type_ref": "DB_Z_READ_BASE_HI"
3751 "map": {"at": 163952, "to": "mm"},
3752 "name": "DB_Z_WRITE_BASE_HI",
3753 "type_ref": "DB_Z_READ_BASE_HI"
3757 "map": {"at": 163956, "to": "mm"},
3758 "name": "DB_STENCIL_WRITE_BASE_HI",
3759 "type_ref": "DB_Z_READ_BASE_HI"
3763 "map": {"at": 163960, "to": "mm"},
3764 "name": "DB_HTILE_DATA_BASE_HI",
3765 "type_ref": "DB_Z_READ_BASE_HI"
3769 "map": {"at": 163964, "to": "mm"},
3770 "name": "DB_RMI_L2_CACHE_CONTROL",
3771 "type_ref": "DB_RMI_L2_CACHE_CONTROL"
3775 "map": {"at": 163968, "to": "mm"},
3776 "name": "TA_BC_BASE_ADDR",
3777 "type_ref": "TA_BC_BASE_ADDR"
3781 "map": {"at": 163972, "to": "mm"},
3782 "name": "TA_BC_BASE_ADDR_HI",
3783 "type_ref": "TA_BC_BASE_ADDR_HI"
3787 "map": {"at": 164328, "to": "mm"},
3788 "name": "COHER_DEST_BASE_HI_0",
3789 "type_ref": "COHER_DEST_BASE_HI_0"
3793 "map": {"at": 164332, "to": "mm"},
3794 "name": "COHER_DEST_BASE_HI_1",
3795 "type_ref": "COHER_DEST_BASE_HI_0"
3799 "map": {"at": 164336, "to": "mm"},
3800 "name": "COHER_DEST_BASE_HI_2",
3801 "type_ref": "COHER_DEST_BASE_HI_0"
3805 "map": {"at": 164340, "to": "mm"},
3806 "name": "COHER_DEST_BASE_HI_3",
3807 "type_ref": "COHER_DEST_BASE_HI_0"
3811 "map": {"at": 164344, "to": "mm"},
3812 "name": "COHER_DEST_BASE_2",
3813 "type_ref": "COHER_DEST_BASE_2"
3817 "map": {"at": 164348, "to": "mm"},
3818 "name": "COHER_DEST_BASE_3",
3819 "type_ref": "COHER_DEST_BASE_2"
3823 "map": {"at": 164352, "to": "mm"},
3824 "name": "PA_SC_WINDOW_OFFSET",
3825 "type_ref": "PA_SC_WINDOW_OFFSET"
3829 "map": {"at": 164356, "to": "mm"},
3830 "name": "PA_SC_WINDOW_SCISSOR_TL",
3831 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3835 "map": {"at": 164360, "to": "mm"},
3836 "name": "PA_SC_WINDOW_SCISSOR_BR",
3837 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3841 "map": {"at": 164364, "to": "mm"},
3842 "name": "PA_SC_CLIPRECT_RULE",
3843 "type_ref": "PA_SC_CLIPRECT_RULE"
3847 "map": {"at": 164368, "to": "mm"},
3848 "name": "PA_SC_CLIPRECT_0_TL",
3849 "type_ref": "PA_SC_CLIPRECT_0_TL"
3853 "map": {"at": 164372, "to": "mm"},
3854 "name": "PA_SC_CLIPRECT_0_BR",
3855 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3859 "map": {"at": 164376, "to": "mm"},
3860 "name": "PA_SC_CLIPRECT_1_TL",
3861 "type_ref": "PA_SC_CLIPRECT_0_TL"
3865 "map": {"at": 164380, "to": "mm"},
3866 "name": "PA_SC_CLIPRECT_1_BR",
3867 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3871 "map": {"at": 164384, "to": "mm"},
3872 "name": "PA_SC_CLIPRECT_2_TL",
3873 "type_ref": "PA_SC_CLIPRECT_0_TL"
3877 "map": {"at": 164388, "to": "mm"},
3878 "name": "PA_SC_CLIPRECT_2_BR",
3879 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3883 "map": {"at": 164392, "to": "mm"},
3884 "name": "PA_SC_CLIPRECT_3_TL",
3885 "type_ref": "PA_SC_CLIPRECT_0_TL"
3889 "map": {"at": 164396, "to": "mm"},
3890 "name": "PA_SC_CLIPRECT_3_BR",
3891 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3895 "map": {"at": 164400, "to": "mm"},
3896 "name": "PA_SC_EDGERULE",
3897 "type_ref": "PA_SC_EDGERULE"
3901 "map": {"at": 164404, "to": "mm"},
3902 "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3903 "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3907 "map": {"at": 164408, "to": "mm"},
3908 "name": "CB_TARGET_MASK",
3909 "type_ref": "CB_TARGET_MASK"
3913 "map": {"at": 164412, "to": "mm"},
3914 "name": "CB_SHADER_MASK",
3915 "type_ref": "CB_SHADER_MASK"
3919 "map": {"at": 164416, "to": "mm"},
3920 "name": "PA_SC_GENERIC_SCISSOR_TL",
3921 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3925 "map": {"at": 164420, "to": "mm"},
3926 "name": "PA_SC_GENERIC_SCISSOR_BR",
3927 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3931 "map": {"at": 164424, "to": "mm"},
3932 "name": "COHER_DEST_BASE_0",
3933 "type_ref": "COHER_DEST_BASE_2"
3937 "map": {"at": 164428, "to": "mm"},
3938 "name": "COHER_DEST_BASE_1",
3939 "type_ref": "COHER_DEST_BASE_2"
3943 "map": {"at": 164432, "to": "mm"},
3944 "name": "PA_SC_VPORT_SCISSOR_0_TL",
3945 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3949 "map": {"at": 164436, "to": "mm"},
3950 "name": "PA_SC_VPORT_SCISSOR_0_BR",
3951 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3955 "map": {"at": 164440, "to": "mm"},
3956 "name": "PA_SC_VPORT_SCISSOR_1_TL",
3957 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3961 "map": {"at": 164444, "to": "mm"},
3962 "name": "PA_SC_VPORT_SCISSOR_1_BR",
3963 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3967 "map": {"at": 164448, "to": "mm"},
3968 "name": "PA_SC_VPORT_SCISSOR_2_TL",
3969 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3973 "map": {"at": 164452, "to": "mm"},
3974 "name": "PA_SC_VPORT_SCISSOR_2_BR",
3975 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3979 "map": {"at": 164456, "to": "mm"},
3980 "name": "PA_SC_VPORT_SCISSOR_3_TL",
3981 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3985 "map": {"at": 164460, "to": "mm"},
3986 "name": "PA_SC_VPORT_SCISSOR_3_BR",
3987 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3991 "map": {"at": 164464, "to": "mm"},
3992 "name": "PA_SC_VPORT_SCISSOR_4_TL",
3993 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3997 "map": {"at": 164468, "to": "mm"},
3998 "name": "PA_SC_VPORT_SCISSOR_4_BR",
3999 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4003 "map": {"at": 164472, "to": "mm"},
4004 "name": "PA_SC_VPORT_SCISSOR_5_TL",
4005 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4009 "map": {"at": 164476, "to": "mm"},
4010 "name": "PA_SC_VPORT_SCISSOR_5_BR",
4011 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4015 "map": {"at": 164480, "to": "mm"},
4016 "name": "PA_SC_VPORT_SCISSOR_6_TL",
4017 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4021 "map": {"at": 164484, "to": "mm"},
4022 "name": "PA_SC_VPORT_SCISSOR_6_BR",
4023 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4027 "map": {"at": 164488, "to": "mm"},
4028 "name": "PA_SC_VPORT_SCISSOR_7_TL",
4029 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4033 "map": {"at": 164492, "to": "mm"},
4034 "name": "PA_SC_VPORT_SCISSOR_7_BR",
4035 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4039 "map": {"at": 164496, "to": "mm"},
4040 "name": "PA_SC_VPORT_SCISSOR_8_TL",
4041 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4045 "map": {"at": 164500, "to": "mm"},
4046 "name": "PA_SC_VPORT_SCISSOR_8_BR",
4047 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4051 "map": {"at": 164504, "to": "mm"},
4052 "name": "PA_SC_VPORT_SCISSOR_9_TL",
4053 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4057 "map": {"at": 164508, "to": "mm"},
4058 "name": "PA_SC_VPORT_SCISSOR_9_BR",
4059 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4063 "map": {"at": 164512, "to": "mm"},
4064 "name": "PA_SC_VPORT_SCISSOR_10_TL",
4065 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4069 "map": {"at": 164516, "to": "mm"},
4070 "name": "PA_SC_VPORT_SCISSOR_10_BR",
4071 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4075 "map": {"at": 164520, "to": "mm"},
4076 "name": "PA_SC_VPORT_SCISSOR_11_TL",
4077 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4081 "map": {"at": 164524, "to": "mm"},
4082 "name": "PA_SC_VPORT_SCISSOR_11_BR",
4083 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4087 "map": {"at": 164528, "to": "mm"},
4088 "name": "PA_SC_VPORT_SCISSOR_12_TL",
4089 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4093 "map": {"at": 164532, "to": "mm"},
4094 "name": "PA_SC_VPORT_SCISSOR_12_BR",
4095 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4099 "map": {"at": 164536, "to": "mm"},
4100 "name": "PA_SC_VPORT_SCISSOR_13_TL",
4101 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4105 "map": {"at": 164540, "to": "mm"},
4106 "name": "PA_SC_VPORT_SCISSOR_13_BR",
4107 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4111 "map": {"at": 164544, "to": "mm"},
4112 "name": "PA_SC_VPORT_SCISSOR_14_TL",
4113 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4117 "map": {"at": 164548, "to": "mm"},
4118 "name": "PA_SC_VPORT_SCISSOR_14_BR",
4119 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4123 "map": {"at": 164552, "to": "mm"},
4124 "name": "PA_SC_VPORT_SCISSOR_15_TL",
4125 "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4129 "map": {"at": 164556, "to": "mm"},
4130 "name": "PA_SC_VPORT_SCISSOR_15_BR",
4131 "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4135 "map": {"at": 164560, "to": "mm"},
4136 "name": "PA_SC_VPORT_ZMIN_0",
4137 "type_ref": "PA_SC_VPORT_ZMIN_0"
4141 "map": {"at": 164564, "to": "mm"},
4142 "name": "PA_SC_VPORT_ZMAX_0",
4143 "type_ref": "PA_SC_VPORT_ZMAX_0"
4147 "map": {"at": 164568, "to": "mm"},
4148 "name": "PA_SC_VPORT_ZMIN_1",
4149 "type_ref": "PA_SC_VPORT_ZMIN_0"
4153 "map": {"at": 164572, "to": "mm"},
4154 "name": "PA_SC_VPORT_ZMAX_1",
4155 "type_ref": "PA_SC_VPORT_ZMAX_0"
4159 "map": {"at": 164576, "to": "mm"},
4160 "name": "PA_SC_VPORT_ZMIN_2",
4161 "type_ref": "PA_SC_VPORT_ZMIN_0"
4165 "map": {"at": 164580, "to": "mm"},
4166 "name": "PA_SC_VPORT_ZMAX_2",
4167 "type_ref": "PA_SC_VPORT_ZMAX_0"
4171 "map": {"at": 164584, "to": "mm"},
4172 "name": "PA_SC_VPORT_ZMIN_3",
4173 "type_ref": "PA_SC_VPORT_ZMIN_0"
4177 "map": {"at": 164588, "to": "mm"},
4178 "name": "PA_SC_VPORT_ZMAX_3",
4179 "type_ref": "PA_SC_VPORT_ZMAX_0"
4183 "map": {"at": 164592, "to": "mm"},
4184 "name": "PA_SC_VPORT_ZMIN_4",
4185 "type_ref": "PA_SC_VPORT_ZMIN_0"
4189 "map": {"at": 164596, "to": "mm"},
4190 "name": "PA_SC_VPORT_ZMAX_4",
4191 "type_ref": "PA_SC_VPORT_ZMAX_0"
4195 "map": {"at": 164600, "to": "mm"},
4196 "name": "PA_SC_VPORT_ZMIN_5",
4197 "type_ref": "PA_SC_VPORT_ZMIN_0"
4201 "map": {"at": 164604, "to": "mm"},
4202 "name": "PA_SC_VPORT_ZMAX_5",
4203 "type_ref": "PA_SC_VPORT_ZMAX_0"
4207 "map": {"at": 164608, "to": "mm"},
4208 "name": "PA_SC_VPORT_ZMIN_6",
4209 "type_ref": "PA_SC_VPORT_ZMIN_0"
4213 "map": {"at": 164612, "to": "mm"},
4214 "name": "PA_SC_VPORT_ZMAX_6",
4215 "type_ref": "PA_SC_VPORT_ZMAX_0"
4219 "map": {"at": 164616, "to": "mm"},
4220 "name": "PA_SC_VPORT_ZMIN_7",
4221 "type_ref": "PA_SC_VPORT_ZMIN_0"
4225 "map": {"at": 164620, "to": "mm"},
4226 "name": "PA_SC_VPORT_ZMAX_7",
4227 "type_ref": "PA_SC_VPORT_ZMAX_0"
4231 "map": {"at": 164624, "to": "mm"},
4232 "name": "PA_SC_VPORT_ZMIN_8",
4233 "type_ref": "PA_SC_VPORT_ZMIN_0"
4237 "map": {"at": 164628, "to": "mm"},
4238 "name": "PA_SC_VPORT_ZMAX_8",
4239 "type_ref": "PA_SC_VPORT_ZMAX_0"
4243 "map": {"at": 164632, "to": "mm"},
4244 "name": "PA_SC_VPORT_ZMIN_9",
4245 "type_ref": "PA_SC_VPORT_ZMIN_0"
4249 "map": {"at": 164636, "to": "mm"},
4250 "name": "PA_SC_VPORT_ZMAX_9",
4251 "type_ref": "PA_SC_VPORT_ZMAX_0"
4255 "map": {"at": 164640, "to": "mm"},
4256 "name": "PA_SC_VPORT_ZMIN_10",
4257 "type_ref": "PA_SC_VPORT_ZMIN_0"
4261 "map": {"at": 164644, "to": "mm"},
4262 "name": "PA_SC_VPORT_ZMAX_10",
4263 "type_ref": "PA_SC_VPORT_ZMAX_0"
4267 "map": {"at": 164648, "to": "mm"},
4268 "name": "PA_SC_VPORT_ZMIN_11",
4269 "type_ref": "PA_SC_VPORT_ZMIN_0"
4273 "map": {"at": 164652, "to": "mm"},
4274 "name": "PA_SC_VPORT_ZMAX_11",
4275 "type_ref": "PA_SC_VPORT_ZMAX_0"
4279 "map": {"at": 164656, "to": "mm"},
4280 "name": "PA_SC_VPORT_ZMIN_12",
4281 "type_ref": "PA_SC_VPORT_ZMIN_0"
4285 "map": {"at": 164660, "to": "mm"},
4286 "name": "PA_SC_VPORT_ZMAX_12",
4287 "type_ref": "PA_SC_VPORT_ZMAX_0"
4291 "map": {"at": 164664, "to": "mm"},
4292 "name": "PA_SC_VPORT_ZMIN_13",
4293 "type_ref": "PA_SC_VPORT_ZMIN_0"
4297 "map": {"at": 164668, "to": "mm"},
4298 "name": "PA_SC_VPORT_ZMAX_13",
4299 "type_ref": "PA_SC_VPORT_ZMAX_0"
4303 "map": {"at": 164672, "to": "mm"},
4304 "name": "PA_SC_VPORT_ZMIN_14",
4305 "type_ref": "PA_SC_VPORT_ZMIN_0"
4309 "map": {"at": 164676, "to": "mm"},
4310 "name": "PA_SC_VPORT_ZMAX_14",
4311 "type_ref": "PA_SC_VPORT_ZMAX_0"
4315 "map": {"at": 164680, "to": "mm"},
4316 "name": "PA_SC_VPORT_ZMIN_15",
4317 "type_ref": "PA_SC_VPORT_ZMIN_0"
4321 "map": {"at": 164684, "to": "mm"},
4322 "name": "PA_SC_VPORT_ZMAX_15",
4323 "type_ref": "PA_SC_VPORT_ZMAX_0"
4327 "map": {"at": 164688, "to": "mm"},
4328 "name": "PA_SC_RASTER_CONFIG",
4329 "type_ref": "PA_SC_RASTER_CONFIG"
4333 "map": {"at": 164692, "to": "mm"},
4334 "name": "PA_SC_RASTER_CONFIG_1",
4335 "type_ref": "PA_SC_RASTER_CONFIG_1"
4339 "map": {"at": 164696, "to": "mm"},
4340 "name": "PA_SC_SCREEN_EXTENT_CONTROL",
4341 "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
4345 "map": {"at": 164700, "to": "mm"},
4346 "name": "PA_SC_TILE_STEERING_OVERRIDE",
4347 "type_ref": "PA_SC_TILE_STEERING_OVERRIDE"
4351 "map": {"at": 164704, "to": "mm"},
4352 "name": "CP_PERFMON_CNTX_CNTL",
4353 "type_ref": "CP_PERFMON_CNTX_CNTL"
4357 "map": {"at": 164708, "to": "mm"},
4358 "name": "CP_PIPEID",
4359 "type_ref": "CP_PIPEID"
4363 "map": {"at": 164712, "to": "mm"},
4365 "type_ref": "CP_VMID"
4369 "map": {"at": 164768, "to": "mm"},
4370 "name": "PA_SC_RIGHT_VERT_GRID",
4371 "type_ref": "PA_SC_RIGHT_VERT_GRID"
4375 "map": {"at": 164772, "to": "mm"},
4376 "name": "PA_SC_LEFT_VERT_GRID",
4377 "type_ref": "PA_SC_RIGHT_VERT_GRID"
4381 "map": {"at": 164776, "to": "mm"},
4382 "name": "PA_SC_HORIZ_GRID",
4383 "type_ref": "PA_SC_HORIZ_GRID"
4387 "map": {"at": 164864, "to": "mm"},
4388 "name": "VGT_MAX_VTX_INDX",
4389 "type_ref": "VGT_MAX_VTX_INDX"
4393 "map": {"at": 164868, "to": "mm"},
4394 "name": "VGT_MIN_VTX_INDX",
4395 "type_ref": "VGT_MIN_VTX_INDX"
4399 "map": {"at": 164872, "to": "mm"},
4400 "name": "VGT_INDX_OFFSET",
4401 "type_ref": "VGT_INDX_OFFSET"
4405 "map": {"at": 164876, "to": "mm"},
4406 "name": "VGT_MULTI_PRIM_IB_RESET_INDX",
4407 "type_ref": "VGT_MULTI_PRIM_IB_RESET_INDX"
4411 "map": {"at": 164880, "to": "mm"},
4412 "name": "CB_RMI_GL2_CACHE_CONTROL",
4413 "type_ref": "CB_RMI_GL2_CACHE_CONTROL"
4417 "map": {"at": 164884, "to": "mm"},
4418 "name": "CB_BLEND_RED",
4419 "type_ref": "CB_BLEND_RED"
4423 "map": {"at": 164888, "to": "mm"},
4424 "name": "CB_BLEND_GREEN",
4425 "type_ref": "CB_BLEND_GREEN"
4429 "map": {"at": 164892, "to": "mm"},
4430 "name": "CB_BLEND_BLUE",
4431 "type_ref": "CB_BLEND_BLUE"
4435 "map": {"at": 164896, "to": "mm"},
4436 "name": "CB_BLEND_ALPHA",
4437 "type_ref": "CB_BLEND_ALPHA"
4441 "map": {"at": 164900, "to": "mm"},
4442 "name": "CB_DCC_CONTROL",
4443 "type_ref": "CB_DCC_CONTROL"
4447 "map": {"at": 164904, "to": "mm"},
4448 "name": "CB_COVERAGE_OUT_CONTROL",
4449 "type_ref": "CB_COVERAGE_OUT_CONTROL"
4453 "map": {"at": 164908, "to": "mm"},
4454 "name": "DB_STENCIL_CONTROL",
4455 "type_ref": "DB_STENCIL_CONTROL"
4459 "map": {"at": 164912, "to": "mm"},
4460 "name": "DB_STENCILREFMASK",
4461 "type_ref": "DB_STENCILREFMASK"
4465 "map": {"at": 164916, "to": "mm"},
4466 "name": "DB_STENCILREFMASK_BF",
4467 "type_ref": "DB_STENCILREFMASK_BF"
4471 "map": {"at": 164924, "to": "mm"},
4472 "name": "PA_CL_VPORT_XSCALE",
4473 "type_ref": "PA_CL_VPORT_XSCALE"
4477 "map": {"at": 164928, "to": "mm"},
4478 "name": "PA_CL_VPORT_XOFFSET",
4479 "type_ref": "PA_CL_VPORT_XOFFSET"
4483 "map": {"at": 164932, "to": "mm"},
4484 "name": "PA_CL_VPORT_YSCALE",
4485 "type_ref": "PA_CL_VPORT_YSCALE"
4489 "map": {"at": 164936, "to": "mm"},
4490 "name": "PA_CL_VPORT_YOFFSET",
4491 "type_ref": "PA_CL_VPORT_YOFFSET"
4495 "map": {"at": 164940, "to": "mm"},
4496 "name": "PA_CL_VPORT_ZSCALE",
4497 "type_ref": "PA_CL_VPORT_ZSCALE"
4501 "map": {"at": 164944, "to": "mm"},
4502 "name": "PA_CL_VPORT_ZOFFSET",
4503 "type_ref": "PA_CL_VPORT_ZOFFSET"
4507 "map": {"at": 164948, "to": "mm"},
4508 "name": "PA_CL_VPORT_XSCALE_1",
4509 "type_ref": "PA_CL_VPORT_XSCALE"
4513 "map": {"at": 164952, "to": "mm"},
4514 "name": "PA_CL_VPORT_XOFFSET_1",
4515 "type_ref": "PA_CL_VPORT_XOFFSET"
4519 "map": {"at": 164956, "to": "mm"},
4520 "name": "PA_CL_VPORT_YSCALE_1",
4521 "type_ref": "PA_CL_VPORT_YSCALE"
4525 "map": {"at": 164960, "to": "mm"},
4526 "name": "PA_CL_VPORT_YOFFSET_1",
4527 "type_ref": "PA_CL_VPORT_YOFFSET"
4531 "map": {"at": 164964, "to": "mm"},
4532 "name": "PA_CL_VPORT_ZSCALE_1",
4533 "type_ref": "PA_CL_VPORT_ZSCALE"
4537 "map": {"at": 164968, "to": "mm"},
4538 "name": "PA_CL_VPORT_ZOFFSET_1",
4539 "type_ref": "PA_CL_VPORT_ZOFFSET"
4543 "map": {"at": 164972, "to": "mm"},
4544 "name": "PA_CL_VPORT_XSCALE_2",
4545 "type_ref": "PA_CL_VPORT_XSCALE"
4549 "map": {"at": 164976, "to": "mm"},
4550 "name": "PA_CL_VPORT_XOFFSET_2",
4551 "type_ref": "PA_CL_VPORT_XOFFSET"
4555 "map": {"at": 164980, "to": "mm"},
4556 "name": "PA_CL_VPORT_YSCALE_2",
4557 "type_ref": "PA_CL_VPORT_YSCALE"
4561 "map": {"at": 164984, "to": "mm"},
4562 "name": "PA_CL_VPORT_YOFFSET_2",
4563 "type_ref": "PA_CL_VPORT_YOFFSET"
4567 "map": {"at": 164988, "to": "mm"},
4568 "name": "PA_CL_VPORT_ZSCALE_2",
4569 "type_ref": "PA_CL_VPORT_ZSCALE"
4573 "map": {"at": 164992, "to": "mm"},
4574 "name": "PA_CL_VPORT_ZOFFSET_2",
4575 "type_ref": "PA_CL_VPORT_ZOFFSET"
4579 "map": {"at": 164996, "to": "mm"},
4580 "name": "PA_CL_VPORT_XSCALE_3",
4581 "type_ref": "PA_CL_VPORT_XSCALE"
4585 "map": {"at": 165000, "to": "mm"},
4586 "name": "PA_CL_VPORT_XOFFSET_3",
4587 "type_ref": "PA_CL_VPORT_XOFFSET"
4591 "map": {"at": 165004, "to": "mm"},
4592 "name": "PA_CL_VPORT_YSCALE_3",
4593 "type_ref": "PA_CL_VPORT_YSCALE"
4597 "map": {"at": 165008, "to": "mm"},
4598 "name": "PA_CL_VPORT_YOFFSET_3",
4599 "type_ref": "PA_CL_VPORT_YOFFSET"
4603 "map": {"at": 165012, "to": "mm"},
4604 "name": "PA_CL_VPORT_ZSCALE_3",
4605 "type_ref": "PA_CL_VPORT_ZSCALE"
4609 "map": {"at": 165016, "to": "mm"},
4610 "name": "PA_CL_VPORT_ZOFFSET_3",
4611 "type_ref": "PA_CL_VPORT_ZOFFSET"
4615 "map": {"at": 165020, "to": "mm"},
4616 "name": "PA_CL_VPORT_XSCALE_4",
4617 "type_ref": "PA_CL_VPORT_XSCALE"
4621 "map": {"at": 165024, "to": "mm"},
4622 "name": "PA_CL_VPORT_XOFFSET_4",
4623 "type_ref": "PA_CL_VPORT_XOFFSET"
4627 "map": {"at": 165028, "to": "mm"},
4628 "name": "PA_CL_VPORT_YSCALE_4",
4629 "type_ref": "PA_CL_VPORT_YSCALE"
4633 "map": {"at": 165032, "to": "mm"},
4634 "name": "PA_CL_VPORT_YOFFSET_4",
4635 "type_ref": "PA_CL_VPORT_YOFFSET"
4639 "map": {"at": 165036, "to": "mm"},
4640 "name": "PA_CL_VPORT_ZSCALE_4",
4641 "type_ref": "PA_CL_VPORT_ZSCALE"
4645 "map": {"at": 165040, "to": "mm"},
4646 "name": "PA_CL_VPORT_ZOFFSET_4",
4647 "type_ref": "PA_CL_VPORT_ZOFFSET"
4651 "map": {"at": 165044, "to": "mm"},
4652 "name": "PA_CL_VPORT_XSCALE_5",
4653 "type_ref": "PA_CL_VPORT_XSCALE"
4657 "map": {"at": 165048, "to": "mm"},
4658 "name": "PA_CL_VPORT_XOFFSET_5",
4659 "type_ref": "PA_CL_VPORT_XOFFSET"
4663 "map": {"at": 165052, "to": "mm"},
4664 "name": "PA_CL_VPORT_YSCALE_5",
4665 "type_ref": "PA_CL_VPORT_YSCALE"
4669 "map": {"at": 165056, "to": "mm"},
4670 "name": "PA_CL_VPORT_YOFFSET_5",
4671 "type_ref": "PA_CL_VPORT_YOFFSET"
4675 "map": {"at": 165060, "to": "mm"},
4676 "name": "PA_CL_VPORT_ZSCALE_5",
4677 "type_ref": "PA_CL_VPORT_ZSCALE"
4681 "map": {"at": 165064, "to": "mm"},
4682 "name": "PA_CL_VPORT_ZOFFSET_5",
4683 "type_ref": "PA_CL_VPORT_ZOFFSET"
4687 "map": {"at": 165068, "to": "mm"},
4688 "name": "PA_CL_VPORT_XSCALE_6",
4689 "type_ref": "PA_CL_VPORT_XSCALE"
4693 "map": {"at": 165072, "to": "mm"},
4694 "name": "PA_CL_VPORT_XOFFSET_6",
4695 "type_ref": "PA_CL_VPORT_XOFFSET"
4699 "map": {"at": 165076, "to": "mm"},
4700 "name": "PA_CL_VPORT_YSCALE_6",
4701 "type_ref": "PA_CL_VPORT_YSCALE"
4705 "map": {"at": 165080, "to": "mm"},
4706 "name": "PA_CL_VPORT_YOFFSET_6",
4707 "type_ref": "PA_CL_VPORT_YOFFSET"
4711 "map": {"at": 165084, "to": "mm"},
4712 "name": "PA_CL_VPORT_ZSCALE_6",
4713 "type_ref": "PA_CL_VPORT_ZSCALE"
4717 "map": {"at": 165088, "to": "mm"},
4718 "name": "PA_CL_VPORT_ZOFFSET_6",
4719 "type_ref": "PA_CL_VPORT_ZOFFSET"
4723 "map": {"at": 165092, "to": "mm"},
4724 "name": "PA_CL_VPORT_XSCALE_7",
4725 "type_ref": "PA_CL_VPORT_XSCALE"
4729 "map": {"at": 165096, "to": "mm"},
4730 "name": "PA_CL_VPORT_XOFFSET_7",
4731 "type_ref": "PA_CL_VPORT_XOFFSET"
4735 "map": {"at": 165100, "to": "mm"},
4736 "name": "PA_CL_VPORT_YSCALE_7",
4737 "type_ref": "PA_CL_VPORT_YSCALE"
4741 "map": {"at": 165104, "to": "mm"},
4742 "name": "PA_CL_VPORT_YOFFSET_7",
4743 "type_ref": "PA_CL_VPORT_YOFFSET"
4747 "map": {"at": 165108, "to": "mm"},
4748 "name": "PA_CL_VPORT_ZSCALE_7",
4749 "type_ref": "PA_CL_VPORT_ZSCALE"
4753 "map": {"at": 165112, "to": "mm"},
4754 "name": "PA_CL_VPORT_ZOFFSET_7",
4755 "type_ref": "PA_CL_VPORT_ZOFFSET"
4759 "map": {"at": 165116, "to": "mm"},
4760 "name": "PA_CL_VPORT_XSCALE_8",
4761 "type_ref": "PA_CL_VPORT_XSCALE"
4765 "map": {"at": 165120, "to": "mm"},
4766 "name": "PA_CL_VPORT_XOFFSET_8",
4767 "type_ref": "PA_CL_VPORT_XOFFSET"
4771 "map": {"at": 165124, "to": "mm"},
4772 "name": "PA_CL_VPORT_YSCALE_8",
4773 "type_ref": "PA_CL_VPORT_YSCALE"
4777 "map": {"at": 165128, "to": "mm"},
4778 "name": "PA_CL_VPORT_YOFFSET_8",
4779 "type_ref": "PA_CL_VPORT_YOFFSET"
4783 "map": {"at": 165132, "to": "mm"},
4784 "name": "PA_CL_VPORT_ZSCALE_8",
4785 "type_ref": "PA_CL_VPORT_ZSCALE"
4789 "map": {"at": 165136, "to": "mm"},
4790 "name": "PA_CL_VPORT_ZOFFSET_8",
4791 "type_ref": "PA_CL_VPORT_ZOFFSET"
4795 "map": {"at": 165140, "to": "mm"},
4796 "name": "PA_CL_VPORT_XSCALE_9",
4797 "type_ref": "PA_CL_VPORT_XSCALE"
4801 "map": {"at": 165144, "to": "mm"},
4802 "name": "PA_CL_VPORT_XOFFSET_9",
4803 "type_ref": "PA_CL_VPORT_XOFFSET"
4807 "map": {"at": 165148, "to": "mm"},
4808 "name": "PA_CL_VPORT_YSCALE_9",
4809 "type_ref": "PA_CL_VPORT_YSCALE"
4813 "map": {"at": 165152, "to": "mm"},
4814 "name": "PA_CL_VPORT_YOFFSET_9",
4815 "type_ref": "PA_CL_VPORT_YOFFSET"
4819 "map": {"at": 165156, "to": "mm"},
4820 "name": "PA_CL_VPORT_ZSCALE_9",
4821 "type_ref": "PA_CL_VPORT_ZSCALE"
4825 "map": {"at": 165160, "to": "mm"},
4826 "name": "PA_CL_VPORT_ZOFFSET_9",
4827 "type_ref": "PA_CL_VPORT_ZOFFSET"
4831 "map": {"at": 165164, "to": "mm"},
4832 "name": "PA_CL_VPORT_XSCALE_10",
4833 "type_ref": "PA_CL_VPORT_XSCALE"
4837 "map": {"at": 165168, "to": "mm"},
4838 "name": "PA_CL_VPORT_XOFFSET_10",
4839 "type_ref": "PA_CL_VPORT_XOFFSET"
4843 "map": {"at": 165172, "to": "mm"},
4844 "name": "PA_CL_VPORT_YSCALE_10",
4845 "type_ref": "PA_CL_VPORT_YSCALE"
4849 "map": {"at": 165176, "to": "mm"},
4850 "name": "PA_CL_VPORT_YOFFSET_10",
4851 "type_ref": "PA_CL_VPORT_YOFFSET"
4855 "map": {"at": 165180, "to": "mm"},
4856 "name": "PA_CL_VPORT_ZSCALE_10",
4857 "type_ref": "PA_CL_VPORT_ZSCALE"
4861 "map": {"at": 165184, "to": "mm"},
4862 "name": "PA_CL_VPORT_ZOFFSET_10",
4863 "type_ref": "PA_CL_VPORT_ZOFFSET"
4867 "map": {"at": 165188, "to": "mm"},
4868 "name": "PA_CL_VPORT_XSCALE_11",
4869 "type_ref": "PA_CL_VPORT_XSCALE"
4873 "map": {"at": 165192, "to": "mm"},
4874 "name": "PA_CL_VPORT_XOFFSET_11",
4875 "type_ref": "PA_CL_VPORT_XOFFSET"
4879 "map": {"at": 165196, "to": "mm"},
4880 "name": "PA_CL_VPORT_YSCALE_11",
4881 "type_ref": "PA_CL_VPORT_YSCALE"
4885 "map": {"at": 165200, "to": "mm"},
4886 "name": "PA_CL_VPORT_YOFFSET_11",
4887 "type_ref": "PA_CL_VPORT_YOFFSET"
4891 "map": {"at": 165204, "to": "mm"},
4892 "name": "PA_CL_VPORT_ZSCALE_11",
4893 "type_ref": "PA_CL_VPORT_ZSCALE"
4897 "map": {"at": 165208, "to": "mm"},
4898 "name": "PA_CL_VPORT_ZOFFSET_11",
4899 "type_ref": "PA_CL_VPORT_ZOFFSET"
4903 "map": {"at": 165212, "to": "mm"},
4904 "name": "PA_CL_VPORT_XSCALE_12",
4905 "type_ref": "PA_CL_VPORT_XSCALE"
4909 "map": {"at": 165216, "to": "mm"},
4910 "name": "PA_CL_VPORT_XOFFSET_12",
4911 "type_ref": "PA_CL_VPORT_XOFFSET"
4915 "map": {"at": 165220, "to": "mm"},
4916 "name": "PA_CL_VPORT_YSCALE_12",
4917 "type_ref": "PA_CL_VPORT_YSCALE"
4921 "map": {"at": 165224, "to": "mm"},
4922 "name": "PA_CL_VPORT_YOFFSET_12",
4923 "type_ref": "PA_CL_VPORT_YOFFSET"
4927 "map": {"at": 165228, "to": "mm"},
4928 "name": "PA_CL_VPORT_ZSCALE_12",
4929 "type_ref": "PA_CL_VPORT_ZSCALE"
4933 "map": {"at": 165232, "to": "mm"},
4934 "name": "PA_CL_VPORT_ZOFFSET_12",
4935 "type_ref": "PA_CL_VPORT_ZOFFSET"
4939 "map": {"at": 165236, "to": "mm"},
4940 "name": "PA_CL_VPORT_XSCALE_13",
4941 "type_ref": "PA_CL_VPORT_XSCALE"
4945 "map": {"at": 165240, "to": "mm"},
4946 "name": "PA_CL_VPORT_XOFFSET_13",
4947 "type_ref": "PA_CL_VPORT_XOFFSET"
4951 "map": {"at": 165244, "to": "mm"},
4952 "name": "PA_CL_VPORT_YSCALE_13",
4953 "type_ref": "PA_CL_VPORT_YSCALE"
4957 "map": {"at": 165248, "to": "mm"},
4958 "name": "PA_CL_VPORT_YOFFSET_13",
4959 "type_ref": "PA_CL_VPORT_YOFFSET"
4963 "map": {"at": 165252, "to": "mm"},
4964 "name": "PA_CL_VPORT_ZSCALE_13",
4965 "type_ref": "PA_CL_VPORT_ZSCALE"
4969 "map": {"at": 165256, "to": "mm"},
4970 "name": "PA_CL_VPORT_ZOFFSET_13",
4971 "type_ref": "PA_CL_VPORT_ZOFFSET"
4975 "map": {"at": 165260, "to": "mm"},
4976 "name": "PA_CL_VPORT_XSCALE_14",
4977 "type_ref": "PA_CL_VPORT_XSCALE"
4981 "map": {"at": 165264, "to": "mm"},
4982 "name": "PA_CL_VPORT_XOFFSET_14",
4983 "type_ref": "PA_CL_VPORT_XOFFSET"
4987 "map": {"at": 165268, "to": "mm"},
4988 "name": "PA_CL_VPORT_YSCALE_14",
4989 "type_ref": "PA_CL_VPORT_YSCALE"
4993 "map": {"at": 165272, "to": "mm"},
4994 "name": "PA_CL_VPORT_YOFFSET_14",
4995 "type_ref": "PA_CL_VPORT_YOFFSET"
4999 "map": {"at": 165276, "to": "mm"},
5000 "name": "PA_CL_VPORT_ZSCALE_14",
5001 "type_ref": "PA_CL_VPORT_ZSCALE"
5005 "map": {"at": 165280, "to": "mm"},
5006 "name": "PA_CL_VPORT_ZOFFSET_14",
5007 "type_ref": "PA_CL_VPORT_ZOFFSET"
5011 "map": {"at": 165284, "to": "mm"},
5012 "name": "PA_CL_VPORT_XSCALE_15",
5013 "type_ref": "PA_CL_VPORT_XSCALE"
5017 "map": {"at": 165288, "to": "mm"},
5018 "name": "PA_CL_VPORT_XOFFSET_15",
5019 "type_ref": "PA_CL_VPORT_XOFFSET"
5023 "map": {"at": 165292, "to": "mm"},
5024 "name": "PA_CL_VPORT_YSCALE_15",
5025 "type_ref": "PA_CL_VPORT_YSCALE"
5029 "map": {"at": 165296, "to": "mm"},
5030 "name": "PA_CL_VPORT_YOFFSET_15",
5031 "type_ref": "PA_CL_VPORT_YOFFSET"
5035 "map": {"at": 165300, "to": "mm"},
5036 "name": "PA_CL_VPORT_ZSCALE_15",
5037 "type_ref": "PA_CL_VPORT_ZSCALE"
5041 "map": {"at": 165304, "to": "mm"},
5042 "name": "PA_CL_VPORT_ZOFFSET_15",
5043 "type_ref": "PA_CL_VPORT_ZOFFSET"
5047 "map": {"at": 165308, "to": "mm"},
5048 "name": "PA_CL_UCP_0_X",
5049 "type_ref": "PA_CL_UCP_0_X"
5053 "map": {"at": 165312, "to": "mm"},
5054 "name": "PA_CL_UCP_0_Y",
5055 "type_ref": "PA_CL_UCP_0_X"
5059 "map": {"at": 165316, "to": "mm"},
5060 "name": "PA_CL_UCP_0_Z",
5061 "type_ref": "PA_CL_UCP_0_X"
5065 "map": {"at": 165320, "to": "mm"},
5066 "name": "PA_CL_UCP_0_W",
5067 "type_ref": "PA_CL_UCP_0_X"
5071 "map": {"at": 165324, "to": "mm"},
5072 "name": "PA_CL_UCP_1_X",
5073 "type_ref": "PA_CL_UCP_0_X"
5077 "map": {"at": 165328, "to": "mm"},
5078 "name": "PA_CL_UCP_1_Y",
5079 "type_ref": "PA_CL_UCP_0_X"
5083 "map": {"at": 165332, "to": "mm"},
5084 "name": "PA_CL_UCP_1_Z",
5085 "type_ref": "PA_CL_UCP_0_X"
5089 "map": {"at": 165336, "to": "mm"},
5090 "name": "PA_CL_UCP_1_W",
5091 "type_ref": "PA_CL_UCP_0_X"
5095 "map": {"at": 165340, "to": "mm"},
5096 "name": "PA_CL_UCP_2_X",
5097 "type_ref": "PA_CL_UCP_0_X"
5101 "map": {"at": 165344, "to": "mm"},
5102 "name": "PA_CL_UCP_2_Y",
5103 "type_ref": "PA_CL_UCP_0_X"
5107 "map": {"at": 165348, "to": "mm"},
5108 "name": "PA_CL_UCP_2_Z",
5109 "type_ref": "PA_CL_UCP_0_X"
5113 "map": {"at": 165352, "to": "mm"},
5114 "name": "PA_CL_UCP_2_W",
5115 "type_ref": "PA_CL_UCP_0_X"
5119 "map": {"at": 165356, "to": "mm"},
5120 "name": "PA_CL_UCP_3_X",
5121 "type_ref": "PA_CL_UCP_0_X"
5125 "map": {"at": 165360, "to": "mm"},
5126 "name": "PA_CL_UCP_3_Y",
5127 "type_ref": "PA_CL_UCP_0_X"
5131 "map": {"at": 165364, "to": "mm"},
5132 "name": "PA_CL_UCP_3_Z",
5133 "type_ref": "PA_CL_UCP_0_X"
5137 "map": {"at": 165368, "to": "mm"},
5138 "name": "PA_CL_UCP_3_W",
5139 "type_ref": "PA_CL_UCP_0_X"
5143 "map": {"at": 165372, "to": "mm"},
5144 "name": "PA_CL_UCP_4_X",
5145 "type_ref": "PA_CL_UCP_0_X"
5149 "map": {"at": 165376, "to": "mm"},
5150 "name": "PA_CL_UCP_4_Y",
5151 "type_ref": "PA_CL_UCP_0_X"
5155 "map": {"at": 165380, "to": "mm"},
5156 "name": "PA_CL_UCP_4_Z",
5157 "type_ref": "PA_CL_UCP_0_X"
5161 "map": {"at": 165384, "to": "mm"},
5162 "name": "PA_CL_UCP_4_W",
5163 "type_ref": "PA_CL_UCP_0_X"
5167 "map": {"at": 165388, "to": "mm"},
5168 "name": "PA_CL_UCP_5_X",
5169 "type_ref": "PA_CL_UCP_0_X"
5173 "map": {"at": 165392, "to": "mm"},
5174 "name": "PA_CL_UCP_5_Y",
5175 "type_ref": "PA_CL_UCP_0_X"
5179 "map": {"at": 165396, "to": "mm"},
5180 "name": "PA_CL_UCP_5_Z",
5181 "type_ref": "PA_CL_UCP_0_X"
5185 "map": {"at": 165400, "to": "mm"},
5186 "name": "PA_CL_UCP_5_W",
5187 "type_ref": "PA_CL_UCP_0_X"
5191 "map": {"at": 165404, "to": "mm"},
5192 "name": "PA_CL_PROG_NEAR_CLIP_Z",
5193 "type_ref": "PA_CL_UCP_0_X"
5197 "map": {"at": 165444, "to": "mm"},
5198 "name": "SPI_PS_INPUT_CNTL_0",
5199 "type_ref": "SPI_PS_INPUT_CNTL_0"
5203 "map": {"at": 165448, "to": "mm"},
5204 "name": "SPI_PS_INPUT_CNTL_1",
5205 "type_ref": "SPI_PS_INPUT_CNTL_0"
5209 "map": {"at": 165452, "to": "mm"},
5210 "name": "SPI_PS_INPUT_CNTL_2",
5211 "type_ref": "SPI_PS_INPUT_CNTL_0"
5215 "map": {"at": 165456, "to": "mm"},
5216 "name": "SPI_PS_INPUT_CNTL_3",
5217 "type_ref": "SPI_PS_INPUT_CNTL_0"
5221 "map": {"at": 165460, "to": "mm"},
5222 "name": "SPI_PS_INPUT_CNTL_4",
5223 "type_ref": "SPI_PS_INPUT_CNTL_0"
5227 "map": {"at": 165464, "to": "mm"},
5228 "name": "SPI_PS_INPUT_CNTL_5",
5229 "type_ref": "SPI_PS_INPUT_CNTL_0"
5233 "map": {"at": 165468, "to": "mm"},
5234 "name": "SPI_PS_INPUT_CNTL_6",
5235 "type_ref": "SPI_PS_INPUT_CNTL_0"
5239 "map": {"at": 165472, "to": "mm"},
5240 "name": "SPI_PS_INPUT_CNTL_7",
5241 "type_ref": "SPI_PS_INPUT_CNTL_0"
5245 "map": {"at": 165476, "to": "mm"},
5246 "name": "SPI_PS_INPUT_CNTL_8",
5247 "type_ref": "SPI_PS_INPUT_CNTL_0"
5251 "map": {"at": 165480, "to": "mm"},
5252 "name": "SPI_PS_INPUT_CNTL_9",
5253 "type_ref": "SPI_PS_INPUT_CNTL_0"
5257 "map": {"at": 165484, "to": "mm"},
5258 "name": "SPI_PS_INPUT_CNTL_10",
5259 "type_ref": "SPI_PS_INPUT_CNTL_0"
5263 "map": {"at": 165488, "to": "mm"},
5264 "name": "SPI_PS_INPUT_CNTL_11",
5265 "type_ref": "SPI_PS_INPUT_CNTL_0"
5269 "map": {"at": 165492, "to": "mm"},
5270 "name": "SPI_PS_INPUT_CNTL_12",
5271 "type_ref": "SPI_PS_INPUT_CNTL_0"
5275 "map": {"at": 165496, "to": "mm"},
5276 "name": "SPI_PS_INPUT_CNTL_13",
5277 "type_ref": "SPI_PS_INPUT_CNTL_0"
5281 "map": {"at": 165500, "to": "mm"},
5282 "name": "SPI_PS_INPUT_CNTL_14",
5283 "type_ref": "SPI_PS_INPUT_CNTL_0"
5287 "map": {"at": 165504, "to": "mm"},
5288 "name": "SPI_PS_INPUT_CNTL_15",
5289 "type_ref": "SPI_PS_INPUT_CNTL_0"
5293 "map": {"at": 165508, "to": "mm"},
5294 "name": "SPI_PS_INPUT_CNTL_16",
5295 "type_ref": "SPI_PS_INPUT_CNTL_0"
5299 "map": {"at": 165512, "to": "mm"},
5300 "name": "SPI_PS_INPUT_CNTL_17",
5301 "type_ref": "SPI_PS_INPUT_CNTL_0"
5305 "map": {"at": 165516, "to": "mm"},
5306 "name": "SPI_PS_INPUT_CNTL_18",
5307 "type_ref": "SPI_PS_INPUT_CNTL_0"
5311 "map": {"at": 165520, "to": "mm"},
5312 "name": "SPI_PS_INPUT_CNTL_19",
5313 "type_ref": "SPI_PS_INPUT_CNTL_0"
5317 "map": {"at": 165524, "to": "mm"},
5318 "name": "SPI_PS_INPUT_CNTL_20",
5319 "type_ref": "SPI_PS_INPUT_CNTL_20"
5323 "map": {"at": 165528, "to": "mm"},
5324 "name": "SPI_PS_INPUT_CNTL_21",
5325 "type_ref": "SPI_PS_INPUT_CNTL_20"
5329 "map": {"at": 165532, "to": "mm"},
5330 "name": "SPI_PS_INPUT_CNTL_22",
5331 "type_ref": "SPI_PS_INPUT_CNTL_20"
5335 "map": {"at": 165536, "to": "mm"},
5336 "name": "SPI_PS_INPUT_CNTL_23",
5337 "type_ref": "SPI_PS_INPUT_CNTL_20"
5341 "map": {"at": 165540, "to": "mm"},
5342 "name": "SPI_PS_INPUT_CNTL_24",
5343 "type_ref": "SPI_PS_INPUT_CNTL_20"
5347 "map": {"at": 165544, "to": "mm"},
5348 "name": "SPI_PS_INPUT_CNTL_25",
5349 "type_ref": "SPI_PS_INPUT_CNTL_20"
5353 "map": {"at": 165548, "to": "mm"},
5354 "name": "SPI_PS_INPUT_CNTL_26",
5355 "type_ref": "SPI_PS_INPUT_CNTL_20"
5359 "map": {"at": 165552, "to": "mm"},
5360 "name": "SPI_PS_INPUT_CNTL_27",
5361 "type_ref": "SPI_PS_INPUT_CNTL_20"
5365 "map": {"at": 165556, "to": "mm"},
5366 "name": "SPI_PS_INPUT_CNTL_28",
5367 "type_ref": "SPI_PS_INPUT_CNTL_20"
5371 "map": {"at": 165560, "to": "mm"},
5372 "name": "SPI_PS_INPUT_CNTL_29",
5373 "type_ref": "SPI_PS_INPUT_CNTL_20"
5377 "map": {"at": 165564, "to": "mm"},
5378 "name": "SPI_PS_INPUT_CNTL_30",
5379 "type_ref": "SPI_PS_INPUT_CNTL_20"
5383 "map": {"at": 165568, "to": "mm"},
5384 "name": "SPI_PS_INPUT_CNTL_31",
5385 "type_ref": "SPI_PS_INPUT_CNTL_20"
5389 "map": {"at": 165572, "to": "mm"},
5390 "name": "SPI_VS_OUT_CONFIG",
5391 "type_ref": "SPI_VS_OUT_CONFIG"
5395 "map": {"at": 165580, "to": "mm"},
5396 "name": "SPI_PS_INPUT_ENA",
5397 "type_ref": "SPI_PS_INPUT_ENA"
5401 "map": {"at": 165584, "to": "mm"},
5402 "name": "SPI_PS_INPUT_ADDR",
5403 "type_ref": "SPI_PS_INPUT_ENA"
5407 "map": {"at": 165588, "to": "mm"},
5408 "name": "SPI_INTERP_CONTROL_0",
5409 "type_ref": "SPI_INTERP_CONTROL_0"
5413 "map": {"at": 165592, "to": "mm"},
5414 "name": "SPI_PS_IN_CONTROL",
5415 "type_ref": "SPI_PS_IN_CONTROL"
5419 "map": {"at": 165600, "to": "mm"},
5420 "name": "SPI_BARYC_CNTL",
5421 "type_ref": "SPI_BARYC_CNTL"
5425 "map": {"at": 165608, "to": "mm"},
5426 "name": "SPI_TMPRING_SIZE",
5427 "type_ref": "COMPUTE_TMPRING_SIZE"
5431 "map": {"at": 165640, "to": "mm"},
5432 "name": "SPI_SHADER_IDX_FORMAT",
5433 "type_ref": "SPI_SHADER_IDX_FORMAT"
5437 "map": {"at": 165644, "to": "mm"},
5438 "name": "SPI_SHADER_POS_FORMAT",
5439 "type_ref": "SPI_SHADER_POS_FORMAT"
5443 "map": {"at": 165648, "to": "mm"},
5444 "name": "SPI_SHADER_Z_FORMAT",
5445 "type_ref": "SPI_SHADER_Z_FORMAT"
5449 "map": {"at": 165652, "to": "mm"},
5450 "name": "SPI_SHADER_COL_FORMAT",
5451 "type_ref": "SPI_SHADER_COL_FORMAT"
5455 "map": {"at": 165716, "to": "mm"},
5456 "name": "SX_PS_DOWNCONVERT",
5457 "type_ref": "SX_PS_DOWNCONVERT"
5461 "map": {"at": 165720, "to": "mm"},
5462 "name": "SX_BLEND_OPT_EPSILON",
5463 "type_ref": "SX_BLEND_OPT_EPSILON"
5467 "map": {"at": 165724, "to": "mm"},
5468 "name": "SX_BLEND_OPT_CONTROL",
5469 "type_ref": "SX_BLEND_OPT_CONTROL"
5473 "map": {"at": 165728, "to": "mm"},
5474 "name": "SX_MRT0_BLEND_OPT",
5475 "type_ref": "SX_MRT0_BLEND_OPT"
5479 "map": {"at": 165732, "to": "mm"},
5480 "name": "SX_MRT1_BLEND_OPT",
5481 "type_ref": "SX_MRT0_BLEND_OPT"
5485 "map": {"at": 165736, "to": "mm"},
5486 "name": "SX_MRT2_BLEND_OPT",
5487 "type_ref": "SX_MRT0_BLEND_OPT"
5491 "map": {"at": 165740, "to": "mm"},
5492 "name": "SX_MRT3_BLEND_OPT",
5493 "type_ref": "SX_MRT0_BLEND_OPT"
5497 "map": {"at": 165744, "to": "mm"},
5498 "name": "SX_MRT4_BLEND_OPT",
5499 "type_ref": "SX_MRT0_BLEND_OPT"
5503 "map": {"at": 165748, "to": "mm"},
5504 "name": "SX_MRT5_BLEND_OPT",
5505 "type_ref": "SX_MRT0_BLEND_OPT"
5509 "map": {"at": 165752, "to": "mm"},
5510 "name": "SX_MRT6_BLEND_OPT",
5511 "type_ref": "SX_MRT0_BLEND_OPT"
5515 "map": {"at": 165756, "to": "mm"},
5516 "name": "SX_MRT7_BLEND_OPT",
5517 "type_ref": "SX_MRT0_BLEND_OPT"
5521 "map": {"at": 165760, "to": "mm"},
5522 "name": "CB_BLEND0_CONTROL",
5523 "type_ref": "CB_BLEND0_CONTROL"
5527 "map": {"at": 165764, "to": "mm"},
5528 "name": "CB_BLEND1_CONTROL",
5529 "type_ref": "CB_BLEND0_CONTROL"
5533 "map": {"at": 165768, "to": "mm"},
5534 "name": "CB_BLEND2_CONTROL",
5535 "type_ref": "CB_BLEND0_CONTROL"
5539 "map": {"at": 165772, "to": "mm"},
5540 "name": "CB_BLEND3_CONTROL",
5541 "type_ref": "CB_BLEND0_CONTROL"
5545 "map": {"at": 165776, "to": "mm"},
5546 "name": "CB_BLEND4_CONTROL",
5547 "type_ref": "CB_BLEND0_CONTROL"
5551 "map": {"at": 165780, "to": "mm"},
5552 "name": "CB_BLEND5_CONTROL",
5553 "type_ref": "CB_BLEND0_CONTROL"
5557 "map": {"at": 165784, "to": "mm"},
5558 "name": "CB_BLEND6_CONTROL",
5559 "type_ref": "CB_BLEND0_CONTROL"
5563 "map": {"at": 165788, "to": "mm"},
5564 "name": "CB_BLEND7_CONTROL",
5565 "type_ref": "CB_BLEND0_CONTROL"
5569 "map": {"at": 165836, "to": "mm"},
5570 "name": "CS_COPY_STATE",
5571 "type_ref": "CS_COPY_STATE"
5575 "map": {"at": 165840, "to": "mm"},
5576 "name": "GFX_COPY_STATE",
5577 "type_ref": "CS_COPY_STATE"
5581 "map": {"at": 165844, "to": "mm"},
5582 "name": "PA_CL_POINT_X_RAD",
5583 "type_ref": "PA_CL_UCP_0_X"
5587 "map": {"at": 165848, "to": "mm"},
5588 "name": "PA_CL_POINT_Y_RAD",
5589 "type_ref": "PA_CL_UCP_0_X"
5593 "map": {"at": 165852, "to": "mm"},
5594 "name": "PA_CL_POINT_SIZE",
5595 "type_ref": "PA_CL_UCP_0_X"
5599 "map": {"at": 165856, "to": "mm"},
5600 "name": "PA_CL_POINT_CULL_RAD",
5601 "type_ref": "PA_CL_UCP_0_X"
5605 "map": {"at": 165860, "to": "mm"},
5606 "name": "VGT_DMA_BASE_HI",
5607 "type_ref": "VGT_DMA_BASE_HI"
5611 "map": {"at": 165864, "to": "mm"},
5612 "name": "VGT_DMA_BASE",
5613 "type_ref": "VGT_DMA_BASE"
5617 "map": {"at": 165872, "to": "mm"},
5618 "name": "VGT_DRAW_INITIATOR",
5619 "type_ref": "VGT_DRAW_INITIATOR"
5623 "map": {"at": 165876, "to": "mm"},
5624 "name": "VGT_IMMED_DATA",
5625 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
5629 "map": {"at": 165880, "to": "mm"},
5630 "name": "VGT_EVENT_ADDRESS_REG",
5631 "type_ref": "VGT_EVENT_ADDRESS_REG"
5635 "map": {"at": 165884, "to": "mm"},
5636 "name": "GE_MAX_OUTPUT_PER_SUBGROUP",
5637 "type_ref": "GE_MAX_OUTPUT_PER_SUBGROUP"
5641 "map": {"at": 165888, "to": "mm"},
5642 "name": "DB_DEPTH_CONTROL",
5643 "type_ref": "DB_DEPTH_CONTROL"
5647 "map": {"at": 165892, "to": "mm"},
5649 "type_ref": "DB_EQAA"
5653 "map": {"at": 165896, "to": "mm"},
5654 "name": "CB_COLOR_CONTROL",
5655 "type_ref": "CB_COLOR_CONTROL"
5659 "map": {"at": 165900, "to": "mm"},
5660 "name": "DB_SHADER_CONTROL",
5661 "type_ref": "DB_SHADER_CONTROL"
5665 "map": {"at": 165904, "to": "mm"},
5666 "name": "PA_CL_CLIP_CNTL",
5667 "type_ref": "PA_CL_CLIP_CNTL"
5671 "map": {"at": 165908, "to": "mm"},
5672 "name": "PA_SU_SC_MODE_CNTL",
5673 "type_ref": "PA_SU_SC_MODE_CNTL"
5677 "map": {"at": 165912, "to": "mm"},
5678 "name": "PA_CL_VTE_CNTL",
5679 "type_ref": "PA_CL_VTE_CNTL"
5683 "map": {"at": 165916, "to": "mm"},
5684 "name": "PA_CL_VS_OUT_CNTL",
5685 "type_ref": "PA_CL_VS_OUT_CNTL"
5689 "map": {"at": 165920, "to": "mm"},
5690 "name": "PA_CL_NANINF_CNTL",
5691 "type_ref": "PA_CL_NANINF_CNTL"
5695 "map": {"at": 165924, "to": "mm"},
5696 "name": "PA_SU_LINE_STIPPLE_CNTL",
5697 "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
5701 "map": {"at": 165928, "to": "mm"},
5702 "name": "PA_SU_LINE_STIPPLE_SCALE",
5703 "type_ref": "PA_SU_LINE_STIPPLE_SCALE"
5707 "map": {"at": 165932, "to": "mm"},
5708 "name": "PA_SU_PRIM_FILTER_CNTL",
5709 "type_ref": "PA_SU_PRIM_FILTER_CNTL"
5713 "map": {"at": 165936, "to": "mm"},
5714 "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
5715 "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL"
5719 "map": {"at": 165940, "to": "mm"},
5720 "name": "PA_CL_OBJPRIM_ID_CNTL",
5721 "type_ref": "PA_CL_OBJPRIM_ID_CNTL"
5725 "map": {"at": 165944, "to": "mm"},
5726 "name": "PA_CL_NGG_CNTL",
5727 "type_ref": "PA_CL_NGG_CNTL"
5731 "map": {"at": 165948, "to": "mm"},
5732 "name": "PA_SU_OVER_RASTERIZATION_CNTL",
5733 "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL"
5737 "map": {"at": 165952, "to": "mm"},
5738 "name": "PA_STEREO_CNTL",
5739 "type_ref": "PA_STEREO_CNTL"
5743 "map": {"at": 165956, "to": "mm"},
5744 "name": "PA_STATE_STEREO_X",
5745 "type_ref": "PA_STATE_STEREO_X"
5749 "map": {"at": 166400, "to": "mm"},
5750 "name": "PA_SU_POINT_SIZE",
5751 "type_ref": "PA_SU_POINT_SIZE"
5755 "map": {"at": 166404, "to": "mm"},
5756 "name": "PA_SU_POINT_MINMAX",
5757 "type_ref": "PA_SU_POINT_MINMAX"
5761 "map": {"at": 166408, "to": "mm"},
5762 "name": "PA_SU_LINE_CNTL",
5763 "type_ref": "PA_SU_LINE_CNTL"
5767 "map": {"at": 166412, "to": "mm"},
5768 "name": "PA_SC_LINE_STIPPLE",
5769 "type_ref": "PA_SC_LINE_STIPPLE"
5773 "map": {"at": 166416, "to": "mm"},
5774 "name": "VGT_OUTPUT_PATH_CNTL",
5775 "type_ref": "VGT_OUTPUT_PATH_CNTL"
5779 "map": {"at": 166420, "to": "mm"},
5780 "name": "VGT_HOS_CNTL",
5781 "type_ref": "VGT_HOS_CNTL"
5785 "map": {"at": 166424, "to": "mm"},
5786 "name": "VGT_HOS_MAX_TESS_LEVEL",
5787 "type_ref": "VGT_HOS_MAX_TESS_LEVEL"
5791 "map": {"at": 166428, "to": "mm"},
5792 "name": "VGT_HOS_MIN_TESS_LEVEL",
5793 "type_ref": "VGT_HOS_MIN_TESS_LEVEL"
5797 "map": {"at": 166432, "to": "mm"},
5798 "name": "VGT_HOS_REUSE_DEPTH",
5799 "type_ref": "VGT_HOS_REUSE_DEPTH"
5803 "map": {"at": 166436, "to": "mm"},
5804 "name": "VGT_GROUP_PRIM_TYPE",
5805 "type_ref": "VGT_GROUP_PRIM_TYPE"
5809 "map": {"at": 166440, "to": "mm"},
5810 "name": "VGT_GROUP_FIRST_DECR",
5811 "type_ref": "VGT_GROUP_FIRST_DECR"
5815 "map": {"at": 166444, "to": "mm"},
5816 "name": "VGT_GROUP_DECR",
5817 "type_ref": "VGT_GROUP_DECR"
5821 "map": {"at": 166448, "to": "mm"},
5822 "name": "VGT_GROUP_VECT_0_CNTL",
5823 "type_ref": "VGT_GROUP_VECT_0_CNTL"
5827 "map": {"at": 166452, "to": "mm"},
5828 "name": "VGT_GROUP_VECT_1_CNTL",
5829 "type_ref": "VGT_GROUP_VECT_0_CNTL"
5833 "map": {"at": 166456, "to": "mm"},
5834 "name": "VGT_GROUP_VECT_0_FMT_CNTL",
5835 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5839 "map": {"at": 166460, "to": "mm"},
5840 "name": "VGT_GROUP_VECT_1_FMT_CNTL",
5841 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5845 "map": {"at": 166464, "to": "mm"},
5846 "name": "VGT_GS_MODE",
5847 "type_ref": "VGT_GS_MODE"
5851 "map": {"at": 166468, "to": "mm"},
5852 "name": "VGT_GS_ONCHIP_CNTL",
5853 "type_ref": "VGT_GS_ONCHIP_CNTL"
5857 "map": {"at": 166472, "to": "mm"},
5858 "name": "PA_SC_MODE_CNTL_0",
5859 "type_ref": "PA_SC_MODE_CNTL_0"
5863 "map": {"at": 166476, "to": "mm"},
5864 "name": "PA_SC_MODE_CNTL_1",
5865 "type_ref": "PA_SC_MODE_CNTL_1"
5869 "map": {"at": 166480, "to": "mm"},
5870 "name": "VGT_ENHANCE",
5871 "type_ref": "VGT_ENHANCE"
5875 "map": {"at": 166484, "to": "mm"},
5876 "name": "VGT_GS_PER_ES",
5877 "type_ref": "VGT_GS_PER_ES"
5881 "map": {"at": 166488, "to": "mm"},
5882 "name": "VGT_ES_PER_GS",
5883 "type_ref": "VGT_ES_PER_GS"
5887 "map": {"at": 166492, "to": "mm"},
5888 "name": "VGT_GS_PER_VS",
5889 "type_ref": "VGT_GS_PER_VS"
5893 "map": {"at": 166496, "to": "mm"},
5894 "name": "VGT_GSVS_RING_OFFSET_1",
5895 "type_ref": "VGT_GSVS_RING_OFFSET_1"
5899 "map": {"at": 166500, "to": "mm"},
5900 "name": "VGT_GSVS_RING_OFFSET_2",
5901 "type_ref": "VGT_GSVS_RING_OFFSET_1"
5905 "map": {"at": 166504, "to": "mm"},
5906 "name": "VGT_GSVS_RING_OFFSET_3",
5907 "type_ref": "VGT_GSVS_RING_OFFSET_1"
5911 "map": {"at": 166508, "to": "mm"},
5912 "name": "VGT_GS_OUT_PRIM_TYPE",
5913 "type_ref": "VGT_GS_OUT_PRIM_TYPE"
5917 "map": {"at": 166512, "to": "mm"},
5918 "name": "IA_ENHANCE",
5919 "type_ref": "VGT_ENHANCE"
5923 "map": {"at": 166516, "to": "mm"},
5924 "name": "VGT_DMA_SIZE",
5925 "type_ref": "VGT_DMA_SIZE"
5929 "map": {"at": 166520, "to": "mm"},
5930 "name": "VGT_DMA_MAX_SIZE",
5931 "type_ref": "VGT_DMA_MAX_SIZE"
5935 "map": {"at": 166524, "to": "mm"},
5936 "name": "VGT_DMA_INDEX_TYPE",
5937 "type_ref": "VGT_DMA_INDEX_TYPE"
5941 "map": {"at": 166528, "to": "mm"},
5942 "name": "WD_ENHANCE",
5943 "type_ref": "VGT_ENHANCE"
5947 "map": {"at": 166532, "to": "mm"},
5948 "name": "VGT_PRIMITIVEID_EN",
5949 "type_ref": "VGT_PRIMITIVEID_EN"
5953 "map": {"at": 166536, "to": "mm"},
5954 "name": "VGT_DMA_NUM_INSTANCES",
5955 "type_ref": "VGT_DMA_NUM_INSTANCES"
5959 "map": {"at": 166540, "to": "mm"},
5960 "name": "VGT_PRIMITIVEID_RESET",
5961 "type_ref": "VGT_PRIMITIVEID_RESET"
5965 "map": {"at": 166544, "to": "mm"},
5966 "name": "VGT_EVENT_INITIATOR",
5967 "type_ref": "VGT_EVENT_INITIATOR"
5971 "map": {"at": 166548, "to": "mm"},
5972 "name": "VGT_MULTI_PRIM_IB_RESET_EN",
5973 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
5977 "map": {"at": 166552, "to": "mm"},
5978 "name": "VGT_DRAW_PAYLOAD_CNTL",
5979 "type_ref": "VGT_DRAW_PAYLOAD_CNTL"
5983 "map": {"at": 166560, "to": "mm"},
5984 "name": "VGT_INSTANCE_STEP_RATE_0",
5985 "type_ref": "VGT_INSTANCE_STEP_RATE_0"
5989 "map": {"at": 166564, "to": "mm"},
5990 "name": "VGT_INSTANCE_STEP_RATE_1",
5991 "type_ref": "VGT_INSTANCE_STEP_RATE_0"
5995 "map": {"at": 166568, "to": "mm"},
5996 "name": "IA_MULTI_VGT_PARAM",
5997 "type_ref": "IA_MULTI_VGT_PARAM"
6001 "map": {"at": 166572, "to": "mm"},
6002 "name": "VGT_ESGS_RING_ITEMSIZE",
6003 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6007 "map": {"at": 166576, "to": "mm"},
6008 "name": "VGT_GSVS_RING_ITEMSIZE",
6009 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6013 "map": {"at": 166580, "to": "mm"},
6014 "name": "VGT_REUSE_OFF",
6015 "type_ref": "VGT_REUSE_OFF"
6019 "map": {"at": 166584, "to": "mm"},
6020 "name": "VGT_VTX_CNT_EN",
6021 "type_ref": "VGT_VTX_CNT_EN"
6025 "map": {"at": 166588, "to": "mm"},
6026 "name": "DB_HTILE_SURFACE",
6027 "type_ref": "DB_HTILE_SURFACE"
6031 "map": {"at": 166592, "to": "mm"},
6032 "name": "DB_SRESULTS_COMPARE_STATE0",
6033 "type_ref": "DB_SRESULTS_COMPARE_STATE0"
6037 "map": {"at": 166596, "to": "mm"},
6038 "name": "DB_SRESULTS_COMPARE_STATE1",
6039 "type_ref": "DB_SRESULTS_COMPARE_STATE1"
6043 "map": {"at": 166600, "to": "mm"},
6044 "name": "DB_PRELOAD_CONTROL",
6045 "type_ref": "DB_PRELOAD_CONTROL"
6049 "map": {"at": 166608, "to": "mm"},
6050 "name": "VGT_STRMOUT_BUFFER_SIZE_0",
6051 "type_ref": "COMPUTE_DIM_X"
6055 "map": {"at": 166612, "to": "mm"},
6056 "name": "VGT_STRMOUT_VTX_STRIDE_0",
6057 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
6061 "map": {"at": 166620, "to": "mm"},
6062 "name": "VGT_STRMOUT_BUFFER_OFFSET_0",
6063 "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6067 "map": {"at": 166624, "to": "mm"},
6068 "name": "VGT_STRMOUT_BUFFER_SIZE_1",
6069 "type_ref": "COMPUTE_DIM_X"
6073 "map": {"at": 166628, "to": "mm"},
6074 "name": "VGT_STRMOUT_VTX_STRIDE_1",
6075 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
6079 "map": {"at": 166636, "to": "mm"},
6080 "name": "VGT_STRMOUT_BUFFER_OFFSET_1",
6081 "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6085 "map": {"at": 166640, "to": "mm"},
6086 "name": "VGT_STRMOUT_BUFFER_SIZE_2",
6087 "type_ref": "COMPUTE_DIM_X"
6091 "map": {"at": 166644, "to": "mm"},
6092 "name": "VGT_STRMOUT_VTX_STRIDE_2",
6093 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
6097 "map": {"at": 166652, "to": "mm"},
6098 "name": "VGT_STRMOUT_BUFFER_OFFSET_2",
6099 "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6103 "map": {"at": 166656, "to": "mm"},
6104 "name": "VGT_STRMOUT_BUFFER_SIZE_3",
6105 "type_ref": "COMPUTE_DIM_X"
6109 "map": {"at": 166660, "to": "mm"},
6110 "name": "VGT_STRMOUT_VTX_STRIDE_3",
6111 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
6115 "map": {"at": 166668, "to": "mm"},
6116 "name": "VGT_STRMOUT_BUFFER_OFFSET_3",
6117 "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6121 "map": {"at": 166696, "to": "mm"},
6122 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET",
6123 "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6127 "map": {"at": 166700, "to": "mm"},
6128 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE",
6129 "type_ref": "COMPUTE_DIM_X"
6133 "map": {"at": 166704, "to": "mm"},
6134 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
6135 "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
6139 "map": {"at": 166712, "to": "mm"},
6140 "name": "VGT_GS_MAX_VERT_OUT",
6141 "type_ref": "VGT_GS_MAX_VERT_OUT"
6145 "map": {"at": 166732, "to": "mm"},
6146 "name": "GE_NGG_SUBGRP_CNTL",
6147 "type_ref": "GE_NGG_SUBGRP_CNTL"
6151 "map": {"at": 166736, "to": "mm"},
6152 "name": "VGT_TESS_DISTRIBUTION",
6153 "type_ref": "VGT_TESS_DISTRIBUTION"
6157 "map": {"at": 166740, "to": "mm"},
6158 "name": "VGT_SHADER_STAGES_EN",
6159 "type_ref": "VGT_SHADER_STAGES_EN"
6163 "map": {"at": 166744, "to": "mm"},
6164 "name": "VGT_LS_HS_CONFIG",
6165 "type_ref": "VGT_LS_HS_CONFIG"
6169 "map": {"at": 166748, "to": "mm"},
6170 "name": "VGT_GS_VERT_ITEMSIZE",
6171 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6175 "map": {"at": 166752, "to": "mm"},
6176 "name": "VGT_GS_VERT_ITEMSIZE_1",
6177 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6181 "map": {"at": 166756, "to": "mm"},
6182 "name": "VGT_GS_VERT_ITEMSIZE_2",
6183 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6187 "map": {"at": 166760, "to": "mm"},
6188 "name": "VGT_GS_VERT_ITEMSIZE_3",
6189 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6193 "map": {"at": 166764, "to": "mm"},
6194 "name": "VGT_TF_PARAM",
6195 "type_ref": "VGT_TF_PARAM"
6199 "map": {"at": 166768, "to": "mm"},
6200 "name": "DB_ALPHA_TO_MASK",
6201 "type_ref": "DB_ALPHA_TO_MASK"
6205 "map": {"at": 166772, "to": "mm"},
6206 "name": "VGT_DISPATCH_DRAW_INDEX",
6207 "type_ref": "VGT_DISPATCH_DRAW_INDEX"
6211 "map": {"at": 166776, "to": "mm"},
6212 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
6213 "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
6217 "map": {"at": 166780, "to": "mm"},
6218 "name": "PA_SU_POLY_OFFSET_CLAMP",
6219 "type_ref": "PA_SU_POLY_OFFSET_CLAMP"
6223 "map": {"at": 166784, "to": "mm"},
6224 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE",
6225 "type_ref": "PA_SU_POLY_OFFSET_FRONT_SCALE"
6229 "map": {"at": 166788, "to": "mm"},
6230 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET",
6231 "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6235 "map": {"at": 166792, "to": "mm"},
6236 "name": "PA_SU_POLY_OFFSET_BACK_SCALE",
6237 "type_ref": "PA_SU_POLY_OFFSET_FRONT_SCALE"
6241 "map": {"at": 166796, "to": "mm"},
6242 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET",
6243 "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6247 "map": {"at": 166800, "to": "mm"},
6248 "name": "VGT_GS_INSTANCE_CNT",
6249 "type_ref": "VGT_GS_INSTANCE_CNT"
6253 "map": {"at": 166804, "to": "mm"},
6254 "name": "VGT_STRMOUT_CONFIG",
6255 "type_ref": "VGT_STRMOUT_CONFIG"
6259 "map": {"at": 166808, "to": "mm"},
6260 "name": "VGT_STRMOUT_BUFFER_CONFIG",
6261 "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
6265 "map": {"at": 166812, "to": "mm"},
6266 "name": "VGT_DMA_EVENT_INITIATOR",
6267 "type_ref": "VGT_EVENT_INITIATOR"
6271 "map": {"at": 166868, "to": "mm"},
6272 "name": "PA_SC_CENTROID_PRIORITY_0",
6273 "type_ref": "PA_SC_CENTROID_PRIORITY_0"
6277 "map": {"at": 166872, "to": "mm"},
6278 "name": "PA_SC_CENTROID_PRIORITY_1",
6279 "type_ref": "PA_SC_CENTROID_PRIORITY_1"
6283 "map": {"at": 166876, "to": "mm"},
6284 "name": "PA_SC_LINE_CNTL",
6285 "type_ref": "PA_SC_LINE_CNTL"
6289 "map": {"at": 166880, "to": "mm"},
6290 "name": "PA_SC_AA_CONFIG",
6291 "type_ref": "PA_SC_AA_CONFIG"
6295 "map": {"at": 166884, "to": "mm"},
6296 "name": "PA_SU_VTX_CNTL",
6297 "type_ref": "PA_SU_VTX_CNTL"
6301 "map": {"at": 166888, "to": "mm"},
6302 "name": "PA_CL_GB_VERT_CLIP_ADJ",
6303 "type_ref": "PA_CL_UCP_0_X"
6307 "map": {"at": 166892, "to": "mm"},
6308 "name": "PA_CL_GB_VERT_DISC_ADJ",
6309 "type_ref": "PA_CL_UCP_0_X"
6313 "map": {"at": 166896, "to": "mm"},
6314 "name": "PA_CL_GB_HORZ_CLIP_ADJ",
6315 "type_ref": "PA_CL_UCP_0_X"
6319 "map": {"at": 166900, "to": "mm"},
6320 "name": "PA_CL_GB_HORZ_DISC_ADJ",
6321 "type_ref": "PA_CL_UCP_0_X"
6325 "map": {"at": 166904, "to": "mm"},
6326 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
6327 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
6331 "map": {"at": 166908, "to": "mm"},
6332 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
6333 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
6337 "map": {"at": 166912, "to": "mm"},
6338 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
6339 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
6343 "map": {"at": 166916, "to": "mm"},
6344 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
6345 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
6349 "map": {"at": 166920, "to": "mm"},
6350 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
6351 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
6355 "map": {"at": 166924, "to": "mm"},
6356 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
6357 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
6361 "map": {"at": 166928, "to": "mm"},
6362 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
6363 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
6367 "map": {"at": 166932, "to": "mm"},
6368 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
6369 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
6373 "map": {"at": 166936, "to": "mm"},
6374 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
6375 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
6379 "map": {"at": 166940, "to": "mm"},
6380 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
6381 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
6385 "map": {"at": 166944, "to": "mm"},
6386 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
6387 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
6391 "map": {"at": 166948, "to": "mm"},
6392 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
6393 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
6397 "map": {"at": 166952, "to": "mm"},
6398 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
6399 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
6403 "map": {"at": 166956, "to": "mm"},
6404 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
6405 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
6409 "map": {"at": 166960, "to": "mm"},
6410 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
6411 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
6415 "map": {"at": 166964, "to": "mm"},
6416 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
6417 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
6421 "map": {"at": 166968, "to": "mm"},
6422 "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
6423 "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
6427 "map": {"at": 166972, "to": "mm"},
6428 "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
6429 "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
6433 "map": {"at": 166976, "to": "mm"},
6434 "name": "PA_SC_SHADER_CONTROL",
6435 "type_ref": "PA_SC_SHADER_CONTROL"
6439 "map": {"at": 166980, "to": "mm"},
6440 "name": "PA_SC_BINNER_CNTL_0",
6441 "type_ref": "PA_SC_BINNER_CNTL_0"
6445 "map": {"at": 166984, "to": "mm"},
6446 "name": "PA_SC_BINNER_CNTL_1",
6447 "type_ref": "PA_SC_BINNER_CNTL_1"
6451 "map": {"at": 166988, "to": "mm"},
6452 "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
6453 "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
6457 "map": {"at": 166992, "to": "mm"},
6458 "name": "PA_SC_NGG_MODE_CNTL",
6459 "type_ref": "PA_SC_NGG_MODE_CNTL"
6463 "map": {"at": 167000, "to": "mm"},
6464 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
6465 "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
6469 "map": {"at": 167004, "to": "mm"},
6470 "name": "VGT_OUT_DEALLOC_CNTL",
6471 "type_ref": "VGT_OUT_DEALLOC_CNTL"
6475 "map": {"at": 167008, "to": "mm"},
6476 "name": "CB_COLOR0_BASE",
6477 "type_ref": "DB_HTILE_DATA_BASE"
6481 "map": {"at": 167012, "to": "mm"},
6482 "name": "CB_COLOR0_PITCH",
6483 "type_ref": "CB_COLOR0_PITCH"
6487 "map": {"at": 167016, "to": "mm"},
6488 "name": "CB_COLOR0_SLICE",
6489 "type_ref": "CB_COLOR0_SLICE"
6493 "map": {"at": 167020, "to": "mm"},
6494 "name": "CB_COLOR0_VIEW",
6495 "type_ref": "CB_COLOR0_VIEW"
6499 "map": {"at": 167024, "to": "mm"},
6500 "name": "CB_COLOR0_INFO",
6501 "type_ref": "CB_COLOR0_INFO"
6505 "map": {"at": 167028, "to": "mm"},
6506 "name": "CB_COLOR0_ATTRIB",
6507 "type_ref": "CB_COLOR0_ATTRIB"
6511 "map": {"at": 167032, "to": "mm"},
6512 "name": "CB_COLOR0_DCC_CONTROL",
6513 "type_ref": "CB_COLOR0_DCC_CONTROL"
6517 "map": {"at": 167036, "to": "mm"},
6518 "name": "CB_COLOR0_CMASK",
6519 "type_ref": "DB_HTILE_DATA_BASE"
6523 "map": {"at": 167040, "to": "mm"},
6524 "name": "CB_COLOR0_CMASK_SLICE",
6525 "type_ref": "CB_COLOR0_CMASK_SLICE"
6529 "map": {"at": 167044, "to": "mm"},
6530 "name": "CB_COLOR0_FMASK",
6531 "type_ref": "DB_HTILE_DATA_BASE"
6535 "map": {"at": 167048, "to": "mm"},
6536 "name": "CB_COLOR0_FMASK_SLICE",
6537 "type_ref": "CB_COLOR0_SLICE"
6541 "map": {"at": 167052, "to": "mm"},
6542 "name": "CB_COLOR0_CLEAR_WORD0",
6543 "type_ref": "CB_COLOR0_CLEAR_WORD0"
6547 "map": {"at": 167056, "to": "mm"},
6548 "name": "CB_COLOR0_CLEAR_WORD1",
6549 "type_ref": "CB_COLOR0_CLEAR_WORD1"
6553 "map": {"at": 167060, "to": "mm"},
6554 "name": "CB_COLOR0_DCC_BASE",
6555 "type_ref": "DB_HTILE_DATA_BASE"
6559 "map": {"at": 167068, "to": "mm"},
6560 "name": "CB_COLOR1_BASE",
6561 "type_ref": "DB_HTILE_DATA_BASE"
6565 "map": {"at": 167072, "to": "mm"},
6566 "name": "CB_COLOR1_PITCH",
6567 "type_ref": "CB_COLOR0_PITCH"
6571 "map": {"at": 167076, "to": "mm"},
6572 "name": "CB_COLOR1_SLICE",
6573 "type_ref": "CB_COLOR0_SLICE"
6577 "map": {"at": 167080, "to": "mm"},
6578 "name": "CB_COLOR1_VIEW",
6579 "type_ref": "CB_COLOR0_VIEW"
6583 "map": {"at": 167084, "to": "mm"},
6584 "name": "CB_COLOR1_INFO",
6585 "type_ref": "CB_COLOR0_INFO"
6589 "map": {"at": 167088, "to": "mm"},
6590 "name": "CB_COLOR1_ATTRIB",
6591 "type_ref": "CB_COLOR0_ATTRIB"
6595 "map": {"at": 167092, "to": "mm"},
6596 "name": "CB_COLOR1_DCC_CONTROL",
6597 "type_ref": "CB_COLOR0_DCC_CONTROL"
6601 "map": {"at": 167096, "to": "mm"},
6602 "name": "CB_COLOR1_CMASK",
6603 "type_ref": "DB_HTILE_DATA_BASE"
6607 "map": {"at": 167100, "to": "mm"},
6608 "name": "CB_COLOR1_CMASK_SLICE",
6609 "type_ref": "CB_COLOR0_CMASK_SLICE"
6613 "map": {"at": 167104, "to": "mm"},
6614 "name": "CB_COLOR1_FMASK",
6615 "type_ref": "DB_HTILE_DATA_BASE"
6619 "map": {"at": 167108, "to": "mm"},
6620 "name": "CB_COLOR1_FMASK_SLICE",
6621 "type_ref": "CB_COLOR0_SLICE"
6625 "map": {"at": 167112, "to": "mm"},
6626 "name": "CB_COLOR1_CLEAR_WORD0",
6627 "type_ref": "CB_COLOR0_CLEAR_WORD0"
6631 "map": {"at": 167116, "to": "mm"},
6632 "name": "CB_COLOR1_CLEAR_WORD1",
6633 "type_ref": "CB_COLOR0_CLEAR_WORD1"
6637 "map": {"at": 167120, "to": "mm"},
6638 "name": "CB_COLOR1_DCC_BASE",
6639 "type_ref": "DB_HTILE_DATA_BASE"
6643 "map": {"at": 167128, "to": "mm"},
6644 "name": "CB_COLOR2_BASE",
6645 "type_ref": "DB_HTILE_DATA_BASE"
6649 "map": {"at": 167132, "to": "mm"},
6650 "name": "CB_COLOR2_PITCH",
6651 "type_ref": "CB_COLOR0_PITCH"
6655 "map": {"at": 167136, "to": "mm"},
6656 "name": "CB_COLOR2_SLICE",
6657 "type_ref": "CB_COLOR0_SLICE"
6661 "map": {"at": 167140, "to": "mm"},
6662 "name": "CB_COLOR2_VIEW",
6663 "type_ref": "CB_COLOR0_VIEW"
6667 "map": {"at": 167144, "to": "mm"},
6668 "name": "CB_COLOR2_INFO",
6669 "type_ref": "CB_COLOR0_INFO"
6673 "map": {"at": 167148, "to": "mm"},
6674 "name": "CB_COLOR2_ATTRIB",
6675 "type_ref": "CB_COLOR0_ATTRIB"
6679 "map": {"at": 167152, "to": "mm"},
6680 "name": "CB_COLOR2_DCC_CONTROL",
6681 "type_ref": "CB_COLOR0_DCC_CONTROL"
6685 "map": {"at": 167156, "to": "mm"},
6686 "name": "CB_COLOR2_CMASK",
6687 "type_ref": "DB_HTILE_DATA_BASE"
6691 "map": {"at": 167160, "to": "mm"},
6692 "name": "CB_COLOR2_CMASK_SLICE",
6693 "type_ref": "CB_COLOR0_CMASK_SLICE"
6697 "map": {"at": 167164, "to": "mm"},
6698 "name": "CB_COLOR2_FMASK",
6699 "type_ref": "DB_HTILE_DATA_BASE"
6703 "map": {"at": 167168, "to": "mm"},
6704 "name": "CB_COLOR2_FMASK_SLICE",
6705 "type_ref": "CB_COLOR0_SLICE"
6709 "map": {"at": 167172, "to": "mm"},
6710 "name": "CB_COLOR2_CLEAR_WORD0",
6711 "type_ref": "CB_COLOR0_CLEAR_WORD0"
6715 "map": {"at": 167176, "to": "mm"},
6716 "name": "CB_COLOR2_CLEAR_WORD1",
6717 "type_ref": "CB_COLOR0_CLEAR_WORD1"
6721 "map": {"at": 167180, "to": "mm"},
6722 "name": "CB_COLOR2_DCC_BASE",
6723 "type_ref": "DB_HTILE_DATA_BASE"
6727 "map": {"at": 167188, "to": "mm"},
6728 "name": "CB_COLOR3_BASE",
6729 "type_ref": "DB_HTILE_DATA_BASE"
6733 "map": {"at": 167192, "to": "mm"},
6734 "name": "CB_COLOR3_PITCH",
6735 "type_ref": "CB_COLOR0_PITCH"
6739 "map": {"at": 167196, "to": "mm"},
6740 "name": "CB_COLOR3_SLICE",
6741 "type_ref": "CB_COLOR0_SLICE"
6745 "map": {"at": 167200, "to": "mm"},
6746 "name": "CB_COLOR3_VIEW",
6747 "type_ref": "CB_COLOR0_VIEW"
6751 "map": {"at": 167204, "to": "mm"},
6752 "name": "CB_COLOR3_INFO",
6753 "type_ref": "CB_COLOR0_INFO"
6757 "map": {"at": 167208, "to": "mm"},
6758 "name": "CB_COLOR3_ATTRIB",
6759 "type_ref": "CB_COLOR0_ATTRIB"
6763 "map": {"at": 167212, "to": "mm"},
6764 "name": "CB_COLOR3_DCC_CONTROL",
6765 "type_ref": "CB_COLOR0_DCC_CONTROL"
6769 "map": {"at": 167216, "to": "mm"},
6770 "name": "CB_COLOR3_CMASK",
6771 "type_ref": "DB_HTILE_DATA_BASE"
6775 "map": {"at": 167220, "to": "mm"},
6776 "name": "CB_COLOR3_CMASK_SLICE",
6777 "type_ref": "CB_COLOR0_CMASK_SLICE"
6781 "map": {"at": 167224, "to": "mm"},
6782 "name": "CB_COLOR3_FMASK",
6783 "type_ref": "DB_HTILE_DATA_BASE"
6787 "map": {"at": 167228, "to": "mm"},
6788 "name": "CB_COLOR3_FMASK_SLICE",
6789 "type_ref": "CB_COLOR0_SLICE"
6793 "map": {"at": 167232, "to": "mm"},
6794 "name": "CB_COLOR3_CLEAR_WORD0",
6795 "type_ref": "CB_COLOR0_CLEAR_WORD0"
6799 "map": {"at": 167236, "to": "mm"},
6800 "name": "CB_COLOR3_CLEAR_WORD1",
6801 "type_ref": "CB_COLOR0_CLEAR_WORD1"
6805 "map": {"at": 167240, "to": "mm"},
6806 "name": "CB_COLOR3_DCC_BASE",
6807 "type_ref": "DB_HTILE_DATA_BASE"
6811 "map": {"at": 167248, "to": "mm"},
6812 "name": "CB_COLOR4_BASE",
6813 "type_ref": "DB_HTILE_DATA_BASE"
6817 "map": {"at": 167252, "to": "mm"},
6818 "name": "CB_COLOR4_PITCH",
6819 "type_ref": "CB_COLOR0_PITCH"
6823 "map": {"at": 167256, "to": "mm"},
6824 "name": "CB_COLOR4_SLICE",
6825 "type_ref": "CB_COLOR0_SLICE"
6829 "map": {"at": 167260, "to": "mm"},
6830 "name": "CB_COLOR4_VIEW",
6831 "type_ref": "CB_COLOR0_VIEW"
6835 "map": {"at": 167264, "to": "mm"},
6836 "name": "CB_COLOR4_INFO",
6837 "type_ref": "CB_COLOR0_INFO"
6841 "map": {"at": 167268, "to": "mm"},
6842 "name": "CB_COLOR4_ATTRIB",
6843 "type_ref": "CB_COLOR0_ATTRIB"
6847 "map": {"at": 167272, "to": "mm"},
6848 "name": "CB_COLOR4_DCC_CONTROL",
6849 "type_ref": "CB_COLOR0_DCC_CONTROL"
6853 "map": {"at": 167276, "to": "mm"},
6854 "name": "CB_COLOR4_CMASK",
6855 "type_ref": "DB_HTILE_DATA_BASE"
6859 "map": {"at": 167280, "to": "mm"},
6860 "name": "CB_COLOR4_CMASK_SLICE",
6861 "type_ref": "CB_COLOR0_CMASK_SLICE"
6865 "map": {"at": 167284, "to": "mm"},
6866 "name": "CB_COLOR4_FMASK",
6867 "type_ref": "DB_HTILE_DATA_BASE"
6871 "map": {"at": 167288, "to": "mm"},
6872 "name": "CB_COLOR4_FMASK_SLICE",
6873 "type_ref": "CB_COLOR0_SLICE"
6877 "map": {"at": 167292, "to": "mm"},
6878 "name": "CB_COLOR4_CLEAR_WORD0",
6879 "type_ref": "CB_COLOR0_CLEAR_WORD0"
6883 "map": {"at": 167296, "to": "mm"},
6884 "name": "CB_COLOR4_CLEAR_WORD1",
6885 "type_ref": "CB_COLOR0_CLEAR_WORD1"
6889 "map": {"at": 167300, "to": "mm"},
6890 "name": "CB_COLOR4_DCC_BASE",
6891 "type_ref": "DB_HTILE_DATA_BASE"
6895 "map": {"at": 167308, "to": "mm"},
6896 "name": "CB_COLOR5_BASE",
6897 "type_ref": "DB_HTILE_DATA_BASE"
6901 "map": {"at": 167312, "to": "mm"},
6902 "name": "CB_COLOR5_PITCH",
6903 "type_ref": "CB_COLOR0_PITCH"
6907 "map": {"at": 167316, "to": "mm"},
6908 "name": "CB_COLOR5_SLICE",
6909 "type_ref": "CB_COLOR0_SLICE"
6913 "map": {"at": 167320, "to": "mm"},
6914 "name": "CB_COLOR5_VIEW",
6915 "type_ref": "CB_COLOR0_VIEW"
6919 "map": {"at": 167324, "to": "mm"},
6920 "name": "CB_COLOR5_INFO",
6921 "type_ref": "CB_COLOR0_INFO"
6925 "map": {"at": 167328, "to": "mm"},
6926 "name": "CB_COLOR5_ATTRIB",
6927 "type_ref": "CB_COLOR0_ATTRIB"
6931 "map": {"at": 167332, "to": "mm"},
6932 "name": "CB_COLOR5_DCC_CONTROL",
6933 "type_ref": "CB_COLOR0_DCC_CONTROL"
6937 "map": {"at": 167336, "to": "mm"},
6938 "name": "CB_COLOR5_CMASK",
6939 "type_ref": "DB_HTILE_DATA_BASE"
6943 "map": {"at": 167340, "to": "mm"},
6944 "name": "CB_COLOR5_CMASK_SLICE",
6945 "type_ref": "CB_COLOR0_CMASK_SLICE"
6949 "map": {"at": 167344, "to": "mm"},
6950 "name": "CB_COLOR5_FMASK",
6951 "type_ref": "DB_HTILE_DATA_BASE"
6955 "map": {"at": 167348, "to": "mm"},
6956 "name": "CB_COLOR5_FMASK_SLICE",
6957 "type_ref": "CB_COLOR0_SLICE"
6961 "map": {"at": 167352, "to": "mm"},
6962 "name": "CB_COLOR5_CLEAR_WORD0",
6963 "type_ref": "CB_COLOR0_CLEAR_WORD0"
6967 "map": {"at": 167356, "to": "mm"},
6968 "name": "CB_COLOR5_CLEAR_WORD1",
6969 "type_ref": "CB_COLOR0_CLEAR_WORD1"
6973 "map": {"at": 167360, "to": "mm"},
6974 "name": "CB_COLOR5_DCC_BASE",
6975 "type_ref": "DB_HTILE_DATA_BASE"
6979 "map": {"at": 167368, "to": "mm"},
6980 "name": "CB_COLOR6_BASE",
6981 "type_ref": "DB_HTILE_DATA_BASE"
6985 "map": {"at": 167372, "to": "mm"},
6986 "name": "CB_COLOR6_PITCH",
6987 "type_ref": "CB_COLOR0_PITCH"
6991 "map": {"at": 167376, "to": "mm"},
6992 "name": "CB_COLOR6_SLICE",
6993 "type_ref": "CB_COLOR0_SLICE"
6997 "map": {"at": 167380, "to": "mm"},
6998 "name": "CB_COLOR6_VIEW",
6999 "type_ref": "CB_COLOR0_VIEW"
7003 "map": {"at": 167384, "to": "mm"},
7004 "name": "CB_COLOR6_INFO",
7005 "type_ref": "CB_COLOR0_INFO"
7009 "map": {"at": 167388, "to": "mm"},
7010 "name": "CB_COLOR6_ATTRIB",
7011 "type_ref": "CB_COLOR0_ATTRIB"
7015 "map": {"at": 167392, "to": "mm"},
7016 "name": "CB_COLOR6_DCC_CONTROL",
7017 "type_ref": "CB_COLOR0_DCC_CONTROL"
7021 "map": {"at": 167396, "to": "mm"},
7022 "name": "CB_COLOR6_CMASK",
7023 "type_ref": "DB_HTILE_DATA_BASE"
7027 "map": {"at": 167400, "to": "mm"},
7028 "name": "CB_COLOR6_CMASK_SLICE",
7029 "type_ref": "CB_COLOR0_CMASK_SLICE"
7033 "map": {"at": 167404, "to": "mm"},
7034 "name": "CB_COLOR6_FMASK",
7035 "type_ref": "DB_HTILE_DATA_BASE"
7039 "map": {"at": 167408, "to": "mm"},
7040 "name": "CB_COLOR6_FMASK_SLICE",
7041 "type_ref": "CB_COLOR0_SLICE"
7045 "map": {"at": 167412, "to": "mm"},
7046 "name": "CB_COLOR6_CLEAR_WORD0",
7047 "type_ref": "CB_COLOR0_CLEAR_WORD0"
7051 "map": {"at": 167416, "to": "mm"},
7052 "name": "CB_COLOR6_CLEAR_WORD1",
7053 "type_ref": "CB_COLOR0_CLEAR_WORD1"
7057 "map": {"at": 167420, "to": "mm"},
7058 "name": "CB_COLOR6_DCC_BASE",
7059 "type_ref": "DB_HTILE_DATA_BASE"
7063 "map": {"at": 167428, "to": "mm"},
7064 "name": "CB_COLOR7_BASE",
7065 "type_ref": "DB_HTILE_DATA_BASE"
7069 "map": {"at": 167432, "to": "mm"},
7070 "name": "CB_COLOR7_PITCH",
7071 "type_ref": "CB_COLOR0_PITCH"
7075 "map": {"at": 167436, "to": "mm"},
7076 "name": "CB_COLOR7_SLICE",
7077 "type_ref": "CB_COLOR0_SLICE"
7081 "map": {"at": 167440, "to": "mm"},
7082 "name": "CB_COLOR7_VIEW",
7083 "type_ref": "CB_COLOR0_VIEW"
7087 "map": {"at": 167444, "to": "mm"},
7088 "name": "CB_COLOR7_INFO",
7089 "type_ref": "CB_COLOR0_INFO"
7093 "map": {"at": 167448, "to": "mm"},
7094 "name": "CB_COLOR7_ATTRIB",
7095 "type_ref": "CB_COLOR0_ATTRIB"
7099 "map": {"at": 167452, "to": "mm"},
7100 "name": "CB_COLOR7_DCC_CONTROL",
7101 "type_ref": "CB_COLOR0_DCC_CONTROL"
7105 "map": {"at": 167456, "to": "mm"},
7106 "name": "CB_COLOR7_CMASK",
7107 "type_ref": "DB_HTILE_DATA_BASE"
7111 "map": {"at": 167460, "to": "mm"},
7112 "name": "CB_COLOR7_CMASK_SLICE",
7113 "type_ref": "CB_COLOR0_CMASK_SLICE"
7117 "map": {"at": 167464, "to": "mm"},
7118 "name": "CB_COLOR7_FMASK",
7119 "type_ref": "DB_HTILE_DATA_BASE"
7123 "map": {"at": 167468, "to": "mm"},
7124 "name": "CB_COLOR7_FMASK_SLICE",
7125 "type_ref": "CB_COLOR0_SLICE"
7129 "map": {"at": 167472, "to": "mm"},
7130 "name": "CB_COLOR7_CLEAR_WORD0",
7131 "type_ref": "CB_COLOR0_CLEAR_WORD0"
7135 "map": {"at": 167476, "to": "mm"},
7136 "name": "CB_COLOR7_CLEAR_WORD1",
7137 "type_ref": "CB_COLOR0_CLEAR_WORD1"
7141 "map": {"at": 167480, "to": "mm"},
7142 "name": "CB_COLOR7_DCC_BASE",
7143 "type_ref": "DB_HTILE_DATA_BASE"
7147 "map": {"at": 167488, "to": "mm"},
7148 "name": "CB_COLOR0_BASE_EXT",
7149 "type_ref": "CB_COLOR0_BASE_EXT"
7153 "map": {"at": 167492, "to": "mm"},
7154 "name": "CB_COLOR1_BASE_EXT",
7155 "type_ref": "CB_COLOR0_BASE_EXT"
7159 "map": {"at": 167496, "to": "mm"},
7160 "name": "CB_COLOR2_BASE_EXT",
7161 "type_ref": "CB_COLOR0_BASE_EXT"
7165 "map": {"at": 167500, "to": "mm"},
7166 "name": "CB_COLOR3_BASE_EXT",
7167 "type_ref": "CB_COLOR0_BASE_EXT"
7171 "map": {"at": 167504, "to": "mm"},
7172 "name": "CB_COLOR4_BASE_EXT",
7173 "type_ref": "CB_COLOR0_BASE_EXT"
7177 "map": {"at": 167508, "to": "mm"},
7178 "name": "CB_COLOR5_BASE_EXT",
7179 "type_ref": "CB_COLOR0_BASE_EXT"
7183 "map": {"at": 167512, "to": "mm"},
7184 "name": "CB_COLOR6_BASE_EXT",
7185 "type_ref": "CB_COLOR0_BASE_EXT"
7189 "map": {"at": 167516, "to": "mm"},
7190 "name": "CB_COLOR7_BASE_EXT",
7191 "type_ref": "CB_COLOR0_BASE_EXT"
7195 "map": {"at": 167520, "to": "mm"},
7196 "name": "CB_COLOR0_CMASK_BASE_EXT",
7197 "type_ref": "CB_COLOR0_BASE_EXT"
7201 "map": {"at": 167524, "to": "mm"},
7202 "name": "CB_COLOR1_CMASK_BASE_EXT",
7203 "type_ref": "CB_COLOR0_BASE_EXT"
7207 "map": {"at": 167528, "to": "mm"},
7208 "name": "CB_COLOR2_CMASK_BASE_EXT",
7209 "type_ref": "CB_COLOR0_BASE_EXT"
7213 "map": {"at": 167532, "to": "mm"},
7214 "name": "CB_COLOR3_CMASK_BASE_EXT",
7215 "type_ref": "CB_COLOR0_BASE_EXT"
7219 "map": {"at": 167536, "to": "mm"},
7220 "name": "CB_COLOR4_CMASK_BASE_EXT",
7221 "type_ref": "CB_COLOR0_BASE_EXT"
7225 "map": {"at": 167540, "to": "mm"},
7226 "name": "CB_COLOR5_CMASK_BASE_EXT",
7227 "type_ref": "CB_COLOR0_BASE_EXT"
7231 "map": {"at": 167544, "to": "mm"},
7232 "name": "CB_COLOR6_CMASK_BASE_EXT",
7233 "type_ref": "CB_COLOR0_BASE_EXT"
7237 "map": {"at": 167548, "to": "mm"},
7238 "name": "CB_COLOR7_CMASK_BASE_EXT",
7239 "type_ref": "CB_COLOR0_BASE_EXT"
7243 "map": {"at": 167552, "to": "mm"},
7244 "name": "CB_COLOR0_FMASK_BASE_EXT",
7245 "type_ref": "CB_COLOR0_BASE_EXT"
7249 "map": {"at": 167556, "to": "mm"},
7250 "name": "CB_COLOR1_FMASK_BASE_EXT",
7251 "type_ref": "CB_COLOR0_BASE_EXT"
7255 "map": {"at": 167560, "to": "mm"},
7256 "name": "CB_COLOR2_FMASK_BASE_EXT",
7257 "type_ref": "CB_COLOR0_BASE_EXT"
7261 "map": {"at": 167564, "to": "mm"},
7262 "name": "CB_COLOR3_FMASK_BASE_EXT",
7263 "type_ref": "CB_COLOR0_BASE_EXT"
7267 "map": {"at": 167568, "to": "mm"},
7268 "name": "CB_COLOR4_FMASK_BASE_EXT",
7269 "type_ref": "CB_COLOR0_BASE_EXT"
7273 "map": {"at": 167572, "to": "mm"},
7274 "name": "CB_COLOR5_FMASK_BASE_EXT",
7275 "type_ref": "CB_COLOR0_BASE_EXT"
7279 "map": {"at": 167576, "to": "mm"},
7280 "name": "CB_COLOR6_FMASK_BASE_EXT",
7281 "type_ref": "CB_COLOR0_BASE_EXT"
7285 "map": {"at": 167580, "to": "mm"},
7286 "name": "CB_COLOR7_FMASK_BASE_EXT",
7287 "type_ref": "CB_COLOR0_BASE_EXT"
7291 "map": {"at": 167584, "to": "mm"},
7292 "name": "CB_COLOR0_DCC_BASE_EXT",
7293 "type_ref": "CB_COLOR0_BASE_EXT"
7297 "map": {"at": 167588, "to": "mm"},
7298 "name": "CB_COLOR1_DCC_BASE_EXT",
7299 "type_ref": "CB_COLOR0_BASE_EXT"
7303 "map": {"at": 167592, "to": "mm"},
7304 "name": "CB_COLOR2_DCC_BASE_EXT",
7305 "type_ref": "CB_COLOR0_BASE_EXT"
7309 "map": {"at": 167596, "to": "mm"},
7310 "name": "CB_COLOR3_DCC_BASE_EXT",
7311 "type_ref": "CB_COLOR0_BASE_EXT"
7315 "map": {"at": 167600, "to": "mm"},
7316 "name": "CB_COLOR4_DCC_BASE_EXT",
7317 "type_ref": "CB_COLOR0_BASE_EXT"
7321 "map": {"at": 167604, "to": "mm"},
7322 "name": "CB_COLOR5_DCC_BASE_EXT",
7323 "type_ref": "CB_COLOR0_BASE_EXT"
7327 "map": {"at": 167608, "to": "mm"},
7328 "name": "CB_COLOR6_DCC_BASE_EXT",
7329 "type_ref": "CB_COLOR0_BASE_EXT"
7333 "map": {"at": 167612, "to": "mm"},
7334 "name": "CB_COLOR7_DCC_BASE_EXT",
7335 "type_ref": "CB_COLOR0_BASE_EXT"
7339 "map": {"at": 167616, "to": "mm"},
7340 "name": "CB_COLOR0_ATTRIB2",
7341 "type_ref": "CB_COLOR0_ATTRIB2"
7345 "map": {"at": 167620, "to": "mm"},
7346 "name": "CB_COLOR1_ATTRIB2",
7347 "type_ref": "CB_COLOR0_ATTRIB2"
7351 "map": {"at": 167624, "to": "mm"},
7352 "name": "CB_COLOR2_ATTRIB2",
7353 "type_ref": "CB_COLOR0_ATTRIB2"
7357 "map": {"at": 167628, "to": "mm"},
7358 "name": "CB_COLOR3_ATTRIB2",
7359 "type_ref": "CB_COLOR0_ATTRIB2"
7363 "map": {"at": 167632, "to": "mm"},
7364 "name": "CB_COLOR4_ATTRIB2",
7365 "type_ref": "CB_COLOR0_ATTRIB2"
7369 "map": {"at": 167636, "to": "mm"},
7370 "name": "CB_COLOR5_ATTRIB2",
7371 "type_ref": "CB_COLOR0_ATTRIB2"
7375 "map": {"at": 167640, "to": "mm"},
7376 "name": "CB_COLOR6_ATTRIB2",
7377 "type_ref": "CB_COLOR0_ATTRIB2"
7381 "map": {"at": 167644, "to": "mm"},
7382 "name": "CB_COLOR7_ATTRIB2",
7383 "type_ref": "CB_COLOR0_ATTRIB2"
7387 "map": {"at": 167648, "to": "mm"},
7388 "name": "CB_COLOR0_ATTRIB3",
7389 "type_ref": "CB_COLOR0_ATTRIB3"
7393 "map": {"at": 167652, "to": "mm"},
7394 "name": "CB_COLOR1_ATTRIB3",
7395 "type_ref": "CB_COLOR0_ATTRIB3"
7399 "map": {"at": 167656, "to": "mm"},
7400 "name": "CB_COLOR2_ATTRIB3",
7401 "type_ref": "CB_COLOR0_ATTRIB3"
7405 "map": {"at": 167660, "to": "mm"},
7406 "name": "CB_COLOR3_ATTRIB3",
7407 "type_ref": "CB_COLOR0_ATTRIB3"
7411 "map": {"at": 167664, "to": "mm"},
7412 "name": "CB_COLOR4_ATTRIB3",
7413 "type_ref": "CB_COLOR0_ATTRIB3"
7417 "map": {"at": 167668, "to": "mm"},
7418 "name": "CB_COLOR5_ATTRIB3",
7419 "type_ref": "CB_COLOR0_ATTRIB3"
7423 "map": {"at": 167672, "to": "mm"},
7424 "name": "CB_COLOR6_ATTRIB3",
7425 "type_ref": "CB_COLOR0_ATTRIB3"
7429 "map": {"at": 167676, "to": "mm"},
7430 "name": "CB_COLOR7_ATTRIB3",
7431 "type_ref": "CB_COLOR0_ATTRIB3"
7435 "map": {"at": 196608, "to": "mm"},
7436 "name": "CP_EOP_DONE_ADDR_LO",
7437 "type_ref": "CP_EOP_DONE_ADDR_LO"
7441 "map": {"at": 196612, "to": "mm"},
7442 "name": "CP_EOP_DONE_ADDR_HI",
7443 "type_ref": "CP_EOP_DONE_ADDR_HI"
7447 "map": {"at": 196616, "to": "mm"},
7448 "name": "CP_EOP_DONE_DATA_LO",
7449 "type_ref": "CP_EOP_DONE_DATA_LO"
7453 "map": {"at": 196620, "to": "mm"},
7454 "name": "CP_EOP_DONE_DATA_HI",
7455 "type_ref": "CP_EOP_DONE_DATA_HI"
7459 "map": {"at": 196624, "to": "mm"},
7460 "name": "CP_EOP_LAST_FENCE_LO",
7461 "type_ref": "CP_EOP_LAST_FENCE_LO"
7465 "map": {"at": 196628, "to": "mm"},
7466 "name": "CP_EOP_LAST_FENCE_HI",
7467 "type_ref": "CP_EOP_LAST_FENCE_HI"
7471 "map": {"at": 196632, "to": "mm"},
7472 "name": "CP_STREAM_OUT_ADDR_LO",
7473 "type_ref": "CP_STREAM_OUT_ADDR_LO"
7477 "map": {"at": 196636, "to": "mm"},
7478 "name": "CP_STREAM_OUT_ADDR_HI",
7479 "type_ref": "CP_STREAM_OUT_ADDR_HI"
7483 "map": {"at": 196640, "to": "mm"},
7484 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO",
7485 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
7489 "map": {"at": 196644, "to": "mm"},
7490 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI",
7491 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
7495 "map": {"at": 196648, "to": "mm"},
7496 "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO",
7497 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
7501 "map": {"at": 196652, "to": "mm"},
7502 "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI",
7503 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
7507 "map": {"at": 196656, "to": "mm"},
7508 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO",
7509 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
7513 "map": {"at": 196660, "to": "mm"},
7514 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI",
7515 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
7519 "map": {"at": 196664, "to": "mm"},
7520 "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO",
7521 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
7525 "map": {"at": 196668, "to": "mm"},
7526 "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI",
7527 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
7531 "map": {"at": 196672, "to": "mm"},
7532 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO",
7533 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
7537 "map": {"at": 196676, "to": "mm"},
7538 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI",
7539 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
7543 "map": {"at": 196680, "to": "mm"},
7544 "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO",
7545 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
7549 "map": {"at": 196684, "to": "mm"},
7550 "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI",
7551 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
7555 "map": {"at": 196688, "to": "mm"},
7556 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO",
7557 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
7561 "map": {"at": 196692, "to": "mm"},
7562 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI",
7563 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
7567 "map": {"at": 196696, "to": "mm"},
7568 "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO",
7569 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
7573 "map": {"at": 196700, "to": "mm"},
7574 "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI",
7575 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
7579 "map": {"at": 196704, "to": "mm"},
7580 "name": "CP_PIPE_STATS_ADDR_LO",
7581 "type_ref": "CP_PIPE_STATS_ADDR_LO"
7585 "map": {"at": 196708, "to": "mm"},
7586 "name": "CP_PIPE_STATS_ADDR_HI",
7587 "type_ref": "CP_PIPE_STATS_ADDR_HI"
7591 "map": {"at": 196712, "to": "mm"},
7592 "name": "CP_VGT_IAVERT_COUNT_LO",
7593 "type_ref": "CP_VGT_IAVERT_COUNT_LO"
7597 "map": {"at": 196716, "to": "mm"},
7598 "name": "CP_VGT_IAVERT_COUNT_HI",
7599 "type_ref": "CP_VGT_IAVERT_COUNT_HI"
7603 "map": {"at": 196720, "to": "mm"},
7604 "name": "CP_VGT_IAPRIM_COUNT_LO",
7605 "type_ref": "CP_VGT_IAPRIM_COUNT_LO"
7609 "map": {"at": 196724, "to": "mm"},
7610 "name": "CP_VGT_IAPRIM_COUNT_HI",
7611 "type_ref": "CP_VGT_IAPRIM_COUNT_HI"
7615 "map": {"at": 196728, "to": "mm"},
7616 "name": "CP_VGT_GSPRIM_COUNT_LO",
7617 "type_ref": "CP_VGT_GSPRIM_COUNT_LO"
7621 "map": {"at": 196732, "to": "mm"},
7622 "name": "CP_VGT_GSPRIM_COUNT_HI",
7623 "type_ref": "CP_VGT_GSPRIM_COUNT_HI"
7627 "map": {"at": 196736, "to": "mm"},
7628 "name": "CP_VGT_VSINVOC_COUNT_LO",
7629 "type_ref": "CP_VGT_VSINVOC_COUNT_LO"
7633 "map": {"at": 196740, "to": "mm"},
7634 "name": "CP_VGT_VSINVOC_COUNT_HI",
7635 "type_ref": "CP_VGT_VSINVOC_COUNT_HI"
7639 "map": {"at": 196744, "to": "mm"},
7640 "name": "CP_VGT_GSINVOC_COUNT_LO",
7641 "type_ref": "CP_VGT_GSINVOC_COUNT_LO"
7645 "map": {"at": 196748, "to": "mm"},
7646 "name": "CP_VGT_GSINVOC_COUNT_HI",
7647 "type_ref": "CP_VGT_GSINVOC_COUNT_HI"
7651 "map": {"at": 196752, "to": "mm"},
7652 "name": "CP_VGT_HSINVOC_COUNT_LO",
7653 "type_ref": "CP_VGT_HSINVOC_COUNT_LO"
7657 "map": {"at": 196756, "to": "mm"},
7658 "name": "CP_VGT_HSINVOC_COUNT_HI",
7659 "type_ref": "CP_VGT_HSINVOC_COUNT_HI"
7663 "map": {"at": 196760, "to": "mm"},
7664 "name": "CP_VGT_DSINVOC_COUNT_LO",
7665 "type_ref": "CP_VGT_DSINVOC_COUNT_LO"
7669 "map": {"at": 196764, "to": "mm"},
7670 "name": "CP_VGT_DSINVOC_COUNT_HI",
7671 "type_ref": "CP_VGT_DSINVOC_COUNT_HI"
7675 "map": {"at": 196768, "to": "mm"},
7676 "name": "CP_PA_CINVOC_COUNT_LO",
7677 "type_ref": "CP_PA_CINVOC_COUNT_LO"
7681 "map": {"at": 196772, "to": "mm"},
7682 "name": "CP_PA_CINVOC_COUNT_HI",
7683 "type_ref": "CP_PA_CINVOC_COUNT_HI"
7687 "map": {"at": 196776, "to": "mm"},
7688 "name": "CP_PA_CPRIM_COUNT_LO",
7689 "type_ref": "CP_PA_CPRIM_COUNT_LO"
7693 "map": {"at": 196780, "to": "mm"},
7694 "name": "CP_PA_CPRIM_COUNT_HI",
7695 "type_ref": "CP_PA_CPRIM_COUNT_HI"
7699 "map": {"at": 196784, "to": "mm"},
7700 "name": "CP_SC_PSINVOC_COUNT0_LO",
7701 "type_ref": "CP_SC_PSINVOC_COUNT0_LO"
7705 "map": {"at": 196788, "to": "mm"},
7706 "name": "CP_SC_PSINVOC_COUNT0_HI",
7707 "type_ref": "CP_SC_PSINVOC_COUNT0_HI"
7711 "map": {"at": 196792, "to": "mm"},
7712 "name": "CP_SC_PSINVOC_COUNT1_LO",
7713 "type_ref": "CP_SC_PSINVOC_COUNT1_LO"
7717 "map": {"at": 196796, "to": "mm"},
7718 "name": "CP_SC_PSINVOC_COUNT1_HI",
7719 "type_ref": "CP_SC_PSINVOC_COUNT1_LO"
7723 "map": {"at": 196800, "to": "mm"},
7724 "name": "CP_VGT_CSINVOC_COUNT_LO",
7725 "type_ref": "CP_VGT_CSINVOC_COUNT_LO"
7729 "map": {"at": 196804, "to": "mm"},
7730 "name": "CP_VGT_CSINVOC_COUNT_HI",
7731 "type_ref": "CP_VGT_CSINVOC_COUNT_HI"
7735 "map": {"at": 196808, "to": "mm"},
7736 "name": "CP_EOP_DONE_DOORBELL",
7737 "type_ref": "CP_EOP_DONE_DOORBELL"
7741 "map": {"at": 196812, "to": "mm"},
7742 "name": "CP_STREAM_OUT_DOORBELL",
7743 "type_ref": "CP_EOP_DONE_DOORBELL"
7747 "map": {"at": 196816, "to": "mm"},
7748 "name": "CP_SEM_DOORBELL",
7749 "type_ref": "CP_EOP_DONE_DOORBELL"
7753 "map": {"at": 196852, "to": "mm"},
7754 "name": "CP_PIPE_STATS_CONTROL",
7755 "type_ref": "CP_PIPE_STATS_CONTROL"
7759 "map": {"at": 196856, "to": "mm"},
7760 "name": "CP_STREAM_OUT_CONTROL",
7761 "type_ref": "CP_PIPE_STATS_CONTROL"
7765 "map": {"at": 196860, "to": "mm"},
7766 "name": "CP_STRMOUT_CNTL",
7767 "type_ref": "CP_STRMOUT_CNTL"
7771 "map": {"at": 196864, "to": "mm"},
7772 "name": "SCRATCH_REG0",
7773 "type_ref": "SCRATCH_REG0"
7777 "map": {"at": 196868, "to": "mm"},
7778 "name": "SCRATCH_REG1",
7779 "type_ref": "SCRATCH_REG1"
7783 "map": {"at": 196872, "to": "mm"},
7784 "name": "SCRATCH_REG2",
7785 "type_ref": "SCRATCH_REG2"
7789 "map": {"at": 196876, "to": "mm"},
7790 "name": "SCRATCH_REG3",
7791 "type_ref": "SCRATCH_REG3"
7795 "map": {"at": 196880, "to": "mm"},
7796 "name": "SCRATCH_REG4",
7797 "type_ref": "SCRATCH_REG4"
7801 "map": {"at": 196884, "to": "mm"},
7802 "name": "SCRATCH_REG5",
7803 "type_ref": "SCRATCH_REG5"
7807 "map": {"at": 196888, "to": "mm"},
7808 "name": "SCRATCH_REG6",
7809 "type_ref": "SCRATCH_REG6"
7813 "map": {"at": 196892, "to": "mm"},
7814 "name": "SCRATCH_REG7",
7815 "type_ref": "SCRATCH_REG7"
7819 "map": {"at": 196896, "to": "mm"},
7820 "name": "CP_PIPE_STATS_DOORBELL",
7821 "type_ref": "CP_EOP_DONE_DOORBELL"
7825 "map": {"at": 196908, "to": "mm"},
7826 "name": "CP_APPEND_DDID_CNT",
7827 "type_ref": "COMPUTE_PGM_HI"
7831 "map": {"at": 196912, "to": "mm"},
7832 "name": "CP_APPEND_DATA_HI",
7833 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
7837 "map": {"at": 196916, "to": "mm"},
7838 "name": "CP_APPEND_LAST_CS_FENCE_HI",
7839 "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7843 "map": {"at": 196920, "to": "mm"},
7844 "name": "CP_APPEND_LAST_PS_FENCE_HI",
7845 "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7849 "map": {"at": 196928, "to": "mm"},
7850 "name": "SCRATCH_UMSK",
7851 "type_ref": "SCRATCH_UMSK"
7855 "map": {"at": 196932, "to": "mm"},
7856 "name": "SCRATCH_ADDR",
7857 "type_ref": "SCRATCH_ADDR"
7861 "map": {"at": 196936, "to": "mm"},
7862 "name": "CP_PFP_ATOMIC_PREOP_LO",
7863 "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
7867 "map": {"at": 196940, "to": "mm"},
7868 "name": "CP_PFP_ATOMIC_PREOP_HI",
7869 "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
7873 "map": {"at": 196944, "to": "mm"},
7874 "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO",
7875 "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7879 "map": {"at": 196948, "to": "mm"},
7880 "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI",
7881 "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7885 "map": {"at": 196952, "to": "mm"},
7886 "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO",
7887 "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7891 "map": {"at": 196956, "to": "mm"},
7892 "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI",
7893 "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7897 "map": {"at": 196960, "to": "mm"},
7898 "name": "CP_APPEND_ADDR_LO",
7899 "type_ref": "CP_APPEND_ADDR_LO"
7903 "map": {"at": 196964, "to": "mm"},
7904 "name": "CP_APPEND_ADDR_HI",
7905 "type_ref": "CP_APPEND_ADDR_HI"
7909 "map": {"at": 196968, "to": "mm"},
7910 "name": "CP_APPEND_DATA",
7911 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
7915 "map": {"at": 196972, "to": "mm"},
7916 "name": "CP_APPEND_LAST_CS_FENCE",
7917 "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7921 "map": {"at": 196976, "to": "mm"},
7922 "name": "CP_APPEND_LAST_PS_FENCE",
7923 "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7927 "map": {"at": 196980, "to": "mm"},
7928 "name": "CP_ATOMIC_PREOP_LO",
7929 "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
7933 "map": {"at": 196984, "to": "mm"},
7934 "name": "CP_ATOMIC_PREOP_HI",
7935 "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
7939 "map": {"at": 196988, "to": "mm"},
7940 "name": "CP_GDS_ATOMIC0_PREOP_LO",
7941 "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7945 "map": {"at": 196992, "to": "mm"},
7946 "name": "CP_GDS_ATOMIC0_PREOP_HI",
7947 "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7951 "map": {"at": 196996, "to": "mm"},
7952 "name": "CP_GDS_ATOMIC1_PREOP_LO",
7953 "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7957 "map": {"at": 197000, "to": "mm"},
7958 "name": "CP_GDS_ATOMIC1_PREOP_HI",
7959 "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7963 "map": {"at": 197028, "to": "mm"},
7964 "name": "CP_ME_MC_WADDR_LO",
7965 "type_ref": "CP_ME_MC_WADDR_LO"
7969 "map": {"at": 197032, "to": "mm"},
7970 "name": "CP_ME_MC_WADDR_HI",
7971 "type_ref": "CP_ME_MC_WADDR_HI"
7975 "map": {"at": 197036, "to": "mm"},
7976 "name": "CP_ME_MC_WDATA_LO",
7977 "type_ref": "CP_ME_MC_WDATA_LO"
7981 "map": {"at": 197040, "to": "mm"},
7982 "name": "CP_ME_MC_WDATA_HI",
7983 "type_ref": "CP_ME_MC_WDATA_HI"
7987 "map": {"at": 197044, "to": "mm"},
7988 "name": "CP_ME_MC_RADDR_LO",
7989 "type_ref": "CP_ME_MC_RADDR_LO"
7993 "map": {"at": 197048, "to": "mm"},
7994 "name": "CP_ME_MC_RADDR_HI",
7995 "type_ref": "CP_ME_MC_RADDR_HI"
7999 "map": {"at": 197052, "to": "mm"},
8000 "name": "CP_SEM_WAIT_TIMER",
8001 "type_ref": "CP_SEM_WAIT_TIMER"
8005 "map": {"at": 197056, "to": "mm"},
8006 "name": "CP_SIG_SEM_ADDR_LO",
8007 "type_ref": "CP_SIG_SEM_ADDR_LO"
8011 "map": {"at": 197060, "to": "mm"},
8012 "name": "CP_SIG_SEM_ADDR_HI",
8013 "type_ref": "CP_SIG_SEM_ADDR_HI"
8017 "map": {"at": 197072, "to": "mm"},
8018 "name": "CP_WAIT_REG_MEM_TIMEOUT",
8019 "type_ref": "CP_WAIT_REG_MEM_TIMEOUT"
8023 "map": {"at": 197076, "to": "mm"},
8024 "name": "CP_WAIT_SEM_ADDR_LO",
8025 "type_ref": "CP_SIG_SEM_ADDR_LO"
8029 "map": {"at": 197080, "to": "mm"},
8030 "name": "CP_WAIT_SEM_ADDR_HI",
8031 "type_ref": "CP_SIG_SEM_ADDR_HI"
8035 "map": {"at": 197084, "to": "mm"},
8036 "name": "CP_DMA_PFP_CONTROL",
8037 "type_ref": "CP_DMA_PFP_CONTROL"
8041 "map": {"at": 197088, "to": "mm"},
8042 "name": "CP_DMA_ME_CONTROL",
8043 "type_ref": "CP_DMA_PFP_CONTROL"
8047 "map": {"at": 197092, "to": "mm"},
8048 "name": "CP_COHER_BASE_HI",
8049 "type_ref": "CP_COHER_BASE_HI"
8053 "map": {"at": 197100, "to": "mm"},
8054 "name": "CP_COHER_START_DELAY",
8055 "type_ref": "CP_COHER_START_DELAY"
8059 "map": {"at": 197104, "to": "mm"},
8060 "name": "CP_COHER_CNTL",
8061 "type_ref": "CP_COHER_CNTL"
8065 "map": {"at": 197108, "to": "mm"},
8066 "name": "CP_COHER_SIZE",
8067 "type_ref": "CP_COHER_SIZE"
8071 "map": {"at": 197112, "to": "mm"},
8072 "name": "CP_COHER_BASE",
8073 "type_ref": "CP_COHER_BASE"
8077 "map": {"at": 197116, "to": "mm"},
8078 "name": "CP_COHER_STATUS",
8079 "type_ref": "CP_COHER_STATUS"
8083 "map": {"at": 197120, "to": "mm"},
8084 "name": "CP_DMA_ME_SRC_ADDR",
8085 "type_ref": "CP_DMA_ME_SRC_ADDR"
8089 "map": {"at": 197124, "to": "mm"},
8090 "name": "CP_DMA_ME_SRC_ADDR_HI",
8091 "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
8095 "map": {"at": 197128, "to": "mm"},
8096 "name": "CP_DMA_ME_DST_ADDR",
8097 "type_ref": "CP_DMA_ME_DST_ADDR"
8101 "map": {"at": 197132, "to": "mm"},
8102 "name": "CP_DMA_ME_DST_ADDR_HI",
8103 "type_ref": "CP_DMA_ME_DST_ADDR_HI"
8107 "map": {"at": 197136, "to": "mm"},
8108 "name": "CP_DMA_ME_COMMAND",
8109 "type_ref": "CP_DMA_ME_COMMAND"
8113 "map": {"at": 197140, "to": "mm"},
8114 "name": "CP_DMA_PFP_SRC_ADDR",
8115 "type_ref": "CP_DMA_ME_SRC_ADDR"
8119 "map": {"at": 197144, "to": "mm"},
8120 "name": "CP_DMA_PFP_SRC_ADDR_HI",
8121 "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
8125 "map": {"at": 197148, "to": "mm"},
8126 "name": "CP_DMA_PFP_DST_ADDR",
8127 "type_ref": "CP_DMA_ME_DST_ADDR"
8131 "map": {"at": 197152, "to": "mm"},
8132 "name": "CP_DMA_PFP_DST_ADDR_HI",
8133 "type_ref": "CP_DMA_ME_DST_ADDR_HI"
8137 "map": {"at": 197156, "to": "mm"},
8138 "name": "CP_DMA_PFP_COMMAND",
8139 "type_ref": "CP_DMA_ME_COMMAND"
8143 "map": {"at": 197160, "to": "mm"},
8144 "name": "CP_DMA_CNTL",
8145 "type_ref": "CP_DMA_CNTL"
8149 "map": {"at": 197164, "to": "mm"},
8150 "name": "CP_DMA_READ_TAGS",
8151 "type_ref": "CP_DMA_READ_TAGS"
8155 "map": {"at": 197168, "to": "mm"},
8156 "name": "CP_COHER_SIZE_HI",
8157 "type_ref": "CP_COHER_SIZE_HI"
8161 "map": {"at": 197172, "to": "mm"},
8162 "name": "CP_PFP_IB_CONTROL",
8163 "type_ref": "CP_PFP_IB_CONTROL"
8167 "map": {"at": 197176, "to": "mm"},
8168 "name": "CP_PFP_LOAD_CONTROL",
8169 "type_ref": "CP_PFP_LOAD_CONTROL"
8173 "map": {"at": 197180, "to": "mm"},
8174 "name": "CP_SCRATCH_INDEX",
8175 "type_ref": "CP_SCRATCH_INDEX"
8179 "map": {"at": 197184, "to": "mm"},
8180 "name": "CP_SCRATCH_DATA",
8181 "type_ref": "CP_CPC_SCRATCH_DATA"
8185 "map": {"at": 197188, "to": "mm"},
8186 "name": "CP_RB_OFFSET",
8187 "type_ref": "CP_RB_OFFSET"
8191 "map": {"at": 197192, "to": "mm"},
8192 "name": "CP_IB1_OFFSET",
8193 "type_ref": "CP_IB1_OFFSET"
8197 "map": {"at": 197196, "to": "mm"},
8198 "name": "CP_IB2_OFFSET",
8199 "type_ref": "CP_IB2_OFFSET"
8203 "map": {"at": 197200, "to": "mm"},
8204 "name": "CP_IB1_PREAMBLE_BEGIN",
8205 "type_ref": "CP_IB1_PREAMBLE_BEGIN"
8209 "map": {"at": 197204, "to": "mm"},
8210 "name": "CP_IB1_PREAMBLE_END",
8211 "type_ref": "CP_IB1_PREAMBLE_END"
8215 "map": {"at": 197208, "to": "mm"},
8216 "name": "CP_IB2_PREAMBLE_BEGIN",
8217 "type_ref": "CP_IB2_PREAMBLE_BEGIN"
8221 "map": {"at": 197212, "to": "mm"},
8222 "name": "CP_IB2_PREAMBLE_END",
8223 "type_ref": "CP_IB2_PREAMBLE_END"
8227 "map": {"at": 197216, "to": "mm"},
8228 "name": "CP_CE_IB1_OFFSET",
8229 "type_ref": "CP_IB1_OFFSET"
8233 "map": {"at": 197220, "to": "mm"},
8234 "name": "CP_CE_IB2_OFFSET",
8235 "type_ref": "CP_IB2_OFFSET"
8239 "map": {"at": 197224, "to": "mm"},
8240 "name": "CP_CE_COUNTER",
8241 "type_ref": "CP_CE_COUNTER"
8245 "map": {"at": 197232, "to": "mm"},
8246 "name": "CP_DMA_ME_CMD_ADDR_LO",
8247 "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
8251 "map": {"at": 197236, "to": "mm"},
8252 "name": "CP_DMA_ME_CMD_ADDR_HI",
8253 "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
8257 "map": {"at": 197240, "to": "mm"},
8258 "name": "CP_DMA_PFP_CMD_ADDR_LO",
8259 "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
8263 "map": {"at": 197244, "to": "mm"},
8264 "name": "CP_DMA_PFP_CMD_ADDR_HI",
8265 "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
8269 "map": {"at": 197248, "to": "mm"},
8270 "name": "CP_APPEND_CMD_ADDR_LO",
8271 "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
8275 "map": {"at": 197252, "to": "mm"},
8276 "name": "CP_APPEND_CMD_ADDR_HI",
8277 "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
8281 "map": {"at": 197364, "to": "mm"},
8282 "name": "CP_CE_INIT_CMD_BUFSZ",
8283 "type_ref": "CP_CE_INIT_CMD_BUFSZ"
8287 "map": {"at": 197368, "to": "mm"},
8288 "name": "CP_CE_IB1_CMD_BUFSZ",
8289 "type_ref": "CP_CE_IB1_CMD_BUFSZ"
8293 "map": {"at": 197372, "to": "mm"},
8294 "name": "CP_CE_IB2_CMD_BUFSZ",
8295 "type_ref": "CP_CE_IB2_CMD_BUFSZ"
8299 "map": {"at": 197376, "to": "mm"},
8300 "name": "CP_IB1_CMD_BUFSZ",
8301 "type_ref": "CP_CE_IB1_CMD_BUFSZ"
8305 "map": {"at": 197380, "to": "mm"},
8306 "name": "CP_IB2_CMD_BUFSZ",
8307 "type_ref": "CP_CE_IB2_CMD_BUFSZ"
8311 "map": {"at": 197384, "to": "mm"},
8312 "name": "CP_ST_CMD_BUFSZ",
8313 "type_ref": "CP_ST_CMD_BUFSZ"
8317 "map": {"at": 197388, "to": "mm"},
8318 "name": "CP_CE_INIT_BASE_LO",
8319 "type_ref": "CP_CE_INIT_BASE_LO"
8323 "map": {"at": 197392, "to": "mm"},
8324 "name": "CP_CE_INIT_BASE_HI",
8325 "type_ref": "CP_CE_INIT_BASE_HI"
8329 "map": {"at": 197396, "to": "mm"},
8330 "name": "CP_CE_INIT_BUFSZ",
8331 "type_ref": "CP_CE_INIT_BUFSZ"
8335 "map": {"at": 197400, "to": "mm"},
8336 "name": "CP_CE_IB1_BASE_LO",
8337 "type_ref": "CP_CE_IB1_BASE_LO"
8341 "map": {"at": 197404, "to": "mm"},
8342 "name": "CP_CE_IB1_BASE_HI",
8343 "type_ref": "CP_CE_IB1_BASE_HI"
8347 "map": {"at": 197408, "to": "mm"},
8348 "name": "CP_CE_IB1_BUFSZ",
8349 "type_ref": "CP_CE_IB1_BUFSZ"
8353 "map": {"at": 197412, "to": "mm"},
8354 "name": "CP_CE_IB2_BASE_LO",
8355 "type_ref": "CP_CE_IB2_BASE_LO"
8359 "map": {"at": 197416, "to": "mm"},
8360 "name": "CP_CE_IB2_BASE_HI",
8361 "type_ref": "CP_CE_IB2_BASE_HI"
8365 "map": {"at": 197420, "to": "mm"},
8366 "name": "CP_CE_IB2_BUFSZ",
8367 "type_ref": "CP_CE_IB2_BUFSZ"
8371 "map": {"at": 197424, "to": "mm"},
8372 "name": "CP_IB1_BASE_LO",
8373 "type_ref": "CP_CE_IB1_BASE_LO"
8377 "map": {"at": 197428, "to": "mm"},
8378 "name": "CP_IB1_BASE_HI",
8379 "type_ref": "CP_CE_IB1_BASE_HI"
8383 "map": {"at": 197432, "to": "mm"},
8384 "name": "CP_IB1_BUFSZ",
8385 "type_ref": "CP_CE_IB1_BUFSZ"
8389 "map": {"at": 197436, "to": "mm"},
8390 "name": "CP_IB2_BASE_LO",
8391 "type_ref": "CP_CE_IB2_BASE_LO"
8395 "map": {"at": 197440, "to": "mm"},
8396 "name": "CP_IB2_BASE_HI",
8397 "type_ref": "CP_CE_IB2_BASE_HI"
8401 "map": {"at": 197444, "to": "mm"},
8402 "name": "CP_IB2_BUFSZ",
8403 "type_ref": "CP_CE_IB2_BUFSZ"
8407 "map": {"at": 197448, "to": "mm"},
8408 "name": "CP_ST_BASE_LO",
8409 "type_ref": "CP_ST_BASE_LO"
8413 "map": {"at": 197452, "to": "mm"},
8414 "name": "CP_ST_BASE_HI",
8415 "type_ref": "CP_ST_BASE_HI"
8419 "map": {"at": 197456, "to": "mm"},
8420 "name": "CP_ST_BUFSZ",
8421 "type_ref": "CP_ST_BUFSZ"
8425 "map": {"at": 197460, "to": "mm"},
8426 "name": "CP_EOP_DONE_EVENT_CNTL",
8427 "type_ref": "CP_EOP_DONE_EVENT_CNTL"
8431 "map": {"at": 197464, "to": "mm"},
8432 "name": "CP_EOP_DONE_DATA_CNTL",
8433 "type_ref": "CP_EOP_DONE_DATA_CNTL"
8437 "map": {"at": 197468, "to": "mm"},
8438 "name": "CP_EOP_DONE_CNTX_ID",
8439 "type_ref": "CP_EOP_DONE_CNTX_ID"
8443 "map": {"at": 197472, "to": "mm"},
8444 "name": "CP_DB_BASE_LO",
8445 "type_ref": "CP_DB_BASE_LO"
8449 "map": {"at": 197476, "to": "mm"},
8450 "name": "CP_DB_BASE_HI",
8451 "type_ref": "CP_DB_BASE_HI"
8455 "map": {"at": 197480, "to": "mm"},
8456 "name": "CP_DB_BUFSZ",
8457 "type_ref": "CP_DB_BUFSZ"
8461 "map": {"at": 197484, "to": "mm"},
8462 "name": "CP_DB_CMD_BUFSZ",
8463 "type_ref": "CP_DB_CMD_BUFSZ"
8467 "map": {"at": 197488, "to": "mm"},
8468 "name": "CP_CE_DB_BASE_LO",
8469 "type_ref": "CP_DB_BASE_LO"
8473 "map": {"at": 197492, "to": "mm"},
8474 "name": "CP_CE_DB_BASE_HI",
8475 "type_ref": "CP_DB_BASE_HI"
8479 "map": {"at": 197496, "to": "mm"},
8480 "name": "CP_CE_DB_BUFSZ",
8481 "type_ref": "CP_DB_BUFSZ"
8485 "map": {"at": 197500, "to": "mm"},
8486 "name": "CP_CE_DB_CMD_BUFSZ",
8487 "type_ref": "CP_DB_CMD_BUFSZ"
8491 "map": {"at": 197552, "to": "mm"},
8492 "name": "CP_PFP_COMPLETION_STATUS",
8493 "type_ref": "CP_PFP_COMPLETION_STATUS"
8497 "map": {"at": 197556, "to": "mm"},
8498 "name": "CP_CE_COMPLETION_STATUS",
8499 "type_ref": "CP_PFP_COMPLETION_STATUS"
8503 "map": {"at": 197560, "to": "mm"},
8504 "name": "CP_PRED_NOT_VISIBLE",
8505 "type_ref": "CP_PRED_NOT_VISIBLE"
8509 "map": {"at": 197568, "to": "mm"},
8510 "name": "CP_PFP_METADATA_BASE_ADDR",
8511 "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8515 "map": {"at": 197572, "to": "mm"},
8516 "name": "CP_PFP_METADATA_BASE_ADDR_HI",
8517 "type_ref": "CP_EOP_DONE_ADDR_HI"
8521 "map": {"at": 197576, "to": "mm"},
8522 "name": "CP_CE_METADATA_BASE_ADDR",
8523 "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8527 "map": {"at": 197580, "to": "mm"},
8528 "name": "CP_CE_METADATA_BASE_ADDR_HI",
8529 "type_ref": "CP_EOP_DONE_ADDR_HI"
8533 "map": {"at": 197584, "to": "mm"},
8534 "name": "CP_DRAW_INDX_INDR_ADDR",
8535 "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8539 "map": {"at": 197588, "to": "mm"},
8540 "name": "CP_DRAW_INDX_INDR_ADDR_HI",
8541 "type_ref": "CP_EOP_DONE_ADDR_HI"
8545 "map": {"at": 197592, "to": "mm"},
8546 "name": "CP_DISPATCH_INDR_ADDR",
8547 "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8551 "map": {"at": 197596, "to": "mm"},
8552 "name": "CP_DISPATCH_INDR_ADDR_HI",
8553 "type_ref": "CP_EOP_DONE_ADDR_HI"
8557 "map": {"at": 197600, "to": "mm"},
8558 "name": "CP_INDEX_BASE_ADDR",
8559 "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8563 "map": {"at": 197604, "to": "mm"},
8564 "name": "CP_INDEX_BASE_ADDR_HI",
8565 "type_ref": "CP_EOP_DONE_ADDR_HI"
8569 "map": {"at": 197608, "to": "mm"},
8570 "name": "CP_INDEX_TYPE",
8571 "type_ref": "CP_INDEX_TYPE"
8575 "map": {"at": 197612, "to": "mm"},
8576 "name": "CP_GDS_BKUP_ADDR",
8577 "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8581 "map": {"at": 197616, "to": "mm"},
8582 "name": "CP_GDS_BKUP_ADDR_HI",
8583 "type_ref": "CP_EOP_DONE_ADDR_HI"
8587 "map": {"at": 197620, "to": "mm"},
8588 "name": "CP_SAMPLE_STATUS",
8589 "type_ref": "CP_SAMPLE_STATUS"
8593 "map": {"at": 197624, "to": "mm"},
8594 "name": "CP_ME_COHER_CNTL",
8595 "type_ref": "CP_ME_COHER_CNTL"
8599 "map": {"at": 197628, "to": "mm"},
8600 "name": "CP_ME_COHER_SIZE",
8601 "type_ref": "CP_COHER_SIZE"
8605 "map": {"at": 197632, "to": "mm"},
8606 "name": "CP_ME_COHER_SIZE_HI",
8607 "type_ref": "CP_COHER_SIZE_HI"
8611 "map": {"at": 197636, "to": "mm"},
8612 "name": "CP_ME_COHER_BASE",
8613 "type_ref": "CP_COHER_BASE"
8617 "map": {"at": 197640, "to": "mm"},
8618 "name": "CP_ME_COHER_BASE_HI",
8619 "type_ref": "CP_COHER_BASE_HI"
8623 "map": {"at": 197644, "to": "mm"},
8624 "name": "CP_ME_COHER_STATUS",
8625 "type_ref": "CP_ME_COHER_STATUS"
8629 "map": {"at": 197888, "to": "mm"},
8630 "name": "RLC_GPM_PERF_COUNT_0",
8631 "type_ref": "RLC_GPM_PERF_COUNT_0"
8635 "map": {"at": 197892, "to": "mm"},
8636 "name": "RLC_GPM_PERF_COUNT_1",
8637 "type_ref": "RLC_GPM_PERF_COUNT_0"
8641 "map": {"at": 198656, "to": "mm"},
8642 "name": "GRBM_GFX_INDEX",
8643 "type_ref": "GRBM_GFX_INDEX"
8647 "map": {"at": 198912, "to": "mm"},
8648 "name": "VGT_ESGS_RING_SIZE_UMD",
8649 "type_ref": "VGT_ESGS_RING_SIZE_UMD"
8653 "map": {"at": 198916, "to": "mm"},
8654 "name": "VGT_GSVS_RING_SIZE_UMD",
8655 "type_ref": "VGT_ESGS_RING_SIZE_UMD"
8659 "map": {"at": 198920, "to": "mm"},
8660 "name": "VGT_PRIMITIVE_TYPE",
8661 "type_ref": "VGT_PRIMITIVE_TYPE"
8665 "map": {"at": 198924, "to": "mm"},
8666 "name": "VGT_INDEX_TYPE",
8667 "type_ref": "CP_INDEX_TYPE"
8671 "map": {"at": 198928, "to": "mm"},
8672 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0",
8673 "type_ref": "COMPUTE_DIM_X"
8677 "map": {"at": 198932, "to": "mm"},
8678 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1",
8679 "type_ref": "COMPUTE_DIM_X"
8683 "map": {"at": 198936, "to": "mm"},
8684 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2",
8685 "type_ref": "COMPUTE_DIM_X"
8689 "map": {"at": 198940, "to": "mm"},
8690 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3",
8691 "type_ref": "COMPUTE_DIM_X"
8695 "map": {"at": 198948, "to": "mm"},
8696 "name": "GE_MIN_VTX_INDX",
8697 "type_ref": "VGT_MIN_VTX_INDX"
8701 "map": {"at": 198952, "to": "mm"},
8702 "name": "GE_INDX_OFFSET",
8703 "type_ref": "VGT_INDX_OFFSET"
8707 "map": {"at": 198956, "to": "mm"},
8708 "name": "GE_MULTI_PRIM_IB_RESET_EN",
8709 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
8713 "map": {"at": 198960, "to": "mm"},
8714 "name": "VGT_NUM_INDICES",
8715 "type_ref": "VGT_DMA_SIZE"
8719 "map": {"at": 198964, "to": "mm"},
8720 "name": "VGT_NUM_INSTANCES",
8721 "type_ref": "VGT_DMA_NUM_INSTANCES"
8725 "map": {"at": 198968, "to": "mm"},
8726 "name": "VGT_TF_RING_SIZE_UMD",
8727 "type_ref": "VGT_TF_RING_SIZE_UMD"
8731 "map": {"at": 198972, "to": "mm"},
8732 "name": "VGT_HS_OFFCHIP_PARAM_UMD",
8733 "type_ref": "VGT_HS_OFFCHIP_PARAM_UMD"
8737 "map": {"at": 198976, "to": "mm"},
8738 "name": "VGT_TF_MEMORY_BASE_UMD",
8739 "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8743 "map": {"at": 198980, "to": "mm"},
8744 "name": "GE_DMA_FIRST_INDEX",
8745 "type_ref": "GE_DMA_FIRST_INDEX"
8749 "map": {"at": 198984, "to": "mm"},
8750 "name": "WD_POS_BUF_BASE",
8751 "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8755 "map": {"at": 198988, "to": "mm"},
8756 "name": "WD_POS_BUF_BASE_HI",
8757 "type_ref": "DB_Z_READ_BASE_HI"
8761 "map": {"at": 198992, "to": "mm"},
8762 "name": "WD_CNTL_SB_BUF_BASE",
8763 "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8767 "map": {"at": 198996, "to": "mm"},
8768 "name": "WD_CNTL_SB_BUF_BASE_HI",
8769 "type_ref": "DB_Z_READ_BASE_HI"
8773 "map": {"at": 199000, "to": "mm"},
8774 "name": "WD_INDEX_BUF_BASE",
8775 "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8779 "map": {"at": 199004, "to": "mm"},
8780 "name": "WD_INDEX_BUF_BASE_HI",
8781 "type_ref": "DB_Z_READ_BASE_HI"
8785 "map": {"at": 199008, "to": "mm"},
8786 "name": "IA_MULTI_VGT_PARAM_PIPED",
8787 "type_ref": "IA_MULTI_VGT_PARAM_PIPED"
8791 "map": {"at": 199012, "to": "mm"},
8792 "name": "GE_MAX_VTX_INDX",
8793 "type_ref": "VGT_MAX_VTX_INDX"
8797 "map": {"at": 199016, "to": "mm"},
8798 "name": "VGT_INSTANCE_BASE_ID",
8799 "type_ref": "VGT_INSTANCE_BASE_ID"
8803 "map": {"at": 199020, "to": "mm"},
8805 "type_ref": "GE_CNTL"
8809 "map": {"at": 199024, "to": "mm"},
8810 "name": "GE_USER_VGPR1",
8811 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8815 "map": {"at": 199028, "to": "mm"},
8816 "name": "GE_USER_VGPR2",
8817 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8821 "map": {"at": 199032, "to": "mm"},
8822 "name": "GE_USER_VGPR3",
8823 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8827 "map": {"at": 199036, "to": "mm"},
8828 "name": "GE_STEREO_CNTL",
8829 "type_ref": "GE_STEREO_CNTL"
8833 "map": {"at": 199040, "to": "mm"},
8834 "name": "GE_PC_ALLOC",
8835 "type_ref": "GE_PC_ALLOC"
8839 "map": {"at": 199044, "to": "mm"},
8840 "name": "VGT_TF_MEMORY_BASE_HI_UMD",
8841 "type_ref": "DB_Z_READ_BASE_HI"
8845 "map": {"at": 199048, "to": "mm"},
8846 "name": "GE_USER_VGPR_EN",
8847 "type_ref": "GE_USER_VGPR_EN"
8851 "map": {"at": 199168, "to": "mm"},
8852 "name": "PA_SU_LINE_STIPPLE_VALUE",
8853 "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
8857 "map": {"at": 199172, "to": "mm"},
8858 "name": "PA_SC_LINE_STIPPLE_STATE",
8859 "type_ref": "PA_SC_LINE_STIPPLE_STATE"
8863 "map": {"at": 199184, "to": "mm"},
8864 "name": "PA_SC_SCREEN_EXTENT_MIN_0",
8865 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8869 "map": {"at": 199188, "to": "mm"},
8870 "name": "PA_SC_SCREEN_EXTENT_MAX_0",
8871 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8875 "map": {"at": 199192, "to": "mm"},
8876 "name": "PA_SC_SCREEN_EXTENT_MIN_1",
8877 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8881 "map": {"at": 199212, "to": "mm"},
8882 "name": "PA_SC_SCREEN_EXTENT_MAX_1",
8883 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8887 "map": {"at": 199296, "to": "mm"},
8888 "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
8889 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8893 "map": {"at": 199300, "to": "mm"},
8894 "name": "PA_SC_P3D_TRAP_SCREEN_H",
8895 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8899 "map": {"at": 199304, "to": "mm"},
8900 "name": "PA_SC_P3D_TRAP_SCREEN_V",
8901 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8905 "map": {"at": 199308, "to": "mm"},
8906 "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
8907 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8911 "map": {"at": 199312, "to": "mm"},
8912 "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
8913 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8917 "map": {"at": 199328, "to": "mm"},
8918 "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
8919 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8923 "map": {"at": 199332, "to": "mm"},
8924 "name": "PA_SC_HP3D_TRAP_SCREEN_H",
8925 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8929 "map": {"at": 199336, "to": "mm"},
8930 "name": "PA_SC_HP3D_TRAP_SCREEN_V",
8931 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8935 "map": {"at": 199340, "to": "mm"},
8936 "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
8937 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8941 "map": {"at": 199344, "to": "mm"},
8942 "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
8943 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8947 "map": {"at": 199360, "to": "mm"},
8948 "name": "PA_SC_TRAP_SCREEN_HV_EN",
8949 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8953 "map": {"at": 199364, "to": "mm"},
8954 "name": "PA_SC_TRAP_SCREEN_H",
8955 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8959 "map": {"at": 199368, "to": "mm"},
8960 "name": "PA_SC_TRAP_SCREEN_V",
8961 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8965 "map": {"at": 199372, "to": "mm"},
8966 "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
8967 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8971 "map": {"at": 199376, "to": "mm"},
8972 "name": "PA_SC_TRAP_SCREEN_COUNT",
8973 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8977 "map": {"at": 199936, "to": "mm"},
8978 "name": "SQ_THREAD_TRACE_USERDATA_0",
8979 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8983 "map": {"at": 199940, "to": "mm"},
8984 "name": "SQ_THREAD_TRACE_USERDATA_1",
8985 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8989 "map": {"at": 199944, "to": "mm"},
8990 "name": "SQ_THREAD_TRACE_USERDATA_2",
8991 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8995 "map": {"at": 199948, "to": "mm"},
8996 "name": "SQ_THREAD_TRACE_USERDATA_3",
8997 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9001 "map": {"at": 199952, "to": "mm"},
9002 "name": "SQ_THREAD_TRACE_USERDATA_4",
9003 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9007 "map": {"at": 199956, "to": "mm"},
9008 "name": "SQ_THREAD_TRACE_USERDATA_5",
9009 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9013 "map": {"at": 199960, "to": "mm"},
9014 "name": "SQ_THREAD_TRACE_USERDATA_6",
9015 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9019 "map": {"at": 199964, "to": "mm"},
9020 "name": "SQ_THREAD_TRACE_USERDATA_7",
9021 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9025 "map": {"at": 199968, "to": "mm"},
9026 "name": "SQC_CACHES",
9027 "type_ref": "SQC_CACHES"
9031 "map": {"at": 199972, "to": "mm"},
9032 "name": "SQC_WRITEBACK",
9033 "type_ref": "SQC_WRITEBACK"
9037 "map": {"at": 200192, "to": "mm"},
9038 "name": "TA_CS_BC_BASE_ADDR",
9039 "type_ref": "TA_BC_BASE_ADDR"
9043 "map": {"at": 200196, "to": "mm"},
9044 "name": "TA_CS_BC_BASE_ADDR_HI",
9045 "type_ref": "TA_BC_BASE_ADDR_HI"
9049 "map": {"at": 200448, "to": "mm"},
9050 "name": "DB_OCCLUSION_COUNT0_LOW",
9051 "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9055 "map": {"at": 200452, "to": "mm"},
9056 "name": "DB_OCCLUSION_COUNT0_HI",
9057 "type_ref": "DB_OCCLUSION_COUNT0_HI"
9061 "map": {"at": 200456, "to": "mm"},
9062 "name": "DB_OCCLUSION_COUNT1_LOW",
9063 "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9067 "map": {"at": 200460, "to": "mm"},
9068 "name": "DB_OCCLUSION_COUNT1_HI",
9069 "type_ref": "DB_OCCLUSION_COUNT0_HI"
9073 "map": {"at": 200464, "to": "mm"},
9074 "name": "DB_OCCLUSION_COUNT2_LOW",
9075 "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9079 "map": {"at": 200468, "to": "mm"},
9080 "name": "DB_OCCLUSION_COUNT2_HI",
9081 "type_ref": "DB_OCCLUSION_COUNT0_HI"
9085 "map": {"at": 200472, "to": "mm"},
9086 "name": "DB_OCCLUSION_COUNT3_LOW",
9087 "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9091 "map": {"at": 200476, "to": "mm"},
9092 "name": "DB_OCCLUSION_COUNT3_HI",
9093 "type_ref": "DB_OCCLUSION_COUNT0_HI"
9097 "map": {"at": 200696, "to": "mm"},
9098 "name": "DB_ZPASS_COUNT_LOW",
9099 "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9103 "map": {"at": 200700, "to": "mm"},
9104 "name": "DB_ZPASS_COUNT_HI",
9105 "type_ref": "DB_OCCLUSION_COUNT0_HI"
9109 "map": {"at": 200704, "to": "mm"},
9110 "name": "GDS_RD_ADDR",
9111 "type_ref": "GDS_RD_ADDR"
9115 "map": {"at": 200708, "to": "mm"},
9116 "name": "GDS_RD_DATA",
9117 "type_ref": "GDS_RD_DATA"
9121 "map": {"at": 200712, "to": "mm"},
9122 "name": "GDS_RD_BURST_ADDR",
9123 "type_ref": "GDS_RD_BURST_ADDR"
9127 "map": {"at": 200716, "to": "mm"},
9128 "name": "GDS_RD_BURST_COUNT",
9129 "type_ref": "GDS_RD_BURST_COUNT"
9133 "map": {"at": 200720, "to": "mm"},
9134 "name": "GDS_RD_BURST_DATA",
9135 "type_ref": "GDS_RD_BURST_DATA"
9139 "map": {"at": 200724, "to": "mm"},
9140 "name": "GDS_WR_ADDR",
9141 "type_ref": "GDS_WR_ADDR"
9145 "map": {"at": 200728, "to": "mm"},
9146 "name": "GDS_WR_DATA",
9147 "type_ref": "GDS_WR_DATA"
9151 "map": {"at": 200732, "to": "mm"},
9152 "name": "GDS_WR_BURST_ADDR",
9153 "type_ref": "GDS_WR_ADDR"
9157 "map": {"at": 200736, "to": "mm"},
9158 "name": "GDS_WR_BURST_DATA",
9159 "type_ref": "GDS_WR_DATA"
9163 "map": {"at": 200740, "to": "mm"},
9164 "name": "GDS_WRITE_COMPLETE",
9165 "type_ref": "GDS_WRITE_COMPLETE"
9169 "map": {"at": 200744, "to": "mm"},
9170 "name": "GDS_ATOM_CNTL",
9171 "type_ref": "GDS_ATOM_CNTL"
9175 "map": {"at": 200748, "to": "mm"},
9176 "name": "GDS_ATOM_COMPLETE",
9177 "type_ref": "GDS_ATOM_COMPLETE"
9181 "map": {"at": 200752, "to": "mm"},
9182 "name": "GDS_ATOM_BASE",
9183 "type_ref": "GDS_ATOM_BASE"
9187 "map": {"at": 200756, "to": "mm"},
9188 "name": "GDS_ATOM_SIZE",
9189 "type_ref": "GDS_ATOM_SIZE"
9193 "map": {"at": 200760, "to": "mm"},
9194 "name": "GDS_ATOM_OFFSET0",
9195 "type_ref": "GDS_ATOM_OFFSET0"
9199 "map": {"at": 200764, "to": "mm"},
9200 "name": "GDS_ATOM_OFFSET1",
9201 "type_ref": "GDS_ATOM_OFFSET1"
9205 "map": {"at": 200768, "to": "mm"},
9206 "name": "GDS_ATOM_DST",
9207 "type_ref": "GDS_ATOM_DST"
9211 "map": {"at": 200772, "to": "mm"},
9212 "name": "GDS_ATOM_OP",
9213 "type_ref": "GDS_ATOM_OP"
9217 "map": {"at": 200776, "to": "mm"},
9218 "name": "GDS_ATOM_SRC0",
9219 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9223 "map": {"at": 200780, "to": "mm"},
9224 "name": "GDS_ATOM_SRC0_U",
9225 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9229 "map": {"at": 200784, "to": "mm"},
9230 "name": "GDS_ATOM_SRC1",
9231 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9235 "map": {"at": 200788, "to": "mm"},
9236 "name": "GDS_ATOM_SRC1_U",
9237 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9241 "map": {"at": 200792, "to": "mm"},
9242 "name": "GDS_ATOM_READ0",
9243 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9247 "map": {"at": 200796, "to": "mm"},
9248 "name": "GDS_ATOM_READ0_U",
9249 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9253 "map": {"at": 200800, "to": "mm"},
9254 "name": "GDS_ATOM_READ1",
9255 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9259 "map": {"at": 200804, "to": "mm"},
9260 "name": "GDS_ATOM_READ1_U",
9261 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9265 "map": {"at": 200808, "to": "mm"},
9266 "name": "GDS_GWS_RESOURCE_CNTL",
9267 "type_ref": "GDS_GWS_RESOURCE_CNTL"
9271 "map": {"at": 200812, "to": "mm"},
9272 "name": "GDS_GWS_RESOURCE",
9273 "type_ref": "GDS_GWS_RESOURCE"
9277 "map": {"at": 200816, "to": "mm"},
9278 "name": "GDS_GWS_RESOURCE_CNT",
9279 "type_ref": "GDS_GWS_RESOURCE_CNT"
9283 "map": {"at": 200820, "to": "mm"},
9284 "name": "GDS_OA_CNTL",
9285 "type_ref": "GDS_OA_CNTL"
9289 "map": {"at": 200824, "to": "mm"},
9290 "name": "GDS_OA_COUNTER",
9291 "type_ref": "GDS_OA_COUNTER"
9295 "map": {"at": 200828, "to": "mm"},
9296 "name": "GDS_OA_ADDRESS",
9297 "type_ref": "GDS_OA_ADDRESS"
9301 "map": {"at": 200832, "to": "mm"},
9302 "name": "GDS_OA_INCDEC",
9303 "type_ref": "GDS_OA_INCDEC"
9307 "map": {"at": 200836, "to": "mm"},
9308 "name": "GDS_OA_RING_SIZE",
9309 "type_ref": "GDS_OA_RING_SIZE"
9313 "map": {"at": 200960, "to": "mm"},
9314 "name": "SPI_CONFIG_CNTL_REMAP",
9315 "type_ref": "SPI_CONFIG_CNTL_REMAP"
9319 "map": {"at": 200964, "to": "mm"},
9320 "name": "SPI_CONFIG_CNTL_1_REMAP",
9321 "type_ref": "SPI_CONFIG_CNTL_REMAP"
9325 "map": {"at": 200968, "to": "mm"},
9326 "name": "SPI_CONFIG_CNTL_2_REMAP",
9327 "type_ref": "SPI_CONFIG_CNTL_REMAP"
9331 "map": {"at": 200972, "to": "mm"},
9332 "name": "SPI_WAVE_LIMIT_CNTL_REMAP",
9333 "type_ref": "SPI_CONFIG_CNTL_REMAP"
9337 "map": {"at": 212992, "to": "mm"},
9338 "name": "CPG_PERFCOUNTER1_LO",
9339 "type_ref": "CPG_PERFCOUNTER1_LO"
9343 "map": {"at": 212996, "to": "mm"},
9344 "name": "CPG_PERFCOUNTER1_HI",
9345 "type_ref": "CPG_PERFCOUNTER1_HI"
9349 "map": {"at": 213000, "to": "mm"},
9350 "name": "CPG_PERFCOUNTER0_LO",
9351 "type_ref": "CPG_PERFCOUNTER1_LO"
9355 "map": {"at": 213004, "to": "mm"},
9356 "name": "CPG_PERFCOUNTER0_HI",
9357 "type_ref": "CPG_PERFCOUNTER1_HI"
9361 "map": {"at": 213008, "to": "mm"},
9362 "name": "CPC_PERFCOUNTER1_LO",
9363 "type_ref": "CPG_PERFCOUNTER1_LO"
9367 "map": {"at": 213012, "to": "mm"},
9368 "name": "CPC_PERFCOUNTER1_HI",
9369 "type_ref": "CPG_PERFCOUNTER1_HI"
9373 "map": {"at": 213016, "to": "mm"},
9374 "name": "CPC_PERFCOUNTER0_LO",
9375 "type_ref": "CPG_PERFCOUNTER1_LO"
9379 "map": {"at": 213020, "to": "mm"},
9380 "name": "CPC_PERFCOUNTER0_HI",
9381 "type_ref": "CPG_PERFCOUNTER1_HI"
9385 "map": {"at": 213024, "to": "mm"},
9386 "name": "CPF_PERFCOUNTER1_LO",
9387 "type_ref": "CPG_PERFCOUNTER1_LO"
9391 "map": {"at": 213028, "to": "mm"},
9392 "name": "CPF_PERFCOUNTER1_HI",
9393 "type_ref": "CPG_PERFCOUNTER1_HI"
9397 "map": {"at": 213032, "to": "mm"},
9398 "name": "CPF_PERFCOUNTER0_LO",
9399 "type_ref": "CPG_PERFCOUNTER1_LO"
9403 "map": {"at": 213036, "to": "mm"},
9404 "name": "CPF_PERFCOUNTER0_HI",
9405 "type_ref": "CPG_PERFCOUNTER1_HI"
9409 "map": {"at": 213040, "to": "mm"},
9410 "name": "CPF_LATENCY_STATS_DATA",
9411 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9415 "map": {"at": 213044, "to": "mm"},
9416 "name": "CPG_LATENCY_STATS_DATA",
9417 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9421 "map": {"at": 213048, "to": "mm"},
9422 "name": "CPC_LATENCY_STATS_DATA",
9423 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9427 "map": {"at": 213248, "to": "mm"},
9428 "name": "GRBM_PERFCOUNTER0_LO",
9429 "type_ref": "CPG_PERFCOUNTER1_LO"
9433 "map": {"at": 213252, "to": "mm"},
9434 "name": "GRBM_PERFCOUNTER0_HI",
9435 "type_ref": "CPG_PERFCOUNTER1_HI"
9439 "map": {"at": 213260, "to": "mm"},
9440 "name": "GRBM_PERFCOUNTER1_LO",
9441 "type_ref": "CPG_PERFCOUNTER1_LO"
9445 "map": {"at": 213264, "to": "mm"},
9446 "name": "GRBM_PERFCOUNTER1_HI",
9447 "type_ref": "CPG_PERFCOUNTER1_HI"
9451 "map": {"at": 213268, "to": "mm"},
9452 "name": "GRBM_SE0_PERFCOUNTER_LO",
9453 "type_ref": "CPG_PERFCOUNTER1_LO"
9457 "map": {"at": 213272, "to": "mm"},
9458 "name": "GRBM_SE0_PERFCOUNTER_HI",
9459 "type_ref": "CPG_PERFCOUNTER1_HI"
9463 "map": {"at": 213276, "to": "mm"},
9464 "name": "GRBM_SE1_PERFCOUNTER_LO",
9465 "type_ref": "CPG_PERFCOUNTER1_LO"
9469 "map": {"at": 213280, "to": "mm"},
9470 "name": "GRBM_SE1_PERFCOUNTER_HI",
9471 "type_ref": "CPG_PERFCOUNTER1_HI"
9475 "map": {"at": 213284, "to": "mm"},
9476 "name": "GRBM_SE2_PERFCOUNTER_LO",
9477 "type_ref": "CPG_PERFCOUNTER1_LO"
9481 "map": {"at": 213288, "to": "mm"},
9482 "name": "GRBM_SE2_PERFCOUNTER_HI",
9483 "type_ref": "CPG_PERFCOUNTER1_HI"
9487 "map": {"at": 213292, "to": "mm"},
9488 "name": "GRBM_SE3_PERFCOUNTER_LO",
9489 "type_ref": "CPG_PERFCOUNTER1_LO"
9493 "map": {"at": 213296, "to": "mm"},
9494 "name": "GRBM_SE3_PERFCOUNTER_HI",
9495 "type_ref": "CPG_PERFCOUNTER1_HI"
9499 "map": {"at": 213504, "to": "mm"},
9500 "name": "GE_PERFCOUNTER0_LO",
9501 "type_ref": "CPG_PERFCOUNTER1_LO"
9505 "map": {"at": 213508, "to": "mm"},
9506 "name": "GE_PERFCOUNTER0_HI",
9507 "type_ref": "CPG_PERFCOUNTER1_HI"
9511 "map": {"at": 213512, "to": "mm"},
9512 "name": "GE_PERFCOUNTER1_LO",
9513 "type_ref": "CPG_PERFCOUNTER1_LO"
9517 "map": {"at": 213516, "to": "mm"},
9518 "name": "GE_PERFCOUNTER1_HI",
9519 "type_ref": "CPG_PERFCOUNTER1_HI"
9523 "map": {"at": 213520, "to": "mm"},
9524 "name": "GE_PERFCOUNTER2_LO",
9525 "type_ref": "CPG_PERFCOUNTER1_LO"
9529 "map": {"at": 213524, "to": "mm"},
9530 "name": "GE_PERFCOUNTER2_HI",
9531 "type_ref": "CPG_PERFCOUNTER1_HI"
9535 "map": {"at": 213528, "to": "mm"},
9536 "name": "GE_PERFCOUNTER3_LO",
9537 "type_ref": "CPG_PERFCOUNTER1_LO"
9541 "map": {"at": 213532, "to": "mm"},
9542 "name": "GE_PERFCOUNTER3_HI",
9543 "type_ref": "CPG_PERFCOUNTER1_HI"
9547 "map": {"at": 213536, "to": "mm"},
9548 "name": "GE_PERFCOUNTER4_LO",
9549 "type_ref": "CPG_PERFCOUNTER1_LO"
9553 "map": {"at": 213540, "to": "mm"},
9554 "name": "GE_PERFCOUNTER4_HI",
9555 "type_ref": "CPG_PERFCOUNTER1_HI"
9559 "map": {"at": 213544, "to": "mm"},
9560 "name": "GE_PERFCOUNTER5_LO",
9561 "type_ref": "CPG_PERFCOUNTER1_LO"
9565 "map": {"at": 213548, "to": "mm"},
9566 "name": "GE_PERFCOUNTER5_HI",
9567 "type_ref": "CPG_PERFCOUNTER1_HI"
9571 "map": {"at": 213552, "to": "mm"},
9572 "name": "GE_PERFCOUNTER6_LO",
9573 "type_ref": "CPG_PERFCOUNTER1_LO"
9577 "map": {"at": 213556, "to": "mm"},
9578 "name": "GE_PERFCOUNTER6_HI",
9579 "type_ref": "CPG_PERFCOUNTER1_HI"
9583 "map": {"at": 213560, "to": "mm"},
9584 "name": "GE_PERFCOUNTER7_LO",
9585 "type_ref": "CPG_PERFCOUNTER1_LO"
9589 "map": {"at": 213564, "to": "mm"},
9590 "name": "GE_PERFCOUNTER7_HI",
9591 "type_ref": "CPG_PERFCOUNTER1_HI"
9595 "map": {"at": 213568, "to": "mm"},
9596 "name": "GE_PERFCOUNTER8_LO",
9597 "type_ref": "CPG_PERFCOUNTER1_LO"
9601 "map": {"at": 213572, "to": "mm"},
9602 "name": "GE_PERFCOUNTER8_HI",
9603 "type_ref": "CPG_PERFCOUNTER1_HI"
9607 "map": {"at": 213576, "to": "mm"},
9608 "name": "GE_PERFCOUNTER9_LO",
9609 "type_ref": "CPG_PERFCOUNTER1_LO"
9613 "map": {"at": 213580, "to": "mm"},
9614 "name": "GE_PERFCOUNTER9_HI",
9615 "type_ref": "CPG_PERFCOUNTER1_HI"
9619 "map": {"at": 213584, "to": "mm"},
9620 "name": "GE_PERFCOUNTER10_LO",
9621 "type_ref": "CPG_PERFCOUNTER1_LO"
9625 "map": {"at": 213588, "to": "mm"},
9626 "name": "GE_PERFCOUNTER10_HI",
9627 "type_ref": "CPG_PERFCOUNTER1_HI"
9631 "map": {"at": 213592, "to": "mm"},
9632 "name": "GE_PERFCOUNTER11_LO",
9633 "type_ref": "CPG_PERFCOUNTER1_LO"
9637 "map": {"at": 213596, "to": "mm"},
9638 "name": "GE_PERFCOUNTER11_HI",
9639 "type_ref": "CPG_PERFCOUNTER1_HI"
9643 "map": {"at": 214016, "to": "mm"},
9644 "name": "PA_SU_PERFCOUNTER0_LO",
9645 "type_ref": "CPG_PERFCOUNTER1_LO"
9649 "map": {"at": 214020, "to": "mm"},
9650 "name": "PA_SU_PERFCOUNTER0_HI",
9651 "type_ref": "PA_SU_PERFCOUNTER0_HI"
9655 "map": {"at": 214024, "to": "mm"},
9656 "name": "PA_SU_PERFCOUNTER1_LO",
9657 "type_ref": "CPG_PERFCOUNTER1_LO"
9661 "map": {"at": 214028, "to": "mm"},
9662 "name": "PA_SU_PERFCOUNTER1_HI",
9663 "type_ref": "PA_SU_PERFCOUNTER0_HI"
9667 "map": {"at": 214032, "to": "mm"},
9668 "name": "PA_SU_PERFCOUNTER2_LO",
9669 "type_ref": "CPG_PERFCOUNTER1_LO"
9673 "map": {"at": 214036, "to": "mm"},
9674 "name": "PA_SU_PERFCOUNTER2_HI",
9675 "type_ref": "PA_SU_PERFCOUNTER0_HI"
9679 "map": {"at": 214040, "to": "mm"},
9680 "name": "PA_SU_PERFCOUNTER3_LO",
9681 "type_ref": "CPG_PERFCOUNTER1_LO"
9685 "map": {"at": 214044, "to": "mm"},
9686 "name": "PA_SU_PERFCOUNTER3_HI",
9687 "type_ref": "PA_SU_PERFCOUNTER0_HI"
9691 "map": {"at": 214272, "to": "mm"},
9692 "name": "PA_SC_PERFCOUNTER0_LO",
9693 "type_ref": "CPG_PERFCOUNTER1_LO"
9697 "map": {"at": 214276, "to": "mm"},
9698 "name": "PA_SC_PERFCOUNTER0_HI",
9699 "type_ref": "CPG_PERFCOUNTER1_HI"
9703 "map": {"at": 214280, "to": "mm"},
9704 "name": "PA_SC_PERFCOUNTER1_LO",
9705 "type_ref": "CPG_PERFCOUNTER1_LO"
9709 "map": {"at": 214284, "to": "mm"},
9710 "name": "PA_SC_PERFCOUNTER1_HI",
9711 "type_ref": "CPG_PERFCOUNTER1_HI"
9715 "map": {"at": 214288, "to": "mm"},
9716 "name": "PA_SC_PERFCOUNTER2_LO",
9717 "type_ref": "CPG_PERFCOUNTER1_LO"
9721 "map": {"at": 214292, "to": "mm"},
9722 "name": "PA_SC_PERFCOUNTER2_HI",
9723 "type_ref": "CPG_PERFCOUNTER1_HI"
9727 "map": {"at": 214296, "to": "mm"},
9728 "name": "PA_SC_PERFCOUNTER3_LO",
9729 "type_ref": "CPG_PERFCOUNTER1_LO"
9733 "map": {"at": 214300, "to": "mm"},
9734 "name": "PA_SC_PERFCOUNTER3_HI",
9735 "type_ref": "CPG_PERFCOUNTER1_HI"
9739 "map": {"at": 214304, "to": "mm"},
9740 "name": "PA_SC_PERFCOUNTER4_LO",
9741 "type_ref": "CPG_PERFCOUNTER1_LO"
9745 "map": {"at": 214308, "to": "mm"},
9746 "name": "PA_SC_PERFCOUNTER4_HI",
9747 "type_ref": "CPG_PERFCOUNTER1_HI"
9751 "map": {"at": 214312, "to": "mm"},
9752 "name": "PA_SC_PERFCOUNTER5_LO",
9753 "type_ref": "CPG_PERFCOUNTER1_LO"
9757 "map": {"at": 214316, "to": "mm"},
9758 "name": "PA_SC_PERFCOUNTER5_HI",
9759 "type_ref": "CPG_PERFCOUNTER1_HI"
9763 "map": {"at": 214320, "to": "mm"},
9764 "name": "PA_SC_PERFCOUNTER6_LO",
9765 "type_ref": "CPG_PERFCOUNTER1_LO"
9769 "map": {"at": 214324, "to": "mm"},
9770 "name": "PA_SC_PERFCOUNTER6_HI",
9771 "type_ref": "CPG_PERFCOUNTER1_HI"
9775 "map": {"at": 214328, "to": "mm"},
9776 "name": "PA_SC_PERFCOUNTER7_LO",
9777 "type_ref": "CPG_PERFCOUNTER1_LO"
9781 "map": {"at": 214332, "to": "mm"},
9782 "name": "PA_SC_PERFCOUNTER7_HI",
9783 "type_ref": "CPG_PERFCOUNTER1_HI"
9787 "map": {"at": 214528, "to": "mm"},
9788 "name": "SPI_PERFCOUNTER0_HI",
9789 "type_ref": "CPG_PERFCOUNTER1_HI"
9793 "map": {"at": 214532, "to": "mm"},
9794 "name": "SPI_PERFCOUNTER0_LO",
9795 "type_ref": "CPG_PERFCOUNTER1_LO"
9799 "map": {"at": 214536, "to": "mm"},
9800 "name": "SPI_PERFCOUNTER1_HI",
9801 "type_ref": "CPG_PERFCOUNTER1_HI"
9805 "map": {"at": 214540, "to": "mm"},
9806 "name": "SPI_PERFCOUNTER1_LO",
9807 "type_ref": "CPG_PERFCOUNTER1_LO"
9811 "map": {"at": 214544, "to": "mm"},
9812 "name": "SPI_PERFCOUNTER2_HI",
9813 "type_ref": "CPG_PERFCOUNTER1_HI"
9817 "map": {"at": 214548, "to": "mm"},
9818 "name": "SPI_PERFCOUNTER2_LO",
9819 "type_ref": "CPG_PERFCOUNTER1_LO"
9823 "map": {"at": 214552, "to": "mm"},
9824 "name": "SPI_PERFCOUNTER3_HI",
9825 "type_ref": "CPG_PERFCOUNTER1_HI"
9829 "map": {"at": 214556, "to": "mm"},
9830 "name": "SPI_PERFCOUNTER3_LO",
9831 "type_ref": "CPG_PERFCOUNTER1_LO"
9835 "map": {"at": 214560, "to": "mm"},
9836 "name": "SPI_PERFCOUNTER4_HI",
9837 "type_ref": "CPG_PERFCOUNTER1_HI"
9841 "map": {"at": 214564, "to": "mm"},
9842 "name": "SPI_PERFCOUNTER4_LO",
9843 "type_ref": "CPG_PERFCOUNTER1_LO"
9847 "map": {"at": 214568, "to": "mm"},
9848 "name": "SPI_PERFCOUNTER5_HI",
9849 "type_ref": "CPG_PERFCOUNTER1_HI"
9853 "map": {"at": 214572, "to": "mm"},
9854 "name": "SPI_PERFCOUNTER5_LO",
9855 "type_ref": "CPG_PERFCOUNTER1_LO"
9859 "map": {"at": 214784, "to": "mm"},
9860 "name": "SQ_PERFCOUNTER0_LO",
9861 "type_ref": "CPG_PERFCOUNTER1_LO"
9865 "map": {"at": 214788, "to": "mm"},
9866 "name": "SQ_PERFCOUNTER0_HI",
9867 "type_ref": "CPG_PERFCOUNTER1_HI"
9871 "map": {"at": 214792, "to": "mm"},
9872 "name": "SQ_PERFCOUNTER1_LO",
9873 "type_ref": "CPG_PERFCOUNTER1_LO"
9877 "map": {"at": 214796, "to": "mm"},
9878 "name": "SQ_PERFCOUNTER1_HI",
9879 "type_ref": "CPG_PERFCOUNTER1_HI"
9883 "map": {"at": 214800, "to": "mm"},
9884 "name": "SQ_PERFCOUNTER2_LO",
9885 "type_ref": "CPG_PERFCOUNTER1_LO"
9889 "map": {"at": 214804, "to": "mm"},
9890 "name": "SQ_PERFCOUNTER2_HI",
9891 "type_ref": "CPG_PERFCOUNTER1_HI"
9895 "map": {"at": 214808, "to": "mm"},
9896 "name": "SQ_PERFCOUNTER3_LO",
9897 "type_ref": "CPG_PERFCOUNTER1_LO"
9901 "map": {"at": 214812, "to": "mm"},
9902 "name": "SQ_PERFCOUNTER3_HI",
9903 "type_ref": "CPG_PERFCOUNTER1_HI"
9907 "map": {"at": 214816, "to": "mm"},
9908 "name": "SQ_PERFCOUNTER4_LO",
9909 "type_ref": "CPG_PERFCOUNTER1_LO"
9913 "map": {"at": 214820, "to": "mm"},
9914 "name": "SQ_PERFCOUNTER4_HI",
9915 "type_ref": "CPG_PERFCOUNTER1_HI"
9919 "map": {"at": 214824, "to": "mm"},
9920 "name": "SQ_PERFCOUNTER5_LO",
9921 "type_ref": "CPG_PERFCOUNTER1_LO"
9925 "map": {"at": 214828, "to": "mm"},
9926 "name": "SQ_PERFCOUNTER5_HI",
9927 "type_ref": "CPG_PERFCOUNTER1_HI"
9931 "map": {"at": 214832, "to": "mm"},
9932 "name": "SQ_PERFCOUNTER6_LO",
9933 "type_ref": "CPG_PERFCOUNTER1_LO"
9937 "map": {"at": 214836, "to": "mm"},
9938 "name": "SQ_PERFCOUNTER6_HI",
9939 "type_ref": "CPG_PERFCOUNTER1_HI"
9943 "map": {"at": 214840, "to": "mm"},
9944 "name": "SQ_PERFCOUNTER7_LO",
9945 "type_ref": "CPG_PERFCOUNTER1_LO"
9949 "map": {"at": 214844, "to": "mm"},
9950 "name": "SQ_PERFCOUNTER7_HI",
9951 "type_ref": "CPG_PERFCOUNTER1_HI"
9955 "map": {"at": 214848, "to": "mm"},
9956 "name": "SQ_PERFCOUNTER8_LO",
9957 "type_ref": "CPG_PERFCOUNTER1_LO"
9961 "map": {"at": 214852, "to": "mm"},
9962 "name": "SQ_PERFCOUNTER8_HI",
9963 "type_ref": "CPG_PERFCOUNTER1_HI"
9967 "map": {"at": 214856, "to": "mm"},
9968 "name": "SQ_PERFCOUNTER9_LO",
9969 "type_ref": "CPG_PERFCOUNTER1_LO"
9973 "map": {"at": 214860, "to": "mm"},
9974 "name": "SQ_PERFCOUNTER9_HI",
9975 "type_ref": "CPG_PERFCOUNTER1_HI"
9979 "map": {"at": 214864, "to": "mm"},
9980 "name": "SQ_PERFCOUNTER10_LO",
9981 "type_ref": "CPG_PERFCOUNTER1_LO"
9985 "map": {"at": 214868, "to": "mm"},
9986 "name": "SQ_PERFCOUNTER10_HI",
9987 "type_ref": "CPG_PERFCOUNTER1_HI"
9991 "map": {"at": 214872, "to": "mm"},
9992 "name": "SQ_PERFCOUNTER11_LO",
9993 "type_ref": "CPG_PERFCOUNTER1_LO"
9997 "map": {"at": 214876, "to": "mm"},
9998 "name": "SQ_PERFCOUNTER11_HI",
9999 "type_ref": "CPG_PERFCOUNTER1_HI"
10002 "chips": ["gfx10"],
10003 "map": {"at": 214880, "to": "mm"},
10004 "name": "SQ_PERFCOUNTER12_LO",
10005 "type_ref": "CPG_PERFCOUNTER1_LO"
10008 "chips": ["gfx10"],
10009 "map": {"at": 214884, "to": "mm"},
10010 "name": "SQ_PERFCOUNTER12_HI",
10011 "type_ref": "CPG_PERFCOUNTER1_HI"
10014 "chips": ["gfx10"],
10015 "map": {"at": 214888, "to": "mm"},
10016 "name": "SQ_PERFCOUNTER13_LO",
10017 "type_ref": "CPG_PERFCOUNTER1_LO"
10020 "chips": ["gfx10"],
10021 "map": {"at": 214892, "to": "mm"},
10022 "name": "SQ_PERFCOUNTER13_HI",
10023 "type_ref": "CPG_PERFCOUNTER1_HI"
10026 "chips": ["gfx10"],
10027 "map": {"at": 214896, "to": "mm"},
10028 "name": "SQ_PERFCOUNTER14_LO",
10029 "type_ref": "CPG_PERFCOUNTER1_LO"
10032 "chips": ["gfx10"],
10033 "map": {"at": 214900, "to": "mm"},
10034 "name": "SQ_PERFCOUNTER14_HI",
10035 "type_ref": "CPG_PERFCOUNTER1_HI"
10038 "chips": ["gfx10"],
10039 "map": {"at": 214904, "to": "mm"},
10040 "name": "SQ_PERFCOUNTER15_LO",
10041 "type_ref": "CPG_PERFCOUNTER1_LO"
10044 "chips": ["gfx10"],
10045 "map": {"at": 214908, "to": "mm"},
10046 "name": "SQ_PERFCOUNTER15_HI",
10047 "type_ref": "CPG_PERFCOUNTER1_HI"
10050 "chips": ["gfx10"],
10051 "map": {"at": 215296, "to": "mm"},
10052 "name": "SX_PERFCOUNTER0_LO",
10053 "type_ref": "CPG_PERFCOUNTER1_LO"
10056 "chips": ["gfx10"],
10057 "map": {"at": 215300, "to": "mm"},
10058 "name": "SX_PERFCOUNTER0_HI",
10059 "type_ref": "CPG_PERFCOUNTER1_HI"
10062 "chips": ["gfx10"],
10063 "map": {"at": 215304, "to": "mm"},
10064 "name": "SX_PERFCOUNTER1_LO",
10065 "type_ref": "CPG_PERFCOUNTER1_LO"
10068 "chips": ["gfx10"],
10069 "map": {"at": 215308, "to": "mm"},
10070 "name": "SX_PERFCOUNTER1_HI",
10071 "type_ref": "CPG_PERFCOUNTER1_HI"
10074 "chips": ["gfx10"],
10075 "map": {"at": 215312, "to": "mm"},
10076 "name": "SX_PERFCOUNTER2_LO",
10077 "type_ref": "CPG_PERFCOUNTER1_LO"
10080 "chips": ["gfx10"],
10081 "map": {"at": 215316, "to": "mm"},
10082 "name": "SX_PERFCOUNTER2_HI",
10083 "type_ref": "CPG_PERFCOUNTER1_HI"
10086 "chips": ["gfx10"],
10087 "map": {"at": 215320, "to": "mm"},
10088 "name": "SX_PERFCOUNTER3_LO",
10089 "type_ref": "CPG_PERFCOUNTER1_LO"
10092 "chips": ["gfx10"],
10093 "map": {"at": 215324, "to": "mm"},
10094 "name": "SX_PERFCOUNTER3_HI",
10095 "type_ref": "CPG_PERFCOUNTER1_HI"
10098 "chips": ["gfx10"],
10099 "map": {"at": 215424, "to": "mm"},
10100 "name": "GCEA_PERFCOUNTER2_LO",
10101 "type_ref": "CPG_PERFCOUNTER1_LO"
10104 "chips": ["gfx10"],
10105 "map": {"at": 215428, "to": "mm"},
10106 "name": "GCEA_PERFCOUNTER2_HI",
10107 "type_ref": "CPG_PERFCOUNTER1_HI"
10110 "chips": ["gfx10"],
10111 "map": {"at": 215552, "to": "mm"},
10112 "name": "GDS_PERFCOUNTER0_LO",
10113 "type_ref": "CPG_PERFCOUNTER1_LO"
10116 "chips": ["gfx10"],
10117 "map": {"at": 215556, "to": "mm"},
10118 "name": "GDS_PERFCOUNTER0_HI",
10119 "type_ref": "CPG_PERFCOUNTER1_HI"
10122 "chips": ["gfx10"],
10123 "map": {"at": 215560, "to": "mm"},
10124 "name": "GDS_PERFCOUNTER1_LO",
10125 "type_ref": "CPG_PERFCOUNTER1_LO"
10128 "chips": ["gfx10"],
10129 "map": {"at": 215564, "to": "mm"},
10130 "name": "GDS_PERFCOUNTER1_HI",
10131 "type_ref": "CPG_PERFCOUNTER1_HI"
10134 "chips": ["gfx10"],
10135 "map": {"at": 215568, "to": "mm"},
10136 "name": "GDS_PERFCOUNTER2_LO",
10137 "type_ref": "CPG_PERFCOUNTER1_LO"
10140 "chips": ["gfx10"],
10141 "map": {"at": 215572, "to": "mm"},
10142 "name": "GDS_PERFCOUNTER2_HI",
10143 "type_ref": "CPG_PERFCOUNTER1_HI"
10146 "chips": ["gfx10"],
10147 "map": {"at": 215576, "to": "mm"},
10148 "name": "GDS_PERFCOUNTER3_LO",
10149 "type_ref": "CPG_PERFCOUNTER1_LO"
10152 "chips": ["gfx10"],
10153 "map": {"at": 215580, "to": "mm"},
10154 "name": "GDS_PERFCOUNTER3_HI",
10155 "type_ref": "CPG_PERFCOUNTER1_HI"
10158 "chips": ["gfx10"],
10159 "map": {"at": 215808, "to": "mm"},
10160 "name": "TA_PERFCOUNTER0_LO",
10161 "type_ref": "CPG_PERFCOUNTER1_LO"
10164 "chips": ["gfx10"],
10165 "map": {"at": 215812, "to": "mm"},
10166 "name": "TA_PERFCOUNTER0_HI",
10167 "type_ref": "CPG_PERFCOUNTER1_HI"
10170 "chips": ["gfx10"],
10171 "map": {"at": 215816, "to": "mm"},
10172 "name": "TA_PERFCOUNTER1_LO",
10173 "type_ref": "CPG_PERFCOUNTER1_LO"
10176 "chips": ["gfx10"],
10177 "map": {"at": 215820, "to": "mm"},
10178 "name": "TA_PERFCOUNTER1_HI",
10179 "type_ref": "CPG_PERFCOUNTER1_HI"
10182 "chips": ["gfx10"],
10183 "map": {"at": 216064, "to": "mm"},
10184 "name": "TD_PERFCOUNTER0_LO",
10185 "type_ref": "CPG_PERFCOUNTER1_LO"
10188 "chips": ["gfx10"],
10189 "map": {"at": 216068, "to": "mm"},
10190 "name": "TD_PERFCOUNTER0_HI",
10191 "type_ref": "CPG_PERFCOUNTER1_HI"
10194 "chips": ["gfx10"],
10195 "map": {"at": 216072, "to": "mm"},
10196 "name": "TD_PERFCOUNTER1_LO",
10197 "type_ref": "CPG_PERFCOUNTER1_LO"
10200 "chips": ["gfx10"],
10201 "map": {"at": 216076, "to": "mm"},
10202 "name": "TD_PERFCOUNTER1_HI",
10203 "type_ref": "CPG_PERFCOUNTER1_HI"
10206 "chips": ["gfx10"],
10207 "map": {"at": 216320, "to": "mm"},
10208 "name": "TCP_PERFCOUNTER0_LO",
10209 "type_ref": "CPG_PERFCOUNTER1_LO"
10212 "chips": ["gfx10"],
10213 "map": {"at": 216324, "to": "mm"},
10214 "name": "TCP_PERFCOUNTER0_HI",
10215 "type_ref": "CPG_PERFCOUNTER1_HI"
10218 "chips": ["gfx10"],
10219 "map": {"at": 216328, "to": "mm"},
10220 "name": "TCP_PERFCOUNTER1_LO",
10221 "type_ref": "CPG_PERFCOUNTER1_LO"
10224 "chips": ["gfx10"],
10225 "map": {"at": 216332, "to": "mm"},
10226 "name": "TCP_PERFCOUNTER1_HI",
10227 "type_ref": "CPG_PERFCOUNTER1_HI"
10230 "chips": ["gfx10"],
10231 "map": {"at": 216336, "to": "mm"},
10232 "name": "TCP_PERFCOUNTER2_LO",
10233 "type_ref": "CPG_PERFCOUNTER1_LO"
10236 "chips": ["gfx10"],
10237 "map": {"at": 216340, "to": "mm"},
10238 "name": "TCP_PERFCOUNTER2_HI",
10239 "type_ref": "CPG_PERFCOUNTER1_HI"
10242 "chips": ["gfx10"],
10243 "map": {"at": 216344, "to": "mm"},
10244 "name": "TCP_PERFCOUNTER3_LO",
10245 "type_ref": "CPG_PERFCOUNTER1_LO"
10248 "chips": ["gfx10"],
10249 "map": {"at": 216348, "to": "mm"},
10250 "name": "TCP_PERFCOUNTER3_HI",
10251 "type_ref": "CPG_PERFCOUNTER1_HI"
10254 "chips": ["gfx10"],
10255 "map": {"at": 216576, "to": "mm"},
10256 "name": "GL2C_PERFCOUNTER0_LO",
10257 "type_ref": "CPG_PERFCOUNTER1_LO"
10260 "chips": ["gfx10"],
10261 "map": {"at": 216580, "to": "mm"},
10262 "name": "GL2C_PERFCOUNTER0_HI",
10263 "type_ref": "CPG_PERFCOUNTER1_HI"
10266 "chips": ["gfx10"],
10267 "map": {"at": 216584, "to": "mm"},
10268 "name": "GL2C_PERFCOUNTER1_LO",
10269 "type_ref": "CPG_PERFCOUNTER1_LO"
10272 "chips": ["gfx10"],
10273 "map": {"at": 216588, "to": "mm"},
10274 "name": "GL2C_PERFCOUNTER1_HI",
10275 "type_ref": "CPG_PERFCOUNTER1_HI"
10278 "chips": ["gfx10"],
10279 "map": {"at": 216592, "to": "mm"},
10280 "name": "GL2C_PERFCOUNTER2_LO",
10281 "type_ref": "CPG_PERFCOUNTER1_LO"
10284 "chips": ["gfx10"],
10285 "map": {"at": 216596, "to": "mm"},
10286 "name": "GL2C_PERFCOUNTER2_HI",
10287 "type_ref": "CPG_PERFCOUNTER1_HI"
10290 "chips": ["gfx10"],
10291 "map": {"at": 216600, "to": "mm"},
10292 "name": "GL2C_PERFCOUNTER3_LO",
10293 "type_ref": "CPG_PERFCOUNTER1_LO"
10296 "chips": ["gfx10"],
10297 "map": {"at": 216604, "to": "mm"},
10298 "name": "GL2C_PERFCOUNTER3_HI",
10299 "type_ref": "CPG_PERFCOUNTER1_HI"
10302 "chips": ["gfx10"],
10303 "map": {"at": 216640, "to": "mm"},
10304 "name": "GL2A_PERFCOUNTER0_LO",
10305 "type_ref": "CPG_PERFCOUNTER1_LO"
10308 "chips": ["gfx10"],
10309 "map": {"at": 216644, "to": "mm"},
10310 "name": "GL2A_PERFCOUNTER0_HI",
10311 "type_ref": "CPG_PERFCOUNTER1_HI"
10314 "chips": ["gfx10"],
10315 "map": {"at": 216648, "to": "mm"},
10316 "name": "GL2A_PERFCOUNTER1_LO",
10317 "type_ref": "CPG_PERFCOUNTER1_LO"
10320 "chips": ["gfx10"],
10321 "map": {"at": 216652, "to": "mm"},
10322 "name": "GL2A_PERFCOUNTER1_HI",
10323 "type_ref": "CPG_PERFCOUNTER1_HI"
10326 "chips": ["gfx10"],
10327 "map": {"at": 216656, "to": "mm"},
10328 "name": "GL2A_PERFCOUNTER2_LO",
10329 "type_ref": "CPG_PERFCOUNTER1_LO"
10332 "chips": ["gfx10"],
10333 "map": {"at": 216660, "to": "mm"},
10334 "name": "GL2A_PERFCOUNTER2_HI",
10335 "type_ref": "CPG_PERFCOUNTER1_HI"
10338 "chips": ["gfx10"],
10339 "map": {"at": 216664, "to": "mm"},
10340 "name": "GL2A_PERFCOUNTER3_LO",
10341 "type_ref": "CPG_PERFCOUNTER1_LO"
10344 "chips": ["gfx10"],
10345 "map": {"at": 216668, "to": "mm"},
10346 "name": "GL2A_PERFCOUNTER3_HI",
10347 "type_ref": "CPG_PERFCOUNTER1_HI"
10350 "chips": ["gfx10"],
10351 "map": {"at": 216704, "to": "mm"},
10352 "name": "GL1C_PERFCOUNTER0_LO",
10353 "type_ref": "CPG_PERFCOUNTER1_LO"
10356 "chips": ["gfx10"],
10357 "map": {"at": 216708, "to": "mm"},
10358 "name": "GL1C_PERFCOUNTER0_HI",
10359 "type_ref": "CPG_PERFCOUNTER1_HI"
10362 "chips": ["gfx10"],
10363 "map": {"at": 216712, "to": "mm"},
10364 "name": "GL1C_PERFCOUNTER1_LO",
10365 "type_ref": "CPG_PERFCOUNTER1_LO"
10368 "chips": ["gfx10"],
10369 "map": {"at": 216716, "to": "mm"},
10370 "name": "GL1C_PERFCOUNTER1_HI",
10371 "type_ref": "CPG_PERFCOUNTER1_HI"
10374 "chips": ["gfx10"],
10375 "map": {"at": 216720, "to": "mm"},
10376 "name": "GL1C_PERFCOUNTER2_LO",
10377 "type_ref": "CPG_PERFCOUNTER1_LO"
10380 "chips": ["gfx10"],
10381 "map": {"at": 216724, "to": "mm"},
10382 "name": "GL1C_PERFCOUNTER2_HI",
10383 "type_ref": "CPG_PERFCOUNTER1_HI"
10386 "chips": ["gfx10"],
10387 "map": {"at": 216728, "to": "mm"},
10388 "name": "GL1C_PERFCOUNTER3_LO",
10389 "type_ref": "CPG_PERFCOUNTER1_LO"
10392 "chips": ["gfx10"],
10393 "map": {"at": 216732, "to": "mm"},
10394 "name": "GL1C_PERFCOUNTER3_HI",
10395 "type_ref": "CPG_PERFCOUNTER1_HI"
10398 "chips": ["gfx10"],
10399 "map": {"at": 216832, "to": "mm"},
10400 "name": "CHC_PERFCOUNTER0_LO",
10401 "type_ref": "CPG_PERFCOUNTER1_LO"
10404 "chips": ["gfx10"],
10405 "map": {"at": 216836, "to": "mm"},
10406 "name": "CHC_PERFCOUNTER0_HI",
10407 "type_ref": "CPG_PERFCOUNTER1_HI"
10410 "chips": ["gfx10"],
10411 "map": {"at": 216840, "to": "mm"},
10412 "name": "CHC_PERFCOUNTER1_LO",
10413 "type_ref": "CPG_PERFCOUNTER1_LO"
10416 "chips": ["gfx10"],
10417 "map": {"at": 216844, "to": "mm"},
10418 "name": "CHC_PERFCOUNTER1_HI",
10419 "type_ref": "CPG_PERFCOUNTER1_HI"
10422 "chips": ["gfx10"],
10423 "map": {"at": 216848, "to": "mm"},
10424 "name": "CHC_PERFCOUNTER2_LO",
10425 "type_ref": "CPG_PERFCOUNTER1_LO"
10428 "chips": ["gfx10"],
10429 "map": {"at": 216852, "to": "mm"},
10430 "name": "CHC_PERFCOUNTER2_HI",
10431 "type_ref": "CPG_PERFCOUNTER1_HI"
10434 "chips": ["gfx10"],
10435 "map": {"at": 216856, "to": "mm"},
10436 "name": "CHC_PERFCOUNTER3_LO",
10437 "type_ref": "CPG_PERFCOUNTER1_LO"
10440 "chips": ["gfx10"],
10441 "map": {"at": 216860, "to": "mm"},
10442 "name": "CHC_PERFCOUNTER3_HI",
10443 "type_ref": "CPG_PERFCOUNTER1_HI"
10446 "chips": ["gfx10"],
10447 "map": {"at": 216864, "to": "mm"},
10448 "name": "CHCG_PERFCOUNTER0_LO",
10449 "type_ref": "CPG_PERFCOUNTER1_LO"
10452 "chips": ["gfx10"],
10453 "map": {"at": 216868, "to": "mm"},
10454 "name": "CHCG_PERFCOUNTER0_HI",
10455 "type_ref": "CPG_PERFCOUNTER1_HI"
10458 "chips": ["gfx10"],
10459 "map": {"at": 216872, "to": "mm"},
10460 "name": "CHCG_PERFCOUNTER1_LO",
10461 "type_ref": "CPG_PERFCOUNTER1_LO"
10464 "chips": ["gfx10"],
10465 "map": {"at": 216876, "to": "mm"},
10466 "name": "CHCG_PERFCOUNTER1_HI",
10467 "type_ref": "CPG_PERFCOUNTER1_HI"
10470 "chips": ["gfx10"],
10471 "map": {"at": 216880, "to": "mm"},
10472 "name": "CHCG_PERFCOUNTER2_LO",
10473 "type_ref": "CPG_PERFCOUNTER1_LO"
10476 "chips": ["gfx10"],
10477 "map": {"at": 216884, "to": "mm"},
10478 "name": "CHCG_PERFCOUNTER2_HI",
10479 "type_ref": "CPG_PERFCOUNTER1_HI"
10482 "chips": ["gfx10"],
10483 "map": {"at": 216888, "to": "mm"},
10484 "name": "CHCG_PERFCOUNTER3_LO",
10485 "type_ref": "CPG_PERFCOUNTER1_LO"
10488 "chips": ["gfx10"],
10489 "map": {"at": 216892, "to": "mm"},
10490 "name": "CHCG_PERFCOUNTER3_HI",
10491 "type_ref": "CPG_PERFCOUNTER1_HI"
10494 "chips": ["gfx10"],
10495 "map": {"at": 217112, "to": "mm"},
10496 "name": "CB_PERFCOUNTER0_LO",
10497 "type_ref": "CPG_PERFCOUNTER1_LO"
10500 "chips": ["gfx10"],
10501 "map": {"at": 217116, "to": "mm"},
10502 "name": "CB_PERFCOUNTER0_HI",
10503 "type_ref": "CPG_PERFCOUNTER1_HI"
10506 "chips": ["gfx10"],
10507 "map": {"at": 217120, "to": "mm"},
10508 "name": "CB_PERFCOUNTER1_LO",
10509 "type_ref": "CPG_PERFCOUNTER1_LO"
10512 "chips": ["gfx10"],
10513 "map": {"at": 217124, "to": "mm"},
10514 "name": "CB_PERFCOUNTER1_HI",
10515 "type_ref": "CPG_PERFCOUNTER1_HI"
10518 "chips": ["gfx10"],
10519 "map": {"at": 217128, "to": "mm"},
10520 "name": "CB_PERFCOUNTER2_LO",
10521 "type_ref": "CPG_PERFCOUNTER1_LO"
10524 "chips": ["gfx10"],
10525 "map": {"at": 217132, "to": "mm"},
10526 "name": "CB_PERFCOUNTER2_HI",
10527 "type_ref": "CPG_PERFCOUNTER1_HI"
10530 "chips": ["gfx10"],
10531 "map": {"at": 217136, "to": "mm"},
10532 "name": "CB_PERFCOUNTER3_LO",
10533 "type_ref": "CPG_PERFCOUNTER1_LO"
10536 "chips": ["gfx10"],
10537 "map": {"at": 217140, "to": "mm"},
10538 "name": "CB_PERFCOUNTER3_HI",
10539 "type_ref": "CPG_PERFCOUNTER1_HI"
10542 "chips": ["gfx10"],
10543 "map": {"at": 217344, "to": "mm"},
10544 "name": "DB_PERFCOUNTER0_LO",
10545 "type_ref": "CPG_PERFCOUNTER1_LO"
10548 "chips": ["gfx10"],
10549 "map": {"at": 217348, "to": "mm"},
10550 "name": "DB_PERFCOUNTER0_HI",
10551 "type_ref": "CPG_PERFCOUNTER1_HI"
10554 "chips": ["gfx10"],
10555 "map": {"at": 217352, "to": "mm"},
10556 "name": "DB_PERFCOUNTER1_LO",
10557 "type_ref": "CPG_PERFCOUNTER1_LO"
10560 "chips": ["gfx10"],
10561 "map": {"at": 217356, "to": "mm"},
10562 "name": "DB_PERFCOUNTER1_HI",
10563 "type_ref": "CPG_PERFCOUNTER1_HI"
10566 "chips": ["gfx10"],
10567 "map": {"at": 217360, "to": "mm"},
10568 "name": "DB_PERFCOUNTER2_LO",
10569 "type_ref": "CPG_PERFCOUNTER1_LO"
10572 "chips": ["gfx10"],
10573 "map": {"at": 217364, "to": "mm"},
10574 "name": "DB_PERFCOUNTER2_HI",
10575 "type_ref": "CPG_PERFCOUNTER1_HI"
10578 "chips": ["gfx10"],
10579 "map": {"at": 217368, "to": "mm"},
10580 "name": "DB_PERFCOUNTER3_LO",
10581 "type_ref": "CPG_PERFCOUNTER1_LO"
10584 "chips": ["gfx10"],
10585 "map": {"at": 217372, "to": "mm"},
10586 "name": "DB_PERFCOUNTER3_HI",
10587 "type_ref": "CPG_PERFCOUNTER1_HI"
10590 "chips": ["gfx10"],
10591 "map": {"at": 217600, "to": "mm"},
10592 "name": "RLC_PERFCOUNTER0_LO",
10593 "type_ref": "CPG_PERFCOUNTER1_LO"
10596 "chips": ["gfx10"],
10597 "map": {"at": 217604, "to": "mm"},
10598 "name": "RLC_PERFCOUNTER0_HI",
10599 "type_ref": "CPG_PERFCOUNTER1_HI"
10602 "chips": ["gfx10"],
10603 "map": {"at": 217608, "to": "mm"},
10604 "name": "RLC_PERFCOUNTER1_LO",
10605 "type_ref": "CPG_PERFCOUNTER1_LO"
10608 "chips": ["gfx10"],
10609 "map": {"at": 217612, "to": "mm"},
10610 "name": "RLC_PERFCOUNTER1_HI",
10611 "type_ref": "CPG_PERFCOUNTER1_HI"
10614 "chips": ["gfx10"],
10615 "map": {"at": 217856, "to": "mm"},
10616 "name": "RMI_PERFCOUNTER0_LO",
10617 "type_ref": "CPG_PERFCOUNTER1_LO"
10620 "chips": ["gfx10"],
10621 "map": {"at": 217860, "to": "mm"},
10622 "name": "RMI_PERFCOUNTER0_HI",
10623 "type_ref": "CPG_PERFCOUNTER1_HI"
10626 "chips": ["gfx10"],
10627 "map": {"at": 217864, "to": "mm"},
10628 "name": "RMI_PERFCOUNTER1_LO",
10629 "type_ref": "CPG_PERFCOUNTER1_LO"
10632 "chips": ["gfx10"],
10633 "map": {"at": 217868, "to": "mm"},
10634 "name": "RMI_PERFCOUNTER1_HI",
10635 "type_ref": "CPG_PERFCOUNTER1_HI"
10638 "chips": ["gfx10"],
10639 "map": {"at": 217872, "to": "mm"},
10640 "name": "RMI_PERFCOUNTER2_LO",
10641 "type_ref": "CPG_PERFCOUNTER1_LO"
10644 "chips": ["gfx10"],
10645 "map": {"at": 217876, "to": "mm"},
10646 "name": "RMI_PERFCOUNTER2_HI",
10647 "type_ref": "CPG_PERFCOUNTER1_HI"
10650 "chips": ["gfx10"],
10651 "map": {"at": 217880, "to": "mm"},
10652 "name": "RMI_PERFCOUNTER3_LO",
10653 "type_ref": "CPG_PERFCOUNTER1_LO"
10656 "chips": ["gfx10"],
10657 "map": {"at": 217884, "to": "mm"},
10658 "name": "RMI_PERFCOUNTER3_HI",
10659 "type_ref": "CPG_PERFCOUNTER1_HI"
10662 "chips": ["gfx10"],
10663 "map": {"at": 217984, "to": "mm"},
10664 "name": "GC_ATC_L2_PERFCOUNTER_LO",
10665 "type_ref": "GC_ATC_L2_PERFCOUNTER_LO"
10668 "chips": ["gfx10"],
10669 "map": {"at": 217988, "to": "mm"},
10670 "name": "GC_ATC_L2_PERFCOUNTER_HI",
10671 "type_ref": "GC_ATC_L2_PERFCOUNTER_HI"
10674 "chips": ["gfx10"],
10675 "map": {"at": 218016, "to": "mm"},
10676 "name": "GCMC_VM_L2_PERFCOUNTER_LO",
10677 "type_ref": "GC_ATC_L2_PERFCOUNTER_LO"
10680 "chips": ["gfx10"],
10681 "map": {"at": 218020, "to": "mm"},
10682 "name": "GCMC_VM_L2_PERFCOUNTER_HI",
10683 "type_ref": "GC_ATC_L2_PERFCOUNTER_HI"
10686 "chips": ["gfx10"],
10687 "map": {"at": 218080, "to": "mm"},
10688 "name": "GCVML2_PERFCOUNTER2_0_LO",
10689 "type_ref": "CPG_PERFCOUNTER1_LO"
10692 "chips": ["gfx10"],
10693 "map": {"at": 218084, "to": "mm"},
10694 "name": "GCVML2_PERFCOUNTER2_1_LO",
10695 "type_ref": "CPG_PERFCOUNTER1_LO"
10698 "chips": ["gfx10"],
10699 "map": {"at": 218088, "to": "mm"},
10700 "name": "GCVML2_PERFCOUNTER2_0_HI",
10701 "type_ref": "CPG_PERFCOUNTER1_HI"
10704 "chips": ["gfx10"],
10705 "map": {"at": 218092, "to": "mm"},
10706 "name": "GCVML2_PERFCOUNTER2_1_HI",
10707 "type_ref": "CPG_PERFCOUNTER1_HI"
10710 "chips": ["gfx10"],
10711 "map": {"at": 218096, "to": "mm"},
10712 "name": "GC_ATC_L2_PERFCOUNTER2_LO",
10713 "type_ref": "CPG_PERFCOUNTER1_LO"
10716 "chips": ["gfx10"],
10717 "map": {"at": 218100, "to": "mm"},
10718 "name": "GC_ATC_L2_PERFCOUNTER2_HI",
10719 "type_ref": "CPG_PERFCOUNTER1_HI"
10722 "chips": ["gfx10"],
10723 "map": {"at": 218224, "to": "mm"},
10724 "name": "UTCL1_PERFCOUNTER0_LO",
10725 "type_ref": "CPG_PERFCOUNTER1_LO"
10728 "chips": ["gfx10"],
10729 "map": {"at": 218228, "to": "mm"},
10730 "name": "UTCL1_PERFCOUNTER0_HI",
10731 "type_ref": "CPG_PERFCOUNTER1_HI"
10734 "chips": ["gfx10"],
10735 "map": {"at": 218232, "to": "mm"},
10736 "name": "UTCL1_PERFCOUNTER1_LO",
10737 "type_ref": "CPG_PERFCOUNTER1_LO"
10740 "chips": ["gfx10"],
10741 "map": {"at": 218236, "to": "mm"},
10742 "name": "UTCL1_PERFCOUNTER1_HI",
10743 "type_ref": "CPG_PERFCOUNTER1_HI"
10746 "chips": ["gfx10"],
10747 "map": {"at": 218240, "to": "mm"},
10748 "name": "GCR_PERFCOUNTER0_LO",
10749 "type_ref": "CPG_PERFCOUNTER1_LO"
10752 "chips": ["gfx10"],
10753 "map": {"at": 218244, "to": "mm"},
10754 "name": "GCR_PERFCOUNTER0_HI",
10755 "type_ref": "CPG_PERFCOUNTER1_HI"
10758 "chips": ["gfx10"],
10759 "map": {"at": 218248, "to": "mm"},
10760 "name": "GCR_PERFCOUNTER1_LO",
10761 "type_ref": "CPG_PERFCOUNTER1_LO"
10764 "chips": ["gfx10"],
10765 "map": {"at": 218252, "to": "mm"},
10766 "name": "GCR_PERFCOUNTER1_HI",
10767 "type_ref": "CPG_PERFCOUNTER1_HI"
10770 "chips": ["gfx10"],
10771 "map": {"at": 218624, "to": "mm"},
10772 "name": "PA_PH_PERFCOUNTER0_LO",
10773 "type_ref": "CPG_PERFCOUNTER1_LO"
10776 "chips": ["gfx10"],
10777 "map": {"at": 218628, "to": "mm"},
10778 "name": "PA_PH_PERFCOUNTER0_HI",
10779 "type_ref": "CPG_PERFCOUNTER1_HI"
10782 "chips": ["gfx10"],
10783 "map": {"at": 218632, "to": "mm"},
10784 "name": "PA_PH_PERFCOUNTER1_LO",
10785 "type_ref": "CPG_PERFCOUNTER1_LO"
10788 "chips": ["gfx10"],
10789 "map": {"at": 218636, "to": "mm"},
10790 "name": "PA_PH_PERFCOUNTER1_HI",
10791 "type_ref": "CPG_PERFCOUNTER1_HI"
10794 "chips": ["gfx10"],
10795 "map": {"at": 218640, "to": "mm"},
10796 "name": "PA_PH_PERFCOUNTER2_LO",
10797 "type_ref": "CPG_PERFCOUNTER1_LO"
10800 "chips": ["gfx10"],
10801 "map": {"at": 218644, "to": "mm"},
10802 "name": "PA_PH_PERFCOUNTER2_HI",
10803 "type_ref": "CPG_PERFCOUNTER1_HI"
10806 "chips": ["gfx10"],
10807 "map": {"at": 218648, "to": "mm"},
10808 "name": "PA_PH_PERFCOUNTER3_LO",
10809 "type_ref": "CPG_PERFCOUNTER1_LO"
10812 "chips": ["gfx10"],
10813 "map": {"at": 218652, "to": "mm"},
10814 "name": "PA_PH_PERFCOUNTER3_HI",
10815 "type_ref": "CPG_PERFCOUNTER1_HI"
10818 "chips": ["gfx10"],
10819 "map": {"at": 218656, "to": "mm"},
10820 "name": "PA_PH_PERFCOUNTER4_LO",
10821 "type_ref": "CPG_PERFCOUNTER1_LO"
10824 "chips": ["gfx10"],
10825 "map": {"at": 218660, "to": "mm"},
10826 "name": "PA_PH_PERFCOUNTER4_HI",
10827 "type_ref": "CPG_PERFCOUNTER1_HI"
10830 "chips": ["gfx10"],
10831 "map": {"at": 218664, "to": "mm"},
10832 "name": "PA_PH_PERFCOUNTER5_LO",
10833 "type_ref": "CPG_PERFCOUNTER1_LO"
10836 "chips": ["gfx10"],
10837 "map": {"at": 218668, "to": "mm"},
10838 "name": "PA_PH_PERFCOUNTER5_HI",
10839 "type_ref": "CPG_PERFCOUNTER1_HI"
10842 "chips": ["gfx10"],
10843 "map": {"at": 218672, "to": "mm"},
10844 "name": "PA_PH_PERFCOUNTER6_LO",
10845 "type_ref": "CPG_PERFCOUNTER1_LO"
10848 "chips": ["gfx10"],
10849 "map": {"at": 218676, "to": "mm"},
10850 "name": "PA_PH_PERFCOUNTER6_HI",
10851 "type_ref": "CPG_PERFCOUNTER1_HI"
10854 "chips": ["gfx10"],
10855 "map": {"at": 218680, "to": "mm"},
10856 "name": "PA_PH_PERFCOUNTER7_LO",
10857 "type_ref": "CPG_PERFCOUNTER1_LO"
10860 "chips": ["gfx10"],
10861 "map": {"at": 218684, "to": "mm"},
10862 "name": "PA_PH_PERFCOUNTER7_HI",
10863 "type_ref": "CPG_PERFCOUNTER1_HI"
10866 "chips": ["gfx10"],
10867 "map": {"at": 218880, "to": "mm"},
10868 "name": "GL1A_PERFCOUNTER0_LO",
10869 "type_ref": "CPG_PERFCOUNTER1_LO"
10872 "chips": ["gfx10"],
10873 "map": {"at": 218884, "to": "mm"},
10874 "name": "GL1A_PERFCOUNTER0_HI",
10875 "type_ref": "CPG_PERFCOUNTER1_HI"
10878 "chips": ["gfx10"],
10879 "map": {"at": 218888, "to": "mm"},
10880 "name": "GL1A_PERFCOUNTER1_LO",
10881 "type_ref": "CPG_PERFCOUNTER1_LO"
10884 "chips": ["gfx10"],
10885 "map": {"at": 218892, "to": "mm"},
10886 "name": "GL1A_PERFCOUNTER1_HI",
10887 "type_ref": "CPG_PERFCOUNTER1_HI"
10890 "chips": ["gfx10"],
10891 "map": {"at": 218896, "to": "mm"},
10892 "name": "GL1A_PERFCOUNTER2_LO",
10893 "type_ref": "CPG_PERFCOUNTER1_LO"
10896 "chips": ["gfx10"],
10897 "map": {"at": 218900, "to": "mm"},
10898 "name": "GL1A_PERFCOUNTER2_HI",
10899 "type_ref": "CPG_PERFCOUNTER1_HI"
10902 "chips": ["gfx10"],
10903 "map": {"at": 218904, "to": "mm"},
10904 "name": "GL1A_PERFCOUNTER3_LO",
10905 "type_ref": "CPG_PERFCOUNTER1_LO"
10908 "chips": ["gfx10"],
10909 "map": {"at": 218908, "to": "mm"},
10910 "name": "GL1A_PERFCOUNTER3_HI",
10911 "type_ref": "CPG_PERFCOUNTER1_HI"
10914 "chips": ["gfx10"],
10915 "map": {"at": 219136, "to": "mm"},
10916 "name": "CHA_PERFCOUNTER0_LO",
10917 "type_ref": "CPG_PERFCOUNTER1_LO"
10920 "chips": ["gfx10"],
10921 "map": {"at": 219140, "to": "mm"},
10922 "name": "CHA_PERFCOUNTER0_HI",
10923 "type_ref": "CPG_PERFCOUNTER1_HI"
10926 "chips": ["gfx10"],
10927 "map": {"at": 219144, "to": "mm"},
10928 "name": "CHA_PERFCOUNTER1_LO",
10929 "type_ref": "CPG_PERFCOUNTER1_LO"
10932 "chips": ["gfx10"],
10933 "map": {"at": 219148, "to": "mm"},
10934 "name": "CHA_PERFCOUNTER1_HI",
10935 "type_ref": "CPG_PERFCOUNTER1_HI"
10938 "chips": ["gfx10"],
10939 "map": {"at": 219152, "to": "mm"},
10940 "name": "CHA_PERFCOUNTER2_LO",
10941 "type_ref": "CPG_PERFCOUNTER1_LO"
10944 "chips": ["gfx10"],
10945 "map": {"at": 219156, "to": "mm"},
10946 "name": "CHA_PERFCOUNTER2_HI",
10947 "type_ref": "CPG_PERFCOUNTER1_HI"
10950 "chips": ["gfx10"],
10951 "map": {"at": 219160, "to": "mm"},
10952 "name": "CHA_PERFCOUNTER3_LO",
10953 "type_ref": "CPG_PERFCOUNTER1_LO"
10956 "chips": ["gfx10"],
10957 "map": {"at": 219164, "to": "mm"},
10958 "name": "CHA_PERFCOUNTER3_HI",
10959 "type_ref": "CPG_PERFCOUNTER1_HI"
10962 "chips": ["gfx10"],
10963 "map": {"at": 219392, "to": "mm"},
10964 "name": "GUS_PERFCOUNTER2_LO",
10965 "type_ref": "CPG_PERFCOUNTER1_LO"
10968 "chips": ["gfx10"],
10969 "map": {"at": 219396, "to": "mm"},
10970 "name": "GUS_PERFCOUNTER2_HI",
10971 "type_ref": "CPG_PERFCOUNTER1_HI"
10974 "chips": ["gfx10"],
10975 "map": {"at": 221184, "to": "mm"},
10976 "name": "CPG_PERFCOUNTER1_SELECT",
10977 "type_ref": "CPG_PERFCOUNTER1_SELECT"
10980 "chips": ["gfx10"],
10981 "map": {"at": 221188, "to": "mm"},
10982 "name": "CPG_PERFCOUNTER0_SELECT1",
10983 "type_ref": "CPG_PERFCOUNTER0_SELECT1"
10986 "chips": ["gfx10"],
10987 "map": {"at": 221192, "to": "mm"},
10988 "name": "CPG_PERFCOUNTER0_SELECT",
10989 "type_ref": "CPG_PERFCOUNTER1_SELECT"
10992 "chips": ["gfx10"],
10993 "map": {"at": 221196, "to": "mm"},
10994 "name": "CPC_PERFCOUNTER1_SELECT",
10995 "type_ref": "CPG_PERFCOUNTER1_SELECT"
10998 "chips": ["gfx10"],
10999 "map": {"at": 221200, "to": "mm"},
11000 "name": "CPC_PERFCOUNTER0_SELECT1",
11001 "type_ref": "CPG_PERFCOUNTER0_SELECT1"
11004 "chips": ["gfx10"],
11005 "map": {"at": 221204, "to": "mm"},
11006 "name": "CPF_PERFCOUNTER1_SELECT",
11007 "type_ref": "CPG_PERFCOUNTER1_SELECT"
11010 "chips": ["gfx10"],
11011 "map": {"at": 221208, "to": "mm"},
11012 "name": "CPF_PERFCOUNTER0_SELECT1",
11013 "type_ref": "CPG_PERFCOUNTER0_SELECT1"
11016 "chips": ["gfx10"],
11017 "map": {"at": 221212, "to": "mm"},
11018 "name": "CPF_PERFCOUNTER0_SELECT",
11019 "type_ref": "CPG_PERFCOUNTER1_SELECT"
11022 "chips": ["gfx10"],
11023 "map": {"at": 221216, "to": "mm"},
11024 "name": "CP_PERFMON_CNTL",
11025 "type_ref": "CP_PERFMON_CNTL"
11028 "chips": ["gfx10"],
11029 "map": {"at": 221220, "to": "mm"},
11030 "name": "CPC_PERFCOUNTER0_SELECT",
11031 "type_ref": "CPG_PERFCOUNTER1_SELECT"
11034 "chips": ["gfx10"],
11035 "map": {"at": 221224, "to": "mm"},
11036 "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
11037 "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT"
11040 "chips": ["gfx10"],
11041 "map": {"at": 221228, "to": "mm"},
11042 "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
11043 "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
11046 "chips": ["gfx10"],
11047 "map": {"at": 221232, "to": "mm"},
11048 "name": "CPF_LATENCY_STATS_SELECT",
11049 "type_ref": "CPF_LATENCY_STATS_SELECT"
11052 "chips": ["gfx10"],
11053 "map": {"at": 221236, "to": "mm"},
11054 "name": "CPG_LATENCY_STATS_SELECT",
11055 "type_ref": "CPG_LATENCY_STATS_SELECT"
11058 "chips": ["gfx10"],
11059 "map": {"at": 221240, "to": "mm"},
11060 "name": "CPC_LATENCY_STATS_SELECT",
11061 "type_ref": "CPF_LATENCY_STATS_SELECT"
11064 "chips": ["gfx10"],
11065 "map": {"at": 221248, "to": "mm"},
11066 "name": "CP_DRAW_OBJECT",
11067 "type_ref": "CP_DRAW_OBJECT"
11070 "chips": ["gfx10"],
11071 "map": {"at": 221252, "to": "mm"},
11072 "name": "CP_DRAW_OBJECT_COUNTER",
11073 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
11076 "chips": ["gfx10"],
11077 "map": {"at": 221256, "to": "mm"},
11078 "name": "CP_DRAW_WINDOW_MASK_HI",
11079 "type_ref": "CP_DRAW_WINDOW_MASK_HI"
11082 "chips": ["gfx10"],
11083 "map": {"at": 221260, "to": "mm"},
11084 "name": "CP_DRAW_WINDOW_HI",
11085 "type_ref": "CP_DRAW_WINDOW_HI"
11088 "chips": ["gfx10"],
11089 "map": {"at": 221264, "to": "mm"},
11090 "name": "CP_DRAW_WINDOW_LO",
11091 "type_ref": "CP_DRAW_WINDOW_LO"
11094 "chips": ["gfx10"],
11095 "map": {"at": 221268, "to": "mm"},
11096 "name": "CP_DRAW_WINDOW_CNTL",
11097 "type_ref": "CP_DRAW_WINDOW_CNTL"
11100 "chips": ["gfx10"],
11101 "map": {"at": 221440, "to": "mm"},
11102 "name": "GRBM_PERFCOUNTER0_SELECT",
11103 "type_ref": "GRBM_PERFCOUNTER0_SELECT"
11106 "chips": ["gfx10"],
11107 "map": {"at": 221444, "to": "mm"},
11108 "name": "GRBM_PERFCOUNTER1_SELECT",
11109 "type_ref": "GRBM_PERFCOUNTER0_SELECT"
11112 "chips": ["gfx10"],
11113 "map": {"at": 221448, "to": "mm"},
11114 "name": "GRBM_SE0_PERFCOUNTER_SELECT",
11115 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
11118 "chips": ["gfx10"],
11119 "map": {"at": 221452, "to": "mm"},
11120 "name": "GRBM_SE1_PERFCOUNTER_SELECT",
11121 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
11124 "chips": ["gfx10"],
11125 "map": {"at": 221456, "to": "mm"},
11126 "name": "GRBM_SE2_PERFCOUNTER_SELECT",
11127 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
11130 "chips": ["gfx10"],
11131 "map": {"at": 221460, "to": "mm"},
11132 "name": "GRBM_SE3_PERFCOUNTER_SELECT",
11133 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
11136 "chips": ["gfx10"],
11137 "map": {"at": 221492, "to": "mm"},
11138 "name": "GRBM_PERFCOUNTER0_SELECT_HI",
11139 "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
11142 "chips": ["gfx10"],
11143 "map": {"at": 221496, "to": "mm"},
11144 "name": "GRBM_PERFCOUNTER1_SELECT_HI",
11145 "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
11148 "chips": ["gfx10"],
11149 "map": {"at": 221696, "to": "mm"},
11150 "name": "GE_PERFCOUNTER0_SELECT",
11151 "type_ref": "GE_PERFCOUNTER0_SELECT"
11154 "chips": ["gfx10"],
11155 "map": {"at": 221700, "to": "mm"},
11156 "name": "GE_PERFCOUNTER0_SELECT1",
11157 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11160 "chips": ["gfx10"],
11161 "map": {"at": 221704, "to": "mm"},
11162 "name": "GE_PERFCOUNTER1_SELECT",
11163 "type_ref": "GE_PERFCOUNTER0_SELECT"
11166 "chips": ["gfx10"],
11167 "map": {"at": 221708, "to": "mm"},
11168 "name": "GE_PERFCOUNTER1_SELECT1",
11169 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11172 "chips": ["gfx10"],
11173 "map": {"at": 221712, "to": "mm"},
11174 "name": "GE_PERFCOUNTER2_SELECT",
11175 "type_ref": "GE_PERFCOUNTER0_SELECT"
11178 "chips": ["gfx10"],
11179 "map": {"at": 221716, "to": "mm"},
11180 "name": "GE_PERFCOUNTER2_SELECT1",
11181 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11184 "chips": ["gfx10"],
11185 "map": {"at": 221720, "to": "mm"},
11186 "name": "GE_PERFCOUNTER3_SELECT",
11187 "type_ref": "GE_PERFCOUNTER0_SELECT"
11190 "chips": ["gfx10"],
11191 "map": {"at": 221724, "to": "mm"},
11192 "name": "GE_PERFCOUNTER3_SELECT1",
11193 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11196 "chips": ["gfx10"],
11197 "map": {"at": 221728, "to": "mm"},
11198 "name": "GE_PERFCOUNTER4_SELECT",
11199 "type_ref": "GE_PERFCOUNTER4_SELECT"
11202 "chips": ["gfx10"],
11203 "map": {"at": 221736, "to": "mm"},
11204 "name": "GE_PERFCOUNTER5_SELECT",
11205 "type_ref": "GE_PERFCOUNTER4_SELECT"
11208 "chips": ["gfx10"],
11209 "map": {"at": 221744, "to": "mm"},
11210 "name": "GE_PERFCOUNTER6_SELECT",
11211 "type_ref": "GE_PERFCOUNTER4_SELECT"
11214 "chips": ["gfx10"],
11215 "map": {"at": 221752, "to": "mm"},
11216 "name": "GE_PERFCOUNTER7_SELECT",
11217 "type_ref": "GE_PERFCOUNTER4_SELECT"
11220 "chips": ["gfx10"],
11221 "map": {"at": 221760, "to": "mm"},
11222 "name": "GE_PERFCOUNTER8_SELECT",
11223 "type_ref": "GE_PERFCOUNTER4_SELECT"
11226 "chips": ["gfx10"],
11227 "map": {"at": 221768, "to": "mm"},
11228 "name": "GE_PERFCOUNTER9_SELECT",
11229 "type_ref": "GE_PERFCOUNTER4_SELECT"
11232 "chips": ["gfx10"],
11233 "map": {"at": 221776, "to": "mm"},
11234 "name": "GE_PERFCOUNTER10_SELECT",
11235 "type_ref": "GE_PERFCOUNTER4_SELECT"
11238 "chips": ["gfx10"],
11239 "map": {"at": 221784, "to": "mm"},
11240 "name": "GE_PERFCOUNTER11_SELECT",
11241 "type_ref": "GE_PERFCOUNTER4_SELECT"
11244 "chips": ["gfx10"],
11245 "map": {"at": 222208, "to": "mm"},
11246 "name": "PA_SU_PERFCOUNTER0_SELECT",
11247 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11250 "chips": ["gfx10"],
11251 "map": {"at": 222212, "to": "mm"},
11252 "name": "PA_SU_PERFCOUNTER0_SELECT1",
11253 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11256 "chips": ["gfx10"],
11257 "map": {"at": 222216, "to": "mm"},
11258 "name": "PA_SU_PERFCOUNTER1_SELECT",
11259 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11262 "chips": ["gfx10"],
11263 "map": {"at": 222220, "to": "mm"},
11264 "name": "PA_SU_PERFCOUNTER1_SELECT1",
11265 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11268 "chips": ["gfx10"],
11269 "map": {"at": 222224, "to": "mm"},
11270 "name": "PA_SU_PERFCOUNTER2_SELECT",
11271 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11274 "chips": ["gfx10"],
11275 "map": {"at": 222228, "to": "mm"},
11276 "name": "PA_SU_PERFCOUNTER2_SELECT1",
11277 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11280 "chips": ["gfx10"],
11281 "map": {"at": 222232, "to": "mm"},
11282 "name": "PA_SU_PERFCOUNTER3_SELECT",
11283 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11286 "chips": ["gfx10"],
11287 "map": {"at": 222236, "to": "mm"},
11288 "name": "PA_SU_PERFCOUNTER3_SELECT1",
11289 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11292 "chips": ["gfx10"],
11293 "map": {"at": 222464, "to": "mm"},
11294 "name": "PA_SC_PERFCOUNTER0_SELECT",
11295 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11298 "chips": ["gfx10"],
11299 "map": {"at": 222468, "to": "mm"},
11300 "name": "PA_SC_PERFCOUNTER0_SELECT1",
11301 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11304 "chips": ["gfx10"],
11305 "map": {"at": 222472, "to": "mm"},
11306 "name": "PA_SC_PERFCOUNTER1_SELECT",
11307 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11310 "chips": ["gfx10"],
11311 "map": {"at": 222476, "to": "mm"},
11312 "name": "PA_SC_PERFCOUNTER2_SELECT",
11313 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11316 "chips": ["gfx10"],
11317 "map": {"at": 222480, "to": "mm"},
11318 "name": "PA_SC_PERFCOUNTER3_SELECT",
11319 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11322 "chips": ["gfx10"],
11323 "map": {"at": 222484, "to": "mm"},
11324 "name": "PA_SC_PERFCOUNTER4_SELECT",
11325 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11328 "chips": ["gfx10"],
11329 "map": {"at": 222488, "to": "mm"},
11330 "name": "PA_SC_PERFCOUNTER5_SELECT",
11331 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11334 "chips": ["gfx10"],
11335 "map": {"at": 222492, "to": "mm"},
11336 "name": "PA_SC_PERFCOUNTER6_SELECT",
11337 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11340 "chips": ["gfx10"],
11341 "map": {"at": 222496, "to": "mm"},
11342 "name": "PA_SC_PERFCOUNTER7_SELECT",
11343 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11346 "chips": ["gfx10"],
11347 "map": {"at": 222720, "to": "mm"},
11348 "name": "SPI_PERFCOUNTER0_SELECT",
11349 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11352 "chips": ["gfx10"],
11353 "map": {"at": 222724, "to": "mm"},
11354 "name": "SPI_PERFCOUNTER1_SELECT",
11355 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11358 "chips": ["gfx10"],
11359 "map": {"at": 222728, "to": "mm"},
11360 "name": "SPI_PERFCOUNTER2_SELECT",
11361 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11364 "chips": ["gfx10"],
11365 "map": {"at": 222732, "to": "mm"},
11366 "name": "SPI_PERFCOUNTER3_SELECT",
11367 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11370 "chips": ["gfx10"],
11371 "map": {"at": 222736, "to": "mm"},
11372 "name": "SPI_PERFCOUNTER0_SELECT1",
11373 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11376 "chips": ["gfx10"],
11377 "map": {"at": 222740, "to": "mm"},
11378 "name": "SPI_PERFCOUNTER1_SELECT1",
11379 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11382 "chips": ["gfx10"],
11383 "map": {"at": 222744, "to": "mm"},
11384 "name": "SPI_PERFCOUNTER2_SELECT1",
11385 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11388 "chips": ["gfx10"],
11389 "map": {"at": 222748, "to": "mm"},
11390 "name": "SPI_PERFCOUNTER3_SELECT1",
11391 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11394 "chips": ["gfx10"],
11395 "map": {"at": 222752, "to": "mm"},
11396 "name": "SPI_PERFCOUNTER4_SELECT",
11397 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11400 "chips": ["gfx10"],
11401 "map": {"at": 222756, "to": "mm"},
11402 "name": "SPI_PERFCOUNTER5_SELECT",
11403 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11406 "chips": ["gfx10"],
11407 "map": {"at": 222760, "to": "mm"},
11408 "name": "SPI_PERFCOUNTER_BINS",
11409 "type_ref": "SPI_PERFCOUNTER_BINS"
11412 "chips": ["gfx10"],
11413 "map": {"at": 222976, "to": "mm"},
11414 "name": "SQ_PERFCOUNTER0_SELECT",
11415 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11418 "chips": ["gfx10"],
11419 "map": {"at": 222980, "to": "mm"},
11420 "name": "SQ_PERFCOUNTER1_SELECT",
11421 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11424 "chips": ["gfx10"],
11425 "map": {"at": 222984, "to": "mm"},
11426 "name": "SQ_PERFCOUNTER2_SELECT",
11427 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11430 "chips": ["gfx10"],
11431 "map": {"at": 222988, "to": "mm"},
11432 "name": "SQ_PERFCOUNTER3_SELECT",
11433 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11436 "chips": ["gfx10"],
11437 "map": {"at": 222992, "to": "mm"},
11438 "name": "SQ_PERFCOUNTER4_SELECT",
11439 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11442 "chips": ["gfx10"],
11443 "map": {"at": 222996, "to": "mm"},
11444 "name": "SQ_PERFCOUNTER5_SELECT",
11445 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11448 "chips": ["gfx10"],
11449 "map": {"at": 223000, "to": "mm"},
11450 "name": "SQ_PERFCOUNTER6_SELECT",
11451 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11454 "chips": ["gfx10"],
11455 "map": {"at": 223004, "to": "mm"},
11456 "name": "SQ_PERFCOUNTER7_SELECT",
11457 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11460 "chips": ["gfx10"],
11461 "map": {"at": 223008, "to": "mm"},
11462 "name": "SQ_PERFCOUNTER8_SELECT",
11463 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11466 "chips": ["gfx10"],
11467 "map": {"at": 223012, "to": "mm"},
11468 "name": "SQ_PERFCOUNTER9_SELECT",
11469 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11472 "chips": ["gfx10"],
11473 "map": {"at": 223016, "to": "mm"},
11474 "name": "SQ_PERFCOUNTER10_SELECT",
11475 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11478 "chips": ["gfx10"],
11479 "map": {"at": 223020, "to": "mm"},
11480 "name": "SQ_PERFCOUNTER11_SELECT",
11481 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11484 "chips": ["gfx10"],
11485 "map": {"at": 223024, "to": "mm"},
11486 "name": "SQ_PERFCOUNTER12_SELECT",
11487 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11490 "chips": ["gfx10"],
11491 "map": {"at": 223028, "to": "mm"},
11492 "name": "SQ_PERFCOUNTER13_SELECT",
11493 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11496 "chips": ["gfx10"],
11497 "map": {"at": 223032, "to": "mm"},
11498 "name": "SQ_PERFCOUNTER14_SELECT",
11499 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11502 "chips": ["gfx10"],
11503 "map": {"at": 223036, "to": "mm"},
11504 "name": "SQ_PERFCOUNTER15_SELECT",
11505 "type_ref": "SQ_PERFCOUNTER0_SELECT"
11508 "chips": ["gfx10"],
11509 "map": {"at": 223104, "to": "mm"},
11510 "name": "SQ_PERFCOUNTER_CTRL",
11511 "type_ref": "SQ_PERFCOUNTER_CTRL"
11514 "chips": ["gfx10"],
11515 "map": {"at": 223112, "to": "mm"},
11516 "name": "SQ_PERFCOUNTER_CTRL2",
11517 "type_ref": "SQ_PERFCOUNTER_CTRL2"
11520 "chips": ["gfx10"],
11521 "map": {"at": 223232, "to": "mm"},
11522 "name": "GCEA_PERFCOUNTER2_SELECT",
11523 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11526 "chips": ["gfx10"],
11527 "map": {"at": 223236, "to": "mm"},
11528 "name": "GCEA_PERFCOUNTER2_SELECT1",
11529 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11532 "chips": ["gfx10"],
11533 "map": {"at": 223240, "to": "mm"},
11534 "name": "GCEA_PERFCOUNTER2_MODE",
11535 "type_ref": "GCEA_PERFCOUNTER2_MODE"
11538 "chips": ["gfx10"],
11539 "map": {"at": 223488, "to": "mm"},
11540 "name": "SX_PERFCOUNTER0_SELECT",
11541 "type_ref": "SX_PERFCOUNTER0_SELECT"
11544 "chips": ["gfx10"],
11545 "map": {"at": 223492, "to": "mm"},
11546 "name": "SX_PERFCOUNTER1_SELECT",
11547 "type_ref": "SX_PERFCOUNTER0_SELECT"
11550 "chips": ["gfx10"],
11551 "map": {"at": 223496, "to": "mm"},
11552 "name": "SX_PERFCOUNTER2_SELECT",
11553 "type_ref": "SX_PERFCOUNTER0_SELECT"
11556 "chips": ["gfx10"],
11557 "map": {"at": 223500, "to": "mm"},
11558 "name": "SX_PERFCOUNTER3_SELECT",
11559 "type_ref": "SX_PERFCOUNTER0_SELECT"
11562 "chips": ["gfx10"],
11563 "map": {"at": 223504, "to": "mm"},
11564 "name": "SX_PERFCOUNTER0_SELECT1",
11565 "type_ref": "SX_PERFCOUNTER0_SELECT1"
11568 "chips": ["gfx10"],
11569 "map": {"at": 223508, "to": "mm"},
11570 "name": "SX_PERFCOUNTER1_SELECT1",
11571 "type_ref": "SX_PERFCOUNTER0_SELECT1"
11574 "chips": ["gfx10"],
11575 "map": {"at": 223744, "to": "mm"},
11576 "name": "GDS_PERFCOUNTER0_SELECT",
11577 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11580 "chips": ["gfx10"],
11581 "map": {"at": 223748, "to": "mm"},
11582 "name": "GDS_PERFCOUNTER1_SELECT",
11583 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11586 "chips": ["gfx10"],
11587 "map": {"at": 223752, "to": "mm"},
11588 "name": "GDS_PERFCOUNTER2_SELECT",
11589 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11592 "chips": ["gfx10"],
11593 "map": {"at": 223756, "to": "mm"},
11594 "name": "GDS_PERFCOUNTER3_SELECT",
11595 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11598 "chips": ["gfx10"],
11599 "map": {"at": 223760, "to": "mm"},
11600 "name": "GDS_PERFCOUNTER0_SELECT1",
11601 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11604 "chips": ["gfx10"],
11605 "map": {"at": 224000, "to": "mm"},
11606 "name": "TA_PERFCOUNTER0_SELECT",
11607 "type_ref": "TA_PERFCOUNTER0_SELECT"
11610 "chips": ["gfx10"],
11611 "map": {"at": 224004, "to": "mm"},
11612 "name": "TA_PERFCOUNTER0_SELECT1",
11613 "type_ref": "TA_PERFCOUNTER0_SELECT1"
11616 "chips": ["gfx10"],
11617 "map": {"at": 224008, "to": "mm"},
11618 "name": "TA_PERFCOUNTER1_SELECT",
11619 "type_ref": "TA_PERFCOUNTER1_SELECT"
11622 "chips": ["gfx10"],
11623 "map": {"at": 224256, "to": "mm"},
11624 "name": "TD_PERFCOUNTER0_SELECT",
11625 "type_ref": "TA_PERFCOUNTER0_SELECT"
11628 "chips": ["gfx10"],
11629 "map": {"at": 224260, "to": "mm"},
11630 "name": "TD_PERFCOUNTER0_SELECT1",
11631 "type_ref": "TA_PERFCOUNTER0_SELECT1"
11634 "chips": ["gfx10"],
11635 "map": {"at": 224264, "to": "mm"},
11636 "name": "TD_PERFCOUNTER1_SELECT",
11637 "type_ref": "TA_PERFCOUNTER1_SELECT"
11640 "chips": ["gfx10"],
11641 "map": {"at": 224512, "to": "mm"},
11642 "name": "TCP_PERFCOUNTER0_SELECT",
11643 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11646 "chips": ["gfx10"],
11647 "map": {"at": 224516, "to": "mm"},
11648 "name": "TCP_PERFCOUNTER0_SELECT1",
11649 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11652 "chips": ["gfx10"],
11653 "map": {"at": 224520, "to": "mm"},
11654 "name": "TCP_PERFCOUNTER1_SELECT",
11655 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11658 "chips": ["gfx10"],
11659 "map": {"at": 224524, "to": "mm"},
11660 "name": "TCP_PERFCOUNTER1_SELECT1",
11661 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11664 "chips": ["gfx10"],
11665 "map": {"at": 224528, "to": "mm"},
11666 "name": "TCP_PERFCOUNTER2_SELECT",
11667 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11670 "chips": ["gfx10"],
11671 "map": {"at": 224532, "to": "mm"},
11672 "name": "TCP_PERFCOUNTER3_SELECT",
11673 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11676 "chips": ["gfx10"],
11677 "map": {"at": 224768, "to": "mm"},
11678 "name": "GL2C_PERFCOUNTER0_SELECT",
11679 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11682 "chips": ["gfx10"],
11683 "map": {"at": 224772, "to": "mm"},
11684 "name": "GL2C_PERFCOUNTER0_SELECT1",
11685 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11688 "chips": ["gfx10"],
11689 "map": {"at": 224776, "to": "mm"},
11690 "name": "GL2C_PERFCOUNTER1_SELECT",
11691 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11694 "chips": ["gfx10"],
11695 "map": {"at": 224780, "to": "mm"},
11696 "name": "GL2C_PERFCOUNTER1_SELECT1",
11697 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11700 "chips": ["gfx10"],
11701 "map": {"at": 224784, "to": "mm"},
11702 "name": "GL2C_PERFCOUNTER2_SELECT",
11703 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11706 "chips": ["gfx10"],
11707 "map": {"at": 224788, "to": "mm"},
11708 "name": "GL2C_PERFCOUNTER3_SELECT",
11709 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11712 "chips": ["gfx10"],
11713 "map": {"at": 224832, "to": "mm"},
11714 "name": "GL2A_PERFCOUNTER0_SELECT",
11715 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11718 "chips": ["gfx10"],
11719 "map": {"at": 224836, "to": "mm"},
11720 "name": "GL2A_PERFCOUNTER0_SELECT1",
11721 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11724 "chips": ["gfx10"],
11725 "map": {"at": 224840, "to": "mm"},
11726 "name": "GL2A_PERFCOUNTER1_SELECT",
11727 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11730 "chips": ["gfx10"],
11731 "map": {"at": 224844, "to": "mm"},
11732 "name": "GL2A_PERFCOUNTER1_SELECT1",
11733 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11736 "chips": ["gfx10"],
11737 "map": {"at": 224848, "to": "mm"},
11738 "name": "GL2A_PERFCOUNTER2_SELECT",
11739 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11742 "chips": ["gfx10"],
11743 "map": {"at": 224852, "to": "mm"},
11744 "name": "GL2A_PERFCOUNTER3_SELECT",
11745 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11748 "chips": ["gfx10"],
11749 "map": {"at": 224896, "to": "mm"},
11750 "name": "GL1C_PERFCOUNTER0_SELECT",
11751 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11754 "chips": ["gfx10"],
11755 "map": {"at": 224900, "to": "mm"},
11756 "name": "GL1C_PERFCOUNTER0_SELECT1",
11757 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11760 "chips": ["gfx10"],
11761 "map": {"at": 224904, "to": "mm"},
11762 "name": "GL1C_PERFCOUNTER1_SELECT",
11763 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11766 "chips": ["gfx10"],
11767 "map": {"at": 224908, "to": "mm"},
11768 "name": "GL1C_PERFCOUNTER2_SELECT",
11769 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11772 "chips": ["gfx10"],
11773 "map": {"at": 224912, "to": "mm"},
11774 "name": "GL1C_PERFCOUNTER3_SELECT",
11775 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11778 "chips": ["gfx10"],
11779 "map": {"at": 225024, "to": "mm"},
11780 "name": "CHC_PERFCOUNTER0_SELECT",
11781 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11784 "chips": ["gfx10"],
11785 "map": {"at": 225028, "to": "mm"},
11786 "name": "CHC_PERFCOUNTER0_SELECT1",
11787 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11790 "chips": ["gfx10"],
11791 "map": {"at": 225032, "to": "mm"},
11792 "name": "CHC_PERFCOUNTER1_SELECT",
11793 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11796 "chips": ["gfx10"],
11797 "map": {"at": 225036, "to": "mm"},
11798 "name": "CHC_PERFCOUNTER2_SELECT",
11799 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11802 "chips": ["gfx10"],
11803 "map": {"at": 225040, "to": "mm"},
11804 "name": "CHC_PERFCOUNTER3_SELECT",
11805 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11808 "chips": ["gfx10"],
11809 "map": {"at": 225048, "to": "mm"},
11810 "name": "CHCG_PERFCOUNTER0_SELECT",
11811 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11814 "chips": ["gfx10"],
11815 "map": {"at": 225052, "to": "mm"},
11816 "name": "CHCG_PERFCOUNTER0_SELECT1",
11817 "type_ref": "GE_PERFCOUNTER0_SELECT1"
11820 "chips": ["gfx10"],
11821 "map": {"at": 225056, "to": "mm"},
11822 "name": "CHCG_PERFCOUNTER1_SELECT",
11823 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11826 "chips": ["gfx10"],
11827 "map": {"at": 225060, "to": "mm"},
11828 "name": "CHCG_PERFCOUNTER2_SELECT",
11829 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11832 "chips": ["gfx10"],
11833 "map": {"at": 225064, "to": "mm"},
11834 "name": "CHCG_PERFCOUNTER3_SELECT",
11835 "type_ref": "TCP_PERFCOUNTER2_SELECT"
11838 "chips": ["gfx10"],
11839 "map": {"at": 225280, "to": "mm"},
11840 "name": "CB_PERFCOUNTER_FILTER",
11841 "type_ref": "CB_PERFCOUNTER_FILTER"
11844 "chips": ["gfx10"],
11845 "map": {"at": 225284, "to": "mm"},
11846 "name": "CB_PERFCOUNTER0_SELECT",
11847 "type_ref": "CB_PERFCOUNTER0_SELECT"
11850 "chips": ["gfx10"],
11851 "map": {"at": 225288, "to": "mm"},
11852 "name": "CB_PERFCOUNTER0_SELECT1",
11853 "type_ref": "CB_PERFCOUNTER0_SELECT1"
11856 "chips": ["gfx10"],
11857 "map": {"at": 225292, "to": "mm"},
11858 "name": "CB_PERFCOUNTER1_SELECT",
11859 "type_ref": "CB_PERFCOUNTER1_SELECT"
11862 "chips": ["gfx10"],
11863 "map": {"at": 225296, "to": "mm"},
11864 "name": "CB_PERFCOUNTER2_SELECT",
11865 "type_ref": "CB_PERFCOUNTER1_SELECT"
11868 "chips": ["gfx10"],
11869 "map": {"at": 225300, "to": "mm"},
11870 "name": "CB_PERFCOUNTER3_SELECT",
11871 "type_ref": "CB_PERFCOUNTER1_SELECT"
11874 "chips": ["gfx10"],
11875 "map": {"at": 225536, "to": "mm"},
11876 "name": "DB_PERFCOUNTER0_SELECT",
11877 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11880 "chips": ["gfx10"],
11881 "map": {"at": 225540, "to": "mm"},
11882 "name": "DB_PERFCOUNTER0_SELECT1",
11883 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11886 "chips": ["gfx10"],
11887 "map": {"at": 225544, "to": "mm"},
11888 "name": "DB_PERFCOUNTER1_SELECT",
11889 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11892 "chips": ["gfx10"],
11893 "map": {"at": 225548, "to": "mm"},
11894 "name": "DB_PERFCOUNTER1_SELECT1",
11895 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11898 "chips": ["gfx10"],
11899 "map": {"at": 225552, "to": "mm"},
11900 "name": "DB_PERFCOUNTER2_SELECT",
11901 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11904 "chips": ["gfx10"],
11905 "map": {"at": 225560, "to": "mm"},
11906 "name": "DB_PERFCOUNTER3_SELECT",
11907 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11910 "chips": ["gfx10"],
11911 "map": {"at": 225792, "to": "mm"},
11912 "name": "RLC_SPM_PERFMON_CNTL",
11913 "type_ref": "RLC_SPM_PERFMON_CNTL"
11916 "chips": ["gfx10"],
11917 "map": {"at": 225796, "to": "mm"},
11918 "name": "RLC_SPM_PERFMON_RING_BASE_LO",
11919 "type_ref": "RLC_SPM_PERFMON_RING_BASE_LO"
11922 "chips": ["gfx10"],
11923 "map": {"at": 225800, "to": "mm"},
11924 "name": "RLC_SPM_PERFMON_RING_BASE_HI",
11925 "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
11928 "chips": ["gfx10"],
11929 "map": {"at": 225804, "to": "mm"},
11930 "name": "RLC_SPM_PERFMON_RING_SIZE",
11931 "type_ref": "RLC_SPM_PERFMON_RING_SIZE"
11934 "chips": ["gfx10"],
11935 "map": {"at": 225808, "to": "mm"},
11936 "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
11937 "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
11940 "chips": ["gfx10"],
11941 "map": {"at": 225812, "to": "mm"},
11942 "name": "RLC_SPM_RING_RDPTR",
11943 "type_ref": "RLC_SPM_RING_RDPTR"
11946 "chips": ["gfx10"],
11947 "map": {"at": 225816, "to": "mm"},
11948 "name": "RLC_SPM_SEGMENT_THRESHOLD",
11949 "type_ref": "RLC_SPM_SEGMENT_THRESHOLD"
11952 "chips": ["gfx10"],
11953 "map": {"at": 225820, "to": "mm"},
11954 "name": "RLC_SPM_SE_MUXSEL_ADDR",
11955 "type_ref": "RLC_SPM_SE_MUXSEL_ADDR"
11958 "chips": ["gfx10"],
11959 "map": {"at": 225824, "to": "mm"},
11960 "name": "RLC_SPM_SE_MUXSEL_DATA",
11961 "type_ref": "RLC_SPM_SE_MUXSEL_DATA"
11964 "chips": ["gfx10"],
11965 "map": {"at": 225828, "to": "mm"},
11966 "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
11967 "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
11970 "chips": ["gfx10"],
11971 "map": {"at": 225832, "to": "mm"},
11972 "name": "RLC_SPM_GLOBAL_MUXSEL_DATA",
11973 "type_ref": "RLC_SPM_SE_MUXSEL_DATA"
11976 "chips": ["gfx10"],
11977 "map": {"at": 225836, "to": "mm"},
11978 "name": "RLC_SPM_DESER_START_SKEW",
11979 "type_ref": "RLC_SPM_DESER_START_SKEW"
11982 "chips": ["gfx10"],
11983 "map": {"at": 225840, "to": "mm"},
11984 "name": "RLC_SPM_GLOBALS_SAMPLE_SKEW",
11985 "type_ref": "RLC_SPM_GLOBALS_SAMPLE_SKEW"
11988 "chips": ["gfx10"],
11989 "map": {"at": 225844, "to": "mm"},
11990 "name": "RLC_SPM_GLOBALS_MUXSEL_SKEW",
11991 "type_ref": "RLC_SPM_GLOBALS_MUXSEL_SKEW"
11994 "chips": ["gfx10"],
11995 "map": {"at": 225848, "to": "mm"},
11996 "name": "RLC_SPM_SE_SAMPLE_SKEW",
11997 "type_ref": "RLC_SPM_SE_SAMPLE_SKEW"
12000 "chips": ["gfx10"],
12001 "map": {"at": 225852, "to": "mm"},
12002 "name": "RLC_SPM_SE_MUXSEL_SKEW",
12003 "type_ref": "RLC_SPM_SE_MUXSEL_SKEW"
12006 "chips": ["gfx10"],
12007 "map": {"at": 225856, "to": "mm"},
12008 "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR",
12009 "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR"
12012 "chips": ["gfx10"],
12013 "map": {"at": 225860, "to": "mm"},
12014 "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA",
12015 "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
12018 "chips": ["gfx10"],
12019 "map": {"at": 225864, "to": "mm"},
12020 "name": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR",
12021 "type_ref": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR"
12024 "chips": ["gfx10"],
12025 "map": {"at": 225868, "to": "mm"},
12026 "name": "RLC_SPM_SE_SAMPLEDELAY_IND_DATA",
12027 "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
12030 "chips": ["gfx10"],
12031 "map": {"at": 225872, "to": "mm"},
12032 "name": "RLC_SPM_RING_WRPTR",
12033 "type_ref": "RLC_SPM_RING_WRPTR"
12036 "chips": ["gfx10"],
12037 "map": {"at": 225876, "to": "mm"},
12038 "name": "RLC_SPM_ACCUM_DATARAM_ADDR",
12039 "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
12042 "chips": ["gfx10"],
12043 "map": {"at": 225880, "to": "mm"},
12044 "name": "RLC_SPM_ACCUM_DATARAM_DATA",
12045 "type_ref": "RLC_SPM_ACCUM_DATARAM_DATA"
12048 "chips": ["gfx10"],
12049 "map": {"at": 225884, "to": "mm"},
12050 "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR",
12051 "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR"
12054 "chips": ["gfx10"],
12055 "map": {"at": 225888, "to": "mm"},
12056 "name": "RLC_SPM_ACCUM_CTRLRAM_DATA",
12057 "type_ref": "RLC_SPM_ACCUM_CTRLRAM_DATA"
12060 "chips": ["gfx10"],
12061 "map": {"at": 225892, "to": "mm"},
12062 "name": "RLC_SPM_ACCUM_STATUS",
12063 "type_ref": "RLC_SPM_ACCUM_STATUS"
12066 "chips": ["gfx10"],
12067 "map": {"at": 225896, "to": "mm"},
12068 "name": "RLC_SPM_ACCUM_CTRL",
12069 "type_ref": "RLC_SPM_ACCUM_CTRL"
12072 "chips": ["gfx10"],
12073 "map": {"at": 225900, "to": "mm"},
12074 "name": "RLC_SPM_ACCUM_MODE",
12075 "type_ref": "RLC_SPM_ACCUM_MODE"
12078 "chips": ["gfx10"],
12079 "map": {"at": 225904, "to": "mm"},
12080 "name": "RLC_SPM_ACCUM_THRESHOLD",
12081 "type_ref": "RLC_SPM_ACCUM_THRESHOLD"
12084 "chips": ["gfx10"],
12085 "map": {"at": 225908, "to": "mm"},
12086 "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED",
12087 "type_ref": "RLC_SPM_ACCUM_SAMPLES_REQUESTED"
12090 "chips": ["gfx10"],
12091 "map": {"at": 225912, "to": "mm"},
12092 "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT",
12093 "type_ref": "RLC_SPM_ACCUM_DATARAM_WRCOUNT"
12096 "chips": ["gfx10"],
12097 "map": {"at": 225916, "to": "mm"},
12098 "name": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE",
12099 "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
12102 "chips": ["gfx10"],
12103 "map": {"at": 225920, "to": "mm"},
12104 "name": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE",
12105 "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
12108 "chips": ["gfx10"],
12109 "map": {"at": 225924, "to": "mm"},
12110 "name": "RLC_SPM_VIRT_CTRL",
12111 "type_ref": "RLC_SPM_VIRT_CTRL"
12114 "chips": ["gfx10"],
12115 "map": {"at": 225932, "to": "mm"},
12116 "name": "RLC_SPM_VIRT_STATUS",
12117 "type_ref": "RLC_SPM_VIRT_STATUS"
12120 "chips": ["gfx10"],
12121 "map": {"at": 226048, "to": "mm"},
12122 "name": "RLC_PERFMON_CNTL",
12123 "type_ref": "RLC_PERFMON_CNTL"
12126 "chips": ["gfx10"],
12127 "map": {"at": 226052, "to": "mm"},
12128 "name": "RLC_PERFCOUNTER0_SELECT",
12129 "type_ref": "RLC_PERFCOUNTER0_SELECT"
12132 "chips": ["gfx10"],
12133 "map": {"at": 226056, "to": "mm"},
12134 "name": "RLC_PERFCOUNTER1_SELECT",
12135 "type_ref": "RLC_PERFCOUNTER0_SELECT"
12138 "chips": ["gfx10"],
12139 "map": {"at": 226060, "to": "mm"},
12140 "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
12141 "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL"
12144 "chips": ["gfx10"],
12145 "map": {"at": 226064, "to": "mm"},
12146 "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
12147 "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
12150 "chips": ["gfx10"],
12151 "map": {"at": 226068, "to": "mm"},
12152 "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA",
12153 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
12156 "chips": ["gfx10"],
12157 "map": {"at": 226072, "to": "mm"},
12158 "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
12159 "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
12162 "chips": ["gfx10"],
12163 "map": {"at": 226076, "to": "mm"},
12164 "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA",
12165 "type_ref": "SPI_SHADER_USER_DATA_PS_0"
12168 "chips": ["gfx10"],
12169 "map": {"at": 226192, "to": "mm"},
12170 "name": "RLC_PERFMON_CLK_CNTL",
12171 "type_ref": "RLC_PERFMON_CLK_CNTL"
12174 "chips": ["gfx10"],
12175 "map": {"at": 226196, "to": "mm"},
12176 "name": "RLC_PERFMON_CLK_CNTL_UCODE",
12177 "type_ref": "RLC_PERFMON_CLK_CNTL"
12180 "chips": ["gfx10"],
12181 "map": {"at": 226304, "to": "mm"},
12182 "name": "RMI_PERFCOUNTER0_SELECT",
12183 "type_ref": "CB_PERFCOUNTER0_SELECT"
12186 "chips": ["gfx10"],
12187 "map": {"at": 226308, "to": "mm"},
12188 "name": "RMI_PERFCOUNTER0_SELECT1",
12189 "type_ref": "CB_PERFCOUNTER0_SELECT1"
12192 "chips": ["gfx10"],
12193 "map": {"at": 226312, "to": "mm"},
12194 "name": "RMI_PERFCOUNTER1_SELECT",
12195 "type_ref": "CB_PERFCOUNTER1_SELECT"
12198 "chips": ["gfx10"],
12199 "map": {"at": 226316, "to": "mm"},
12200 "name": "RMI_PERFCOUNTER2_SELECT",
12201 "type_ref": "CB_PERFCOUNTER0_SELECT"
12204 "chips": ["gfx10"],
12205 "map": {"at": 226320, "to": "mm"},
12206 "name": "RMI_PERFCOUNTER2_SELECT1",
12207 "type_ref": "CB_PERFCOUNTER0_SELECT1"
12210 "chips": ["gfx10"],
12211 "map": {"at": 226324, "to": "mm"},
12212 "name": "RMI_PERFCOUNTER3_SELECT",
12213 "type_ref": "CB_PERFCOUNTER1_SELECT"
12216 "chips": ["gfx10"],
12217 "map": {"at": 226328, "to": "mm"},
12218 "name": "RMI_PERF_COUNTER_CNTL",
12219 "type_ref": "RMI_PERF_COUNTER_CNTL"
12222 "chips": ["gfx10"],
12223 "map": {"at": 226432, "to": "mm"},
12224 "name": "GC_ATC_L2_PERFCOUNTER0_CFG",
12225 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12228 "chips": ["gfx10"],
12229 "map": {"at": 226436, "to": "mm"},
12230 "name": "GC_ATC_L2_PERFCOUNTER1_CFG",
12231 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12234 "chips": ["gfx10"],
12235 "map": {"at": 226440, "to": "mm"},
12236 "name": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL",
12237 "type_ref": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL"
12240 "chips": ["gfx10"],
12241 "map": {"at": 226480, "to": "mm"},
12242 "name": "GCMC_VM_L2_PERFCOUNTER0_CFG",
12243 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12246 "chips": ["gfx10"],
12247 "map": {"at": 226484, "to": "mm"},
12248 "name": "GCMC_VM_L2_PERFCOUNTER1_CFG",
12249 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12252 "chips": ["gfx10"],
12253 "map": {"at": 226488, "to": "mm"},
12254 "name": "GCMC_VM_L2_PERFCOUNTER2_CFG",
12255 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12258 "chips": ["gfx10"],
12259 "map": {"at": 226492, "to": "mm"},
12260 "name": "GCMC_VM_L2_PERFCOUNTER3_CFG",
12261 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12264 "chips": ["gfx10"],
12265 "map": {"at": 226496, "to": "mm"},
12266 "name": "GCMC_VM_L2_PERFCOUNTER4_CFG",
12267 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12270 "chips": ["gfx10"],
12271 "map": {"at": 226500, "to": "mm"},
12272 "name": "GCMC_VM_L2_PERFCOUNTER5_CFG",
12273 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12276 "chips": ["gfx10"],
12277 "map": {"at": 226504, "to": "mm"},
12278 "name": "GCMC_VM_L2_PERFCOUNTER6_CFG",
12279 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12282 "chips": ["gfx10"],
12283 "map": {"at": 226508, "to": "mm"},
12284 "name": "GCMC_VM_L2_PERFCOUNTER7_CFG",
12285 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12288 "chips": ["gfx10"],
12289 "map": {"at": 226512, "to": "mm"},
12290 "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL",
12291 "type_ref": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL"
12294 "chips": ["gfx10"],
12295 "map": {"at": 226544, "to": "mm"},
12296 "name": "GCVML2_PERFCOUNTER2_0_SELECT",
12297 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12300 "chips": ["gfx10"],
12301 "map": {"at": 226548, "to": "mm"},
12302 "name": "GCVML2_PERFCOUNTER2_1_SELECT",
12303 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12306 "chips": ["gfx10"],
12307 "map": {"at": 226552, "to": "mm"},
12308 "name": "GCVML2_PERFCOUNTER2_0_SELECT1",
12309 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12312 "chips": ["gfx10"],
12313 "map": {"at": 226556, "to": "mm"},
12314 "name": "GCVML2_PERFCOUNTER2_1_SELECT1",
12315 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12318 "chips": ["gfx10"],
12319 "map": {"at": 226560, "to": "mm"},
12320 "name": "GCVML2_PERFCOUNTER2_0_MODE",
12321 "type_ref": "GCEA_PERFCOUNTER2_MODE"
12324 "chips": ["gfx10"],
12325 "map": {"at": 226564, "to": "mm"},
12326 "name": "GCVML2_PERFCOUNTER2_1_MODE",
12327 "type_ref": "GCEA_PERFCOUNTER2_MODE"
12330 "chips": ["gfx10"],
12331 "map": {"at": 226608, "to": "mm"},
12332 "name": "GC_ATC_L2_PERFCOUNTER2_SELECT",
12333 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12336 "chips": ["gfx10"],
12337 "map": {"at": 226612, "to": "mm"},
12338 "name": "GC_ATC_L2_PERFCOUNTER2_SELECT1",
12339 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12342 "chips": ["gfx10"],
12343 "map": {"at": 226616, "to": "mm"},
12344 "name": "GC_ATC_L2_PERFCOUNTER2_MODE",
12345 "type_ref": "GCEA_PERFCOUNTER2_MODE"
12348 "chips": ["gfx10"],
12349 "map": {"at": 226688, "to": "mm"},
12350 "name": "GCR_PERFCOUNTER0_SELECT",
12351 "type_ref": "CB_PERFCOUNTER0_SELECT"
12354 "chips": ["gfx10"],
12355 "map": {"at": 226692, "to": "mm"},
12356 "name": "GCR_PERFCOUNTER0_SELECT1",
12357 "type_ref": "CB_PERFCOUNTER0_SELECT1"
12360 "chips": ["gfx10"],
12361 "map": {"at": 226696, "to": "mm"},
12362 "name": "GCR_PERFCOUNTER1_SELECT",
12363 "type_ref": "GCR_PERFCOUNTER1_SELECT"
12366 "chips": ["gfx10"],
12367 "map": {"at": 226700, "to": "mm"},
12368 "name": "UTCL1_PERFCOUNTER0_SELECT",
12369 "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
12372 "chips": ["gfx10"],
12373 "map": {"at": 226704, "to": "mm"},
12374 "name": "UTCL1_PERFCOUNTER1_SELECT",
12375 "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
12378 "chips": ["gfx10"],
12379 "map": {"at": 226816, "to": "mm"},
12380 "name": "PA_PH_PERFCOUNTER0_SELECT",
12381 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12384 "chips": ["gfx10"],
12385 "map": {"at": 226820, "to": "mm"},
12386 "name": "PA_PH_PERFCOUNTER0_SELECT1",
12387 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12390 "chips": ["gfx10"],
12391 "map": {"at": 226824, "to": "mm"},
12392 "name": "PA_PH_PERFCOUNTER1_SELECT",
12393 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12396 "chips": ["gfx10"],
12397 "map": {"at": 226828, "to": "mm"},
12398 "name": "PA_PH_PERFCOUNTER2_SELECT",
12399 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12402 "chips": ["gfx10"],
12403 "map": {"at": 226832, "to": "mm"},
12404 "name": "PA_PH_PERFCOUNTER3_SELECT",
12405 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12408 "chips": ["gfx10"],
12409 "map": {"at": 226836, "to": "mm"},
12410 "name": "PA_PH_PERFCOUNTER4_SELECT",
12411 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12414 "chips": ["gfx10"],
12415 "map": {"at": 226840, "to": "mm"},
12416 "name": "PA_PH_PERFCOUNTER5_SELECT",
12417 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12420 "chips": ["gfx10"],
12421 "map": {"at": 226844, "to": "mm"},
12422 "name": "PA_PH_PERFCOUNTER6_SELECT",
12423 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12426 "chips": ["gfx10"],
12427 "map": {"at": 226848, "to": "mm"},
12428 "name": "PA_PH_PERFCOUNTER7_SELECT",
12429 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12432 "chips": ["gfx10"],
12433 "map": {"at": 226880, "to": "mm"},
12434 "name": "PA_PH_PERFCOUNTER1_SELECT1",
12435 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12438 "chips": ["gfx10"],
12439 "map": {"at": 226884, "to": "mm"},
12440 "name": "PA_PH_PERFCOUNTER2_SELECT1",
12441 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12444 "chips": ["gfx10"],
12445 "map": {"at": 226888, "to": "mm"},
12446 "name": "PA_PH_PERFCOUNTER3_SELECT1",
12447 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12450 "chips": ["gfx10"],
12451 "map": {"at": 227072, "to": "mm"},
12452 "name": "GL1A_PERFCOUNTER0_SELECT",
12453 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12456 "chips": ["gfx10"],
12457 "map": {"at": 227076, "to": "mm"},
12458 "name": "GL1A_PERFCOUNTER0_SELECT1",
12459 "type_ref": "GE_PERFCOUNTER0_SELECT1"
12462 "chips": ["gfx10"],
12463 "map": {"at": 227080, "to": "mm"},
12464 "name": "GL1A_PERFCOUNTER1_SELECT",
12465 "type_ref": "TCP_PERFCOUNTER2_SELECT"
12468 "chips": ["gfx10"],
12469 "map": {"at": 227084, "to": "mm"},
12470 "name": "GL1A_PERFCOUNTER2_SELECT",
12471 "type_ref": "TCP_PERFCOUNTER2_SELECT"
12474 "chips": ["gfx10"],
12475 "map": {"at": 227088, "to": "mm"},
12476 "name": "GL1A_PERFCOUNTER3_SELECT",
12477 "type_ref": "TCP_PERFCOUNTER2_SELECT"
12480 "chips": ["gfx10"],
12481 "map": {"at": 227200, "to": "mm"},
12482 "name": "CHA_PERFCOUNTER0_SELECT",
12483 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12486 "chips": ["gfx10"],
12487 "map": {"at": 227204, "to": "mm"},
12488 "name": "CHA_PERFCOUNTER0_SELECT1",
12489 "type_ref": "GE_PERFCOUNTER0_SELECT1"
12492 "chips": ["gfx10"],
12493 "map": {"at": 227208, "to": "mm"},
12494 "name": "CHA_PERFCOUNTER1_SELECT",
12495 "type_ref": "TCP_PERFCOUNTER2_SELECT"
12498 "chips": ["gfx10"],
12499 "map": {"at": 227212, "to": "mm"},
12500 "name": "CHA_PERFCOUNTER2_SELECT",
12501 "type_ref": "TCP_PERFCOUNTER2_SELECT"
12504 "chips": ["gfx10"],
12505 "map": {"at": 227216, "to": "mm"},
12506 "name": "CHA_PERFCOUNTER3_SELECT",
12507 "type_ref": "TCP_PERFCOUNTER2_SELECT"
12510 "chips": ["gfx10"],
12511 "map": {"at": 227328, "to": "mm"},
12512 "name": "GUS_PERFCOUNTER2_SELECT",
12513 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12516 "chips": ["gfx10"],
12517 "map": {"at": 227332, "to": "mm"},
12518 "name": "GUS_PERFCOUNTER2_SELECT1",
12519 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12522 "chips": ["gfx10"],
12523 "map": {"at": 227336, "to": "mm"},
12524 "name": "GUS_PERFCOUNTER2_MODE",
12525 "type_ref": "GCEA_PERFCOUNTER2_MODE"
12528 "register_types": {
12529 "CB_BLEND0_CONTROL": {
12531 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
12532 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
12533 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
12534 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
12535 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
12536 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
12537 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
12538 {"bits": [30, 30], "name": "ENABLE"},
12539 {"bits": [31, 31], "name": "DISABLE_ROP3"}
12542 "CB_BLEND_ALPHA": {
12544 {"bits": [0, 31], "name": "BLEND_ALPHA"}
12549 {"bits": [0, 31], "name": "BLEND_BLUE"}
12552 "CB_BLEND_GREEN": {
12554 {"bits": [0, 31], "name": "BLEND_GREEN"}
12559 {"bits": [0, 31], "name": "BLEND_RED"}
12562 "CB_COLOR0_ATTRIB": {
12564 {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
12565 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
12566 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
12567 {"bits": [12, 14], "name": "NUM_SAMPLES"},
12568 {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
12569 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
12570 {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"},
12571 {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"}
12574 "CB_COLOR0_ATTRIB2": {
12576 {"bits": [0, 13], "name": "MIP0_HEIGHT"},
12577 {"bits": [14, 27], "name": "MIP0_WIDTH"},
12578 {"bits": [28, 31], "name": "MAX_MIP"}
12581 "CB_COLOR0_ATTRIB3": {
12583 {"bits": [0, 12], "name": "MIP0_DEPTH"},
12584 {"bits": [13, 13], "name": "META_LINEAR"},
12585 {"bits": [14, 18], "name": "COLOR_SW_MODE"},
12586 {"bits": [19, 23], "name": "FMASK_SW_MODE"},
12587 {"bits": [24, 25], "name": "RESOURCE_TYPE"},
12588 {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"},
12589 {"bits": [27, 29], "name": "RESOURCE_LEVEL"},
12590 {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"}
12593 "CB_COLOR0_BASE_EXT": {
12595 {"bits": [0, 7], "name": "BASE_256B"}
12598 "CB_COLOR0_CLEAR_WORD0": {
12600 {"bits": [0, 31], "name": "CLEAR_WORD0"}
12603 "CB_COLOR0_CLEAR_WORD1": {
12605 {"bits": [0, 31], "name": "CLEAR_WORD1"}
12608 "CB_COLOR0_CMASK_SLICE": {
12610 {"bits": [0, 13], "name": "TILE_MAX"}
12613 "CB_COLOR0_DCC_CONTROL": {
12615 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
12616 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
12617 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
12618 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
12619 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
12620 {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
12621 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
12622 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
12623 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
12624 {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
12625 {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
12626 {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"}
12629 "CB_COLOR0_INFO": {
12631 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
12632 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
12633 {"bits": [7, 7], "name": "LINEAR_GENERAL"},
12634 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
12635 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
12636 {"bits": [13, 13], "name": "FAST_CLEAR"},
12637 {"bits": [14, 14], "name": "COMPRESSION"},
12638 {"bits": [15, 15], "name": "BLEND_CLAMP"},
12639 {"bits": [16, 16], "name": "BLEND_BYPASS"},
12640 {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
12641 {"bits": [18, 18], "name": "ROUND_MODE"},
12642 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
12643 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
12644 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
12645 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
12646 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
12647 {"bits": [28, 28], "name": "DCC_ENABLE"},
12648 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
12649 {"bits": [31, 31], "name": "ALT_TILE_MODE"}
12652 "CB_COLOR0_PITCH": {
12654 {"bits": [0, 10], "name": "TILE_MAX"},
12655 {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
12658 "CB_COLOR0_SLICE": {
12660 {"bits": [0, 21], "name": "TILE_MAX"}
12663 "CB_COLOR0_VIEW": {
12665 {"bits": [0, 12], "name": "SLICE_START"},
12666 {"bits": [13, 25], "name": "SLICE_MAX"},
12667 {"bits": [26, 29], "name": "MIP_LEVEL"}
12670 "CB_COLOR_CONTROL": {
12672 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
12673 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
12674 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
12675 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
12678 "CB_COVERAGE_OUT_CONTROL": {
12680 {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
12681 {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
12682 {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
12683 {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
12686 "CB_DCC_CONTROL": {
12688 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
12689 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
12690 {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
12691 {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
12692 {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
12693 {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
12694 {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
12695 {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
12698 "CB_PERFCOUNTER0_SELECT": {
12700 {"bits": [0, 8], "name": "PERF_SEL"},
12701 {"bits": [10, 18], "name": "PERF_SEL1"},
12702 {"bits": [20, 23], "name": "CNTR_MODE"},
12703 {"bits": [24, 27], "name": "PERF_MODE1"},
12704 {"bits": [28, 31], "name": "PERF_MODE"}
12707 "CB_PERFCOUNTER0_SELECT1": {
12709 {"bits": [0, 8], "name": "PERF_SEL2"},
12710 {"bits": [10, 18], "name": "PERF_SEL3"},
12711 {"bits": [24, 27], "name": "PERF_MODE3"},
12712 {"bits": [28, 31], "name": "PERF_MODE2"}
12715 "CB_PERFCOUNTER1_SELECT": {
12717 {"bits": [0, 8], "name": "PERF_SEL"},
12718 {"bits": [28, 31], "name": "PERF_MODE"}
12721 "CB_PERFCOUNTER_FILTER": {
12723 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
12724 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
12725 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
12726 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
12727 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
12728 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
12729 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
12730 {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
12731 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
12732 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
12733 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
12734 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
12737 "CB_RMI_GL2_CACHE_CONTROL": {
12739 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
12740 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
12741 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
12742 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
12743 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
12744 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
12745 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
12746 {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
12747 {"bits": [30, 30], "name": "FMASK_BIG_PAGE"},
12748 {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
12751 "CB_SHADER_MASK": {
12753 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
12754 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
12755 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
12756 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
12757 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
12758 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
12759 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
12760 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
12763 "CB_TARGET_MASK": {
12765 {"bits": [0, 3], "name": "TARGET0_ENABLE"},
12766 {"bits": [4, 7], "name": "TARGET1_ENABLE"},
12767 {"bits": [8, 11], "name": "TARGET2_ENABLE"},
12768 {"bits": [12, 15], "name": "TARGET3_ENABLE"},
12769 {"bits": [16, 19], "name": "TARGET4_ENABLE"},
12770 {"bits": [20, 23], "name": "TARGET5_ENABLE"},
12771 {"bits": [24, 27], "name": "TARGET6_ENABLE"},
12772 {"bits": [28, 31], "name": "TARGET7_ENABLE"}
12775 "COHER_DEST_BASE_2": {
12777 {"bits": [0, 31], "name": "DEST_BASE_256B"}
12780 "COHER_DEST_BASE_HI_0": {
12782 {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
12785 "COMPUTE_DDID_INDEX": {
12787 {"bits": [0, 10], "name": "INDEX"}
12790 "COMPUTE_DESTINATION_EN_SE0": {
12792 {"bits": [0, 31], "name": "CU_EN"}
12797 {"bits": [0, 31], "name": "SIZE"}
12800 "COMPUTE_DISPATCH_ID": {
12802 {"bits": [0, 31], "name": "DISPATCH_ID"}
12805 "COMPUTE_DISPATCH_INITIATOR": {
12807 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
12808 {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
12809 {"bits": [2, 2], "name": "FORCE_START_AT_000"},
12810 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
12811 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
12812 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
12813 {"bits": [6, 6], "name": "ORDER_MODE"},
12814 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
12815 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
12816 {"bits": [12, 12], "name": "RESERVED"},
12817 {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
12818 {"bits": [14, 14], "name": "RESTORE"},
12819 {"bits": [15, 15], "name": "CS_W32_EN"}
12822 "COMPUTE_DISPATCH_TUNNEL": {
12824 {"bits": [0, 9], "name": "OFF_DELAY"},
12825 {"bits": [10, 10], "name": "IMMEDIATE"}
12828 "COMPUTE_MISC_RESERVED": {
12830 {"bits": [0, 1], "name": "SEND_SEID"},
12831 {"bits": [2, 2], "name": "RESERVED2"},
12832 {"bits": [3, 3], "name": "RESERVED3"},
12833 {"bits": [4, 4], "name": "RESERVED4"},
12834 {"bits": [5, 16], "name": "WAVE_ID_BASE"}
12837 "COMPUTE_NUM_THREAD_X": {
12839 {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
12840 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
12843 "COMPUTE_PERFCOUNT_ENABLE": {
12845 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
12848 "COMPUTE_PGM_HI": {
12850 {"bits": [0, 7], "name": "DATA"}
12853 "COMPUTE_PGM_RSRC1": {
12855 {"bits": [0, 5], "name": "VGPRS"},
12856 {"bits": [6, 9], "name": "SGPRS"},
12857 {"bits": [10, 11], "name": "PRIORITY"},
12858 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12859 {"bits": [20, 20], "name": "PRIV"},
12860 {"bits": [21, 21], "name": "DX10_CLAMP"},
12861 {"bits": [23, 23], "name": "IEEE_MODE"},
12862 {"bits": [24, 24], "name": "BULKY"},
12863 {"bits": [26, 26], "name": "FP16_OVFL"},
12864 {"bits": [29, 29], "name": "WGP_MODE"},
12865 {"bits": [30, 30], "name": "MEM_ORDERED"},
12866 {"bits": [31, 31], "name": "FWD_PROGRESS"}
12869 "COMPUTE_PGM_RSRC2": {
12871 {"bits": [0, 0], "name": "SCRATCH_EN"},
12872 {"bits": [1, 5], "name": "USER_SGPR"},
12873 {"bits": [6, 6], "name": "TRAP_PRESENT"},
12874 {"bits": [7, 7], "name": "TGID_X_EN"},
12875 {"bits": [8, 8], "name": "TGID_Y_EN"},
12876 {"bits": [9, 9], "name": "TGID_Z_EN"},
12877 {"bits": [10, 10], "name": "TG_SIZE_EN"},
12878 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
12879 {"bits": [13, 14], "name": "EXCP_EN_MSB"},
12880 {"bits": [15, 23], "name": "LDS_SIZE"},
12881 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
12884 "COMPUTE_PGM_RSRC3": {
12886 {"bits": [0, 3], "name": "SHARED_VGPR_CNT"}
12889 "COMPUTE_PIPELINESTAT_ENABLE": {
12891 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
12894 "COMPUTE_RELAUNCH": {
12896 {"bits": [0, 29], "name": "PAYLOAD"},
12897 {"bits": [30, 30], "name": "IS_EVENT"},
12898 {"bits": [31, 31], "name": "IS_STATE"}
12901 "COMPUTE_REQ_CTRL": {
12903 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
12904 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
12905 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
12906 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
12907 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
12908 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
12909 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
12910 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
12911 {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
12914 "COMPUTE_RESOURCE_LIMITS": {
12916 {"bits": [0, 9], "name": "WAVES_PER_SH"},
12917 {"bits": [12, 15], "name": "TG_PER_CU"},
12918 {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
12919 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
12920 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
12921 {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
12924 "COMPUTE_RESTART_X": {
12926 {"bits": [0, 31], "name": "RESTART"}
12929 "COMPUTE_START_X": {
12931 {"bits": [0, 31], "name": "START"}
12934 "COMPUTE_THREADGROUP_ID": {
12936 {"bits": [0, 31], "name": "THREADGROUP_ID"}
12939 "COMPUTE_THREAD_TRACE_ENABLE": {
12941 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
12944 "COMPUTE_TMPRING_SIZE": {
12946 {"bits": [0, 11], "name": "WAVES"},
12947 {"bits": [12, 24], "name": "WAVESIZE"}
12952 {"bits": [0, 3], "name": "DATA"}
12955 "COMPUTE_WAVE_RESTORE_ADDR_HI": {
12957 {"bits": [0, 15], "name": "ADDR"}
12960 "COMPUTE_WAVE_RESTORE_ADDR_LO": {
12962 {"bits": [0, 31], "name": "ADDR"}
12965 "CPF_LATENCY_STATS_SELECT": {
12967 {"bits": [0, 3], "name": "INDEX"},
12968 {"bits": [30, 30], "name": "CLEAR"},
12969 {"bits": [31, 31], "name": "ENABLE"}
12972 "CPF_TC_PERF_COUNTER_WINDOW_SELECT": {
12974 {"bits": [0, 2], "name": "INDEX"},
12975 {"bits": [30, 30], "name": "ALWAYS"},
12976 {"bits": [31, 31], "name": "ENABLE"}
12979 "CPG_LATENCY_STATS_SELECT": {
12981 {"bits": [0, 4], "name": "INDEX"},
12982 {"bits": [30, 30], "name": "CLEAR"},
12983 {"bits": [31, 31], "name": "ENABLE"}
12986 "CPG_PERFCOUNTER0_SELECT1": {
12988 {"bits": [0, 9], "name": "PERF_SEL2"},
12989 {"bits": [10, 19], "name": "PERF_SEL3"},
12990 {"bits": [24, 27], "name": "CNTR_MODE3"},
12991 {"bits": [28, 31], "name": "CNTR_MODE2"}
12994 "CPG_PERFCOUNTER1_HI": {
12996 {"bits": [0, 31], "name": "PERFCOUNTER_HI"}
12999 "CPG_PERFCOUNTER1_LO": {
13001 {"bits": [0, 31], "name": "PERFCOUNTER_LO"}
13004 "CPG_PERFCOUNTER1_SELECT": {
13006 {"bits": [0, 9], "name": "PERF_SEL"},
13007 {"bits": [10, 19], "name": "PERF_SEL1"},
13008 {"bits": [20, 23], "name": "SPM_MODE"},
13009 {"bits": [24, 27], "name": "CNTR_MODE1"},
13010 {"bits": [28, 31], "name": "CNTR_MODE0"}
13013 "CPG_TC_PERF_COUNTER_WINDOW_SELECT": {
13015 {"bits": [0, 4], "name": "INDEX"},
13016 {"bits": [30, 30], "name": "ALWAYS"},
13017 {"bits": [31, 31], "name": "ENABLE"}
13020 "CP_APPEND_ADDR_HI": {
13022 {"bits": [0, 15], "name": "MEM_ADDR_HI"},
13023 {"bits": [16, 16], "name": "CS_PS_SEL"},
13024 {"bits": [25, 26], "name": "CACHE_POLICY"},
13025 {"bits": [29, 31], "name": "COMMAND"}
13028 "CP_APPEND_ADDR_LO": {
13030 {"bits": [2, 31], "name": "MEM_ADDR_LO"}
13033 "CP_APPEND_LAST_CS_FENCE_HI": {
13035 {"bits": [0, 31], "name": "LAST_FENCE"}
13040 {"bits": [0, 31], "name": "CONST_ENGINE_COUNT"}
13043 "CP_CE_IB1_BASE_HI": {
13045 {"bits": [0, 15], "name": "IB1_BASE_HI"}
13048 "CP_CE_IB1_BASE_LO": {
13050 {"bits": [2, 31], "name": "IB1_BASE_LO"}
13053 "CP_CE_IB1_BUFSZ": {
13055 {"bits": [0, 19], "name": "IB1_BUFSZ"}
13058 "CP_CE_IB1_CMD_BUFSZ": {
13060 {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
13063 "CP_CE_IB2_BASE_HI": {
13065 {"bits": [0, 15], "name": "IB2_BASE_HI"}
13068 "CP_CE_IB2_BASE_LO": {
13070 {"bits": [2, 31], "name": "IB2_BASE_LO"}
13073 "CP_CE_IB2_BUFSZ": {
13075 {"bits": [0, 19], "name": "IB2_BUFSZ"}
13078 "CP_CE_IB2_CMD_BUFSZ": {
13080 {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
13083 "CP_CE_INIT_BASE_HI": {
13085 {"bits": [0, 15], "name": "INIT_BASE_HI"}
13088 "CP_CE_INIT_BASE_LO": {
13090 {"bits": [5, 31], "name": "INIT_BASE_LO"}
13093 "CP_CE_INIT_BUFSZ": {
13095 {"bits": [0, 11], "name": "INIT_BUFSZ"}
13098 "CP_CE_INIT_CMD_BUFSZ": {
13100 {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
13105 {"bits": [0, 31], "name": "COHER_BASE_256B"}
13108 "CP_COHER_BASE_HI": {
13110 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
13115 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
13116 {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
13117 {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
13118 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
13119 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
13120 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
13121 {"bits": [23, 23], "name": "TC_ACTION_ENA"},
13122 {"bits": [25, 25], "name": "CB_ACTION_ENA"},
13123 {"bits": [26, 26], "name": "DB_ACTION_ENA"},
13124 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
13125 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
13126 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
13127 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
13132 {"bits": [0, 31], "name": "COHER_SIZE_256B"}
13135 "CP_COHER_SIZE_HI": {
13137 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
13140 "CP_COHER_START_DELAY": {
13142 {"bits": [0, 5], "name": "START_DELAY_COUNT"}
13145 "CP_COHER_STATUS": {
13147 {"bits": [24, 25], "name": "MEID"},
13148 {"bits": [31, 31], "name": "STATUS"}
13151 "CP_CPC_BUSY_STAT": {
13153 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
13154 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
13155 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
13156 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
13157 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
13158 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
13159 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
13160 {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
13161 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
13162 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
13163 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
13164 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
13165 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
13166 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
13167 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
13168 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
13169 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
13170 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
13171 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
13172 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
13173 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
13174 {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
13175 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
13176 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
13177 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
13178 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
13179 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
13180 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
13183 "CP_CPC_BUSY_STAT2": {
13185 {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
13186 {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
13187 {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
13188 {"bits": [7, 7], "name": "MES_TC_BUSY"},
13189 {"bits": [8, 8], "name": "MES_DMA_BUSY"},
13190 {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
13191 {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
13192 {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
13193 {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
13196 "CP_CPC_GRBM_FREE_COUNT": {
13198 {"bits": [0, 5], "name": "FREE_COUNT"}
13201 "CP_CPC_HALT_HYST_COUNT": {
13203 {"bits": [0, 3], "name": "COUNT"}
13206 "CP_CPC_SCRATCH_DATA": {
13208 {"bits": [0, 31], "name": "SCRATCH_DATA"}
13211 "CP_CPC_SCRATCH_INDEX": {
13213 {"bits": [0, 8], "name": "SCRATCH_INDEX"},
13214 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
13217 "CP_CPC_STALLED_STAT1": {
13219 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
13220 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
13221 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
13222 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
13223 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
13224 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
13225 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
13226 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
13227 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
13228 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
13229 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
13230 {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
13231 {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
13232 {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
13233 {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
13238 {"bits": [0, 0], "name": "MEC1_BUSY"},
13239 {"bits": [1, 1], "name": "MEC2_BUSY"},
13240 {"bits": [2, 2], "name": "DC0_BUSY"},
13241 {"bits": [3, 3], "name": "DC1_BUSY"},
13242 {"bits": [4, 4], "name": "RCIU1_BUSY"},
13243 {"bits": [5, 5], "name": "RCIU2_BUSY"},
13244 {"bits": [6, 6], "name": "ROQ1_BUSY"},
13245 {"bits": [7, 7], "name": "ROQ2_BUSY"},
13246 {"bits": [10, 10], "name": "TCIU_BUSY"},
13247 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
13248 {"bits": [12, 12], "name": "QU_BUSY"},
13249 {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
13250 {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
13251 {"bits": [15, 15], "name": "GCRIU_BUSY"},
13252 {"bits": [16, 16], "name": "MES_BUSY"},
13253 {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
13254 {"bits": [18, 18], "name": "RCIU3_BUSY"},
13255 {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
13256 {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
13257 {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
13258 {"bits": [31, 31], "name": "CPC_BUSY"}
13261 "CP_CPF_BUSY_STAT": {
13263 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
13264 {"bits": [1, 1], "name": "CSF_RING_BUSY"},
13265 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
13266 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
13267 {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
13268 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
13269 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
13270 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
13271 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
13272 {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
13273 {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
13274 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
13275 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
13276 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
13277 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
13278 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
13279 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
13280 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
13281 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
13282 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
13283 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
13284 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
13285 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
13286 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
13287 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
13288 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
13289 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
13290 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
13291 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
13292 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
13293 {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
13294 {"bits": [31, 31], "name": "HQD_IB_BUSY"}
13297 "CP_CPF_BUSY_STAT2": {
13299 {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
13300 {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
13301 {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
13302 {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
13303 {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
13304 {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
13305 {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
13306 {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
13307 {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
13310 "CP_CPF_GRBM_FREE_COUNT": {
13312 {"bits": [0, 2], "name": "FREE_COUNT"}
13315 "CP_CPF_STALLED_STAT1": {
13317 {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
13318 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
13319 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
13320 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
13321 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
13322 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
13323 {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
13324 {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
13325 {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
13326 {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
13327 {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
13328 {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
13329 {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
13334 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
13335 {"bits": [1, 1], "name": "CSF_BUSY"},
13336 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
13337 {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
13338 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
13339 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
13340 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
13341 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
13342 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
13343 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
13344 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
13345 {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
13346 {"bits": [14, 14], "name": "TCIU_BUSY"},
13347 {"bits": [15, 15], "name": "HQD_BUSY"},
13348 {"bits": [16, 16], "name": "PRT_BUSY"},
13349 {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
13350 {"bits": [18, 18], "name": "RCIU_BUSY"},
13351 {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
13352 {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
13353 {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
13354 {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
13355 {"bits": [23, 23], "name": "GCRIU_BUSY"},
13356 {"bits": [24, 24], "name": "MES_HQD_BUSY"},
13357 {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
13358 {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
13359 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
13360 {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
13361 {"bits": [31, 31], "name": "CPF_BUSY"}
13366 {"bits": [0, 15], "name": "DB_BASE_HI"}
13371 {"bits": [2, 31], "name": "DB_BASE_LO"}
13376 {"bits": [0, 19], "name": "DB_BUFSZ"}
13379 "CP_DB_CMD_BUFSZ": {
13381 {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
13386 {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
13387 {"bits": [1, 1], "name": "WATCH_CONTROL"},
13388 {"bits": [4, 5], "name": "MIN_AVAILSZ"},
13389 {"bits": [16, 24], "name": "BUFFER_DEPTH"},
13390 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
13391 {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
13392 {"bits": [30, 31], "name": "PIO_COUNT"}
13395 "CP_DMA_ME_CMD_ADDR_HI": {
13397 {"bits": [0, 15], "name": "ADDR_HI"},
13398 {"bits": [16, 31], "name": "RSVD"}
13401 "CP_DMA_ME_CMD_ADDR_LO": {
13403 {"bits": [0, 1], "name": "RSVD"},
13404 {"bits": [2, 31], "name": "ADDR_LO"}
13407 "CP_DMA_ME_COMMAND": {
13409 {"bits": [0, 25], "name": "BYTE_COUNT"},
13410 {"bits": [26, 26], "name": "SAS"},
13411 {"bits": [27, 27], "name": "DAS"},
13412 {"bits": [28, 28], "name": "SAIC"},
13413 {"bits": [29, 29], "name": "DAIC"},
13414 {"bits": [30, 30], "name": "RAW_WAIT"},
13415 {"bits": [31, 31], "name": "DIS_WC"}
13418 "CP_DMA_ME_DST_ADDR": {
13420 {"bits": [0, 31], "name": "DST_ADDR"}
13423 "CP_DMA_ME_DST_ADDR_HI": {
13425 {"bits": [0, 15], "name": "DST_ADDR_HI"}
13428 "CP_DMA_ME_SRC_ADDR": {
13430 {"bits": [0, 31], "name": "SRC_ADDR"}
13433 "CP_DMA_ME_SRC_ADDR_HI": {
13435 {"bits": [0, 15], "name": "SRC_ADDR_HI"}
13438 "CP_DMA_PFP_CONTROL": {
13440 {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
13441 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
13442 {"bits": [15, 15], "name": "SRC_VOLATLE"},
13443 {"bits": [20, 21], "name": "DST_SELECT"},
13444 {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
13445 {"bits": [27, 27], "name": "DST_VOLATLE"},
13446 {"bits": [29, 30], "name": "SRC_SELECT"}
13449 "CP_DMA_READ_TAGS": {
13451 {"bits": [0, 25], "name": "DMA_READ_TAG"},
13452 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
13455 "CP_DRAW_OBJECT": {
13457 {"bits": [0, 31], "name": "OBJECT"}
13460 "CP_DRAW_WINDOW_CNTL": {
13462 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
13463 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
13464 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
13465 {"bits": [8, 8], "name": "MODE"}
13468 "CP_DRAW_WINDOW_HI": {
13470 {"bits": [0, 31], "name": "WINDOW_HI"}
13473 "CP_DRAW_WINDOW_LO": {
13475 {"bits": [0, 15], "name": "MIN"},
13476 {"bits": [16, 31], "name": "MAX"}
13479 "CP_DRAW_WINDOW_MASK_HI": {
13481 {"bits": [0, 31], "name": "WINDOW_MASK_HI"}
13484 "CP_EOP_DONE_ADDR_HI": {
13486 {"bits": [0, 15], "name": "ADDR_HI"}
13489 "CP_EOP_DONE_ADDR_LO": {
13491 {"bits": [2, 31], "name": "ADDR_LO"}
13494 "CP_EOP_DONE_CNTX_ID": {
13496 {"bits": [0, 31], "name": "CNTX_ID"}
13499 "CP_EOP_DONE_DATA_CNTL": {
13501 {"bits": [16, 17], "name": "DST_SEL"},
13502 {"bits": [24, 26], "name": "INT_SEL"},
13503 {"bits": [29, 31], "name": "DATA_SEL"}
13506 "CP_EOP_DONE_DATA_HI": {
13508 {"bits": [0, 31], "name": "DATA_HI"}
13511 "CP_EOP_DONE_DATA_LO": {
13513 {"bits": [0, 31], "name": "DATA_LO"}
13516 "CP_EOP_DONE_DOORBELL": {
13518 {"bits": [2, 27], "name": "DOORBELL_OFFSET"}
13521 "CP_EOP_DONE_EVENT_CNTL": {
13523 {"bits": [12, 23], "name": "GCR_CNTL"},
13524 {"bits": [25, 26], "name": "CACHE_POLICY"},
13525 {"bits": [27, 27], "name": "EOP_VOLATILE"},
13526 {"bits": [28, 28], "name": "EXECUTE"}
13529 "CP_EOP_LAST_FENCE_HI": {
13531 {"bits": [0, 31], "name": "LAST_FENCE_HI"}
13534 "CP_EOP_LAST_FENCE_LO": {
13536 {"bits": [0, 31], "name": "LAST_FENCE_LO"}
13541 {"bits": [0, 19], "name": "IB1_OFFSET"}
13544 "CP_IB1_PREAMBLE_BEGIN": {
13546 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
13549 "CP_IB1_PREAMBLE_END": {
13551 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
13556 {"bits": [0, 19], "name": "IB2_OFFSET"}
13559 "CP_IB2_PREAMBLE_BEGIN": {
13561 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
13564 "CP_IB2_PREAMBLE_END": {
13566 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
13571 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
13574 "CP_ME_COHER_CNTL": {
13576 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
13577 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
13578 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
13579 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
13580 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
13581 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
13582 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
13583 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
13584 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
13585 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
13586 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
13587 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
13588 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
13591 "CP_ME_COHER_STATUS": {
13593 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
13594 {"bits": [31, 31], "name": "STATUS"}
13597 "CP_ME_MC_RADDR_HI": {
13599 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
13600 {"bits": [22, 23], "name": "CACHE_POLICY"}
13603 "CP_ME_MC_RADDR_LO": {
13605 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
13608 "CP_ME_MC_WADDR_HI": {
13610 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
13611 {"bits": [22, 23], "name": "CACHE_POLICY"}
13614 "CP_ME_MC_WADDR_LO": {
13616 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
13619 "CP_ME_MC_WDATA_HI": {
13621 {"bits": [0, 31], "name": "ME_MC_WDATA_HI"}
13624 "CP_ME_MC_WDATA_LO": {
13626 {"bits": [0, 31], "name": "ME_MC_WDATA_LO"}
13629 "CP_NUM_PRIM_NEEDED_COUNT0_HI": {
13631 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_HI"}
13634 "CP_NUM_PRIM_NEEDED_COUNT0_LO": {
13636 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_LO"}
13639 "CP_NUM_PRIM_NEEDED_COUNT1_HI": {
13641 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_HI"}
13644 "CP_NUM_PRIM_NEEDED_COUNT1_LO": {
13646 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_LO"}
13649 "CP_NUM_PRIM_NEEDED_COUNT2_HI": {
13651 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_HI"}
13654 "CP_NUM_PRIM_NEEDED_COUNT2_LO": {
13656 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_LO"}
13659 "CP_NUM_PRIM_NEEDED_COUNT3_HI": {
13661 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_HI"}
13664 "CP_NUM_PRIM_NEEDED_COUNT3_LO": {
13666 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_LO"}
13669 "CP_NUM_PRIM_WRITTEN_COUNT0_HI": {
13671 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_HI"}
13674 "CP_NUM_PRIM_WRITTEN_COUNT0_LO": {
13676 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_LO"}
13679 "CP_NUM_PRIM_WRITTEN_COUNT1_HI": {
13681 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_HI"}
13684 "CP_NUM_PRIM_WRITTEN_COUNT1_LO": {
13686 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_LO"}
13689 "CP_NUM_PRIM_WRITTEN_COUNT2_HI": {
13691 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_HI"}
13694 "CP_NUM_PRIM_WRITTEN_COUNT2_LO": {
13696 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_LO"}
13699 "CP_NUM_PRIM_WRITTEN_COUNT3_HI": {
13701 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_HI"}
13704 "CP_NUM_PRIM_WRITTEN_COUNT3_LO": {
13706 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_LO"}
13709 "CP_PA_CINVOC_COUNT_HI": {
13711 {"bits": [0, 31], "name": "CINVOC_COUNT_HI"}
13714 "CP_PA_CINVOC_COUNT_LO": {
13716 {"bits": [0, 31], "name": "CINVOC_COUNT_LO"}
13719 "CP_PA_CPRIM_COUNT_HI": {
13721 {"bits": [0, 31], "name": "CPRIM_COUNT_HI"}
13724 "CP_PA_CPRIM_COUNT_LO": {
13726 {"bits": [0, 31], "name": "CPRIM_COUNT_LO"}
13729 "CP_PERFMON_CNTL": {
13731 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
13732 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
13733 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
13734 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
13737 "CP_PERFMON_CNTX_CNTL": {
13739 {"bits": [31, 31], "name": "PERFMON_ENABLE"}
13742 "CP_PFP_ATOMIC_PREOP_HI": {
13744 {"bits": [0, 31], "name": "ATOMIC_PREOP_HI"}
13747 "CP_PFP_ATOMIC_PREOP_LO": {
13749 {"bits": [0, 31], "name": "ATOMIC_PREOP_LO"}
13752 "CP_PFP_COMPLETION_STATUS": {
13754 {"bits": [0, 1], "name": "STATUS"}
13757 "CP_PFP_GDS_ATOMIC0_PREOP_HI": {
13759 {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_HI"}
13762 "CP_PFP_GDS_ATOMIC0_PREOP_LO": {
13764 {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_LO"}
13767 "CP_PFP_GDS_ATOMIC1_PREOP_HI": {
13769 {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_HI"}
13772 "CP_PFP_GDS_ATOMIC1_PREOP_LO": {
13774 {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_LO"}
13777 "CP_PFP_IB_CONTROL": {
13779 {"bits": [0, 7], "name": "IB_EN"}
13782 "CP_PFP_LOAD_CONTROL": {
13784 {"bits": [0, 0], "name": "CONFIG_REG_EN"},
13785 {"bits": [1, 1], "name": "CNTX_REG_EN"},
13786 {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
13787 {"bits": [24, 24], "name": "SH_CS_REG_EN"}
13790 "CP_PFP_METADATA_BASE_ADDR": {
13792 {"bits": [0, 31], "name": "ADDR_LO"}
13797 {"bits": [0, 1], "name": "PIPE_ID"}
13800 "CP_PIPE_STATS_ADDR_HI": {
13802 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
13805 "CP_PIPE_STATS_ADDR_LO": {
13807 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
13810 "CP_PIPE_STATS_CONTROL": {
13812 {"bits": [25, 26], "name": "CACHE_POLICY"}
13815 "CP_PRED_NOT_VISIBLE": {
13817 {"bits": [0, 0], "name": "NOT_VISIBLE"}
13822 {"bits": [0, 19], "name": "RB_OFFSET"}
13825 "CP_SAMPLE_STATUS": {
13827 {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
13828 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
13829 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
13830 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
13831 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
13832 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
13833 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
13834 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
13837 "CP_SCRATCH_INDEX": {
13839 {"bits": [0, 7], "name": "SCRATCH_INDEX"},
13840 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
13843 "CP_SC_PSINVOC_COUNT0_HI": {
13845 {"bits": [0, 31], "name": "PSINVOC_COUNT0_HI"}
13848 "CP_SC_PSINVOC_COUNT0_LO": {
13850 {"bits": [0, 31], "name": "PSINVOC_COUNT0_LO"}
13853 "CP_SC_PSINVOC_COUNT1_LO": {
13855 {"bits": [0, 31], "name": "OBSOLETE"}
13858 "CP_SEM_WAIT_TIMER": {
13860 {"bits": [0, 31], "name": "SEM_WAIT_TIMER"}
13863 "CP_SIG_SEM_ADDR_HI": {
13865 {"bits": [0, 15], "name": "SEM_ADDR_HI"},
13866 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
13867 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
13868 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
13869 {"bits": [29, 31], "name": "SEM_SELECT"}
13872 "CP_SIG_SEM_ADDR_LO": {
13874 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
13875 {"bits": [3, 31], "name": "SEM_ADDR_LO"}
13878 "CP_STREAM_OUT_ADDR_HI": {
13880 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
13883 "CP_STREAM_OUT_ADDR_LO": {
13885 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
13888 "CP_STRMOUT_CNTL": {
13890 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
13895 {"bits": [0, 15], "name": "ST_BASE_HI"}
13900 {"bits": [2, 31], "name": "ST_BASE_LO"}
13905 {"bits": [0, 19], "name": "ST_BUFSZ"}
13908 "CP_ST_CMD_BUFSZ": {
13910 {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
13913 "CP_VGT_CSINVOC_COUNT_HI": {
13915 {"bits": [0, 31], "name": "CSINVOC_COUNT_HI"}
13918 "CP_VGT_CSINVOC_COUNT_LO": {
13920 {"bits": [0, 31], "name": "CSINVOC_COUNT_LO"}
13923 "CP_VGT_DSINVOC_COUNT_HI": {
13925 {"bits": [0, 31], "name": "DSINVOC_COUNT_HI"}
13928 "CP_VGT_DSINVOC_COUNT_LO": {
13930 {"bits": [0, 31], "name": "DSINVOC_COUNT_LO"}
13933 "CP_VGT_GSINVOC_COUNT_HI": {
13935 {"bits": [0, 31], "name": "GSINVOC_COUNT_HI"}
13938 "CP_VGT_GSINVOC_COUNT_LO": {
13940 {"bits": [0, 31], "name": "GSINVOC_COUNT_LO"}
13943 "CP_VGT_GSPRIM_COUNT_HI": {
13945 {"bits": [0, 31], "name": "GSPRIM_COUNT_HI"}
13948 "CP_VGT_GSPRIM_COUNT_LO": {
13950 {"bits": [0, 31], "name": "GSPRIM_COUNT_LO"}
13953 "CP_VGT_HSINVOC_COUNT_HI": {
13955 {"bits": [0, 31], "name": "HSINVOC_COUNT_HI"}
13958 "CP_VGT_HSINVOC_COUNT_LO": {
13960 {"bits": [0, 31], "name": "HSINVOC_COUNT_LO"}
13963 "CP_VGT_IAPRIM_COUNT_HI": {
13965 {"bits": [0, 31], "name": "IAPRIM_COUNT_HI"}
13968 "CP_VGT_IAPRIM_COUNT_LO": {
13970 {"bits": [0, 31], "name": "IAPRIM_COUNT_LO"}
13973 "CP_VGT_IAVERT_COUNT_HI": {
13975 {"bits": [0, 31], "name": "IAVERT_COUNT_HI"}
13978 "CP_VGT_IAVERT_COUNT_LO": {
13980 {"bits": [0, 31], "name": "IAVERT_COUNT_LO"}
13983 "CP_VGT_VSINVOC_COUNT_HI": {
13985 {"bits": [0, 31], "name": "VSINVOC_COUNT_HI"}
13988 "CP_VGT_VSINVOC_COUNT_LO": {
13990 {"bits": [0, 31], "name": "VSINVOC_COUNT_LO"}
13995 {"bits": [0, 3], "name": "VMID"}
13998 "CP_WAIT_REG_MEM_TIMEOUT": {
14000 {"bits": [0, 31], "name": "WAIT_REG_MEM_TIMEOUT"}
14005 {"bits": [0, 2], "name": "SRC_STATE_ID"}
14008 "DB_ALPHA_TO_MASK": {
14010 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
14011 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
14012 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
14013 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
14014 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
14015 {"bits": [16, 16], "name": "OFFSET_ROUND"}
14018 "DB_COUNT_CONTROL": {
14020 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
14021 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
14022 {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
14023 {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
14024 {"bits": [4, 6], "name": "SAMPLE_RATE"},
14025 {"bits": [8, 11], "name": "ZPASS_ENABLE"},
14026 {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
14027 {"bits": [16, 19], "name": "SFAIL_ENABLE"},
14028 {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
14029 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
14030 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
14033 "DB_DEPTH_BOUNDS_MAX": {
14035 {"bits": [0, 31], "name": "MAX"}
14038 "DB_DEPTH_BOUNDS_MIN": {
14040 {"bits": [0, 31], "name": "MIN"}
14043 "DB_DEPTH_CLEAR": {
14045 {"bits": [0, 31], "name": "DEPTH_CLEAR"}
14048 "DB_DEPTH_CONTROL": {
14050 {"bits": [0, 0], "name": "STENCIL_ENABLE"},
14051 {"bits": [1, 1], "name": "Z_ENABLE"},
14052 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
14053 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
14054 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
14055 {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
14056 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
14057 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
14058 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
14059 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
14062 "DB_DEPTH_SIZE_XY": {
14064 {"bits": [0, 13], "name": "X_MAX"},
14065 {"bits": [16, 29], "name": "Y_MAX"}
14070 {"bits": [0, 10], "name": "SLICE_START"},
14071 {"bits": [11, 12], "name": "SLICE_START_HI"},
14072 {"bits": [13, 23], "name": "SLICE_MAX"},
14073 {"bits": [24, 24], "name": "Z_READ_ONLY"},
14074 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
14075 {"bits": [26, 29], "name": "MIPID"},
14076 {"bits": [30, 31], "name": "SLICE_MAX_HI"}
14079 "DB_DFSM_CONTROL": {
14081 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
14082 {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
14083 {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
14088 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
14089 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
14090 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
14091 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
14092 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
14093 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
14094 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
14095 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
14096 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
14097 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
14098 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
14099 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
14102 "DB_HTILE_DATA_BASE": {
14104 {"bits": [0, 31], "name": "BASE_256B"}
14107 "DB_HTILE_SURFACE": {
14109 {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
14110 {"bits": [1, 1], "name": "FULL_CACHE"},
14111 {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
14112 {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
14113 {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
14114 {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
14115 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
14116 {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
14117 {"bits": [18, 18], "name": "PIPE_ALIGNED"}
14120 "DB_OCCLUSION_COUNT0_HI": {
14122 {"bits": [0, 30], "name": "COUNT_HI"}
14125 "DB_OCCLUSION_COUNT0_LOW": {
14127 {"bits": [0, 31], "name": "COUNT_LOW"}
14130 "DB_PRELOAD_CONTROL": {
14132 {"bits": [0, 7], "name": "START_X"},
14133 {"bits": [8, 15], "name": "START_Y"},
14134 {"bits": [16, 23], "name": "MAX_X"},
14135 {"bits": [24, 31], "name": "MAX_Y"}
14138 "DB_RENDER_CONTROL": {
14140 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
14141 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
14142 {"bits": [2, 2], "name": "DEPTH_COPY"},
14143 {"bits": [3, 3], "name": "STENCIL_COPY"},
14144 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
14145 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
14146 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
14147 {"bits": [7, 7], "name": "COPY_CENTROID"},
14148 {"bits": [8, 11], "name": "COPY_SAMPLE"},
14149 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}
14152 "DB_RENDER_OVERRIDE": {
14154 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
14155 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
14156 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
14157 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
14158 {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
14159 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
14160 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
14161 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
14162 {"bits": [11, 11], "name": "FORCE_Z_READ"},
14163 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
14164 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
14165 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
14166 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
14167 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
14168 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
14169 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
14170 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
14171 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
14172 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
14173 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
14174 {"bits": [29, 29], "name": "FORCE_Z_VALID"},
14175 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
14176 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
14179 "DB_RENDER_OVERRIDE2": {
14181 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
14182 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
14183 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
14184 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
14185 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
14186 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
14187 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
14188 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
14189 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
14190 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
14191 {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
14192 {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
14193 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
14194 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
14195 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
14196 {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"}
14199 "DB_RESERVED_REG_1": {
14201 {"bits": [0, 10], "name": "FIELD_1"},
14202 {"bits": [11, 21], "name": "FIELD_2"}
14205 "DB_RESERVED_REG_2": {
14207 {"bits": [0, 3], "name": "FIELD_1"},
14208 {"bits": [4, 7], "name": "FIELD_2"},
14209 {"bits": [8, 12], "name": "FIELD_3"},
14210 {"bits": [13, 14], "name": "FIELD_4"},
14211 {"bits": [15, 16], "name": "FIELD_5"},
14212 {"bits": [17, 18], "name": "FIELD_6"},
14213 {"bits": [19, 20], "name": "FIELD_7"},
14214 {"bits": [28, 31], "name": "RESOURCE_LEVEL"}
14217 "DB_RESERVED_REG_3": {
14219 {"bits": [0, 21], "name": "FIELD_1"}
14222 "DB_RMI_L2_CACHE_CONTROL": {
14224 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
14225 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
14226 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
14227 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
14228 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
14229 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
14230 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
14231 {"bits": [24, 24], "name": "Z_BIG_PAGE"},
14232 {"bits": [25, 25], "name": "S_BIG_PAGE"}
14235 "DB_SHADER_CONTROL": {
14237 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
14238 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
14239 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
14240 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
14241 {"bits": [6, 6], "name": "KILL_ENABLE"},
14242 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
14243 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
14244 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
14245 {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
14246 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
14247 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
14248 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
14249 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
14250 {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
14251 {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
14252 {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"},
14253 {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"}
14256 "DB_SRESULTS_COMPARE_STATE0": {
14258 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
14259 {"bits": [4, 11], "name": "COMPAREVALUE0"},
14260 {"bits": [12, 19], "name": "COMPAREMASK0"},
14261 {"bits": [24, 24], "name": "ENABLE0"}
14264 "DB_SRESULTS_COMPARE_STATE1": {
14266 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
14267 {"bits": [4, 11], "name": "COMPAREVALUE1"},
14268 {"bits": [12, 19], "name": "COMPAREMASK1"},
14269 {"bits": [24, 24], "name": "ENABLE1"}
14272 "DB_STENCILREFMASK": {
14274 {"bits": [0, 7], "name": "STENCILTESTVAL"},
14275 {"bits": [8, 15], "name": "STENCILMASK"},
14276 {"bits": [16, 23], "name": "STENCILWRITEMASK"},
14277 {"bits": [24, 31], "name": "STENCILOPVAL"}
14280 "DB_STENCILREFMASK_BF": {
14282 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
14283 {"bits": [8, 15], "name": "STENCILMASK_BF"},
14284 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
14285 {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
14288 "DB_STENCIL_CLEAR": {
14290 {"bits": [0, 7], "name": "CLEAR"}
14293 "DB_STENCIL_CONTROL": {
14295 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
14296 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
14297 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
14298 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
14299 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
14300 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
14303 "DB_STENCIL_INFO": {
14305 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
14306 {"bits": [4, 8], "name": "SW_MODE"},
14307 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
14308 {"bits": [11, 11], "name": "ITERATE_FLUSH"},
14309 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
14310 {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
14311 {"bits": [20, 20], "name": "ITERATE_256"},
14312 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
14313 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
14318 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
14319 {"bits": [2, 3], "name": "NUM_SAMPLES"},
14320 {"bits": [4, 8], "name": "SW_MODE"},
14321 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
14322 {"bits": [11, 11], "name": "ITERATE_FLUSH"},
14323 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
14324 {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
14325 {"bits": [16, 19], "name": "MAXMIP"},
14326 {"bits": [20, 20], "name": "ITERATE_256"},
14327 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
14328 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
14329 {"bits": [28, 28], "name": "READ_SIZE"},
14330 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
14331 {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
14334 "DB_Z_READ_BASE_HI": {
14336 {"bits": [0, 7], "name": "BASE_HI"}
14339 "GB_ADDR_CONFIG": {
14341 {"bits": [0, 2], "name": "NUM_PIPES"},
14342 {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
14343 {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
14344 {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
14345 {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
14348 "GB_MACROTILE_MODE0": {
14350 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
14351 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
14352 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
14353 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
14358 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
14359 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
14360 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
14361 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
14362 {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
14365 "GCEA_PERFCOUNTER2_MODE": {
14367 {"bits": [0, 1], "name": "COMPARE_MODE0"},
14368 {"bits": [2, 3], "name": "COMPARE_MODE1"},
14369 {"bits": [4, 5], "name": "COMPARE_MODE2"},
14370 {"bits": [6, 7], "name": "COMPARE_MODE3"},
14371 {"bits": [8, 11], "name": "COMPARE_VALUE0"},
14372 {"bits": [12, 15], "name": "COMPARE_VALUE1"},
14373 {"bits": [16, 19], "name": "COMPARE_VALUE2"},
14374 {"bits": [20, 23], "name": "COMPARE_VALUE3"}
14377 "GCR_PERFCOUNTER1_SELECT": {
14379 {"bits": [0, 8], "name": "PERF_SEL"},
14380 {"bits": [24, 27], "name": "PERF_MODE"},
14381 {"bits": [28, 31], "name": "CNTL_MODE"}
14384 "GC_ATC_L2_PERFCOUNTER0_CFG": {
14386 {"bits": [0, 7], "name": "PERF_SEL"},
14387 {"bits": [8, 15], "name": "PERF_SEL_END"},
14388 {"bits": [24, 27], "name": "PERF_MODE"},
14389 {"bits": [28, 28], "name": "ENABLE"},
14390 {"bits": [29, 29], "name": "CLEAR"}
14393 "GC_ATC_L2_PERFCOUNTER_HI": {
14395 {"bits": [0, 15], "name": "COUNTER_HI"},
14396 {"bits": [16, 31], "name": "COMPARE_VALUE"}
14399 "GC_ATC_L2_PERFCOUNTER_LO": {
14401 {"bits": [0, 31], "name": "COUNTER_LO"}
14404 "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL": {
14406 {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
14407 {"bits": [8, 15], "name": "START_TRIGGER"},
14408 {"bits": [16, 23], "name": "STOP_TRIGGER"},
14409 {"bits": [24, 24], "name": "ENABLE_ANY"},
14410 {"bits": [25, 25], "name": "CLEAR_ALL"},
14411 {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
14416 {"bits": [0, 15], "name": "BASE"},
14417 {"bits": [16, 31], "name": "UNUSED"}
14422 {"bits": [0, 5], "name": "AINC"},
14423 {"bits": [6, 7], "name": "UNUSED1"},
14424 {"bits": [8, 9], "name": "DMODE"},
14425 {"bits": [10, 31], "name": "UNUSED2"}
14428 "GDS_ATOM_COMPLETE": {
14430 {"bits": [0, 0], "name": "COMPLETE"},
14431 {"bits": [1, 31], "name": "UNUSED"}
14436 {"bits": [0, 31], "name": "DST"}
14439 "GDS_ATOM_OFFSET0": {
14441 {"bits": [0, 7], "name": "OFFSET0"},
14442 {"bits": [8, 31], "name": "UNUSED"}
14445 "GDS_ATOM_OFFSET1": {
14447 {"bits": [0, 7], "name": "OFFSET1"},
14448 {"bits": [8, 31], "name": "UNUSED"}
14453 {"bits": [0, 7], "name": "OP"},
14454 {"bits": [8, 31], "name": "UNUSED"}
14459 {"bits": [0, 15], "name": "SIZE"},
14460 {"bits": [16, 31], "name": "UNUSED"}
14463 "GDS_GWS_RESOURCE": {
14465 {"bits": [0, 0], "name": "FLAG"},
14466 {"bits": [1, 12], "name": "COUNTER"},
14467 {"bits": [13, 13], "name": "TYPE"},
14468 {"bits": [14, 14], "name": "DED"},
14469 {"bits": [15, 15], "name": "RELEASE_ALL"},
14470 {"bits": [16, 26], "name": "HEAD_QUEUE"},
14471 {"bits": [27, 27], "name": "HEAD_VALID"},
14472 {"bits": [28, 28], "name": "HEAD_FLAG"},
14473 {"bits": [29, 29], "name": "HALTED"},
14474 {"bits": [30, 31], "name": "UNUSED1"}
14477 "GDS_GWS_RESOURCE_CNT": {
14479 {"bits": [0, 15], "name": "RESOURCE_CNT"},
14480 {"bits": [16, 31], "name": "UNUSED"}
14483 "GDS_GWS_RESOURCE_CNTL": {
14485 {"bits": [0, 5], "name": "INDEX"},
14486 {"bits": [6, 31], "name": "UNUSED"}
14489 "GDS_OA_ADDRESS": {
14491 {"bits": [0, 15], "name": "DS_ADDRESS"},
14492 {"bits": [16, 19], "name": "CRAWLER_TYPE"},
14493 {"bits": [20, 23], "name": "CRAWLER"},
14494 {"bits": [24, 29], "name": "UNUSED"},
14495 {"bits": [30, 30], "name": "NO_ALLOC"},
14496 {"bits": [31, 31], "name": "ENABLE"}
14501 {"bits": [0, 3], "name": "INDEX"},
14502 {"bits": [4, 31], "name": "UNUSED"}
14505 "GDS_OA_COUNTER": {
14507 {"bits": [0, 31], "name": "SPACE_AVAILABLE"}
14512 {"bits": [0, 30], "name": "VALUE"},
14513 {"bits": [31, 31], "name": "INCDEC"}
14516 "GDS_OA_RING_SIZE": {
14518 {"bits": [0, 31], "name": "RING_SIZE"}
14523 {"bits": [0, 31], "name": "READ_ADDR"}
14526 "GDS_RD_BURST_ADDR": {
14528 {"bits": [0, 31], "name": "BURST_ADDR"}
14531 "GDS_RD_BURST_COUNT": {
14533 {"bits": [0, 31], "name": "BURST_COUNT"}
14536 "GDS_RD_BURST_DATA": {
14538 {"bits": [0, 31], "name": "BURST_DATA"}
14543 {"bits": [0, 31], "name": "READ_DATA"}
14546 "GDS_WRITE_COMPLETE": {
14548 {"bits": [0, 31], "name": "WRITE_COMPLETE"}
14553 {"bits": [0, 31], "name": "WRITE_ADDR"}
14558 {"bits": [0, 31], "name": "WRITE_DATA"}
14563 {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
14564 {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
14565 {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
14566 {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
14569 "GE_DMA_FIRST_INDEX": {
14571 {"bits": [0, 31], "name": "FIRST_INDEX"}
14574 "GE_MAX_OUTPUT_PER_SUBGROUP": {
14576 {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
14579 "GE_NGG_SUBGRP_CNTL": {
14581 {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
14582 {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
14587 {"bits": [0, 0], "name": "OVERSUB_EN"},
14588 {"bits": [1, 10], "name": "NUM_PC_LINES"}
14591 "GE_PERFCOUNTER0_SELECT": {
14593 {"bits": [0, 9], "name": "PERF_SEL0"},
14594 {"bits": [10, 19], "name": "PERF_SEL1"},
14595 {"bits": [20, 23], "name": "CNTR_MODE"},
14596 {"bits": [24, 27], "name": "PERF_MODE0"},
14597 {"bits": [28, 31], "name": "PERF_MODE1"}
14600 "GE_PERFCOUNTER0_SELECT1": {
14602 {"bits": [0, 9], "name": "PERF_SEL2"},
14603 {"bits": [10, 19], "name": "PERF_SEL3"},
14604 {"bits": [24, 27], "name": "PERF_MODE2"},
14605 {"bits": [28, 31], "name": "PERF_MODE3"}
14608 "GE_PERFCOUNTER4_SELECT": {
14610 {"bits": [0, 9], "name": "PERF_SEL0"},
14611 {"bits": [28, 31], "name": "PERF_MODE"}
14614 "GE_STEREO_CNTL": {
14616 {"bits": [0, 2], "name": "RT_SLICE"},
14617 {"bits": [3, 6], "name": "VIEWPORT"},
14618 {"bits": [8, 8], "name": "EN_STEREO"}
14621 "GE_USER_VGPR_EN": {
14623 {"bits": [0, 0], "name": "EN_USER_VGPR1"},
14624 {"bits": [1, 1], "name": "EN_USER_VGPR2"},
14625 {"bits": [2, 2], "name": "EN_USER_VGPR3"}
14628 "GRBM_GFX_INDEX": {
14630 {"bits": [0, 7], "name": "INSTANCE_INDEX"},
14631 {"bits": [8, 15], "name": "SA_INDEX"},
14632 {"bits": [16, 23], "name": "SE_INDEX"},
14633 {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
14634 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
14635 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
14638 "GRBM_PERFCOUNTER0_SELECT": {
14640 {"bits": [0, 5], "name": "PERF_SEL"},
14641 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
14642 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
14643 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
14644 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
14645 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
14646 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
14647 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
14648 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
14649 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
14650 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
14651 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
14652 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
14653 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
14654 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
14655 {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
14656 {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
14657 {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
14658 {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
14659 {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
14662 "GRBM_PERFCOUNTER0_SELECT_HI": {
14664 {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
14665 {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
14666 {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
14667 {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
14668 {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
14669 {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
14670 {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
14671 {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
14674 "GRBM_SE0_PERFCOUNTER_SELECT": {
14676 {"bits": [0, 5], "name": "PERF_SEL"},
14677 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
14678 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
14679 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
14680 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
14681 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
14682 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
14683 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
14684 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
14685 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
14686 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
14687 {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
14688 {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
14689 {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
14690 {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
14695 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
14696 {"bits": [5, 5], "name": "RSMU_RQ_PENDING"},
14697 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
14698 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
14699 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
14700 {"bits": [12, 12], "name": "DB_CLEAN"},
14701 {"bits": [13, 13], "name": "CB_CLEAN"},
14702 {"bits": [14, 14], "name": "TA_BUSY"},
14703 {"bits": [15, 15], "name": "GDS_BUSY"},
14704 {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
14705 {"bits": [20, 20], "name": "SX_BUSY"},
14706 {"bits": [21, 21], "name": "GE_BUSY"},
14707 {"bits": [22, 22], "name": "SPI_BUSY"},
14708 {"bits": [23, 23], "name": "BCI_BUSY"},
14709 {"bits": [24, 24], "name": "SC_BUSY"},
14710 {"bits": [25, 25], "name": "PA_BUSY"},
14711 {"bits": [26, 26], "name": "DB_BUSY"},
14712 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
14713 {"bits": [29, 29], "name": "CP_BUSY"},
14714 {"bits": [30, 30], "name": "CB_BUSY"},
14715 {"bits": [31, 31], "name": "GUI_ACTIVE"}
14720 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
14721 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
14722 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
14723 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
14724 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
14725 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
14726 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
14727 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
14728 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
14729 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
14730 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
14731 {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
14732 {"bits": [15, 15], "name": "UTCL2_BUSY"},
14733 {"bits": [16, 16], "name": "EA_BUSY"},
14734 {"bits": [17, 17], "name": "RMI_BUSY"},
14735 {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
14736 {"bits": [19, 19], "name": "CPF_RQ_PENDING"},
14737 {"bits": [20, 20], "name": "EA_LINK_BUSY"},
14738 {"bits": [21, 21], "name": "SDMA_BUSY"},
14739 {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
14740 {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
14741 {"bits": [24, 24], "name": "RLC_BUSY"},
14742 {"bits": [25, 25], "name": "TCP_BUSY"},
14743 {"bits": [28, 28], "name": "CPF_BUSY"},
14744 {"bits": [29, 29], "name": "CPC_BUSY"},
14745 {"bits": [30, 30], "name": "CPG_BUSY"},
14746 {"bits": [31, 31], "name": "CPAXI_BUSY"}
14751 {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
14752 {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"},
14753 {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
14754 {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
14755 {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
14756 {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"},
14757 {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"},
14758 {"bits": [13, 13], "name": "PH_BUSY"},
14759 {"bits": [14, 14], "name": "CH_BUSY"},
14760 {"bits": [15, 15], "name": "GL2CC_BUSY"},
14761 {"bits": [16, 16], "name": "GL1CC_BUSY"},
14762 {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
14763 {"bits": [29, 29], "name": "GUS_BUSY"},
14764 {"bits": [30, 30], "name": "UTCL1_BUSY"},
14765 {"bits": [31, 31], "name": "PMM_BUSY"}
14768 "GRBM_STATUS_SE0": {
14770 {"bits": [1, 1], "name": "DB_CLEAN"},
14771 {"bits": [2, 2], "name": "CB_CLEAN"},
14772 {"bits": [3, 3], "name": "UTCL1_BUSY"},
14773 {"bits": [4, 4], "name": "TCP_BUSY"},
14774 {"bits": [5, 5], "name": "GL1CC_BUSY"},
14775 {"bits": [21, 21], "name": "RMI_BUSY"},
14776 {"bits": [22, 22], "name": "BCI_BUSY"},
14777 {"bits": [24, 24], "name": "PA_BUSY"},
14778 {"bits": [25, 25], "name": "TA_BUSY"},
14779 {"bits": [26, 26], "name": "SX_BUSY"},
14780 {"bits": [27, 27], "name": "SPI_BUSY"},
14781 {"bits": [29, 29], "name": "SC_BUSY"},
14782 {"bits": [30, 30], "name": "DB_BUSY"},
14783 {"bits": [31, 31], "name": "CB_BUSY"}
14786 "IA_MULTI_VGT_PARAM": {
14788 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
14789 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
14790 {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
14791 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
14792 {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
14793 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
14796 "IA_MULTI_VGT_PARAM_PIPED": {
14798 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
14799 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
14800 {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
14801 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
14802 {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
14803 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
14804 {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
14805 {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
14806 {"bits": [23, 23], "name": "HW_USE_ONLY"}
14809 "PA_CL_CLIP_CNTL": {
14811 {"bits": [0, 0], "name": "UCP_ENA_0"},
14812 {"bits": [1, 1], "name": "UCP_ENA_1"},
14813 {"bits": [2, 2], "name": "UCP_ENA_2"},
14814 {"bits": [3, 3], "name": "UCP_ENA_3"},
14815 {"bits": [4, 4], "name": "UCP_ENA_4"},
14816 {"bits": [5, 5], "name": "UCP_ENA_5"},
14817 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
14818 {"bits": [14, 15], "name": "PS_UCP_MODE"},
14819 {"bits": [16, 16], "name": "CLIP_DISABLE"},
14820 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
14821 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
14822 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
14823 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
14824 {"bits": [21, 21], "name": "VTX_KILL_OR"},
14825 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
14826 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
14827 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
14828 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
14829 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
14830 {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
14833 "PA_CL_NANINF_CNTL": {
14835 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
14836 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
14837 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
14838 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
14839 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
14840 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
14841 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
14842 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
14843 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
14844 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
14845 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
14846 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
14847 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
14848 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
14849 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
14850 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
14853 "PA_CL_NGG_CNTL": {
14855 {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
14856 {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"}
14859 "PA_CL_OBJPRIM_ID_CNTL": {
14861 {"bits": [0, 0], "name": "OBJ_ID_SEL"},
14862 {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"}
14867 {"bits": [0, 31], "name": "DATA_REGISTER"}
14870 "PA_CL_VPORT_XOFFSET": {
14872 {"bits": [0, 31], "name": "VPORT_XOFFSET"}
14875 "PA_CL_VPORT_XSCALE": {
14877 {"bits": [0, 31], "name": "VPORT_XSCALE"}
14880 "PA_CL_VPORT_YOFFSET": {
14882 {"bits": [0, 31], "name": "VPORT_YOFFSET"}
14885 "PA_CL_VPORT_YSCALE": {
14887 {"bits": [0, 31], "name": "VPORT_YSCALE"}
14890 "PA_CL_VPORT_ZOFFSET": {
14892 {"bits": [0, 31], "name": "VPORT_ZOFFSET"}
14895 "PA_CL_VPORT_ZSCALE": {
14897 {"bits": [0, 31], "name": "VPORT_ZSCALE"}
14900 "PA_CL_VS_OUT_CNTL": {
14902 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
14903 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
14904 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
14905 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
14906 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
14907 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
14908 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
14909 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
14910 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
14911 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
14912 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
14913 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
14914 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
14915 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
14916 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
14917 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
14918 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
14919 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
14920 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
14921 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
14922 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
14923 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
14924 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
14925 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
14926 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
14927 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
14928 {"bits": [26, 26], "name": "USE_VTX_SHD_OBJPRIM_ID"},
14929 {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"}
14932 "PA_CL_VTE_CNTL": {
14934 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
14935 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
14936 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
14937 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
14938 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
14939 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
14940 {"bits": [8, 8], "name": "VTX_XY_FMT"},
14941 {"bits": [9, 9], "name": "VTX_Z_FMT"},
14942 {"bits": [10, 10], "name": "VTX_W0_FMT"},
14943 {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
14946 "PA_SC_AA_CONFIG": {
14948 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
14949 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
14950 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
14951 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
14952 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
14953 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}
14956 "PA_SC_AA_MASK_X0Y0_X1Y0": {
14958 {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
14959 {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
14962 "PA_SC_AA_MASK_X0Y1_X1Y1": {
14964 {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
14965 {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
14968 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
14970 {"bits": [0, 3], "name": "S0_X"},
14971 {"bits": [4, 7], "name": "S0_Y"},
14972 {"bits": [8, 11], "name": "S1_X"},
14973 {"bits": [12, 15], "name": "S1_Y"},
14974 {"bits": [16, 19], "name": "S2_X"},
14975 {"bits": [20, 23], "name": "S2_Y"},
14976 {"bits": [24, 27], "name": "S3_X"},
14977 {"bits": [28, 31], "name": "S3_Y"}
14980 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
14982 {"bits": [0, 3], "name": "S4_X"},
14983 {"bits": [4, 7], "name": "S4_Y"},
14984 {"bits": [8, 11], "name": "S5_X"},
14985 {"bits": [12, 15], "name": "S5_Y"},
14986 {"bits": [16, 19], "name": "S6_X"},
14987 {"bits": [20, 23], "name": "S6_Y"},
14988 {"bits": [24, 27], "name": "S7_X"},
14989 {"bits": [28, 31], "name": "S7_Y"}
14992 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
14994 {"bits": [0, 3], "name": "S8_X"},
14995 {"bits": [4, 7], "name": "S8_Y"},
14996 {"bits": [8, 11], "name": "S9_X"},
14997 {"bits": [12, 15], "name": "S9_Y"},
14998 {"bits": [16, 19], "name": "S10_X"},
14999 {"bits": [20, 23], "name": "S10_Y"},
15000 {"bits": [24, 27], "name": "S11_X"},
15001 {"bits": [28, 31], "name": "S11_Y"}
15004 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
15006 {"bits": [0, 3], "name": "S12_X"},
15007 {"bits": [4, 7], "name": "S12_Y"},
15008 {"bits": [8, 11], "name": "S13_X"},
15009 {"bits": [12, 15], "name": "S13_Y"},
15010 {"bits": [16, 19], "name": "S14_X"},
15011 {"bits": [20, 23], "name": "S14_Y"},
15012 {"bits": [24, 27], "name": "S15_X"},
15013 {"bits": [28, 31], "name": "S15_Y"}
15016 "PA_SC_BINNER_CNTL_0": {
15018 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
15019 {"bits": [2, 2], "name": "BIN_SIZE_X"},
15020 {"bits": [3, 3], "name": "BIN_SIZE_Y"},
15021 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
15022 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
15023 {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
15024 {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
15025 {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
15026 {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
15027 {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
15028 {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
15029 {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
15032 "PA_SC_BINNER_CNTL_1": {
15034 {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
15035 {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
15038 "PA_SC_CENTROID_PRIORITY_0": {
15040 {"bits": [0, 3], "name": "DISTANCE_0"},
15041 {"bits": [4, 7], "name": "DISTANCE_1"},
15042 {"bits": [8, 11], "name": "DISTANCE_2"},
15043 {"bits": [12, 15], "name": "DISTANCE_3"},
15044 {"bits": [16, 19], "name": "DISTANCE_4"},
15045 {"bits": [20, 23], "name": "DISTANCE_5"},
15046 {"bits": [24, 27], "name": "DISTANCE_6"},
15047 {"bits": [28, 31], "name": "DISTANCE_7"}
15050 "PA_SC_CENTROID_PRIORITY_1": {
15052 {"bits": [0, 3], "name": "DISTANCE_8"},
15053 {"bits": [4, 7], "name": "DISTANCE_9"},
15054 {"bits": [8, 11], "name": "DISTANCE_10"},
15055 {"bits": [12, 15], "name": "DISTANCE_11"},
15056 {"bits": [16, 19], "name": "DISTANCE_12"},
15057 {"bits": [20, 23], "name": "DISTANCE_13"},
15058 {"bits": [24, 27], "name": "DISTANCE_14"},
15059 {"bits": [28, 31], "name": "DISTANCE_15"}
15062 "PA_SC_CLIPRECT_0_TL": {
15064 {"bits": [0, 14], "name": "TL_X"},
15065 {"bits": [16, 30], "name": "TL_Y"}
15068 "PA_SC_CLIPRECT_RULE": {
15070 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
15073 "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": {
15075 {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
15076 {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
15077 {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
15078 {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
15079 {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
15080 {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
15081 {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
15082 {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
15083 {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
15084 {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
15085 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
15086 {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
15087 {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
15088 {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
15089 {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
15090 {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
15091 {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
15092 {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
15093 {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
15094 {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
15097 "PA_SC_EDGERULE": {
15099 {"bits": [0, 3], "name": "ER_TRI"},
15100 {"bits": [4, 7], "name": "ER_POINT"},
15101 {"bits": [8, 11], "name": "ER_RECT"},
15102 {"bits": [12, 17], "name": "ER_LINE_LR"},
15103 {"bits": [18, 23], "name": "ER_LINE_RL"},
15104 {"bits": [24, 27], "name": "ER_LINE_TB"},
15105 {"bits": [28, 31], "name": "ER_LINE_BT"}
15108 "PA_SC_HORIZ_GRID": {
15110 {"bits": [0, 7], "name": "TOP_QTR"},
15111 {"bits": [8, 15], "name": "TOP_HALF"},
15112 {"bits": [16, 23], "name": "BOT_HALF"},
15113 {"bits": [24, 31], "name": "BOT_QTR"}
15116 "PA_SC_LINE_CNTL": {
15118 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
15119 {"bits": [10, 10], "name": "LAST_PIXEL"},
15120 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
15121 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
15122 {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
15125 "PA_SC_LINE_STIPPLE": {
15127 {"bits": [0, 15], "name": "LINE_PATTERN"},
15128 {"bits": [16, 23], "name": "REPEAT_COUNT"},
15129 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
15130 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
15133 "PA_SC_LINE_STIPPLE_STATE": {
15135 {"bits": [0, 3], "name": "CURRENT_PTR"},
15136 {"bits": [8, 15], "name": "CURRENT_COUNT"}
15139 "PA_SC_MODE_CNTL_0": {
15141 {"bits": [0, 0], "name": "MSAA_ENABLE"},
15142 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
15143 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
15144 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
15145 {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"},
15146 {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
15147 {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
15150 "PA_SC_MODE_CNTL_1": {
15152 {"bits": [0, 0], "name": "WALK_SIZE"},
15153 {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
15154 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
15155 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
15156 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
15157 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
15158 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
15159 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
15160 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
15161 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
15162 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
15163 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
15164 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
15165 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
15166 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
15167 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
15168 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
15169 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
15170 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
15171 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
15172 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
15173 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
15174 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
15175 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
15178 "PA_SC_NGG_MODE_CNTL": {
15180 {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
15181 {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"}
15184 "PA_SC_P3D_TRAP_SCREEN_H": {
15186 {"bits": [0, 13], "name": "X_COORD"}
15189 "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
15191 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
15192 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
15195 "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": {
15197 {"bits": [0, 15], "name": "COUNT"}
15200 "PA_SC_P3D_TRAP_SCREEN_V": {
15202 {"bits": [0, 13], "name": "Y_COORD"}
15205 "PA_SC_PERFCOUNTER1_SELECT": {
15207 {"bits": [0, 9], "name": "PERF_SEL"}
15210 "PA_SC_RASTER_CONFIG": {
15212 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
15213 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
15214 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
15215 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
15216 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
15217 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
15218 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
15219 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
15220 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
15221 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
15222 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
15223 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
15224 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
15225 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
15226 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
15229 "PA_SC_RASTER_CONFIG_1": {
15231 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
15232 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
15233 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
15236 "PA_SC_RIGHT_VERT_GRID": {
15238 {"bits": [0, 7], "name": "LEFT_QTR"},
15239 {"bits": [8, 15], "name": "LEFT_HALF"},
15240 {"bits": [16, 23], "name": "RIGHT_HALF"},
15241 {"bits": [24, 31], "name": "RIGHT_QTR"}
15244 "PA_SC_SCREEN_EXTENT_CONTROL": {
15246 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
15247 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
15250 "PA_SC_SCREEN_EXTENT_MIN_0": {
15252 {"bits": [0, 15], "name": "X"},
15253 {"bits": [16, 31], "name": "Y"}
15256 "PA_SC_SCREEN_SCISSOR_BR": {
15258 {"bits": [0, 15], "name": "BR_X"},
15259 {"bits": [16, 31], "name": "BR_Y"}
15262 "PA_SC_SCREEN_SCISSOR_TL": {
15264 {"bits": [0, 15], "name": "TL_X"},
15265 {"bits": [16, 31], "name": "TL_Y"}
15268 "PA_SC_SHADER_CONTROL": {
15270 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
15271 {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
15272 {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
15273 {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"}
15276 "PA_SC_TILE_STEERING_OVERRIDE": {
15278 {"bits": [0, 0], "name": "ENABLE"},
15279 {"bits": [1, 2], "name": "NUM_SE"},
15280 {"bits": [5, 6], "name": "NUM_RB_PER_SE"},
15281 {"bits": [8, 8], "name": "DISABLE_SRBSL_DB_OPTIMIZED_PACKING"},
15282 {"bits": [12, 13], "name": "NUM_SC"},
15283 {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
15284 {"bits": [20, 20], "name": "NUM_PACKER_PER_SC"}
15287 "PA_SC_VPORT_ZMAX_0": {
15289 {"bits": [0, 31], "name": "VPORT_ZMAX"}
15292 "PA_SC_VPORT_ZMIN_0": {
15294 {"bits": [0, 31], "name": "VPORT_ZMIN"}
15297 "PA_SC_WINDOW_OFFSET": {
15299 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
15300 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
15303 "PA_SC_WINDOW_SCISSOR_BR": {
15305 {"bits": [0, 14], "name": "BR_X"},
15306 {"bits": [16, 30], "name": "BR_Y"}
15309 "PA_SC_WINDOW_SCISSOR_TL": {
15311 {"bits": [0, 14], "name": "TL_X"},
15312 {"bits": [16, 30], "name": "TL_Y"},
15313 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
15316 "PA_STATE_STEREO_X": {
15318 {"bits": [0, 31], "name": "STEREO_X_OFFSET"}
15321 "PA_STEREO_CNTL": {
15323 {"bits": [1, 4], "name": "STEREO_MODE"},
15324 {"bits": [5, 7], "name": "RT_SLICE_MODE"},
15325 {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
15326 {"bits": [16, 18], "name": "VP_ID_MODE"},
15327 {"bits": [19, 22], "name": "VP_ID_OFFSET"}
15330 "PA_SU_HARDWARE_SCREEN_OFFSET": {
15332 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
15333 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
15336 "PA_SU_LINE_CNTL": {
15338 {"bits": [0, 15], "name": "WIDTH"}
15341 "PA_SU_LINE_STIPPLE_CNTL": {
15343 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
15344 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
15345 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
15346 {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
15349 "PA_SU_LINE_STIPPLE_SCALE": {
15351 {"bits": [0, 31], "name": "LINE_STIPPLE_SCALE"}
15354 "PA_SU_LINE_STIPPLE_VALUE": {
15356 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
15359 "PA_SU_OVER_RASTERIZATION_CNTL": {
15361 {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
15362 {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
15363 {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
15364 {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
15365 {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
15368 "PA_SU_PERFCOUNTER0_HI": {
15370 {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
15373 "PA_SU_PERFCOUNTER0_SELECT": {
15375 {"bits": [0, 9], "name": "PERF_SEL"},
15376 {"bits": [10, 19], "name": "PERF_SEL1"},
15377 {"bits": [20, 23], "name": "CNTR_MODE"},
15378 {"bits": [24, 27], "name": "PERF_MODE1"},
15379 {"bits": [28, 31], "name": "PERF_MODE"}
15382 "PA_SU_PERFCOUNTER0_SELECT1": {
15384 {"bits": [0, 9], "name": "PERF_SEL2"},
15385 {"bits": [10, 19], "name": "PERF_SEL3"},
15386 {"bits": [24, 27], "name": "PERF_MODE3"},
15387 {"bits": [28, 31], "name": "PERF_MODE2"}
15390 "PA_SU_POINT_MINMAX": {
15392 {"bits": [0, 15], "name": "MIN_SIZE"},
15393 {"bits": [16, 31], "name": "MAX_SIZE"}
15396 "PA_SU_POINT_SIZE": {
15398 {"bits": [0, 15], "name": "HEIGHT"},
15399 {"bits": [16, 31], "name": "WIDTH"}
15402 "PA_SU_POLY_OFFSET_CLAMP": {
15404 {"bits": [0, 31], "name": "CLAMP"}
15407 "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
15409 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
15410 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
15413 "PA_SU_POLY_OFFSET_FRONT_SCALE": {
15415 {"bits": [0, 31], "name": "SCALE"}
15418 "PA_SU_PRIM_FILTER_CNTL": {
15420 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
15421 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
15422 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
15423 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
15424 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
15425 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
15426 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
15427 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
15428 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
15429 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
15430 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
15433 "PA_SU_SC_MODE_CNTL": {
15435 {"bits": [0, 0], "name": "CULL_FRONT"},
15436 {"bits": [1, 1], "name": "CULL_BACK"},
15437 {"bits": [2, 2], "name": "FACE"},
15438 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
15439 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
15440 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
15441 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
15442 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
15443 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
15444 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
15445 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
15446 {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
15447 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
15448 {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
15449 {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
15450 {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
15453 "PA_SU_SMALL_PRIM_FILTER_CNTL": {
15455 {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
15456 {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
15457 {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
15458 {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
15459 {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"},
15460 {"bits": [5, 5], "name": "SRBSL_ENABLE"},
15461 {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"}
15464 "PA_SU_VTX_CNTL": {
15466 {"bits": [0, 0], "name": "PIX_CENTER"},
15467 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
15468 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
15471 "RLC_GPM_PERF_COUNT_0": {
15473 {"bits": [0, 3], "name": "FEATURE_SEL"},
15474 {"bits": [4, 7], "name": "SE_INDEX"},
15475 {"bits": [8, 11], "name": "SA_INDEX"},
15476 {"bits": [12, 15], "name": "WGP_INDEX"},
15477 {"bits": [16, 17], "name": "EVENT_SEL"},
15478 {"bits": [18, 19], "name": "UNUSED"},
15479 {"bits": [20, 20], "name": "ENABLE"},
15480 {"bits": [21, 31], "name": "RESERVED"}
15483 "RLC_GPU_IOV_PERF_CNT_CNTL": {
15485 {"bits": [0, 0], "name": "ENABLE"},
15486 {"bits": [1, 1], "name": "MODE_SELECT"},
15487 {"bits": [2, 2], "name": "RESET"},
15488 {"bits": [3, 31], "name": "RESERVED"}
15491 "RLC_GPU_IOV_PERF_CNT_WR_ADDR": {
15493 {"bits": [0, 3], "name": "VFID"},
15494 {"bits": [4, 5], "name": "CNT_ID"},
15495 {"bits": [6, 31], "name": "RESERVED"}
15498 "RLC_PERFCOUNTER0_SELECT": {
15500 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
15503 "RLC_PERFMON_CLK_CNTL": {
15505 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
15508 "RLC_PERFMON_CNTL": {
15510 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
15511 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
15514 "RLC_SPM_ACCUM_CTRL": {
15516 {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
15517 {"bits": [1, 1], "name": "StrobeStartAccumulation"},
15518 {"bits": [2, 2], "name": "StrobeRearmAccum"},
15519 {"bits": [3, 3], "name": "StrobeSpmDoneInt"},
15520 {"bits": [4, 4], "name": "StrobeAccumDoneInt"},
15521 {"bits": [5, 5], "name": "StrobeResetAccum"},
15522 {"bits": [6, 9], "name": "StrobeStartSpm"},
15523 {"bits": [10, 31], "name": "RESERVED"}
15526 "RLC_SPM_ACCUM_CTRLRAM_ADDR": {
15528 {"bits": [0, 8], "name": "addr"},
15529 {"bits": [9, 31], "name": "RESERVED"}
15532 "RLC_SPM_ACCUM_CTRLRAM_DATA": {
15534 {"bits": [0, 7], "name": "data"},
15535 {"bits": [8, 31], "name": "RESERVED"}
15538 "RLC_SPM_ACCUM_DATARAM_ADDR": {
15540 {"bits": [0, 6], "name": "addr"},
15541 {"bits": [7, 31], "name": "RESERVED"}
15544 "RLC_SPM_ACCUM_DATARAM_DATA": {
15546 {"bits": [0, 31], "name": "data"}
15549 "RLC_SPM_ACCUM_DATARAM_WRCOUNT": {
15551 {"bits": [0, 18], "name": "DataRamWrCount"},
15552 {"bits": [19, 31], "name": "RESERVED"}
15555 "RLC_SPM_ACCUM_MODE": {
15557 {"bits": [0, 0], "name": "EnableAccum"},
15558 {"bits": [1, 1], "name": "AutoAccumEn"},
15559 {"bits": [2, 2], "name": "AutoSpmEn"},
15560 {"bits": [3, 3], "name": "Globals_LoadOverride"},
15561 {"bits": [4, 4], "name": "SE0_LoadOverride"},
15562 {"bits": [5, 5], "name": "SE1_LoadOverride"},
15563 {"bits": [6, 6], "name": "AutoResetPerfmonDisable"},
15564 {"bits": [7, 31], "name": "RESERVED"}
15567 "RLC_SPM_ACCUM_SAMPLES_REQUESTED": {
15569 {"bits": [0, 7], "name": "SamplesRequested"},
15570 {"bits": [8, 31], "name": "RESERVED"}
15573 "RLC_SPM_ACCUM_STATUS": {
15575 {"bits": [0, 7], "name": "NumbSamplesCompleted"},
15576 {"bits": [8, 8], "name": "AccumDone"},
15577 {"bits": [9, 9], "name": "SpmDone"},
15578 {"bits": [10, 10], "name": "AccumOverflow"},
15579 {"bits": [11, 11], "name": "AccumArmed"},
15580 {"bits": [12, 12], "name": "SequenceInProgress"},
15581 {"bits": [13, 13], "name": "FinalSequenceInProgress"},
15582 {"bits": [14, 14], "name": "AllFifosEmpty"},
15583 {"bits": [15, 15], "name": "FSMIsIdle"},
15584 {"bits": [16, 31], "name": "RESERVED"}
15587 "RLC_SPM_ACCUM_THRESHOLD": {
15589 {"bits": [0, 15], "name": "Threshold"},
15590 {"bits": [16, 31], "name": "RESERVED"}
15593 "RLC_SPM_DESER_START_SKEW": {
15595 {"bits": [0, 6], "name": "DESER_START_SKEW"},
15596 {"bits": [7, 31], "name": "RESERVED"}
15599 "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR": {
15601 {"bits": [0, 31], "name": "GLB_SAMPLEDELAY_INDEX"}
15604 "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA": {
15606 {"bits": [0, 6], "name": "data"},
15607 {"bits": [7, 31], "name": "RESERVED"}
15610 "RLC_SPM_GLOBALS_MUXSEL_SKEW": {
15612 {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"},
15613 {"bits": [7, 31], "name": "RESERVED"}
15616 "RLC_SPM_GLOBALS_SAMPLE_SKEW": {
15618 {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"},
15619 {"bits": [7, 31], "name": "RESERVED"}
15622 "RLC_SPM_GLOBAL_MUXSEL_ADDR": {
15624 {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"},
15625 {"bits": [8, 31], "name": "RESERVED"}
15628 "RLC_SPM_PERFMON_CNTL": {
15630 {"bits": [0, 11], "name": "RESERVED1"},
15631 {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
15632 {"bits": [14, 15], "name": "RESERVED"},
15633 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
15636 "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE": {
15638 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
15639 {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"},
15640 {"bits": [16, 31], "name": "RESERVED"}
15643 "RLC_SPM_PERFMON_RING_BASE_HI": {
15645 {"bits": [0, 15], "name": "RING_BASE_HI"},
15646 {"bits": [16, 31], "name": "RESERVED"}
15649 "RLC_SPM_PERFMON_RING_BASE_LO": {
15651 {"bits": [0, 31], "name": "RING_BASE_LO"}
15654 "RLC_SPM_PERFMON_RING_SIZE": {
15656 {"bits": [0, 31], "name": "RING_BASE_SIZE"}
15659 "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE": {
15661 {"bits": [0, 7], "name": "SE0_NUM_LINE"},
15662 {"bits": [8, 15], "name": "SE1_NUM_LINE"},
15663 {"bits": [16, 23], "name": "SE2_NUM_LINE"},
15664 {"bits": [24, 31], "name": "SE3_NUM_LINE"}
15667 "RLC_SPM_PERFMON_SEGMENT_SIZE": {
15669 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
15670 {"bits": [8, 10], "name": "RESERVED1"},
15671 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
15672 {"bits": [16, 20], "name": "SE0_NUM_LINE"},
15673 {"bits": [21, 25], "name": "SE1_NUM_LINE"},
15674 {"bits": [26, 30], "name": "SE2_NUM_LINE"},
15675 {"bits": [31, 31], "name": "RESERVED"}
15678 "RLC_SPM_RING_RDPTR": {
15680 {"bits": [0, 31], "name": "PERFMON_RING_RDPTR"}
15683 "RLC_SPM_RING_WRPTR": {
15685 {"bits": [0, 4], "name": "RESERVED"},
15686 {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
15689 "RLC_SPM_SEGMENT_THRESHOLD": {
15691 {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
15692 {"bits": [8, 31], "name": "RESERVED"}
15695 "RLC_SPM_SE_MUXSEL_ADDR": {
15697 {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"},
15698 {"bits": [9, 31], "name": "RESERVED"}
15701 "RLC_SPM_SE_MUXSEL_DATA": {
15703 {"bits": [0, 31], "name": "PERFMON_SEL_DATA"}
15706 "RLC_SPM_SE_MUXSEL_SKEW": {
15708 {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"},
15709 {"bits": [7, 31], "name": "RESERVED"}
15712 "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR": {
15714 {"bits": [0, 31], "name": "SE_SAMPLEDELAY_INDEX"}
15717 "RLC_SPM_SE_SAMPLE_SKEW": {
15719 {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"},
15720 {"bits": [7, 31], "name": "RESERVED"}
15723 "RLC_SPM_VIRT_CTRL": {
15725 {"bits": [0, 0], "name": "PauseSpmSamplingRequest"}
15728 "RLC_SPM_VIRT_STATUS": {
15730 {"bits": [0, 0], "name": "SpmSamplingPaused"}
15733 "RMI_PERF_COUNTER_CNTL": {
15735 {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
15736 {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
15737 {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
15738 {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
15739 {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
15740 {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
15741 {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
15742 {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
15743 {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
15744 {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
15749 {"bits": [0, 31], "name": "OBSOLETE_ADDR"}
15754 {"bits": [0, 31], "name": "SCRATCH_REG0"}
15759 {"bits": [0, 31], "name": "SCRATCH_REG1"}
15764 {"bits": [0, 31], "name": "SCRATCH_REG2"}
15769 {"bits": [0, 31], "name": "SCRATCH_REG3"}
15774 {"bits": [0, 31], "name": "SCRATCH_REG4"}
15779 {"bits": [0, 31], "name": "SCRATCH_REG5"}
15784 {"bits": [0, 31], "name": "SCRATCH_REG6"}
15789 {"bits": [0, 31], "name": "SCRATCH_REG7"}
15794 {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
15795 {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
15798 "SPI_BARYC_CNTL": {
15800 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
15801 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
15802 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
15803 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
15804 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
15805 {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
15806 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
15809 "SPI_CONFIG_CNTL": {
15811 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
15812 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
15813 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
15814 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
15815 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
15816 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
15817 {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
15818 {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
15819 {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
15822 "SPI_CONFIG_CNTL_REMAP": {
15824 {"bits": [0, 31], "name": "RESERVED"}
15827 "SPI_INTERP_CONTROL_0": {
15829 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
15830 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
15831 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
15832 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
15833 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
15834 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
15835 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
15838 "SPI_PERFCOUNTER_BINS": {
15840 {"bits": [0, 3], "name": "BIN0_MIN"},
15841 {"bits": [4, 7], "name": "BIN0_MAX"},
15842 {"bits": [8, 11], "name": "BIN1_MIN"},
15843 {"bits": [12, 15], "name": "BIN1_MAX"},
15844 {"bits": [16, 19], "name": "BIN2_MIN"},
15845 {"bits": [20, 23], "name": "BIN2_MAX"},
15846 {"bits": [24, 27], "name": "BIN3_MIN"},
15847 {"bits": [28, 31], "name": "BIN3_MAX"}
15850 "SPI_PS_INPUT_CNTL_0": {
15852 {"bits": [0, 5], "name": "OFFSET"},
15853 {"bits": [8, 9], "name": "DEFAULT_VAL"},
15854 {"bits": [10, 10], "name": "FLAT_SHADE"},
15855 {"bits": [13, 16], "name": "CYL_WRAP"},
15856 {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
15857 {"bits": [18, 18], "name": "DUP"},
15858 {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
15859 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
15860 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
15861 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
15862 {"bits": [24, 24], "name": "ATTR0_VALID"},
15863 {"bits": [25, 25], "name": "ATTR1_VALID"}
15866 "SPI_PS_INPUT_CNTL_20": {
15868 {"bits": [0, 5], "name": "OFFSET"},
15869 {"bits": [8, 9], "name": "DEFAULT_VAL"},
15870 {"bits": [10, 10], "name": "FLAT_SHADE"},
15871 {"bits": [18, 18], "name": "DUP"},
15872 {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
15873 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
15874 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
15875 {"bits": [24, 24], "name": "ATTR0_VALID"},
15876 {"bits": [25, 25], "name": "ATTR1_VALID"}
15879 "SPI_PS_INPUT_ENA": {
15881 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
15882 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
15883 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
15884 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
15885 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
15886 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
15887 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
15888 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
15889 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
15890 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
15891 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
15892 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
15893 {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
15894 {"bits": [13, 13], "name": "ANCILLARY_ENA"},
15895 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
15896 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
15899 "SPI_PS_IN_CONTROL": {
15901 {"bits": [0, 5], "name": "NUM_INTERP"},
15902 {"bits": [6, 6], "name": "PARAM_GEN"},
15903 {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
15904 {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
15905 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
15906 {"bits": [15, 15], "name": "PS_W32_EN"}
15909 "SPI_SHADER_COL_FORMAT": {
15911 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
15912 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
15913 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
15914 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
15915 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
15916 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
15917 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
15918 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
15921 "SPI_SHADER_IDX_FORMAT": {
15923 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
15926 "SPI_SHADER_LATE_ALLOC_VS": {
15928 {"bits": [0, 5], "name": "LIMIT"}
15931 "SPI_SHADER_PGM_CHKSUM_PS": {
15933 {"bits": [0, 31], "name": "CHECKSUM"}
15936 "SPI_SHADER_PGM_HI_PS": {
15938 {"bits": [0, 7], "name": "MEM_BASE"}
15941 "SPI_SHADER_PGM_LO_PS": {
15943 {"bits": [0, 31], "name": "MEM_BASE"}
15946 "SPI_SHADER_PGM_RSRC1_ES": {
15948 {"bits": [0, 5], "name": "VGPRS"},
15949 {"bits": [6, 9], "name": "SGPRS"},
15950 {"bits": [10, 11], "name": "PRIORITY"},
15951 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15952 {"bits": [20, 20], "name": "PRIV"},
15953 {"bits": [21, 21], "name": "DX10_CLAMP"},
15954 {"bits": [23, 23], "name": "IEEE_MODE"},
15955 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
15956 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
15957 {"bits": [31, 31], "name": "FP16_OVFL"}
15960 "SPI_SHADER_PGM_RSRC1_GS": {
15962 {"bits": [0, 5], "name": "VGPRS"},
15963 {"bits": [6, 9], "name": "SGPRS"},
15964 {"bits": [10, 11], "name": "PRIORITY"},
15965 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15966 {"bits": [20, 20], "name": "PRIV"},
15967 {"bits": [21, 21], "name": "DX10_CLAMP"},
15968 {"bits": [23, 23], "name": "IEEE_MODE"},
15969 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
15970 {"bits": [25, 25], "name": "MEM_ORDERED"},
15971 {"bits": [26, 26], "name": "FWD_PROGRESS"},
15972 {"bits": [27, 27], "name": "WGP_MODE"},
15973 {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
15974 {"bits": [31, 31], "name": "FP16_OVFL"}
15977 "SPI_SHADER_PGM_RSRC1_HS": {
15979 {"bits": [0, 5], "name": "VGPRS"},
15980 {"bits": [6, 9], "name": "SGPRS"},
15981 {"bits": [10, 11], "name": "PRIORITY"},
15982 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15983 {"bits": [20, 20], "name": "PRIV"},
15984 {"bits": [21, 21], "name": "DX10_CLAMP"},
15985 {"bits": [23, 23], "name": "IEEE_MODE"},
15986 {"bits": [24, 24], "name": "MEM_ORDERED"},
15987 {"bits": [25, 25], "name": "FWD_PROGRESS"},
15988 {"bits": [26, 26], "name": "WGP_MODE"},
15989 {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
15990 {"bits": [30, 30], "name": "FP16_OVFL"}
15993 "SPI_SHADER_PGM_RSRC1_LS": {
15995 {"bits": [0, 5], "name": "VGPRS"},
15996 {"bits": [6, 9], "name": "SGPRS"},
15997 {"bits": [10, 11], "name": "PRIORITY"},
15998 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15999 {"bits": [20, 20], "name": "PRIV"},
16000 {"bits": [21, 21], "name": "DX10_CLAMP"},
16001 {"bits": [23, 23], "name": "IEEE_MODE"},
16002 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
16003 {"bits": [30, 30], "name": "FP16_OVFL"}
16006 "SPI_SHADER_PGM_RSRC1_PS": {
16008 {"bits": [0, 5], "name": "VGPRS"},
16009 {"bits": [6, 9], "name": "SGPRS"},
16010 {"bits": [10, 11], "name": "PRIORITY"},
16011 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
16012 {"bits": [20, 20], "name": "PRIV"},
16013 {"bits": [21, 21], "name": "DX10_CLAMP"},
16014 {"bits": [23, 23], "name": "IEEE_MODE"},
16015 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
16016 {"bits": [25, 25], "name": "MEM_ORDERED"},
16017 {"bits": [26, 26], "name": "FWD_PROGRESS"},
16018 {"bits": [29, 29], "name": "FP16_OVFL"}
16021 "SPI_SHADER_PGM_RSRC1_VS": {
16023 {"bits": [0, 5], "name": "VGPRS"},
16024 {"bits": [6, 9], "name": "SGPRS"},
16025 {"bits": [10, 11], "name": "PRIORITY"},
16026 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
16027 {"bits": [20, 20], "name": "PRIV"},
16028 {"bits": [21, 21], "name": "DX10_CLAMP"},
16029 {"bits": [23, 23], "name": "IEEE_MODE"},
16030 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
16031 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
16032 {"bits": [27, 27], "name": "MEM_ORDERED"},
16033 {"bits": [28, 28], "name": "FWD_PROGRESS"},
16034 {"bits": [31, 31], "name": "FP16_OVFL"}
16037 "SPI_SHADER_PGM_RSRC2_ES_VS": {
16039 {"bits": [0, 0], "name": "SCRATCH_EN"},
16040 {"bits": [1, 5], "name": "USER_SGPR"},
16041 {"bits": [6, 6], "name": "TRAP_PRESENT"},
16042 {"bits": [7, 7], "name": "OC_LDS_EN"},
16043 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16044 {"bits": [20, 28], "name": "LDS_SIZE"}
16047 "SPI_SHADER_PGM_RSRC2_GS": {
16049 {"bits": [0, 0], "name": "SCRATCH_EN"},
16050 {"bits": [1, 5], "name": "USER_SGPR"},
16051 {"bits": [6, 6], "name": "TRAP_PRESENT"},
16052 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16053 {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
16054 {"bits": [18, 18], "name": "OC_LDS_EN"},
16055 {"bits": [19, 26], "name": "LDS_SIZE"},
16056 {"bits": [27, 27], "name": "USER_SGPR_MSB"},
16057 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
16060 "SPI_SHADER_PGM_RSRC2_GS_VS": {
16062 {"bits": [0, 0], "name": "SCRATCH_EN"},
16063 {"bits": [1, 5], "name": "USER_SGPR"},
16064 {"bits": [6, 6], "name": "TRAP_PRESENT"},
16065 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16066 {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
16067 {"bits": [18, 18], "name": "OC_LDS_EN"},
16068 {"bits": [19, 26], "name": "LDS_SIZE"},
16069 {"bits": [27, 27], "name": "SKIP_USGPR0"},
16070 {"bits": [28, 28], "name": "USER_SGPR_MSB"}
16073 "SPI_SHADER_PGM_RSRC2_HS": {
16075 {"bits": [0, 0], "name": "SCRATCH_EN"},
16076 {"bits": [1, 5], "name": "USER_SGPR"},
16077 {"bits": [6, 6], "name": "TRAP_PRESENT"},
16078 {"bits": [7, 7], "name": "OC_LDS_EN"},
16079 {"bits": [8, 8], "name": "TG_SIZE_EN"},
16080 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16081 {"bits": [18, 26], "name": "LDS_SIZE"},
16082 {"bits": [27, 27], "name": "USER_SGPR_MSB"},
16083 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
16086 "SPI_SHADER_PGM_RSRC2_LS_VS": {
16088 {"bits": [0, 0], "name": "SCRATCH_EN"},
16089 {"bits": [1, 5], "name": "USER_SGPR"},
16090 {"bits": [6, 6], "name": "TRAP_PRESENT"},
16091 {"bits": [7, 15], "name": "LDS_SIZE"},
16092 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
16095 "SPI_SHADER_PGM_RSRC2_PS": {
16097 {"bits": [0, 0], "name": "SCRATCH_EN"},
16098 {"bits": [1, 5], "name": "USER_SGPR"},
16099 {"bits": [6, 6], "name": "TRAP_PRESENT"},
16100 {"bits": [7, 7], "name": "WAVE_CNT_EN"},
16101 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
16102 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16103 {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
16104 {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
16105 {"bits": [27, 27], "name": "USER_SGPR_MSB"},
16106 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
16109 "SPI_SHADER_PGM_RSRC2_VS": {
16111 {"bits": [0, 0], "name": "SCRATCH_EN"},
16112 {"bits": [1, 5], "name": "USER_SGPR"},
16113 {"bits": [6, 6], "name": "TRAP_PRESENT"},
16114 {"bits": [7, 7], "name": "OC_LDS_EN"},
16115 {"bits": [8, 8], "name": "SO_BASE0_EN"},
16116 {"bits": [9, 9], "name": "SO_BASE1_EN"},
16117 {"bits": [10, 10], "name": "SO_BASE2_EN"},
16118 {"bits": [11, 11], "name": "SO_BASE3_EN"},
16119 {"bits": [12, 12], "name": "SO_EN"},
16120 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16121 {"bits": [22, 22], "name": "PC_BASE_EN"},
16122 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
16123 {"bits": [27, 27], "name": "USER_SGPR_MSB"},
16124 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
16127 "SPI_SHADER_PGM_RSRC3_GS": {
16129 {"bits": [0, 15], "name": "CU_EN"},
16130 {"bits": [16, 21], "name": "WAVE_LIMIT"},
16131 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
16132 {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
16135 "SPI_SHADER_PGM_RSRC3_HS": {
16137 {"bits": [0, 5], "name": "WAVE_LIMIT"},
16138 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
16139 {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
16140 {"bits": [16, 31], "name": "CU_EN"}
16143 "SPI_SHADER_PGM_RSRC3_PS": {
16145 {"bits": [0, 15], "name": "CU_EN"},
16146 {"bits": [16, 21], "name": "WAVE_LIMIT"},
16147 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
16150 "SPI_SHADER_PGM_RSRC4_GS": {
16152 {"bits": [0, 15], "name": "CU_EN"},
16153 {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"}
16156 "SPI_SHADER_PGM_RSRC4_PS": {
16158 {"bits": [0, 15], "name": "CU_EN"}
16161 "SPI_SHADER_POS_FORMAT": {
16163 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
16164 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
16165 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
16166 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
16167 {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
16170 "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS": {
16172 {"bits": [0, 2], "name": "TOTAL_WAVE_COUNT_HIER_SELECT"},
16173 {"bits": [3, 5], "name": "PER_TYPE_WAVE_COUNT_HIER_SELECT"},
16174 {"bits": [6, 6], "name": "GROUP_UPDATE_EN"},
16175 {"bits": [8, 15], "name": "TOTAL_WAVE_COUNT_COEFFICIENT"},
16176 {"bits": [16, 23], "name": "PER_TYPE_WAVE_COUNT_COEFFICIENT"}
16179 "SPI_SHADER_REQ_CTRL_PS": {
16181 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
16182 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
16183 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
16184 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
16185 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
16186 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
16187 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
16188 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
16191 "SPI_SHADER_USER_ACCUM_PS_0": {
16193 {"bits": [0, 6], "name": "CONTRIBUTION"}
16196 "SPI_SHADER_USER_DATA_PS_0": {
16198 {"bits": [0, 31], "name": "DATA"}
16201 "SPI_SHADER_Z_FORMAT": {
16203 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
16206 "SPI_VS_OUT_CONFIG": {
16208 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
16209 {"bits": [6, 6], "name": "VS_HALF_PACK"},
16210 {"bits": [7, 7], "name": "NO_PC_EXPORT"}
16215 {"bits": [0, 0], "name": "TARGET_INST"},
16216 {"bits": [1, 1], "name": "TARGET_DATA"},
16217 {"bits": [2, 2], "name": "INVALIDATE"},
16218 {"bits": [3, 3], "name": "WRITEBACK"},
16219 {"bits": [4, 4], "name": "VOL"},
16220 {"bits": [16, 16], "name": "COMPLETE"},
16221 {"bits": [17, 18], "name": "L2_WB_POLICY"}
16226 {"bits": [0, 0], "name": "DWB"},
16227 {"bits": [1, 1], "name": "DIRTY"}
16230 "SQ_PERFCOUNTER0_SELECT": {
16232 {"bits": [0, 8], "name": "PERF_SEL"},
16233 {"bits": [12, 15], "name": "SQC_BANK_MASK"},
16234 {"bits": [20, 23], "name": "SPM_MODE"},
16235 {"bits": [28, 31], "name": "PERF_MODE"}
16238 "SQ_PERFCOUNTER_CTRL": {
16240 {"bits": [0, 0], "name": "PS_EN"},
16241 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
16242 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
16243 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
16244 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
16245 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
16246 {"bits": [6, 6], "name": "CS_EN"},
16247 {"bits": [8, 9], "name": "CNTR_RATE"},
16248 {"bits": [13, 13], "name": "DISABLE_FLUSH"}
16251 "SQ_PERFCOUNTER_CTRL2": {
16253 {"bits": [0, 0], "name": "FORCE_EN"}
16256 "SQ_THREAD_TRACE_BUF0_BASE": {
16258 {"bits": [0, 31], "name": "BASE_LO"}
16261 "SQ_THREAD_TRACE_BUF0_SIZE": {
16263 {"bits": [0, 3], "name": "BASE_HI"},
16264 {"bits": [8, 29], "name": "SIZE"}
16267 "SQ_THREAD_TRACE_CTRL": {
16269 {"bits": [0, 1], "name": "MODE"},
16270 {"bits": [2, 2], "name": "ALL_VMID"},
16271 {"bits": [3, 3], "name": "CH_PERF_EN"},
16272 {"bits": [4, 4], "name": "INTERRUPT_EN"},
16273 {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
16274 {"bits": [6, 8], "name": "HIWATER"},
16275 {"bits": [9, 9], "name": "REG_STALL_EN"},
16276 {"bits": [10, 10], "name": "SPI_STALL_EN"},
16277 {"bits": [11, 11], "name": "SQ_STALL_EN"},
16278 {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
16279 {"bits": [13, 13], "name": "UTIL_TIMER"},
16280 {"bits": [14, 15], "name": "WAVESTART_MODE"},
16281 {"bits": [16, 17], "name": "RT_FREQ"},
16282 {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
16283 {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
16284 {"bits": [30, 30], "name": "CAPTURE_ALL"},
16285 {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
16288 "SQ_THREAD_TRACE_DROPPED_CNTR": {
16290 {"bits": [0, 31], "name": "CNTR"}
16293 "SQ_THREAD_TRACE_MASK": {
16295 {"bits": [0, 1], "name": "SIMD_SEL"},
16296 {"bits": [4, 7], "name": "WGP_SEL"},
16297 {"bits": [9, 9], "name": "SA_SEL"},
16298 {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
16301 "SQ_THREAD_TRACE_STATUS": {
16303 {"bits": [0, 11], "name": "FINISH_PENDING"},
16304 {"bits": [12, 23], "name": "FINISH_DONE"},
16305 {"bits": [24, 24], "name": "UTC_ERR"},
16306 {"bits": [25, 25], "name": "BUSY"},
16307 {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
16308 {"bits": [27, 27], "name": "EVENT_CNTR_STALL"}
16311 "SQ_THREAD_TRACE_TOKEN_MASK": {
16313 {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
16314 {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
16315 {"bits": [24, 25], "name": "INST_EXCLUDE"},
16316 {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
16319 "SQ_THREAD_TRACE_WPTR": {
16321 {"bits": [0, 28], "name": "OFFSET"},
16322 {"bits": [31, 31], "name": "BUFFER_ID"}
16325 "SQ_WAVE_EXEC_HI": {
16327 {"bits": [0, 31], "name": "EXEC_HI"}
16330 "SQ_WAVE_EXEC_LO": {
16332 {"bits": [0, 31], "name": "EXEC_LO"}
16335 "SQ_WAVE_FLAT_XNACK_MASK": {
16337 {"bits": [0, 31], "name": "MASK"}
16340 "SQ_WAVE_FLUSH_IB": {
16342 {"bits": [0, 31], "name": "UNUSED"}
16345 "SQ_WAVE_GPR_ALLOC": {
16347 {"bits": [0, 7], "name": "VGPR_BASE"},
16348 {"bits": [8, 15], "name": "VGPR_SIZE"},
16349 {"bits": [16, 23], "name": "SGPR_BASE"},
16350 {"bits": [24, 27], "name": "SGPR_SIZE"}
16353 "SQ_WAVE_HW_ID1": {
16355 {"bits": [0, 4], "name": "WAVE_ID"},
16356 {"bits": [8, 9], "name": "SIMD_ID"},
16357 {"bits": [10, 13], "name": "WGP_ID"},
16358 {"bits": [16, 16], "name": "SA_ID"},
16359 {"bits": [18, 19], "name": "SE_ID"}
16362 "SQ_WAVE_HW_ID2": {
16364 {"bits": [0, 3], "name": "QUEUE_ID"},
16365 {"bits": [4, 5], "name": "PIPE_ID"},
16366 {"bits": [8, 9], "name": "ME_ID"},
16367 {"bits": [12, 14], "name": "STATE_ID"},
16368 {"bits": [16, 20], "name": "WG_ID"},
16369 {"bits": [24, 27], "name": "VM_ID"},
16370 {"bits": [29, 30], "name": "COMPAT_LEVEL"}
16373 "SQ_WAVE_HW_ID_LEGACY": {
16375 {"bits": [0, 3], "name": "WAVE_ID"},
16376 {"bits": [4, 5], "name": "SIMD_ID"},
16377 {"bits": [6, 7], "name": "PIPE_ID"},
16378 {"bits": [8, 11], "name": "CU_ID"},
16379 {"bits": [12, 12], "name": "SH_ID"},
16380 {"bits": [13, 14], "name": "SE_ID"},
16381 {"bits": [15, 15], "name": "WAVE_ID_MSB"},
16382 {"bits": [16, 19], "name": "TG_ID"},
16383 {"bits": [20, 23], "name": "VM_ID"},
16384 {"bits": [24, 26], "name": "QUEUE_ID"},
16385 {"bits": [27, 29], "name": "STATE_ID"},
16386 {"bits": [30, 31], "name": "ME_ID"}
16389 "SQ_WAVE_IB_DBG1": {
16391 {"bits": [0, 0], "name": "XNACK_ERROR"},
16392 {"bits": [1, 1], "name": "XNACK"},
16393 {"bits": [2, 2], "name": "TA_NEED_RESET"},
16394 {"bits": [3, 3], "name": "XNACK_OVERRIDE"},
16395 {"bits": [4, 9], "name": "XCNT"},
16396 {"bits": [11, 16], "name": "QCNT"},
16397 {"bits": [18, 23], "name": "RCNT"},
16398 {"bits": [24, 24], "name": "WAVE_IDLE"},
16399 {"bits": [25, 31], "name": "MISC_CNT"}
16402 "SQ_WAVE_IB_STS": {
16404 {"bits": [0, 3], "name": "VM_CNT"},
16405 {"bits": [4, 6], "name": "EXP_CNT"},
16406 {"bits": [7, 7], "name": "LGKM_CNT_BIT4"},
16407 {"bits": [8, 11], "name": "LGKM_CNT"},
16408 {"bits": [12, 14], "name": "VALU_CNT"},
16409 {"bits": [15, 15], "name": "FIRST_REPLAY"},
16410 {"bits": [16, 21], "name": "RCNT"},
16411 {"bits": [22, 23], "name": "VM_CNT_HI"},
16412 {"bits": [24, 24], "name": "LGKM_CNT_BIT5"},
16413 {"bits": [25, 25], "name": "REPLAY_W64H"},
16414 {"bits": [26, 31], "name": "VS_CNT"}
16417 "SQ_WAVE_IB_STS2": {
16419 {"bits": [0, 1], "name": "INST_PREFETCH"},
16420 {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"},
16421 {"bits": [8, 9], "name": "MEM_ORDER"},
16422 {"bits": [10, 10], "name": "FWD_PROGRESS"},
16423 {"bits": [11, 11], "name": "WAVE64"},
16424 {"bits": [12, 12], "name": "WAVE64HI"},
16425 {"bits": [13, 13], "name": "SUBV_LOOP"}
16428 "SQ_WAVE_INST_DW0": {
16430 {"bits": [0, 31], "name": "INST_DW0"}
16433 "SQ_WAVE_LDS_ALLOC": {
16435 {"bits": [0, 8], "name": "LDS_BASE"},
16436 {"bits": [12, 20], "name": "LDS_SIZE"},
16437 {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
16442 {"bits": [0, 31], "name": "M0"}
16447 {"bits": [0, 3], "name": "FP_ROUND"},
16448 {"bits": [4, 7], "name": "FP_DENORM"},
16449 {"bits": [8, 8], "name": "DX10_CLAMP"},
16450 {"bits": [9, 9], "name": "IEEE"},
16451 {"bits": [10, 10], "name": "LOD_CLAMPED"},
16452 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16453 {"bits": [23, 23], "name": "FP16_OVFL"},
16454 {"bits": [27, 27], "name": "DISABLE_PERF"},
16455 {"bits": [28, 28], "name": "VSKIP"},
16456 {"bits": [29, 31], "name": "CSP"}
16461 {"bits": [0, 15], "name": "PC_HI"}
16466 {"bits": [0, 31], "name": "PC_LO"}
16469 "SQ_WAVE_POPS_PACKER": {
16471 {"bits": [0, 0], "name": "POPS_EN"},
16472 {"bits": [1, 2], "name": "POPS_PACKER_ID"}
16475 "SQ_WAVE_SCHED_MODE": {
16477 {"bits": [0, 1], "name": "DEP_MODE"}
16480 "SQ_WAVE_STATUS": {
16482 {"bits": [0, 0], "name": "SCC"},
16483 {"bits": [1, 2], "name": "SPI_PRIO"},
16484 {"bits": [3, 4], "name": "USER_PRIO"},
16485 {"bits": [5, 5], "name": "PRIV"},
16486 {"bits": [6, 6], "name": "TRAP_EN"},
16487 {"bits": [7, 7], "name": "TTRACE_EN"},
16488 {"bits": [8, 8], "name": "EXPORT_RDY"},
16489 {"bits": [9, 9], "name": "EXECZ"},
16490 {"bits": [10, 10], "name": "VCCZ"},
16491 {"bits": [11, 11], "name": "IN_TG"},
16492 {"bits": [12, 12], "name": "IN_BARRIER"},
16493 {"bits": [13, 13], "name": "HALT"},
16494 {"bits": [14, 14], "name": "TRAP"},
16495 {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
16496 {"bits": [16, 16], "name": "VALID"},
16497 {"bits": [17, 17], "name": "ECC_ERR"},
16498 {"bits": [18, 18], "name": "SKIP_EXPORT"},
16499 {"bits": [19, 19], "name": "PERF_EN"},
16500 {"bits": [23, 23], "name": "FATAL_HALT"},
16501 {"bits": [27, 27], "name": "MUST_EXPORT"}
16504 "SQ_WAVE_TRAPSTS": {
16506 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
16507 {"bits": [10, 10], "name": "SAVECTX"},
16508 {"bits": [11, 11], "name": "ILLEGAL_INST"},
16509 {"bits": [12, 14], "name": "EXCP_HI"},
16510 {"bits": [15, 15], "name": "BUFFER_OOB"},
16511 {"bits": [16, 19], "name": "EXCP_CYCLE"},
16512 {"bits": [20, 23], "name": "EXCP_GROUP_MASK"},
16513 {"bits": [24, 24], "name": "EXCP_WAVE64HI"},
16514 {"bits": [28, 28], "name": "XNACK_ERROR"},
16515 {"bits": [29, 31], "name": "DP_RATE"}
16518 "SQ_WAVE_VGPR_OFFSET": {
16520 {"bits": [0, 5], "name": "SRC0"},
16521 {"bits": [6, 11], "name": "SRC1"},
16522 {"bits": [12, 17], "name": "SRC2"},
16523 {"bits": [18, 23], "name": "DST"}
16526 "SX_BLEND_OPT_CONTROL": {
16528 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
16529 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
16530 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
16531 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
16532 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
16533 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
16534 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
16535 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
16536 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
16537 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
16538 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
16539 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
16540 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
16541 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
16542 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
16543 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
16544 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
16547 "SX_BLEND_OPT_EPSILON": {
16549 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
16550 {"bits": [4, 7], "name": "MRT1_EPSILON"},
16551 {"bits": [8, 11], "name": "MRT2_EPSILON"},
16552 {"bits": [12, 15], "name": "MRT3_EPSILON"},
16553 {"bits": [16, 19], "name": "MRT4_EPSILON"},
16554 {"bits": [20, 23], "name": "MRT5_EPSILON"},
16555 {"bits": [24, 27], "name": "MRT6_EPSILON"},
16556 {"bits": [28, 31], "name": "MRT7_EPSILON"}
16559 "SX_MRT0_BLEND_OPT": {
16561 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
16562 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
16563 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
16564 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
16565 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
16566 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
16569 "SX_PERFCOUNTER0_SELECT": {
16571 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"},
16572 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"},
16573 {"bits": [20, 23], "name": "CNTR_MODE"}
16576 "SX_PERFCOUNTER0_SELECT1": {
16578 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"},
16579 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}
16582 "SX_PS_DOWNCONVERT": {
16584 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
16585 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
16586 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
16587 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
16588 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
16589 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
16590 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
16591 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
16594 "TA_BC_BASE_ADDR": {
16596 {"bits": [0, 31], "name": "ADDRESS"}
16599 "TA_BC_BASE_ADDR_HI": {
16601 {"bits": [0, 7], "name": "ADDRESS"}
16604 "TA_PERFCOUNTER0_SELECT": {
16606 {"bits": [0, 7], "name": "PERF_SEL"},
16607 {"bits": [10, 17], "name": "PERF_SEL1"},
16608 {"bits": [20, 23], "name": "CNTR_MODE"},
16609 {"bits": [24, 27], "name": "PERF_MODE1"},
16610 {"bits": [28, 31], "name": "PERF_MODE"}
16613 "TA_PERFCOUNTER0_SELECT1": {
16615 {"bits": [0, 7], "name": "PERF_SEL2"},
16616 {"bits": [10, 17], "name": "PERF_SEL3"},
16617 {"bits": [24, 27], "name": "PERF_MODE3"},
16618 {"bits": [28, 31], "name": "PERF_MODE2"}
16621 "TA_PERFCOUNTER1_SELECT": {
16623 {"bits": [0, 7], "name": "PERF_SEL"},
16624 {"bits": [20, 23], "name": "CNTR_MODE"},
16625 {"bits": [28, 31], "name": "PERF_MODE"}
16628 "TCP_PERFCOUNTER2_SELECT": {
16630 {"bits": [0, 9], "name": "PERF_SEL"},
16631 {"bits": [20, 23], "name": "CNTR_MODE"},
16632 {"bits": [28, 31], "name": "PERF_MODE"}
16635 "UTCL1_PERFCOUNTER0_SELECT": {
16637 {"bits": [0, 9], "name": "PERF_SEL"},
16638 {"bits": [28, 31], "name": "COUNTER_MODE"}
16641 "VGT_DISPATCH_DRAW_INDEX": {
16643 {"bits": [0, 31], "name": "MATCH_INDEX"}
16648 {"bits": [0, 31], "name": "BASE_ADDR"}
16651 "VGT_DMA_BASE_HI": {
16653 {"bits": [0, 15], "name": "BASE_ADDR"}
16656 "VGT_DMA_INDEX_TYPE": {
16658 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
16659 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
16660 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
16661 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
16662 {"bits": [8, 8], "name": "ATC"},
16663 {"bits": [9, 9], "name": "NOT_EOP"},
16664 {"bits": [10, 10], "name": "REQ_PATH"},
16665 {"bits": [11, 13], "name": "MTYPE"}
16668 "VGT_DMA_MAX_SIZE": {
16670 {"bits": [0, 31], "name": "MAX_SIZE"}
16673 "VGT_DMA_NUM_INSTANCES": {
16675 {"bits": [0, 31], "name": "NUM_INSTANCES"}
16680 {"bits": [0, 31], "name": "NUM_INDICES"}
16683 "VGT_DRAW_INITIATOR": {
16685 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
16686 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
16687 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
16688 {"bits": [5, 5], "name": "NOT_EOP"},
16689 {"bits": [6, 6], "name": "USE_OPAQUE"},
16690 {"bits": [7, 7], "name": "UNROLLED_INST"},
16691 {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"},
16692 {"bits": [29, 31], "name": "REG_RT_INDEX"}
16695 "VGT_DRAW_PAYLOAD_CNTL": {
16697 {"bits": [0, 0], "name": "OBJPRIM_ID_EN"},
16698 {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
16699 {"bits": [2, 2], "name": "OBJECT_ID_INST_EN"},
16700 {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
16701 {"bits": [4, 4], "name": "EN_DRAW_VP"}
16706 {"bits": [0, 31], "name": "MISC"}
16709 "VGT_ESGS_RING_ITEMSIZE": {
16711 {"bits": [0, 14], "name": "ITEMSIZE"}
16714 "VGT_ESGS_RING_SIZE_UMD": {
16716 {"bits": [0, 31], "name": "MEM_SIZE"}
16721 {"bits": [0, 10], "name": "ES_PER_GS"}
16724 "VGT_EVENT_ADDRESS_REG": {
16726 {"bits": [0, 27], "name": "ADDRESS_LOW"}
16729 "VGT_EVENT_INITIATOR": {
16731 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
16732 {"bits": [10, 26], "name": "ADDRESS_HI"},
16733 {"bits": [27, 27], "name": "EXTENDED_EVENT"}
16736 "VGT_GROUP_DECR": {
16738 {"bits": [0, 3], "name": "DECR"}
16741 "VGT_GROUP_FIRST_DECR": {
16743 {"bits": [0, 3], "name": "FIRST_DECR"}
16746 "VGT_GROUP_PRIM_TYPE": {
16748 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
16749 {"bits": [14, 14], "name": "RETAIN_ORDER"},
16750 {"bits": [15, 15], "name": "RETAIN_QUADS"},
16751 {"bits": [16, 18], "name": "PRIM_ORDER"}
16754 "VGT_GROUP_VECT_0_CNTL": {
16756 {"bits": [0, 0], "name": "COMP_X_EN"},
16757 {"bits": [1, 1], "name": "COMP_Y_EN"},
16758 {"bits": [2, 2], "name": "COMP_Z_EN"},
16759 {"bits": [3, 3], "name": "COMP_W_EN"},
16760 {"bits": [8, 15], "name": "STRIDE"},
16761 {"bits": [16, 23], "name": "SHIFT"}
16764 "VGT_GROUP_VECT_0_FMT_CNTL": {
16766 {"bits": [0, 3], "name": "X_CONV"},
16767 {"bits": [4, 7], "name": "X_OFFSET"},
16768 {"bits": [8, 11], "name": "Y_CONV"},
16769 {"bits": [12, 15], "name": "Y_OFFSET"},
16770 {"bits": [16, 19], "name": "Z_CONV"},
16771 {"bits": [20, 23], "name": "Z_OFFSET"},
16772 {"bits": [24, 27], "name": "W_CONV"},
16773 {"bits": [28, 31], "name": "W_OFFSET"}
16776 "VGT_GSVS_RING_OFFSET_1": {
16778 {"bits": [0, 14], "name": "OFFSET"}
16781 "VGT_GS_INSTANCE_CNT": {
16783 {"bits": [0, 0], "name": "ENABLE"},
16784 {"bits": [2, 8], "name": "CNT"},
16785 {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
16788 "VGT_GS_MAX_VERT_OUT": {
16790 {"bits": [0, 10], "name": "MAX_VERT_OUT"}
16795 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
16796 {"bits": [3, 3], "name": "RESERVED_0"},
16797 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
16798 {"bits": [6, 10], "name": "RESERVED_1"},
16799 {"bits": [11, 11], "name": "GS_C_PACK_EN"},
16800 {"bits": [12, 12], "name": "RESERVED_2"},
16801 {"bits": [13, 13], "name": "ES_PASSTHRU"},
16802 {"bits": [14, 14], "name": "COMPUTE_MODE"},
16803 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
16804 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
16805 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
16806 {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
16807 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
16808 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
16809 {"bits": [21, 22], "name": "ONCHIP"}
16812 "VGT_GS_ONCHIP_CNTL": {
16814 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
16815 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
16816 {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
16819 "VGT_GS_OUT_PRIM_TYPE": {
16821 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
16822 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
16823 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
16824 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
16825 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
16830 {"bits": [0, 10], "name": "GS_PER_ES"}
16835 {"bits": [0, 3], "name": "GS_PER_VS"}
16840 {"bits": [0, 1], "name": "TESS_MODE"}
16843 "VGT_HOS_MAX_TESS_LEVEL": {
16845 {"bits": [0, 31], "name": "MAX_TESS"}
16848 "VGT_HOS_MIN_TESS_LEVEL": {
16850 {"bits": [0, 31], "name": "MIN_TESS"}
16853 "VGT_HOS_REUSE_DEPTH": {
16855 {"bits": [0, 7], "name": "REUSE_DEPTH"}
16858 "VGT_HS_OFFCHIP_PARAM_UMD": {
16860 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
16861 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
16864 "VGT_INDX_OFFSET": {
16866 {"bits": [0, 31], "name": "INDX_OFFSET"}
16869 "VGT_INSTANCE_BASE_ID": {
16871 {"bits": [0, 31], "name": "INSTANCE_BASE_ID"}
16874 "VGT_INSTANCE_STEP_RATE_0": {
16876 {"bits": [0, 31], "name": "STEP_RATE"}
16879 "VGT_LS_HS_CONFIG": {
16881 {"bits": [0, 7], "name": "NUM_PATCHES"},
16882 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
16883 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
16886 "VGT_MAX_VTX_INDX": {
16888 {"bits": [0, 31], "name": "MAX_INDX"}
16891 "VGT_MIN_VTX_INDX": {
16893 {"bits": [0, 31], "name": "MIN_INDX"}
16896 "VGT_MULTI_PRIM_IB_RESET_EN": {
16898 {"bits": [0, 0], "name": "RESET_EN"},
16899 {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
16902 "VGT_MULTI_PRIM_IB_RESET_INDX": {
16904 {"bits": [0, 31], "name": "RESET_INDX"}
16907 "VGT_OUTPUT_PATH_CNTL": {
16909 {"bits": [0, 2], "name": "PATH_SELECT"}
16912 "VGT_OUT_DEALLOC_CNTL": {
16914 {"bits": [0, 6], "name": "DEALLOC_DIST"}
16917 "VGT_PRIMITIVEID_EN": {
16919 {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
16920 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
16921 {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
16924 "VGT_PRIMITIVEID_RESET": {
16926 {"bits": [0, 31], "name": "VALUE"}
16929 "VGT_PRIMITIVE_TYPE": {
16931 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
16936 {"bits": [0, 0], "name": "REUSE_OFF"}
16939 "VGT_SHADER_STAGES_EN": {
16941 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
16942 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
16943 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
16944 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
16945 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
16946 {"bits": [8, 8], "name": "DYNAMIC_HS"},
16947 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
16948 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
16949 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
16950 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
16951 {"bits": [13, 13], "name": "PRIMGEN_EN"},
16952 {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
16953 {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
16954 {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
16955 {"bits": [21, 21], "name": "HS_W32_EN"},
16956 {"bits": [22, 22], "name": "GS_W32_EN"},
16957 {"bits": [23, 23], "name": "VS_W32_EN"},
16958 {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
16959 {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"}
16962 "VGT_STRMOUT_BUFFER_CONFIG": {
16964 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
16965 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
16966 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
16967 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
16970 "VGT_STRMOUT_BUFFER_OFFSET_0": {
16972 {"bits": [0, 31], "name": "OFFSET"}
16975 "VGT_STRMOUT_CONFIG": {
16977 {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
16978 {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
16979 {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
16980 {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
16981 {"bits": [4, 6], "name": "RAST_STREAM"},
16982 {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
16983 {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
16984 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
16987 "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
16989 {"bits": [0, 8], "name": "VERTEX_STRIDE"}
16992 "VGT_STRMOUT_VTX_STRIDE_0": {
16994 {"bits": [0, 9], "name": "STRIDE"}
16997 "VGT_TESS_DISTRIBUTION": {
16999 {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
17000 {"bits": [8, 15], "name": "ACCUM_TRI"},
17001 {"bits": [16, 23], "name": "ACCUM_QUAD"},
17002 {"bits": [24, 28], "name": "DONUT_SPLIT"},
17003 {"bits": [29, 31], "name": "TRAP_SPLIT"}
17006 "VGT_TF_MEMORY_BASE_UMD": {
17008 {"bits": [0, 31], "name": "BASE"}
17013 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
17014 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
17015 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
17016 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
17017 {"bits": [9, 9], "name": "DEPRECATED"},
17018 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
17019 {"bits": [14, 14], "name": "DISABLE_DONUTS"},
17020 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
17021 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
17022 {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
17023 {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
17024 {"bits": [23, 25], "name": "MTYPE"}
17027 "VGT_TF_RING_SIZE_UMD": {
17029 {"bits": [0, 15], "name": "SIZE"}
17032 "VGT_VERTEX_REUSE_BLOCK_CNTL": {
17034 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
17037 "VGT_VTX_CNT_EN": {
17039 {"bits": [0, 0], "name": "VTX_CNT_EN"}