projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: predicate cmask eliminate when using DCC.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_fail = false;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_fail = true;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_fail = true;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_fail = true;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344
345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
346
347 ++cmd_buffer->state.trace_id;
348 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME));
353 radeon_emit(cs, va);
354 radeon_emit(cs, va >> 32);
355 radeon_emit(cs, cmd_buffer->state.trace_id);
356 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
357 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
358 }
359
360 static void
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
365 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
366 8);
367 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
369
370 if (cmd_buffer->device->physical_device->has_rbplus) {
371 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
372 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
373 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
374 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
375 }
376 }
377
378 static void
379 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
380 struct radv_pipeline *pipeline)
381 {
382 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
383 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
384 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
385
386 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
387 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
388 }
389
390 /* 12.4 fixed-point */
391 static unsigned radv_pack_float_12p4(float x)
392 {
393 return x <= 0 ? 0 :
394 x >= 4096 ? 0xffff : x * 16;
395 }
396
397 uint32_t
398 radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
399 {
400 switch (stage) {
401 case MESA_SHADER_FRAGMENT:
402 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
403 case MESA_SHADER_VERTEX:
404 if (has_tess)
405 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
406 else
407 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
408 case MESA_SHADER_GEOMETRY:
409 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
410 case MESA_SHADER_COMPUTE:
411 return R_00B900_COMPUTE_USER_DATA_0;
412 case MESA_SHADER_TESS_CTRL:
413 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
414 case MESA_SHADER_TESS_EVAL:
415 if (has_gs)
416 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
417 else
418 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
419 default:
420 unreachable("unknown shader");
421 }
422 }
423
424 struct ac_userdata_info *
425 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
426 gl_shader_stage stage,
427 int idx)
428 {
429 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
430 }
431
432 static void
433 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline,
435 gl_shader_stage stage,
436 int idx, uint64_t va)
437 {
438 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
439 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
440 if (loc->sgpr_idx == -1)
441 return;
442 assert(loc->num_sgprs == 2);
443 assert(!loc->indirect);
444 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
445 radeon_emit(cmd_buffer->cs, va);
446 radeon_emit(cmd_buffer->cs, va >> 32);
447 }
448
449 static void
450 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
451 struct radv_pipeline *pipeline)
452 {
453 int num_samples = pipeline->graphics.ms.num_samples;
454 struct radv_multisample_state *ms = &pipeline->graphics.ms;
455 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
456
457 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
458 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
459 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
460
461 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
462 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
463
464 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
465 return;
466
467 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
468 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
469 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
470
471 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
472
473 /* GFX9: Flush DFSM when the AA mode changes. */
474 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
475 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
476 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
477 }
478 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
479 uint32_t offset;
480 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
481 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
482 if (loc->sgpr_idx == -1)
483 return;
484 assert(loc->num_sgprs == 1);
485 assert(!loc->indirect);
486 switch (num_samples) {
487 default:
488 offset = 0;
489 break;
490 case 2:
491 offset = 1;
492 break;
493 case 4:
494 offset = 3;
495 break;
496 case 8:
497 offset = 7;
498 break;
499 case 16:
500 offset = 15;
501 break;
502 }
503
504 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
505 cmd_buffer->sample_positions_needed = true;
506 }
507 }
508
509 static void
510 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 struct radv_raster_state *raster = &pipeline->graphics.raster;
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
516 raster->pa_cl_clip_cntl);
517
518 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
519 raster->spi_interp_control);
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
522 unsigned tmp = (unsigned)(1.0 * 8.0);
523 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
524 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
525 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
526
527 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
528 raster->pa_su_vtx_cntl);
529
530 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
531 raster->pa_su_sc_mode_cntl);
532 }
533
534 static inline void
535 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
536 unsigned size)
537 {
538 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
539 si_cp_dma_prefetch(cmd_buffer, va, size);
540 }
541
542 static void
543 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
544 struct radv_pipeline *pipeline,
545 struct radv_shader_variant *shader,
546 struct ac_vs_output_info *outinfo)
547 {
548 struct radeon_winsys *ws = cmd_buffer->device->ws;
549 uint64_t va = ws->buffer_get_va(shader->bo);
550 unsigned export_count;
551
552 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
553 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
554
555 export_count = MAX2(1, outinfo->param_exports);
556 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
557 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
558
559 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
560 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
561 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
562 V_02870C_SPI_SHADER_4COMP :
563 V_02870C_SPI_SHADER_NONE) |
564 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
565 V_02870C_SPI_SHADER_4COMP :
566 V_02870C_SPI_SHADER_NONE) |
567 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
568 V_02870C_SPI_SHADER_4COMP :
569 V_02870C_SPI_SHADER_NONE));
570
571
572 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
573 radeon_emit(cmd_buffer->cs, va >> 8);
574 radeon_emit(cmd_buffer->cs, va >> 40);
575 radeon_emit(cmd_buffer->cs, shader->rsrc1);
576 radeon_emit(cmd_buffer->cs, shader->rsrc2);
577
578 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
579 S_028818_VTX_W0_FMT(1) |
580 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
581 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
582 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
583
584
585 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
586 pipeline->graphics.pa_cl_vs_out_cntl);
587
588 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
589 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
590 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
591 }
592
593 static void
594 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
595 struct radv_shader_variant *shader,
596 struct ac_es_output_info *outinfo)
597 {
598 struct radeon_winsys *ws = cmd_buffer->device->ws;
599 uint64_t va = ws->buffer_get_va(shader->bo);
600
601 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
602 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
603
604 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
605 outinfo->esgs_itemsize / 4);
606 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
607 radeon_emit(cmd_buffer->cs, va >> 8);
608 radeon_emit(cmd_buffer->cs, va >> 40);
609 radeon_emit(cmd_buffer->cs, shader->rsrc1);
610 radeon_emit(cmd_buffer->cs, shader->rsrc2);
611 }
612
613 static void
614 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_shader_variant *shader)
616 {
617 struct radeon_winsys *ws = cmd_buffer->device->ws;
618 uint64_t va = ws->buffer_get_va(shader->bo);
619 uint32_t rsrc2 = shader->rsrc2;
620
621 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
622 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
623
624 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
625 radeon_emit(cmd_buffer->cs, va >> 8);
626 radeon_emit(cmd_buffer->cs, va >> 40);
627
628 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
629 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
630 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
631 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
632
633 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
634 radeon_emit(cmd_buffer->cs, shader->rsrc1);
635 radeon_emit(cmd_buffer->cs, rsrc2);
636 }
637
638 static void
639 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
640 struct radv_shader_variant *shader)
641 {
642 struct radeon_winsys *ws = cmd_buffer->device->ws;
643 uint64_t va = ws->buffer_get_va(shader->bo);
644
645 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
646 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
647
648 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
649 radeon_emit(cmd_buffer->cs, va >> 8);
650 radeon_emit(cmd_buffer->cs, va >> 40);
651 radeon_emit(cmd_buffer->cs, shader->rsrc1);
652 radeon_emit(cmd_buffer->cs, shader->rsrc2);
653 }
654
655 static void
656 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
657 struct radv_pipeline *pipeline)
658 {
659 struct radv_shader_variant *vs;
660
661 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
662
663 vs = pipeline->shaders[MESA_SHADER_VERTEX];
664
665 if (vs->info.vs.as_ls)
666 radv_emit_hw_ls(cmd_buffer, vs);
667 else if (vs->info.vs.as_es)
668 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
669 else
670 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
671
672 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
673 }
674
675
676 static void
677 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_pipeline *pipeline)
679 {
680 if (!radv_pipeline_has_tess(pipeline))
681 return;
682
683 struct radv_shader_variant *tes, *tcs;
684
685 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
686 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
687
688 if (tes->info.tes.as_es)
689 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
690 else
691 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
692
693 radv_emit_hw_hs(cmd_buffer, tcs);
694
695 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
696 pipeline->graphics.tess.tf_param);
697
698 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
699 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
700 pipeline->graphics.tess.ls_hs_config);
701 else
702 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
703 pipeline->graphics.tess.ls_hs_config);
704
705 struct ac_userdata_info *loc;
706
707 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
708 if (loc->sgpr_idx != -1) {
709 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
710 assert(loc->num_sgprs == 4);
711 assert(!loc->indirect);
712 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
713 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
714 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
715 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
716 pipeline->graphics.tess.num_tcs_input_cp << 26);
717 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
718 }
719
720 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
721 if (loc->sgpr_idx != -1) {
722 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
723 assert(loc->num_sgprs == 1);
724 assert(!loc->indirect);
725
726 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
727 pipeline->graphics.tess.offchip_layout);
728 }
729
730 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
731 if (loc->sgpr_idx != -1) {
732 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
733 assert(loc->num_sgprs == 1);
734 assert(!loc->indirect);
735
736 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
737 pipeline->graphics.tess.tcs_in_layout);
738 }
739 }
740
741 static void
742 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
743 struct radv_pipeline *pipeline)
744 {
745 struct radeon_winsys *ws = cmd_buffer->device->ws;
746 struct radv_shader_variant *gs;
747 uint64_t va;
748
749 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
750
751 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
752 if (!gs)
753 return;
754
755 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
756
757 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
758 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
759 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
760 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
761
762 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
763
764 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
765
766 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
767 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
768 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
769 radeon_emit(cmd_buffer->cs, 0);
770 radeon_emit(cmd_buffer->cs, 0);
771 radeon_emit(cmd_buffer->cs, 0);
772
773 uint32_t gs_num_invocations = gs->info.gs.invocations;
774 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
775 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
776 S_028B90_ENABLE(gs_num_invocations > 0));
777
778 va = ws->buffer_get_va(gs->bo);
779 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
780 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
781
782 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
783 radeon_emit(cmd_buffer->cs, va >> 8);
784 radeon_emit(cmd_buffer->cs, va >> 40);
785 radeon_emit(cmd_buffer->cs, gs->rsrc1);
786 radeon_emit(cmd_buffer->cs, gs->rsrc2);
787
788 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
789
790 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
791 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
792 if (loc->sgpr_idx != -1) {
793 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
794 uint32_t num_entries = 64;
795 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
796
797 if (is_vi)
798 num_entries *= stride;
799
800 stride = S_008F04_STRIDE(stride);
801 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
802 radeon_emit(cmd_buffer->cs, stride);
803 radeon_emit(cmd_buffer->cs, num_entries);
804 }
805 }
806
807 static void
808 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
809 struct radv_pipeline *pipeline)
810 {
811 struct radeon_winsys *ws = cmd_buffer->device->ws;
812 struct radv_shader_variant *ps;
813 uint64_t va;
814 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
815 struct radv_blend_state *blend = &pipeline->graphics.blend;
816 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
817
818 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
819
820 va = ws->buffer_get_va(ps->bo);
821 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
822 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
823
824 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
825 radeon_emit(cmd_buffer->cs, va >> 8);
826 radeon_emit(cmd_buffer->cs, va >> 40);
827 radeon_emit(cmd_buffer->cs, ps->rsrc1);
828 radeon_emit(cmd_buffer->cs, ps->rsrc2);
829
830 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
831 pipeline->graphics.db_shader_control);
832
833 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
834 ps->config.spi_ps_input_ena);
835
836 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
837 ps->config.spi_ps_input_addr);
838
839 if (ps->info.fs.force_persample)
840 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
841
842 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
843 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
844
845 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
848 pipeline->graphics.shader_z_format);
849
850 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
851
852 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
853 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
854
855 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
856 /* optimise this? */
857 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
858 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
859 }
860
861 if (pipeline->graphics.ps_input_cntl_num) {
862 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
863 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
864 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
865 }
866 }
867 }
868
869 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
870 struct radv_pipeline *pipeline)
871 {
872 uint32_t vtx_reuse_depth = 30;
873 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
874 return;
875
876 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
877 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
878 vtx_reuse_depth = 14;
879 }
880 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
881 vtx_reuse_depth);
882 }
883
884 static void
885 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
886 struct radv_pipeline *pipeline)
887 {
888 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
889 return;
890
891 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
892 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
893 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
894 radv_update_multisample_state(cmd_buffer, pipeline);
895 radv_emit_vertex_shader(cmd_buffer, pipeline);
896 radv_emit_tess_shaders(cmd_buffer, pipeline);
897 radv_emit_geometry_shader(cmd_buffer, pipeline);
898 radv_emit_fragment_shader(cmd_buffer, pipeline);
899 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
900
901 cmd_buffer->scratch_size_needed =
902 MAX2(cmd_buffer->scratch_size_needed,
903 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
904
905 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
906 S_0286E8_WAVES(pipeline->max_waves) |
907 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
908
909 if (!cmd_buffer->state.emitted_pipeline ||
910 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
911 pipeline->graphics.can_use_guardband)
912 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
913
914 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
915
916 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
917 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
918 } else {
919 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
920 }
921 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
922
923 cmd_buffer->state.emitted_pipeline = pipeline;
924 }
925
926 static void
927 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
928 {
929 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
930 cmd_buffer->state.dynamic.viewport.viewports);
931 }
932
933 static void
934 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
935 {
936 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
937 si_write_scissors(cmd_buffer->cs, 0, count,
938 cmd_buffer->state.dynamic.scissor.scissors,
939 cmd_buffer->state.dynamic.viewport.viewports,
940 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
941 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
942 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
943 }
944
945 static void
946 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
947 int index,
948 struct radv_color_buffer_info *cb)
949 {
950 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
951
952 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
953 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
954 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
955 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
956 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
957 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
958 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
959 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
960 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
963 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
964 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
965
966 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
967 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
968 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
969
970 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
971 cb->gfx9_epitch);
972 } else {
973 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
974 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
975 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
976 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
977 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
978 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
979 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
980 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
981 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
982 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
983 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
984 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
985
986 if (is_vi) { /* DCC BASE */
987 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
988 }
989 }
990 }
991
992 static void
993 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
994 struct radv_ds_buffer_info *ds,
995 struct radv_image *image,
996 VkImageLayout layout)
997 {
998 uint32_t db_z_info = ds->db_z_info;
999 uint32_t db_stencil_info = ds->db_stencil_info;
1000
1001 if (!radv_layout_has_htile(image, layout,
1002 radv_image_queue_family_mask(image,
1003 cmd_buffer->queue_family_index,
1004 cmd_buffer->queue_family_index))) {
1005 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1006 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1007 }
1008
1009 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1010
1011 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1012 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1013 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1014 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1015 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1016
1017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1018 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1019 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1020 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1021 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1022 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1023 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1024 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1025 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1026 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1027 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1028
1029 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1030 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1031 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1032 } else {
1033 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1034
1035 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1036 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1037 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1038 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1039 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1040 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1041 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1042 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1043 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1044 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1045
1046 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1047 }
1048
1049 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1050 ds->pa_su_poly_offset_db_fmt_cntl);
1051 }
1052
1053 void
1054 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1055 struct radv_image *image,
1056 VkClearDepthStencilValue ds_clear_value,
1057 VkImageAspectFlags aspects)
1058 {
1059 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1060 va += image->offset + image->clear_value_offset;
1061 unsigned reg_offset = 0, reg_count = 0;
1062
1063 if (!image->surface.htile_size || !aspects)
1064 return;
1065
1066 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1067 ++reg_count;
1068 } else {
1069 ++reg_offset;
1070 va += 4;
1071 }
1072 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1073 ++reg_count;
1074
1075 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1076
1077 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1078 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1079 S_370_WR_CONFIRM(1) |
1080 S_370_ENGINE_SEL(V_370_PFP));
1081 radeon_emit(cmd_buffer->cs, va);
1082 radeon_emit(cmd_buffer->cs, va >> 32);
1083 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1084 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1085 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1086 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1087
1088 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1089 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1090 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1091 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1092 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1093 }
1094
1095 static void
1096 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1097 struct radv_image *image)
1098 {
1099 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1100 va += image->offset + image->clear_value_offset;
1101
1102 if (!image->surface.htile_size)
1103 return;
1104
1105 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1106
1107 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1108 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1109 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1110 COPY_DATA_COUNT_SEL);
1111 radeon_emit(cmd_buffer->cs, va);
1112 radeon_emit(cmd_buffer->cs, va >> 32);
1113 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1114 radeon_emit(cmd_buffer->cs, 0);
1115
1116 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1117 radeon_emit(cmd_buffer->cs, 0);
1118 }
1119
1120 /*
1121 *with DCC some colors don't require CMASK elimiation before being
1122 * used as a texture. This sets a predicate value to determine if the
1123 * cmask eliminate is required.
1124 */
1125 void
1126 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1127 struct radv_image *image,
1128 bool value)
1129 {
1130 uint64_t pred_val = value;
1131 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1132 va += image->offset + image->dcc_pred_offset;
1133
1134 if (!image->surface.dcc_size)
1135 return;
1136
1137 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1138
1139 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1140 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1141 S_370_WR_CONFIRM(1) |
1142 S_370_ENGINE_SEL(V_370_PFP));
1143 radeon_emit(cmd_buffer->cs, va);
1144 radeon_emit(cmd_buffer->cs, va >> 32);
1145 radeon_emit(cmd_buffer->cs, pred_val);
1146 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1147 }
1148
1149 void
1150 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1151 struct radv_image *image,
1152 int idx,
1153 uint32_t color_values[2])
1154 {
1155 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1156 va += image->offset + image->clear_value_offset;
1157
1158 if (!image->cmask.size && !image->surface.dcc_size)
1159 return;
1160
1161 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1162
1163 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1164 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1165 S_370_WR_CONFIRM(1) |
1166 S_370_ENGINE_SEL(V_370_PFP));
1167 radeon_emit(cmd_buffer->cs, va);
1168 radeon_emit(cmd_buffer->cs, va >> 32);
1169 radeon_emit(cmd_buffer->cs, color_values[0]);
1170 radeon_emit(cmd_buffer->cs, color_values[1]);
1171
1172 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1173 radeon_emit(cmd_buffer->cs, color_values[0]);
1174 radeon_emit(cmd_buffer->cs, color_values[1]);
1175 }
1176
1177 static void
1178 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1179 struct radv_image *image,
1180 int idx)
1181 {
1182 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1183 va += image->offset + image->clear_value_offset;
1184
1185 if (!image->cmask.size && !image->surface.dcc_size)
1186 return;
1187
1188 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1189 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1190
1191 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1192 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1193 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1194 COPY_DATA_COUNT_SEL);
1195 radeon_emit(cmd_buffer->cs, va);
1196 radeon_emit(cmd_buffer->cs, va >> 32);
1197 radeon_emit(cmd_buffer->cs, reg >> 2);
1198 radeon_emit(cmd_buffer->cs, 0);
1199
1200 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1201 radeon_emit(cmd_buffer->cs, 0);
1202 }
1203
1204 void
1205 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1206 {
1207 int i;
1208 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1209 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1210
1211 for (i = 0; i < subpass->color_count; ++i) {
1212 int idx = subpass->color_attachments[i].attachment;
1213 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1214
1215 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1216
1217 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1218 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1219
1220 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1221 }
1222
1223 for (i = subpass->color_count; i < 8; i++)
1224 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1225 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1226
1227 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1228 int idx = subpass->depth_stencil_attachment.attachment;
1229 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1230 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1231 struct radv_image *image = att->attachment->image;
1232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1233 uint32_t queue_mask = radv_image_queue_family_mask(image,
1234 cmd_buffer->queue_family_index,
1235 cmd_buffer->queue_family_index);
1236 /* We currently don't support writing decompressed HTILE */
1237 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1238 radv_layout_is_htile_compressed(image, layout, queue_mask));
1239
1240 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1241
1242 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1243 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1244 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1245 }
1246 radv_load_depth_clear_regs(cmd_buffer, image);
1247 } else {
1248 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1249 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1250 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1251 }
1252 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1253 S_028208_BR_X(framebuffer->width) |
1254 S_028208_BR_Y(framebuffer->height));
1255
1256 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1257 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1258 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1259 }
1260 }
1261
1262 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1263 {
1264 uint32_t db_count_control;
1265
1266 if(!cmd_buffer->state.active_occlusion_queries) {
1267 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1268 db_count_control = 0;
1269 } else {
1270 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1271 }
1272 } else {
1273 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1274 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1275 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1276 S_028004_ZPASS_ENABLE(1) |
1277 S_028004_SLICE_EVEN_ENABLE(1) |
1278 S_028004_SLICE_ODD_ENABLE(1);
1279 } else {
1280 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1281 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1282 }
1283 }
1284
1285 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1286 }
1287
1288 static void
1289 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1290 {
1291 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1292
1293 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1294 return;
1295
1296 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1297 radv_emit_viewport(cmd_buffer);
1298
1299 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1300 radv_emit_scissor(cmd_buffer);
1301
1302 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1303 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1304 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1305 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1306 }
1307
1308 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1309 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1310 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1311 }
1312
1313 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1314 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1315 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1316 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1317 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1318 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1319 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1320 S_028430_STENCILOPVAL(1));
1321 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1322 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1323 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1324 S_028434_STENCILOPVAL_BF(1));
1325 }
1326
1327 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1328 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1329 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1330 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1331 }
1332
1333 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1334 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1335 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1336 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1337 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1338
1339 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1340 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1341 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1342 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1343 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1344 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1345 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1346 }
1347 }
1348
1349 cmd_buffer->state.dirty = 0;
1350 }
1351
1352 static void
1353 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1354 struct radv_pipeline *pipeline,
1355 int idx,
1356 uint64_t va,
1357 gl_shader_stage stage)
1358 {
1359 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1360 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1361
1362 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1363 return;
1364
1365 assert(!desc_set_loc->indirect);
1366 assert(desc_set_loc->num_sgprs == 2);
1367 radeon_set_sh_reg_seq(cmd_buffer->cs,
1368 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1369 radeon_emit(cmd_buffer->cs, va);
1370 radeon_emit(cmd_buffer->cs, va >> 32);
1371 }
1372
1373 static void
1374 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1375 VkShaderStageFlags stages,
1376 struct radv_descriptor_set *set,
1377 unsigned idx)
1378 {
1379 if (cmd_buffer->state.pipeline) {
1380 radv_foreach_stage(stage, stages) {
1381 if (cmd_buffer->state.pipeline->shaders[stage])
1382 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1383 idx, set->va,
1384 stage);
1385 }
1386 }
1387
1388 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1389 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1390 idx, set->va,
1391 MESA_SHADER_COMPUTE);
1392 }
1393
1394 static void
1395 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1396 {
1397 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1398 uint32_t *ptr = NULL;
1399 unsigned bo_offset;
1400
1401 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1402 &bo_offset,
1403 (void**) &ptr))
1404 return;
1405
1406 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1407 set->va += bo_offset;
1408
1409 memcpy(ptr, set->mapped_ptr, set->size);
1410 }
1411
1412 static void
1413 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1414 {
1415 uint32_t size = MAX_SETS * 2 * 4;
1416 uint32_t offset;
1417 void *ptr;
1418
1419 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1420 256, &offset, &ptr))
1421 return;
1422
1423 for (unsigned i = 0; i < MAX_SETS; i++) {
1424 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1425 uint64_t set_va = 0;
1426 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1427 if (set)
1428 set_va = set->va;
1429 uptr[0] = set_va & 0xffffffff;
1430 uptr[1] = set_va >> 32;
1431 }
1432
1433 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1434 va += offset;
1435
1436 if (cmd_buffer->state.pipeline) {
1437 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1438 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1439 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1440
1441 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1442 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1443 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1444
1445 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1446 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1447 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1448
1449 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1450 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1451 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1452
1453 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1454 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1455 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1456 }
1457
1458 if (cmd_buffer->state.compute_pipeline)
1459 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1460 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1461 }
1462
1463 static void
1464 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1465 VkShaderStageFlags stages)
1466 {
1467 unsigned i;
1468
1469 if (!cmd_buffer->state.descriptors_dirty)
1470 return;
1471
1472 if (cmd_buffer->state.push_descriptors_dirty)
1473 radv_flush_push_descriptors(cmd_buffer);
1474
1475 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1476 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1477 radv_flush_indirect_descriptor_sets(cmd_buffer);
1478 }
1479
1480 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1481 cmd_buffer->cs,
1482 MAX_SETS * MESA_SHADER_STAGES * 4);
1483
1484 for (i = 0; i < MAX_SETS; i++) {
1485 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1486 continue;
1487 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1488 if (!set)
1489 continue;
1490
1491 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1492 }
1493 cmd_buffer->state.descriptors_dirty = 0;
1494 cmd_buffer->state.push_descriptors_dirty = false;
1495 assert(cmd_buffer->cs->cdw <= cdw_max);
1496 }
1497
1498 static void
1499 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1500 struct radv_pipeline *pipeline,
1501 VkShaderStageFlags stages)
1502 {
1503 struct radv_pipeline_layout *layout = pipeline->layout;
1504 unsigned offset;
1505 void *ptr;
1506 uint64_t va;
1507
1508 stages &= cmd_buffer->push_constant_stages;
1509 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1510 return;
1511
1512 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1513 16 * layout->dynamic_offset_count,
1514 256, &offset, &ptr))
1515 return;
1516
1517 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1518 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1519 16 * layout->dynamic_offset_count);
1520
1521 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1522 va += offset;
1523
1524 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1525 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1526
1527 radv_foreach_stage(stage, stages) {
1528 if (pipeline->shaders[stage]) {
1529 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1530 AC_UD_PUSH_CONSTANTS, va);
1531 }
1532 }
1533
1534 cmd_buffer->push_constant_stages &= ~stages;
1535 assert(cmd_buffer->cs->cdw <= cdw_max);
1536 }
1537
1538 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1539 bool indexed_draw)
1540 {
1541 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1542
1543 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1544 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1545 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1546 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1547 primitive_reset_en);
1548 } else {
1549 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1550 primitive_reset_en);
1551 }
1552 }
1553
1554 if (primitive_reset_en) {
1555 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1556
1557 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1558 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1559 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1560 primitive_reset_index);
1561 }
1562 }
1563 }
1564
1565 static void
1566 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1567 {
1568 struct radv_device *device = cmd_buffer->device;
1569
1570 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1571 cmd_buffer->state.pipeline->num_vertex_attribs &&
1572 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1573 unsigned vb_offset;
1574 void *vb_ptr;
1575 uint32_t i = 0;
1576 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1577 uint64_t va;
1578
1579 /* allocate some descriptor state for vertex buffers */
1580 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1581 &vb_offset, &vb_ptr);
1582
1583 for (i = 0; i < num_attribs; i++) {
1584 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1585 uint32_t offset;
1586 int vb = cmd_buffer->state.pipeline->va_binding[i];
1587 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1588 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1589
1590 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1591 va = device->ws->buffer_get_va(buffer->bo);
1592
1593 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1594 va += offset + buffer->offset;
1595 desc[0] = va;
1596 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1597 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1598 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1599 else
1600 desc[2] = buffer->size - offset;
1601 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1602 }
1603
1604 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1605 va += vb_offset;
1606
1607 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1608 AC_UD_VS_VERTEX_BUFFERS, va);
1609 }
1610 cmd_buffer->state.vb_dirty = 0;
1611 }
1612
1613 static void
1614 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1615 bool indexed_draw, bool instanced_draw,
1616 bool indirect_draw,
1617 uint32_t draw_vertex_count)
1618 {
1619 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1620 uint32_t ia_multi_vgt_param;
1621
1622 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1623 cmd_buffer->cs, 4096);
1624
1625 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer);
1626
1627 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1628 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1629
1630 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1631 radv_emit_framebuffer_state(cmd_buffer);
1632
1633 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1634 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1635 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1636 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1637 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1638 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1639 else
1640 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1641 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1642 }
1643
1644 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1645
1646 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1647
1648 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1649 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1650 VK_SHADER_STAGE_ALL_GRAPHICS);
1651
1652 assert(cmd_buffer->cs->cdw <= cdw_max);
1653
1654 si_emit_cache_flush(cmd_buffer);
1655 }
1656
1657 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1658 VkPipelineStageFlags src_stage_mask)
1659 {
1660 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1661 VK_PIPELINE_STAGE_TRANSFER_BIT |
1662 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1663 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1664 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1665 }
1666
1667 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1668 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1669 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1670 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1671 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1672 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1673 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1674 VK_PIPELINE_STAGE_TRANSFER_BIT |
1675 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1676 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1677 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1678 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1679 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1680 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1681 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1682 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1683 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1684 }
1685 }
1686
1687 static enum radv_cmd_flush_bits
1688 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1689 VkAccessFlags src_flags)
1690 {
1691 enum radv_cmd_flush_bits flush_bits = 0;
1692 uint32_t b;
1693 for_each_bit(b, src_flags) {
1694 switch ((VkAccessFlagBits)(1 << b)) {
1695 case VK_ACCESS_SHADER_WRITE_BIT:
1696 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1697 break;
1698 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1699 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1700 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1701 break;
1702 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1703 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1704 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1705 break;
1706 case VK_ACCESS_TRANSFER_WRITE_BIT:
1707 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1708 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1709 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1710 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1711 RADV_CMD_FLAG_INV_GLOBAL_L2;
1712 break;
1713 default:
1714 break;
1715 }
1716 }
1717 return flush_bits;
1718 }
1719
1720 static enum radv_cmd_flush_bits
1721 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1722 VkAccessFlags dst_flags,
1723 struct radv_image *image)
1724 {
1725 enum radv_cmd_flush_bits flush_bits = 0;
1726 uint32_t b;
1727 for_each_bit(b, dst_flags) {
1728 switch ((VkAccessFlagBits)(1 << b)) {
1729 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1730 case VK_ACCESS_INDEX_READ_BIT:
1731 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1732 break;
1733 case VK_ACCESS_UNIFORM_READ_BIT:
1734 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1735 break;
1736 case VK_ACCESS_SHADER_READ_BIT:
1737 case VK_ACCESS_TRANSFER_READ_BIT:
1738 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1739 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1740 RADV_CMD_FLAG_INV_GLOBAL_L2;
1741 break;
1742 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1743 /* TODO: change to image && when the image gets passed
1744 * through from the subpass. */
1745 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1746 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1747 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1748 break;
1749 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1750 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1751 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1752 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1753 break;
1754 default:
1755 break;
1756 }
1757 }
1758 return flush_bits;
1759 }
1760
1761 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1762 {
1763 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1764 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1765 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1766 NULL);
1767 }
1768
1769 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1770 VkAttachmentReference att)
1771 {
1772 unsigned idx = att.attachment;
1773 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1774 VkImageSubresourceRange range;
1775 range.aspectMask = 0;
1776 range.baseMipLevel = view->base_mip;
1777 range.levelCount = 1;
1778 range.baseArrayLayer = view->base_layer;
1779 range.layerCount = cmd_buffer->state.framebuffer->layers;
1780
1781 radv_handle_image_transition(cmd_buffer,
1782 view->image,
1783 cmd_buffer->state.attachments[idx].current_layout,
1784 att.layout, 0, 0, &range,
1785 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1786
1787 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1788
1789
1790 }
1791
1792 void
1793 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1794 const struct radv_subpass *subpass, bool transitions)
1795 {
1796 if (transitions) {
1797 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1798
1799 for (unsigned i = 0; i < subpass->color_count; ++i) {
1800 radv_handle_subpass_image_transition(cmd_buffer,
1801 subpass->color_attachments[i]);
1802 }
1803
1804 for (unsigned i = 0; i < subpass->input_count; ++i) {
1805 radv_handle_subpass_image_transition(cmd_buffer,
1806 subpass->input_attachments[i]);
1807 }
1808
1809 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1810 radv_handle_subpass_image_transition(cmd_buffer,
1811 subpass->depth_stencil_attachment);
1812 }
1813 }
1814
1815 cmd_buffer->state.subpass = subpass;
1816
1817 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1818 }
1819
1820 static void
1821 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1822 struct radv_render_pass *pass,
1823 const VkRenderPassBeginInfo *info)
1824 {
1825 struct radv_cmd_state *state = &cmd_buffer->state;
1826
1827 if (pass->attachment_count == 0) {
1828 state->attachments = NULL;
1829 return;
1830 }
1831
1832 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1833 pass->attachment_count *
1834 sizeof(state->attachments[0]),
1835 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1836 if (state->attachments == NULL) {
1837 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1838 abort();
1839 }
1840
1841 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1842 struct radv_render_pass_attachment *att = &pass->attachments[i];
1843 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1844 VkImageAspectFlags clear_aspects = 0;
1845
1846 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1847 /* color attachment */
1848 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1849 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1850 }
1851 } else {
1852 /* depthstencil attachment */
1853 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1854 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1855 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1856 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1857 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1858 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1859 }
1860 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1861 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1862 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1863 }
1864 }
1865
1866 state->attachments[i].pending_clear_aspects = clear_aspects;
1867 if (clear_aspects && info) {
1868 assert(info->clearValueCount > i);
1869 state->attachments[i].clear_value = info->pClearValues[i];
1870 }
1871
1872 state->attachments[i].current_layout = att->initial_layout;
1873 }
1874 }
1875
1876 VkResult radv_AllocateCommandBuffers(
1877 VkDevice _device,
1878 const VkCommandBufferAllocateInfo *pAllocateInfo,
1879 VkCommandBuffer *pCommandBuffers)
1880 {
1881 RADV_FROM_HANDLE(radv_device, device, _device);
1882 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1883
1884 VkResult result = VK_SUCCESS;
1885 uint32_t i;
1886
1887 memset(pCommandBuffers, 0,
1888 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1889
1890 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1891
1892 if (!list_empty(&pool->free_cmd_buffers)) {
1893 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1894
1895 list_del(&cmd_buffer->pool_link);
1896 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1897
1898 radv_reset_cmd_buffer(cmd_buffer);
1899 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1900 cmd_buffer->level = pAllocateInfo->level;
1901
1902 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1903 result = VK_SUCCESS;
1904 } else {
1905 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1906 &pCommandBuffers[i]);
1907 }
1908 if (result != VK_SUCCESS)
1909 break;
1910 }
1911
1912 if (result != VK_SUCCESS)
1913 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1914 i, pCommandBuffers);
1915
1916 return result;
1917 }
1918
1919 void radv_FreeCommandBuffers(
1920 VkDevice device,
1921 VkCommandPool commandPool,
1922 uint32_t commandBufferCount,
1923 const VkCommandBuffer *pCommandBuffers)
1924 {
1925 for (uint32_t i = 0; i < commandBufferCount; i++) {
1926 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1927
1928 if (cmd_buffer) {
1929 if (cmd_buffer->pool) {
1930 list_del(&cmd_buffer->pool_link);
1931 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1932 } else
1933 radv_cmd_buffer_destroy(cmd_buffer);
1934
1935 }
1936 }
1937 }
1938
1939 VkResult radv_ResetCommandBuffer(
1940 VkCommandBuffer commandBuffer,
1941 VkCommandBufferResetFlags flags)
1942 {
1943 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1944 radv_reset_cmd_buffer(cmd_buffer);
1945 return VK_SUCCESS;
1946 }
1947
1948 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1949 {
1950 struct radv_device *device = cmd_buffer->device;
1951 if (device->gfx_init) {
1952 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1953 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1954 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1955 radeon_emit(cmd_buffer->cs, va);
1956 radeon_emit(cmd_buffer->cs, va >> 32);
1957 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1958 } else
1959 si_init_config(cmd_buffer);
1960 }
1961
1962 VkResult radv_BeginCommandBuffer(
1963 VkCommandBuffer commandBuffer,
1964 const VkCommandBufferBeginInfo *pBeginInfo)
1965 {
1966 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1967 radv_reset_cmd_buffer(cmd_buffer);
1968
1969 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1970 cmd_buffer->state.last_primitive_reset_en = -1;
1971
1972 /* setup initial configuration into command buffer */
1973 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1974 switch (cmd_buffer->queue_family_index) {
1975 case RADV_QUEUE_GENERAL:
1976 emit_gfx_buffer_state(cmd_buffer);
1977 radv_set_db_count_control(cmd_buffer);
1978 break;
1979 case RADV_QUEUE_COMPUTE:
1980 si_init_compute(cmd_buffer);
1981 break;
1982 case RADV_QUEUE_TRANSFER:
1983 default:
1984 break;
1985 }
1986 }
1987
1988 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1989 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1990 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1991
1992 struct radv_subpass *subpass =
1993 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1994
1995 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1996 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1997 }
1998
1999 radv_cmd_buffer_trace_emit(cmd_buffer);
2000 return VK_SUCCESS;
2001 }
2002
2003 void radv_CmdBindVertexBuffers(
2004 VkCommandBuffer commandBuffer,
2005 uint32_t firstBinding,
2006 uint32_t bindingCount,
2007 const VkBuffer* pBuffers,
2008 const VkDeviceSize* pOffsets)
2009 {
2010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2011 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2012
2013 /* We have to defer setting up vertex buffer since we need the buffer
2014 * stride from the pipeline. */
2015
2016 assert(firstBinding + bindingCount < MAX_VBS);
2017 for (uint32_t i = 0; i < bindingCount; i++) {
2018 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2019 vb[firstBinding + i].offset = pOffsets[i];
2020 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
2021 }
2022 }
2023
2024 void radv_CmdBindIndexBuffer(
2025 VkCommandBuffer commandBuffer,
2026 VkBuffer buffer,
2027 VkDeviceSize offset,
2028 VkIndexType indexType)
2029 {
2030 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2031 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2032
2033 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2034 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2035 cmd_buffer->state.index_va += index_buffer->offset + offset;
2036
2037 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2038 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2039 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2040 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2041 }
2042
2043
2044 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2045 struct radv_descriptor_set *set,
2046 unsigned idx)
2047 {
2048 struct radeon_winsys *ws = cmd_buffer->device->ws;
2049
2050 cmd_buffer->state.descriptors[idx] = set;
2051 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2052 if (!set)
2053 return;
2054
2055 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2056
2057 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2058 if (set->descriptors[j])
2059 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2060
2061 if(set->bo)
2062 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2063 }
2064
2065 void radv_CmdBindDescriptorSets(
2066 VkCommandBuffer commandBuffer,
2067 VkPipelineBindPoint pipelineBindPoint,
2068 VkPipelineLayout _layout,
2069 uint32_t firstSet,
2070 uint32_t descriptorSetCount,
2071 const VkDescriptorSet* pDescriptorSets,
2072 uint32_t dynamicOffsetCount,
2073 const uint32_t* pDynamicOffsets)
2074 {
2075 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2076 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2077 unsigned dyn_idx = 0;
2078
2079 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2080 unsigned idx = i + firstSet;
2081 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2082 radv_bind_descriptor_set(cmd_buffer, set, idx);
2083
2084 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2085 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2086 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2087 assert(dyn_idx < dynamicOffsetCount);
2088
2089 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2090 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2091 dst[0] = va;
2092 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2093 dst[2] = range->size;
2094 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2095 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2096 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2097 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2098 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2099 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2100 cmd_buffer->push_constant_stages |=
2101 set->layout->dynamic_shader_stages;
2102 }
2103 }
2104 }
2105
2106 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2107 struct radv_descriptor_set *set,
2108 struct radv_descriptor_set_layout *layout)
2109 {
2110 set->size = layout->size;
2111 set->layout = layout;
2112
2113 if (cmd_buffer->push_descriptors.capacity < set->size) {
2114 size_t new_size = MAX2(set->size, 1024);
2115 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2116 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2117
2118 free(set->mapped_ptr);
2119 set->mapped_ptr = malloc(new_size);
2120
2121 if (!set->mapped_ptr) {
2122 cmd_buffer->push_descriptors.capacity = 0;
2123 cmd_buffer->record_fail = true;
2124 return false;
2125 }
2126
2127 cmd_buffer->push_descriptors.capacity = new_size;
2128 }
2129
2130 return true;
2131 }
2132
2133 void radv_meta_push_descriptor_set(
2134 struct radv_cmd_buffer* cmd_buffer,
2135 VkPipelineBindPoint pipelineBindPoint,
2136 VkPipelineLayout _layout,
2137 uint32_t set,
2138 uint32_t descriptorWriteCount,
2139 const VkWriteDescriptorSet* pDescriptorWrites)
2140 {
2141 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2142 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2143 unsigned bo_offset;
2144
2145 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2146
2147 push_set->size = layout->set[set].layout->size;
2148 push_set->layout = layout->set[set].layout;
2149
2150 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2151 &bo_offset,
2152 (void**) &push_set->mapped_ptr))
2153 return;
2154
2155 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2156 push_set->va += bo_offset;
2157
2158 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2159 radv_descriptor_set_to_handle(push_set),
2160 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2161
2162 cmd_buffer->state.descriptors[set] = push_set;
2163 cmd_buffer->state.descriptors_dirty |= (1u << set);
2164 }
2165
2166 void radv_CmdPushDescriptorSetKHR(
2167 VkCommandBuffer commandBuffer,
2168 VkPipelineBindPoint pipelineBindPoint,
2169 VkPipelineLayout _layout,
2170 uint32_t set,
2171 uint32_t descriptorWriteCount,
2172 const VkWriteDescriptorSet* pDescriptorWrites)
2173 {
2174 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2175 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2176 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2177
2178 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2179
2180 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2181 return;
2182
2183 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2184 radv_descriptor_set_to_handle(push_set),
2185 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2186
2187 cmd_buffer->state.descriptors[set] = push_set;
2188 cmd_buffer->state.descriptors_dirty |= (1u << set);
2189 cmd_buffer->state.push_descriptors_dirty = true;
2190 }
2191
2192 void radv_CmdPushDescriptorSetWithTemplateKHR(
2193 VkCommandBuffer commandBuffer,
2194 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2195 VkPipelineLayout _layout,
2196 uint32_t set,
2197 const void* pData)
2198 {
2199 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2200 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2201 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2202
2203 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2204
2205 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2206 return;
2207
2208 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2209 descriptorUpdateTemplate, pData);
2210
2211 cmd_buffer->state.descriptors[set] = push_set;
2212 cmd_buffer->state.descriptors_dirty |= (1u << set);
2213 cmd_buffer->state.push_descriptors_dirty = true;
2214 }
2215
2216 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2217 VkPipelineLayout layout,
2218 VkShaderStageFlags stageFlags,
2219 uint32_t offset,
2220 uint32_t size,
2221 const void* pValues)
2222 {
2223 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2224 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2225 cmd_buffer->push_constant_stages |= stageFlags;
2226 }
2227
2228 VkResult radv_EndCommandBuffer(
2229 VkCommandBuffer commandBuffer)
2230 {
2231 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2232
2233 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2234 si_emit_cache_flush(cmd_buffer);
2235
2236 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2237 cmd_buffer->record_fail)
2238 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2239 return VK_SUCCESS;
2240 }
2241
2242 static void
2243 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2244 {
2245 struct radeon_winsys *ws = cmd_buffer->device->ws;
2246 struct radv_shader_variant *compute_shader;
2247 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2248 uint64_t va;
2249
2250 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2251 return;
2252
2253 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2254
2255 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2256 va = ws->buffer_get_va(compute_shader->bo);
2257
2258 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2259 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2260
2261 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2262 cmd_buffer->cs, 16);
2263
2264 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2265 radeon_emit(cmd_buffer->cs, va >> 8);
2266 radeon_emit(cmd_buffer->cs, va >> 40);
2267
2268 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2269 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2270 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2271
2272
2273 cmd_buffer->compute_scratch_size_needed =
2274 MAX2(cmd_buffer->compute_scratch_size_needed,
2275 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2276
2277 /* change these once we have scratch support */
2278 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2279 S_00B860_WAVES(pipeline->max_waves) |
2280 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2281
2282 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2283 radeon_emit(cmd_buffer->cs,
2284 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2285 radeon_emit(cmd_buffer->cs,
2286 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2287 radeon_emit(cmd_buffer->cs,
2288 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2289
2290 assert(cmd_buffer->cs->cdw <= cdw_max);
2291 }
2292
2293 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2294 {
2295 for (unsigned i = 0; i < MAX_SETS; i++) {
2296 if (cmd_buffer->state.descriptors[i])
2297 cmd_buffer->state.descriptors_dirty |= (1u << i);
2298 }
2299 }
2300
2301 void radv_CmdBindPipeline(
2302 VkCommandBuffer commandBuffer,
2303 VkPipelineBindPoint pipelineBindPoint,
2304 VkPipeline _pipeline)
2305 {
2306 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2307 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2308
2309 radv_mark_descriptor_sets_dirty(cmd_buffer);
2310
2311 switch (pipelineBindPoint) {
2312 case VK_PIPELINE_BIND_POINT_COMPUTE:
2313 cmd_buffer->state.compute_pipeline = pipeline;
2314 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2315 break;
2316 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2317 cmd_buffer->state.pipeline = pipeline;
2318 if (!pipeline)
2319 break;
2320
2321 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2322 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2323
2324 /* Apply the dynamic state from the pipeline */
2325 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2326 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2327 &pipeline->dynamic_state,
2328 pipeline->dynamic_state_mask);
2329
2330 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2331 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2332 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2333 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2334
2335 if (radv_pipeline_has_tess(pipeline))
2336 cmd_buffer->tess_rings_needed = true;
2337
2338 if (radv_pipeline_has_gs(pipeline)) {
2339 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2340 AC_UD_SCRATCH_RING_OFFSETS);
2341 if (cmd_buffer->ring_offsets_idx == -1)
2342 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2343 else if (loc->sgpr_idx != -1)
2344 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2345 }
2346 break;
2347 default:
2348 assert(!"invalid bind point");
2349 break;
2350 }
2351 }
2352
2353 void radv_CmdSetViewport(
2354 VkCommandBuffer commandBuffer,
2355 uint32_t firstViewport,
2356 uint32_t viewportCount,
2357 const VkViewport* pViewports)
2358 {
2359 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2360
2361 const uint32_t total_count = firstViewport + viewportCount;
2362 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2363 cmd_buffer->state.dynamic.viewport.count = total_count;
2364
2365 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2366 pViewports, viewportCount * sizeof(*pViewports));
2367
2368 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2369 }
2370
2371 void radv_CmdSetScissor(
2372 VkCommandBuffer commandBuffer,
2373 uint32_t firstScissor,
2374 uint32_t scissorCount,
2375 const VkRect2D* pScissors)
2376 {
2377 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2378
2379 const uint32_t total_count = firstScissor + scissorCount;
2380 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2381 cmd_buffer->state.dynamic.scissor.count = total_count;
2382
2383 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2384 pScissors, scissorCount * sizeof(*pScissors));
2385 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2386 }
2387
2388 void radv_CmdSetLineWidth(
2389 VkCommandBuffer commandBuffer,
2390 float lineWidth)
2391 {
2392 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2393 cmd_buffer->state.dynamic.line_width = lineWidth;
2394 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2395 }
2396
2397 void radv_CmdSetDepthBias(
2398 VkCommandBuffer commandBuffer,
2399 float depthBiasConstantFactor,
2400 float depthBiasClamp,
2401 float depthBiasSlopeFactor)
2402 {
2403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2404
2405 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2406 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2407 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2408
2409 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2410 }
2411
2412 void radv_CmdSetBlendConstants(
2413 VkCommandBuffer commandBuffer,
2414 const float blendConstants[4])
2415 {
2416 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2417
2418 memcpy(cmd_buffer->state.dynamic.blend_constants,
2419 blendConstants, sizeof(float) * 4);
2420
2421 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2422 }
2423
2424 void radv_CmdSetDepthBounds(
2425 VkCommandBuffer commandBuffer,
2426 float minDepthBounds,
2427 float maxDepthBounds)
2428 {
2429 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2430
2431 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2432 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2433
2434 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2435 }
2436
2437 void radv_CmdSetStencilCompareMask(
2438 VkCommandBuffer commandBuffer,
2439 VkStencilFaceFlags faceMask,
2440 uint32_t compareMask)
2441 {
2442 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2443
2444 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2445 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2446 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2447 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2448
2449 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2450 }
2451
2452 void radv_CmdSetStencilWriteMask(
2453 VkCommandBuffer commandBuffer,
2454 VkStencilFaceFlags faceMask,
2455 uint32_t writeMask)
2456 {
2457 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2458
2459 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2460 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2461 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2462 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2463
2464 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2465 }
2466
2467 void radv_CmdSetStencilReference(
2468 VkCommandBuffer commandBuffer,
2469 VkStencilFaceFlags faceMask,
2470 uint32_t reference)
2471 {
2472 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2473
2474 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2475 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2476 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2477 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2478
2479 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2480 }
2481
2482 void radv_CmdExecuteCommands(
2483 VkCommandBuffer commandBuffer,
2484 uint32_t commandBufferCount,
2485 const VkCommandBuffer* pCmdBuffers)
2486 {
2487 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2488
2489 /* Emit pending flushes on primary prior to executing secondary */
2490 si_emit_cache_flush(primary);
2491
2492 for (uint32_t i = 0; i < commandBufferCount; i++) {
2493 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2494
2495 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2496 secondary->scratch_size_needed);
2497 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2498 secondary->compute_scratch_size_needed);
2499
2500 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2501 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2502 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2503 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2504 if (secondary->tess_rings_needed)
2505 primary->tess_rings_needed = true;
2506 if (secondary->sample_positions_needed)
2507 primary->sample_positions_needed = true;
2508
2509 if (secondary->ring_offsets_idx != -1) {
2510 if (primary->ring_offsets_idx == -1)
2511 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2512 else
2513 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2514 }
2515 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2516 }
2517
2518 /* if we execute secondary we need to re-emit out pipelines */
2519 if (commandBufferCount) {
2520 primary->state.emitted_pipeline = NULL;
2521 primary->state.emitted_compute_pipeline = NULL;
2522 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2523 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2524 primary->state.last_primitive_reset_en = -1;
2525 primary->state.last_primitive_reset_index = 0;
2526 radv_mark_descriptor_sets_dirty(primary);
2527 }
2528 }
2529
2530 VkResult radv_CreateCommandPool(
2531 VkDevice _device,
2532 const VkCommandPoolCreateInfo* pCreateInfo,
2533 const VkAllocationCallbacks* pAllocator,
2534 VkCommandPool* pCmdPool)
2535 {
2536 RADV_FROM_HANDLE(radv_device, device, _device);
2537 struct radv_cmd_pool *pool;
2538
2539 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2540 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2541 if (pool == NULL)
2542 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2543
2544 if (pAllocator)
2545 pool->alloc = *pAllocator;
2546 else
2547 pool->alloc = device->alloc;
2548
2549 list_inithead(&pool->cmd_buffers);
2550 list_inithead(&pool->free_cmd_buffers);
2551
2552 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2553
2554 *pCmdPool = radv_cmd_pool_to_handle(pool);
2555
2556 return VK_SUCCESS;
2557
2558 }
2559
2560 void radv_DestroyCommandPool(
2561 VkDevice _device,
2562 VkCommandPool commandPool,
2563 const VkAllocationCallbacks* pAllocator)
2564 {
2565 RADV_FROM_HANDLE(radv_device, device, _device);
2566 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2567
2568 if (!pool)
2569 return;
2570
2571 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2572 &pool->cmd_buffers, pool_link) {
2573 radv_cmd_buffer_destroy(cmd_buffer);
2574 }
2575
2576 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2577 &pool->free_cmd_buffers, pool_link) {
2578 radv_cmd_buffer_destroy(cmd_buffer);
2579 }
2580
2581 vk_free2(&device->alloc, pAllocator, pool);
2582 }
2583
2584 VkResult radv_ResetCommandPool(
2585 VkDevice device,
2586 VkCommandPool commandPool,
2587 VkCommandPoolResetFlags flags)
2588 {
2589 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2590
2591 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2592 &pool->cmd_buffers, pool_link) {
2593 radv_reset_cmd_buffer(cmd_buffer);
2594 }
2595
2596 return VK_SUCCESS;
2597 }
2598
2599 void radv_TrimCommandPoolKHR(
2600 VkDevice device,
2601 VkCommandPool commandPool,
2602 VkCommandPoolTrimFlagsKHR flags)
2603 {
2604 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2605
2606 if (!pool)
2607 return;
2608
2609 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2610 &pool->free_cmd_buffers, pool_link) {
2611 radv_cmd_buffer_destroy(cmd_buffer);
2612 }
2613 }
2614
2615 void radv_CmdBeginRenderPass(
2616 VkCommandBuffer commandBuffer,
2617 const VkRenderPassBeginInfo* pRenderPassBegin,
2618 VkSubpassContents contents)
2619 {
2620 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2621 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2622 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2623
2624 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2625 cmd_buffer->cs, 2048);
2626
2627 cmd_buffer->state.framebuffer = framebuffer;
2628 cmd_buffer->state.pass = pass;
2629 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2630 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2631
2632 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2633 assert(cmd_buffer->cs->cdw <= cdw_max);
2634
2635 radv_cmd_buffer_clear_subpass(cmd_buffer);
2636 }
2637
2638 void radv_CmdNextSubpass(
2639 VkCommandBuffer commandBuffer,
2640 VkSubpassContents contents)
2641 {
2642 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2643
2644 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2645
2646 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2647 2048);
2648
2649 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2650 radv_cmd_buffer_clear_subpass(cmd_buffer);
2651 }
2652
2653 void radv_CmdDraw(
2654 VkCommandBuffer commandBuffer,
2655 uint32_t vertexCount,
2656 uint32_t instanceCount,
2657 uint32_t firstVertex,
2658 uint32_t firstInstance)
2659 {
2660 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2661
2662 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2663
2664 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2665
2666 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2667 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2668 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2669 radeon_emit(cmd_buffer->cs, firstVertex);
2670 radeon_emit(cmd_buffer->cs, firstInstance);
2671 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2672 radeon_emit(cmd_buffer->cs, 0);
2673
2674 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2675 radeon_emit(cmd_buffer->cs, instanceCount);
2676
2677 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2678 radeon_emit(cmd_buffer->cs, vertexCount);
2679 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2680 S_0287F0_USE_OPAQUE(0));
2681
2682 assert(cmd_buffer->cs->cdw <= cdw_max);
2683
2684 radv_cmd_buffer_trace_emit(cmd_buffer);
2685 }
2686
2687 void radv_CmdDrawIndexed(
2688 VkCommandBuffer commandBuffer,
2689 uint32_t indexCount,
2690 uint32_t instanceCount,
2691 uint32_t firstIndex,
2692 int32_t vertexOffset,
2693 uint32_t firstInstance)
2694 {
2695 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2696 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2697 uint64_t index_va;
2698
2699 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2700
2701 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2702
2703 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2704 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2705 2, cmd_buffer->state.index_type);
2706 } else {
2707 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2708 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2709 }
2710
2711 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2712 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2713 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2714 radeon_emit(cmd_buffer->cs, vertexOffset);
2715 radeon_emit(cmd_buffer->cs, firstInstance);
2716 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2717 radeon_emit(cmd_buffer->cs, 0);
2718
2719 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2720 radeon_emit(cmd_buffer->cs, instanceCount);
2721
2722 index_va = cmd_buffer->state.index_va;
2723 index_va += firstIndex * index_size;
2724 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2725 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2726 radeon_emit(cmd_buffer->cs, index_va);
2727 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2728 radeon_emit(cmd_buffer->cs, indexCount);
2729 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2730
2731 assert(cmd_buffer->cs->cdw <= cdw_max);
2732 radv_cmd_buffer_trace_emit(cmd_buffer);
2733 }
2734
2735 static void
2736 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2737 VkBuffer _buffer,
2738 VkDeviceSize offset,
2739 VkBuffer _count_buffer,
2740 VkDeviceSize count_offset,
2741 uint32_t draw_count,
2742 uint32_t stride,
2743 bool indexed)
2744 {
2745 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2746 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2747 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2748 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2749 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2750 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2751 indirect_va += offset + buffer->offset;
2752 uint64_t count_va = 0;
2753
2754 if (count_buffer) {
2755 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2756 count_va += count_offset + count_buffer->offset;
2757 }
2758
2759 if (!draw_count)
2760 return;
2761
2762 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2763 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2764 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2765 assert(base_reg);
2766
2767 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2768 radeon_emit(cs, 1);
2769 radeon_emit(cs, indirect_va);
2770 radeon_emit(cs, indirect_va >> 32);
2771
2772 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2773 PKT3_DRAW_INDIRECT_MULTI,
2774 8, false));
2775 radeon_emit(cs, 0);
2776 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2777 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2778 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2779 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2780 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2781 radeon_emit(cs, draw_count); /* count */
2782 radeon_emit(cs, count_va); /* count_addr */
2783 radeon_emit(cs, count_va >> 32);
2784 radeon_emit(cs, stride); /* stride */
2785 radeon_emit(cs, di_src_sel);
2786 radv_cmd_buffer_trace_emit(cmd_buffer);
2787 }
2788
2789 static void
2790 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2791 VkBuffer buffer,
2792 VkDeviceSize offset,
2793 VkBuffer countBuffer,
2794 VkDeviceSize countBufferOffset,
2795 uint32_t maxDrawCount,
2796 uint32_t stride)
2797 {
2798 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2799 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2800
2801 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2802 cmd_buffer->cs, 14);
2803
2804 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2805 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2806
2807 assert(cmd_buffer->cs->cdw <= cdw_max);
2808 }
2809
2810 static void
2811 radv_cmd_draw_indexed_indirect_count(
2812 VkCommandBuffer commandBuffer,
2813 VkBuffer buffer,
2814 VkDeviceSize offset,
2815 VkBuffer countBuffer,
2816 VkDeviceSize countBufferOffset,
2817 uint32_t maxDrawCount,
2818 uint32_t stride)
2819 {
2820 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2821 uint64_t index_va;
2822 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2823
2824 index_va = cmd_buffer->state.index_va;
2825
2826 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2827
2828 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2829 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2830
2831 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2832 radeon_emit(cmd_buffer->cs, index_va);
2833 radeon_emit(cmd_buffer->cs, index_va >> 32);
2834
2835 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2836 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2837
2838 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2839 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2840
2841 assert(cmd_buffer->cs->cdw <= cdw_max);
2842 }
2843
2844 void radv_CmdDrawIndirect(
2845 VkCommandBuffer commandBuffer,
2846 VkBuffer buffer,
2847 VkDeviceSize offset,
2848 uint32_t drawCount,
2849 uint32_t stride)
2850 {
2851 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2852 VK_NULL_HANDLE, 0, drawCount, stride);
2853 }
2854
2855 void radv_CmdDrawIndexedIndirect(
2856 VkCommandBuffer commandBuffer,
2857 VkBuffer buffer,
2858 VkDeviceSize offset,
2859 uint32_t drawCount,
2860 uint32_t stride)
2861 {
2862 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2863 VK_NULL_HANDLE, 0, drawCount, stride);
2864 }
2865
2866 void radv_CmdDrawIndirectCountAMD(
2867 VkCommandBuffer commandBuffer,
2868 VkBuffer buffer,
2869 VkDeviceSize offset,
2870 VkBuffer countBuffer,
2871 VkDeviceSize countBufferOffset,
2872 uint32_t maxDrawCount,
2873 uint32_t stride)
2874 {
2875 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2876 countBuffer, countBufferOffset,
2877 maxDrawCount, stride);
2878 }
2879
2880 void radv_CmdDrawIndexedIndirectCountAMD(
2881 VkCommandBuffer commandBuffer,
2882 VkBuffer buffer,
2883 VkDeviceSize offset,
2884 VkBuffer countBuffer,
2885 VkDeviceSize countBufferOffset,
2886 uint32_t maxDrawCount,
2887 uint32_t stride)
2888 {
2889 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2890 countBuffer, countBufferOffset,
2891 maxDrawCount, stride);
2892 }
2893
2894 static void
2895 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2896 {
2897 radv_emit_compute_pipeline(cmd_buffer);
2898 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2899 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2900 VK_SHADER_STAGE_COMPUTE_BIT);
2901 si_emit_cache_flush(cmd_buffer);
2902 }
2903
2904 void radv_CmdDispatch(
2905 VkCommandBuffer commandBuffer,
2906 uint32_t x,
2907 uint32_t y,
2908 uint32_t z)
2909 {
2910 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2911
2912 radv_flush_compute_state(cmd_buffer);
2913
2914 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2915
2916 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2917 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2918 if (loc->sgpr_idx != -1) {
2919 assert(!loc->indirect);
2920 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2921 assert(loc->num_sgprs == grid_used);
2922 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2923 radeon_emit(cmd_buffer->cs, x);
2924 if (grid_used > 1)
2925 radeon_emit(cmd_buffer->cs, y);
2926 if (grid_used > 2)
2927 radeon_emit(cmd_buffer->cs, z);
2928 }
2929
2930 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2931 PKT3_SHADER_TYPE_S(1));
2932 radeon_emit(cmd_buffer->cs, x);
2933 radeon_emit(cmd_buffer->cs, y);
2934 radeon_emit(cmd_buffer->cs, z);
2935 radeon_emit(cmd_buffer->cs, 1);
2936
2937 assert(cmd_buffer->cs->cdw <= cdw_max);
2938 radv_cmd_buffer_trace_emit(cmd_buffer);
2939 }
2940
2941 void radv_CmdDispatchIndirect(
2942 VkCommandBuffer commandBuffer,
2943 VkBuffer _buffer,
2944 VkDeviceSize offset)
2945 {
2946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2947 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2948 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2949 va += buffer->offset + offset;
2950
2951 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2952
2953 radv_flush_compute_state(cmd_buffer);
2954
2955 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2956 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2957 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2958 if (loc->sgpr_idx != -1) {
2959 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2960 for (unsigned i = 0; i < grid_used; ++i) {
2961 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2962 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2963 COPY_DATA_DST_SEL(COPY_DATA_REG));
2964 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2965 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2966 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2967 radeon_emit(cmd_buffer->cs, 0);
2968 }
2969 }
2970
2971 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2972 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2973 PKT3_SHADER_TYPE_S(1));
2974 radeon_emit(cmd_buffer->cs, va);
2975 radeon_emit(cmd_buffer->cs, va >> 32);
2976 radeon_emit(cmd_buffer->cs, 1);
2977 } else {
2978 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2979 PKT3_SHADER_TYPE_S(1));
2980 radeon_emit(cmd_buffer->cs, 1);
2981 radeon_emit(cmd_buffer->cs, va);
2982 radeon_emit(cmd_buffer->cs, va >> 32);
2983
2984 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2985 PKT3_SHADER_TYPE_S(1));
2986 radeon_emit(cmd_buffer->cs, 0);
2987 radeon_emit(cmd_buffer->cs, 1);
2988 }
2989
2990 assert(cmd_buffer->cs->cdw <= cdw_max);
2991 radv_cmd_buffer_trace_emit(cmd_buffer);
2992 }
2993
2994 void radv_unaligned_dispatch(
2995 struct radv_cmd_buffer *cmd_buffer,
2996 uint32_t x,
2997 uint32_t y,
2998 uint32_t z)
2999 {
3000 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3001 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3002 uint32_t blocks[3], remainder[3];
3003
3004 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
3005 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
3006 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
3007
3008 /* If aligned, these should be an entire block size, not 0 */
3009 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
3010 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
3011 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
3012
3013 radv_flush_compute_state(cmd_buffer);
3014
3015 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
3016
3017 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3018 radeon_emit(cmd_buffer->cs,
3019 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
3020 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3021 radeon_emit(cmd_buffer->cs,
3022 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3023 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3024 radeon_emit(cmd_buffer->cs,
3025 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3026 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3027
3028 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3029 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3030 if (loc->sgpr_idx != -1) {
3031 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3032 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3033 radeon_emit(cmd_buffer->cs, blocks[0]);
3034 if (grid_used > 1)
3035 radeon_emit(cmd_buffer->cs, blocks[1]);
3036 if (grid_used > 2)
3037 radeon_emit(cmd_buffer->cs, blocks[2]);
3038 }
3039 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3040 PKT3_SHADER_TYPE_S(1));
3041 radeon_emit(cmd_buffer->cs, blocks[0]);
3042 radeon_emit(cmd_buffer->cs, blocks[1]);
3043 radeon_emit(cmd_buffer->cs, blocks[2]);
3044 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3045 S_00B800_PARTIAL_TG_EN(1));
3046
3047 assert(cmd_buffer->cs->cdw <= cdw_max);
3048 radv_cmd_buffer_trace_emit(cmd_buffer);
3049 }
3050
3051 void radv_CmdEndRenderPass(
3052 VkCommandBuffer commandBuffer)
3053 {
3054 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3055
3056 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3057
3058 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3059
3060 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3061 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3062 radv_handle_subpass_image_transition(cmd_buffer,
3063 (VkAttachmentReference){i, layout});
3064 }
3065
3066 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3067
3068 cmd_buffer->state.pass = NULL;
3069 cmd_buffer->state.subpass = NULL;
3070 cmd_buffer->state.attachments = NULL;
3071 cmd_buffer->state.framebuffer = NULL;
3072 }
3073
3074 /*
3075 * For HTILE we have the following interesting clear words:
3076 * 0x0000030f: Uncompressed.
3077 * 0xfffffff0: Clear depth to 1.0
3078 * 0x00000000: Clear depth to 0.0
3079 */
3080 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3081 struct radv_image *image,
3082 const VkImageSubresourceRange *range,
3083 uint32_t clear_word)
3084 {
3085 assert(range->baseMipLevel == 0);
3086 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3087 unsigned layer_count = radv_get_layerCount(image, range);
3088 uint64_t size = image->surface.htile_slice_size * layer_count;
3089 uint64_t offset = image->offset + image->htile_offset +
3090 image->surface.htile_slice_size * range->baseArrayLayer;
3091
3092 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3093 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3094
3095 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3096
3097 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3098 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3099 RADV_CMD_FLAG_INV_VMEM_L1 |
3100 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3101 }
3102
3103 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3104 struct radv_image *image,
3105 VkImageLayout src_layout,
3106 VkImageLayout dst_layout,
3107 unsigned src_queue_mask,
3108 unsigned dst_queue_mask,
3109 const VkImageSubresourceRange *range,
3110 VkImageAspectFlags pending_clears)
3111 {
3112 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3113 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3114 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3115 cmd_buffer->state.render_area.extent.width == image->info.width &&
3116 cmd_buffer->state.render_area.extent.height == image->info.height) {
3117 /* The clear will initialize htile. */
3118 return;
3119 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3120 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3121 /* TODO: merge with the clear if applicable */
3122 radv_initialize_htile(cmd_buffer, image, range, 0);
3123 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3124 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3125 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3126 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3127 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3128 VkImageSubresourceRange local_range = *range;
3129 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3130 local_range.baseMipLevel = 0;
3131 local_range.levelCount = 1;
3132
3133 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3134 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3135
3136 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3137
3138 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3139 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3140 }
3141 }
3142
3143 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3144 struct radv_image *image, uint32_t value)
3145 {
3146 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3147 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3148
3149 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3150 image->cmask.size, value);
3151
3152 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3153 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3154 RADV_CMD_FLAG_INV_VMEM_L1 |
3155 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3156 }
3157
3158 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3159 struct radv_image *image,
3160 VkImageLayout src_layout,
3161 VkImageLayout dst_layout,
3162 unsigned src_queue_mask,
3163 unsigned dst_queue_mask,
3164 const VkImageSubresourceRange *range,
3165 VkImageAspectFlags pending_clears)
3166 {
3167 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3168 if (image->fmask.size)
3169 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3170 else
3171 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3172 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3173 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3174 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3175 }
3176 }
3177
3178 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3179 struct radv_image *image, uint32_t value)
3180 {
3181
3182 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3183 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3184
3185 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3186 image->surface.dcc_size, value);
3187
3188 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3189 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3190 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3191 RADV_CMD_FLAG_INV_VMEM_L1 |
3192 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3193 }
3194
3195 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3196 struct radv_image *image,
3197 VkImageLayout src_layout,
3198 VkImageLayout dst_layout,
3199 unsigned src_queue_mask,
3200 unsigned dst_queue_mask,
3201 const VkImageSubresourceRange *range,
3202 VkImageAspectFlags pending_clears)
3203 {
3204 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3205 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3206 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3207 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3208 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3209 }
3210 }
3211
3212 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3213 struct radv_image *image,
3214 VkImageLayout src_layout,
3215 VkImageLayout dst_layout,
3216 uint32_t src_family,
3217 uint32_t dst_family,
3218 const VkImageSubresourceRange *range,
3219 VkImageAspectFlags pending_clears)
3220 {
3221 if (image->exclusive && src_family != dst_family) {
3222 /* This is an acquire or a release operation and there will be
3223 * a corresponding release/acquire. Do the transition in the
3224 * most flexible queue. */
3225
3226 assert(src_family == cmd_buffer->queue_family_index ||
3227 dst_family == cmd_buffer->queue_family_index);
3228
3229 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3230 return;
3231
3232 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3233 (src_family == RADV_QUEUE_GENERAL ||
3234 dst_family == RADV_QUEUE_GENERAL))
3235 return;
3236 }
3237
3238 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3239 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3240
3241 if (image->surface.htile_size)
3242 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3243 dst_layout, src_queue_mask,
3244 dst_queue_mask, range,
3245 pending_clears);
3246
3247 if (image->cmask.size)
3248 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3249 dst_layout, src_queue_mask,
3250 dst_queue_mask, range,
3251 pending_clears);
3252
3253 if (image->surface.dcc_size)
3254 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3255 dst_layout, src_queue_mask,
3256 dst_queue_mask, range,
3257 pending_clears);
3258 }
3259
3260 void radv_CmdPipelineBarrier(
3261 VkCommandBuffer commandBuffer,
3262 VkPipelineStageFlags srcStageMask,
3263 VkPipelineStageFlags destStageMask,
3264 VkBool32 byRegion,
3265 uint32_t memoryBarrierCount,
3266 const VkMemoryBarrier* pMemoryBarriers,
3267 uint32_t bufferMemoryBarrierCount,
3268 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3269 uint32_t imageMemoryBarrierCount,
3270 const VkImageMemoryBarrier* pImageMemoryBarriers)
3271 {
3272 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3273 enum radv_cmd_flush_bits src_flush_bits = 0;
3274 enum radv_cmd_flush_bits dst_flush_bits = 0;
3275
3276 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3277 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3278 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3279 NULL);
3280 }
3281
3282 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3283 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3284 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3285 NULL);
3286 }
3287
3288 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3289 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3290 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3291 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3292 image);
3293 }
3294
3295 radv_stage_flush(cmd_buffer, srcStageMask);
3296 cmd_buffer->state.flush_bits |= src_flush_bits;
3297
3298 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3299 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3300 radv_handle_image_transition(cmd_buffer, image,
3301 pImageMemoryBarriers[i].oldLayout,
3302 pImageMemoryBarriers[i].newLayout,
3303 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3304 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3305 &pImageMemoryBarriers[i].subresourceRange,
3306 0);
3307 }
3308
3309 cmd_buffer->state.flush_bits |= dst_flush_bits;
3310 }
3311
3312
3313 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3314 struct radv_event *event,
3315 VkPipelineStageFlags stageMask,
3316 unsigned value)
3317 {
3318 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3319 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3320
3321 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3322
3323 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3324
3325 /* TODO: this is overkill. Probably should figure something out from
3326 * the stage mask. */
3327
3328 si_cs_emit_write_event_eop(cs,
3329 cmd_buffer->state.predicating,
3330 cmd_buffer->device->physical_device->rad_info.chip_class,
3331 false,
3332 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3333 1, va, 2, value);
3334
3335 assert(cmd_buffer->cs->cdw <= cdw_max);
3336 }
3337
3338 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3339 VkEvent _event,
3340 VkPipelineStageFlags stageMask)
3341 {
3342 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3343 RADV_FROM_HANDLE(radv_event, event, _event);
3344
3345 write_event(cmd_buffer, event, stageMask, 1);
3346 }
3347
3348 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3349 VkEvent _event,
3350 VkPipelineStageFlags stageMask)
3351 {
3352 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3353 RADV_FROM_HANDLE(radv_event, event, _event);
3354
3355 write_event(cmd_buffer, event, stageMask, 0);
3356 }
3357
3358 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3359 uint32_t eventCount,
3360 const VkEvent* pEvents,
3361 VkPipelineStageFlags srcStageMask,
3362 VkPipelineStageFlags dstStageMask,
3363 uint32_t memoryBarrierCount,
3364 const VkMemoryBarrier* pMemoryBarriers,
3365 uint32_t bufferMemoryBarrierCount,
3366 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3367 uint32_t imageMemoryBarrierCount,
3368 const VkImageMemoryBarrier* pImageMemoryBarriers)
3369 {
3370 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3371 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3372
3373 for (unsigned i = 0; i < eventCount; ++i) {
3374 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3375 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3376
3377 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3378
3379 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3380
3381 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3382 assert(cmd_buffer->cs->cdw <= cdw_max);
3383 }
3384
3385
3386 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3387 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3388
3389 radv_handle_image_transition(cmd_buffer, image,
3390 pImageMemoryBarriers[i].oldLayout,
3391 pImageMemoryBarriers[i].newLayout,
3392 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3393 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3394 &pImageMemoryBarriers[i].subresourceRange,
3395 0);
3396 }
3397
3398 /* TODO: figure out how to do memory barriers without waiting */
3399 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3400 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3401 RADV_CMD_FLAG_INV_VMEM_L1 |
3402 RADV_CMD_FLAG_INV_SMEM_L1;
3403 }