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radv: Prepare for not using the guard band for lines & points.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
206 }
207
208 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
209 {
210
211 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
212
213 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
214 &cmd_buffer->upload.list, list) {
215 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
216 list_del(&up->list);
217 free(up);
218 }
219
220 cmd_buffer->scratch_size_needed = 0;
221 cmd_buffer->compute_scratch_size_needed = 0;
222 cmd_buffer->esgs_ring_size_needed = 0;
223 cmd_buffer->gsvs_ring_size_needed = 0;
224
225 if (cmd_buffer->upload.upload_bo)
226 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
227 cmd_buffer->upload.upload_bo, 8);
228 cmd_buffer->upload.offset = 0;
229
230 cmd_buffer->record_fail = false;
231
232 cmd_buffer->ring_offsets_idx = -1;
233 }
234
235 static bool
236 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
237 uint64_t min_needed)
238 {
239 uint64_t new_size;
240 struct radeon_winsys_bo *bo;
241 struct radv_cmd_buffer_upload *upload;
242 struct radv_device *device = cmd_buffer->device;
243
244 new_size = MAX2(min_needed, 16 * 1024);
245 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
246
247 bo = device->ws->buffer_create(device->ws,
248 new_size, 4096,
249 RADEON_DOMAIN_GTT,
250 RADEON_FLAG_CPU_ACCESS);
251
252 if (!bo) {
253 cmd_buffer->record_fail = true;
254 return false;
255 }
256
257 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
258 if (cmd_buffer->upload.upload_bo) {
259 upload = malloc(sizeof(*upload));
260
261 if (!upload) {
262 cmd_buffer->record_fail = true;
263 device->ws->buffer_destroy(bo);
264 return false;
265 }
266
267 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
268 list_add(&upload->list, &cmd_buffer->upload.list);
269 }
270
271 cmd_buffer->upload.upload_bo = bo;
272 cmd_buffer->upload.size = new_size;
273 cmd_buffer->upload.offset = 0;
274 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
275
276 if (!cmd_buffer->upload.map) {
277 cmd_buffer->record_fail = true;
278 return false;
279 }
280
281 return true;
282 }
283
284 bool
285 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
286 unsigned size,
287 unsigned alignment,
288 unsigned *out_offset,
289 void **ptr)
290 {
291 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
292 if (offset + size > cmd_buffer->upload.size) {
293 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
294 return false;
295 offset = 0;
296 }
297
298 *out_offset = offset;
299 *ptr = cmd_buffer->upload.map + offset;
300
301 cmd_buffer->upload.offset = offset + size;
302 return true;
303 }
304
305 bool
306 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
307 unsigned size, unsigned alignment,
308 const void *data, unsigned *out_offset)
309 {
310 uint8_t *ptr;
311
312 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
313 out_offset, (void **)&ptr))
314 return false;
315
316 if (ptr)
317 memcpy(ptr, data, size);
318
319 return true;
320 }
321
322 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
323 {
324 struct radv_device *device = cmd_buffer->device;
325 struct radeon_winsys_cs *cs = cmd_buffer->cs;
326 uint64_t va;
327
328 if (!device->trace_bo)
329 return;
330
331 va = device->ws->buffer_get_va(device->trace_bo);
332
333 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
334
335 ++cmd_buffer->state.trace_id;
336 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
337 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
338 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
339 S_370_WR_CONFIRM(1) |
340 S_370_ENGINE_SEL(V_370_ME));
341 radeon_emit(cs, va);
342 radeon_emit(cs, va >> 32);
343 radeon_emit(cs, cmd_buffer->state.trace_id);
344 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
345 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
346 }
347
348 static void
349 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
350 struct radv_pipeline *pipeline)
351 {
352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
353 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
354 8);
355 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
356 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
357 }
358
359 static void
360 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
361 struct radv_pipeline *pipeline)
362 {
363 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
364 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
365 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
366
367 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
369 }
370
371 /* 12.4 fixed-point */
372 static unsigned radv_pack_float_12p4(float x)
373 {
374 return x <= 0 ? 0 :
375 x >= 4096 ? 0xffff : x * 16;
376 }
377
378 static uint32_t
379 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs)
380 {
381 switch (stage) {
382 case MESA_SHADER_FRAGMENT:
383 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
384 case MESA_SHADER_VERTEX:
385 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
386 case MESA_SHADER_GEOMETRY:
387 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
388 case MESA_SHADER_COMPUTE:
389 return R_00B900_COMPUTE_USER_DATA_0;
390 default:
391 unreachable("unknown shader");
392 }
393 }
394
395 static struct ac_userdata_info *
396 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
397 gl_shader_stage stage,
398 int idx)
399 {
400 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
401 }
402
403 static void
404 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
405 struct radv_pipeline *pipeline,
406 gl_shader_stage stage,
407 int idx, uint64_t va)
408 {
409 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
410 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
411 if (loc->sgpr_idx == -1)
412 return;
413 assert(loc->num_sgprs == 2);
414 assert(!loc->indirect);
415 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
416 radeon_emit(cmd_buffer->cs, va);
417 radeon_emit(cmd_buffer->cs, va >> 32);
418 }
419
420 static void
421 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
422 struct radv_pipeline *pipeline)
423 {
424 int num_samples = pipeline->graphics.ms.num_samples;
425 struct radv_multisample_state *ms = &pipeline->graphics.ms;
426 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
427
428 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
429 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
430 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
431
432 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
433 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
434
435 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
436 return;
437
438 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
439 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
440 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
441
442 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
443
444 uint32_t samples_offset;
445 void *samples_ptr;
446 void *src;
447 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
448 &samples_ptr);
449 switch (num_samples) {
450 case 1:
451 src = cmd_buffer->device->sample_locations_1x;
452 break;
453 case 2:
454 src = cmd_buffer->device->sample_locations_2x;
455 break;
456 case 4:
457 src = cmd_buffer->device->sample_locations_4x;
458 break;
459 case 8:
460 src = cmd_buffer->device->sample_locations_8x;
461 break;
462 case 16:
463 src = cmd_buffer->device->sample_locations_16x;
464 break;
465 default:
466 unreachable("unknown number of samples");
467 }
468 memcpy(samples_ptr, src, num_samples * 4 * 2);
469
470 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
471 va += samples_offset;
472
473 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
474 AC_UD_PS_SAMPLE_POS, va);
475 }
476
477 static void
478 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
479 struct radv_pipeline *pipeline)
480 {
481 struct radv_raster_state *raster = &pipeline->graphics.raster;
482
483 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
484 raster->pa_cl_clip_cntl);
485
486 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
487 raster->spi_interp_control);
488
489 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
490 unsigned tmp = (unsigned)(1.0 * 8.0);
491 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
492 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
493 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
494
495 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
496 raster->pa_su_vtx_cntl);
497
498 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
499 raster->pa_su_sc_mode_cntl);
500 }
501
502 static void
503 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
504 struct radv_pipeline *pipeline,
505 struct radv_shader_variant *shader,
506 struct ac_vs_output_info *outinfo)
507 {
508 struct radeon_winsys *ws = cmd_buffer->device->ws;
509 uint64_t va = ws->buffer_get_va(shader->bo);
510 unsigned export_count;
511
512 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
513
514 export_count = MAX2(1, outinfo->param_exports);
515 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
516 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
517
518 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
519 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
520 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
521 V_02870C_SPI_SHADER_4COMP :
522 V_02870C_SPI_SHADER_NONE) |
523 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
524 V_02870C_SPI_SHADER_4COMP :
525 V_02870C_SPI_SHADER_NONE) |
526 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
527 V_02870C_SPI_SHADER_4COMP :
528 V_02870C_SPI_SHADER_NONE));
529
530
531 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
532 radeon_emit(cmd_buffer->cs, va >> 8);
533 radeon_emit(cmd_buffer->cs, va >> 40);
534 radeon_emit(cmd_buffer->cs, shader->rsrc1);
535 radeon_emit(cmd_buffer->cs, shader->rsrc2);
536
537 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
538 S_028818_VTX_W0_FMT(1) |
539 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
540 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
541 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
542
543
544 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
545 pipeline->graphics.pa_cl_vs_out_cntl);
546
547 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
548 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
549 }
550
551 static void
552 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
553 struct radv_shader_variant *shader,
554 struct ac_es_output_info *outinfo)
555 {
556 struct radeon_winsys *ws = cmd_buffer->device->ws;
557 uint64_t va = ws->buffer_get_va(shader->bo);
558
559 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
560
561 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
562 outinfo->esgs_itemsize / 4);
563 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
564 radeon_emit(cmd_buffer->cs, va >> 8);
565 radeon_emit(cmd_buffer->cs, va >> 40);
566 radeon_emit(cmd_buffer->cs, shader->rsrc1);
567 radeon_emit(cmd_buffer->cs, shader->rsrc2);
568 }
569
570 static void
571 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline)
573 {
574 struct radv_shader_variant *vs;
575
576 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
577
578 vs = pipeline->shaders[MESA_SHADER_VERTEX];
579
580 if (vs->info.vs.as_es)
581 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
582 else
583 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
584
585 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
586 }
587
588
589 static void
590 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
591 struct radv_pipeline *pipeline)
592 {
593 struct radeon_winsys *ws = cmd_buffer->device->ws;
594 struct radv_shader_variant *gs;
595 uint64_t va;
596
597 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
598
599 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
600 if (!gs)
601 return;
602
603 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
604
605 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
606 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
607 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
608 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
609
610 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
611
612 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
613
614 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
615 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
616 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
617 radeon_emit(cmd_buffer->cs, 0);
618 radeon_emit(cmd_buffer->cs, 0);
619 radeon_emit(cmd_buffer->cs, 0);
620
621 uint32_t gs_num_invocations = gs->info.gs.invocations;
622 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
623 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
624 S_028B90_ENABLE(gs_num_invocations > 0));
625
626 va = ws->buffer_get_va(gs->bo);
627 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
628 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
629 radeon_emit(cmd_buffer->cs, va >> 8);
630 radeon_emit(cmd_buffer->cs, va >> 40);
631 radeon_emit(cmd_buffer->cs, gs->rsrc1);
632 radeon_emit(cmd_buffer->cs, gs->rsrc2);
633
634 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
635
636 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
637 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
638 if (loc->sgpr_idx != -1) {
639 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
640 uint32_t num_entries = 64;
641 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
642
643 if (is_vi)
644 num_entries *= stride;
645
646 stride = S_008F04_STRIDE(stride);
647 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
648 radeon_emit(cmd_buffer->cs, stride);
649 radeon_emit(cmd_buffer->cs, num_entries);
650 }
651 }
652
653 static void
654 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
655 struct radv_pipeline *pipeline)
656 {
657 struct radeon_winsys *ws = cmd_buffer->device->ws;
658 struct radv_shader_variant *ps;
659 uint64_t va;
660 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
661 struct radv_blend_state *blend = &pipeline->graphics.blend;
662 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
663
664 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
665
666 va = ws->buffer_get_va(ps->bo);
667 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
668
669 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
670 radeon_emit(cmd_buffer->cs, va >> 8);
671 radeon_emit(cmd_buffer->cs, va >> 40);
672 radeon_emit(cmd_buffer->cs, ps->rsrc1);
673 radeon_emit(cmd_buffer->cs, ps->rsrc2);
674
675 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
676 pipeline->graphics.db_shader_control);
677
678 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
679 ps->config.spi_ps_input_ena);
680
681 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
682 ps->config.spi_ps_input_addr);
683
684 if (ps->info.fs.force_persample)
685 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
686
687 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
688 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
689
690 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
691
692 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
693 pipeline->graphics.shader_z_format);
694
695 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
696
697 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
698 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
699
700 if (pipeline->graphics.ps_input_cntl_num) {
701 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
702 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
703 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
704 }
705 }
706 }
707
708 static void
709 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
710 struct radv_pipeline *pipeline)
711 {
712 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
713 return;
714
715 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
716 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
717 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
718 radv_update_multisample_state(cmd_buffer, pipeline);
719 radv_emit_vertex_shader(cmd_buffer, pipeline);
720 radv_emit_geometry_shader(cmd_buffer, pipeline);
721 radv_emit_fragment_shader(cmd_buffer, pipeline);
722
723 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
724 pipeline->graphics.prim_restart_enable);
725
726 cmd_buffer->scratch_size_needed =
727 MAX2(cmd_buffer->scratch_size_needed,
728 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
731 S_0286E8_WAVES(pipeline->max_waves) |
732 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
733
734 if (!cmd_buffer->state.emitted_pipeline ||
735 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
736 pipeline->graphics.can_use_guardband)
737 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
738 cmd_buffer->state.emitted_pipeline = pipeline;
739 }
740
741 static void
742 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
743 {
744 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
745 cmd_buffer->state.dynamic.viewport.viewports);
746 }
747
748 static void
749 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
750 {
751 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
752 si_write_scissors(cmd_buffer->cs, 0, count,
753 cmd_buffer->state.dynamic.scissor.scissors);
754 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
755 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
756 }
757
758 static void
759 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
760 int index,
761 struct radv_color_buffer_info *cb)
762 {
763 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
764 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
765 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
766 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
767 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
768 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
769 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
770 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
771 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
772 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
773 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
774 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
775 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
776
777 if (is_vi) { /* DCC BASE */
778 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
779 }
780 }
781
782 static void
783 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
784 struct radv_ds_buffer_info *ds,
785 struct radv_image *image,
786 VkImageLayout layout)
787 {
788 uint32_t db_z_info = ds->db_z_info;
789
790 if (!radv_layout_has_htile(image, layout))
791 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
792
793 if (!radv_layout_can_expclear(image, layout))
794 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
795
796 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
797 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
798
799 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
800 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
801 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
802 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
803 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
804 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
805 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
806 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
807 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
808 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
809
810 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
811 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
812 ds->pa_su_poly_offset_db_fmt_cntl);
813 }
814
815 /*
816 * To hw resolve multisample images both src and dst need to have the same
817 * micro tiling mode. However we don't always know in advance when creating
818 * the images. This function gets called if we have a resolve attachment,
819 * and tests if the attachment image has the same tiling mode, then it
820 * checks if the generated framebuffer data has the same tiling mode, and
821 * updates it if not.
822 */
823 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
824 struct radv_attachment_info *att,
825 uint32_t micro_tile_mode)
826 {
827 struct radv_image *image = att->attachment->image;
828 uint32_t tile_mode_index;
829 if (image->surface.nsamples <= 1)
830 return;
831
832 if (image->surface.micro_tile_mode != micro_tile_mode) {
833 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
834 }
835
836 if (att->cb.micro_tile_mode != micro_tile_mode) {
837 tile_mode_index = image->surface.tiling_index[0];
838
839 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
840 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
841 att->cb.micro_tile_mode = micro_tile_mode;
842 }
843 }
844
845 void
846 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
847 struct radv_image *image,
848 VkClearDepthStencilValue ds_clear_value,
849 VkImageAspectFlags aspects)
850 {
851 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
852 va += image->offset + image->clear_value_offset;
853 unsigned reg_offset = 0, reg_count = 0;
854
855 if (!image->surface.htile_size || !aspects)
856 return;
857
858 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
859 ++reg_count;
860 } else {
861 ++reg_offset;
862 va += 4;
863 }
864 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
865 ++reg_count;
866
867 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
868
869 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
870 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
871 S_370_WR_CONFIRM(1) |
872 S_370_ENGINE_SEL(V_370_PFP));
873 radeon_emit(cmd_buffer->cs, va);
874 radeon_emit(cmd_buffer->cs, va >> 32);
875 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
876 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
877 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
878 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
879
880 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
881 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
882 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
883 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
884 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
885 }
886
887 static void
888 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_image *image)
890 {
891 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
892 va += image->offset + image->clear_value_offset;
893
894 if (!image->surface.htile_size)
895 return;
896
897 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
898
899 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
900 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
901 COPY_DATA_DST_SEL(COPY_DATA_REG) |
902 COPY_DATA_COUNT_SEL);
903 radeon_emit(cmd_buffer->cs, va);
904 radeon_emit(cmd_buffer->cs, va >> 32);
905 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
906 radeon_emit(cmd_buffer->cs, 0);
907
908 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
909 radeon_emit(cmd_buffer->cs, 0);
910 }
911
912 void
913 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
914 struct radv_image *image,
915 int idx,
916 uint32_t color_values[2])
917 {
918 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
919 va += image->offset + image->clear_value_offset;
920
921 if (!image->cmask.size && !image->surface.dcc_size)
922 return;
923
924 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
925
926 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
927 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
928 S_370_WR_CONFIRM(1) |
929 S_370_ENGINE_SEL(V_370_PFP));
930 radeon_emit(cmd_buffer->cs, va);
931 radeon_emit(cmd_buffer->cs, va >> 32);
932 radeon_emit(cmd_buffer->cs, color_values[0]);
933 radeon_emit(cmd_buffer->cs, color_values[1]);
934
935 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
936 radeon_emit(cmd_buffer->cs, color_values[0]);
937 radeon_emit(cmd_buffer->cs, color_values[1]);
938 }
939
940 static void
941 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
942 struct radv_image *image,
943 int idx)
944 {
945 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
946 va += image->offset + image->clear_value_offset;
947
948 if (!image->cmask.size && !image->surface.dcc_size)
949 return;
950
951 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
952 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
953
954 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
955 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
956 COPY_DATA_DST_SEL(COPY_DATA_REG) |
957 COPY_DATA_COUNT_SEL);
958 radeon_emit(cmd_buffer->cs, va);
959 radeon_emit(cmd_buffer->cs, va >> 32);
960 radeon_emit(cmd_buffer->cs, reg >> 2);
961 radeon_emit(cmd_buffer->cs, 0);
962
963 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
964 radeon_emit(cmd_buffer->cs, 0);
965 }
966
967 void
968 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
969 {
970 int i;
971 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
972 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
973 int dst_resolve_micro_tile_mode = -1;
974
975 if (subpass->has_resolve) {
976 uint32_t a = subpass->resolve_attachments[0].attachment;
977 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
978 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
979 }
980 for (i = 0; i < subpass->color_count; ++i) {
981 int idx = subpass->color_attachments[i].attachment;
982 struct radv_attachment_info *att = &framebuffer->attachments[idx];
983
984 if (dst_resolve_micro_tile_mode != -1) {
985 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
986 att, dst_resolve_micro_tile_mode);
987 }
988 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
989
990 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
991 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
992
993 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
994 }
995
996 for (i = subpass->color_count; i < 8; i++)
997 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
998 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
999
1000 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1001 int idx = subpass->depth_stencil_attachment.attachment;
1002 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1003 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1004 struct radv_image *image = att->attachment->image;
1005 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1006
1007 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1008
1009 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1010 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1011 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1012 }
1013 radv_load_depth_clear_regs(cmd_buffer, image);
1014 } else {
1015 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1016 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1017 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1018 }
1019 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1020 S_028208_BR_X(framebuffer->width) |
1021 S_028208_BR_Y(framebuffer->height));
1022 }
1023
1024 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1025 {
1026 uint32_t db_count_control;
1027
1028 if(!cmd_buffer->state.active_occlusion_queries) {
1029 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1030 db_count_control = 0;
1031 } else {
1032 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1033 }
1034 } else {
1035 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1036 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1037 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1038 S_028004_ZPASS_ENABLE(1) |
1039 S_028004_SLICE_EVEN_ENABLE(1) |
1040 S_028004_SLICE_ODD_ENABLE(1);
1041 } else {
1042 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1043 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1044 }
1045 }
1046
1047 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1048 }
1049
1050 static void
1051 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1052 {
1053 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1054
1055 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1056 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1057 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1058 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1059 }
1060
1061 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1062 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1063 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1064 }
1065
1066 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1067 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1068 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1069 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1070 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1071 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1072 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1073 S_028430_STENCILOPVAL(1));
1074 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1075 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1076 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1077 S_028434_STENCILOPVAL_BF(1));
1078 }
1079
1080 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1081 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1082 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1083 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1084 }
1085
1086 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1087 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1088 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1089 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1090 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1091
1092 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1093 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1094 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1095 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1096 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1097 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1098 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1099 }
1100 }
1101
1102 cmd_buffer->state.dirty = 0;
1103 }
1104
1105 static void
1106 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1107 struct radv_pipeline *pipeline,
1108 int idx,
1109 uint64_t va,
1110 gl_shader_stage stage)
1111 {
1112 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1113 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
1114
1115 if (desc_set_loc->sgpr_idx == -1)
1116 return;
1117
1118 assert(!desc_set_loc->indirect);
1119 assert(desc_set_loc->num_sgprs == 2);
1120 radeon_set_sh_reg_seq(cmd_buffer->cs,
1121 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1122 radeon_emit(cmd_buffer->cs, va);
1123 radeon_emit(cmd_buffer->cs, va >> 32);
1124 }
1125
1126 static void
1127 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1128 struct radv_pipeline *pipeline,
1129 VkShaderStageFlags stages,
1130 struct radv_descriptor_set *set,
1131 unsigned idx)
1132 {
1133 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1134 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1135 idx, set->va,
1136 MESA_SHADER_FRAGMENT);
1137
1138 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1139 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1140 idx, set->va,
1141 MESA_SHADER_VERTEX);
1142
1143 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1144 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1145 idx, set->va,
1146 MESA_SHADER_GEOMETRY);
1147
1148 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1149 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1150 idx, set->va,
1151 MESA_SHADER_COMPUTE);
1152 }
1153
1154 static void
1155 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1156 struct radv_pipeline *pipeline,
1157 VkShaderStageFlags stages)
1158 {
1159 unsigned i;
1160 if (!cmd_buffer->state.descriptors_dirty)
1161 return;
1162
1163 for (i = 0; i < MAX_SETS; i++) {
1164 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1165 continue;
1166 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1167 if (!set)
1168 continue;
1169
1170 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1171 }
1172 cmd_buffer->state.descriptors_dirty = 0;
1173 }
1174
1175 static void
1176 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1177 struct radv_pipeline *pipeline,
1178 VkShaderStageFlags stages)
1179 {
1180 struct radv_pipeline_layout *layout = pipeline->layout;
1181 unsigned offset;
1182 void *ptr;
1183 uint64_t va;
1184
1185 stages &= cmd_buffer->push_constant_stages;
1186 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1187 return;
1188
1189 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1190 16 * layout->dynamic_offset_count,
1191 256, &offset, &ptr))
1192 return;
1193
1194 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1195 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1196 16 * layout->dynamic_offset_count);
1197
1198 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1199 va += offset;
1200
1201 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1202 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1203 AC_UD_PUSH_CONSTANTS, va);
1204
1205 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1206 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1207 AC_UD_PUSH_CONSTANTS, va);
1208
1209 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1210 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1211 AC_UD_PUSH_CONSTANTS, va);
1212
1213 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1214 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1215 AC_UD_PUSH_CONSTANTS, va);
1216
1217 cmd_buffer->push_constant_stages &= ~stages;
1218 }
1219
1220 static void
1221 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1222 bool instanced_draw, bool indirect_draw,
1223 uint32_t draw_vertex_count)
1224 {
1225 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1226 struct radv_device *device = cmd_buffer->device;
1227 uint32_t ia_multi_vgt_param;
1228 uint32_t ls_hs_config = 0;
1229
1230 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1231 cmd_buffer->cs, 4096);
1232
1233 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1234 cmd_buffer->state.pipeline->num_vertex_attribs) {
1235 unsigned vb_offset;
1236 void *vb_ptr;
1237 uint32_t i = 0;
1238 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1239 uint64_t va;
1240
1241 /* allocate some descriptor state for vertex buffers */
1242 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1243 &vb_offset, &vb_ptr);
1244
1245 for (i = 0; i < num_attribs; i++) {
1246 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1247 uint32_t offset;
1248 int vb = cmd_buffer->state.pipeline->va_binding[i];
1249 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1250 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1251
1252 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1253 va = device->ws->buffer_get_va(buffer->bo);
1254
1255 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1256 va += offset + buffer->offset;
1257 desc[0] = va;
1258 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1259 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1260 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1261 else
1262 desc[2] = buffer->size - offset;
1263 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1264 }
1265
1266 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1267 va += vb_offset;
1268
1269 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1270 AC_UD_VS_VERTEX_BUFFERS, va);
1271 }
1272
1273 cmd_buffer->state.vertex_descriptors_dirty = false;
1274 cmd_buffer->state.vb_dirty = 0;
1275 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1276 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1277
1278 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1279 radv_emit_framebuffer_state(cmd_buffer);
1280
1281 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1282 radv_emit_viewport(cmd_buffer);
1283
1284 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1285 radv_emit_scissor(cmd_buffer);
1286
1287 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1288 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1289 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1290 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1291 else
1292 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1293 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1294 }
1295
1296 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1297 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1298
1299 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1300 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1301 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1302 } else {
1303 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1304 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1305 }
1306 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1307 }
1308
1309 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1310
1311 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1312 VK_SHADER_STAGE_ALL_GRAPHICS);
1313 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1314 VK_SHADER_STAGE_ALL_GRAPHICS);
1315
1316 assert(cmd_buffer->cs->cdw <= cdw_max);
1317
1318 si_emit_cache_flush(cmd_buffer);
1319 }
1320
1321 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1322 VkPipelineStageFlags src_stage_mask)
1323 {
1324 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1325 VK_PIPELINE_STAGE_TRANSFER_BIT |
1326 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1327 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1328 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1329 }
1330
1331 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1332 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1333 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1334 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1335 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1336 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1337 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1338 VK_PIPELINE_STAGE_TRANSFER_BIT |
1339 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1340 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1341 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1342 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1343 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1344 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1345 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1346 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1347 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1348 }
1349 }
1350
1351 static enum radv_cmd_flush_bits
1352 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1353 VkAccessFlags src_flags)
1354 {
1355 enum radv_cmd_flush_bits flush_bits = 0;
1356 uint32_t b;
1357 for_each_bit(b, src_flags) {
1358 switch ((VkAccessFlagBits)(1 << b)) {
1359 case VK_ACCESS_SHADER_WRITE_BIT:
1360 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1361 break;
1362 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1363 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1364 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1365 break;
1366 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1367 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1368 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1369 break;
1370 case VK_ACCESS_TRANSFER_WRITE_BIT:
1371 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1372 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1373 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1374 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1375 RADV_CMD_FLAG_INV_GLOBAL_L2;
1376 break;
1377 default:
1378 break;
1379 }
1380 }
1381 return flush_bits;
1382 }
1383
1384 static enum radv_cmd_flush_bits
1385 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1386 VkAccessFlags dst_flags,
1387 struct radv_image *image)
1388 {
1389 enum radv_cmd_flush_bits flush_bits = 0;
1390 uint32_t b;
1391 for_each_bit(b, dst_flags) {
1392 switch ((VkAccessFlagBits)(1 << b)) {
1393 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1394 case VK_ACCESS_INDEX_READ_BIT:
1395 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1396 break;
1397 case VK_ACCESS_UNIFORM_READ_BIT:
1398 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1399 break;
1400 case VK_ACCESS_SHADER_READ_BIT:
1401 case VK_ACCESS_TRANSFER_READ_BIT:
1402 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1403 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1404 RADV_CMD_FLAG_INV_GLOBAL_L2;
1405 break;
1406 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1407 /* TODO: change to image && when the image gets passed
1408 * through from the subpass. */
1409 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1410 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1411 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1412 break;
1413 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1414 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1415 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1416 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1417 break;
1418 default:
1419 break;
1420 }
1421 }
1422 return flush_bits;
1423 }
1424
1425 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1426 {
1427 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1428 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1429 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1430 NULL);
1431 }
1432
1433 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1434 VkAttachmentReference att)
1435 {
1436 unsigned idx = att.attachment;
1437 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1438 VkImageSubresourceRange range;
1439 range.aspectMask = 0;
1440 range.baseMipLevel = view->base_mip;
1441 range.levelCount = 1;
1442 range.baseArrayLayer = view->base_layer;
1443 range.layerCount = cmd_buffer->state.framebuffer->layers;
1444
1445 radv_handle_image_transition(cmd_buffer,
1446 view->image,
1447 cmd_buffer->state.attachments[idx].current_layout,
1448 att.layout, 0, 0, &range,
1449 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1450
1451 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1452
1453
1454 }
1455
1456 void
1457 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1458 const struct radv_subpass *subpass, bool transitions)
1459 {
1460 if (transitions) {
1461 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1462
1463 for (unsigned i = 0; i < subpass->color_count; ++i) {
1464 radv_handle_subpass_image_transition(cmd_buffer,
1465 subpass->color_attachments[i]);
1466 }
1467
1468 for (unsigned i = 0; i < subpass->input_count; ++i) {
1469 radv_handle_subpass_image_transition(cmd_buffer,
1470 subpass->input_attachments[i]);
1471 }
1472
1473 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1474 radv_handle_subpass_image_transition(cmd_buffer,
1475 subpass->depth_stencil_attachment);
1476 }
1477 }
1478
1479 cmd_buffer->state.subpass = subpass;
1480
1481 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1482 }
1483
1484 static void
1485 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1486 struct radv_render_pass *pass,
1487 const VkRenderPassBeginInfo *info)
1488 {
1489 struct radv_cmd_state *state = &cmd_buffer->state;
1490
1491 if (pass->attachment_count == 0) {
1492 state->attachments = NULL;
1493 return;
1494 }
1495
1496 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1497 pass->attachment_count *
1498 sizeof(state->attachments[0]),
1499 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1500 if (state->attachments == NULL) {
1501 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1502 abort();
1503 }
1504
1505 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1506 struct radv_render_pass_attachment *att = &pass->attachments[i];
1507 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1508 VkImageAspectFlags clear_aspects = 0;
1509
1510 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1511 /* color attachment */
1512 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1513 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1514 }
1515 } else {
1516 /* depthstencil attachment */
1517 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1518 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1519 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1520 }
1521 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1522 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1523 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1524 }
1525 }
1526
1527 state->attachments[i].pending_clear_aspects = clear_aspects;
1528 if (clear_aspects && info) {
1529 assert(info->clearValueCount > i);
1530 state->attachments[i].clear_value = info->pClearValues[i];
1531 }
1532
1533 state->attachments[i].current_layout = att->initial_layout;
1534 }
1535 }
1536
1537 VkResult radv_AllocateCommandBuffers(
1538 VkDevice _device,
1539 const VkCommandBufferAllocateInfo *pAllocateInfo,
1540 VkCommandBuffer *pCommandBuffers)
1541 {
1542 RADV_FROM_HANDLE(radv_device, device, _device);
1543 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1544
1545 VkResult result = VK_SUCCESS;
1546 uint32_t i;
1547
1548 memset(pCommandBuffers, 0,
1549 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1550
1551 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1552
1553 if (!list_empty(&pool->free_cmd_buffers)) {
1554 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1555
1556 list_del(&cmd_buffer->pool_link);
1557 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1558
1559 radv_reset_cmd_buffer(cmd_buffer);
1560 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1561 cmd_buffer->level = pAllocateInfo->level;
1562
1563 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1564 result = VK_SUCCESS;
1565 } else {
1566 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1567 &pCommandBuffers[i]);
1568 }
1569 if (result != VK_SUCCESS)
1570 break;
1571 }
1572
1573 if (result != VK_SUCCESS)
1574 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1575 i, pCommandBuffers);
1576
1577 return result;
1578 }
1579
1580 void radv_FreeCommandBuffers(
1581 VkDevice device,
1582 VkCommandPool commandPool,
1583 uint32_t commandBufferCount,
1584 const VkCommandBuffer *pCommandBuffers)
1585 {
1586 for (uint32_t i = 0; i < commandBufferCount; i++) {
1587 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1588
1589 if (cmd_buffer) {
1590 if (cmd_buffer->pool) {
1591 list_del(&cmd_buffer->pool_link);
1592 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1593 } else
1594 radv_cmd_buffer_destroy(cmd_buffer);
1595
1596 }
1597 }
1598 }
1599
1600 VkResult radv_ResetCommandBuffer(
1601 VkCommandBuffer commandBuffer,
1602 VkCommandBufferResetFlags flags)
1603 {
1604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1605 radv_reset_cmd_buffer(cmd_buffer);
1606 return VK_SUCCESS;
1607 }
1608
1609 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1610 {
1611 struct radv_device *device = cmd_buffer->device;
1612 if (device->gfx_init) {
1613 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1614 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1615 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1616 radeon_emit(cmd_buffer->cs, va);
1617 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1618 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1619 } else
1620 si_init_config(cmd_buffer);
1621 }
1622
1623 VkResult radv_BeginCommandBuffer(
1624 VkCommandBuffer commandBuffer,
1625 const VkCommandBufferBeginInfo *pBeginInfo)
1626 {
1627 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1628 radv_reset_cmd_buffer(cmd_buffer);
1629
1630 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1631
1632 /* setup initial configuration into command buffer */
1633 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1634 switch (cmd_buffer->queue_family_index) {
1635 case RADV_QUEUE_GENERAL:
1636 emit_gfx_buffer_state(cmd_buffer);
1637 radv_set_db_count_control(cmd_buffer);
1638 break;
1639 case RADV_QUEUE_COMPUTE:
1640 si_init_compute(cmd_buffer);
1641 break;
1642 case RADV_QUEUE_TRANSFER:
1643 default:
1644 break;
1645 }
1646 }
1647
1648 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1649 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1650 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1651
1652 struct radv_subpass *subpass =
1653 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1654
1655 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1656 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1657 }
1658
1659 return VK_SUCCESS;
1660 }
1661
1662 void radv_CmdBindVertexBuffers(
1663 VkCommandBuffer commandBuffer,
1664 uint32_t firstBinding,
1665 uint32_t bindingCount,
1666 const VkBuffer* pBuffers,
1667 const VkDeviceSize* pOffsets)
1668 {
1669 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1670 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1671
1672 /* We have to defer setting up vertex buffer since we need the buffer
1673 * stride from the pipeline. */
1674
1675 assert(firstBinding + bindingCount < MAX_VBS);
1676 for (uint32_t i = 0; i < bindingCount; i++) {
1677 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1678 vb[firstBinding + i].offset = pOffsets[i];
1679 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1680 }
1681 }
1682
1683 void radv_CmdBindIndexBuffer(
1684 VkCommandBuffer commandBuffer,
1685 VkBuffer buffer,
1686 VkDeviceSize offset,
1687 VkIndexType indexType)
1688 {
1689 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1690
1691 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1692 cmd_buffer->state.index_offset = offset;
1693 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1694 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1695 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1696 }
1697
1698
1699 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1700 struct radv_descriptor_set *set,
1701 unsigned idx)
1702 {
1703 struct radeon_winsys *ws = cmd_buffer->device->ws;
1704
1705 cmd_buffer->state.descriptors[idx] = set;
1706 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1707 if (!set)
1708 return;
1709
1710 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1711 if (set->descriptors[j])
1712 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1713
1714 if(set->bo)
1715 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1716 }
1717
1718 void radv_CmdBindDescriptorSets(
1719 VkCommandBuffer commandBuffer,
1720 VkPipelineBindPoint pipelineBindPoint,
1721 VkPipelineLayout _layout,
1722 uint32_t firstSet,
1723 uint32_t descriptorSetCount,
1724 const VkDescriptorSet* pDescriptorSets,
1725 uint32_t dynamicOffsetCount,
1726 const uint32_t* pDynamicOffsets)
1727 {
1728 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1729 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1730 unsigned dyn_idx = 0;
1731
1732 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1733 cmd_buffer->cs, MAX_SETS * 4 * 6);
1734
1735 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1736 unsigned idx = i + firstSet;
1737 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1738 radv_bind_descriptor_set(cmd_buffer, set, idx);
1739
1740 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1741 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1742 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1743 assert(dyn_idx < dynamicOffsetCount);
1744
1745 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1746 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1747 dst[0] = va;
1748 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1749 dst[2] = range->size;
1750 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1751 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1752 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1753 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1754 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1755 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1756 cmd_buffer->push_constant_stages |=
1757 set->layout->dynamic_shader_stages;
1758 }
1759 }
1760
1761 assert(cmd_buffer->cs->cdw <= cdw_max);
1762 }
1763
1764 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1765 VkPipelineLayout layout,
1766 VkShaderStageFlags stageFlags,
1767 uint32_t offset,
1768 uint32_t size,
1769 const void* pValues)
1770 {
1771 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1772 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1773 cmd_buffer->push_constant_stages |= stageFlags;
1774 }
1775
1776 VkResult radv_EndCommandBuffer(
1777 VkCommandBuffer commandBuffer)
1778 {
1779 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1780
1781 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1782 si_emit_cache_flush(cmd_buffer);
1783
1784 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1785 cmd_buffer->record_fail)
1786 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1787 return VK_SUCCESS;
1788 }
1789
1790 static void
1791 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1792 {
1793 struct radeon_winsys *ws = cmd_buffer->device->ws;
1794 struct radv_shader_variant *compute_shader;
1795 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1796 uint64_t va;
1797
1798 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1799 return;
1800
1801 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1802
1803 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1804 va = ws->buffer_get_va(compute_shader->bo);
1805
1806 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1807
1808 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1809 cmd_buffer->cs, 16);
1810
1811 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1812 radeon_emit(cmd_buffer->cs, va >> 8);
1813 radeon_emit(cmd_buffer->cs, va >> 40);
1814
1815 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1816 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1817 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1818
1819
1820 cmd_buffer->compute_scratch_size_needed =
1821 MAX2(cmd_buffer->compute_scratch_size_needed,
1822 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1823
1824 /* change these once we have scratch support */
1825 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1826 S_00B860_WAVES(pipeline->max_waves) |
1827 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1828
1829 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1830 radeon_emit(cmd_buffer->cs,
1831 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1832 radeon_emit(cmd_buffer->cs,
1833 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1834 radeon_emit(cmd_buffer->cs,
1835 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1836
1837 assert(cmd_buffer->cs->cdw <= cdw_max);
1838 }
1839
1840
1841 void radv_CmdBindPipeline(
1842 VkCommandBuffer commandBuffer,
1843 VkPipelineBindPoint pipelineBindPoint,
1844 VkPipeline _pipeline)
1845 {
1846 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1847 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1848
1849 for (unsigned i = 0; i < MAX_SETS; i++) {
1850 if (cmd_buffer->state.descriptors[i])
1851 cmd_buffer->state.descriptors_dirty |= (1 << i);
1852 }
1853
1854 switch (pipelineBindPoint) {
1855 case VK_PIPELINE_BIND_POINT_COMPUTE:
1856 cmd_buffer->state.compute_pipeline = pipeline;
1857 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1858 break;
1859 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1860 cmd_buffer->state.pipeline = pipeline;
1861 cmd_buffer->state.vertex_descriptors_dirty = true;
1862 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1863 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1864
1865 /* Apply the dynamic state from the pipeline */
1866 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1867 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1868 &pipeline->dynamic_state,
1869 pipeline->dynamic_state_mask);
1870
1871 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1872 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1873 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1874 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1875
1876 if (radv_pipeline_has_gs(pipeline)) {
1877 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1878 AC_UD_SCRATCH_RING_OFFSETS);
1879 if (cmd_buffer->ring_offsets_idx == -1)
1880 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1881 else if (loc->sgpr_idx != -1)
1882 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
1883 }
1884 break;
1885 default:
1886 assert(!"invalid bind point");
1887 break;
1888 }
1889 }
1890
1891 void radv_CmdSetViewport(
1892 VkCommandBuffer commandBuffer,
1893 uint32_t firstViewport,
1894 uint32_t viewportCount,
1895 const VkViewport* pViewports)
1896 {
1897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1898
1899 const uint32_t total_count = firstViewport + viewportCount;
1900 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1901 cmd_buffer->state.dynamic.viewport.count = total_count;
1902
1903 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1904 pViewports, viewportCount * sizeof(*pViewports));
1905
1906 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1907 }
1908
1909 void radv_CmdSetScissor(
1910 VkCommandBuffer commandBuffer,
1911 uint32_t firstScissor,
1912 uint32_t scissorCount,
1913 const VkRect2D* pScissors)
1914 {
1915 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1916
1917 const uint32_t total_count = firstScissor + scissorCount;
1918 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1919 cmd_buffer->state.dynamic.scissor.count = total_count;
1920
1921 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1922 pScissors, scissorCount * sizeof(*pScissors));
1923 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1924 }
1925
1926 void radv_CmdSetLineWidth(
1927 VkCommandBuffer commandBuffer,
1928 float lineWidth)
1929 {
1930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1931 cmd_buffer->state.dynamic.line_width = lineWidth;
1932 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1933 }
1934
1935 void radv_CmdSetDepthBias(
1936 VkCommandBuffer commandBuffer,
1937 float depthBiasConstantFactor,
1938 float depthBiasClamp,
1939 float depthBiasSlopeFactor)
1940 {
1941 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1942
1943 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1944 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1945 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1946
1947 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1948 }
1949
1950 void radv_CmdSetBlendConstants(
1951 VkCommandBuffer commandBuffer,
1952 const float blendConstants[4])
1953 {
1954 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1955
1956 memcpy(cmd_buffer->state.dynamic.blend_constants,
1957 blendConstants, sizeof(float) * 4);
1958
1959 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1960 }
1961
1962 void radv_CmdSetDepthBounds(
1963 VkCommandBuffer commandBuffer,
1964 float minDepthBounds,
1965 float maxDepthBounds)
1966 {
1967 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1968
1969 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1970 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1971
1972 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1973 }
1974
1975 void radv_CmdSetStencilCompareMask(
1976 VkCommandBuffer commandBuffer,
1977 VkStencilFaceFlags faceMask,
1978 uint32_t compareMask)
1979 {
1980 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1981
1982 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1983 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1984 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1985 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1986
1987 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1988 }
1989
1990 void radv_CmdSetStencilWriteMask(
1991 VkCommandBuffer commandBuffer,
1992 VkStencilFaceFlags faceMask,
1993 uint32_t writeMask)
1994 {
1995 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1996
1997 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1998 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1999 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2000 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2001
2002 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2003 }
2004
2005 void radv_CmdSetStencilReference(
2006 VkCommandBuffer commandBuffer,
2007 VkStencilFaceFlags faceMask,
2008 uint32_t reference)
2009 {
2010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2011
2012 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2013 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2014 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2015 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2016
2017 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2018 }
2019
2020
2021 void radv_CmdExecuteCommands(
2022 VkCommandBuffer commandBuffer,
2023 uint32_t commandBufferCount,
2024 const VkCommandBuffer* pCmdBuffers)
2025 {
2026 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2027
2028 /* Emit pending flushes on primary prior to executing secondary */
2029 si_emit_cache_flush(primary);
2030
2031 for (uint32_t i = 0; i < commandBufferCount; i++) {
2032 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2033
2034 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2035 secondary->scratch_size_needed);
2036 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2037 secondary->compute_scratch_size_needed);
2038
2039 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2040 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2041 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2042 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2043
2044 if (secondary->ring_offsets_idx != -1) {
2045 if (primary->ring_offsets_idx == -1)
2046 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2047 else
2048 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2049 }
2050 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2051 }
2052
2053 /* if we execute secondary we need to re-emit out pipelines */
2054 if (commandBufferCount) {
2055 primary->state.emitted_pipeline = NULL;
2056 primary->state.emitted_compute_pipeline = NULL;
2057 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2058 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2059 }
2060 }
2061
2062 VkResult radv_CreateCommandPool(
2063 VkDevice _device,
2064 const VkCommandPoolCreateInfo* pCreateInfo,
2065 const VkAllocationCallbacks* pAllocator,
2066 VkCommandPool* pCmdPool)
2067 {
2068 RADV_FROM_HANDLE(radv_device, device, _device);
2069 struct radv_cmd_pool *pool;
2070
2071 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2072 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2073 if (pool == NULL)
2074 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2075
2076 if (pAllocator)
2077 pool->alloc = *pAllocator;
2078 else
2079 pool->alloc = device->alloc;
2080
2081 list_inithead(&pool->cmd_buffers);
2082 list_inithead(&pool->free_cmd_buffers);
2083
2084 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2085
2086 *pCmdPool = radv_cmd_pool_to_handle(pool);
2087
2088 return VK_SUCCESS;
2089
2090 }
2091
2092 void radv_DestroyCommandPool(
2093 VkDevice _device,
2094 VkCommandPool commandPool,
2095 const VkAllocationCallbacks* pAllocator)
2096 {
2097 RADV_FROM_HANDLE(radv_device, device, _device);
2098 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2099
2100 if (!pool)
2101 return;
2102
2103 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2104 &pool->cmd_buffers, pool_link) {
2105 radv_cmd_buffer_destroy(cmd_buffer);
2106 }
2107
2108 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2109 &pool->free_cmd_buffers, pool_link) {
2110 radv_cmd_buffer_destroy(cmd_buffer);
2111 }
2112
2113 vk_free2(&device->alloc, pAllocator, pool);
2114 }
2115
2116 VkResult radv_ResetCommandPool(
2117 VkDevice device,
2118 VkCommandPool commandPool,
2119 VkCommandPoolResetFlags flags)
2120 {
2121 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2122
2123 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2124 &pool->cmd_buffers, pool_link) {
2125 radv_reset_cmd_buffer(cmd_buffer);
2126 }
2127
2128 return VK_SUCCESS;
2129 }
2130
2131 void radv_TrimCommandPoolKHR(
2132 VkDevice device,
2133 VkCommandPool commandPool,
2134 VkCommandPoolTrimFlagsKHR flags)
2135 {
2136 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2137
2138 if (!pool)
2139 return;
2140
2141 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2142 &pool->free_cmd_buffers, pool_link) {
2143 radv_cmd_buffer_destroy(cmd_buffer);
2144 }
2145 }
2146
2147 void radv_CmdBeginRenderPass(
2148 VkCommandBuffer commandBuffer,
2149 const VkRenderPassBeginInfo* pRenderPassBegin,
2150 VkSubpassContents contents)
2151 {
2152 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2153 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2154 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2155
2156 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2157 cmd_buffer->cs, 2048);
2158
2159 cmd_buffer->state.framebuffer = framebuffer;
2160 cmd_buffer->state.pass = pass;
2161 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2162 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2163
2164 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2165 assert(cmd_buffer->cs->cdw <= cdw_max);
2166
2167 radv_cmd_buffer_clear_subpass(cmd_buffer);
2168 }
2169
2170 void radv_CmdNextSubpass(
2171 VkCommandBuffer commandBuffer,
2172 VkSubpassContents contents)
2173 {
2174 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2175
2176 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2177
2178 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2179 2048);
2180
2181 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2182 radv_cmd_buffer_clear_subpass(cmd_buffer);
2183 }
2184
2185 void radv_CmdDraw(
2186 VkCommandBuffer commandBuffer,
2187 uint32_t vertexCount,
2188 uint32_t instanceCount,
2189 uint32_t firstVertex,
2190 uint32_t firstInstance)
2191 {
2192 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2193
2194 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount);
2195
2196 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2197
2198 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2199 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2200 if (loc->sgpr_idx != -1) {
2201 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2202 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2203 radeon_emit(cmd_buffer->cs, firstVertex);
2204 radeon_emit(cmd_buffer->cs, firstInstance);
2205 radeon_emit(cmd_buffer->cs, 0);
2206 }
2207 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2208 radeon_emit(cmd_buffer->cs, instanceCount);
2209
2210 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2211 radeon_emit(cmd_buffer->cs, vertexCount);
2212 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2213 S_0287F0_USE_OPAQUE(0));
2214
2215 assert(cmd_buffer->cs->cdw <= cdw_max);
2216
2217 radv_cmd_buffer_trace_emit(cmd_buffer);
2218 }
2219
2220 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2221 {
2222 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
2223
2224 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2225 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2226 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2227 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2228 primitive_reset_index);
2229 }
2230 }
2231
2232 void radv_CmdDrawIndexed(
2233 VkCommandBuffer commandBuffer,
2234 uint32_t indexCount,
2235 uint32_t instanceCount,
2236 uint32_t firstIndex,
2237 int32_t vertexOffset,
2238 uint32_t firstInstance)
2239 {
2240 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2241 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2242 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2243 uint64_t index_va;
2244
2245 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount);
2246 radv_emit_primitive_reset_index(cmd_buffer);
2247
2248 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2249
2250 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2251 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2252
2253 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2254 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2255 if (loc->sgpr_idx != -1) {
2256 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2257 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2258 radeon_emit(cmd_buffer->cs, vertexOffset);
2259 radeon_emit(cmd_buffer->cs, firstInstance);
2260 radeon_emit(cmd_buffer->cs, 0);
2261 }
2262 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2263 radeon_emit(cmd_buffer->cs, instanceCount);
2264
2265 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2266 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2267 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2268 radeon_emit(cmd_buffer->cs, index_max_size);
2269 radeon_emit(cmd_buffer->cs, index_va);
2270 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2271 radeon_emit(cmd_buffer->cs, indexCount);
2272 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2273
2274 assert(cmd_buffer->cs->cdw <= cdw_max);
2275 radv_cmd_buffer_trace_emit(cmd_buffer);
2276 }
2277
2278 static void
2279 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2280 VkBuffer _buffer,
2281 VkDeviceSize offset,
2282 VkBuffer _count_buffer,
2283 VkDeviceSize count_offset,
2284 uint32_t draw_count,
2285 uint32_t stride,
2286 bool indexed)
2287 {
2288 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2289 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2290 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2291 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2292 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2293 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2294 indirect_va += offset + buffer->offset;
2295 uint64_t count_va = 0;
2296
2297 if (count_buffer) {
2298 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2299 count_va += count_offset + count_buffer->offset;
2300 }
2301
2302 if (!draw_count)
2303 return;
2304
2305 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2306
2307 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2308 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2309 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2310 assert(loc->sgpr_idx != -1);
2311 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2312 radeon_emit(cs, 1);
2313 radeon_emit(cs, indirect_va);
2314 radeon_emit(cs, indirect_va >> 32);
2315
2316 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2317 PKT3_DRAW_INDIRECT_MULTI,
2318 8, false));
2319 radeon_emit(cs, 0);
2320 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2321 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2322 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2323 S_2C3_DRAW_INDEX_ENABLE(1) |
2324 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2325 radeon_emit(cs, draw_count); /* count */
2326 radeon_emit(cs, count_va); /* count_addr */
2327 radeon_emit(cs, count_va >> 32);
2328 radeon_emit(cs, stride); /* stride */
2329 radeon_emit(cs, di_src_sel);
2330 radv_cmd_buffer_trace_emit(cmd_buffer);
2331 }
2332
2333 static void
2334 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2335 VkBuffer buffer,
2336 VkDeviceSize offset,
2337 VkBuffer countBuffer,
2338 VkDeviceSize countBufferOffset,
2339 uint32_t maxDrawCount,
2340 uint32_t stride)
2341 {
2342 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2343 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2344
2345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2346 cmd_buffer->cs, 14);
2347
2348 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2349 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2350
2351 assert(cmd_buffer->cs->cdw <= cdw_max);
2352 }
2353
2354 static void
2355 radv_cmd_draw_indexed_indirect_count(
2356 VkCommandBuffer commandBuffer,
2357 VkBuffer buffer,
2358 VkDeviceSize offset,
2359 VkBuffer countBuffer,
2360 VkDeviceSize countBufferOffset,
2361 uint32_t maxDrawCount,
2362 uint32_t stride)
2363 {
2364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2365 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2366 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2367 uint64_t index_va;
2368 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2369 radv_emit_primitive_reset_index(cmd_buffer);
2370
2371 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2372 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2373
2374 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2375
2376 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2377 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2378
2379 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2380 radeon_emit(cmd_buffer->cs, index_va);
2381 radeon_emit(cmd_buffer->cs, index_va >> 32);
2382
2383 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2384 radeon_emit(cmd_buffer->cs, index_max_size);
2385
2386 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2387 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2388
2389 assert(cmd_buffer->cs->cdw <= cdw_max);
2390 }
2391
2392 void radv_CmdDrawIndirect(
2393 VkCommandBuffer commandBuffer,
2394 VkBuffer buffer,
2395 VkDeviceSize offset,
2396 uint32_t drawCount,
2397 uint32_t stride)
2398 {
2399 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2400 VK_NULL_HANDLE, 0, drawCount, stride);
2401 }
2402
2403 void radv_CmdDrawIndexedIndirect(
2404 VkCommandBuffer commandBuffer,
2405 VkBuffer buffer,
2406 VkDeviceSize offset,
2407 uint32_t drawCount,
2408 uint32_t stride)
2409 {
2410 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2411 VK_NULL_HANDLE, 0, drawCount, stride);
2412 }
2413
2414 void radv_CmdDrawIndirectCountAMD(
2415 VkCommandBuffer commandBuffer,
2416 VkBuffer buffer,
2417 VkDeviceSize offset,
2418 VkBuffer countBuffer,
2419 VkDeviceSize countBufferOffset,
2420 uint32_t maxDrawCount,
2421 uint32_t stride)
2422 {
2423 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2424 countBuffer, countBufferOffset,
2425 maxDrawCount, stride);
2426 }
2427
2428 void radv_CmdDrawIndexedIndirectCountAMD(
2429 VkCommandBuffer commandBuffer,
2430 VkBuffer buffer,
2431 VkDeviceSize offset,
2432 VkBuffer countBuffer,
2433 VkDeviceSize countBufferOffset,
2434 uint32_t maxDrawCount,
2435 uint32_t stride)
2436 {
2437 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2438 countBuffer, countBufferOffset,
2439 maxDrawCount, stride);
2440 }
2441
2442 static void
2443 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2444 {
2445 radv_emit_compute_pipeline(cmd_buffer);
2446 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2447 VK_SHADER_STAGE_COMPUTE_BIT);
2448 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2449 VK_SHADER_STAGE_COMPUTE_BIT);
2450 si_emit_cache_flush(cmd_buffer);
2451 }
2452
2453 void radv_CmdDispatch(
2454 VkCommandBuffer commandBuffer,
2455 uint32_t x,
2456 uint32_t y,
2457 uint32_t z)
2458 {
2459 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2460
2461 radv_flush_compute_state(cmd_buffer);
2462
2463 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2464
2465 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2466 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2467 if (loc->sgpr_idx != -1) {
2468 assert(!loc->indirect);
2469 assert(loc->num_sgprs == 3);
2470 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2471 radeon_emit(cmd_buffer->cs, x);
2472 radeon_emit(cmd_buffer->cs, y);
2473 radeon_emit(cmd_buffer->cs, z);
2474 }
2475
2476 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2477 PKT3_SHADER_TYPE_S(1));
2478 radeon_emit(cmd_buffer->cs, x);
2479 radeon_emit(cmd_buffer->cs, y);
2480 radeon_emit(cmd_buffer->cs, z);
2481 radeon_emit(cmd_buffer->cs, 1);
2482
2483 assert(cmd_buffer->cs->cdw <= cdw_max);
2484 radv_cmd_buffer_trace_emit(cmd_buffer);
2485 }
2486
2487 void radv_CmdDispatchIndirect(
2488 VkCommandBuffer commandBuffer,
2489 VkBuffer _buffer,
2490 VkDeviceSize offset)
2491 {
2492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2493 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2494 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2495 va += buffer->offset + offset;
2496
2497 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2498
2499 radv_flush_compute_state(cmd_buffer);
2500
2501 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2502 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2503 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2504 if (loc->sgpr_idx != -1) {
2505 for (unsigned i = 0; i < 3; ++i) {
2506 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2507 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2508 COPY_DATA_DST_SEL(COPY_DATA_REG));
2509 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2510 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2511 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2512 radeon_emit(cmd_buffer->cs, 0);
2513 }
2514 }
2515
2516 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2517 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2518 PKT3_SHADER_TYPE_S(1));
2519 radeon_emit(cmd_buffer->cs, va);
2520 radeon_emit(cmd_buffer->cs, va >> 32);
2521 radeon_emit(cmd_buffer->cs, 1);
2522 } else {
2523 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2524 PKT3_SHADER_TYPE_S(1));
2525 radeon_emit(cmd_buffer->cs, 1);
2526 radeon_emit(cmd_buffer->cs, va);
2527 radeon_emit(cmd_buffer->cs, va >> 32);
2528
2529 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2530 PKT3_SHADER_TYPE_S(1));
2531 radeon_emit(cmd_buffer->cs, 0);
2532 radeon_emit(cmd_buffer->cs, 1);
2533 }
2534
2535 assert(cmd_buffer->cs->cdw <= cdw_max);
2536 radv_cmd_buffer_trace_emit(cmd_buffer);
2537 }
2538
2539 void radv_unaligned_dispatch(
2540 struct radv_cmd_buffer *cmd_buffer,
2541 uint32_t x,
2542 uint32_t y,
2543 uint32_t z)
2544 {
2545 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2546 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2547 uint32_t blocks[3], remainder[3];
2548
2549 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2550 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2551 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2552
2553 /* If aligned, these should be an entire block size, not 0 */
2554 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2555 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2556 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2557
2558 radv_flush_compute_state(cmd_buffer);
2559
2560 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2561
2562 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2563 radeon_emit(cmd_buffer->cs,
2564 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2565 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2566 radeon_emit(cmd_buffer->cs,
2567 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2568 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2569 radeon_emit(cmd_buffer->cs,
2570 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2571 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2572
2573 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2574 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2575 if (loc->sgpr_idx != -1) {
2576 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2577 radeon_emit(cmd_buffer->cs, blocks[0]);
2578 radeon_emit(cmd_buffer->cs, blocks[1]);
2579 radeon_emit(cmd_buffer->cs, blocks[2]);
2580 }
2581 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2582 PKT3_SHADER_TYPE_S(1));
2583 radeon_emit(cmd_buffer->cs, blocks[0]);
2584 radeon_emit(cmd_buffer->cs, blocks[1]);
2585 radeon_emit(cmd_buffer->cs, blocks[2]);
2586 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2587 S_00B800_PARTIAL_TG_EN(1));
2588
2589 assert(cmd_buffer->cs->cdw <= cdw_max);
2590 radv_cmd_buffer_trace_emit(cmd_buffer);
2591 }
2592
2593 void radv_CmdEndRenderPass(
2594 VkCommandBuffer commandBuffer)
2595 {
2596 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2597
2598 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2599
2600 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2601
2602 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2603 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2604 radv_handle_subpass_image_transition(cmd_buffer,
2605 (VkAttachmentReference){i, layout});
2606 }
2607
2608 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2609
2610 cmd_buffer->state.pass = NULL;
2611 cmd_buffer->state.subpass = NULL;
2612 cmd_buffer->state.attachments = NULL;
2613 cmd_buffer->state.framebuffer = NULL;
2614 }
2615
2616
2617 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2618 struct radv_image *image,
2619 const VkImageSubresourceRange *range)
2620 {
2621 assert(range->baseMipLevel == 0);
2622 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2623 unsigned layer_count = radv_get_layerCount(image, range);
2624 uint64_t size = image->surface.htile_slice_size * layer_count;
2625 uint64_t offset = image->offset + image->htile_offset +
2626 image->surface.htile_slice_size * range->baseArrayLayer;
2627
2628 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2629 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2630
2631 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2632
2633 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2634 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2635 RADV_CMD_FLAG_INV_VMEM_L1 |
2636 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2637 }
2638
2639 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2640 struct radv_image *image,
2641 VkImageLayout src_layout,
2642 VkImageLayout dst_layout,
2643 const VkImageSubresourceRange *range,
2644 VkImageAspectFlags pending_clears)
2645 {
2646 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2647 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2648 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2649 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2650 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2651 /* The clear will initialize htile. */
2652 return;
2653 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2654 radv_layout_has_htile(image, dst_layout)) {
2655 /* TODO: merge with the clear if applicable */
2656 radv_initialize_htile(cmd_buffer, image, range);
2657 } else if (!radv_layout_has_htile(image, src_layout) &&
2658 radv_layout_has_htile(image, dst_layout)) {
2659 radv_initialize_htile(cmd_buffer, image, range);
2660 } else if ((radv_layout_has_htile(image, src_layout) &&
2661 !radv_layout_has_htile(image, dst_layout)) ||
2662 (radv_layout_is_htile_compressed(image, src_layout) &&
2663 !radv_layout_is_htile_compressed(image, dst_layout))) {
2664 VkImageSubresourceRange local_range = *range;
2665 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2666 local_range.baseMipLevel = 0;
2667 local_range.levelCount = 1;
2668
2669 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2670 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2671
2672 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
2673
2674 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2675 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2676 }
2677 }
2678
2679 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2680 struct radv_image *image, uint32_t value)
2681 {
2682 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2683 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2684
2685 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2686 image->cmask.size, value);
2687
2688 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2689 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2690 RADV_CMD_FLAG_INV_VMEM_L1 |
2691 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2692 }
2693
2694 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2695 struct radv_image *image,
2696 VkImageLayout src_layout,
2697 VkImageLayout dst_layout,
2698 unsigned src_queue_mask,
2699 unsigned dst_queue_mask,
2700 const VkImageSubresourceRange *range,
2701 VkImageAspectFlags pending_clears)
2702 {
2703 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2704 if (image->fmask.size)
2705 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2706 else
2707 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2708 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2709 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2710 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2711 }
2712 }
2713
2714 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2715 struct radv_image *image, uint32_t value)
2716 {
2717
2718 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2719 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2720
2721 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2722 image->surface.dcc_size, value);
2723
2724 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2725 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2726 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2727 RADV_CMD_FLAG_INV_VMEM_L1 |
2728 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2729 }
2730
2731 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2732 struct radv_image *image,
2733 VkImageLayout src_layout,
2734 VkImageLayout dst_layout,
2735 unsigned src_queue_mask,
2736 unsigned dst_queue_mask,
2737 const VkImageSubresourceRange *range,
2738 VkImageAspectFlags pending_clears)
2739 {
2740 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2741 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2742 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2743 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2744 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2745 }
2746 }
2747
2748 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2749 struct radv_image *image,
2750 VkImageLayout src_layout,
2751 VkImageLayout dst_layout,
2752 uint32_t src_family,
2753 uint32_t dst_family,
2754 const VkImageSubresourceRange *range,
2755 VkImageAspectFlags pending_clears)
2756 {
2757 if (image->exclusive && src_family != dst_family) {
2758 /* This is an acquire or a release operation and there will be
2759 * a corresponding release/acquire. Do the transition in the
2760 * most flexible queue. */
2761
2762 assert(src_family == cmd_buffer->queue_family_index ||
2763 dst_family == cmd_buffer->queue_family_index);
2764
2765 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2766 return;
2767
2768 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2769 (src_family == RADV_QUEUE_GENERAL ||
2770 dst_family == RADV_QUEUE_GENERAL))
2771 return;
2772 }
2773
2774 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2775 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2776
2777 if (image->surface.htile_size)
2778 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2779 dst_layout, range, pending_clears);
2780
2781 if (image->cmask.size)
2782 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2783 dst_layout, src_queue_mask,
2784 dst_queue_mask, range,
2785 pending_clears);
2786
2787 if (image->surface.dcc_size)
2788 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2789 dst_layout, src_queue_mask,
2790 dst_queue_mask, range,
2791 pending_clears);
2792 }
2793
2794 void radv_CmdPipelineBarrier(
2795 VkCommandBuffer commandBuffer,
2796 VkPipelineStageFlags srcStageMask,
2797 VkPipelineStageFlags destStageMask,
2798 VkBool32 byRegion,
2799 uint32_t memoryBarrierCount,
2800 const VkMemoryBarrier* pMemoryBarriers,
2801 uint32_t bufferMemoryBarrierCount,
2802 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2803 uint32_t imageMemoryBarrierCount,
2804 const VkImageMemoryBarrier* pImageMemoryBarriers)
2805 {
2806 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2807 enum radv_cmd_flush_bits src_flush_bits = 0;
2808 enum radv_cmd_flush_bits dst_flush_bits = 0;
2809
2810 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2811 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
2812 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
2813 NULL);
2814 }
2815
2816 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2817 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
2818 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
2819 NULL);
2820 }
2821
2822 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2823 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2824 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
2825 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
2826 image);
2827 }
2828
2829 radv_stage_flush(cmd_buffer, srcStageMask);
2830 cmd_buffer->state.flush_bits |= src_flush_bits;
2831
2832 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2833 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2834 radv_handle_image_transition(cmd_buffer, image,
2835 pImageMemoryBarriers[i].oldLayout,
2836 pImageMemoryBarriers[i].newLayout,
2837 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2838 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2839 &pImageMemoryBarriers[i].subresourceRange,
2840 0);
2841 }
2842
2843 cmd_buffer->state.flush_bits |= dst_flush_bits;
2844 }
2845
2846
2847 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2848 struct radv_event *event,
2849 VkPipelineStageFlags stageMask,
2850 unsigned value)
2851 {
2852 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2853 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2854
2855 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2856
2857 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2858
2859 /* TODO: this is overkill. Probably should figure something out from
2860 * the stage mask. */
2861
2862 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2863 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2864 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2865 EVENT_INDEX(5));
2866 radeon_emit(cs, va);
2867 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2868 radeon_emit(cs, 2);
2869 radeon_emit(cs, 0);
2870 }
2871
2872 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2873 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2874 EVENT_INDEX(5));
2875 radeon_emit(cs, va);
2876 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2877 radeon_emit(cs, value);
2878 radeon_emit(cs, 0);
2879
2880 assert(cmd_buffer->cs->cdw <= cdw_max);
2881 }
2882
2883 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2884 VkEvent _event,
2885 VkPipelineStageFlags stageMask)
2886 {
2887 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2888 RADV_FROM_HANDLE(radv_event, event, _event);
2889
2890 write_event(cmd_buffer, event, stageMask, 1);
2891 }
2892
2893 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2894 VkEvent _event,
2895 VkPipelineStageFlags stageMask)
2896 {
2897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2898 RADV_FROM_HANDLE(radv_event, event, _event);
2899
2900 write_event(cmd_buffer, event, stageMask, 0);
2901 }
2902
2903 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2904 uint32_t eventCount,
2905 const VkEvent* pEvents,
2906 VkPipelineStageFlags srcStageMask,
2907 VkPipelineStageFlags dstStageMask,
2908 uint32_t memoryBarrierCount,
2909 const VkMemoryBarrier* pMemoryBarriers,
2910 uint32_t bufferMemoryBarrierCount,
2911 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2912 uint32_t imageMemoryBarrierCount,
2913 const VkImageMemoryBarrier* pImageMemoryBarriers)
2914 {
2915 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2916 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2917
2918 for (unsigned i = 0; i < eventCount; ++i) {
2919 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2920 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2921
2922 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2923
2924 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2925
2926 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2927 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2928 radeon_emit(cs, va);
2929 radeon_emit(cs, va >> 32);
2930 radeon_emit(cs, 1); /* reference value */
2931 radeon_emit(cs, 0xffffffff); /* mask */
2932 radeon_emit(cs, 4); /* poll interval */
2933
2934 assert(cmd_buffer->cs->cdw <= cdw_max);
2935 }
2936
2937
2938 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2939 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2940
2941 radv_handle_image_transition(cmd_buffer, image,
2942 pImageMemoryBarriers[i].oldLayout,
2943 pImageMemoryBarriers[i].newLayout,
2944 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2945 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2946 &pImageMemoryBarriers[i].subresourceRange,
2947 0);
2948 }
2949
2950 /* TODO: figure out how to do memory barriers without waiting */
2951 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2952 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2953 RADV_CMD_FLAG_INV_VMEM_L1 |
2954 RADV_CMD_FLAG_INV_SMEM_L1;
2955 }