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radv: do not update the number of scissors in vkCmdSetScissor()
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
87 dest->viewport.count = src->viewport.count;
88 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
89 src->viewport.count);
90 }
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
93 dest->scissor.count = src->scissor.count;
94 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
95 src->scissor.count);
96 }
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
99 dest->line_width = src->line_width;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
102 dest->depth_bias = src->depth_bias;
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
105 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
108 dest->depth_bounds = src->depth_bounds;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
111 dest->stencil_compare_mask = src->stencil_compare_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
114 dest->stencil_write_mask = src->stencil_write_mask;
115
116 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
117 dest->stencil_reference = src->stencil_reference;
118 }
119
120 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
121 {
122 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
123 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
124 }
125
126 enum ring_type radv_queue_family_to_ring(int f) {
127 switch (f) {
128 case RADV_QUEUE_GENERAL:
129 return RING_GFX;
130 case RADV_QUEUE_COMPUTE:
131 return RING_COMPUTE;
132 case RADV_QUEUE_TRANSFER:
133 return RING_DMA;
134 default:
135 unreachable("Unknown queue family");
136 }
137 }
138
139 static VkResult radv_create_cmd_buffer(
140 struct radv_device * device,
141 struct radv_cmd_pool * pool,
142 VkCommandBufferLevel level,
143 VkCommandBuffer* pCommandBuffer)
144 {
145 struct radv_cmd_buffer *cmd_buffer;
146 unsigned ring;
147 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
148 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
149 if (cmd_buffer == NULL)
150 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
151
152 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
153 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
154 cmd_buffer->device = device;
155 cmd_buffer->pool = pool;
156 cmd_buffer->level = level;
157
158 if (pool) {
159 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
160 cmd_buffer->queue_family_index = pool->queue_family_index;
161
162 } else {
163 /* Init the pool_link so we can safefly call list_del when we destroy
164 * the command buffer
165 */
166 list_inithead(&cmd_buffer->pool_link);
167 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
168 }
169
170 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
171
172 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
173 if (!cmd_buffer->cs) {
174 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
175 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
176 }
177
178 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
179
180 cmd_buffer->upload.offset = 0;
181 cmd_buffer->upload.size = 0;
182 list_inithead(&cmd_buffer->upload.list);
183
184 return VK_SUCCESS;
185 }
186
187 static void
188 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
189 {
190 list_del(&cmd_buffer->pool_link);
191
192 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
193 &cmd_buffer->upload.list, list) {
194 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
195 list_del(&up->list);
196 free(up);
197 }
198
199 if (cmd_buffer->upload.upload_bo)
200 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
201 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
202 free(cmd_buffer->push_descriptors.set.mapped_ptr);
203 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
204 }
205
206 static VkResult
207 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
208 {
209
210 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
211
212 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
213 &cmd_buffer->upload.list, list) {
214 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
215 list_del(&up->list);
216 free(up);
217 }
218
219 cmd_buffer->push_constant_stages = 0;
220 cmd_buffer->scratch_size_needed = 0;
221 cmd_buffer->compute_scratch_size_needed = 0;
222 cmd_buffer->esgs_ring_size_needed = 0;
223 cmd_buffer->gsvs_ring_size_needed = 0;
224 cmd_buffer->tess_rings_needed = false;
225 cmd_buffer->sample_positions_needed = false;
226
227 if (cmd_buffer->upload.upload_bo)
228 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
229 cmd_buffer->upload.upload_bo, 8);
230 cmd_buffer->upload.offset = 0;
231
232 cmd_buffer->record_result = VK_SUCCESS;
233
234 cmd_buffer->ring_offsets_idx = -1;
235
236 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
237 void *fence_ptr;
238 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
239 &cmd_buffer->gfx9_fence_offset,
240 &fence_ptr);
241 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
242 }
243
244 return cmd_buffer->record_result;
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 static void
335 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
336 unsigned count, const uint32_t *data)
337 {
338 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
339 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
340 S_370_WR_CONFIRM(1) |
341 S_370_ENGINE_SEL(V_370_ME));
342 radeon_emit(cs, va);
343 radeon_emit(cs, va >> 32);
344 radeon_emit_array(cs, data, count);
345 }
346
347 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
348 {
349 struct radv_device *device = cmd_buffer->device;
350 struct radeon_winsys_cs *cs = cmd_buffer->cs;
351 uint64_t va;
352
353 if (!device->trace_bo)
354 return;
355
356 va = device->ws->buffer_get_va(device->trace_bo);
357 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
358 va += 4;
359
360 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
361
362 ++cmd_buffer->state.trace_id;
363 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
364 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
365 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
366 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
367 }
368
369 static void
370 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
371 {
372 if (cmd_buffer->device->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
373 enum radv_cmd_flush_bits flags;
374
375 /* Force wait for graphics/compute engines to be idle. */
376 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
377 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
378
379 si_cs_emit_cache_flush(cmd_buffer->cs, false,
380 cmd_buffer->device->physical_device->rad_info.chip_class,
381 NULL, 0,
382 radv_cmd_buffer_uses_mec(cmd_buffer),
383 flags);
384 }
385
386 radv_cmd_buffer_trace_emit(cmd_buffer);
387 }
388
389 static void
390 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
391 struct radv_pipeline *pipeline, enum ring_type ring)
392 {
393 struct radv_device *device = cmd_buffer->device;
394 struct radeon_winsys_cs *cs = cmd_buffer->cs;
395 uint32_t data[2];
396 uint64_t va;
397
398 if (!device->trace_bo)
399 return;
400
401 va = device->ws->buffer_get_va(device->trace_bo);
402
403 switch (ring) {
404 case RING_GFX:
405 va += 8;
406 break;
407 case RING_COMPUTE:
408 va += 16;
409 break;
410 default:
411 assert(!"invalid ring type");
412 }
413
414 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
415 cmd_buffer->cs, 6);
416
417 data[0] = (uintptr_t)pipeline;
418 data[1] = (uintptr_t)pipeline >> 32;
419
420 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
421 radv_emit_write_data_packet(cs, va, 2, data);
422 }
423
424 static void
425 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
426 {
427 struct radv_device *device = cmd_buffer->device;
428 struct radeon_winsys_cs *cs = cmd_buffer->cs;
429 uint32_t data[MAX_SETS * 2] = {};
430 uint64_t va;
431
432 if (!device->trace_bo)
433 return;
434
435 va = device->ws->buffer_get_va(device->trace_bo) + 24;
436
437 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
438 cmd_buffer->cs, 4 + MAX_SETS * 2);
439
440 for (int i = 0; i < MAX_SETS; i++) {
441 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
442 if (!set)
443 continue;
444
445 data[i * 2] = (uintptr_t)set;
446 data[i * 2 + 1] = (uintptr_t)set >> 32;
447 }
448
449 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
450 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
451 }
452
453 static void
454 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
455 struct radv_pipeline *pipeline)
456 {
457 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
458 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
459 8);
460 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
461 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
462
463 if (cmd_buffer->device->physical_device->has_rbplus) {
464
465 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
466 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
467
468 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
469 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
470 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
471 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
472 }
473 }
474
475 static void
476 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
477 struct radv_pipeline *pipeline)
478 {
479 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
480 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
481 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
482
483 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
484 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
485 }
486
487 /* 12.4 fixed-point */
488 static unsigned radv_pack_float_12p4(float x)
489 {
490 return x <= 0 ? 0 :
491 x >= 4096 ? 0xffff : x * 16;
492 }
493
494 struct ac_userdata_info *
495 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
496 gl_shader_stage stage,
497 int idx)
498 {
499 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
500 }
501
502 static void
503 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
504 struct radv_pipeline *pipeline,
505 gl_shader_stage stage,
506 int idx, uint64_t va)
507 {
508 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
509 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
510 if (loc->sgpr_idx == -1)
511 return;
512 assert(loc->num_sgprs == 2);
513 assert(!loc->indirect);
514 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
515 radeon_emit(cmd_buffer->cs, va);
516 radeon_emit(cmd_buffer->cs, va >> 32);
517 }
518
519 static void
520 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
521 struct radv_pipeline *pipeline)
522 {
523 int num_samples = pipeline->graphics.ms.num_samples;
524 struct radv_multisample_state *ms = &pipeline->graphics.ms;
525 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
526
527 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
528 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
529 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
530
531 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
532 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
533
534 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
535 return;
536
537 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
538 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
539 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
540
541 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
542
543 /* GFX9: Flush DFSM when the AA mode changes. */
544 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
545 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
546 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
547 }
548 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
549 uint32_t offset;
550 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
551 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
552 if (loc->sgpr_idx == -1)
553 return;
554 assert(loc->num_sgprs == 1);
555 assert(!loc->indirect);
556 switch (num_samples) {
557 default:
558 offset = 0;
559 break;
560 case 2:
561 offset = 1;
562 break;
563 case 4:
564 offset = 3;
565 break;
566 case 8:
567 offset = 7;
568 break;
569 case 16:
570 offset = 15;
571 break;
572 }
573
574 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
575 cmd_buffer->sample_positions_needed = true;
576 }
577 }
578
579 static void
580 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
581 struct radv_pipeline *pipeline)
582 {
583 struct radv_raster_state *raster = &pipeline->graphics.raster;
584
585 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
586 raster->pa_cl_clip_cntl);
587
588 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
589 raster->spi_interp_control);
590
591 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
592 unsigned tmp = (unsigned)(1.0 * 8.0);
593 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
594 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
595 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
596
597 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
598 raster->pa_su_vtx_cntl);
599
600 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
601 raster->pa_su_sc_mode_cntl);
602 }
603
604 static inline void
605 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
606 unsigned size)
607 {
608 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
609 si_cp_dma_prefetch(cmd_buffer, va, size);
610 }
611
612 static void
613 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
614 struct radv_pipeline *pipeline,
615 struct radv_shader_variant *shader,
616 struct ac_vs_output_info *outinfo)
617 {
618 struct radeon_winsys *ws = cmd_buffer->device->ws;
619 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
620 unsigned export_count;
621
622 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
623 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
624
625 export_count = MAX2(1, outinfo->param_exports);
626 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
627 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
628
629 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
630 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
631 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
632 V_02870C_SPI_SHADER_4COMP :
633 V_02870C_SPI_SHADER_NONE) |
634 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
635 V_02870C_SPI_SHADER_4COMP :
636 V_02870C_SPI_SHADER_NONE) |
637 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
638 V_02870C_SPI_SHADER_4COMP :
639 V_02870C_SPI_SHADER_NONE));
640
641
642 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
643 radeon_emit(cmd_buffer->cs, va >> 8);
644 radeon_emit(cmd_buffer->cs, va >> 40);
645 radeon_emit(cmd_buffer->cs, shader->rsrc1);
646 radeon_emit(cmd_buffer->cs, shader->rsrc2);
647
648 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
649 S_028818_VTX_W0_FMT(1) |
650 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
651 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
652 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
653
654
655 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
656 pipeline->graphics.pa_cl_vs_out_cntl);
657
658 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
659 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
660 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
661 }
662
663 static void
664 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
665 struct radv_shader_variant *shader,
666 struct ac_es_output_info *outinfo)
667 {
668 struct radeon_winsys *ws = cmd_buffer->device->ws;
669 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
670
671 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
672 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
673
674 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
675 outinfo->esgs_itemsize / 4);
676 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
677 radeon_emit(cmd_buffer->cs, va >> 8);
678 radeon_emit(cmd_buffer->cs, va >> 40);
679 radeon_emit(cmd_buffer->cs, shader->rsrc1);
680 radeon_emit(cmd_buffer->cs, shader->rsrc2);
681 }
682
683 static void
684 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
685 struct radv_shader_variant *shader)
686 {
687 struct radeon_winsys *ws = cmd_buffer->device->ws;
688 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
689 uint32_t rsrc2 = shader->rsrc2;
690
691 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
692 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
693
694 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
695 radeon_emit(cmd_buffer->cs, va >> 8);
696 radeon_emit(cmd_buffer->cs, va >> 40);
697
698 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
699 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
700 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
701 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
702
703 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
704 radeon_emit(cmd_buffer->cs, shader->rsrc1);
705 radeon_emit(cmd_buffer->cs, rsrc2);
706 }
707
708 static void
709 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
710 struct radv_shader_variant *shader)
711 {
712 struct radeon_winsys *ws = cmd_buffer->device->ws;
713 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
714
715 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
716 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
717
718 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
719 radeon_emit(cmd_buffer->cs, va >> 8);
720 radeon_emit(cmd_buffer->cs, va >> 40);
721 radeon_emit(cmd_buffer->cs, shader->rsrc1);
722 radeon_emit(cmd_buffer->cs, shader->rsrc2);
723 }
724
725 static void
726 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
727 struct radv_pipeline *pipeline)
728 {
729 struct radv_shader_variant *vs;
730
731 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
732
733 vs = pipeline->shaders[MESA_SHADER_VERTEX];
734
735 if (vs->info.vs.as_ls)
736 radv_emit_hw_ls(cmd_buffer, vs);
737 else if (vs->info.vs.as_es)
738 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
739 else
740 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
741
742 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
743 }
744
745
746 static void
747 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
748 struct radv_pipeline *pipeline)
749 {
750 if (!radv_pipeline_has_tess(pipeline))
751 return;
752
753 struct radv_shader_variant *tes, *tcs;
754
755 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
756 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
757
758 if (tes->info.tes.as_es)
759 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
760 else
761 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
762
763 radv_emit_hw_hs(cmd_buffer, tcs);
764
765 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
766 pipeline->graphics.tess.tf_param);
767
768 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
769 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
770 pipeline->graphics.tess.ls_hs_config);
771 else
772 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
773 pipeline->graphics.tess.ls_hs_config);
774
775 struct ac_userdata_info *loc;
776
777 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
778 if (loc->sgpr_idx != -1) {
779 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
780 assert(loc->num_sgprs == 4);
781 assert(!loc->indirect);
782 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
783 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
784 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
785 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
786 pipeline->graphics.tess.num_tcs_input_cp << 26);
787 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
788 }
789
790 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
791 if (loc->sgpr_idx != -1) {
792 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
793 assert(loc->num_sgprs == 1);
794 assert(!loc->indirect);
795
796 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
797 pipeline->graphics.tess.offchip_layout);
798 }
799
800 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
801 if (loc->sgpr_idx != -1) {
802 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
803 assert(loc->num_sgprs == 1);
804 assert(!loc->indirect);
805
806 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
807 pipeline->graphics.tess.tcs_in_layout);
808 }
809 }
810
811 static void
812 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
813 struct radv_pipeline *pipeline)
814 {
815 struct radeon_winsys *ws = cmd_buffer->device->ws;
816 struct radv_shader_variant *gs;
817 uint64_t va;
818
819 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
820
821 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
822 if (!gs)
823 return;
824
825 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
826
827 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
828 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
829 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
830 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
831
832 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
833
834 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
835
836 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
837 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
838 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
839 radeon_emit(cmd_buffer->cs, 0);
840 radeon_emit(cmd_buffer->cs, 0);
841 radeon_emit(cmd_buffer->cs, 0);
842
843 uint32_t gs_num_invocations = gs->info.gs.invocations;
844 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
845 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
846 S_028B90_ENABLE(gs_num_invocations > 0));
847
848 va = ws->buffer_get_va(gs->bo) + gs->bo_offset;
849 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
850 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
851
852 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
853 radeon_emit(cmd_buffer->cs, va >> 8);
854 radeon_emit(cmd_buffer->cs, va >> 40);
855 radeon_emit(cmd_buffer->cs, gs->rsrc1);
856 radeon_emit(cmd_buffer->cs, gs->rsrc2);
857
858 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
859
860 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
861 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
862 if (loc->sgpr_idx != -1) {
863 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
864 uint32_t num_entries = 64;
865 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
866
867 if (is_vi)
868 num_entries *= stride;
869
870 stride = S_008F04_STRIDE(stride);
871 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
872 radeon_emit(cmd_buffer->cs, stride);
873 radeon_emit(cmd_buffer->cs, num_entries);
874 }
875 }
876
877 static void
878 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
879 struct radv_pipeline *pipeline)
880 {
881 struct radeon_winsys *ws = cmd_buffer->device->ws;
882 struct radv_shader_variant *ps;
883 uint64_t va;
884 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
885 struct radv_blend_state *blend = &pipeline->graphics.blend;
886 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
887
888 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
889 va = ws->buffer_get_va(ps->bo) + ps->bo_offset;
890 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
891 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
892
893 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
894 radeon_emit(cmd_buffer->cs, va >> 8);
895 radeon_emit(cmd_buffer->cs, va >> 40);
896 radeon_emit(cmd_buffer->cs, ps->rsrc1);
897 radeon_emit(cmd_buffer->cs, ps->rsrc2);
898
899 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
900 pipeline->graphics.db_shader_control);
901
902 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
903 ps->config.spi_ps_input_ena);
904
905 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
906 ps->config.spi_ps_input_addr);
907
908 if (ps->info.info.ps.force_persample)
909 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
910
911 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
912 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
913
914 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
915
916 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
917 pipeline->graphics.shader_z_format);
918
919 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
920
921 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
922 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
923
924 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
925 /* optimise this? */
926 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
927 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
928 }
929
930 if (pipeline->graphics.ps_input_cntl_num) {
931 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
932 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
933 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
934 }
935 }
936 }
937
938 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
939 struct radv_pipeline *pipeline)
940 {
941 uint32_t vtx_reuse_depth = 30;
942 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
943 return;
944
945 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
946 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
947 vtx_reuse_depth = 14;
948 }
949 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
950 vtx_reuse_depth);
951 }
952
953 static void
954 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
955 {
956 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
957
958 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
959 return;
960
961 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
962 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
963 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
964 radv_update_multisample_state(cmd_buffer, pipeline);
965 radv_emit_vertex_shader(cmd_buffer, pipeline);
966 radv_emit_tess_shaders(cmd_buffer, pipeline);
967 radv_emit_geometry_shader(cmd_buffer, pipeline);
968 radv_emit_fragment_shader(cmd_buffer, pipeline);
969 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
970
971 cmd_buffer->scratch_size_needed =
972 MAX2(cmd_buffer->scratch_size_needed,
973 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
974
975 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
976 S_0286E8_WAVES(pipeline->max_waves) |
977 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
978
979 if (!cmd_buffer->state.emitted_pipeline ||
980 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
981 pipeline->graphics.can_use_guardband)
982 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
983
984 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
985
986 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
987 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
988 } else {
989 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
990 }
991 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
992
993 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
994
995 cmd_buffer->state.emitted_pipeline = pipeline;
996 }
997
998 static void
999 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1000 {
1001 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1002 cmd_buffer->state.dynamic.viewport.viewports);
1003 }
1004
1005 static void
1006 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1007 {
1008 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1009 si_write_scissors(cmd_buffer->cs, 0, count,
1010 cmd_buffer->state.dynamic.scissor.scissors,
1011 cmd_buffer->state.dynamic.viewport.viewports,
1012 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1013 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1014 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1015 }
1016
1017 static void
1018 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1019 {
1020 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1021
1022 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1023 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1024 }
1025
1026 static void
1027 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1028 {
1029 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1030
1031 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1032 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1033 }
1034
1035 static void
1036 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1037 {
1038 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1039
1040 radeon_set_context_reg_seq(cmd_buffer->cs,
1041 R_028430_DB_STENCILREFMASK, 2);
1042 radeon_emit(cmd_buffer->cs,
1043 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1044 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1045 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1046 S_028430_STENCILOPVAL(1));
1047 radeon_emit(cmd_buffer->cs,
1048 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1049 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1050 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1051 S_028434_STENCILOPVAL_BF(1));
1052 }
1053
1054 static void
1055 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1056 {
1057 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1058
1059 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1060 fui(d->depth_bounds.min));
1061 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1062 fui(d->depth_bounds.max));
1063 }
1064
1065 static void
1066 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1067 {
1068 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1069 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1070 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1071 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1072
1073 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1074 radeon_set_context_reg_seq(cmd_buffer->cs,
1075 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1076 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1077 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1078 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1079 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1080 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1081 }
1082 }
1083
1084 static void
1085 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1086 int index,
1087 struct radv_color_buffer_info *cb)
1088 {
1089 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1090
1091 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1092 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1093 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1094 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1095 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1096 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1097 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1098 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1099 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1100 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1101 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1102 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1103 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1104
1105 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1106 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1107 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1108
1109 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1110 cb->gfx9_epitch);
1111 } else {
1112 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1113 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1114 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1115 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1116 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1117 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1118 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1119 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1120 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1121 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1122 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1123 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1124
1125 if (is_vi) { /* DCC BASE */
1126 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1127 }
1128 }
1129 }
1130
1131 static void
1132 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1133 struct radv_ds_buffer_info *ds,
1134 struct radv_image *image,
1135 VkImageLayout layout)
1136 {
1137 uint32_t db_z_info = ds->db_z_info;
1138 uint32_t db_stencil_info = ds->db_stencil_info;
1139
1140 if (!radv_layout_has_htile(image, layout,
1141 radv_image_queue_family_mask(image,
1142 cmd_buffer->queue_family_index,
1143 cmd_buffer->queue_family_index))) {
1144 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1145 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1146 }
1147
1148 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1149 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1150
1151
1152 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1153 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1154 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1155 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1156 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1157
1158 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1163 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1165 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1167 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1168 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1169
1170 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1171 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1172 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1173 } else {
1174 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1175
1176 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1177 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1178 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1179 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1180 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1183 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1184 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1185 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1186
1187 }
1188
1189 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1190 ds->pa_su_poly_offset_db_fmt_cntl);
1191 }
1192
1193 void
1194 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1195 struct radv_image *image,
1196 VkClearDepthStencilValue ds_clear_value,
1197 VkImageAspectFlags aspects)
1198 {
1199 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1200 va += image->offset + image->clear_value_offset;
1201 unsigned reg_offset = 0, reg_count = 0;
1202
1203 if (!image->surface.htile_size || !aspects)
1204 return;
1205
1206 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1207 ++reg_count;
1208 } else {
1209 ++reg_offset;
1210 va += 4;
1211 }
1212 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1213 ++reg_count;
1214
1215 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1216
1217 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1218 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1219 S_370_WR_CONFIRM(1) |
1220 S_370_ENGINE_SEL(V_370_PFP));
1221 radeon_emit(cmd_buffer->cs, va);
1222 radeon_emit(cmd_buffer->cs, va >> 32);
1223 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1224 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1225 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1226 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1227
1228 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1229 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1230 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1231 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1232 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1233 }
1234
1235 static void
1236 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1237 struct radv_image *image)
1238 {
1239 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1240 va += image->offset + image->clear_value_offset;
1241
1242 if (!image->surface.htile_size)
1243 return;
1244
1245 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1246
1247 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1248 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1249 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1250 COPY_DATA_COUNT_SEL);
1251 radeon_emit(cmd_buffer->cs, va);
1252 radeon_emit(cmd_buffer->cs, va >> 32);
1253 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1254 radeon_emit(cmd_buffer->cs, 0);
1255
1256 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1257 radeon_emit(cmd_buffer->cs, 0);
1258 }
1259
1260 /*
1261 *with DCC some colors don't require CMASK elimiation before being
1262 * used as a texture. This sets a predicate value to determine if the
1263 * cmask eliminate is required.
1264 */
1265 void
1266 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1267 struct radv_image *image,
1268 bool value)
1269 {
1270 uint64_t pred_val = value;
1271 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1272 va += image->offset + image->dcc_pred_offset;
1273
1274 if (!image->surface.dcc_size)
1275 return;
1276
1277 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1278
1279 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1280 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1281 S_370_WR_CONFIRM(1) |
1282 S_370_ENGINE_SEL(V_370_PFP));
1283 radeon_emit(cmd_buffer->cs, va);
1284 radeon_emit(cmd_buffer->cs, va >> 32);
1285 radeon_emit(cmd_buffer->cs, pred_val);
1286 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1287 }
1288
1289 void
1290 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1291 struct radv_image *image,
1292 int idx,
1293 uint32_t color_values[2])
1294 {
1295 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1296 va += image->offset + image->clear_value_offset;
1297
1298 if (!image->cmask.size && !image->surface.dcc_size)
1299 return;
1300
1301 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1302
1303 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1304 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1305 S_370_WR_CONFIRM(1) |
1306 S_370_ENGINE_SEL(V_370_PFP));
1307 radeon_emit(cmd_buffer->cs, va);
1308 radeon_emit(cmd_buffer->cs, va >> 32);
1309 radeon_emit(cmd_buffer->cs, color_values[0]);
1310 radeon_emit(cmd_buffer->cs, color_values[1]);
1311
1312 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1313 radeon_emit(cmd_buffer->cs, color_values[0]);
1314 radeon_emit(cmd_buffer->cs, color_values[1]);
1315 }
1316
1317 static void
1318 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1319 struct radv_image *image,
1320 int idx)
1321 {
1322 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1323 va += image->offset + image->clear_value_offset;
1324
1325 if (!image->cmask.size && !image->surface.dcc_size)
1326 return;
1327
1328 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1329 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1330
1331 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1332 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1333 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1334 COPY_DATA_COUNT_SEL);
1335 radeon_emit(cmd_buffer->cs, va);
1336 radeon_emit(cmd_buffer->cs, va >> 32);
1337 radeon_emit(cmd_buffer->cs, reg >> 2);
1338 radeon_emit(cmd_buffer->cs, 0);
1339
1340 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1341 radeon_emit(cmd_buffer->cs, 0);
1342 }
1343
1344 void
1345 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1346 {
1347 int i;
1348 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1349 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1350
1351 /* this may happen for inherited secondary recording */
1352 if (!framebuffer)
1353 return;
1354
1355 for (i = 0; i < 8; ++i) {
1356 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1357 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1358 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1359 continue;
1360 }
1361
1362 int idx = subpass->color_attachments[i].attachment;
1363 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1364
1365 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1366
1367 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1368 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1369
1370 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1371 }
1372
1373 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1374 int idx = subpass->depth_stencil_attachment.attachment;
1375 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1376 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1377 struct radv_image *image = att->attachment->image;
1378 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1379 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1380 cmd_buffer->queue_family_index,
1381 cmd_buffer->queue_family_index);
1382 /* We currently don't support writing decompressed HTILE */
1383 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1384 radv_layout_is_htile_compressed(image, layout, queue_mask));
1385
1386 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1387
1388 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1389 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1390 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1391 }
1392 radv_load_depth_clear_regs(cmd_buffer, image);
1393 } else {
1394 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1395 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1396 else
1397 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1398
1399 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1400 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1401 }
1402 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1403 S_028208_BR_X(framebuffer->width) |
1404 S_028208_BR_Y(framebuffer->height));
1405
1406 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1407 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1408 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1409 }
1410 }
1411
1412 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1413 {
1414 uint32_t db_count_control;
1415
1416 if(!cmd_buffer->state.active_occlusion_queries) {
1417 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1418 db_count_control = 0;
1419 } else {
1420 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1421 }
1422 } else {
1423 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1424 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1425 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1426 S_028004_ZPASS_ENABLE(1) |
1427 S_028004_SLICE_EVEN_ENABLE(1) |
1428 S_028004_SLICE_ODD_ENABLE(1);
1429 } else {
1430 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1431 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1432 }
1433 }
1434
1435 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1436 }
1437
1438 static void
1439 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1440 {
1441 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1442 return;
1443
1444 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1445 radv_emit_viewport(cmd_buffer);
1446
1447 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1448 radv_emit_scissor(cmd_buffer);
1449
1450 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1451 radv_emit_line_width(cmd_buffer);
1452
1453 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1454 radv_emit_blend_constants(cmd_buffer);
1455
1456 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1457 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1458 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1459 radv_emit_stencil(cmd_buffer);
1460
1461 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1462 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1463 radv_emit_depth_bounds(cmd_buffer);
1464
1465 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1466 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1467 radv_emit_depth_biais(cmd_buffer);
1468
1469 cmd_buffer->state.dirty = 0;
1470 }
1471
1472 static void
1473 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1474 struct radv_pipeline *pipeline,
1475 int idx,
1476 uint64_t va,
1477 gl_shader_stage stage)
1478 {
1479 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1480 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1481
1482 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1483 return;
1484
1485 assert(!desc_set_loc->indirect);
1486 assert(desc_set_loc->num_sgprs == 2);
1487 radeon_set_sh_reg_seq(cmd_buffer->cs,
1488 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1489 radeon_emit(cmd_buffer->cs, va);
1490 radeon_emit(cmd_buffer->cs, va >> 32);
1491 }
1492
1493 static void
1494 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1495 VkShaderStageFlags stages,
1496 struct radv_descriptor_set *set,
1497 unsigned idx)
1498 {
1499 if (cmd_buffer->state.pipeline) {
1500 radv_foreach_stage(stage, stages) {
1501 if (cmd_buffer->state.pipeline->shaders[stage])
1502 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1503 idx, set->va,
1504 stage);
1505 }
1506 }
1507
1508 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1509 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1510 idx, set->va,
1511 MESA_SHADER_COMPUTE);
1512 }
1513
1514 static void
1515 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1516 {
1517 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1518 unsigned bo_offset;
1519
1520 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1521 set->mapped_ptr,
1522 &bo_offset))
1523 return;
1524
1525 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1526 set->va += bo_offset;
1527 }
1528
1529 static void
1530 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1531 {
1532 uint32_t size = MAX_SETS * 2 * 4;
1533 uint32_t offset;
1534 void *ptr;
1535
1536 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1537 256, &offset, &ptr))
1538 return;
1539
1540 for (unsigned i = 0; i < MAX_SETS; i++) {
1541 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1542 uint64_t set_va = 0;
1543 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1544 if (set)
1545 set_va = set->va;
1546 uptr[0] = set_va & 0xffffffff;
1547 uptr[1] = set_va >> 32;
1548 }
1549
1550 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1551 va += offset;
1552
1553 if (cmd_buffer->state.pipeline) {
1554 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1555 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1556 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1557
1558 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1559 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1560 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1561
1562 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1563 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1564 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1565
1566 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1567 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1568 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1569
1570 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1571 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1572 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1573 }
1574
1575 if (cmd_buffer->state.compute_pipeline)
1576 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1577 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1578 }
1579
1580 static void
1581 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1582 VkShaderStageFlags stages)
1583 {
1584 unsigned i;
1585
1586 if (!cmd_buffer->state.descriptors_dirty)
1587 return;
1588
1589 if (cmd_buffer->state.push_descriptors_dirty)
1590 radv_flush_push_descriptors(cmd_buffer);
1591
1592 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1593 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1594 radv_flush_indirect_descriptor_sets(cmd_buffer);
1595 }
1596
1597 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1598 cmd_buffer->cs,
1599 MAX_SETS * MESA_SHADER_STAGES * 4);
1600
1601 for (i = 0; i < MAX_SETS; i++) {
1602 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1603 continue;
1604 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1605 if (!set)
1606 continue;
1607
1608 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1609 }
1610 cmd_buffer->state.descriptors_dirty = 0;
1611 cmd_buffer->state.push_descriptors_dirty = false;
1612
1613 radv_save_descriptors(cmd_buffer);
1614
1615 assert(cmd_buffer->cs->cdw <= cdw_max);
1616 }
1617
1618 static void
1619 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1620 struct radv_pipeline *pipeline,
1621 VkShaderStageFlags stages)
1622 {
1623 struct radv_pipeline_layout *layout = pipeline->layout;
1624 unsigned offset;
1625 void *ptr;
1626 uint64_t va;
1627
1628 stages &= cmd_buffer->push_constant_stages;
1629 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1630 return;
1631
1632 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1633 16 * layout->dynamic_offset_count,
1634 256, &offset, &ptr))
1635 return;
1636
1637 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1638 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1639 16 * layout->dynamic_offset_count);
1640
1641 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1642 va += offset;
1643
1644 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1645 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1646
1647 radv_foreach_stage(stage, stages) {
1648 if (pipeline->shaders[stage]) {
1649 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1650 AC_UD_PUSH_CONSTANTS, va);
1651 }
1652 }
1653
1654 cmd_buffer->push_constant_stages &= ~stages;
1655 assert(cmd_buffer->cs->cdw <= cdw_max);
1656 }
1657
1658 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1659 bool indexed_draw)
1660 {
1661 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1662
1663 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1664 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1665 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1666 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1667 primitive_reset_en);
1668 } else {
1669 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1670 primitive_reset_en);
1671 }
1672 }
1673
1674 if (primitive_reset_en) {
1675 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1676
1677 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1678 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1679 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1680 primitive_reset_index);
1681 }
1682 }
1683 }
1684
1685 static bool
1686 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1687 {
1688 struct radv_device *device = cmd_buffer->device;
1689
1690 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1691 cmd_buffer->state.pipeline->vertex_elements.count &&
1692 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1693 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1694 unsigned vb_offset;
1695 void *vb_ptr;
1696 uint32_t i = 0;
1697 uint32_t count = velems->count;
1698 uint64_t va;
1699
1700 /* allocate some descriptor state for vertex buffers */
1701 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1702 &vb_offset, &vb_ptr))
1703 return false;
1704
1705 for (i = 0; i < count; i++) {
1706 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1707 uint32_t offset;
1708 int vb = velems->binding[i];
1709 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1710 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1711
1712 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1713 va = device->ws->buffer_get_va(buffer->bo);
1714
1715 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1716 va += offset + buffer->offset;
1717 desc[0] = va;
1718 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1719 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1720 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1721 else
1722 desc[2] = buffer->size - offset;
1723 desc[3] = velems->rsrc_word3[i];
1724 }
1725
1726 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1727 va += vb_offset;
1728
1729 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1730 AC_UD_VS_VERTEX_BUFFERS, va);
1731 }
1732 cmd_buffer->state.vb_dirty = false;
1733
1734 return true;
1735 }
1736
1737 static void
1738 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1739 bool indexed_draw, bool instanced_draw,
1740 bool indirect_draw,
1741 uint32_t draw_vertex_count)
1742 {
1743 uint32_t ia_multi_vgt_param;
1744
1745 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1746 cmd_buffer->cs, 4096);
1747
1748 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1749 return;
1750
1751 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1752 radv_emit_graphics_pipeline(cmd_buffer);
1753
1754 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1755 radv_emit_framebuffer_state(cmd_buffer);
1756
1757 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1758 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1759 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1760 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1761 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1762 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1763 else
1764 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1765 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1766 }
1767
1768 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1769
1770 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1771
1772 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1773 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1774 VK_SHADER_STAGE_ALL_GRAPHICS);
1775
1776 assert(cmd_buffer->cs->cdw <= cdw_max);
1777
1778 si_emit_cache_flush(cmd_buffer);
1779 }
1780
1781 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1782 VkPipelineStageFlags src_stage_mask)
1783 {
1784 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1785 VK_PIPELINE_STAGE_TRANSFER_BIT |
1786 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1787 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1788 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1789 }
1790
1791 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1792 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1793 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1794 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1795 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1796 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1797 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1798 VK_PIPELINE_STAGE_TRANSFER_BIT |
1799 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1800 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1801 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1802 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1803 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1804 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1805 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1806 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1807 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1808 }
1809 }
1810
1811 static enum radv_cmd_flush_bits
1812 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1813 VkAccessFlags src_flags)
1814 {
1815 enum radv_cmd_flush_bits flush_bits = 0;
1816 uint32_t b;
1817 for_each_bit(b, src_flags) {
1818 switch ((VkAccessFlagBits)(1 << b)) {
1819 case VK_ACCESS_SHADER_WRITE_BIT:
1820 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1821 break;
1822 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1823 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1824 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1825 break;
1826 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1827 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1828 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1829 break;
1830 case VK_ACCESS_TRANSFER_WRITE_BIT:
1831 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1832 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1833 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1834 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1835 RADV_CMD_FLAG_INV_GLOBAL_L2;
1836 break;
1837 default:
1838 break;
1839 }
1840 }
1841 return flush_bits;
1842 }
1843
1844 static enum radv_cmd_flush_bits
1845 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1846 VkAccessFlags dst_flags,
1847 struct radv_image *image)
1848 {
1849 enum radv_cmd_flush_bits flush_bits = 0;
1850 uint32_t b;
1851 for_each_bit(b, dst_flags) {
1852 switch ((VkAccessFlagBits)(1 << b)) {
1853 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1854 case VK_ACCESS_INDEX_READ_BIT:
1855 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1856 break;
1857 case VK_ACCESS_UNIFORM_READ_BIT:
1858 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1859 break;
1860 case VK_ACCESS_SHADER_READ_BIT:
1861 case VK_ACCESS_TRANSFER_READ_BIT:
1862 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1863 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1864 RADV_CMD_FLAG_INV_GLOBAL_L2;
1865 break;
1866 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1867 /* TODO: change to image && when the image gets passed
1868 * through from the subpass. */
1869 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1870 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1871 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1872 break;
1873 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1874 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1875 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1876 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1877 break;
1878 default:
1879 break;
1880 }
1881 }
1882 return flush_bits;
1883 }
1884
1885 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1886 {
1887 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1888 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1889 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1890 NULL);
1891 }
1892
1893 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1894 VkAttachmentReference att)
1895 {
1896 unsigned idx = att.attachment;
1897 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1898 VkImageSubresourceRange range;
1899 range.aspectMask = 0;
1900 range.baseMipLevel = view->base_mip;
1901 range.levelCount = 1;
1902 range.baseArrayLayer = view->base_layer;
1903 range.layerCount = cmd_buffer->state.framebuffer->layers;
1904
1905 radv_handle_image_transition(cmd_buffer,
1906 view->image,
1907 cmd_buffer->state.attachments[idx].current_layout,
1908 att.layout, 0, 0, &range,
1909 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1910
1911 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1912
1913
1914 }
1915
1916 void
1917 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1918 const struct radv_subpass *subpass, bool transitions)
1919 {
1920 if (transitions) {
1921 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1922
1923 for (unsigned i = 0; i < subpass->color_count; ++i) {
1924 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1925 radv_handle_subpass_image_transition(cmd_buffer,
1926 subpass->color_attachments[i]);
1927 }
1928
1929 for (unsigned i = 0; i < subpass->input_count; ++i) {
1930 radv_handle_subpass_image_transition(cmd_buffer,
1931 subpass->input_attachments[i]);
1932 }
1933
1934 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1935 radv_handle_subpass_image_transition(cmd_buffer,
1936 subpass->depth_stencil_attachment);
1937 }
1938 }
1939
1940 cmd_buffer->state.subpass = subpass;
1941
1942 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1943 }
1944
1945 static VkResult
1946 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1947 struct radv_render_pass *pass,
1948 const VkRenderPassBeginInfo *info)
1949 {
1950 struct radv_cmd_state *state = &cmd_buffer->state;
1951
1952 if (pass->attachment_count == 0) {
1953 state->attachments = NULL;
1954 return VK_SUCCESS;
1955 }
1956
1957 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1958 pass->attachment_count *
1959 sizeof(state->attachments[0]),
1960 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1961 if (state->attachments == NULL) {
1962 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1963 return cmd_buffer->record_result;
1964 }
1965
1966 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1967 struct radv_render_pass_attachment *att = &pass->attachments[i];
1968 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1969 VkImageAspectFlags clear_aspects = 0;
1970
1971 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1972 /* color attachment */
1973 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1974 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1975 }
1976 } else {
1977 /* depthstencil attachment */
1978 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1979 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1980 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1981 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1982 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1983 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1984 }
1985 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1986 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1987 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1988 }
1989 }
1990
1991 state->attachments[i].pending_clear_aspects = clear_aspects;
1992 state->attachments[i].cleared_views = 0;
1993 if (clear_aspects && info) {
1994 assert(info->clearValueCount > i);
1995 state->attachments[i].clear_value = info->pClearValues[i];
1996 }
1997
1998 state->attachments[i].current_layout = att->initial_layout;
1999 }
2000
2001 return VK_SUCCESS;
2002 }
2003
2004 VkResult radv_AllocateCommandBuffers(
2005 VkDevice _device,
2006 const VkCommandBufferAllocateInfo *pAllocateInfo,
2007 VkCommandBuffer *pCommandBuffers)
2008 {
2009 RADV_FROM_HANDLE(radv_device, device, _device);
2010 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2011
2012 VkResult result = VK_SUCCESS;
2013 uint32_t i;
2014
2015 memset(pCommandBuffers, 0,
2016 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2017
2018 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2019
2020 if (!list_empty(&pool->free_cmd_buffers)) {
2021 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2022
2023 list_del(&cmd_buffer->pool_link);
2024 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2025
2026 result = radv_reset_cmd_buffer(cmd_buffer);
2027 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2028 cmd_buffer->level = pAllocateInfo->level;
2029
2030 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2031 } else {
2032 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2033 &pCommandBuffers[i]);
2034 }
2035 if (result != VK_SUCCESS)
2036 break;
2037 }
2038
2039 if (result != VK_SUCCESS)
2040 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2041 i, pCommandBuffers);
2042
2043 return result;
2044 }
2045
2046 void radv_FreeCommandBuffers(
2047 VkDevice device,
2048 VkCommandPool commandPool,
2049 uint32_t commandBufferCount,
2050 const VkCommandBuffer *pCommandBuffers)
2051 {
2052 for (uint32_t i = 0; i < commandBufferCount; i++) {
2053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2054
2055 if (cmd_buffer) {
2056 if (cmd_buffer->pool) {
2057 list_del(&cmd_buffer->pool_link);
2058 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2059 } else
2060 radv_cmd_buffer_destroy(cmd_buffer);
2061
2062 }
2063 }
2064 }
2065
2066 VkResult radv_ResetCommandBuffer(
2067 VkCommandBuffer commandBuffer,
2068 VkCommandBufferResetFlags flags)
2069 {
2070 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2071 return radv_reset_cmd_buffer(cmd_buffer);
2072 }
2073
2074 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2075 {
2076 struct radv_device *device = cmd_buffer->device;
2077 if (device->gfx_init) {
2078 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
2079 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2080 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2081 radeon_emit(cmd_buffer->cs, va);
2082 radeon_emit(cmd_buffer->cs, va >> 32);
2083 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2084 } else
2085 si_init_config(cmd_buffer);
2086 }
2087
2088 VkResult radv_BeginCommandBuffer(
2089 VkCommandBuffer commandBuffer,
2090 const VkCommandBufferBeginInfo *pBeginInfo)
2091 {
2092 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2093 VkResult result;
2094
2095 result = radv_reset_cmd_buffer(cmd_buffer);
2096 if (result != VK_SUCCESS)
2097 return result;
2098
2099 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2100 cmd_buffer->state.last_primitive_reset_en = -1;
2101 cmd_buffer->usage_flags = pBeginInfo->flags;
2102
2103 /* setup initial configuration into command buffer */
2104 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2105 switch (cmd_buffer->queue_family_index) {
2106 case RADV_QUEUE_GENERAL:
2107 emit_gfx_buffer_state(cmd_buffer);
2108 radv_set_db_count_control(cmd_buffer);
2109 break;
2110 case RADV_QUEUE_COMPUTE:
2111 si_init_compute(cmd_buffer);
2112 break;
2113 case RADV_QUEUE_TRANSFER:
2114 default:
2115 break;
2116 }
2117 }
2118
2119 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2120 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2121 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2122
2123 struct radv_subpass *subpass =
2124 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2125
2126 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2127 if (result != VK_SUCCESS)
2128 return result;
2129
2130 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2131 }
2132
2133 radv_cmd_buffer_trace_emit(cmd_buffer);
2134 return result;
2135 }
2136
2137 void radv_CmdBindVertexBuffers(
2138 VkCommandBuffer commandBuffer,
2139 uint32_t firstBinding,
2140 uint32_t bindingCount,
2141 const VkBuffer* pBuffers,
2142 const VkDeviceSize* pOffsets)
2143 {
2144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2145 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2146
2147 /* We have to defer setting up vertex buffer since we need the buffer
2148 * stride from the pipeline. */
2149
2150 assert(firstBinding + bindingCount <= MAX_VBS);
2151 for (uint32_t i = 0; i < bindingCount; i++) {
2152 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2153 vb[firstBinding + i].offset = pOffsets[i];
2154 }
2155
2156 cmd_buffer->state.vb_dirty = true;
2157 }
2158
2159 void radv_CmdBindIndexBuffer(
2160 VkCommandBuffer commandBuffer,
2161 VkBuffer buffer,
2162 VkDeviceSize offset,
2163 VkIndexType indexType)
2164 {
2165 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2166 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2167
2168 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2169 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2170 cmd_buffer->state.index_va += index_buffer->offset + offset;
2171
2172 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2173 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2174 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2175 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2176 }
2177
2178
2179 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2180 struct radv_descriptor_set *set,
2181 unsigned idx)
2182 {
2183 struct radeon_winsys *ws = cmd_buffer->device->ws;
2184
2185 cmd_buffer->state.descriptors[idx] = set;
2186 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2187 if (!set)
2188 return;
2189
2190 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2191
2192 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2193 if (set->descriptors[j])
2194 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2195
2196 if(set->bo)
2197 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2198 }
2199
2200 void radv_CmdBindDescriptorSets(
2201 VkCommandBuffer commandBuffer,
2202 VkPipelineBindPoint pipelineBindPoint,
2203 VkPipelineLayout _layout,
2204 uint32_t firstSet,
2205 uint32_t descriptorSetCount,
2206 const VkDescriptorSet* pDescriptorSets,
2207 uint32_t dynamicOffsetCount,
2208 const uint32_t* pDynamicOffsets)
2209 {
2210 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2211 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2212 unsigned dyn_idx = 0;
2213
2214 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2215 unsigned idx = i + firstSet;
2216 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2217 radv_bind_descriptor_set(cmd_buffer, set, idx);
2218
2219 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2220 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2221 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2222 assert(dyn_idx < dynamicOffsetCount);
2223
2224 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2225 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2226 dst[0] = va;
2227 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2228 dst[2] = range->size;
2229 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2230 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2231 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2232 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2233 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2234 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2235 cmd_buffer->push_constant_stages |=
2236 set->layout->dynamic_shader_stages;
2237 }
2238 }
2239 }
2240
2241 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2242 struct radv_descriptor_set *set,
2243 struct radv_descriptor_set_layout *layout)
2244 {
2245 set->size = layout->size;
2246 set->layout = layout;
2247
2248 if (cmd_buffer->push_descriptors.capacity < set->size) {
2249 size_t new_size = MAX2(set->size, 1024);
2250 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2251 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2252
2253 free(set->mapped_ptr);
2254 set->mapped_ptr = malloc(new_size);
2255
2256 if (!set->mapped_ptr) {
2257 cmd_buffer->push_descriptors.capacity = 0;
2258 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2259 return false;
2260 }
2261
2262 cmd_buffer->push_descriptors.capacity = new_size;
2263 }
2264
2265 return true;
2266 }
2267
2268 void radv_meta_push_descriptor_set(
2269 struct radv_cmd_buffer* cmd_buffer,
2270 VkPipelineBindPoint pipelineBindPoint,
2271 VkPipelineLayout _layout,
2272 uint32_t set,
2273 uint32_t descriptorWriteCount,
2274 const VkWriteDescriptorSet* pDescriptorWrites)
2275 {
2276 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2277 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2278 unsigned bo_offset;
2279
2280 assert(set == 0);
2281 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2282
2283 push_set->size = layout->set[set].layout->size;
2284 push_set->layout = layout->set[set].layout;
2285
2286 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2287 &bo_offset,
2288 (void**) &push_set->mapped_ptr))
2289 return;
2290
2291 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2292 push_set->va += bo_offset;
2293
2294 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2295 radv_descriptor_set_to_handle(push_set),
2296 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2297
2298 cmd_buffer->state.descriptors[set] = push_set;
2299 cmd_buffer->state.descriptors_dirty |= (1u << set);
2300 }
2301
2302 void radv_CmdPushDescriptorSetKHR(
2303 VkCommandBuffer commandBuffer,
2304 VkPipelineBindPoint pipelineBindPoint,
2305 VkPipelineLayout _layout,
2306 uint32_t set,
2307 uint32_t descriptorWriteCount,
2308 const VkWriteDescriptorSet* pDescriptorWrites)
2309 {
2310 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2311 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2312 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2313
2314 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2315
2316 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2317 return;
2318
2319 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2320 radv_descriptor_set_to_handle(push_set),
2321 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2322
2323 cmd_buffer->state.descriptors[set] = push_set;
2324 cmd_buffer->state.descriptors_dirty |= (1u << set);
2325 cmd_buffer->state.push_descriptors_dirty = true;
2326 }
2327
2328 void radv_CmdPushDescriptorSetWithTemplateKHR(
2329 VkCommandBuffer commandBuffer,
2330 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2331 VkPipelineLayout _layout,
2332 uint32_t set,
2333 const void* pData)
2334 {
2335 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2336 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2337 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2338
2339 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2340
2341 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2342 return;
2343
2344 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2345 descriptorUpdateTemplate, pData);
2346
2347 cmd_buffer->state.descriptors[set] = push_set;
2348 cmd_buffer->state.descriptors_dirty |= (1u << set);
2349 cmd_buffer->state.push_descriptors_dirty = true;
2350 }
2351
2352 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2353 VkPipelineLayout layout,
2354 VkShaderStageFlags stageFlags,
2355 uint32_t offset,
2356 uint32_t size,
2357 const void* pValues)
2358 {
2359 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2360 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2361 cmd_buffer->push_constant_stages |= stageFlags;
2362 }
2363
2364 VkResult radv_EndCommandBuffer(
2365 VkCommandBuffer commandBuffer)
2366 {
2367 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2368
2369 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2370 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2371 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2372 si_emit_cache_flush(cmd_buffer);
2373 }
2374
2375 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2376 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2377
2378 return cmd_buffer->record_result;
2379 }
2380
2381 static void
2382 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2383 {
2384 struct radeon_winsys *ws = cmd_buffer->device->ws;
2385 struct radv_shader_variant *compute_shader;
2386 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2387 uint64_t va;
2388
2389 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2390 return;
2391
2392 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2393
2394 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2395 va = ws->buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2396
2397 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2398 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2399
2400 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2401 cmd_buffer->cs, 16);
2402
2403 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2404 radeon_emit(cmd_buffer->cs, va >> 8);
2405 radeon_emit(cmd_buffer->cs, va >> 40);
2406
2407 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2408 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2409 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2410
2411
2412 cmd_buffer->compute_scratch_size_needed =
2413 MAX2(cmd_buffer->compute_scratch_size_needed,
2414 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2415
2416 /* change these once we have scratch support */
2417 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2418 S_00B860_WAVES(pipeline->max_waves) |
2419 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2420
2421 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2422 radeon_emit(cmd_buffer->cs,
2423 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2424 radeon_emit(cmd_buffer->cs,
2425 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2426 radeon_emit(cmd_buffer->cs,
2427 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2428
2429 assert(cmd_buffer->cs->cdw <= cdw_max);
2430 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2431 }
2432
2433 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2434 {
2435 for (unsigned i = 0; i < MAX_SETS; i++) {
2436 if (cmd_buffer->state.descriptors[i])
2437 cmd_buffer->state.descriptors_dirty |= (1u << i);
2438 }
2439 }
2440
2441 void radv_CmdBindPipeline(
2442 VkCommandBuffer commandBuffer,
2443 VkPipelineBindPoint pipelineBindPoint,
2444 VkPipeline _pipeline)
2445 {
2446 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2447 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2448
2449 radv_mark_descriptor_sets_dirty(cmd_buffer);
2450
2451 switch (pipelineBindPoint) {
2452 case VK_PIPELINE_BIND_POINT_COMPUTE:
2453 cmd_buffer->state.compute_pipeline = pipeline;
2454 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2455 break;
2456 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2457 cmd_buffer->state.pipeline = pipeline;
2458 if (!pipeline)
2459 break;
2460
2461 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2462 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2463
2464 /* Apply the dynamic state from the pipeline */
2465 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2466 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2467 &pipeline->dynamic_state,
2468 pipeline->dynamic_state_mask);
2469
2470 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2471 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2472 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2473 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2474
2475 if (radv_pipeline_has_tess(pipeline))
2476 cmd_buffer->tess_rings_needed = true;
2477
2478 if (radv_pipeline_has_gs(pipeline)) {
2479 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2480 AC_UD_SCRATCH_RING_OFFSETS);
2481 if (cmd_buffer->ring_offsets_idx == -1)
2482 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2483 else if (loc->sgpr_idx != -1)
2484 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2485 }
2486 break;
2487 default:
2488 assert(!"invalid bind point");
2489 break;
2490 }
2491 }
2492
2493 void radv_CmdSetViewport(
2494 VkCommandBuffer commandBuffer,
2495 uint32_t firstViewport,
2496 uint32_t viewportCount,
2497 const VkViewport* pViewports)
2498 {
2499 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2500 const uint32_t total_count = firstViewport + viewportCount;
2501
2502 assert(firstViewport < MAX_VIEWPORTS);
2503 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2504
2505 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2506 pViewports, viewportCount * sizeof(*pViewports));
2507
2508 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2509 }
2510
2511 void radv_CmdSetScissor(
2512 VkCommandBuffer commandBuffer,
2513 uint32_t firstScissor,
2514 uint32_t scissorCount,
2515 const VkRect2D* pScissors)
2516 {
2517 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2518 const uint32_t total_count = firstScissor + scissorCount;
2519
2520 assert(firstScissor < MAX_SCISSORS);
2521 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2522
2523 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2524 pScissors, scissorCount * sizeof(*pScissors));
2525 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2526 }
2527
2528 void radv_CmdSetLineWidth(
2529 VkCommandBuffer commandBuffer,
2530 float lineWidth)
2531 {
2532 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2533 cmd_buffer->state.dynamic.line_width = lineWidth;
2534 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2535 }
2536
2537 void radv_CmdSetDepthBias(
2538 VkCommandBuffer commandBuffer,
2539 float depthBiasConstantFactor,
2540 float depthBiasClamp,
2541 float depthBiasSlopeFactor)
2542 {
2543 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2544
2545 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2546 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2547 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2548
2549 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2550 }
2551
2552 void radv_CmdSetBlendConstants(
2553 VkCommandBuffer commandBuffer,
2554 const float blendConstants[4])
2555 {
2556 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2557
2558 memcpy(cmd_buffer->state.dynamic.blend_constants,
2559 blendConstants, sizeof(float) * 4);
2560
2561 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2562 }
2563
2564 void radv_CmdSetDepthBounds(
2565 VkCommandBuffer commandBuffer,
2566 float minDepthBounds,
2567 float maxDepthBounds)
2568 {
2569 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2570
2571 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2572 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2573
2574 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2575 }
2576
2577 void radv_CmdSetStencilCompareMask(
2578 VkCommandBuffer commandBuffer,
2579 VkStencilFaceFlags faceMask,
2580 uint32_t compareMask)
2581 {
2582 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2583
2584 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2585 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2586 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2587 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2588
2589 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2590 }
2591
2592 void radv_CmdSetStencilWriteMask(
2593 VkCommandBuffer commandBuffer,
2594 VkStencilFaceFlags faceMask,
2595 uint32_t writeMask)
2596 {
2597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2598
2599 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2600 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2601 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2602 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2603
2604 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2605 }
2606
2607 void radv_CmdSetStencilReference(
2608 VkCommandBuffer commandBuffer,
2609 VkStencilFaceFlags faceMask,
2610 uint32_t reference)
2611 {
2612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2613
2614 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2615 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2616 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2617 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2618
2619 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2620 }
2621
2622 void radv_CmdExecuteCommands(
2623 VkCommandBuffer commandBuffer,
2624 uint32_t commandBufferCount,
2625 const VkCommandBuffer* pCmdBuffers)
2626 {
2627 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2628
2629 /* Emit pending flushes on primary prior to executing secondary */
2630 si_emit_cache_flush(primary);
2631
2632 for (uint32_t i = 0; i < commandBufferCount; i++) {
2633 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2634
2635 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2636 secondary->scratch_size_needed);
2637 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2638 secondary->compute_scratch_size_needed);
2639
2640 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2641 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2642 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2643 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2644 if (secondary->tess_rings_needed)
2645 primary->tess_rings_needed = true;
2646 if (secondary->sample_positions_needed)
2647 primary->sample_positions_needed = true;
2648
2649 if (secondary->ring_offsets_idx != -1) {
2650 if (primary->ring_offsets_idx == -1)
2651 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2652 else
2653 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2654 }
2655 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2656
2657 primary->state.emitted_pipeline = secondary->state.emitted_pipeline;
2658 primary->state.emitted_compute_pipeline = secondary->state.emitted_compute_pipeline;
2659 primary->state.last_primitive_reset_en = secondary->state.last_primitive_reset_en;
2660 primary->state.last_primitive_reset_index = secondary->state.last_primitive_reset_index;
2661 }
2662
2663 /* if we execute secondary we need to mark some stuff to reset dirty */
2664 if (commandBufferCount) {
2665 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2666 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2667 radv_mark_descriptor_sets_dirty(primary);
2668 }
2669 }
2670
2671 VkResult radv_CreateCommandPool(
2672 VkDevice _device,
2673 const VkCommandPoolCreateInfo* pCreateInfo,
2674 const VkAllocationCallbacks* pAllocator,
2675 VkCommandPool* pCmdPool)
2676 {
2677 RADV_FROM_HANDLE(radv_device, device, _device);
2678 struct radv_cmd_pool *pool;
2679
2680 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2681 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2682 if (pool == NULL)
2683 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2684
2685 if (pAllocator)
2686 pool->alloc = *pAllocator;
2687 else
2688 pool->alloc = device->alloc;
2689
2690 list_inithead(&pool->cmd_buffers);
2691 list_inithead(&pool->free_cmd_buffers);
2692
2693 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2694
2695 *pCmdPool = radv_cmd_pool_to_handle(pool);
2696
2697 return VK_SUCCESS;
2698
2699 }
2700
2701 void radv_DestroyCommandPool(
2702 VkDevice _device,
2703 VkCommandPool commandPool,
2704 const VkAllocationCallbacks* pAllocator)
2705 {
2706 RADV_FROM_HANDLE(radv_device, device, _device);
2707 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2708
2709 if (!pool)
2710 return;
2711
2712 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2713 &pool->cmd_buffers, pool_link) {
2714 radv_cmd_buffer_destroy(cmd_buffer);
2715 }
2716
2717 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2718 &pool->free_cmd_buffers, pool_link) {
2719 radv_cmd_buffer_destroy(cmd_buffer);
2720 }
2721
2722 vk_free2(&device->alloc, pAllocator, pool);
2723 }
2724
2725 VkResult radv_ResetCommandPool(
2726 VkDevice device,
2727 VkCommandPool commandPool,
2728 VkCommandPoolResetFlags flags)
2729 {
2730 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2731 VkResult result;
2732
2733 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2734 &pool->cmd_buffers, pool_link) {
2735 result = radv_reset_cmd_buffer(cmd_buffer);
2736 if (result != VK_SUCCESS)
2737 return result;
2738 }
2739
2740 return VK_SUCCESS;
2741 }
2742
2743 void radv_TrimCommandPoolKHR(
2744 VkDevice device,
2745 VkCommandPool commandPool,
2746 VkCommandPoolTrimFlagsKHR flags)
2747 {
2748 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2749
2750 if (!pool)
2751 return;
2752
2753 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2754 &pool->free_cmd_buffers, pool_link) {
2755 radv_cmd_buffer_destroy(cmd_buffer);
2756 }
2757 }
2758
2759 void radv_CmdBeginRenderPass(
2760 VkCommandBuffer commandBuffer,
2761 const VkRenderPassBeginInfo* pRenderPassBegin,
2762 VkSubpassContents contents)
2763 {
2764 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2765 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2766 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2767
2768 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2769 cmd_buffer->cs, 2048);
2770 MAYBE_UNUSED VkResult result;
2771
2772 cmd_buffer->state.framebuffer = framebuffer;
2773 cmd_buffer->state.pass = pass;
2774 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2775
2776 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2777 if (result != VK_SUCCESS)
2778 return;
2779
2780 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2781 assert(cmd_buffer->cs->cdw <= cdw_max);
2782
2783 radv_cmd_buffer_clear_subpass(cmd_buffer);
2784 }
2785
2786 void radv_CmdNextSubpass(
2787 VkCommandBuffer commandBuffer,
2788 VkSubpassContents contents)
2789 {
2790 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2791
2792 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2793
2794 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2795 2048);
2796
2797 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2798 radv_cmd_buffer_clear_subpass(cmd_buffer);
2799 }
2800
2801 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2802 {
2803 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2804 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2805 if (!pipeline->shaders[stage])
2806 continue;
2807 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2808 if (loc->sgpr_idx == -1)
2809 continue;
2810 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2811 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2812
2813 }
2814 if (pipeline->gs_copy_shader) {
2815 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2816 if (loc->sgpr_idx != -1) {
2817 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2818 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2819 }
2820 }
2821 }
2822
2823 static void
2824 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2825 uint32_t vertex_count)
2826 {
2827 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2828 radeon_emit(cmd_buffer->cs, vertex_count);
2829 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2830 S_0287F0_USE_OPAQUE(0));
2831 }
2832
2833 void radv_CmdDraw(
2834 VkCommandBuffer commandBuffer,
2835 uint32_t vertexCount,
2836 uint32_t instanceCount,
2837 uint32_t firstVertex,
2838 uint32_t firstInstance)
2839 {
2840 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2841
2842 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2843
2844 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2845
2846 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2847 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2848 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2849 radeon_emit(cmd_buffer->cs, firstVertex);
2850 radeon_emit(cmd_buffer->cs, firstInstance);
2851 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2852 radeon_emit(cmd_buffer->cs, 0);
2853
2854 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2855 radeon_emit(cmd_buffer->cs, instanceCount);
2856
2857 if (!cmd_buffer->state.subpass->view_mask) {
2858 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2859 } else {
2860 unsigned i;
2861 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2862 radv_emit_view_index(cmd_buffer, i);
2863
2864 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2865 }
2866 }
2867
2868 assert(cmd_buffer->cs->cdw <= cdw_max);
2869
2870 radv_cmd_buffer_after_draw(cmd_buffer);
2871 }
2872
2873
2874 static void
2875 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2876 uint64_t index_va,
2877 uint32_t index_count)
2878 {
2879 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2880 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2881 radeon_emit(cmd_buffer->cs, index_va);
2882 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2883 radeon_emit(cmd_buffer->cs, index_count);
2884 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2885 }
2886
2887 void radv_CmdDrawIndexed(
2888 VkCommandBuffer commandBuffer,
2889 uint32_t indexCount,
2890 uint32_t instanceCount,
2891 uint32_t firstIndex,
2892 int32_t vertexOffset,
2893 uint32_t firstInstance)
2894 {
2895 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2896 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2897 uint64_t index_va;
2898
2899 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2900
2901 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2902
2903 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2904 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2905 2, cmd_buffer->state.index_type);
2906 } else {
2907 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2908 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2909 }
2910
2911 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2912 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2913 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2914 radeon_emit(cmd_buffer->cs, vertexOffset);
2915 radeon_emit(cmd_buffer->cs, firstInstance);
2916 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2917 radeon_emit(cmd_buffer->cs, 0);
2918
2919 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2920 radeon_emit(cmd_buffer->cs, instanceCount);
2921
2922 index_va = cmd_buffer->state.index_va;
2923 index_va += firstIndex * index_size;
2924 if (!cmd_buffer->state.subpass->view_mask) {
2925 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2926 } else {
2927 unsigned i;
2928 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2929 radv_emit_view_index(cmd_buffer, i);
2930
2931 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2932 }
2933 }
2934
2935 assert(cmd_buffer->cs->cdw <= cdw_max);
2936 radv_cmd_buffer_after_draw(cmd_buffer);
2937 }
2938
2939 static void
2940 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2941 bool indexed,
2942 uint32_t draw_count,
2943 uint64_t count_va,
2944 uint32_t stride)
2945 {
2946 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2947 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2948 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2949 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2950 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2951 assert(base_reg);
2952
2953 if (draw_count == 1 && !count_va && !draw_id_enable) {
2954 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2955 PKT3_DRAW_INDIRECT, 3, false));
2956 radeon_emit(cs, 0);
2957 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2958 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2959 radeon_emit(cs, di_src_sel);
2960 } else {
2961 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2962 PKT3_DRAW_INDIRECT_MULTI,
2963 8, false));
2964 radeon_emit(cs, 0);
2965 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2966 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2967 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2968 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2969 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2970 radeon_emit(cs, draw_count); /* count */
2971 radeon_emit(cs, count_va); /* count_addr */
2972 radeon_emit(cs, count_va >> 32);
2973 radeon_emit(cs, stride); /* stride */
2974 radeon_emit(cs, di_src_sel);
2975 }
2976 }
2977
2978 static void
2979 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2980 VkBuffer _buffer,
2981 VkDeviceSize offset,
2982 VkBuffer _count_buffer,
2983 VkDeviceSize count_offset,
2984 uint32_t draw_count,
2985 uint32_t stride,
2986 bool indexed)
2987 {
2988 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2989 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2990 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2991
2992 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2993 indirect_va += offset + buffer->offset;
2994 uint64_t count_va = 0;
2995
2996 if (count_buffer) {
2997 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2998 count_va += count_offset + count_buffer->offset;
2999 }
3000
3001 if (!draw_count)
3002 return;
3003
3004 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
3005
3006 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3007 radeon_emit(cs, 1);
3008 radeon_emit(cs, indirect_va);
3009 radeon_emit(cs, indirect_va >> 32);
3010
3011 if (!cmd_buffer->state.subpass->view_mask) {
3012 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3013 } else {
3014 unsigned i;
3015 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3016 radv_emit_view_index(cmd_buffer, i);
3017
3018 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3019 }
3020 }
3021 radv_cmd_buffer_after_draw(cmd_buffer);
3022 }
3023
3024 static void
3025 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
3026 VkBuffer buffer,
3027 VkDeviceSize offset,
3028 VkBuffer countBuffer,
3029 VkDeviceSize countBufferOffset,
3030 uint32_t maxDrawCount,
3031 uint32_t stride)
3032 {
3033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3034 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
3035
3036 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3037 cmd_buffer->cs, 24 * MAX_VIEWS);
3038
3039 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3040 countBuffer, countBufferOffset, maxDrawCount, stride, false);
3041
3042 assert(cmd_buffer->cs->cdw <= cdw_max);
3043 }
3044
3045 static void
3046 radv_cmd_draw_indexed_indirect_count(
3047 VkCommandBuffer commandBuffer,
3048 VkBuffer buffer,
3049 VkDeviceSize offset,
3050 VkBuffer countBuffer,
3051 VkDeviceSize countBufferOffset,
3052 uint32_t maxDrawCount,
3053 uint32_t stride)
3054 {
3055 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3056 uint64_t index_va;
3057 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
3058
3059 index_va = cmd_buffer->state.index_va;
3060
3061 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
3062
3063 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
3064 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
3065
3066 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
3067 radeon_emit(cmd_buffer->cs, index_va);
3068 radeon_emit(cmd_buffer->cs, index_va >> 32);
3069
3070 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
3071 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3072
3073 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3074 countBuffer, countBufferOffset, maxDrawCount, stride, true);
3075
3076 assert(cmd_buffer->cs->cdw <= cdw_max);
3077 }
3078
3079 void radv_CmdDrawIndirect(
3080 VkCommandBuffer commandBuffer,
3081 VkBuffer buffer,
3082 VkDeviceSize offset,
3083 uint32_t drawCount,
3084 uint32_t stride)
3085 {
3086 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3087 VK_NULL_HANDLE, 0, drawCount, stride);
3088 }
3089
3090 void radv_CmdDrawIndexedIndirect(
3091 VkCommandBuffer commandBuffer,
3092 VkBuffer buffer,
3093 VkDeviceSize offset,
3094 uint32_t drawCount,
3095 uint32_t stride)
3096 {
3097 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3098 VK_NULL_HANDLE, 0, drawCount, stride);
3099 }
3100
3101 void radv_CmdDrawIndirectCountAMD(
3102 VkCommandBuffer commandBuffer,
3103 VkBuffer buffer,
3104 VkDeviceSize offset,
3105 VkBuffer countBuffer,
3106 VkDeviceSize countBufferOffset,
3107 uint32_t maxDrawCount,
3108 uint32_t stride)
3109 {
3110 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3111 countBuffer, countBufferOffset,
3112 maxDrawCount, stride);
3113 }
3114
3115 void radv_CmdDrawIndexedIndirectCountAMD(
3116 VkCommandBuffer commandBuffer,
3117 VkBuffer buffer,
3118 VkDeviceSize offset,
3119 VkBuffer countBuffer,
3120 VkDeviceSize countBufferOffset,
3121 uint32_t maxDrawCount,
3122 uint32_t stride)
3123 {
3124 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3125 countBuffer, countBufferOffset,
3126 maxDrawCount, stride);
3127 }
3128
3129 struct radv_dispatch_info {
3130 /**
3131 * Determine the layout of the grid (in block units) to be used.
3132 */
3133 uint32_t blocks[3];
3134
3135 /**
3136 * Whether it's an unaligned compute dispatch.
3137 */
3138 bool unaligned;
3139
3140 /**
3141 * Indirect compute parameters resource.
3142 */
3143 struct radv_buffer *indirect;
3144 uint64_t indirect_offset;
3145 };
3146
3147 static void
3148 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3149 const struct radv_dispatch_info *info)
3150 {
3151 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3152 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3153 struct radeon_winsys *ws = cmd_buffer->device->ws;
3154 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3155 struct ac_userdata_info *loc;
3156 uint8_t grid_used;
3157
3158 grid_used = compute_shader->info.info.cs.grid_components_used;
3159
3160 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3161 AC_UD_CS_GRID_SIZE);
3162
3163 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3164
3165 if (info->indirect) {
3166 uint64_t va = ws->buffer_get_va(info->indirect->bo);
3167
3168 va += info->indirect->offset + info->indirect_offset;
3169
3170 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3171
3172 if (loc->sgpr_idx != -1) {
3173 for (unsigned i = 0; i < grid_used; ++i) {
3174 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3175 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3176 COPY_DATA_DST_SEL(COPY_DATA_REG));
3177 radeon_emit(cs, (va + 4 * i));
3178 radeon_emit(cs, (va + 4 * i) >> 32);
3179 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3180 + loc->sgpr_idx * 4) >> 2) + i);
3181 radeon_emit(cs, 0);
3182 }
3183 }
3184
3185 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3186 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3187 PKT3_SHADER_TYPE_S(1));
3188 radeon_emit(cs, va);
3189 radeon_emit(cs, va >> 32);
3190 radeon_emit(cs, 1);
3191 } else {
3192 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3193 PKT3_SHADER_TYPE_S(1));
3194 radeon_emit(cs, 1);
3195 radeon_emit(cs, va);
3196 radeon_emit(cs, va >> 32);
3197
3198 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3199 PKT3_SHADER_TYPE_S(1));
3200 radeon_emit(cs, 0);
3201 radeon_emit(cs, 1);
3202 }
3203 } else {
3204 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3205 unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
3206
3207 if (info->unaligned) {
3208 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3209 unsigned remainder[3];
3210
3211 /* If aligned, these should be an entire block size,
3212 * not 0.
3213 */
3214 remainder[0] = blocks[0] + cs_block_size[0] -
3215 align_u32_npot(blocks[0], cs_block_size[0]);
3216 remainder[1] = blocks[1] + cs_block_size[1] -
3217 align_u32_npot(blocks[1], cs_block_size[1]);
3218 remainder[2] = blocks[2] + cs_block_size[2] -
3219 align_u32_npot(blocks[2], cs_block_size[2]);
3220
3221 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3222 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3223 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3224
3225 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3226 radeon_emit(cs,
3227 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3228 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3229 radeon_emit(cs,
3230 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3231 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3232 radeon_emit(cs,
3233 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3234 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3235
3236 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3237 }
3238
3239 if (loc->sgpr_idx != -1) {
3240 assert(!loc->indirect);
3241 assert(loc->num_sgprs == grid_used);
3242
3243 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3244 loc->sgpr_idx * 4, grid_used);
3245 radeon_emit(cs, blocks[0]);
3246 if (grid_used > 1)
3247 radeon_emit(cs, blocks[1]);
3248 if (grid_used > 2)
3249 radeon_emit(cs, blocks[2]);
3250 }
3251
3252 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3253 PKT3_SHADER_TYPE_S(1));
3254 radeon_emit(cs, blocks[0]);
3255 radeon_emit(cs, blocks[1]);
3256 radeon_emit(cs, blocks[2]);
3257 radeon_emit(cs, dispatch_initiator);
3258 }
3259
3260 assert(cmd_buffer->cs->cdw <= cdw_max);
3261 }
3262
3263 static void
3264 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3265 const struct radv_dispatch_info *info)
3266 {
3267 radv_emit_compute_pipeline(cmd_buffer);
3268
3269 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3270 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3271 VK_SHADER_STAGE_COMPUTE_BIT);
3272
3273 si_emit_cache_flush(cmd_buffer);
3274
3275 radv_emit_dispatch_packets(cmd_buffer, info);
3276
3277 radv_cmd_buffer_after_draw(cmd_buffer);
3278 }
3279
3280 void radv_CmdDispatch(
3281 VkCommandBuffer commandBuffer,
3282 uint32_t x,
3283 uint32_t y,
3284 uint32_t z)
3285 {
3286 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3287 struct radv_dispatch_info info = {};
3288
3289 info.blocks[0] = x;
3290 info.blocks[1] = y;
3291 info.blocks[2] = z;
3292
3293 radv_dispatch(cmd_buffer, &info);
3294 }
3295
3296 void radv_CmdDispatchIndirect(
3297 VkCommandBuffer commandBuffer,
3298 VkBuffer _buffer,
3299 VkDeviceSize offset)
3300 {
3301 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3302 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3303 struct radv_dispatch_info info = {};
3304
3305 info.indirect = buffer;
3306 info.indirect_offset = offset;
3307
3308 radv_dispatch(cmd_buffer, &info);
3309 }
3310
3311 void radv_unaligned_dispatch(
3312 struct radv_cmd_buffer *cmd_buffer,
3313 uint32_t x,
3314 uint32_t y,
3315 uint32_t z)
3316 {
3317 struct radv_dispatch_info info = {};
3318
3319 info.blocks[0] = x;
3320 info.blocks[1] = y;
3321 info.blocks[2] = z;
3322 info.unaligned = 1;
3323
3324 radv_dispatch(cmd_buffer, &info);
3325 }
3326
3327 void radv_CmdEndRenderPass(
3328 VkCommandBuffer commandBuffer)
3329 {
3330 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3331
3332 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3333
3334 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3335
3336 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3337 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3338 radv_handle_subpass_image_transition(cmd_buffer,
3339 (VkAttachmentReference){i, layout});
3340 }
3341
3342 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3343
3344 cmd_buffer->state.pass = NULL;
3345 cmd_buffer->state.subpass = NULL;
3346 cmd_buffer->state.attachments = NULL;
3347 cmd_buffer->state.framebuffer = NULL;
3348 }
3349
3350 /*
3351 * For HTILE we have the following interesting clear words:
3352 * 0x0000030f: Uncompressed.
3353 * 0xfffffff0: Clear depth to 1.0
3354 * 0x00000000: Clear depth to 0.0
3355 */
3356 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3357 struct radv_image *image,
3358 const VkImageSubresourceRange *range,
3359 uint32_t clear_word)
3360 {
3361 assert(range->baseMipLevel == 0);
3362 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3363 unsigned layer_count = radv_get_layerCount(image, range);
3364 uint64_t size = image->surface.htile_slice_size * layer_count;
3365 uint64_t offset = image->offset + image->htile_offset +
3366 image->surface.htile_slice_size * range->baseArrayLayer;
3367
3368 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3369 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3370
3371 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3372
3373 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3374 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3375 RADV_CMD_FLAG_INV_VMEM_L1 |
3376 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3377 }
3378
3379 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3380 struct radv_image *image,
3381 VkImageLayout src_layout,
3382 VkImageLayout dst_layout,
3383 unsigned src_queue_mask,
3384 unsigned dst_queue_mask,
3385 const VkImageSubresourceRange *range,
3386 VkImageAspectFlags pending_clears)
3387 {
3388 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3389 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3390 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3391 cmd_buffer->state.render_area.extent.width == image->info.width &&
3392 cmd_buffer->state.render_area.extent.height == image->info.height) {
3393 /* The clear will initialize htile. */
3394 return;
3395 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3396 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3397 /* TODO: merge with the clear if applicable */
3398 radv_initialize_htile(cmd_buffer, image, range, 0);
3399 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3400 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3401 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3402 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3403 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3404 VkImageSubresourceRange local_range = *range;
3405 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3406 local_range.baseMipLevel = 0;
3407 local_range.levelCount = 1;
3408
3409 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3410 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3411
3412 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3413
3414 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3415 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3416 }
3417 }
3418
3419 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3420 struct radv_image *image, uint32_t value)
3421 {
3422 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3423 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3424
3425 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3426 image->cmask.size, value);
3427
3428 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3429 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3430 RADV_CMD_FLAG_INV_VMEM_L1 |
3431 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3432 }
3433
3434 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3435 struct radv_image *image,
3436 VkImageLayout src_layout,
3437 VkImageLayout dst_layout,
3438 unsigned src_queue_mask,
3439 unsigned dst_queue_mask,
3440 const VkImageSubresourceRange *range,
3441 VkImageAspectFlags pending_clears)
3442 {
3443 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3444 if (image->fmask.size)
3445 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3446 else
3447 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3448 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3449 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3450 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3451 }
3452 }
3453
3454 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3455 struct radv_image *image, uint32_t value)
3456 {
3457
3458 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3459 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3460
3461 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3462 image->surface.dcc_size, value);
3463
3464 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3465 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3466 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3467 RADV_CMD_FLAG_INV_VMEM_L1 |
3468 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3469 }
3470
3471 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3472 struct radv_image *image,
3473 VkImageLayout src_layout,
3474 VkImageLayout dst_layout,
3475 unsigned src_queue_mask,
3476 unsigned dst_queue_mask,
3477 const VkImageSubresourceRange *range,
3478 VkImageAspectFlags pending_clears)
3479 {
3480 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3481 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3482 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3483 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3484 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3485 }
3486 }
3487
3488 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3489 struct radv_image *image,
3490 VkImageLayout src_layout,
3491 VkImageLayout dst_layout,
3492 uint32_t src_family,
3493 uint32_t dst_family,
3494 const VkImageSubresourceRange *range,
3495 VkImageAspectFlags pending_clears)
3496 {
3497 if (image->exclusive && src_family != dst_family) {
3498 /* This is an acquire or a release operation and there will be
3499 * a corresponding release/acquire. Do the transition in the
3500 * most flexible queue. */
3501
3502 assert(src_family == cmd_buffer->queue_family_index ||
3503 dst_family == cmd_buffer->queue_family_index);
3504
3505 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3506 return;
3507
3508 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3509 (src_family == RADV_QUEUE_GENERAL ||
3510 dst_family == RADV_QUEUE_GENERAL))
3511 return;
3512 }
3513
3514 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3515 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3516
3517 if (image->surface.htile_size)
3518 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3519 dst_layout, src_queue_mask,
3520 dst_queue_mask, range,
3521 pending_clears);
3522
3523 if (image->cmask.size)
3524 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3525 dst_layout, src_queue_mask,
3526 dst_queue_mask, range,
3527 pending_clears);
3528
3529 if (image->surface.dcc_size)
3530 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3531 dst_layout, src_queue_mask,
3532 dst_queue_mask, range,
3533 pending_clears);
3534 }
3535
3536 void radv_CmdPipelineBarrier(
3537 VkCommandBuffer commandBuffer,
3538 VkPipelineStageFlags srcStageMask,
3539 VkPipelineStageFlags destStageMask,
3540 VkBool32 byRegion,
3541 uint32_t memoryBarrierCount,
3542 const VkMemoryBarrier* pMemoryBarriers,
3543 uint32_t bufferMemoryBarrierCount,
3544 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3545 uint32_t imageMemoryBarrierCount,
3546 const VkImageMemoryBarrier* pImageMemoryBarriers)
3547 {
3548 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3549 enum radv_cmd_flush_bits src_flush_bits = 0;
3550 enum radv_cmd_flush_bits dst_flush_bits = 0;
3551
3552 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3553 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3554 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3555 NULL);
3556 }
3557
3558 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3559 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3560 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3561 NULL);
3562 }
3563
3564 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3565 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3566 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3567 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3568 image);
3569 }
3570
3571 radv_stage_flush(cmd_buffer, srcStageMask);
3572 cmd_buffer->state.flush_bits |= src_flush_bits;
3573
3574 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3575 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3576 radv_handle_image_transition(cmd_buffer, image,
3577 pImageMemoryBarriers[i].oldLayout,
3578 pImageMemoryBarriers[i].newLayout,
3579 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3580 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3581 &pImageMemoryBarriers[i].subresourceRange,
3582 0);
3583 }
3584
3585 cmd_buffer->state.flush_bits |= dst_flush_bits;
3586 }
3587
3588
3589 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3590 struct radv_event *event,
3591 VkPipelineStageFlags stageMask,
3592 unsigned value)
3593 {
3594 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3595 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3596
3597 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3598
3599 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3600
3601 /* TODO: this is overkill. Probably should figure something out from
3602 * the stage mask. */
3603
3604 si_cs_emit_write_event_eop(cs,
3605 cmd_buffer->state.predicating,
3606 cmd_buffer->device->physical_device->rad_info.chip_class,
3607 false,
3608 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3609 1, va, 2, value);
3610
3611 assert(cmd_buffer->cs->cdw <= cdw_max);
3612 }
3613
3614 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3615 VkEvent _event,
3616 VkPipelineStageFlags stageMask)
3617 {
3618 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3619 RADV_FROM_HANDLE(radv_event, event, _event);
3620
3621 write_event(cmd_buffer, event, stageMask, 1);
3622 }
3623
3624 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3625 VkEvent _event,
3626 VkPipelineStageFlags stageMask)
3627 {
3628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3629 RADV_FROM_HANDLE(radv_event, event, _event);
3630
3631 write_event(cmd_buffer, event, stageMask, 0);
3632 }
3633
3634 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3635 uint32_t eventCount,
3636 const VkEvent* pEvents,
3637 VkPipelineStageFlags srcStageMask,
3638 VkPipelineStageFlags dstStageMask,
3639 uint32_t memoryBarrierCount,
3640 const VkMemoryBarrier* pMemoryBarriers,
3641 uint32_t bufferMemoryBarrierCount,
3642 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3643 uint32_t imageMemoryBarrierCount,
3644 const VkImageMemoryBarrier* pImageMemoryBarriers)
3645 {
3646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3647 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3648
3649 for (unsigned i = 0; i < eventCount; ++i) {
3650 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3651 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3652
3653 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3654
3655 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3656
3657 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3658 assert(cmd_buffer->cs->cdw <= cdw_max);
3659 }
3660
3661
3662 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3663 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3664
3665 radv_handle_image_transition(cmd_buffer, image,
3666 pImageMemoryBarriers[i].oldLayout,
3667 pImageMemoryBarriers[i].newLayout,
3668 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3669 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3670 &pImageMemoryBarriers[i].subresourceRange,
3671 0);
3672 }
3673
3674 /* TODO: figure out how to do memory barriers without waiting */
3675 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3676 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3677 RADV_CMD_FLAG_INV_VMEM_L1 |
3678 RADV_CMD_FLAG_INV_SMEM_L1;
3679 }