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1d552e265aebad5ca8c853adbd11bd3002af303e
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
207 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
208 cmd_buffer->device = device;
209 cmd_buffer->pool = pool;
210 cmd_buffer->level = level;
211
212 if (pool) {
213 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
214 cmd_buffer->queue_family_index = pool->queue_family_index;
215
216 } else {
217 /* Init the pool_link so we can safefly call list_del when we destroy
218 * the command buffer
219 */
220 list_inithead(&cmd_buffer->pool_link);
221 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
222 }
223
224 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
225
226 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
227 if (!cmd_buffer->cs) {
228 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230 }
231
232 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
233
234 cmd_buffer->upload.offset = 0;
235 cmd_buffer->upload.size = 0;
236 list_inithead(&cmd_buffer->upload.list);
237
238 return VK_SUCCESS;
239 }
240
241 static void
242 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
243 {
244 list_del(&cmd_buffer->pool_link);
245
246 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
247 &cmd_buffer->upload.list, list) {
248 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
249 list_del(&up->list);
250 free(up);
251 }
252
253 if (cmd_buffer->upload.upload_bo)
254 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
255 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
256 free(cmd_buffer->push_descriptors.set.mapped_ptr);
257 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
258 }
259
260 static VkResult
261 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
262 {
263
264 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
265
266 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
267 &cmd_buffer->upload.list, list) {
268 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
269 list_del(&up->list);
270 free(up);
271 }
272
273 cmd_buffer->push_constant_stages = 0;
274 cmd_buffer->scratch_size_needed = 0;
275 cmd_buffer->compute_scratch_size_needed = 0;
276 cmd_buffer->esgs_ring_size_needed = 0;
277 cmd_buffer->gsvs_ring_size_needed = 0;
278 cmd_buffer->tess_rings_needed = false;
279 cmd_buffer->sample_positions_needed = false;
280
281 if (cmd_buffer->upload.upload_bo)
282 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
283 cmd_buffer->upload.upload_bo, 8);
284 cmd_buffer->upload.offset = 0;
285
286 cmd_buffer->record_result = VK_SUCCESS;
287
288 cmd_buffer->ring_offsets_idx = -1;
289
290 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
291 void *fence_ptr;
292 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
293 &cmd_buffer->gfx9_fence_offset,
294 &fence_ptr);
295 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
296 }
297
298 return cmd_buffer->record_result;
299 }
300
301 static bool
302 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
303 uint64_t min_needed)
304 {
305 uint64_t new_size;
306 struct radeon_winsys_bo *bo;
307 struct radv_cmd_buffer_upload *upload;
308 struct radv_device *device = cmd_buffer->device;
309
310 new_size = MAX2(min_needed, 16 * 1024);
311 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
312
313 bo = device->ws->buffer_create(device->ws,
314 new_size, 4096,
315 RADEON_DOMAIN_GTT,
316 RADEON_FLAG_CPU_ACCESS|
317 RADEON_FLAG_NO_INTERPROCESS_SHARING);
318
319 if (!bo) {
320 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
321 return false;
322 }
323
324 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
325 if (cmd_buffer->upload.upload_bo) {
326 upload = malloc(sizeof(*upload));
327
328 if (!upload) {
329 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
330 device->ws->buffer_destroy(bo);
331 return false;
332 }
333
334 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
335 list_add(&upload->list, &cmd_buffer->upload.list);
336 }
337
338 cmd_buffer->upload.upload_bo = bo;
339 cmd_buffer->upload.size = new_size;
340 cmd_buffer->upload.offset = 0;
341 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
342
343 if (!cmd_buffer->upload.map) {
344 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
345 return false;
346 }
347
348 return true;
349 }
350
351 bool
352 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
353 unsigned size,
354 unsigned alignment,
355 unsigned *out_offset,
356 void **ptr)
357 {
358 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
359 if (offset + size > cmd_buffer->upload.size) {
360 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
361 return false;
362 offset = 0;
363 }
364
365 *out_offset = offset;
366 *ptr = cmd_buffer->upload.map + offset;
367
368 cmd_buffer->upload.offset = offset + size;
369 return true;
370 }
371
372 bool
373 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
374 unsigned size, unsigned alignment,
375 const void *data, unsigned *out_offset)
376 {
377 uint8_t *ptr;
378
379 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
380 out_offset, (void **)&ptr))
381 return false;
382
383 if (ptr)
384 memcpy(ptr, data, size);
385
386 return true;
387 }
388
389 static void
390 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
391 unsigned count, const uint32_t *data)
392 {
393 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
394 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
395 S_370_WR_CONFIRM(1) |
396 S_370_ENGINE_SEL(V_370_ME));
397 radeon_emit(cs, va);
398 radeon_emit(cs, va >> 32);
399 radeon_emit_array(cs, data, count);
400 }
401
402 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
403 {
404 struct radv_device *device = cmd_buffer->device;
405 struct radeon_winsys_cs *cs = cmd_buffer->cs;
406 uint64_t va;
407
408 if (!device->trace_bo)
409 return;
410
411 va = radv_buffer_get_va(device->trace_bo);
412 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
413 va += 4;
414
415 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
416
417 ++cmd_buffer->state.trace_id;
418 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
419 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
420 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
421 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
422 }
423
424 static void
425 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
426 {
427 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
428 enum radv_cmd_flush_bits flags;
429
430 /* Force wait for graphics/compute engines to be idle. */
431 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
432 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
433
434 si_cs_emit_cache_flush(cmd_buffer->cs, false,
435 cmd_buffer->device->physical_device->rad_info.chip_class,
436 NULL, 0,
437 radv_cmd_buffer_uses_mec(cmd_buffer),
438 flags);
439 }
440
441 radv_cmd_buffer_trace_emit(cmd_buffer);
442 }
443
444 static void
445 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
446 struct radv_pipeline *pipeline, enum ring_type ring)
447 {
448 struct radv_device *device = cmd_buffer->device;
449 struct radeon_winsys_cs *cs = cmd_buffer->cs;
450 uint32_t data[2];
451 uint64_t va;
452
453 if (!device->trace_bo)
454 return;
455
456 va = radv_buffer_get_va(device->trace_bo);
457
458 switch (ring) {
459 case RING_GFX:
460 va += 8;
461 break;
462 case RING_COMPUTE:
463 va += 16;
464 break;
465 default:
466 assert(!"invalid ring type");
467 }
468
469 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
470 cmd_buffer->cs, 6);
471
472 data[0] = (uintptr_t)pipeline;
473 data[1] = (uintptr_t)pipeline >> 32;
474
475 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
476 radv_emit_write_data_packet(cs, va, 2, data);
477 }
478
479 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
480 struct radv_descriptor_set *set,
481 unsigned idx)
482 {
483 cmd_buffer->descriptors[idx] = set;
484 if (set)
485 cmd_buffer->state.valid_descriptors |= (1u << idx);
486 else
487 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
488 cmd_buffer->state.descriptors_dirty |= (1u << idx);
489
490 }
491
492 static void
493 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
494 {
495 struct radv_device *device = cmd_buffer->device;
496 struct radeon_winsys_cs *cs = cmd_buffer->cs;
497 uint32_t data[MAX_SETS * 2] = {};
498 uint64_t va;
499 unsigned i;
500 va = radv_buffer_get_va(device->trace_bo) + 24;
501
502 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
503 cmd_buffer->cs, 4 + MAX_SETS * 2);
504
505 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
506 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
507 data[i * 2] = (uintptr_t)set;
508 data[i * 2 + 1] = (uintptr_t)set >> 32;
509 }
510
511 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
512 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
513 }
514
515 static void
516 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline)
518 {
519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
520 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
521 8);
522 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
523 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
524
525 if (cmd_buffer->device->physical_device->has_rbplus) {
526
527 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
528 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
529
530 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
531 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
532 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
533 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
534 }
535 }
536
537 static void
538 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
539 struct radv_pipeline *pipeline)
540 {
541 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
542 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
543 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
544
545 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
546 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
547 }
548
549 struct ac_userdata_info *
550 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
551 gl_shader_stage stage,
552 int idx)
553 {
554 if (stage == MESA_SHADER_VERTEX) {
555 if (pipeline->shaders[MESA_SHADER_VERTEX])
556 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
557 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
558 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
559 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
560 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
561 } else if (stage == MESA_SHADER_TESS_EVAL) {
562 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
563 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
564 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
565 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
566 }
567 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580 assert(loc->num_sgprs == 2);
581 assert(!loc->indirect);
582 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
583 radeon_emit(cmd_buffer->cs, va);
584 radeon_emit(cmd_buffer->cs, va >> 32);
585 }
586
587 static void
588 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
589 struct radv_pipeline *pipeline)
590 {
591 int num_samples = pipeline->graphics.ms.num_samples;
592 struct radv_multisample_state *ms = &pipeline->graphics.ms;
593 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
594
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
596 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
597 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
598
599 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
600 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
601
602 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
603 return;
604
605 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
606 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
607 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
608
609 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
610
611 /* GFX9: Flush DFSM when the AA mode changes. */
612 if (cmd_buffer->device->dfsm_allowed) {
613 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
614 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
615 }
616 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
617 uint32_t offset;
618 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
619 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
620 if (loc->sgpr_idx == -1)
621 return;
622 assert(loc->num_sgprs == 1);
623 assert(!loc->indirect);
624 switch (num_samples) {
625 default:
626 offset = 0;
627 break;
628 case 2:
629 offset = 1;
630 break;
631 case 4:
632 offset = 3;
633 break;
634 case 8:
635 offset = 7;
636 break;
637 case 16:
638 offset = 15;
639 break;
640 }
641
642 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
643 cmd_buffer->sample_positions_needed = true;
644 }
645 }
646
647 static void
648 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline)
650 {
651 struct radv_raster_state *raster = &pipeline->graphics.raster;
652
653 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
654 raster->pa_cl_clip_cntl);
655 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
656 raster->spi_interp_control);
657 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
658 raster->pa_su_vtx_cntl);
659 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
660 raster->pa_su_sc_mode_cntl);
661 }
662
663 static inline void
664 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
665 unsigned size)
666 {
667 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
668 si_cp_dma_prefetch(cmd_buffer, va, size);
669 }
670
671 static void
672 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_shader_variant *shader)
674 {
675 struct radeon_winsys *ws = cmd_buffer->device->ws;
676 struct radeon_winsys_cs *cs = cmd_buffer->cs;
677 uint64_t va;
678
679 if (!shader)
680 return;
681
682 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
683
684 radv_cs_add_buffer(ws, cs, shader->bo, 8);
685 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
686 }
687
688 static void
689 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
690 struct radv_pipeline *pipeline)
691 {
692 radv_emit_shader_prefetch(cmd_buffer,
693 pipeline->shaders[MESA_SHADER_VERTEX]);
694 radv_emit_shader_prefetch(cmd_buffer,
695 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
696 radv_emit_shader_prefetch(cmd_buffer,
697 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_GEOMETRY]);
700 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_FRAGMENT]);
703 }
704
705 static void
706 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
707 struct radv_pipeline *pipeline,
708 struct radv_shader_variant *shader)
709 {
710 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
711
712 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
713 pipeline->graphics.vs.spi_vs_out_config);
714
715 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
716 pipeline->graphics.vs.spi_shader_pos_format);
717
718 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
719 radeon_emit(cmd_buffer->cs, va >> 8);
720 radeon_emit(cmd_buffer->cs, va >> 40);
721 radeon_emit(cmd_buffer->cs, shader->rsrc1);
722 radeon_emit(cmd_buffer->cs, shader->rsrc2);
723
724 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
725 S_028818_VTX_W0_FMT(1) |
726 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
727 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
728 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
729
730
731 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
732 pipeline->graphics.vs.pa_cl_vs_out_cntl);
733
734 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
735 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
736 pipeline->graphics.vs.vgt_reuse_off);
737 }
738
739 static void
740 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
741 struct radv_pipeline *pipeline,
742 struct radv_shader_variant *shader)
743 {
744 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
745
746 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
747 radeon_emit(cmd_buffer->cs, va >> 8);
748 radeon_emit(cmd_buffer->cs, va >> 40);
749 radeon_emit(cmd_buffer->cs, shader->rsrc1);
750 radeon_emit(cmd_buffer->cs, shader->rsrc2);
751 }
752
753 static void
754 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
755 struct radv_shader_variant *shader)
756 {
757 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
758 uint32_t rsrc2 = shader->rsrc2;
759
760 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
761 radeon_emit(cmd_buffer->cs, va >> 8);
762 radeon_emit(cmd_buffer->cs, va >> 40);
763
764 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
765 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
766 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
767 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
768
769 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
770 radeon_emit(cmd_buffer->cs, shader->rsrc1);
771 radeon_emit(cmd_buffer->cs, rsrc2);
772 }
773
774 static void
775 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
776 struct radv_shader_variant *shader)
777 {
778 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
779
780 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
781 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
782 radeon_emit(cmd_buffer->cs, va >> 8);
783 radeon_emit(cmd_buffer->cs, va >> 40);
784
785 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
786 radeon_emit(cmd_buffer->cs, shader->rsrc1);
787 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
788 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
789 } else {
790 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
791 radeon_emit(cmd_buffer->cs, va >> 8);
792 radeon_emit(cmd_buffer->cs, va >> 40);
793 radeon_emit(cmd_buffer->cs, shader->rsrc1);
794 radeon_emit(cmd_buffer->cs, shader->rsrc2);
795 }
796 }
797
798 static void
799 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
800 struct radv_pipeline *pipeline)
801 {
802 struct radv_shader_variant *vs;
803
804 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
805
806 /* Skip shaders merged into HS/GS */
807 vs = pipeline->shaders[MESA_SHADER_VERTEX];
808 if (!vs)
809 return;
810
811 if (vs->info.vs.as_ls)
812 radv_emit_hw_ls(cmd_buffer, vs);
813 else if (vs->info.vs.as_es)
814 radv_emit_hw_es(cmd_buffer, pipeline, vs);
815 else
816 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
817 }
818
819
820 static void
821 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
822 struct radv_pipeline *pipeline)
823 {
824 if (!radv_pipeline_has_tess(pipeline))
825 return;
826
827 struct radv_shader_variant *tes, *tcs;
828
829 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
830 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
831
832 if (tes) {
833 if (tes->info.tes.as_es)
834 radv_emit_hw_es(cmd_buffer, pipeline, tes);
835 else
836 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
837 }
838
839 radv_emit_hw_hs(cmd_buffer, tcs);
840
841 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
842 pipeline->graphics.tess.tf_param);
843
844 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
845 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
846 pipeline->graphics.tess.ls_hs_config);
847 else
848 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
849 pipeline->graphics.tess.ls_hs_config);
850
851 struct ac_userdata_info *loc;
852
853 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
854 if (loc->sgpr_idx != -1) {
855 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
856 assert(loc->num_sgprs == 4);
857 assert(!loc->indirect);
858 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
859 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
860 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
861 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
862 pipeline->graphics.tess.num_tcs_input_cp << 26);
863 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
864 }
865
866 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
867 if (loc->sgpr_idx != -1) {
868 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
869 assert(loc->num_sgprs == 1);
870 assert(!loc->indirect);
871
872 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
873 pipeline->graphics.tess.offchip_layout);
874 }
875
876 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
877 if (loc->sgpr_idx != -1) {
878 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
879 assert(loc->num_sgprs == 1);
880 assert(!loc->indirect);
881
882 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
883 pipeline->graphics.tess.tcs_in_layout);
884 }
885 }
886
887 static void
888 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_pipeline *pipeline)
890 {
891 struct radv_shader_variant *gs;
892 uint64_t va;
893
894 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
895
896 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
897 if (!gs)
898 return;
899
900 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
901
902 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
903 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
904 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
905 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
906
907 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
908
909 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
910
911 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
912 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
913 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
914 radeon_emit(cmd_buffer->cs, 0);
915 radeon_emit(cmd_buffer->cs, 0);
916 radeon_emit(cmd_buffer->cs, 0);
917
918 uint32_t gs_num_invocations = gs->info.gs.invocations;
919 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
920 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
921 S_028B90_ENABLE(gs_num_invocations > 0));
922
923 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
924 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
925
926 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
927
928 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
929 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
930 radeon_emit(cmd_buffer->cs, va >> 8);
931 radeon_emit(cmd_buffer->cs, va >> 40);
932
933 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
934 radeon_emit(cmd_buffer->cs, gs->rsrc1);
935 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
936 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
937
938 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
939 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
940 } else {
941 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
942 radeon_emit(cmd_buffer->cs, va >> 8);
943 radeon_emit(cmd_buffer->cs, va >> 40);
944 radeon_emit(cmd_buffer->cs, gs->rsrc1);
945 radeon_emit(cmd_buffer->cs, gs->rsrc2);
946 }
947
948 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
949
950 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
951 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
952 if (loc->sgpr_idx != -1) {
953 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
954 uint32_t num_entries = 64;
955 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
956
957 if (is_vi)
958 num_entries *= stride;
959
960 stride = S_008F04_STRIDE(stride);
961 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
962 radeon_emit(cmd_buffer->cs, stride);
963 radeon_emit(cmd_buffer->cs, num_entries);
964 }
965 }
966
967 static void
968 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
969 struct radv_pipeline *pipeline)
970 {
971 struct radv_shader_variant *ps;
972 uint64_t va;
973 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
974 struct radv_blend_state *blend = &pipeline->graphics.blend;
975 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
976
977 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
978 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
979
980 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
981 radeon_emit(cmd_buffer->cs, va >> 8);
982 radeon_emit(cmd_buffer->cs, va >> 40);
983 radeon_emit(cmd_buffer->cs, ps->rsrc1);
984 radeon_emit(cmd_buffer->cs, ps->rsrc2);
985
986 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
987 pipeline->graphics.db_shader_control);
988
989 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
990 ps->config.spi_ps_input_ena);
991
992 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
993 ps->config.spi_ps_input_addr);
994
995 if (ps->info.info.ps.force_persample)
996 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
997
998 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
999 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1000
1001 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1002
1003 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1004 pipeline->graphics.shader_z_format);
1005
1006 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1007
1008 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1009 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1010
1011 if (cmd_buffer->device->dfsm_allowed) {
1012 /* optimise this? */
1013 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1014 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1015 }
1016
1017 if (pipeline->graphics.ps_input_cntl_num) {
1018 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1019 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1020 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1021 }
1022 }
1023 }
1024
1025 static void
1026 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1027 struct radv_pipeline *pipeline)
1028 {
1029 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1030
1031 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1032 return;
1033
1034 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1035 pipeline->graphics.vtx_reuse_depth);
1036 }
1037
1038 static void
1039 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1040 {
1041 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1042
1043 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1044 return;
1045
1046 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1047 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1048 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1049 radv_update_multisample_state(cmd_buffer, pipeline);
1050 radv_emit_vertex_shader(cmd_buffer, pipeline);
1051 radv_emit_tess_shaders(cmd_buffer, pipeline);
1052 radv_emit_geometry_shader(cmd_buffer, pipeline);
1053 radv_emit_fragment_shader(cmd_buffer, pipeline);
1054 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1055
1056 cmd_buffer->scratch_size_needed =
1057 MAX2(cmd_buffer->scratch_size_needed,
1058 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1059
1060 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1061 S_0286E8_WAVES(pipeline->max_waves) |
1062 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1063
1064 if (!cmd_buffer->state.emitted_pipeline ||
1065 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1066 pipeline->graphics.can_use_guardband)
1067 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1068
1069 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1070
1071 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1072 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1073 } else {
1074 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1075 }
1076 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1077
1078 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1079
1080 cmd_buffer->state.emitted_pipeline = pipeline;
1081
1082 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1083 }
1084
1085 static void
1086 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1087 {
1088 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1089 cmd_buffer->state.dynamic.viewport.viewports);
1090 }
1091
1092 static void
1093 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1094 {
1095 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1096
1097 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1098 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1099 si_emit_cache_flush(cmd_buffer);
1100 }
1101 si_write_scissors(cmd_buffer->cs, 0, count,
1102 cmd_buffer->state.dynamic.scissor.scissors,
1103 cmd_buffer->state.dynamic.viewport.viewports,
1104 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1105 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1106 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1107 }
1108
1109 static void
1110 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1111 {
1112 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1113
1114 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1115 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1116 }
1117
1118 static void
1119 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1120 {
1121 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1122
1123 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1124 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1125 }
1126
1127 static void
1128 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1129 {
1130 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1131
1132 radeon_set_context_reg_seq(cmd_buffer->cs,
1133 R_028430_DB_STENCILREFMASK, 2);
1134 radeon_emit(cmd_buffer->cs,
1135 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1136 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1137 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1138 S_028430_STENCILOPVAL(1));
1139 radeon_emit(cmd_buffer->cs,
1140 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1141 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1142 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1143 S_028434_STENCILOPVAL_BF(1));
1144 }
1145
1146 static void
1147 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1148 {
1149 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1150
1151 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1152 fui(d->depth_bounds.min));
1153 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1154 fui(d->depth_bounds.max));
1155 }
1156
1157 static void
1158 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1159 {
1160 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1161 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1162 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1163 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1164
1165 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1166 radeon_set_context_reg_seq(cmd_buffer->cs,
1167 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1168 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1169 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1170 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1171 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1172 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1173 }
1174 }
1175
1176 static void
1177 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1178 int index,
1179 struct radv_color_buffer_info *cb)
1180 {
1181 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1182
1183 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1184 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1185 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1186 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1187 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1188 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1189 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1190 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1191 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1192 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1193 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1195 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1196
1197 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1198 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1199 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1200
1201 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1202 cb->gfx9_epitch);
1203 } else {
1204 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1205 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1206 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1207 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1208 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1209 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1210 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1211 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1212 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1213 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1215 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1216
1217 if (is_vi) { /* DCC BASE */
1218 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1219 }
1220 }
1221 }
1222
1223 static void
1224 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1225 struct radv_ds_buffer_info *ds,
1226 struct radv_image *image,
1227 VkImageLayout layout)
1228 {
1229 uint32_t db_z_info = ds->db_z_info;
1230 uint32_t db_stencil_info = ds->db_stencil_info;
1231
1232 if (!radv_layout_has_htile(image, layout,
1233 radv_image_queue_family_mask(image,
1234 cmd_buffer->queue_family_index,
1235 cmd_buffer->queue_family_index))) {
1236 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1237 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1238 }
1239
1240 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1241 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1242
1243
1244 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1245 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1246 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1247 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1248 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1249
1250 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1251 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1252 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1253 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1254 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1255 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1256 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1257 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1258 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1259 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1260 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1261
1262 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1263 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1264 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1265 } else {
1266 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1267
1268 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1269 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1270 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1271 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1272 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1273 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1274 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1275 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1276 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1277 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1278
1279 }
1280
1281 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1282 ds->pa_su_poly_offset_db_fmt_cntl);
1283 }
1284
1285 void
1286 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1287 struct radv_image *image,
1288 VkClearDepthStencilValue ds_clear_value,
1289 VkImageAspectFlags aspects)
1290 {
1291 uint64_t va = radv_buffer_get_va(image->bo);
1292 va += image->offset + image->clear_value_offset;
1293 unsigned reg_offset = 0, reg_count = 0;
1294
1295 if (!image->surface.htile_size || !aspects)
1296 return;
1297
1298 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1299 ++reg_count;
1300 } else {
1301 ++reg_offset;
1302 va += 4;
1303 }
1304 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1305 ++reg_count;
1306
1307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1308
1309 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1310 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1311 S_370_WR_CONFIRM(1) |
1312 S_370_ENGINE_SEL(V_370_PFP));
1313 radeon_emit(cmd_buffer->cs, va);
1314 radeon_emit(cmd_buffer->cs, va >> 32);
1315 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1316 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1317 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1318 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1319
1320 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1321 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1322 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1323 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1324 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1325 }
1326
1327 static void
1328 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1329 struct radv_image *image)
1330 {
1331 uint64_t va = radv_buffer_get_va(image->bo);
1332 va += image->offset + image->clear_value_offset;
1333
1334 if (!image->surface.htile_size)
1335 return;
1336
1337
1338 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1339 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1340 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1341 COPY_DATA_COUNT_SEL);
1342 radeon_emit(cmd_buffer->cs, va);
1343 radeon_emit(cmd_buffer->cs, va >> 32);
1344 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1345 radeon_emit(cmd_buffer->cs, 0);
1346
1347 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1348 radeon_emit(cmd_buffer->cs, 0);
1349 }
1350
1351 /*
1352 *with DCC some colors don't require CMASK elimiation before being
1353 * used as a texture. This sets a predicate value to determine if the
1354 * cmask eliminate is required.
1355 */
1356 void
1357 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1358 struct radv_image *image,
1359 bool value)
1360 {
1361 uint64_t pred_val = value;
1362 uint64_t va = radv_buffer_get_va(image->bo);
1363 va += image->offset + image->dcc_pred_offset;
1364
1365 if (!image->surface.dcc_size)
1366 return;
1367
1368 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1369
1370 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1371 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1372 S_370_WR_CONFIRM(1) |
1373 S_370_ENGINE_SEL(V_370_PFP));
1374 radeon_emit(cmd_buffer->cs, va);
1375 radeon_emit(cmd_buffer->cs, va >> 32);
1376 radeon_emit(cmd_buffer->cs, pred_val);
1377 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1378 }
1379
1380 void
1381 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1382 struct radv_image *image,
1383 int idx,
1384 uint32_t color_values[2])
1385 {
1386 uint64_t va = radv_buffer_get_va(image->bo);
1387 va += image->offset + image->clear_value_offset;
1388
1389 if (!image->cmask.size && !image->surface.dcc_size)
1390 return;
1391
1392 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 8);
1393
1394 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1395 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1396 S_370_WR_CONFIRM(1) |
1397 S_370_ENGINE_SEL(V_370_PFP));
1398 radeon_emit(cmd_buffer->cs, va);
1399 radeon_emit(cmd_buffer->cs, va >> 32);
1400 radeon_emit(cmd_buffer->cs, color_values[0]);
1401 radeon_emit(cmd_buffer->cs, color_values[1]);
1402
1403 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1404 radeon_emit(cmd_buffer->cs, color_values[0]);
1405 radeon_emit(cmd_buffer->cs, color_values[1]);
1406 }
1407
1408 static void
1409 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1410 struct radv_image *image,
1411 int idx)
1412 {
1413 uint64_t va = radv_buffer_get_va(image->bo);
1414 va += image->offset + image->clear_value_offset;
1415
1416 if (!image->cmask.size && !image->surface.dcc_size)
1417 return;
1418
1419 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1420
1421 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1422 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1423 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1424 COPY_DATA_COUNT_SEL);
1425 radeon_emit(cmd_buffer->cs, va);
1426 radeon_emit(cmd_buffer->cs, va >> 32);
1427 radeon_emit(cmd_buffer->cs, reg >> 2);
1428 radeon_emit(cmd_buffer->cs, 0);
1429
1430 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1431 radeon_emit(cmd_buffer->cs, 0);
1432 }
1433
1434 void
1435 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1436 {
1437 int i;
1438 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1439 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1440
1441 /* this may happen for inherited secondary recording */
1442 if (!framebuffer)
1443 return;
1444
1445 for (i = 0; i < 8; ++i) {
1446 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1447 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1448 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1449 continue;
1450 }
1451
1452 int idx = subpass->color_attachments[i].attachment;
1453 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1454
1455 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1456
1457 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1458 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1459
1460 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1461 }
1462
1463 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1464 int idx = subpass->depth_stencil_attachment.attachment;
1465 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1466 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1467 struct radv_image *image = att->attachment->image;
1468 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1469 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1470 cmd_buffer->queue_family_index,
1471 cmd_buffer->queue_family_index);
1472 /* We currently don't support writing decompressed HTILE */
1473 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1474 radv_layout_is_htile_compressed(image, layout, queue_mask));
1475
1476 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1477
1478 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1479 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1480 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1481 }
1482 radv_load_depth_clear_regs(cmd_buffer, image);
1483 } else {
1484 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1485 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1486 else
1487 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1488
1489 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1490 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1491 }
1492 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1493 S_028208_BR_X(framebuffer->width) |
1494 S_028208_BR_Y(framebuffer->height));
1495
1496 if (cmd_buffer->device->dfsm_allowed) {
1497 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1498 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1499 }
1500
1501 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1502 }
1503
1504 static void
1505 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1506 {
1507 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1508
1509 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1510 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1511 2, cmd_buffer->state.index_type);
1512 } else {
1513 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1514 radeon_emit(cs, cmd_buffer->state.index_type);
1515 }
1516
1517 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1518 radeon_emit(cs, cmd_buffer->state.index_va);
1519 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1520
1521 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1522 radeon_emit(cs, cmd_buffer->state.max_index_count);
1523
1524 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1525 }
1526
1527 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1528 {
1529 uint32_t db_count_control;
1530
1531 if(!cmd_buffer->state.active_occlusion_queries) {
1532 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1533 db_count_control = 0;
1534 } else {
1535 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1536 }
1537 } else {
1538 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1539 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1540 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1541 S_028004_ZPASS_ENABLE(1) |
1542 S_028004_SLICE_EVEN_ENABLE(1) |
1543 S_028004_SLICE_ODD_ENABLE(1);
1544 } else {
1545 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1546 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1547 }
1548 }
1549
1550 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1551 }
1552
1553 static void
1554 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1555 {
1556 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1557 return;
1558
1559 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1560 radv_emit_viewport(cmd_buffer);
1561
1562 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1563 radv_emit_scissor(cmd_buffer);
1564
1565 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1566 radv_emit_line_width(cmd_buffer);
1567
1568 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1569 radv_emit_blend_constants(cmd_buffer);
1570
1571 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1572 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1573 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1574 radv_emit_stencil(cmd_buffer);
1575
1576 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1577 radv_emit_depth_bounds(cmd_buffer);
1578
1579 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1580 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1581 radv_emit_depth_biais(cmd_buffer);
1582
1583 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1584 }
1585
1586 static void
1587 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1588 struct radv_pipeline *pipeline,
1589 int idx,
1590 uint64_t va,
1591 gl_shader_stage stage)
1592 {
1593 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1594 uint32_t base_reg = pipeline->user_data_0[stage];
1595
1596 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1597 return;
1598
1599 assert(!desc_set_loc->indirect);
1600 assert(desc_set_loc->num_sgprs == 2);
1601 radeon_set_sh_reg_seq(cmd_buffer->cs,
1602 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1603 radeon_emit(cmd_buffer->cs, va);
1604 radeon_emit(cmd_buffer->cs, va >> 32);
1605 }
1606
1607 static void
1608 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1609 VkShaderStageFlags stages,
1610 struct radv_descriptor_set *set,
1611 unsigned idx)
1612 {
1613 if (cmd_buffer->state.pipeline) {
1614 radv_foreach_stage(stage, stages) {
1615 if (cmd_buffer->state.pipeline->shaders[stage])
1616 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1617 idx, set->va,
1618 stage);
1619 }
1620 }
1621
1622 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1623 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1624 idx, set->va,
1625 MESA_SHADER_COMPUTE);
1626 }
1627
1628 static void
1629 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1630 {
1631 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1632 unsigned bo_offset;
1633
1634 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1635 set->mapped_ptr,
1636 &bo_offset))
1637 return;
1638
1639 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1640 set->va += bo_offset;
1641 }
1642
1643 static void
1644 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1645 {
1646 uint32_t size = MAX_SETS * 2 * 4;
1647 uint32_t offset;
1648 void *ptr;
1649
1650 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1651 256, &offset, &ptr))
1652 return;
1653
1654 for (unsigned i = 0; i < MAX_SETS; i++) {
1655 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1656 uint64_t set_va = 0;
1657 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1658 if (cmd_buffer->state.valid_descriptors & (1u << i))
1659 set_va = set->va;
1660 uptr[0] = set_va & 0xffffffff;
1661 uptr[1] = set_va >> 32;
1662 }
1663
1664 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1665 va += offset;
1666
1667 if (cmd_buffer->state.pipeline) {
1668 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1669 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1670 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1671
1672 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1673 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1674 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1675
1676 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1677 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1678 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1679
1680 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1681 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1682 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1683
1684 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1685 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1686 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1687 }
1688
1689 if (cmd_buffer->state.compute_pipeline)
1690 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1692 }
1693
1694 static void
1695 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1696 VkShaderStageFlags stages)
1697 {
1698 unsigned i;
1699
1700 if (!cmd_buffer->state.descriptors_dirty)
1701 return;
1702
1703 if (cmd_buffer->state.push_descriptors_dirty)
1704 radv_flush_push_descriptors(cmd_buffer);
1705
1706 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1707 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1708 radv_flush_indirect_descriptor_sets(cmd_buffer);
1709 }
1710
1711 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1712 cmd_buffer->cs,
1713 MAX_SETS * MESA_SHADER_STAGES * 4);
1714
1715 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1716 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1717 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1718 continue;
1719
1720 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1721 }
1722 cmd_buffer->state.descriptors_dirty = 0;
1723 cmd_buffer->state.push_descriptors_dirty = false;
1724
1725 if (cmd_buffer->device->trace_bo)
1726 radv_save_descriptors(cmd_buffer);
1727
1728 assert(cmd_buffer->cs->cdw <= cdw_max);
1729 }
1730
1731 static void
1732 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1733 struct radv_pipeline *pipeline,
1734 VkShaderStageFlags stages)
1735 {
1736 struct radv_pipeline_layout *layout = pipeline->layout;
1737 unsigned offset;
1738 void *ptr;
1739 uint64_t va;
1740
1741 stages &= cmd_buffer->push_constant_stages;
1742 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1743 return;
1744
1745 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1746 16 * layout->dynamic_offset_count,
1747 256, &offset, &ptr))
1748 return;
1749
1750 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1751 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1752 16 * layout->dynamic_offset_count);
1753
1754 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1755 va += offset;
1756
1757 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1758 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1759
1760 radv_foreach_stage(stage, stages) {
1761 if (pipeline->shaders[stage]) {
1762 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1763 AC_UD_PUSH_CONSTANTS, va);
1764 }
1765 }
1766
1767 cmd_buffer->push_constant_stages &= ~stages;
1768 assert(cmd_buffer->cs->cdw <= cdw_max);
1769 }
1770
1771 static bool
1772 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1773 {
1774 struct radv_device *device = cmd_buffer->device;
1775
1776 if ((pipeline_is_dirty || cmd_buffer->state.vb_dirty) &&
1777 cmd_buffer->state.pipeline->vertex_elements.count &&
1778 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1779 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1780 unsigned vb_offset;
1781 void *vb_ptr;
1782 uint32_t i = 0;
1783 uint32_t count = velems->count;
1784 uint64_t va;
1785
1786 /* allocate some descriptor state for vertex buffers */
1787 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1788 &vb_offset, &vb_ptr))
1789 return false;
1790
1791 for (i = 0; i < count; i++) {
1792 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1793 uint32_t offset;
1794 int vb = velems->binding[i];
1795 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1796 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1797
1798 radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo, 8);
1799 va = radv_buffer_get_va(buffer->bo);
1800
1801 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1802 va += offset + buffer->offset;
1803 desc[0] = va;
1804 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1805 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1806 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1807 else
1808 desc[2] = buffer->size - offset;
1809 desc[3] = velems->rsrc_word3[i];
1810 }
1811
1812 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1813 va += vb_offset;
1814
1815 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1816 AC_UD_VS_VERTEX_BUFFERS, va);
1817 }
1818 cmd_buffer->state.vb_dirty = false;
1819
1820 return true;
1821 }
1822
1823 static bool
1824 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1825 {
1826 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1827 return false;
1828
1829 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1830 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1831 VK_SHADER_STAGE_ALL_GRAPHICS);
1832
1833 return true;
1834 }
1835
1836 static void
1837 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1838 bool instanced_draw, bool indirect_draw,
1839 uint32_t draw_vertex_count)
1840 {
1841 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1842 struct radv_cmd_state *state = &cmd_buffer->state;
1843 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1844 uint32_t ia_multi_vgt_param;
1845 int32_t primitive_reset_en;
1846
1847 /* Draw state. */
1848 ia_multi_vgt_param =
1849 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1850 indirect_draw, draw_vertex_count);
1851
1852 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1853 if (info->chip_class >= GFX9) {
1854 radeon_set_uconfig_reg_idx(cs,
1855 R_030960_IA_MULTI_VGT_PARAM,
1856 4, ia_multi_vgt_param);
1857 } else if (info->chip_class >= CIK) {
1858 radeon_set_context_reg_idx(cs,
1859 R_028AA8_IA_MULTI_VGT_PARAM,
1860 1, ia_multi_vgt_param);
1861 } else {
1862 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1863 ia_multi_vgt_param);
1864 }
1865 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1866 }
1867
1868 /* Primitive restart. */
1869 primitive_reset_en =
1870 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1871
1872 if (primitive_reset_en != state->last_primitive_reset_en) {
1873 state->last_primitive_reset_en = primitive_reset_en;
1874 if (info->chip_class >= GFX9) {
1875 radeon_set_uconfig_reg(cs,
1876 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1877 primitive_reset_en);
1878 } else {
1879 radeon_set_context_reg(cs,
1880 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1881 primitive_reset_en);
1882 }
1883 }
1884
1885 if (primitive_reset_en) {
1886 uint32_t primitive_reset_index =
1887 state->index_type ? 0xffffffffu : 0xffffu;
1888
1889 if (primitive_reset_index != state->last_primitive_reset_index) {
1890 radeon_set_context_reg(cs,
1891 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1892 primitive_reset_index);
1893 state->last_primitive_reset_index = primitive_reset_index;
1894 }
1895 }
1896 }
1897
1898 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1899 VkPipelineStageFlags src_stage_mask)
1900 {
1901 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1902 VK_PIPELINE_STAGE_TRANSFER_BIT |
1903 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1904 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1905 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1906 }
1907
1908 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1909 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1910 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1911 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1912 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1913 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1914 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1915 VK_PIPELINE_STAGE_TRANSFER_BIT |
1916 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1917 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1918 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1919 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1920 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1921 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1922 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1923 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1924 }
1925 }
1926
1927 static enum radv_cmd_flush_bits
1928 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1929 VkAccessFlags src_flags)
1930 {
1931 enum radv_cmd_flush_bits flush_bits = 0;
1932 uint32_t b;
1933 for_each_bit(b, src_flags) {
1934 switch ((VkAccessFlagBits)(1 << b)) {
1935 case VK_ACCESS_SHADER_WRITE_BIT:
1936 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1937 break;
1938 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1939 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1940 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1941 break;
1942 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1943 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1944 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1945 break;
1946 case VK_ACCESS_TRANSFER_WRITE_BIT:
1947 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1948 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1949 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1950 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1951 RADV_CMD_FLAG_INV_GLOBAL_L2;
1952 break;
1953 default:
1954 break;
1955 }
1956 }
1957 return flush_bits;
1958 }
1959
1960 static enum radv_cmd_flush_bits
1961 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1962 VkAccessFlags dst_flags,
1963 struct radv_image *image)
1964 {
1965 enum radv_cmd_flush_bits flush_bits = 0;
1966 uint32_t b;
1967 for_each_bit(b, dst_flags) {
1968 switch ((VkAccessFlagBits)(1 << b)) {
1969 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1970 case VK_ACCESS_INDEX_READ_BIT:
1971 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1972 break;
1973 case VK_ACCESS_UNIFORM_READ_BIT:
1974 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1975 break;
1976 case VK_ACCESS_SHADER_READ_BIT:
1977 case VK_ACCESS_TRANSFER_READ_BIT:
1978 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1979 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1980 RADV_CMD_FLAG_INV_GLOBAL_L2;
1981 break;
1982 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1983 /* TODO: change to image && when the image gets passed
1984 * through from the subpass. */
1985 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1986 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1987 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1988 break;
1989 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1990 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1991 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1992 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1993 break;
1994 default:
1995 break;
1996 }
1997 }
1998 return flush_bits;
1999 }
2000
2001 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2002 {
2003 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2004 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2005 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2006 NULL);
2007 }
2008
2009 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2010 VkAttachmentReference att)
2011 {
2012 unsigned idx = att.attachment;
2013 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2014 VkImageSubresourceRange range;
2015 range.aspectMask = 0;
2016 range.baseMipLevel = view->base_mip;
2017 range.levelCount = 1;
2018 range.baseArrayLayer = view->base_layer;
2019 range.layerCount = cmd_buffer->state.framebuffer->layers;
2020
2021 radv_handle_image_transition(cmd_buffer,
2022 view->image,
2023 cmd_buffer->state.attachments[idx].current_layout,
2024 att.layout, 0, 0, &range,
2025 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2026
2027 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2028
2029
2030 }
2031
2032 void
2033 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2034 const struct radv_subpass *subpass, bool transitions)
2035 {
2036 if (transitions) {
2037 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2038
2039 for (unsigned i = 0; i < subpass->color_count; ++i) {
2040 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2041 radv_handle_subpass_image_transition(cmd_buffer,
2042 subpass->color_attachments[i]);
2043 }
2044
2045 for (unsigned i = 0; i < subpass->input_count; ++i) {
2046 radv_handle_subpass_image_transition(cmd_buffer,
2047 subpass->input_attachments[i]);
2048 }
2049
2050 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2051 radv_handle_subpass_image_transition(cmd_buffer,
2052 subpass->depth_stencil_attachment);
2053 }
2054 }
2055
2056 cmd_buffer->state.subpass = subpass;
2057
2058 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2059 }
2060
2061 static VkResult
2062 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2063 struct radv_render_pass *pass,
2064 const VkRenderPassBeginInfo *info)
2065 {
2066 struct radv_cmd_state *state = &cmd_buffer->state;
2067
2068 if (pass->attachment_count == 0) {
2069 state->attachments = NULL;
2070 return VK_SUCCESS;
2071 }
2072
2073 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2074 pass->attachment_count *
2075 sizeof(state->attachments[0]),
2076 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2077 if (state->attachments == NULL) {
2078 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2079 return cmd_buffer->record_result;
2080 }
2081
2082 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2083 struct radv_render_pass_attachment *att = &pass->attachments[i];
2084 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2085 VkImageAspectFlags clear_aspects = 0;
2086
2087 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2088 /* color attachment */
2089 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2090 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2091 }
2092 } else {
2093 /* depthstencil attachment */
2094 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2095 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2096 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2097 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2098 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2099 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2100 }
2101 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2102 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2103 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2104 }
2105 }
2106
2107 state->attachments[i].pending_clear_aspects = clear_aspects;
2108 state->attachments[i].cleared_views = 0;
2109 if (clear_aspects && info) {
2110 assert(info->clearValueCount > i);
2111 state->attachments[i].clear_value = info->pClearValues[i];
2112 }
2113
2114 state->attachments[i].current_layout = att->initial_layout;
2115 }
2116
2117 return VK_SUCCESS;
2118 }
2119
2120 VkResult radv_AllocateCommandBuffers(
2121 VkDevice _device,
2122 const VkCommandBufferAllocateInfo *pAllocateInfo,
2123 VkCommandBuffer *pCommandBuffers)
2124 {
2125 RADV_FROM_HANDLE(radv_device, device, _device);
2126 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2127
2128 VkResult result = VK_SUCCESS;
2129 uint32_t i;
2130
2131 memset(pCommandBuffers, 0,
2132 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2133
2134 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2135
2136 if (!list_empty(&pool->free_cmd_buffers)) {
2137 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2138
2139 list_del(&cmd_buffer->pool_link);
2140 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2141
2142 result = radv_reset_cmd_buffer(cmd_buffer);
2143 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2144 cmd_buffer->level = pAllocateInfo->level;
2145
2146 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2147 } else {
2148 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2149 &pCommandBuffers[i]);
2150 }
2151 if (result != VK_SUCCESS)
2152 break;
2153 }
2154
2155 if (result != VK_SUCCESS)
2156 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2157 i, pCommandBuffers);
2158
2159 return result;
2160 }
2161
2162 void radv_FreeCommandBuffers(
2163 VkDevice device,
2164 VkCommandPool commandPool,
2165 uint32_t commandBufferCount,
2166 const VkCommandBuffer *pCommandBuffers)
2167 {
2168 for (uint32_t i = 0; i < commandBufferCount; i++) {
2169 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2170
2171 if (cmd_buffer) {
2172 if (cmd_buffer->pool) {
2173 list_del(&cmd_buffer->pool_link);
2174 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2175 } else
2176 radv_cmd_buffer_destroy(cmd_buffer);
2177
2178 }
2179 }
2180 }
2181
2182 VkResult radv_ResetCommandBuffer(
2183 VkCommandBuffer commandBuffer,
2184 VkCommandBufferResetFlags flags)
2185 {
2186 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2187 return radv_reset_cmd_buffer(cmd_buffer);
2188 }
2189
2190 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2191 {
2192 struct radv_device *device = cmd_buffer->device;
2193 if (device->gfx_init) {
2194 uint64_t va = radv_buffer_get_va(device->gfx_init);
2195 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2196 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2197 radeon_emit(cmd_buffer->cs, va);
2198 radeon_emit(cmd_buffer->cs, va >> 32);
2199 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2200 } else
2201 si_init_config(cmd_buffer);
2202 }
2203
2204 VkResult radv_BeginCommandBuffer(
2205 VkCommandBuffer commandBuffer,
2206 const VkCommandBufferBeginInfo *pBeginInfo)
2207 {
2208 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2209 VkResult result;
2210
2211 result = radv_reset_cmd_buffer(cmd_buffer);
2212 if (result != VK_SUCCESS)
2213 return result;
2214
2215 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2216 cmd_buffer->state.last_primitive_reset_en = -1;
2217 cmd_buffer->usage_flags = pBeginInfo->flags;
2218
2219 /* setup initial configuration into command buffer */
2220 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2221 switch (cmd_buffer->queue_family_index) {
2222 case RADV_QUEUE_GENERAL:
2223 emit_gfx_buffer_state(cmd_buffer);
2224 break;
2225 case RADV_QUEUE_COMPUTE:
2226 si_init_compute(cmd_buffer);
2227 break;
2228 case RADV_QUEUE_TRANSFER:
2229 default:
2230 break;
2231 }
2232 }
2233
2234 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2235 assert(pBeginInfo->pInheritanceInfo);
2236 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2237 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2238
2239 struct radv_subpass *subpass =
2240 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2241
2242 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2243 if (result != VK_SUCCESS)
2244 return result;
2245
2246 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2247 }
2248
2249 radv_cmd_buffer_trace_emit(cmd_buffer);
2250 return result;
2251 }
2252
2253 void radv_CmdBindVertexBuffers(
2254 VkCommandBuffer commandBuffer,
2255 uint32_t firstBinding,
2256 uint32_t bindingCount,
2257 const VkBuffer* pBuffers,
2258 const VkDeviceSize* pOffsets)
2259 {
2260 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2261 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2262 bool changed = false;
2263
2264 /* We have to defer setting up vertex buffer since we need the buffer
2265 * stride from the pipeline. */
2266
2267 assert(firstBinding + bindingCount <= MAX_VBS);
2268 for (uint32_t i = 0; i < bindingCount; i++) {
2269 uint32_t idx = firstBinding + i;
2270
2271 if (!changed &&
2272 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2273 vb[idx].offset != pOffsets[i])) {
2274 changed = true;
2275 }
2276
2277 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2278 vb[idx].offset = pOffsets[i];
2279 }
2280
2281 if (!changed) {
2282 /* No state changes. */
2283 return;
2284 }
2285
2286 cmd_buffer->state.vb_dirty = true;
2287 }
2288
2289 void radv_CmdBindIndexBuffer(
2290 VkCommandBuffer commandBuffer,
2291 VkBuffer buffer,
2292 VkDeviceSize offset,
2293 VkIndexType indexType)
2294 {
2295 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2296 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2297
2298 if (cmd_buffer->state.index_buffer == index_buffer &&
2299 cmd_buffer->state.index_offset == offset &&
2300 cmd_buffer->state.index_type == indexType) {
2301 /* No state changes. */
2302 return;
2303 }
2304
2305 cmd_buffer->state.index_buffer = index_buffer;
2306 cmd_buffer->state.index_offset = offset;
2307 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2308 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2309 cmd_buffer->state.index_va += index_buffer->offset + offset;
2310
2311 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2312 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2313 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2314 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2315 }
2316
2317
2318 static void
2319 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2320 struct radv_descriptor_set *set, unsigned idx)
2321 {
2322 struct radeon_winsys *ws = cmd_buffer->device->ws;
2323
2324 radv_set_descriptor_set(cmd_buffer, set, idx);
2325 if (!set)
2326 return;
2327
2328 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2329
2330 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2331 if (set->descriptors[j])
2332 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2333
2334 if(set->bo)
2335 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2336 }
2337
2338 void radv_CmdBindDescriptorSets(
2339 VkCommandBuffer commandBuffer,
2340 VkPipelineBindPoint pipelineBindPoint,
2341 VkPipelineLayout _layout,
2342 uint32_t firstSet,
2343 uint32_t descriptorSetCount,
2344 const VkDescriptorSet* pDescriptorSets,
2345 uint32_t dynamicOffsetCount,
2346 const uint32_t* pDynamicOffsets)
2347 {
2348 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2349 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2350 unsigned dyn_idx = 0;
2351
2352 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2353 unsigned idx = i + firstSet;
2354 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2355 radv_bind_descriptor_set(cmd_buffer, set, idx);
2356
2357 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2358 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2359 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2360 assert(dyn_idx < dynamicOffsetCount);
2361
2362 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2363 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2364 dst[0] = va;
2365 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2366 dst[2] = range->size;
2367 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2368 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2369 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2370 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2371 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2372 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2373 cmd_buffer->push_constant_stages |=
2374 set->layout->dynamic_shader_stages;
2375 }
2376 }
2377 }
2378
2379 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2380 struct radv_descriptor_set *set,
2381 struct radv_descriptor_set_layout *layout)
2382 {
2383 set->size = layout->size;
2384 set->layout = layout;
2385
2386 if (cmd_buffer->push_descriptors.capacity < set->size) {
2387 size_t new_size = MAX2(set->size, 1024);
2388 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2389 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2390
2391 free(set->mapped_ptr);
2392 set->mapped_ptr = malloc(new_size);
2393
2394 if (!set->mapped_ptr) {
2395 cmd_buffer->push_descriptors.capacity = 0;
2396 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2397 return false;
2398 }
2399
2400 cmd_buffer->push_descriptors.capacity = new_size;
2401 }
2402
2403 return true;
2404 }
2405
2406 void radv_meta_push_descriptor_set(
2407 struct radv_cmd_buffer* cmd_buffer,
2408 VkPipelineBindPoint pipelineBindPoint,
2409 VkPipelineLayout _layout,
2410 uint32_t set,
2411 uint32_t descriptorWriteCount,
2412 const VkWriteDescriptorSet* pDescriptorWrites)
2413 {
2414 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2415 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2416 unsigned bo_offset;
2417
2418 assert(set == 0);
2419 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2420
2421 push_set->size = layout->set[set].layout->size;
2422 push_set->layout = layout->set[set].layout;
2423
2424 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2425 &bo_offset,
2426 (void**) &push_set->mapped_ptr))
2427 return;
2428
2429 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2430 push_set->va += bo_offset;
2431
2432 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2433 radv_descriptor_set_to_handle(push_set),
2434 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2435
2436 radv_set_descriptor_set(cmd_buffer, push_set, set);
2437 }
2438
2439 void radv_CmdPushDescriptorSetKHR(
2440 VkCommandBuffer commandBuffer,
2441 VkPipelineBindPoint pipelineBindPoint,
2442 VkPipelineLayout _layout,
2443 uint32_t set,
2444 uint32_t descriptorWriteCount,
2445 const VkWriteDescriptorSet* pDescriptorWrites)
2446 {
2447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2448 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2449 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2450
2451 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2452
2453 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2454 return;
2455
2456 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2457 radv_descriptor_set_to_handle(push_set),
2458 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2459
2460 radv_set_descriptor_set(cmd_buffer, push_set, set);
2461 cmd_buffer->state.push_descriptors_dirty = true;
2462 }
2463
2464 void radv_CmdPushDescriptorSetWithTemplateKHR(
2465 VkCommandBuffer commandBuffer,
2466 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2467 VkPipelineLayout _layout,
2468 uint32_t set,
2469 const void* pData)
2470 {
2471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2472 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2473 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2474
2475 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2476
2477 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2478 return;
2479
2480 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2481 descriptorUpdateTemplate, pData);
2482
2483 radv_set_descriptor_set(cmd_buffer, push_set, set);
2484 cmd_buffer->state.push_descriptors_dirty = true;
2485 }
2486
2487 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2488 VkPipelineLayout layout,
2489 VkShaderStageFlags stageFlags,
2490 uint32_t offset,
2491 uint32_t size,
2492 const void* pValues)
2493 {
2494 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2495 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2496 cmd_buffer->push_constant_stages |= stageFlags;
2497 }
2498
2499 VkResult radv_EndCommandBuffer(
2500 VkCommandBuffer commandBuffer)
2501 {
2502 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2503
2504 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2505 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2506 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2507 si_emit_cache_flush(cmd_buffer);
2508 }
2509
2510 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2511
2512 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2513 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2514
2515 return cmd_buffer->record_result;
2516 }
2517
2518 static void
2519 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2520 {
2521 struct radv_shader_variant *compute_shader;
2522 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2523 uint64_t va;
2524
2525 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2526 return;
2527
2528 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2529
2530 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2531 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2532
2533 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2534 cmd_buffer->cs, 16);
2535
2536 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2537 radeon_emit(cmd_buffer->cs, va >> 8);
2538 radeon_emit(cmd_buffer->cs, va >> 40);
2539
2540 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2541 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2542 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2543
2544
2545 cmd_buffer->compute_scratch_size_needed =
2546 MAX2(cmd_buffer->compute_scratch_size_needed,
2547 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2548
2549 /* change these once we have scratch support */
2550 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2551 S_00B860_WAVES(pipeline->max_waves) |
2552 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2553
2554 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2555 radeon_emit(cmd_buffer->cs,
2556 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2557 radeon_emit(cmd_buffer->cs,
2558 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2559 radeon_emit(cmd_buffer->cs,
2560 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2561
2562 assert(cmd_buffer->cs->cdw <= cdw_max);
2563 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2564 }
2565
2566 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2567 {
2568 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2569 }
2570
2571 void radv_CmdBindPipeline(
2572 VkCommandBuffer commandBuffer,
2573 VkPipelineBindPoint pipelineBindPoint,
2574 VkPipeline _pipeline)
2575 {
2576 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2577 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2578
2579 switch (pipelineBindPoint) {
2580 case VK_PIPELINE_BIND_POINT_COMPUTE:
2581 if (cmd_buffer->state.compute_pipeline == pipeline)
2582 return;
2583 radv_mark_descriptor_sets_dirty(cmd_buffer);
2584
2585 cmd_buffer->state.compute_pipeline = pipeline;
2586 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2587 break;
2588 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2589 if (cmd_buffer->state.pipeline == pipeline)
2590 return;
2591 radv_mark_descriptor_sets_dirty(cmd_buffer);
2592
2593 cmd_buffer->state.pipeline = pipeline;
2594 if (!pipeline)
2595 break;
2596
2597 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2598 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2599
2600 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2601
2602 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2603 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2604 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2605 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2606
2607 if (radv_pipeline_has_tess(pipeline))
2608 cmd_buffer->tess_rings_needed = true;
2609
2610 if (radv_pipeline_has_gs(pipeline)) {
2611 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2612 AC_UD_SCRATCH_RING_OFFSETS);
2613 if (cmd_buffer->ring_offsets_idx == -1)
2614 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2615 else if (loc->sgpr_idx != -1)
2616 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2617 }
2618 break;
2619 default:
2620 assert(!"invalid bind point");
2621 break;
2622 }
2623 }
2624
2625 void radv_CmdSetViewport(
2626 VkCommandBuffer commandBuffer,
2627 uint32_t firstViewport,
2628 uint32_t viewportCount,
2629 const VkViewport* pViewports)
2630 {
2631 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2632 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2633
2634 assert(firstViewport < MAX_VIEWPORTS);
2635 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2636
2637 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2638 pViewports, viewportCount * sizeof(*pViewports));
2639
2640 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2641 }
2642
2643 void radv_CmdSetScissor(
2644 VkCommandBuffer commandBuffer,
2645 uint32_t firstScissor,
2646 uint32_t scissorCount,
2647 const VkRect2D* pScissors)
2648 {
2649 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2650 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2651
2652 assert(firstScissor < MAX_SCISSORS);
2653 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2654
2655 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2656 pScissors, scissorCount * sizeof(*pScissors));
2657 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2658 }
2659
2660 void radv_CmdSetLineWidth(
2661 VkCommandBuffer commandBuffer,
2662 float lineWidth)
2663 {
2664 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2665 cmd_buffer->state.dynamic.line_width = lineWidth;
2666 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2667 }
2668
2669 void radv_CmdSetDepthBias(
2670 VkCommandBuffer commandBuffer,
2671 float depthBiasConstantFactor,
2672 float depthBiasClamp,
2673 float depthBiasSlopeFactor)
2674 {
2675 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2676
2677 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2678 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2679 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2680
2681 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2682 }
2683
2684 void radv_CmdSetBlendConstants(
2685 VkCommandBuffer commandBuffer,
2686 const float blendConstants[4])
2687 {
2688 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2689
2690 memcpy(cmd_buffer->state.dynamic.blend_constants,
2691 blendConstants, sizeof(float) * 4);
2692
2693 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2694 }
2695
2696 void radv_CmdSetDepthBounds(
2697 VkCommandBuffer commandBuffer,
2698 float minDepthBounds,
2699 float maxDepthBounds)
2700 {
2701 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2702
2703 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2704 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2705
2706 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2707 }
2708
2709 void radv_CmdSetStencilCompareMask(
2710 VkCommandBuffer commandBuffer,
2711 VkStencilFaceFlags faceMask,
2712 uint32_t compareMask)
2713 {
2714 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2715
2716 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2717 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2718 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2719 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2720
2721 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2722 }
2723
2724 void radv_CmdSetStencilWriteMask(
2725 VkCommandBuffer commandBuffer,
2726 VkStencilFaceFlags faceMask,
2727 uint32_t writeMask)
2728 {
2729 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2730
2731 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2732 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2733 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2734 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2735
2736 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2737 }
2738
2739 void radv_CmdSetStencilReference(
2740 VkCommandBuffer commandBuffer,
2741 VkStencilFaceFlags faceMask,
2742 uint32_t reference)
2743 {
2744 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2745
2746 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2747 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2748 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2749 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2750
2751 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2752 }
2753
2754 void radv_CmdExecuteCommands(
2755 VkCommandBuffer commandBuffer,
2756 uint32_t commandBufferCount,
2757 const VkCommandBuffer* pCmdBuffers)
2758 {
2759 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2760
2761 assert(commandBufferCount > 0);
2762
2763 /* Emit pending flushes on primary prior to executing secondary */
2764 si_emit_cache_flush(primary);
2765
2766 for (uint32_t i = 0; i < commandBufferCount; i++) {
2767 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2768
2769 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2770 secondary->scratch_size_needed);
2771 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2772 secondary->compute_scratch_size_needed);
2773
2774 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2775 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2776 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2777 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2778 if (secondary->tess_rings_needed)
2779 primary->tess_rings_needed = true;
2780 if (secondary->sample_positions_needed)
2781 primary->sample_positions_needed = true;
2782
2783 if (secondary->ring_offsets_idx != -1) {
2784 if (primary->ring_offsets_idx == -1)
2785 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2786 else
2787 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2788 }
2789 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2790
2791
2792 /* When the secondary command buffer is compute only we don't
2793 * need to re-emit the current graphics pipeline.
2794 */
2795 if (secondary->state.emitted_pipeline) {
2796 primary->state.emitted_pipeline =
2797 secondary->state.emitted_pipeline;
2798 }
2799
2800 /* When the secondary command buffer is graphics only we don't
2801 * need to re-emit the current compute pipeline.
2802 */
2803 if (secondary->state.emitted_compute_pipeline) {
2804 primary->state.emitted_compute_pipeline =
2805 secondary->state.emitted_compute_pipeline;
2806 }
2807
2808 /* Only re-emit the draw packets when needed. */
2809 if (secondary->state.last_primitive_reset_en != -1) {
2810 primary->state.last_primitive_reset_en =
2811 secondary->state.last_primitive_reset_en;
2812 }
2813
2814 if (secondary->state.last_primitive_reset_index) {
2815 primary->state.last_primitive_reset_index =
2816 secondary->state.last_primitive_reset_index;
2817 }
2818
2819 if (secondary->state.last_ia_multi_vgt_param) {
2820 primary->state.last_ia_multi_vgt_param =
2821 secondary->state.last_ia_multi_vgt_param;
2822 }
2823 }
2824
2825 /* After executing commands from secondary buffers we have to dirty
2826 * some states.
2827 */
2828 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2829 RADV_CMD_DIRTY_INDEX_BUFFER |
2830 RADV_CMD_DIRTY_DYNAMIC_ALL;
2831 radv_mark_descriptor_sets_dirty(primary);
2832 }
2833
2834 VkResult radv_CreateCommandPool(
2835 VkDevice _device,
2836 const VkCommandPoolCreateInfo* pCreateInfo,
2837 const VkAllocationCallbacks* pAllocator,
2838 VkCommandPool* pCmdPool)
2839 {
2840 RADV_FROM_HANDLE(radv_device, device, _device);
2841 struct radv_cmd_pool *pool;
2842
2843 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2844 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2845 if (pool == NULL)
2846 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2847
2848 if (pAllocator)
2849 pool->alloc = *pAllocator;
2850 else
2851 pool->alloc = device->alloc;
2852
2853 list_inithead(&pool->cmd_buffers);
2854 list_inithead(&pool->free_cmd_buffers);
2855
2856 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2857
2858 *pCmdPool = radv_cmd_pool_to_handle(pool);
2859
2860 return VK_SUCCESS;
2861
2862 }
2863
2864 void radv_DestroyCommandPool(
2865 VkDevice _device,
2866 VkCommandPool commandPool,
2867 const VkAllocationCallbacks* pAllocator)
2868 {
2869 RADV_FROM_HANDLE(radv_device, device, _device);
2870 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2871
2872 if (!pool)
2873 return;
2874
2875 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2876 &pool->cmd_buffers, pool_link) {
2877 radv_cmd_buffer_destroy(cmd_buffer);
2878 }
2879
2880 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2881 &pool->free_cmd_buffers, pool_link) {
2882 radv_cmd_buffer_destroy(cmd_buffer);
2883 }
2884
2885 vk_free2(&device->alloc, pAllocator, pool);
2886 }
2887
2888 VkResult radv_ResetCommandPool(
2889 VkDevice device,
2890 VkCommandPool commandPool,
2891 VkCommandPoolResetFlags flags)
2892 {
2893 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2894 VkResult result;
2895
2896 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2897 &pool->cmd_buffers, pool_link) {
2898 result = radv_reset_cmd_buffer(cmd_buffer);
2899 if (result != VK_SUCCESS)
2900 return result;
2901 }
2902
2903 return VK_SUCCESS;
2904 }
2905
2906 void radv_TrimCommandPoolKHR(
2907 VkDevice device,
2908 VkCommandPool commandPool,
2909 VkCommandPoolTrimFlagsKHR flags)
2910 {
2911 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2912
2913 if (!pool)
2914 return;
2915
2916 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2917 &pool->free_cmd_buffers, pool_link) {
2918 radv_cmd_buffer_destroy(cmd_buffer);
2919 }
2920 }
2921
2922 void radv_CmdBeginRenderPass(
2923 VkCommandBuffer commandBuffer,
2924 const VkRenderPassBeginInfo* pRenderPassBegin,
2925 VkSubpassContents contents)
2926 {
2927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2928 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2929 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2930
2931 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2932 cmd_buffer->cs, 2048);
2933 MAYBE_UNUSED VkResult result;
2934
2935 cmd_buffer->state.framebuffer = framebuffer;
2936 cmd_buffer->state.pass = pass;
2937 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2938
2939 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2940 if (result != VK_SUCCESS)
2941 return;
2942
2943 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2944 assert(cmd_buffer->cs->cdw <= cdw_max);
2945
2946 radv_cmd_buffer_clear_subpass(cmd_buffer);
2947 }
2948
2949 void radv_CmdNextSubpass(
2950 VkCommandBuffer commandBuffer,
2951 VkSubpassContents contents)
2952 {
2953 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2954
2955 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2956
2957 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2958 2048);
2959
2960 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2961 radv_cmd_buffer_clear_subpass(cmd_buffer);
2962 }
2963
2964 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2965 {
2966 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2967 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2968 if (!pipeline->shaders[stage])
2969 continue;
2970 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2971 if (loc->sgpr_idx == -1)
2972 continue;
2973 uint32_t base_reg = pipeline->user_data_0[stage];
2974 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2975
2976 }
2977 if (pipeline->gs_copy_shader) {
2978 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2979 if (loc->sgpr_idx != -1) {
2980 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2981 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2982 }
2983 }
2984 }
2985
2986 static void
2987 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2988 uint32_t vertex_count)
2989 {
2990 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2991 radeon_emit(cmd_buffer->cs, vertex_count);
2992 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2993 S_0287F0_USE_OPAQUE(0));
2994 }
2995
2996 static void
2997 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2998 uint64_t index_va,
2999 uint32_t index_count)
3000 {
3001 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3002 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3003 radeon_emit(cmd_buffer->cs, index_va);
3004 radeon_emit(cmd_buffer->cs, index_va >> 32);
3005 radeon_emit(cmd_buffer->cs, index_count);
3006 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3007 }
3008
3009 static void
3010 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3011 bool indexed,
3012 uint32_t draw_count,
3013 uint64_t count_va,
3014 uint32_t stride)
3015 {
3016 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3017 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3018 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3019 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3020 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3021 assert(base_reg);
3022
3023 if (draw_count == 1 && !count_va && !draw_id_enable) {
3024 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3025 PKT3_DRAW_INDIRECT, 3, false));
3026 radeon_emit(cs, 0);
3027 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3028 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3029 radeon_emit(cs, di_src_sel);
3030 } else {
3031 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3032 PKT3_DRAW_INDIRECT_MULTI,
3033 8, false));
3034 radeon_emit(cs, 0);
3035 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3036 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3037 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3038 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3039 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3040 radeon_emit(cs, draw_count); /* count */
3041 radeon_emit(cs, count_va); /* count_addr */
3042 radeon_emit(cs, count_va >> 32);
3043 radeon_emit(cs, stride); /* stride */
3044 radeon_emit(cs, di_src_sel);
3045 }
3046 }
3047
3048 struct radv_draw_info {
3049 /**
3050 * Number of vertices.
3051 */
3052 uint32_t count;
3053
3054 /**
3055 * Index of the first vertex.
3056 */
3057 int32_t vertex_offset;
3058
3059 /**
3060 * First instance id.
3061 */
3062 uint32_t first_instance;
3063
3064 /**
3065 * Number of instances.
3066 */
3067 uint32_t instance_count;
3068
3069 /**
3070 * First index (indexed draws only).
3071 */
3072 uint32_t first_index;
3073
3074 /**
3075 * Whether it's an indexed draw.
3076 */
3077 bool indexed;
3078
3079 /**
3080 * Indirect draw parameters resource.
3081 */
3082 struct radv_buffer *indirect;
3083 uint64_t indirect_offset;
3084 uint32_t stride;
3085
3086 /**
3087 * Draw count parameters resource.
3088 */
3089 struct radv_buffer *count_buffer;
3090 uint64_t count_buffer_offset;
3091 };
3092
3093 static void
3094 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3095 const struct radv_draw_info *info)
3096 {
3097 struct radv_cmd_state *state = &cmd_buffer->state;
3098 struct radeon_winsys *ws = cmd_buffer->device->ws;
3099 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3100
3101 if (info->indirect) {
3102 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3103 uint64_t count_va = 0;
3104
3105 va += info->indirect->offset + info->indirect_offset;
3106
3107 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3108
3109 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3110 radeon_emit(cs, 1);
3111 radeon_emit(cs, va);
3112 radeon_emit(cs, va >> 32);
3113
3114 if (info->count_buffer) {
3115 count_va = radv_buffer_get_va(info->count_buffer->bo);
3116 count_va += info->count_buffer->offset +
3117 info->count_buffer_offset;
3118
3119 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3120 }
3121
3122 if (!state->subpass->view_mask) {
3123 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3124 info->indexed,
3125 info->count,
3126 count_va,
3127 info->stride);
3128 } else {
3129 unsigned i;
3130 for_each_bit(i, state->subpass->view_mask) {
3131 radv_emit_view_index(cmd_buffer, i);
3132
3133 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3134 info->indexed,
3135 info->count,
3136 count_va,
3137 info->stride);
3138 }
3139 }
3140 } else {
3141 assert(state->pipeline->graphics.vtx_base_sgpr);
3142 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3143 state->pipeline->graphics.vtx_emit_num);
3144 radeon_emit(cs, info->vertex_offset);
3145 radeon_emit(cs, info->first_instance);
3146 if (state->pipeline->graphics.vtx_emit_num == 3)
3147 radeon_emit(cs, 0);
3148
3149 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3150 radeon_emit(cs, info->instance_count);
3151
3152 if (info->indexed) {
3153 int index_size = state->index_type ? 4 : 2;
3154 uint64_t index_va;
3155
3156 index_va = state->index_va;
3157 index_va += info->first_index * index_size;
3158
3159 if (!state->subpass->view_mask) {
3160 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3161 index_va,
3162 info->count);
3163 } else {
3164 unsigned i;
3165 for_each_bit(i, state->subpass->view_mask) {
3166 radv_emit_view_index(cmd_buffer, i);
3167
3168 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3169 index_va,
3170 info->count);
3171 }
3172 }
3173 } else {
3174 if (!state->subpass->view_mask) {
3175 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3176 } else {
3177 unsigned i;
3178 for_each_bit(i, state->subpass->view_mask) {
3179 radv_emit_view_index(cmd_buffer, i);
3180
3181 radv_cs_emit_draw_packet(cmd_buffer,
3182 info->count);
3183 }
3184 }
3185 }
3186 }
3187 }
3188
3189 static void
3190 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3191 const struct radv_draw_info *info)
3192 {
3193 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3194 radv_emit_graphics_pipeline(cmd_buffer);
3195
3196 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3197 radv_emit_framebuffer_state(cmd_buffer);
3198
3199 if (info->indexed) {
3200 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3201 radv_emit_index_buffer(cmd_buffer);
3202 } else {
3203 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3204 * so the state must be re-emitted before the next indexed
3205 * draw.
3206 */
3207 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3208 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3209 }
3210
3211 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3212
3213 radv_emit_draw_registers(cmd_buffer, info->indexed,
3214 info->instance_count > 1, info->indirect,
3215 info->indirect ? 0 : info->count);
3216 }
3217
3218 static void
3219 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3220 const struct radv_draw_info *info)
3221 {
3222 bool pipeline_is_dirty =
3223 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3224 cmd_buffer->state.pipeline &&
3225 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3226
3227 MAYBE_UNUSED unsigned cdw_max =
3228 radeon_check_space(cmd_buffer->device->ws,
3229 cmd_buffer->cs, 4096);
3230
3231 /* Use optimal packet order based on whether we need to sync the
3232 * pipeline.
3233 */
3234 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3235 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3236 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3237 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3238 /* If we have to wait for idle, set all states first, so that
3239 * all SET packets are processed in parallel with previous draw
3240 * calls. Then upload descriptors, set shader pointers, and
3241 * draw, and prefetch at the end. This ensures that the time
3242 * the CUs are idle is very short. (there are only SET_SH
3243 * packets between the wait and the draw)
3244 */
3245 radv_emit_all_graphics_states(cmd_buffer, info);
3246 si_emit_cache_flush(cmd_buffer);
3247 /* <-- CUs are idle here --> */
3248
3249 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3250 return;
3251
3252 radv_emit_draw_packets(cmd_buffer, info);
3253 /* <-- CUs are busy here --> */
3254
3255 /* Start prefetches after the draw has been started. Both will
3256 * run in parallel, but starting the draw first is more
3257 * important.
3258 */
3259 if (pipeline_is_dirty) {
3260 radv_emit_prefetch(cmd_buffer,
3261 cmd_buffer->state.pipeline);
3262 }
3263 } else {
3264 /* If we don't wait for idle, start prefetches first, then set
3265 * states, and draw at the end.
3266 */
3267 si_emit_cache_flush(cmd_buffer);
3268
3269 if (pipeline_is_dirty) {
3270 radv_emit_prefetch(cmd_buffer,
3271 cmd_buffer->state.pipeline);
3272 }
3273
3274 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3275 return;
3276
3277 radv_emit_all_graphics_states(cmd_buffer, info);
3278 radv_emit_draw_packets(cmd_buffer, info);
3279 }
3280
3281 assert(cmd_buffer->cs->cdw <= cdw_max);
3282 radv_cmd_buffer_after_draw(cmd_buffer);
3283 }
3284
3285 void radv_CmdDraw(
3286 VkCommandBuffer commandBuffer,
3287 uint32_t vertexCount,
3288 uint32_t instanceCount,
3289 uint32_t firstVertex,
3290 uint32_t firstInstance)
3291 {
3292 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3293 struct radv_draw_info info = {};
3294
3295 info.count = vertexCount;
3296 info.instance_count = instanceCount;
3297 info.first_instance = firstInstance;
3298 info.vertex_offset = firstVertex;
3299
3300 radv_draw(cmd_buffer, &info);
3301 }
3302
3303 void radv_CmdDrawIndexed(
3304 VkCommandBuffer commandBuffer,
3305 uint32_t indexCount,
3306 uint32_t instanceCount,
3307 uint32_t firstIndex,
3308 int32_t vertexOffset,
3309 uint32_t firstInstance)
3310 {
3311 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3312 struct radv_draw_info info = {};
3313
3314 info.indexed = true;
3315 info.count = indexCount;
3316 info.instance_count = instanceCount;
3317 info.first_index = firstIndex;
3318 info.vertex_offset = vertexOffset;
3319 info.first_instance = firstInstance;
3320
3321 radv_draw(cmd_buffer, &info);
3322 }
3323
3324 void radv_CmdDrawIndirect(
3325 VkCommandBuffer commandBuffer,
3326 VkBuffer _buffer,
3327 VkDeviceSize offset,
3328 uint32_t drawCount,
3329 uint32_t stride)
3330 {
3331 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3332 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3333 struct radv_draw_info info = {};
3334
3335 info.count = drawCount;
3336 info.indirect = buffer;
3337 info.indirect_offset = offset;
3338 info.stride = stride;
3339
3340 radv_draw(cmd_buffer, &info);
3341 }
3342
3343 void radv_CmdDrawIndexedIndirect(
3344 VkCommandBuffer commandBuffer,
3345 VkBuffer _buffer,
3346 VkDeviceSize offset,
3347 uint32_t drawCount,
3348 uint32_t stride)
3349 {
3350 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3351 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3352 struct radv_draw_info info = {};
3353
3354 info.indexed = true;
3355 info.count = drawCount;
3356 info.indirect = buffer;
3357 info.indirect_offset = offset;
3358 info.stride = stride;
3359
3360 radv_draw(cmd_buffer, &info);
3361 }
3362
3363 void radv_CmdDrawIndirectCountAMD(
3364 VkCommandBuffer commandBuffer,
3365 VkBuffer _buffer,
3366 VkDeviceSize offset,
3367 VkBuffer _countBuffer,
3368 VkDeviceSize countBufferOffset,
3369 uint32_t maxDrawCount,
3370 uint32_t stride)
3371 {
3372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3373 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3374 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3375 struct radv_draw_info info = {};
3376
3377 info.count = maxDrawCount;
3378 info.indirect = buffer;
3379 info.indirect_offset = offset;
3380 info.count_buffer = count_buffer;
3381 info.count_buffer_offset = countBufferOffset;
3382 info.stride = stride;
3383
3384 radv_draw(cmd_buffer, &info);
3385 }
3386
3387 void radv_CmdDrawIndexedIndirectCountAMD(
3388 VkCommandBuffer commandBuffer,
3389 VkBuffer _buffer,
3390 VkDeviceSize offset,
3391 VkBuffer _countBuffer,
3392 VkDeviceSize countBufferOffset,
3393 uint32_t maxDrawCount,
3394 uint32_t stride)
3395 {
3396 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3397 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3398 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3399 struct radv_draw_info info = {};
3400
3401 info.indexed = true;
3402 info.count = maxDrawCount;
3403 info.indirect = buffer;
3404 info.indirect_offset = offset;
3405 info.count_buffer = count_buffer;
3406 info.count_buffer_offset = countBufferOffset;
3407 info.stride = stride;
3408
3409 radv_draw(cmd_buffer, &info);
3410 }
3411
3412 struct radv_dispatch_info {
3413 /**
3414 * Determine the layout of the grid (in block units) to be used.
3415 */
3416 uint32_t blocks[3];
3417
3418 /**
3419 * Whether it's an unaligned compute dispatch.
3420 */
3421 bool unaligned;
3422
3423 /**
3424 * Indirect compute parameters resource.
3425 */
3426 struct radv_buffer *indirect;
3427 uint64_t indirect_offset;
3428 };
3429
3430 static void
3431 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3432 const struct radv_dispatch_info *info)
3433 {
3434 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3435 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3436 struct radeon_winsys *ws = cmd_buffer->device->ws;
3437 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3438 struct ac_userdata_info *loc;
3439 unsigned dispatch_initiator;
3440 uint8_t grid_used;
3441
3442 grid_used = compute_shader->info.info.cs.grid_components_used;
3443
3444 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3445 AC_UD_CS_GRID_SIZE);
3446
3447 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3448
3449 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3450 S_00B800_FORCE_START_AT_000(1);
3451
3452 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3453 /* If the KMD allows it (there is a KMD hw register for it),
3454 * allow launching waves out-of-order.
3455 */
3456 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3457 }
3458
3459 if (info->indirect) {
3460 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3461
3462 va += info->indirect->offset + info->indirect_offset;
3463
3464 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3465
3466 if (loc->sgpr_idx != -1) {
3467 for (unsigned i = 0; i < grid_used; ++i) {
3468 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3469 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3470 COPY_DATA_DST_SEL(COPY_DATA_REG));
3471 radeon_emit(cs, (va + 4 * i));
3472 radeon_emit(cs, (va + 4 * i) >> 32);
3473 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3474 + loc->sgpr_idx * 4) >> 2) + i);
3475 radeon_emit(cs, 0);
3476 }
3477 }
3478
3479 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3480 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3481 PKT3_SHADER_TYPE_S(1));
3482 radeon_emit(cs, va);
3483 radeon_emit(cs, va >> 32);
3484 radeon_emit(cs, dispatch_initiator);
3485 } else {
3486 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3487 PKT3_SHADER_TYPE_S(1));
3488 radeon_emit(cs, 1);
3489 radeon_emit(cs, va);
3490 radeon_emit(cs, va >> 32);
3491
3492 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3493 PKT3_SHADER_TYPE_S(1));
3494 radeon_emit(cs, 0);
3495 radeon_emit(cs, dispatch_initiator);
3496 }
3497 } else {
3498 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3499
3500 if (info->unaligned) {
3501 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3502 unsigned remainder[3];
3503
3504 /* If aligned, these should be an entire block size,
3505 * not 0.
3506 */
3507 remainder[0] = blocks[0] + cs_block_size[0] -
3508 align_u32_npot(blocks[0], cs_block_size[0]);
3509 remainder[1] = blocks[1] + cs_block_size[1] -
3510 align_u32_npot(blocks[1], cs_block_size[1]);
3511 remainder[2] = blocks[2] + cs_block_size[2] -
3512 align_u32_npot(blocks[2], cs_block_size[2]);
3513
3514 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3515 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3516 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3517
3518 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3519 radeon_emit(cs,
3520 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3521 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3522 radeon_emit(cs,
3523 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3524 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3525 radeon_emit(cs,
3526 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3527 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3528
3529 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3530 }
3531
3532 if (loc->sgpr_idx != -1) {
3533 assert(!loc->indirect);
3534 assert(loc->num_sgprs == grid_used);
3535
3536 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3537 loc->sgpr_idx * 4, grid_used);
3538 radeon_emit(cs, blocks[0]);
3539 if (grid_used > 1)
3540 radeon_emit(cs, blocks[1]);
3541 if (grid_used > 2)
3542 radeon_emit(cs, blocks[2]);
3543 }
3544
3545 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3546 PKT3_SHADER_TYPE_S(1));
3547 radeon_emit(cs, blocks[0]);
3548 radeon_emit(cs, blocks[1]);
3549 radeon_emit(cs, blocks[2]);
3550 radeon_emit(cs, dispatch_initiator);
3551 }
3552
3553 assert(cmd_buffer->cs->cdw <= cdw_max);
3554 }
3555
3556 static void
3557 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3558 {
3559 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3560 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3561 VK_SHADER_STAGE_COMPUTE_BIT);
3562 }
3563
3564 static void
3565 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3566 const struct radv_dispatch_info *info)
3567 {
3568 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3569 bool pipeline_is_dirty = pipeline &&
3570 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3571
3572 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3573 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3574 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3575 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3576 /* If we have to wait for idle, set all states first, so that
3577 * all SET packets are processed in parallel with previous draw
3578 * calls. Then upload descriptors, set shader pointers, and
3579 * dispatch, and prefetch at the end. This ensures that the
3580 * time the CUs are idle is very short. (there are only SET_SH
3581 * packets between the wait and the draw)
3582 */
3583 radv_emit_compute_pipeline(cmd_buffer);
3584 si_emit_cache_flush(cmd_buffer);
3585 /* <-- CUs are idle here --> */
3586
3587 radv_upload_compute_shader_descriptors(cmd_buffer);
3588
3589 radv_emit_dispatch_packets(cmd_buffer, info);
3590 /* <-- CUs are busy here --> */
3591
3592 /* Start prefetches after the dispatch has been started. Both
3593 * will run in parallel, but starting the dispatch first is
3594 * more important.
3595 */
3596 if (pipeline_is_dirty) {
3597 radv_emit_shader_prefetch(cmd_buffer,
3598 pipeline->shaders[MESA_SHADER_COMPUTE]);
3599 }
3600 } else {
3601 /* If we don't wait for idle, start prefetches first, then set
3602 * states, and dispatch at the end.
3603 */
3604 si_emit_cache_flush(cmd_buffer);
3605
3606 if (pipeline_is_dirty) {
3607 radv_emit_shader_prefetch(cmd_buffer,
3608 pipeline->shaders[MESA_SHADER_COMPUTE]);
3609 }
3610
3611 radv_upload_compute_shader_descriptors(cmd_buffer);
3612
3613 radv_emit_compute_pipeline(cmd_buffer);
3614 radv_emit_dispatch_packets(cmd_buffer, info);
3615 }
3616
3617 radv_cmd_buffer_after_draw(cmd_buffer);
3618 }
3619
3620 void radv_CmdDispatch(
3621 VkCommandBuffer commandBuffer,
3622 uint32_t x,
3623 uint32_t y,
3624 uint32_t z)
3625 {
3626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3627 struct radv_dispatch_info info = {};
3628
3629 info.blocks[0] = x;
3630 info.blocks[1] = y;
3631 info.blocks[2] = z;
3632
3633 radv_dispatch(cmd_buffer, &info);
3634 }
3635
3636 void radv_CmdDispatchIndirect(
3637 VkCommandBuffer commandBuffer,
3638 VkBuffer _buffer,
3639 VkDeviceSize offset)
3640 {
3641 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3642 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3643 struct radv_dispatch_info info = {};
3644
3645 info.indirect = buffer;
3646 info.indirect_offset = offset;
3647
3648 radv_dispatch(cmd_buffer, &info);
3649 }
3650
3651 void radv_unaligned_dispatch(
3652 struct radv_cmd_buffer *cmd_buffer,
3653 uint32_t x,
3654 uint32_t y,
3655 uint32_t z)
3656 {
3657 struct radv_dispatch_info info = {};
3658
3659 info.blocks[0] = x;
3660 info.blocks[1] = y;
3661 info.blocks[2] = z;
3662 info.unaligned = 1;
3663
3664 radv_dispatch(cmd_buffer, &info);
3665 }
3666
3667 void radv_CmdEndRenderPass(
3668 VkCommandBuffer commandBuffer)
3669 {
3670 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3671
3672 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3673
3674 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3675
3676 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3677 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3678 radv_handle_subpass_image_transition(cmd_buffer,
3679 (VkAttachmentReference){i, layout});
3680 }
3681
3682 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3683
3684 cmd_buffer->state.pass = NULL;
3685 cmd_buffer->state.subpass = NULL;
3686 cmd_buffer->state.attachments = NULL;
3687 cmd_buffer->state.framebuffer = NULL;
3688 }
3689
3690 /*
3691 * For HTILE we have the following interesting clear words:
3692 * 0x0000030f: Uncompressed.
3693 * 0xfffffff0: Clear depth to 1.0
3694 * 0x00000000: Clear depth to 0.0
3695 */
3696 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3697 struct radv_image *image,
3698 const VkImageSubresourceRange *range,
3699 uint32_t clear_word)
3700 {
3701 assert(range->baseMipLevel == 0);
3702 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3703 unsigned layer_count = radv_get_layerCount(image, range);
3704 uint64_t size = image->surface.htile_slice_size * layer_count;
3705 uint64_t offset = image->offset + image->htile_offset +
3706 image->surface.htile_slice_size * range->baseArrayLayer;
3707 struct radv_cmd_state *state = &cmd_buffer->state;
3708
3709 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3710 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3711
3712 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3713 size, clear_word);
3714
3715 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3716 }
3717
3718 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3719 struct radv_image *image,
3720 VkImageLayout src_layout,
3721 VkImageLayout dst_layout,
3722 unsigned src_queue_mask,
3723 unsigned dst_queue_mask,
3724 const VkImageSubresourceRange *range,
3725 VkImageAspectFlags pending_clears)
3726 {
3727 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3728 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3729 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3730 cmd_buffer->state.render_area.extent.width == image->info.width &&
3731 cmd_buffer->state.render_area.extent.height == image->info.height) {
3732 /* The clear will initialize htile. */
3733 return;
3734 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3735 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3736 /* TODO: merge with the clear if applicable */
3737 radv_initialize_htile(cmd_buffer, image, range, 0);
3738 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3739 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3740 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3741 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3742 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3743 VkImageSubresourceRange local_range = *range;
3744 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3745 local_range.baseMipLevel = 0;
3746 local_range.levelCount = 1;
3747
3748 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3749 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3750
3751 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3752
3753 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3754 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3755 }
3756 }
3757
3758 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3759 struct radv_image *image, uint32_t value)
3760 {
3761 struct radv_cmd_state *state = &cmd_buffer->state;
3762
3763 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3764 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3765
3766 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3767 image->offset + image->cmask.offset,
3768 image->cmask.size, value);
3769
3770 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3771 }
3772
3773 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3774 struct radv_image *image,
3775 VkImageLayout src_layout,
3776 VkImageLayout dst_layout,
3777 unsigned src_queue_mask,
3778 unsigned dst_queue_mask,
3779 const VkImageSubresourceRange *range)
3780 {
3781 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3782 if (image->fmask.size)
3783 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3784 else
3785 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3786 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3787 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3788 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3789 }
3790 }
3791
3792 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3793 struct radv_image *image, uint32_t value)
3794 {
3795 struct radv_cmd_state *state = &cmd_buffer->state;
3796
3797 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3798 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3799
3800 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3801 image->offset + image->dcc_offset,
3802 image->surface.dcc_size, value);
3803
3804 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3805 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3806 }
3807
3808 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3809 struct radv_image *image,
3810 VkImageLayout src_layout,
3811 VkImageLayout dst_layout,
3812 unsigned src_queue_mask,
3813 unsigned dst_queue_mask,
3814 const VkImageSubresourceRange *range)
3815 {
3816 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3817 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3818 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3819 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3820 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3821 }
3822 }
3823
3824 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3825 struct radv_image *image,
3826 VkImageLayout src_layout,
3827 VkImageLayout dst_layout,
3828 uint32_t src_family,
3829 uint32_t dst_family,
3830 const VkImageSubresourceRange *range,
3831 VkImageAspectFlags pending_clears)
3832 {
3833 if (image->exclusive && src_family != dst_family) {
3834 /* This is an acquire or a release operation and there will be
3835 * a corresponding release/acquire. Do the transition in the
3836 * most flexible queue. */
3837
3838 assert(src_family == cmd_buffer->queue_family_index ||
3839 dst_family == cmd_buffer->queue_family_index);
3840
3841 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3842 return;
3843
3844 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3845 (src_family == RADV_QUEUE_GENERAL ||
3846 dst_family == RADV_QUEUE_GENERAL))
3847 return;
3848 }
3849
3850 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3851 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3852
3853 if (image->surface.htile_size)
3854 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3855 dst_layout, src_queue_mask,
3856 dst_queue_mask, range,
3857 pending_clears);
3858
3859 if (image->cmask.size || image->fmask.size)
3860 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3861 dst_layout, src_queue_mask,
3862 dst_queue_mask, range);
3863
3864 if (image->surface.dcc_size)
3865 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3866 dst_layout, src_queue_mask,
3867 dst_queue_mask, range);
3868 }
3869
3870 void radv_CmdPipelineBarrier(
3871 VkCommandBuffer commandBuffer,
3872 VkPipelineStageFlags srcStageMask,
3873 VkPipelineStageFlags destStageMask,
3874 VkBool32 byRegion,
3875 uint32_t memoryBarrierCount,
3876 const VkMemoryBarrier* pMemoryBarriers,
3877 uint32_t bufferMemoryBarrierCount,
3878 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3879 uint32_t imageMemoryBarrierCount,
3880 const VkImageMemoryBarrier* pImageMemoryBarriers)
3881 {
3882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3883 enum radv_cmd_flush_bits src_flush_bits = 0;
3884 enum radv_cmd_flush_bits dst_flush_bits = 0;
3885
3886 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3887 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3888 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3889 NULL);
3890 }
3891
3892 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3893 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3894 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3895 NULL);
3896 }
3897
3898 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3899 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3900 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3901 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3902 image);
3903 }
3904
3905 radv_stage_flush(cmd_buffer, srcStageMask);
3906 cmd_buffer->state.flush_bits |= src_flush_bits;
3907
3908 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3909 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3910 radv_handle_image_transition(cmd_buffer, image,
3911 pImageMemoryBarriers[i].oldLayout,
3912 pImageMemoryBarriers[i].newLayout,
3913 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3914 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3915 &pImageMemoryBarriers[i].subresourceRange,
3916 0);
3917 }
3918
3919 cmd_buffer->state.flush_bits |= dst_flush_bits;
3920 }
3921
3922
3923 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3924 struct radv_event *event,
3925 VkPipelineStageFlags stageMask,
3926 unsigned value)
3927 {
3928 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3929 uint64_t va = radv_buffer_get_va(event->bo);
3930
3931 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3932
3933 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3934
3935 /* TODO: this is overkill. Probably should figure something out from
3936 * the stage mask. */
3937
3938 si_cs_emit_write_event_eop(cs,
3939 cmd_buffer->state.predicating,
3940 cmd_buffer->device->physical_device->rad_info.chip_class,
3941 false,
3942 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3943 1, va, 2, value);
3944
3945 assert(cmd_buffer->cs->cdw <= cdw_max);
3946 }
3947
3948 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3949 VkEvent _event,
3950 VkPipelineStageFlags stageMask)
3951 {
3952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3953 RADV_FROM_HANDLE(radv_event, event, _event);
3954
3955 write_event(cmd_buffer, event, stageMask, 1);
3956 }
3957
3958 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3959 VkEvent _event,
3960 VkPipelineStageFlags stageMask)
3961 {
3962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3963 RADV_FROM_HANDLE(radv_event, event, _event);
3964
3965 write_event(cmd_buffer, event, stageMask, 0);
3966 }
3967
3968 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3969 uint32_t eventCount,
3970 const VkEvent* pEvents,
3971 VkPipelineStageFlags srcStageMask,
3972 VkPipelineStageFlags dstStageMask,
3973 uint32_t memoryBarrierCount,
3974 const VkMemoryBarrier* pMemoryBarriers,
3975 uint32_t bufferMemoryBarrierCount,
3976 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3977 uint32_t imageMemoryBarrierCount,
3978 const VkImageMemoryBarrier* pImageMemoryBarriers)
3979 {
3980 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3981 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3982
3983 for (unsigned i = 0; i < eventCount; ++i) {
3984 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3985 uint64_t va = radv_buffer_get_va(event->bo);
3986
3987 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3988
3989 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3990
3991 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3992 assert(cmd_buffer->cs->cdw <= cdw_max);
3993 }
3994
3995
3996 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3997 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3998
3999 radv_handle_image_transition(cmd_buffer, image,
4000 pImageMemoryBarriers[i].oldLayout,
4001 pImageMemoryBarriers[i].newLayout,
4002 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4003 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4004 &pImageMemoryBarriers[i].subresourceRange,
4005 0);
4006 }
4007
4008 /* TODO: figure out how to do memory barriers without waiting */
4009 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4010 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4011 RADV_CMD_FLAG_INV_VMEM_L1 |
4012 RADV_CMD_FLAG_INV_SMEM_L1;
4013 }