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1e5e28341358eec900d5c65a9f8698ccfd542aec
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_needed = 0;
336 cmd_buffer->compute_scratch_size_needed = 0;
337 cmd_buffer->esgs_ring_size_needed = 0;
338 cmd_buffer->gsvs_ring_size_needed = 0;
339 cmd_buffer->tess_rings_needed = false;
340 cmd_buffer->gds_needed = false;
341 cmd_buffer->sample_positions_needed = false;
342
343 if (cmd_buffer->upload.upload_bo)
344 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
345 cmd_buffer->upload.upload_bo);
346 cmd_buffer->upload.offset = 0;
347
348 cmd_buffer->record_result = VK_SUCCESS;
349
350 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
351
352 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
353 cmd_buffer->descriptors[i].dirty = 0;
354 cmd_buffer->descriptors[i].valid = 0;
355 cmd_buffer->descriptors[i].push_dirty = false;
356 }
357
358 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
359 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
360 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
361 unsigned fence_offset, eop_bug_offset;
362 void *fence_ptr;
363
364 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
365 &fence_ptr);
366
367 cmd_buffer->gfx9_fence_va =
368 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
369 cmd_buffer->gfx9_fence_va += fence_offset;
370
371 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
372 /* Allocate a buffer for the EOP bug on GFX9. */
373 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
374 &eop_bug_offset, &fence_ptr);
375 cmd_buffer->gfx9_eop_bug_va =
376 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
377 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
378 }
379 }
380
381 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
382
383 return cmd_buffer->record_result;
384 }
385
386 static bool
387 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
388 uint64_t min_needed)
389 {
390 uint64_t new_size;
391 struct radeon_winsys_bo *bo;
392 struct radv_cmd_buffer_upload *upload;
393 struct radv_device *device = cmd_buffer->device;
394
395 new_size = MAX2(min_needed, 16 * 1024);
396 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
397
398 bo = device->ws->buffer_create(device->ws,
399 new_size, 4096,
400 RADEON_DOMAIN_GTT,
401 RADEON_FLAG_CPU_ACCESS|
402 RADEON_FLAG_NO_INTERPROCESS_SHARING |
403 RADEON_FLAG_32BIT,
404 RADV_BO_PRIORITY_UPLOAD_BUFFER);
405
406 if (!bo) {
407 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
408 return false;
409 }
410
411 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
412 if (cmd_buffer->upload.upload_bo) {
413 upload = malloc(sizeof(*upload));
414
415 if (!upload) {
416 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
417 device->ws->buffer_destroy(bo);
418 return false;
419 }
420
421 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
422 list_add(&upload->list, &cmd_buffer->upload.list);
423 }
424
425 cmd_buffer->upload.upload_bo = bo;
426 cmd_buffer->upload.size = new_size;
427 cmd_buffer->upload.offset = 0;
428 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
429
430 if (!cmd_buffer->upload.map) {
431 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
432 return false;
433 }
434
435 return true;
436 }
437
438 bool
439 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
440 unsigned size,
441 unsigned alignment,
442 unsigned *out_offset,
443 void **ptr)
444 {
445 assert(util_is_power_of_two_nonzero(alignment));
446
447 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
448 if (offset + size > cmd_buffer->upload.size) {
449 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
450 return false;
451 offset = 0;
452 }
453
454 *out_offset = offset;
455 *ptr = cmd_buffer->upload.map + offset;
456
457 cmd_buffer->upload.offset = offset + size;
458 return true;
459 }
460
461 bool
462 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
463 unsigned size, unsigned alignment,
464 const void *data, unsigned *out_offset)
465 {
466 uint8_t *ptr;
467
468 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
469 out_offset, (void **)&ptr))
470 return false;
471
472 if (ptr)
473 memcpy(ptr, data, size);
474
475 return true;
476 }
477
478 static void
479 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
480 unsigned count, const uint32_t *data)
481 {
482 struct radeon_cmdbuf *cs = cmd_buffer->cs;
483
484 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
485
486 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
487 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
488 S_370_WR_CONFIRM(1) |
489 S_370_ENGINE_SEL(V_370_ME));
490 radeon_emit(cs, va);
491 radeon_emit(cs, va >> 32);
492 radeon_emit_array(cs, data, count);
493 }
494
495 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
496 {
497 struct radv_device *device = cmd_buffer->device;
498 struct radeon_cmdbuf *cs = cmd_buffer->cs;
499 uint64_t va;
500
501 va = radv_buffer_get_va(device->trace_bo);
502 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
503 va += 4;
504
505 ++cmd_buffer->state.trace_id;
506 radv_emit_write_data_packet(cmd_buffer, va, 1,
507 &cmd_buffer->state.trace_id);
508
509 radeon_check_space(cmd_buffer->device->ws, cs, 2);
510
511 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
512 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
513 }
514
515 static void
516 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
517 enum radv_cmd_flush_bits flags)
518 {
519 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
520 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
521 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
522
523 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
524
525 /* Force wait for graphics or compute engines to be idle. */
526 si_cs_emit_cache_flush(cmd_buffer->cs,
527 cmd_buffer->device->physical_device->rad_info.chip_class,
528 &cmd_buffer->gfx9_fence_idx,
529 cmd_buffer->gfx9_fence_va,
530 radv_cmd_buffer_uses_mec(cmd_buffer),
531 flags, cmd_buffer->gfx9_eop_bug_va);
532 }
533
534 if (unlikely(cmd_buffer->device->trace_bo))
535 radv_cmd_buffer_trace_emit(cmd_buffer);
536 }
537
538 static void
539 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
540 struct radv_pipeline *pipeline, enum ring_type ring)
541 {
542 struct radv_device *device = cmd_buffer->device;
543 uint32_t data[2];
544 uint64_t va;
545
546 va = radv_buffer_get_va(device->trace_bo);
547
548 switch (ring) {
549 case RING_GFX:
550 va += 8;
551 break;
552 case RING_COMPUTE:
553 va += 16;
554 break;
555 default:
556 assert(!"invalid ring type");
557 }
558
559 uint64_t pipeline_address = (uintptr_t)pipeline;
560 data[0] = pipeline_address;
561 data[1] = pipeline_address >> 32;
562
563 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
564 }
565
566 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
567 VkPipelineBindPoint bind_point,
568 struct radv_descriptor_set *set,
569 unsigned idx)
570 {
571 struct radv_descriptor_state *descriptors_state =
572 radv_get_descriptors_state(cmd_buffer, bind_point);
573
574 descriptors_state->sets[idx] = set;
575
576 descriptors_state->valid |= (1u << idx); /* active descriptors */
577 descriptors_state->dirty |= (1u << idx);
578 }
579
580 static void
581 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
582 VkPipelineBindPoint bind_point)
583 {
584 struct radv_descriptor_state *descriptors_state =
585 radv_get_descriptors_state(cmd_buffer, bind_point);
586 struct radv_device *device = cmd_buffer->device;
587 uint32_t data[MAX_SETS * 2] = {};
588 uint64_t va;
589 unsigned i;
590 va = radv_buffer_get_va(device->trace_bo) + 24;
591
592 for_each_bit(i, descriptors_state->valid) {
593 struct radv_descriptor_set *set = descriptors_state->sets[i];
594 data[i * 2] = (uint64_t)(uintptr_t)set;
595 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
596 }
597
598 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
599 }
600
601 struct radv_userdata_info *
602 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
603 gl_shader_stage stage,
604 int idx)
605 {
606 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
607 return &shader->info.user_sgprs_locs.shader_data[idx];
608 }
609
610 static void
611 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
612 struct radv_pipeline *pipeline,
613 gl_shader_stage stage,
614 int idx, uint64_t va)
615 {
616 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
617 uint32_t base_reg = pipeline->user_data_0[stage];
618 if (loc->sgpr_idx == -1)
619 return;
620
621 assert(loc->num_sgprs == 1);
622
623 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
624 base_reg + loc->sgpr_idx * 4, va, false);
625 }
626
627 static void
628 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline,
630 struct radv_descriptor_state *descriptors_state,
631 gl_shader_stage stage)
632 {
633 struct radv_device *device = cmd_buffer->device;
634 struct radeon_cmdbuf *cs = cmd_buffer->cs;
635 uint32_t sh_base = pipeline->user_data_0[stage];
636 struct radv_userdata_locations *locs =
637 &pipeline->shaders[stage]->info.user_sgprs_locs;
638 unsigned mask = locs->descriptor_sets_enabled;
639
640 mask &= descriptors_state->dirty & descriptors_state->valid;
641
642 while (mask) {
643 int start, count;
644
645 u_bit_scan_consecutive_range(&mask, &start, &count);
646
647 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
648 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
649
650 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
651 for (int i = 0; i < count; i++) {
652 struct radv_descriptor_set *set =
653 descriptors_state->sets[start + i];
654
655 radv_emit_shader_pointer_body(device, cs, set->va, true);
656 }
657 }
658 }
659
660 /**
661 * Convert the user sample locations to hardware sample locations (the values
662 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
663 */
664 static void
665 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
666 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
667 {
668 uint32_t x_offset = x % state->grid_size.width;
669 uint32_t y_offset = y % state->grid_size.height;
670 uint32_t num_samples = (uint32_t)state->per_pixel;
671 VkSampleLocationEXT *user_locs;
672 uint32_t pixel_offset;
673
674 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
675
676 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
677 user_locs = &state->locations[pixel_offset];
678
679 for (uint32_t i = 0; i < num_samples; i++) {
680 float shifted_pos_x = user_locs[i].x - 0.5;
681 float shifted_pos_y = user_locs[i].y - 0.5;
682
683 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
684 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
685
686 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
687 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
688 }
689 }
690
691 /**
692 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
693 * locations.
694 */
695 static void
696 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
697 uint32_t *sample_locs_pixel)
698 {
699 for (uint32_t i = 0; i < num_samples; i++) {
700 uint32_t sample_reg_idx = i / 4;
701 uint32_t sample_loc_idx = i % 4;
702 int32_t pos_x = sample_locs[i].x;
703 int32_t pos_y = sample_locs[i].y;
704
705 uint32_t shift_x = 8 * sample_loc_idx;
706 uint32_t shift_y = shift_x + 4;
707
708 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
709 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
710 }
711 }
712
713 /**
714 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
715 * sample locations.
716 */
717 static uint64_t
718 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
719 VkOffset2D *sample_locs,
720 uint32_t num_samples)
721 {
722 uint32_t centroid_priorities[num_samples];
723 uint32_t sample_mask = num_samples - 1;
724 uint32_t distances[num_samples];
725 uint64_t centroid_priority = 0;
726
727 /* Compute the distances from center for each sample. */
728 for (int i = 0; i < num_samples; i++) {
729 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
730 (sample_locs[i].y * sample_locs[i].y);
731 }
732
733 /* Compute the centroid priorities by looking at the distances array. */
734 for (int i = 0; i < num_samples; i++) {
735 uint32_t min_idx = 0;
736
737 for (int j = 1; j < num_samples; j++) {
738 if (distances[j] < distances[min_idx])
739 min_idx = j;
740 }
741
742 centroid_priorities[i] = min_idx;
743 distances[min_idx] = 0xffffffff;
744 }
745
746 /* Compute the final centroid priority. */
747 for (int i = 0; i < 8; i++) {
748 centroid_priority |=
749 centroid_priorities[i & sample_mask] << (i * 4);
750 }
751
752 return centroid_priority << 32 | centroid_priority;
753 }
754
755 /**
756 * Emit the sample locations that are specified with VK_EXT_sample_locations.
757 */
758 static void
759 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
760 {
761 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
762 struct radv_multisample_state *ms = &pipeline->graphics.ms;
763 struct radv_sample_locations_state *sample_location =
764 &cmd_buffer->state.dynamic.sample_location;
765 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
766 struct radeon_cmdbuf *cs = cmd_buffer->cs;
767 uint32_t sample_locs_pixel[4][2] = {};
768 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
769 uint32_t max_sample_dist = 0;
770 uint64_t centroid_priority;
771
772 if (!cmd_buffer->state.dynamic.sample_location.count)
773 return;
774
775 /* Convert the user sample locations to hardware sample locations. */
776 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
777 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
778 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
779 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
780
781 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
782 for (uint32_t i = 0; i < 4; i++) {
783 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
784 sample_locs_pixel[i]);
785 }
786
787 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
788 centroid_priority =
789 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
790 num_samples);
791
792 /* Compute the maximum sample distance from the specified locations. */
793 for (uint32_t i = 0; i < num_samples; i++) {
794 VkOffset2D offset = sample_locs[0][i];
795 max_sample_dist = MAX2(max_sample_dist,
796 MAX2(abs(offset.x), abs(offset.y)));
797 }
798
799 /* Emit the specified user sample locations. */
800 switch (num_samples) {
801 case 2:
802 case 4:
803 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
804 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
805 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
806 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
807 break;
808 case 8:
809 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
810 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
811 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
812 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
813 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
814 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
815 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
816 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
817 break;
818 default:
819 unreachable("invalid number of samples");
820 }
821
822 /* Emit the maximum sample distance and the centroid priority. */
823 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
824
825 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
826 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
827
828 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
829 radeon_emit(cs, pa_sc_aa_config);
830
831 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
832 radeon_emit(cs, centroid_priority);
833 radeon_emit(cs, centroid_priority >> 32);
834
835 /* GFX9: Flush DFSM when the AA mode changes. */
836 if (cmd_buffer->device->dfsm_allowed) {
837 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
838 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
839 }
840
841 cmd_buffer->state.context_roll_without_scissor_emitted = true;
842 }
843
844 static void
845 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
846 struct radv_pipeline *pipeline,
847 gl_shader_stage stage,
848 int idx, int count, uint32_t *values)
849 {
850 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
851 uint32_t base_reg = pipeline->user_data_0[stage];
852 if (loc->sgpr_idx == -1)
853 return;
854
855 assert(loc->num_sgprs == count);
856
857 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
858 radeon_emit_array(cmd_buffer->cs, values, count);
859 }
860
861 static void
862 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
863 struct radv_pipeline *pipeline)
864 {
865 int num_samples = pipeline->graphics.ms.num_samples;
866 struct radv_multisample_state *ms = &pipeline->graphics.ms;
867 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
868
869 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
870 cmd_buffer->sample_positions_needed = true;
871
872 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
873 return;
874
875 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
876 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
877 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
878
879 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
880
881 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
882
883 /* GFX9: Flush DFSM when the AA mode changes. */
884 if (cmd_buffer->device->dfsm_allowed) {
885 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
886 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
887 }
888
889 cmd_buffer->state.context_roll_without_scissor_emitted = true;
890 }
891
892 static void
893 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
894 struct radv_pipeline *pipeline)
895 {
896 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
897
898
899 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
900 return;
901
902 if (old_pipeline &&
903 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
904 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
905 return;
906
907 bool binning_flush = false;
908 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
909 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
910 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
911 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
912 binning_flush = !old_pipeline ||
913 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
914 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
915 }
916
917 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
918 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
919 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
920
921 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
922 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
923 pipeline->graphics.binning.db_dfsm_control);
924 } else {
925 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
926 pipeline->graphics.binning.db_dfsm_control);
927 }
928
929 cmd_buffer->state.context_roll_without_scissor_emitted = true;
930 }
931
932
933 static void
934 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
935 struct radv_shader_variant *shader)
936 {
937 uint64_t va;
938
939 if (!shader)
940 return;
941
942 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
943
944 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
945 }
946
947 static void
948 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
949 struct radv_pipeline *pipeline,
950 bool vertex_stage_only)
951 {
952 struct radv_cmd_state *state = &cmd_buffer->state;
953 uint32_t mask = state->prefetch_L2_mask;
954
955 if (vertex_stage_only) {
956 /* Fast prefetch path for starting draws as soon as possible.
957 */
958 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
959 RADV_PREFETCH_VBO_DESCRIPTORS);
960 }
961
962 if (mask & RADV_PREFETCH_VS)
963 radv_emit_shader_prefetch(cmd_buffer,
964 pipeline->shaders[MESA_SHADER_VERTEX]);
965
966 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
967 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
968
969 if (mask & RADV_PREFETCH_TCS)
970 radv_emit_shader_prefetch(cmd_buffer,
971 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
972
973 if (mask & RADV_PREFETCH_TES)
974 radv_emit_shader_prefetch(cmd_buffer,
975 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
976
977 if (mask & RADV_PREFETCH_GS) {
978 radv_emit_shader_prefetch(cmd_buffer,
979 pipeline->shaders[MESA_SHADER_GEOMETRY]);
980 if (radv_pipeline_has_gs_copy_shader(pipeline))
981 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
982 }
983
984 if (mask & RADV_PREFETCH_PS)
985 radv_emit_shader_prefetch(cmd_buffer,
986 pipeline->shaders[MESA_SHADER_FRAGMENT]);
987
988 state->prefetch_L2_mask &= ~mask;
989 }
990
991 static void
992 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
993 {
994 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
995 return;
996
997 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
998 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
999
1000 unsigned sx_ps_downconvert = 0;
1001 unsigned sx_blend_opt_epsilon = 0;
1002 unsigned sx_blend_opt_control = 0;
1003
1004 for (unsigned i = 0; i < subpass->color_count; ++i) {
1005 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1006 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1007 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1008 continue;
1009 }
1010
1011 int idx = subpass->color_attachments[i].attachment;
1012 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1013
1014 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1015 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1016 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1017 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1018
1019 bool has_alpha, has_rgb;
1020
1021 /* Set if RGB and A are present. */
1022 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1023
1024 if (format == V_028C70_COLOR_8 ||
1025 format == V_028C70_COLOR_16 ||
1026 format == V_028C70_COLOR_32)
1027 has_rgb = !has_alpha;
1028 else
1029 has_rgb = true;
1030
1031 /* Check the colormask and export format. */
1032 if (!(colormask & 0x7))
1033 has_rgb = false;
1034 if (!(colormask & 0x8))
1035 has_alpha = false;
1036
1037 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1038 has_rgb = false;
1039 has_alpha = false;
1040 }
1041
1042 /* Disable value checking for disabled channels. */
1043 if (!has_rgb)
1044 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1045 if (!has_alpha)
1046 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1047
1048 /* Enable down-conversion for 32bpp and smaller formats. */
1049 switch (format) {
1050 case V_028C70_COLOR_8:
1051 case V_028C70_COLOR_8_8:
1052 case V_028C70_COLOR_8_8_8_8:
1053 /* For 1 and 2-channel formats, use the superset thereof. */
1054 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1055 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1056 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1057 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1058 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1059 }
1060 break;
1061
1062 case V_028C70_COLOR_5_6_5:
1063 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1064 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1065 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1066 }
1067 break;
1068
1069 case V_028C70_COLOR_1_5_5_5:
1070 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1071 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1072 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1073 }
1074 break;
1075
1076 case V_028C70_COLOR_4_4_4_4:
1077 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1078 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1079 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1080 }
1081 break;
1082
1083 case V_028C70_COLOR_32:
1084 if (swap == V_028C70_SWAP_STD &&
1085 spi_format == V_028714_SPI_SHADER_32_R)
1086 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1087 else if (swap == V_028C70_SWAP_ALT_REV &&
1088 spi_format == V_028714_SPI_SHADER_32_AR)
1089 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1090 break;
1091
1092 case V_028C70_COLOR_16:
1093 case V_028C70_COLOR_16_16:
1094 /* For 1-channel formats, use the superset thereof. */
1095 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1096 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1097 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1098 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1099 if (swap == V_028C70_SWAP_STD ||
1100 swap == V_028C70_SWAP_STD_REV)
1101 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1102 else
1103 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1104 }
1105 break;
1106
1107 case V_028C70_COLOR_10_11_11:
1108 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1109 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1110 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1111 }
1112 break;
1113
1114 case V_028C70_COLOR_2_10_10_10:
1115 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1116 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1117 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1118 }
1119 break;
1120 }
1121 }
1122
1123 for (unsigned i = subpass->color_count; i < 8; ++i) {
1124 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1125 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1126 }
1127 /* TODO: avoid redundantly setting context registers */
1128 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1129 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1130 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1131 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1132
1133 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1134 }
1135
1136 static void
1137 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1138 {
1139 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1140
1141 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1142 return;
1143
1144 radv_update_multisample_state(cmd_buffer, pipeline);
1145 radv_update_binning_state(cmd_buffer, pipeline);
1146
1147 cmd_buffer->scratch_size_needed =
1148 MAX2(cmd_buffer->scratch_size_needed,
1149 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1150
1151 if (!cmd_buffer->state.emitted_pipeline ||
1152 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1153 pipeline->graphics.can_use_guardband)
1154 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1155
1156 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1157
1158 if (!cmd_buffer->state.emitted_pipeline ||
1159 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1160 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1161 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1162 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1163 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1164 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1165 }
1166
1167 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1168 if (!pipeline->shaders[i])
1169 continue;
1170
1171 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1172 pipeline->shaders[i]->bo);
1173 }
1174
1175 if (radv_pipeline_has_gs_copy_shader(pipeline))
1176 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1177 pipeline->gs_copy_shader->bo);
1178
1179 if (unlikely(cmd_buffer->device->trace_bo))
1180 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1181
1182 cmd_buffer->state.emitted_pipeline = pipeline;
1183
1184 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1185 }
1186
1187 static void
1188 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1189 {
1190 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1191 cmd_buffer->state.dynamic.viewport.viewports);
1192 }
1193
1194 static void
1195 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1196 {
1197 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1198
1199 si_write_scissors(cmd_buffer->cs, 0, count,
1200 cmd_buffer->state.dynamic.scissor.scissors,
1201 cmd_buffer->state.dynamic.viewport.viewports,
1202 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1203
1204 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1205 }
1206
1207 static void
1208 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1209 {
1210 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1211 return;
1212
1213 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1214 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1215 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1216 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1217 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1218 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1219 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1220 }
1221 }
1222
1223 static void
1224 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1225 {
1226 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1227
1228 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1229 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1230 }
1231
1232 static void
1233 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1234 {
1235 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1236
1237 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1238 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1239 }
1240
1241 static void
1242 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1243 {
1244 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1245
1246 radeon_set_context_reg_seq(cmd_buffer->cs,
1247 R_028430_DB_STENCILREFMASK, 2);
1248 radeon_emit(cmd_buffer->cs,
1249 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1250 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1251 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1252 S_028430_STENCILOPVAL(1));
1253 radeon_emit(cmd_buffer->cs,
1254 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1255 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1256 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1257 S_028434_STENCILOPVAL_BF(1));
1258 }
1259
1260 static void
1261 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1262 {
1263 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1264
1265 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1266 fui(d->depth_bounds.min));
1267 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1268 fui(d->depth_bounds.max));
1269 }
1270
1271 static void
1272 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1273 {
1274 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1275 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1276 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1277
1278
1279 radeon_set_context_reg_seq(cmd_buffer->cs,
1280 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1281 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1282 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1283 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1284 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1285 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1286 }
1287
1288 static void
1289 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1290 int index,
1291 struct radv_color_buffer_info *cb,
1292 struct radv_image_view *iview,
1293 VkImageLayout layout,
1294 bool in_render_loop)
1295 {
1296 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1297 uint32_t cb_color_info = cb->cb_color_info;
1298 struct radv_image *image = iview->image;
1299
1300 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1301 radv_image_queue_family_mask(image,
1302 cmd_buffer->queue_family_index,
1303 cmd_buffer->queue_family_index))) {
1304 cb_color_info &= C_028C70_DCC_ENABLE;
1305 }
1306
1307 if (radv_image_is_tc_compat_cmask(image) &&
1308 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1309 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1310 /* If this bit is set, the FMASK decompression operation
1311 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1312 */
1313 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1314 }
1315
1316 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1317 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1318 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1319 radeon_emit(cmd_buffer->cs, 0);
1320 radeon_emit(cmd_buffer->cs, 0);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1322 radeon_emit(cmd_buffer->cs, cb_color_info);
1323 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1324 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1325 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1326 radeon_emit(cmd_buffer->cs, 0);
1327 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1328 radeon_emit(cmd_buffer->cs, 0);
1329
1330 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1331 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1332
1333 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1334 cb->cb_color_base >> 32);
1335 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1336 cb->cb_color_cmask >> 32);
1337 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1338 cb->cb_color_fmask >> 32);
1339 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1340 cb->cb_dcc_base >> 32);
1341 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1342 cb->cb_color_attrib2);
1343 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1344 cb->cb_color_attrib3);
1345 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1346 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1347 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1348 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1349 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1351 radeon_emit(cmd_buffer->cs, cb_color_info);
1352 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1353 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1354 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1355 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1356 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1357 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1358
1359 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1360 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1361 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1362
1363 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1364 cb->cb_mrt_epitch);
1365 } else {
1366 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1367 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1369 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1371 radeon_emit(cmd_buffer->cs, cb_color_info);
1372 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1373 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1374 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1375 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1376 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1377 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1378
1379 if (is_vi) { /* DCC BASE */
1380 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1381 }
1382 }
1383
1384 if (radv_dcc_enabled(image, iview->base_mip)) {
1385 /* Drawing with DCC enabled also compresses colorbuffers. */
1386 VkImageSubresourceRange range = {
1387 .aspectMask = iview->aspect_mask,
1388 .baseMipLevel = iview->base_mip,
1389 .levelCount = iview->level_count,
1390 .baseArrayLayer = iview->base_layer,
1391 .layerCount = iview->layer_count,
1392 };
1393
1394 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1395 }
1396 }
1397
1398 static void
1399 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1400 struct radv_ds_buffer_info *ds,
1401 const struct radv_image_view *iview,
1402 VkImageLayout layout,
1403 bool in_render_loop, bool requires_cond_exec)
1404 {
1405 const struct radv_image *image = iview->image;
1406 uint32_t db_z_info = ds->db_z_info;
1407 uint32_t db_z_info_reg;
1408
1409 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1410 !radv_image_is_tc_compat_htile(image))
1411 return;
1412
1413 if (!radv_layout_has_htile(image, layout, in_render_loop,
1414 radv_image_queue_family_mask(image,
1415 cmd_buffer->queue_family_index,
1416 cmd_buffer->queue_family_index))) {
1417 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1418 }
1419
1420 db_z_info &= C_028040_ZRANGE_PRECISION;
1421
1422 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1423 db_z_info_reg = R_028038_DB_Z_INFO;
1424 } else {
1425 db_z_info_reg = R_028040_DB_Z_INFO;
1426 }
1427
1428 /* When we don't know the last fast clear value we need to emit a
1429 * conditional packet that will eventually skip the following
1430 * SET_CONTEXT_REG packet.
1431 */
1432 if (requires_cond_exec) {
1433 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1434
1435 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1436 radeon_emit(cmd_buffer->cs, va);
1437 radeon_emit(cmd_buffer->cs, va >> 32);
1438 radeon_emit(cmd_buffer->cs, 0);
1439 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1440 }
1441
1442 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1443 }
1444
1445 static void
1446 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1447 struct radv_ds_buffer_info *ds,
1448 struct radv_image_view *iview,
1449 VkImageLayout layout,
1450 bool in_render_loop)
1451 {
1452 const struct radv_image *image = iview->image;
1453 uint32_t db_z_info = ds->db_z_info;
1454 uint32_t db_stencil_info = ds->db_stencil_info;
1455
1456 if (!radv_layout_has_htile(image, layout, in_render_loop,
1457 radv_image_queue_family_mask(image,
1458 cmd_buffer->queue_family_index,
1459 cmd_buffer->queue_family_index))) {
1460 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1461 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1462 }
1463
1464 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1465 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1466
1467 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1468 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1469 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1470
1471 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1472 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1473 radeon_emit(cmd_buffer->cs, db_z_info);
1474 radeon_emit(cmd_buffer->cs, db_stencil_info);
1475 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1476 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1477 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1478 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1479
1480 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1481 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1482 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1483 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1484 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1485 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1486 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1487 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1488 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1489 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1490 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1491
1492 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1493 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1494 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1495 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1496 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1497 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1498 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1499 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1500 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1501 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1502 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1503
1504 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1505 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1506 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1507 } else {
1508 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1509
1510 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1511 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1512 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1513 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1514 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1515 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1516 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1517 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1518 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1519 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1520
1521 }
1522
1523 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1524 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1525 in_render_loop, true);
1526
1527 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1528 ds->pa_su_poly_offset_db_fmt_cntl);
1529 }
1530
1531 /**
1532 * Update the fast clear depth/stencil values if the image is bound as a
1533 * depth/stencil buffer.
1534 */
1535 static void
1536 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1537 const struct radv_image_view *iview,
1538 VkClearDepthStencilValue ds_clear_value,
1539 VkImageAspectFlags aspects)
1540 {
1541 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1542 const struct radv_image *image = iview->image;
1543 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1544 uint32_t att_idx;
1545
1546 if (!cmd_buffer->state.attachments || !subpass)
1547 return;
1548
1549 if (!subpass->depth_stencil_attachment)
1550 return;
1551
1552 att_idx = subpass->depth_stencil_attachment->attachment;
1553 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1554 return;
1555
1556 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1557 radeon_emit(cs, ds_clear_value.stencil);
1558 radeon_emit(cs, fui(ds_clear_value.depth));
1559
1560 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1561 * only needed when clearing Z to 0.0.
1562 */
1563 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1564 ds_clear_value.depth == 0.0) {
1565 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1566 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1567
1568 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1569 iview, layout, in_render_loop, false);
1570 }
1571
1572 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1573 }
1574
1575 /**
1576 * Set the clear depth/stencil values to the image's metadata.
1577 */
1578 static void
1579 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1580 struct radv_image *image,
1581 const VkImageSubresourceRange *range,
1582 VkClearDepthStencilValue ds_clear_value,
1583 VkImageAspectFlags aspects)
1584 {
1585 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1586 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1587 uint32_t level_count = radv_get_levelCount(image, range);
1588
1589 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1590 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1591 /* Use the fastest way when both aspects are used. */
1592 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1593 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1594 S_370_WR_CONFIRM(1) |
1595 S_370_ENGINE_SEL(V_370_PFP));
1596 radeon_emit(cs, va);
1597 radeon_emit(cs, va >> 32);
1598
1599 for (uint32_t l = 0; l < level_count; l++) {
1600 radeon_emit(cs, ds_clear_value.stencil);
1601 radeon_emit(cs, fui(ds_clear_value.depth));
1602 }
1603 } else {
1604 /* Otherwise we need one WRITE_DATA packet per level. */
1605 for (uint32_t l = 0; l < level_count; l++) {
1606 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1607 unsigned value;
1608
1609 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1610 value = fui(ds_clear_value.depth);
1611 va += 4;
1612 } else {
1613 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1614 value = ds_clear_value.stencil;
1615 }
1616
1617 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1618 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1619 S_370_WR_CONFIRM(1) |
1620 S_370_ENGINE_SEL(V_370_PFP));
1621 radeon_emit(cs, va);
1622 radeon_emit(cs, va >> 32);
1623 radeon_emit(cs, value);
1624 }
1625 }
1626 }
1627
1628 /**
1629 * Update the TC-compat metadata value for this image.
1630 */
1631 static void
1632 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1633 struct radv_image *image,
1634 const VkImageSubresourceRange *range,
1635 uint32_t value)
1636 {
1637 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1638
1639 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1640 return;
1641
1642 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1643 uint32_t level_count = radv_get_levelCount(image, range);
1644
1645 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1646 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1647 S_370_WR_CONFIRM(1) |
1648 S_370_ENGINE_SEL(V_370_PFP));
1649 radeon_emit(cs, va);
1650 radeon_emit(cs, va >> 32);
1651
1652 for (uint32_t l = 0; l < level_count; l++)
1653 radeon_emit(cs, value);
1654 }
1655
1656 static void
1657 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1658 const struct radv_image_view *iview,
1659 VkClearDepthStencilValue ds_clear_value)
1660 {
1661 VkImageSubresourceRange range = {
1662 .aspectMask = iview->aspect_mask,
1663 .baseMipLevel = iview->base_mip,
1664 .levelCount = iview->level_count,
1665 .baseArrayLayer = iview->base_layer,
1666 .layerCount = iview->layer_count,
1667 };
1668 uint32_t cond_val;
1669
1670 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1671 * depth clear value is 0.0f.
1672 */
1673 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1674
1675 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1676 cond_val);
1677 }
1678
1679 /**
1680 * Update the clear depth/stencil values for this image.
1681 */
1682 void
1683 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1684 const struct radv_image_view *iview,
1685 VkClearDepthStencilValue ds_clear_value,
1686 VkImageAspectFlags aspects)
1687 {
1688 VkImageSubresourceRange range = {
1689 .aspectMask = iview->aspect_mask,
1690 .baseMipLevel = iview->base_mip,
1691 .levelCount = iview->level_count,
1692 .baseArrayLayer = iview->base_layer,
1693 .layerCount = iview->layer_count,
1694 };
1695 struct radv_image *image = iview->image;
1696
1697 assert(radv_image_has_htile(image));
1698
1699 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1700 ds_clear_value, aspects);
1701
1702 if (radv_image_is_tc_compat_htile(image) &&
1703 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1704 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1705 ds_clear_value);
1706 }
1707
1708 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1709 aspects);
1710 }
1711
1712 /**
1713 * Load the clear depth/stencil values from the image's metadata.
1714 */
1715 static void
1716 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1717 const struct radv_image_view *iview)
1718 {
1719 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1720 const struct radv_image *image = iview->image;
1721 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1722 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1723 unsigned reg_offset = 0, reg_count = 0;
1724
1725 if (!radv_image_has_htile(image))
1726 return;
1727
1728 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1729 ++reg_count;
1730 } else {
1731 ++reg_offset;
1732 va += 4;
1733 }
1734 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1735 ++reg_count;
1736
1737 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1738
1739 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1740 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1741 radeon_emit(cs, va);
1742 radeon_emit(cs, va >> 32);
1743 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1744 radeon_emit(cs, reg_count);
1745 } else {
1746 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1747 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1748 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1749 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1750 radeon_emit(cs, va);
1751 radeon_emit(cs, va >> 32);
1752 radeon_emit(cs, reg >> 2);
1753 radeon_emit(cs, 0);
1754
1755 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1756 radeon_emit(cs, 0);
1757 }
1758 }
1759
1760 /*
1761 * With DCC some colors don't require CMASK elimination before being
1762 * used as a texture. This sets a predicate value to determine if the
1763 * cmask eliminate is required.
1764 */
1765 void
1766 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1767 struct radv_image *image,
1768 const VkImageSubresourceRange *range, bool value)
1769 {
1770 uint64_t pred_val = value;
1771 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1772 uint32_t level_count = radv_get_levelCount(image, range);
1773 uint32_t count = 2 * level_count;
1774
1775 assert(radv_dcc_enabled(image, range->baseMipLevel));
1776
1777 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1778 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1779 S_370_WR_CONFIRM(1) |
1780 S_370_ENGINE_SEL(V_370_PFP));
1781 radeon_emit(cmd_buffer->cs, va);
1782 radeon_emit(cmd_buffer->cs, va >> 32);
1783
1784 for (uint32_t l = 0; l < level_count; l++) {
1785 radeon_emit(cmd_buffer->cs, pred_val);
1786 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1787 }
1788 }
1789
1790 /**
1791 * Update the DCC predicate to reflect the compression state.
1792 */
1793 void
1794 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1795 struct radv_image *image,
1796 const VkImageSubresourceRange *range, bool value)
1797 {
1798 uint64_t pred_val = value;
1799 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1800 uint32_t level_count = radv_get_levelCount(image, range);
1801 uint32_t count = 2 * level_count;
1802
1803 assert(radv_dcc_enabled(image, range->baseMipLevel));
1804
1805 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1806 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1807 S_370_WR_CONFIRM(1) |
1808 S_370_ENGINE_SEL(V_370_PFP));
1809 radeon_emit(cmd_buffer->cs, va);
1810 radeon_emit(cmd_buffer->cs, va >> 32);
1811
1812 for (uint32_t l = 0; l < level_count; l++) {
1813 radeon_emit(cmd_buffer->cs, pred_val);
1814 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1815 }
1816 }
1817
1818 /**
1819 * Update the fast clear color values if the image is bound as a color buffer.
1820 */
1821 static void
1822 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1823 struct radv_image *image,
1824 int cb_idx,
1825 uint32_t color_values[2])
1826 {
1827 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1828 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1829 uint32_t att_idx;
1830
1831 if (!cmd_buffer->state.attachments || !subpass)
1832 return;
1833
1834 att_idx = subpass->color_attachments[cb_idx].attachment;
1835 if (att_idx == VK_ATTACHMENT_UNUSED)
1836 return;
1837
1838 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1839 return;
1840
1841 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1842 radeon_emit(cs, color_values[0]);
1843 radeon_emit(cs, color_values[1]);
1844
1845 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1846 }
1847
1848 /**
1849 * Set the clear color values to the image's metadata.
1850 */
1851 static void
1852 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1853 struct radv_image *image,
1854 const VkImageSubresourceRange *range,
1855 uint32_t color_values[2])
1856 {
1857 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1858 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1859 uint32_t level_count = radv_get_levelCount(image, range);
1860 uint32_t count = 2 * level_count;
1861
1862 assert(radv_image_has_cmask(image) ||
1863 radv_dcc_enabled(image, range->baseMipLevel));
1864
1865 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1866 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1867 S_370_WR_CONFIRM(1) |
1868 S_370_ENGINE_SEL(V_370_PFP));
1869 radeon_emit(cs, va);
1870 radeon_emit(cs, va >> 32);
1871
1872 for (uint32_t l = 0; l < level_count; l++) {
1873 radeon_emit(cs, color_values[0]);
1874 radeon_emit(cs, color_values[1]);
1875 }
1876 }
1877
1878 /**
1879 * Update the clear color values for this image.
1880 */
1881 void
1882 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1883 const struct radv_image_view *iview,
1884 int cb_idx,
1885 uint32_t color_values[2])
1886 {
1887 struct radv_image *image = iview->image;
1888 VkImageSubresourceRange range = {
1889 .aspectMask = iview->aspect_mask,
1890 .baseMipLevel = iview->base_mip,
1891 .levelCount = iview->level_count,
1892 .baseArrayLayer = iview->base_layer,
1893 .layerCount = iview->layer_count,
1894 };
1895
1896 assert(radv_image_has_cmask(image) ||
1897 radv_dcc_enabled(image, iview->base_mip));
1898
1899 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1900
1901 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1902 color_values);
1903 }
1904
1905 /**
1906 * Load the clear color values from the image's metadata.
1907 */
1908 static void
1909 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1910 struct radv_image_view *iview,
1911 int cb_idx)
1912 {
1913 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1914 struct radv_image *image = iview->image;
1915 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1916
1917 if (!radv_image_has_cmask(image) &&
1918 !radv_dcc_enabled(image, iview->base_mip))
1919 return;
1920
1921 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1922
1923 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1924 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1925 radeon_emit(cs, va);
1926 radeon_emit(cs, va >> 32);
1927 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1928 radeon_emit(cs, 2);
1929 } else {
1930 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1931 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1932 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1933 COPY_DATA_COUNT_SEL);
1934 radeon_emit(cs, va);
1935 radeon_emit(cs, va >> 32);
1936 radeon_emit(cs, reg >> 2);
1937 radeon_emit(cs, 0);
1938
1939 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1940 radeon_emit(cs, 0);
1941 }
1942 }
1943
1944 static void
1945 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1946 {
1947 int i;
1948 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1949 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1950
1951 /* this may happen for inherited secondary recording */
1952 if (!framebuffer)
1953 return;
1954
1955 for (i = 0; i < 8; ++i) {
1956 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1957 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1958 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1959 continue;
1960 }
1961
1962 int idx = subpass->color_attachments[i].attachment;
1963 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1964 VkImageLayout layout = subpass->color_attachments[i].layout;
1965 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1966
1967 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1968
1969 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1970 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1971 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1972
1973 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1974 }
1975
1976 if (subpass->depth_stencil_attachment) {
1977 int idx = subpass->depth_stencil_attachment->attachment;
1978 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1979 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1980 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1981 struct radv_image *image = iview->image;
1982 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1983 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1984 cmd_buffer->queue_family_index,
1985 cmd_buffer->queue_family_index);
1986 /* We currently don't support writing decompressed HTILE */
1987 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
1988 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
1989
1990 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
1991
1992 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
1993 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1994 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
1995 }
1996 radv_load_ds_clear_metadata(cmd_buffer, iview);
1997 } else {
1998 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1999 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2000 else
2001 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2002
2003 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2004 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2005 }
2006 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2007 S_028208_BR_X(framebuffer->width) |
2008 S_028208_BR_Y(framebuffer->height));
2009
2010 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2011 bool disable_constant_encode =
2012 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2013 enum chip_class chip_class =
2014 cmd_buffer->device->physical_device->rad_info.chip_class;
2015 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2016
2017 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2018 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2019 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2020 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2021 }
2022
2023 if (cmd_buffer->device->dfsm_allowed) {
2024 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2025 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2026 }
2027
2028 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2029 }
2030
2031 static void
2032 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2033 {
2034 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2035 struct radv_cmd_state *state = &cmd_buffer->state;
2036
2037 if (state->index_type != state->last_index_type) {
2038 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2039 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2040 cs, R_03090C_VGT_INDEX_TYPE,
2041 2, state->index_type);
2042 } else {
2043 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2044 radeon_emit(cs, state->index_type);
2045 }
2046
2047 state->last_index_type = state->index_type;
2048 }
2049
2050 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2051 radeon_emit(cs, state->index_va);
2052 radeon_emit(cs, state->index_va >> 32);
2053
2054 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2055 radeon_emit(cs, state->max_index_count);
2056
2057 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2058 }
2059
2060 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2061 {
2062 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2063 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2064 uint32_t pa_sc_mode_cntl_1 =
2065 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2066 uint32_t db_count_control;
2067
2068 if(!cmd_buffer->state.active_occlusion_queries) {
2069 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2070 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2071 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2072 has_perfect_queries) {
2073 /* Re-enable out-of-order rasterization if the
2074 * bound pipeline supports it and if it's has
2075 * been disabled before starting any perfect
2076 * occlusion queries.
2077 */
2078 radeon_set_context_reg(cmd_buffer->cs,
2079 R_028A4C_PA_SC_MODE_CNTL_1,
2080 pa_sc_mode_cntl_1);
2081 }
2082 }
2083 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2084 } else {
2085 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2086 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2087 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2088
2089 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2090 db_count_control =
2091 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2092 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2093 S_028004_SAMPLE_RATE(sample_rate) |
2094 S_028004_ZPASS_ENABLE(1) |
2095 S_028004_SLICE_EVEN_ENABLE(1) |
2096 S_028004_SLICE_ODD_ENABLE(1);
2097
2098 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2099 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2100 has_perfect_queries) {
2101 /* If the bound pipeline has enabled
2102 * out-of-order rasterization, we should
2103 * disable it before starting any perfect
2104 * occlusion queries.
2105 */
2106 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2107
2108 radeon_set_context_reg(cmd_buffer->cs,
2109 R_028A4C_PA_SC_MODE_CNTL_1,
2110 pa_sc_mode_cntl_1);
2111 }
2112 } else {
2113 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2114 S_028004_SAMPLE_RATE(sample_rate);
2115 }
2116 }
2117
2118 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2119
2120 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2121 }
2122
2123 static void
2124 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2125 {
2126 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2127
2128 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2129 radv_emit_viewport(cmd_buffer);
2130
2131 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2132 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2133 radv_emit_scissor(cmd_buffer);
2134
2135 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2136 radv_emit_line_width(cmd_buffer);
2137
2138 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2139 radv_emit_blend_constants(cmd_buffer);
2140
2141 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2142 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2143 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2144 radv_emit_stencil(cmd_buffer);
2145
2146 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2147 radv_emit_depth_bounds(cmd_buffer);
2148
2149 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2150 radv_emit_depth_bias(cmd_buffer);
2151
2152 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2153 radv_emit_discard_rectangle(cmd_buffer);
2154
2155 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2156 radv_emit_sample_locations(cmd_buffer);
2157
2158 cmd_buffer->state.dirty &= ~states;
2159 }
2160
2161 static void
2162 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2163 VkPipelineBindPoint bind_point)
2164 {
2165 struct radv_descriptor_state *descriptors_state =
2166 radv_get_descriptors_state(cmd_buffer, bind_point);
2167 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2168 unsigned bo_offset;
2169
2170 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2171 set->mapped_ptr,
2172 &bo_offset))
2173 return;
2174
2175 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2176 set->va += bo_offset;
2177 }
2178
2179 static void
2180 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2181 VkPipelineBindPoint bind_point)
2182 {
2183 struct radv_descriptor_state *descriptors_state =
2184 radv_get_descriptors_state(cmd_buffer, bind_point);
2185 uint32_t size = MAX_SETS * 4;
2186 uint32_t offset;
2187 void *ptr;
2188
2189 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2190 256, &offset, &ptr))
2191 return;
2192
2193 for (unsigned i = 0; i < MAX_SETS; i++) {
2194 uint32_t *uptr = ((uint32_t *)ptr) + i;
2195 uint64_t set_va = 0;
2196 struct radv_descriptor_set *set = descriptors_state->sets[i];
2197 if (descriptors_state->valid & (1u << i))
2198 set_va = set->va;
2199 uptr[0] = set_va & 0xffffffff;
2200 }
2201
2202 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2203 va += offset;
2204
2205 if (cmd_buffer->state.pipeline) {
2206 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2207 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2208 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2209
2210 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2211 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2212 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2213
2214 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2215 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2216 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2217
2218 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2219 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2220 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2221
2222 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2223 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2224 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2225 }
2226
2227 if (cmd_buffer->state.compute_pipeline)
2228 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2229 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2230 }
2231
2232 static void
2233 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2234 VkShaderStageFlags stages)
2235 {
2236 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2237 VK_PIPELINE_BIND_POINT_COMPUTE :
2238 VK_PIPELINE_BIND_POINT_GRAPHICS;
2239 struct radv_descriptor_state *descriptors_state =
2240 radv_get_descriptors_state(cmd_buffer, bind_point);
2241 struct radv_cmd_state *state = &cmd_buffer->state;
2242 bool flush_indirect_descriptors;
2243
2244 if (!descriptors_state->dirty)
2245 return;
2246
2247 if (descriptors_state->push_dirty)
2248 radv_flush_push_descriptors(cmd_buffer, bind_point);
2249
2250 flush_indirect_descriptors =
2251 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2252 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2253 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2254 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2255
2256 if (flush_indirect_descriptors)
2257 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2258
2259 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2260 cmd_buffer->cs,
2261 MAX_SETS * MESA_SHADER_STAGES * 4);
2262
2263 if (cmd_buffer->state.pipeline) {
2264 radv_foreach_stage(stage, stages) {
2265 if (!cmd_buffer->state.pipeline->shaders[stage])
2266 continue;
2267
2268 radv_emit_descriptor_pointers(cmd_buffer,
2269 cmd_buffer->state.pipeline,
2270 descriptors_state, stage);
2271 }
2272 }
2273
2274 if (cmd_buffer->state.compute_pipeline &&
2275 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2276 radv_emit_descriptor_pointers(cmd_buffer,
2277 cmd_buffer->state.compute_pipeline,
2278 descriptors_state,
2279 MESA_SHADER_COMPUTE);
2280 }
2281
2282 descriptors_state->dirty = 0;
2283 descriptors_state->push_dirty = false;
2284
2285 assert(cmd_buffer->cs->cdw <= cdw_max);
2286
2287 if (unlikely(cmd_buffer->device->trace_bo))
2288 radv_save_descriptors(cmd_buffer, bind_point);
2289 }
2290
2291 static void
2292 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2293 VkShaderStageFlags stages)
2294 {
2295 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2296 ? cmd_buffer->state.compute_pipeline
2297 : cmd_buffer->state.pipeline;
2298 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2299 VK_PIPELINE_BIND_POINT_COMPUTE :
2300 VK_PIPELINE_BIND_POINT_GRAPHICS;
2301 struct radv_descriptor_state *descriptors_state =
2302 radv_get_descriptors_state(cmd_buffer, bind_point);
2303 struct radv_pipeline_layout *layout = pipeline->layout;
2304 struct radv_shader_variant *shader, *prev_shader;
2305 bool need_push_constants = false;
2306 unsigned offset;
2307 void *ptr;
2308 uint64_t va;
2309
2310 stages &= cmd_buffer->push_constant_stages;
2311 if (!stages ||
2312 (!layout->push_constant_size && !layout->dynamic_offset_count))
2313 return;
2314
2315 radv_foreach_stage(stage, stages) {
2316 if (!pipeline->shaders[stage])
2317 continue;
2318
2319 need_push_constants |= pipeline->shaders[stage]->info.loads_push_constants;
2320 need_push_constants |= pipeline->shaders[stage]->info.loads_dynamic_offsets;
2321
2322 uint8_t base = pipeline->shaders[stage]->info.base_inline_push_consts;
2323 uint8_t count = pipeline->shaders[stage]->info.num_inline_push_consts;
2324
2325 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2326 AC_UD_INLINE_PUSH_CONSTANTS,
2327 count,
2328 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2329 }
2330
2331 if (need_push_constants) {
2332 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2333 16 * layout->dynamic_offset_count,
2334 256, &offset, &ptr))
2335 return;
2336
2337 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2338 memcpy((char*)ptr + layout->push_constant_size,
2339 descriptors_state->dynamic_buffers,
2340 16 * layout->dynamic_offset_count);
2341
2342 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2343 va += offset;
2344
2345 ASSERTED unsigned cdw_max =
2346 radeon_check_space(cmd_buffer->device->ws,
2347 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2348
2349 prev_shader = NULL;
2350 radv_foreach_stage(stage, stages) {
2351 shader = radv_get_shader(pipeline, stage);
2352
2353 /* Avoid redundantly emitting the address for merged stages. */
2354 if (shader && shader != prev_shader) {
2355 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2356 AC_UD_PUSH_CONSTANTS, va);
2357
2358 prev_shader = shader;
2359 }
2360 }
2361 assert(cmd_buffer->cs->cdw <= cdw_max);
2362 }
2363
2364 cmd_buffer->push_constant_stages &= ~stages;
2365 }
2366
2367 static void
2368 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2369 bool pipeline_is_dirty)
2370 {
2371 if ((pipeline_is_dirty ||
2372 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2373 cmd_buffer->state.pipeline->num_vertex_bindings &&
2374 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2375 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2376 unsigned vb_offset;
2377 void *vb_ptr;
2378 uint32_t i = 0;
2379 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2380 uint64_t va;
2381
2382 /* allocate some descriptor state for vertex buffers */
2383 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2384 &vb_offset, &vb_ptr))
2385 return;
2386
2387 for (i = 0; i < count; i++) {
2388 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2389 uint32_t offset;
2390 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2391 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2392
2393 if (!buffer)
2394 continue;
2395
2396 va = radv_buffer_get_va(buffer->bo);
2397
2398 offset = cmd_buffer->vertex_bindings[i].offset;
2399 va += offset + buffer->offset;
2400 desc[0] = va;
2401 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2402 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2403 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2404 else
2405 desc[2] = buffer->size - offset;
2406 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2407 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2408 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2409 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2410
2411 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2412 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2413 S_008F0C_OOB_SELECT(1) |
2414 S_008F0C_RESOURCE_LEVEL(1);
2415 } else {
2416 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2417 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2418 }
2419 }
2420
2421 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2422 va += vb_offset;
2423
2424 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2425 AC_UD_VS_VERTEX_BUFFERS, va);
2426
2427 cmd_buffer->state.vb_va = va;
2428 cmd_buffer->state.vb_size = count * 16;
2429 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2430 }
2431 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2432 }
2433
2434 static void
2435 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2436 {
2437 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2438 struct radv_userdata_info *loc;
2439 uint32_t base_reg;
2440
2441 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2442 if (!radv_get_shader(pipeline, stage))
2443 continue;
2444
2445 loc = radv_lookup_user_sgpr(pipeline, stage,
2446 AC_UD_STREAMOUT_BUFFERS);
2447 if (loc->sgpr_idx == -1)
2448 continue;
2449
2450 base_reg = pipeline->user_data_0[stage];
2451
2452 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2453 base_reg + loc->sgpr_idx * 4, va, false);
2454 }
2455
2456 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2457 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2458 if (loc->sgpr_idx != -1) {
2459 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2460
2461 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2462 base_reg + loc->sgpr_idx * 4, va, false);
2463 }
2464 }
2465 }
2466
2467 static void
2468 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2469 {
2470 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2471 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2472 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2473 unsigned so_offset;
2474 void *so_ptr;
2475 uint64_t va;
2476
2477 /* Allocate some descriptor state for streamout buffers. */
2478 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2479 MAX_SO_BUFFERS * 16, 256,
2480 &so_offset, &so_ptr))
2481 return;
2482
2483 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2484 struct radv_buffer *buffer = sb[i].buffer;
2485 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2486
2487 if (!(so->enabled_mask & (1 << i)))
2488 continue;
2489
2490 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2491
2492 va += sb[i].offset;
2493
2494 /* Set the descriptor.
2495 *
2496 * On GFX8, the format must be non-INVALID, otherwise
2497 * the buffer will be considered not bound and store
2498 * instructions will be no-ops.
2499 */
2500 uint32_t size = 0xffffffff;
2501
2502 /* Compute the correct buffer size for NGG streamout
2503 * because it's used to determine the max emit per
2504 * buffer.
2505 */
2506 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2507 size = buffer->size - sb[i].offset;
2508
2509 desc[0] = va;
2510 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2511 desc[2] = size;
2512 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2513 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2514 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2515 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2516
2517 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2518 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2519 S_008F0C_OOB_SELECT(3) |
2520 S_008F0C_RESOURCE_LEVEL(1);
2521 } else {
2522 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2523 }
2524 }
2525
2526 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2527 va += so_offset;
2528
2529 radv_emit_streamout_buffers(cmd_buffer, va);
2530 }
2531
2532 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2533 }
2534
2535 static void
2536 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2537 {
2538 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2539 radv_flush_streamout_descriptors(cmd_buffer);
2540 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2541 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2542 }
2543
2544 struct radv_draw_info {
2545 /**
2546 * Number of vertices.
2547 */
2548 uint32_t count;
2549
2550 /**
2551 * Index of the first vertex.
2552 */
2553 int32_t vertex_offset;
2554
2555 /**
2556 * First instance id.
2557 */
2558 uint32_t first_instance;
2559
2560 /**
2561 * Number of instances.
2562 */
2563 uint32_t instance_count;
2564
2565 /**
2566 * First index (indexed draws only).
2567 */
2568 uint32_t first_index;
2569
2570 /**
2571 * Whether it's an indexed draw.
2572 */
2573 bool indexed;
2574
2575 /**
2576 * Indirect draw parameters resource.
2577 */
2578 struct radv_buffer *indirect;
2579 uint64_t indirect_offset;
2580 uint32_t stride;
2581
2582 /**
2583 * Draw count parameters resource.
2584 */
2585 struct radv_buffer *count_buffer;
2586 uint64_t count_buffer_offset;
2587
2588 /**
2589 * Stream output parameters resource.
2590 */
2591 struct radv_buffer *strmout_buffer;
2592 uint64_t strmout_buffer_offset;
2593 };
2594
2595 static uint32_t
2596 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2597 {
2598 switch (cmd_buffer->state.index_type) {
2599 case V_028A7C_VGT_INDEX_8:
2600 return 0xffu;
2601 case V_028A7C_VGT_INDEX_16:
2602 return 0xffffu;
2603 case V_028A7C_VGT_INDEX_32:
2604 return 0xffffffffu;
2605 default:
2606 unreachable("invalid index type");
2607 }
2608 }
2609
2610 static void
2611 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2612 bool instanced_draw, bool indirect_draw,
2613 bool count_from_stream_output,
2614 uint32_t draw_vertex_count)
2615 {
2616 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2617 struct radv_cmd_state *state = &cmd_buffer->state;
2618 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2619 unsigned ia_multi_vgt_param;
2620
2621 ia_multi_vgt_param =
2622 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2623 indirect_draw,
2624 count_from_stream_output,
2625 draw_vertex_count);
2626
2627 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2628 if (info->chip_class == GFX9) {
2629 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2630 cs,
2631 R_030960_IA_MULTI_VGT_PARAM,
2632 4, ia_multi_vgt_param);
2633 } else if (info->chip_class >= GFX7) {
2634 radeon_set_context_reg_idx(cs,
2635 R_028AA8_IA_MULTI_VGT_PARAM,
2636 1, ia_multi_vgt_param);
2637 } else {
2638 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2639 ia_multi_vgt_param);
2640 }
2641 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2642 }
2643 }
2644
2645 static void
2646 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2647 const struct radv_draw_info *draw_info)
2648 {
2649 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2650 struct radv_cmd_state *state = &cmd_buffer->state;
2651 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2652 int32_t primitive_reset_en;
2653
2654 /* Draw state. */
2655 if (info->chip_class < GFX10) {
2656 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2657 draw_info->indirect,
2658 !!draw_info->strmout_buffer,
2659 draw_info->indirect ? 0 : draw_info->count);
2660 }
2661
2662 /* Primitive restart. */
2663 primitive_reset_en =
2664 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2665
2666 if (primitive_reset_en != state->last_primitive_reset_en) {
2667 state->last_primitive_reset_en = primitive_reset_en;
2668 if (info->chip_class >= GFX9) {
2669 radeon_set_uconfig_reg(cs,
2670 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2671 primitive_reset_en);
2672 } else {
2673 radeon_set_context_reg(cs,
2674 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2675 primitive_reset_en);
2676 }
2677 }
2678
2679 if (primitive_reset_en) {
2680 uint32_t primitive_reset_index =
2681 radv_get_primitive_reset_index(cmd_buffer);
2682
2683 if (primitive_reset_index != state->last_primitive_reset_index) {
2684 radeon_set_context_reg(cs,
2685 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2686 primitive_reset_index);
2687 state->last_primitive_reset_index = primitive_reset_index;
2688 }
2689 }
2690
2691 if (draw_info->strmout_buffer) {
2692 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2693
2694 va += draw_info->strmout_buffer->offset +
2695 draw_info->strmout_buffer_offset;
2696
2697 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2698 draw_info->stride);
2699
2700 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2701 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2702 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2703 COPY_DATA_WR_CONFIRM);
2704 radeon_emit(cs, va);
2705 radeon_emit(cs, va >> 32);
2706 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2707 radeon_emit(cs, 0); /* unused */
2708
2709 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2710 }
2711 }
2712
2713 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2714 VkPipelineStageFlags src_stage_mask)
2715 {
2716 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2717 VK_PIPELINE_STAGE_TRANSFER_BIT |
2718 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2719 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2720 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2721 }
2722
2723 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2724 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2725 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2726 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2727 VK_PIPELINE_STAGE_TRANSFER_BIT |
2728 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2729 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2730 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2731 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2732 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2733 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2734 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2735 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2736 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2737 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2738 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2739 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2740 }
2741 }
2742
2743 static enum radv_cmd_flush_bits
2744 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2745 VkAccessFlags src_flags,
2746 struct radv_image *image)
2747 {
2748 bool flush_CB_meta = true, flush_DB_meta = true;
2749 enum radv_cmd_flush_bits flush_bits = 0;
2750 uint32_t b;
2751
2752 if (image) {
2753 if (!radv_image_has_CB_metadata(image))
2754 flush_CB_meta = false;
2755 if (!radv_image_has_htile(image))
2756 flush_DB_meta = false;
2757 }
2758
2759 for_each_bit(b, src_flags) {
2760 switch ((VkAccessFlagBits)(1 << b)) {
2761 case VK_ACCESS_SHADER_WRITE_BIT:
2762 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2763 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2764 flush_bits |= RADV_CMD_FLAG_WB_L2;
2765 break;
2766 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2767 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2768 if (flush_CB_meta)
2769 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2770 break;
2771 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2772 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2773 if (flush_DB_meta)
2774 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2775 break;
2776 case VK_ACCESS_TRANSFER_WRITE_BIT:
2777 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2778 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2779 RADV_CMD_FLAG_INV_L2;
2780
2781 if (flush_CB_meta)
2782 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2783 if (flush_DB_meta)
2784 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2785 break;
2786 default:
2787 break;
2788 }
2789 }
2790 return flush_bits;
2791 }
2792
2793 static enum radv_cmd_flush_bits
2794 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2795 VkAccessFlags dst_flags,
2796 struct radv_image *image)
2797 {
2798 bool flush_CB_meta = true, flush_DB_meta = true;
2799 enum radv_cmd_flush_bits flush_bits = 0;
2800 bool flush_CB = true, flush_DB = true;
2801 bool image_is_coherent = false;
2802 uint32_t b;
2803
2804 if (image) {
2805 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2806 flush_CB = false;
2807 flush_DB = false;
2808 }
2809
2810 if (!radv_image_has_CB_metadata(image))
2811 flush_CB_meta = false;
2812 if (!radv_image_has_htile(image))
2813 flush_DB_meta = false;
2814
2815 /* TODO: implement shader coherent for GFX10 */
2816
2817 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2818 if (image->info.samples == 1 &&
2819 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2820 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2821 !vk_format_is_stencil(image->vk_format)) {
2822 /* Single-sample color and single-sample depth
2823 * (not stencil) are coherent with shaders on
2824 * GFX9.
2825 */
2826 image_is_coherent = true;
2827 }
2828 }
2829 }
2830
2831 for_each_bit(b, dst_flags) {
2832 switch ((VkAccessFlagBits)(1 << b)) {
2833 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2834 case VK_ACCESS_INDEX_READ_BIT:
2835 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2836 break;
2837 case VK_ACCESS_UNIFORM_READ_BIT:
2838 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2839 break;
2840 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2841 case VK_ACCESS_TRANSFER_READ_BIT:
2842 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2843 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2844 RADV_CMD_FLAG_INV_L2;
2845 break;
2846 case VK_ACCESS_SHADER_READ_BIT:
2847 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2848 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2849 * invalidate the scalar cache. */
2850 if (cmd_buffer->device->physical_device->use_aco)
2851 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2852
2853 if (!image_is_coherent)
2854 flush_bits |= RADV_CMD_FLAG_INV_L2;
2855 break;
2856 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2857 if (flush_CB)
2858 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2859 if (flush_CB_meta)
2860 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2861 break;
2862 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2863 if (flush_DB)
2864 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2865 if (flush_DB_meta)
2866 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2867 break;
2868 default:
2869 break;
2870 }
2871 }
2872 return flush_bits;
2873 }
2874
2875 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2876 const struct radv_subpass_barrier *barrier)
2877 {
2878 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2879 NULL);
2880 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2881 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2882 NULL);
2883 }
2884
2885 uint32_t
2886 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2887 {
2888 struct radv_cmd_state *state = &cmd_buffer->state;
2889 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2890
2891 /* The id of this subpass shouldn't exceed the number of subpasses in
2892 * this render pass minus 1.
2893 */
2894 assert(subpass_id < state->pass->subpass_count);
2895 return subpass_id;
2896 }
2897
2898 static struct radv_sample_locations_state *
2899 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2900 uint32_t att_idx,
2901 bool begin_subpass)
2902 {
2903 struct radv_cmd_state *state = &cmd_buffer->state;
2904 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2905 struct radv_image_view *view = state->attachments[att_idx].iview;
2906
2907 if (view->image->info.samples == 1)
2908 return NULL;
2909
2910 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2911 /* Return the initial sample locations if this is the initial
2912 * layout transition of the given subpass attachemnt.
2913 */
2914 if (state->attachments[att_idx].sample_location.count > 0)
2915 return &state->attachments[att_idx].sample_location;
2916 } else {
2917 /* Otherwise return the subpass sample locations if defined. */
2918 if (state->subpass_sample_locs) {
2919 /* Because the driver sets the current subpass before
2920 * initial layout transitions, we should use the sample
2921 * locations from the previous subpass to avoid an
2922 * off-by-one problem. Otherwise, use the sample
2923 * locations for the current subpass for final layout
2924 * transitions.
2925 */
2926 if (begin_subpass)
2927 subpass_id--;
2928
2929 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2930 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2931 return &state->subpass_sample_locs[i].sample_location;
2932 }
2933 }
2934 }
2935
2936 return NULL;
2937 }
2938
2939 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2940 struct radv_subpass_attachment att,
2941 bool begin_subpass)
2942 {
2943 unsigned idx = att.attachment;
2944 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2945 struct radv_sample_locations_state *sample_locs;
2946 VkImageSubresourceRange range;
2947 range.aspectMask = 0;
2948 range.baseMipLevel = view->base_mip;
2949 range.levelCount = 1;
2950 range.baseArrayLayer = view->base_layer;
2951 range.layerCount = cmd_buffer->state.framebuffer->layers;
2952
2953 if (cmd_buffer->state.subpass->view_mask) {
2954 /* If the current subpass uses multiview, the driver might have
2955 * performed a fast color/depth clear to the whole image
2956 * (including all layers). To make sure the driver will
2957 * decompress the image correctly (if needed), we have to
2958 * account for the "real" number of layers. If the view mask is
2959 * sparse, this will decompress more layers than needed.
2960 */
2961 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2962 }
2963
2964 /* Get the subpass sample locations for the given attachment, if NULL
2965 * is returned the driver will use the default HW locations.
2966 */
2967 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2968 begin_subpass);
2969
2970 radv_handle_image_transition(cmd_buffer,
2971 view->image,
2972 cmd_buffer->state.attachments[idx].current_layout,
2973 cmd_buffer->state.attachments[idx].current_in_render_loop,
2974 att.layout, att.in_render_loop,
2975 0, 0, &range, sample_locs);
2976
2977 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2978 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
2979
2980
2981 }
2982
2983 void
2984 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2985 const struct radv_subpass *subpass)
2986 {
2987 cmd_buffer->state.subpass = subpass;
2988
2989 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2990 }
2991
2992 static VkResult
2993 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2994 struct radv_render_pass *pass,
2995 const VkRenderPassBeginInfo *info)
2996 {
2997 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2998 vk_find_struct_const(info->pNext,
2999 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3000 struct radv_cmd_state *state = &cmd_buffer->state;
3001
3002 if (!sample_locs) {
3003 state->subpass_sample_locs = NULL;
3004 return VK_SUCCESS;
3005 }
3006
3007 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3008 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3009 &sample_locs->pAttachmentInitialSampleLocations[i];
3010 uint32_t att_idx = att_sample_locs->attachmentIndex;
3011 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3012
3013 assert(vk_format_is_depth_or_stencil(image->vk_format));
3014
3015 /* From the Vulkan spec 1.1.108:
3016 *
3017 * "If the image referenced by the framebuffer attachment at
3018 * index attachmentIndex was not created with
3019 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3020 * then the values specified in sampleLocationsInfo are
3021 * ignored."
3022 */
3023 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3024 continue;
3025
3026 const VkSampleLocationsInfoEXT *sample_locs_info =
3027 &att_sample_locs->sampleLocationsInfo;
3028
3029 state->attachments[att_idx].sample_location.per_pixel =
3030 sample_locs_info->sampleLocationsPerPixel;
3031 state->attachments[att_idx].sample_location.grid_size =
3032 sample_locs_info->sampleLocationGridSize;
3033 state->attachments[att_idx].sample_location.count =
3034 sample_locs_info->sampleLocationsCount;
3035 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3036 sample_locs_info->pSampleLocations,
3037 sample_locs_info->sampleLocationsCount);
3038 }
3039
3040 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3041 sample_locs->postSubpassSampleLocationsCount *
3042 sizeof(state->subpass_sample_locs[0]),
3043 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3044 if (state->subpass_sample_locs == NULL) {
3045 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3046 return cmd_buffer->record_result;
3047 }
3048
3049 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3050
3051 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3052 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3053 &sample_locs->pPostSubpassSampleLocations[i];
3054 const VkSampleLocationsInfoEXT *sample_locs_info =
3055 &subpass_sample_locs_info->sampleLocationsInfo;
3056
3057 state->subpass_sample_locs[i].subpass_idx =
3058 subpass_sample_locs_info->subpassIndex;
3059 state->subpass_sample_locs[i].sample_location.per_pixel =
3060 sample_locs_info->sampleLocationsPerPixel;
3061 state->subpass_sample_locs[i].sample_location.grid_size =
3062 sample_locs_info->sampleLocationGridSize;
3063 state->subpass_sample_locs[i].sample_location.count =
3064 sample_locs_info->sampleLocationsCount;
3065 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3066 sample_locs_info->pSampleLocations,
3067 sample_locs_info->sampleLocationsCount);
3068 }
3069
3070 return VK_SUCCESS;
3071 }
3072
3073 static VkResult
3074 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3075 struct radv_render_pass *pass,
3076 const VkRenderPassBeginInfo *info)
3077 {
3078 struct radv_cmd_state *state = &cmd_buffer->state;
3079 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3080
3081 if (info) {
3082 attachment_info = vk_find_struct_const(info->pNext,
3083 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3084 }
3085
3086
3087 if (pass->attachment_count == 0) {
3088 state->attachments = NULL;
3089 return VK_SUCCESS;
3090 }
3091
3092 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3093 pass->attachment_count *
3094 sizeof(state->attachments[0]),
3095 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3096 if (state->attachments == NULL) {
3097 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3098 return cmd_buffer->record_result;
3099 }
3100
3101 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3102 struct radv_render_pass_attachment *att = &pass->attachments[i];
3103 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3104 VkImageAspectFlags clear_aspects = 0;
3105
3106 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3107 /* color attachment */
3108 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3109 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3110 }
3111 } else {
3112 /* depthstencil attachment */
3113 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3114 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3115 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3116 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3117 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3118 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3119 }
3120 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3121 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3122 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3123 }
3124 }
3125
3126 state->attachments[i].pending_clear_aspects = clear_aspects;
3127 state->attachments[i].cleared_views = 0;
3128 if (clear_aspects && info) {
3129 assert(info->clearValueCount > i);
3130 state->attachments[i].clear_value = info->pClearValues[i];
3131 }
3132
3133 state->attachments[i].current_layout = att->initial_layout;
3134 state->attachments[i].sample_location.count = 0;
3135
3136 struct radv_image_view *iview;
3137 if (attachment_info && attachment_info->attachmentCount > i) {
3138 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3139 } else {
3140 iview = state->framebuffer->attachments[i];
3141 }
3142
3143 state->attachments[i].iview = iview;
3144 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3145 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3146 } else {
3147 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3148 }
3149 }
3150
3151 return VK_SUCCESS;
3152 }
3153
3154 VkResult radv_AllocateCommandBuffers(
3155 VkDevice _device,
3156 const VkCommandBufferAllocateInfo *pAllocateInfo,
3157 VkCommandBuffer *pCommandBuffers)
3158 {
3159 RADV_FROM_HANDLE(radv_device, device, _device);
3160 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3161
3162 VkResult result = VK_SUCCESS;
3163 uint32_t i;
3164
3165 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3166
3167 if (!list_empty(&pool->free_cmd_buffers)) {
3168 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3169
3170 list_del(&cmd_buffer->pool_link);
3171 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3172
3173 result = radv_reset_cmd_buffer(cmd_buffer);
3174 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3175 cmd_buffer->level = pAllocateInfo->level;
3176
3177 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3178 } else {
3179 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3180 &pCommandBuffers[i]);
3181 }
3182 if (result != VK_SUCCESS)
3183 break;
3184 }
3185
3186 if (result != VK_SUCCESS) {
3187 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3188 i, pCommandBuffers);
3189
3190 /* From the Vulkan 1.0.66 spec:
3191 *
3192 * "vkAllocateCommandBuffers can be used to create multiple
3193 * command buffers. If the creation of any of those command
3194 * buffers fails, the implementation must destroy all
3195 * successfully created command buffer objects from this
3196 * command, set all entries of the pCommandBuffers array to
3197 * NULL and return the error."
3198 */
3199 memset(pCommandBuffers, 0,
3200 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3201 }
3202
3203 return result;
3204 }
3205
3206 void radv_FreeCommandBuffers(
3207 VkDevice device,
3208 VkCommandPool commandPool,
3209 uint32_t commandBufferCount,
3210 const VkCommandBuffer *pCommandBuffers)
3211 {
3212 for (uint32_t i = 0; i < commandBufferCount; i++) {
3213 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3214
3215 if (cmd_buffer) {
3216 if (cmd_buffer->pool) {
3217 list_del(&cmd_buffer->pool_link);
3218 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3219 } else
3220 radv_cmd_buffer_destroy(cmd_buffer);
3221
3222 }
3223 }
3224 }
3225
3226 VkResult radv_ResetCommandBuffer(
3227 VkCommandBuffer commandBuffer,
3228 VkCommandBufferResetFlags flags)
3229 {
3230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3231 return radv_reset_cmd_buffer(cmd_buffer);
3232 }
3233
3234 VkResult radv_BeginCommandBuffer(
3235 VkCommandBuffer commandBuffer,
3236 const VkCommandBufferBeginInfo *pBeginInfo)
3237 {
3238 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3239 VkResult result = VK_SUCCESS;
3240
3241 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3242 /* If the command buffer has already been resetted with
3243 * vkResetCommandBuffer, no need to do it again.
3244 */
3245 result = radv_reset_cmd_buffer(cmd_buffer);
3246 if (result != VK_SUCCESS)
3247 return result;
3248 }
3249
3250 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3251 cmd_buffer->state.last_primitive_reset_en = -1;
3252 cmd_buffer->state.last_index_type = -1;
3253 cmd_buffer->state.last_num_instances = -1;
3254 cmd_buffer->state.last_vertex_offset = -1;
3255 cmd_buffer->state.last_first_instance = -1;
3256 cmd_buffer->state.predication_type = -1;
3257 cmd_buffer->usage_flags = pBeginInfo->flags;
3258
3259 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3260 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3261 assert(pBeginInfo->pInheritanceInfo);
3262 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3263 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3264
3265 struct radv_subpass *subpass =
3266 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3267
3268 if (cmd_buffer->state.framebuffer) {
3269 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3270 if (result != VK_SUCCESS)
3271 return result;
3272 }
3273
3274 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3275 }
3276
3277 if (unlikely(cmd_buffer->device->trace_bo)) {
3278 struct radv_device *device = cmd_buffer->device;
3279
3280 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3281 device->trace_bo);
3282
3283 radv_cmd_buffer_trace_emit(cmd_buffer);
3284 }
3285
3286 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3287
3288 return result;
3289 }
3290
3291 void radv_CmdBindVertexBuffers(
3292 VkCommandBuffer commandBuffer,
3293 uint32_t firstBinding,
3294 uint32_t bindingCount,
3295 const VkBuffer* pBuffers,
3296 const VkDeviceSize* pOffsets)
3297 {
3298 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3299 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3300 bool changed = false;
3301
3302 /* We have to defer setting up vertex buffer since we need the buffer
3303 * stride from the pipeline. */
3304
3305 assert(firstBinding + bindingCount <= MAX_VBS);
3306 for (uint32_t i = 0; i < bindingCount; i++) {
3307 uint32_t idx = firstBinding + i;
3308
3309 if (!changed &&
3310 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3311 vb[idx].offset != pOffsets[i])) {
3312 changed = true;
3313 }
3314
3315 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3316 vb[idx].offset = pOffsets[i];
3317
3318 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3319 vb[idx].buffer->bo);
3320 }
3321
3322 if (!changed) {
3323 /* No state changes. */
3324 return;
3325 }
3326
3327 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3328 }
3329
3330 static uint32_t
3331 vk_to_index_type(VkIndexType type)
3332 {
3333 switch (type) {
3334 case VK_INDEX_TYPE_UINT8_EXT:
3335 return V_028A7C_VGT_INDEX_8;
3336 case VK_INDEX_TYPE_UINT16:
3337 return V_028A7C_VGT_INDEX_16;
3338 case VK_INDEX_TYPE_UINT32:
3339 return V_028A7C_VGT_INDEX_32;
3340 default:
3341 unreachable("invalid index type");
3342 }
3343 }
3344
3345 static uint32_t
3346 radv_get_vgt_index_size(uint32_t type)
3347 {
3348 switch (type) {
3349 case V_028A7C_VGT_INDEX_8:
3350 return 1;
3351 case V_028A7C_VGT_INDEX_16:
3352 return 2;
3353 case V_028A7C_VGT_INDEX_32:
3354 return 4;
3355 default:
3356 unreachable("invalid index type");
3357 }
3358 }
3359
3360 void radv_CmdBindIndexBuffer(
3361 VkCommandBuffer commandBuffer,
3362 VkBuffer buffer,
3363 VkDeviceSize offset,
3364 VkIndexType indexType)
3365 {
3366 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3367 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3368
3369 if (cmd_buffer->state.index_buffer == index_buffer &&
3370 cmd_buffer->state.index_offset == offset &&
3371 cmd_buffer->state.index_type == indexType) {
3372 /* No state changes. */
3373 return;
3374 }
3375
3376 cmd_buffer->state.index_buffer = index_buffer;
3377 cmd_buffer->state.index_offset = offset;
3378 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3379 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3380 cmd_buffer->state.index_va += index_buffer->offset + offset;
3381
3382 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3383 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3384 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3385 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3386 }
3387
3388
3389 static void
3390 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3391 VkPipelineBindPoint bind_point,
3392 struct radv_descriptor_set *set, unsigned idx)
3393 {
3394 struct radeon_winsys *ws = cmd_buffer->device->ws;
3395
3396 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3397
3398 assert(set);
3399 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3400
3401 if (!cmd_buffer->device->use_global_bo_list) {
3402 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3403 if (set->descriptors[j])
3404 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3405 }
3406
3407 if(set->bo)
3408 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3409 }
3410
3411 void radv_CmdBindDescriptorSets(
3412 VkCommandBuffer commandBuffer,
3413 VkPipelineBindPoint pipelineBindPoint,
3414 VkPipelineLayout _layout,
3415 uint32_t firstSet,
3416 uint32_t descriptorSetCount,
3417 const VkDescriptorSet* pDescriptorSets,
3418 uint32_t dynamicOffsetCount,
3419 const uint32_t* pDynamicOffsets)
3420 {
3421 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3422 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3423 unsigned dyn_idx = 0;
3424
3425 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3426 struct radv_descriptor_state *descriptors_state =
3427 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3428
3429 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3430 unsigned idx = i + firstSet;
3431 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3432
3433 /* If the set is already bound we only need to update the
3434 * (potentially changed) dynamic offsets. */
3435 if (descriptors_state->sets[idx] != set ||
3436 !(descriptors_state->valid & (1u << idx))) {
3437 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3438 }
3439
3440 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3441 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3442 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3443 assert(dyn_idx < dynamicOffsetCount);
3444
3445 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3446 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3447 dst[0] = va;
3448 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3449 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3450 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3451 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3452 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3453 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3454
3455 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3456 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3457 S_008F0C_OOB_SELECT(3) |
3458 S_008F0C_RESOURCE_LEVEL(1);
3459 } else {
3460 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3461 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3462 }
3463
3464 cmd_buffer->push_constant_stages |=
3465 set->layout->dynamic_shader_stages;
3466 }
3467 }
3468 }
3469
3470 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3471 struct radv_descriptor_set *set,
3472 struct radv_descriptor_set_layout *layout,
3473 VkPipelineBindPoint bind_point)
3474 {
3475 struct radv_descriptor_state *descriptors_state =
3476 radv_get_descriptors_state(cmd_buffer, bind_point);
3477 set->size = layout->size;
3478 set->layout = layout;
3479
3480 if (descriptors_state->push_set.capacity < set->size) {
3481 size_t new_size = MAX2(set->size, 1024);
3482 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3483 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3484
3485 free(set->mapped_ptr);
3486 set->mapped_ptr = malloc(new_size);
3487
3488 if (!set->mapped_ptr) {
3489 descriptors_state->push_set.capacity = 0;
3490 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3491 return false;
3492 }
3493
3494 descriptors_state->push_set.capacity = new_size;
3495 }
3496
3497 return true;
3498 }
3499
3500 void radv_meta_push_descriptor_set(
3501 struct radv_cmd_buffer* cmd_buffer,
3502 VkPipelineBindPoint pipelineBindPoint,
3503 VkPipelineLayout _layout,
3504 uint32_t set,
3505 uint32_t descriptorWriteCount,
3506 const VkWriteDescriptorSet* pDescriptorWrites)
3507 {
3508 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3509 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3510 unsigned bo_offset;
3511
3512 assert(set == 0);
3513 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3514
3515 push_set->size = layout->set[set].layout->size;
3516 push_set->layout = layout->set[set].layout;
3517
3518 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3519 &bo_offset,
3520 (void**) &push_set->mapped_ptr))
3521 return;
3522
3523 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3524 push_set->va += bo_offset;
3525
3526 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3527 radv_descriptor_set_to_handle(push_set),
3528 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3529
3530 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3531 }
3532
3533 void radv_CmdPushDescriptorSetKHR(
3534 VkCommandBuffer commandBuffer,
3535 VkPipelineBindPoint pipelineBindPoint,
3536 VkPipelineLayout _layout,
3537 uint32_t set,
3538 uint32_t descriptorWriteCount,
3539 const VkWriteDescriptorSet* pDescriptorWrites)
3540 {
3541 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3542 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3543 struct radv_descriptor_state *descriptors_state =
3544 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3545 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3546
3547 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3548
3549 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3550 layout->set[set].layout,
3551 pipelineBindPoint))
3552 return;
3553
3554 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3555 * because it is invalid, according to Vulkan spec.
3556 */
3557 for (int i = 0; i < descriptorWriteCount; i++) {
3558 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3559 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3560 }
3561
3562 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3563 radv_descriptor_set_to_handle(push_set),
3564 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3565
3566 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3567 descriptors_state->push_dirty = true;
3568 }
3569
3570 void radv_CmdPushDescriptorSetWithTemplateKHR(
3571 VkCommandBuffer commandBuffer,
3572 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3573 VkPipelineLayout _layout,
3574 uint32_t set,
3575 const void* pData)
3576 {
3577 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3578 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3579 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3580 struct radv_descriptor_state *descriptors_state =
3581 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3582 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3583
3584 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3585
3586 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3587 layout->set[set].layout,
3588 templ->bind_point))
3589 return;
3590
3591 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3592 descriptorUpdateTemplate, pData);
3593
3594 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3595 descriptors_state->push_dirty = true;
3596 }
3597
3598 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3599 VkPipelineLayout layout,
3600 VkShaderStageFlags stageFlags,
3601 uint32_t offset,
3602 uint32_t size,
3603 const void* pValues)
3604 {
3605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3606 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3607 cmd_buffer->push_constant_stages |= stageFlags;
3608 }
3609
3610 VkResult radv_EndCommandBuffer(
3611 VkCommandBuffer commandBuffer)
3612 {
3613 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3614
3615 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3616 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3617 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3618
3619 /* Make sure to sync all pending active queries at the end of
3620 * command buffer.
3621 */
3622 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3623
3624 /* Since NGG streamout uses GDS, we need to make GDS idle when
3625 * we leave the IB, otherwise another process might overwrite
3626 * it while our shaders are busy.
3627 */
3628 if (cmd_buffer->gds_needed)
3629 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3630
3631 si_emit_cache_flush(cmd_buffer);
3632 }
3633
3634 /* Make sure CP DMA is idle at the end of IBs because the kernel
3635 * doesn't wait for it.
3636 */
3637 si_cp_dma_wait_for_idle(cmd_buffer);
3638
3639 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3640 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3641
3642 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3643 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3644
3645 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3646
3647 return cmd_buffer->record_result;
3648 }
3649
3650 static void
3651 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3652 {
3653 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3654
3655 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3656 return;
3657
3658 assert(!pipeline->ctx_cs.cdw);
3659
3660 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3661
3662 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3663 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3664
3665 cmd_buffer->compute_scratch_size_needed =
3666 MAX2(cmd_buffer->compute_scratch_size_needed,
3667 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3668
3669 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3670 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3671
3672 if (unlikely(cmd_buffer->device->trace_bo))
3673 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3674 }
3675
3676 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3677 VkPipelineBindPoint bind_point)
3678 {
3679 struct radv_descriptor_state *descriptors_state =
3680 radv_get_descriptors_state(cmd_buffer, bind_point);
3681
3682 descriptors_state->dirty |= descriptors_state->valid;
3683 }
3684
3685 void radv_CmdBindPipeline(
3686 VkCommandBuffer commandBuffer,
3687 VkPipelineBindPoint pipelineBindPoint,
3688 VkPipeline _pipeline)
3689 {
3690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3691 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3692
3693 switch (pipelineBindPoint) {
3694 case VK_PIPELINE_BIND_POINT_COMPUTE:
3695 if (cmd_buffer->state.compute_pipeline == pipeline)
3696 return;
3697 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3698
3699 cmd_buffer->state.compute_pipeline = pipeline;
3700 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3701 break;
3702 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3703 if (cmd_buffer->state.pipeline == pipeline)
3704 return;
3705 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3706
3707 cmd_buffer->state.pipeline = pipeline;
3708 if (!pipeline)
3709 break;
3710
3711 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3712 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3713
3714 /* the new vertex shader might not have the same user regs */
3715 cmd_buffer->state.last_first_instance = -1;
3716 cmd_buffer->state.last_vertex_offset = -1;
3717
3718 /* Prefetch all pipeline shaders at first draw time. */
3719 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3720
3721 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3722 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3723 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3724 cmd_buffer->state.emitted_pipeline &&
3725 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3726 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3727 /* Transitioning from NGG to legacy GS requires
3728 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3729 * at the beginning of IBs when legacy GS ring pointers
3730 * are set.
3731 */
3732 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3733 }
3734
3735 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3736 radv_bind_streamout_state(cmd_buffer, pipeline);
3737
3738 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3739 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3740 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3741 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3742
3743 if (radv_pipeline_has_tess(pipeline))
3744 cmd_buffer->tess_rings_needed = true;
3745 break;
3746 default:
3747 assert(!"invalid bind point");
3748 break;
3749 }
3750 }
3751
3752 void radv_CmdSetViewport(
3753 VkCommandBuffer commandBuffer,
3754 uint32_t firstViewport,
3755 uint32_t viewportCount,
3756 const VkViewport* pViewports)
3757 {
3758 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3759 struct radv_cmd_state *state = &cmd_buffer->state;
3760 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3761
3762 assert(firstViewport < MAX_VIEWPORTS);
3763 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3764
3765 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3766 pViewports, viewportCount * sizeof(*pViewports))) {
3767 return;
3768 }
3769
3770 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3771 viewportCount * sizeof(*pViewports));
3772
3773 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3774 }
3775
3776 void radv_CmdSetScissor(
3777 VkCommandBuffer commandBuffer,
3778 uint32_t firstScissor,
3779 uint32_t scissorCount,
3780 const VkRect2D* pScissors)
3781 {
3782 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3783 struct radv_cmd_state *state = &cmd_buffer->state;
3784 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3785
3786 assert(firstScissor < MAX_SCISSORS);
3787 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3788
3789 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3790 scissorCount * sizeof(*pScissors))) {
3791 return;
3792 }
3793
3794 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3795 scissorCount * sizeof(*pScissors));
3796
3797 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3798 }
3799
3800 void radv_CmdSetLineWidth(
3801 VkCommandBuffer commandBuffer,
3802 float lineWidth)
3803 {
3804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3805
3806 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3807 return;
3808
3809 cmd_buffer->state.dynamic.line_width = lineWidth;
3810 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3811 }
3812
3813 void radv_CmdSetDepthBias(
3814 VkCommandBuffer commandBuffer,
3815 float depthBiasConstantFactor,
3816 float depthBiasClamp,
3817 float depthBiasSlopeFactor)
3818 {
3819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3820 struct radv_cmd_state *state = &cmd_buffer->state;
3821
3822 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3823 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3824 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3825 return;
3826 }
3827
3828 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3829 state->dynamic.depth_bias.clamp = depthBiasClamp;
3830 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3831
3832 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3833 }
3834
3835 void radv_CmdSetBlendConstants(
3836 VkCommandBuffer commandBuffer,
3837 const float blendConstants[4])
3838 {
3839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3840 struct radv_cmd_state *state = &cmd_buffer->state;
3841
3842 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3843 return;
3844
3845 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3846
3847 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3848 }
3849
3850 void radv_CmdSetDepthBounds(
3851 VkCommandBuffer commandBuffer,
3852 float minDepthBounds,
3853 float maxDepthBounds)
3854 {
3855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3856 struct radv_cmd_state *state = &cmd_buffer->state;
3857
3858 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3859 state->dynamic.depth_bounds.max == maxDepthBounds) {
3860 return;
3861 }
3862
3863 state->dynamic.depth_bounds.min = minDepthBounds;
3864 state->dynamic.depth_bounds.max = maxDepthBounds;
3865
3866 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3867 }
3868
3869 void radv_CmdSetStencilCompareMask(
3870 VkCommandBuffer commandBuffer,
3871 VkStencilFaceFlags faceMask,
3872 uint32_t compareMask)
3873 {
3874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3875 struct radv_cmd_state *state = &cmd_buffer->state;
3876 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3877 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3878
3879 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3880 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3881 return;
3882 }
3883
3884 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3885 state->dynamic.stencil_compare_mask.front = compareMask;
3886 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3887 state->dynamic.stencil_compare_mask.back = compareMask;
3888
3889 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3890 }
3891
3892 void radv_CmdSetStencilWriteMask(
3893 VkCommandBuffer commandBuffer,
3894 VkStencilFaceFlags faceMask,
3895 uint32_t writeMask)
3896 {
3897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3898 struct radv_cmd_state *state = &cmd_buffer->state;
3899 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3900 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3901
3902 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3903 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3904 return;
3905 }
3906
3907 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3908 state->dynamic.stencil_write_mask.front = writeMask;
3909 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3910 state->dynamic.stencil_write_mask.back = writeMask;
3911
3912 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3913 }
3914
3915 void radv_CmdSetStencilReference(
3916 VkCommandBuffer commandBuffer,
3917 VkStencilFaceFlags faceMask,
3918 uint32_t reference)
3919 {
3920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3921 struct radv_cmd_state *state = &cmd_buffer->state;
3922 bool front_same = state->dynamic.stencil_reference.front == reference;
3923 bool back_same = state->dynamic.stencil_reference.back == reference;
3924
3925 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3926 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3927 return;
3928 }
3929
3930 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3931 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3932 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3933 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3934
3935 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3936 }
3937
3938 void radv_CmdSetDiscardRectangleEXT(
3939 VkCommandBuffer commandBuffer,
3940 uint32_t firstDiscardRectangle,
3941 uint32_t discardRectangleCount,
3942 const VkRect2D* pDiscardRectangles)
3943 {
3944 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3945 struct radv_cmd_state *state = &cmd_buffer->state;
3946 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3947
3948 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3949 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3950
3951 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3952 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3953 return;
3954 }
3955
3956 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3957 pDiscardRectangles, discardRectangleCount);
3958
3959 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3960 }
3961
3962 void radv_CmdSetSampleLocationsEXT(
3963 VkCommandBuffer commandBuffer,
3964 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3965 {
3966 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3967 struct radv_cmd_state *state = &cmd_buffer->state;
3968
3969 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3970
3971 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3972 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3973 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3974 typed_memcpy(&state->dynamic.sample_location.locations[0],
3975 pSampleLocationsInfo->pSampleLocations,
3976 pSampleLocationsInfo->sampleLocationsCount);
3977
3978 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3979 }
3980
3981 void radv_CmdExecuteCommands(
3982 VkCommandBuffer commandBuffer,
3983 uint32_t commandBufferCount,
3984 const VkCommandBuffer* pCmdBuffers)
3985 {
3986 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3987
3988 assert(commandBufferCount > 0);
3989
3990 /* Emit pending flushes on primary prior to executing secondary */
3991 si_emit_cache_flush(primary);
3992
3993 for (uint32_t i = 0; i < commandBufferCount; i++) {
3994 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3995
3996 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3997 secondary->scratch_size_needed);
3998 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3999 secondary->compute_scratch_size_needed);
4000
4001 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4002 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4003 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4004 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4005 if (secondary->tess_rings_needed)
4006 primary->tess_rings_needed = true;
4007 if (secondary->sample_positions_needed)
4008 primary->sample_positions_needed = true;
4009
4010 if (!secondary->state.framebuffer &&
4011 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4012 /* Emit the framebuffer state from primary if secondary
4013 * has been recorded without a framebuffer, otherwise
4014 * fast color/depth clears can't work.
4015 */
4016 radv_emit_framebuffer_state(primary);
4017 }
4018
4019 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4020
4021
4022 /* When the secondary command buffer is compute only we don't
4023 * need to re-emit the current graphics pipeline.
4024 */
4025 if (secondary->state.emitted_pipeline) {
4026 primary->state.emitted_pipeline =
4027 secondary->state.emitted_pipeline;
4028 }
4029
4030 /* When the secondary command buffer is graphics only we don't
4031 * need to re-emit the current compute pipeline.
4032 */
4033 if (secondary->state.emitted_compute_pipeline) {
4034 primary->state.emitted_compute_pipeline =
4035 secondary->state.emitted_compute_pipeline;
4036 }
4037
4038 /* Only re-emit the draw packets when needed. */
4039 if (secondary->state.last_primitive_reset_en != -1) {
4040 primary->state.last_primitive_reset_en =
4041 secondary->state.last_primitive_reset_en;
4042 }
4043
4044 if (secondary->state.last_primitive_reset_index) {
4045 primary->state.last_primitive_reset_index =
4046 secondary->state.last_primitive_reset_index;
4047 }
4048
4049 if (secondary->state.last_ia_multi_vgt_param) {
4050 primary->state.last_ia_multi_vgt_param =
4051 secondary->state.last_ia_multi_vgt_param;
4052 }
4053
4054 primary->state.last_first_instance = secondary->state.last_first_instance;
4055 primary->state.last_num_instances = secondary->state.last_num_instances;
4056 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4057
4058 if (secondary->state.last_index_type != -1) {
4059 primary->state.last_index_type =
4060 secondary->state.last_index_type;
4061 }
4062 }
4063
4064 /* After executing commands from secondary buffers we have to dirty
4065 * some states.
4066 */
4067 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4068 RADV_CMD_DIRTY_INDEX_BUFFER |
4069 RADV_CMD_DIRTY_DYNAMIC_ALL;
4070 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4071 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4072 }
4073
4074 VkResult radv_CreateCommandPool(
4075 VkDevice _device,
4076 const VkCommandPoolCreateInfo* pCreateInfo,
4077 const VkAllocationCallbacks* pAllocator,
4078 VkCommandPool* pCmdPool)
4079 {
4080 RADV_FROM_HANDLE(radv_device, device, _device);
4081 struct radv_cmd_pool *pool;
4082
4083 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4084 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4085 if (pool == NULL)
4086 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4087
4088 if (pAllocator)
4089 pool->alloc = *pAllocator;
4090 else
4091 pool->alloc = device->alloc;
4092
4093 list_inithead(&pool->cmd_buffers);
4094 list_inithead(&pool->free_cmd_buffers);
4095
4096 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4097
4098 *pCmdPool = radv_cmd_pool_to_handle(pool);
4099
4100 return VK_SUCCESS;
4101
4102 }
4103
4104 void radv_DestroyCommandPool(
4105 VkDevice _device,
4106 VkCommandPool commandPool,
4107 const VkAllocationCallbacks* pAllocator)
4108 {
4109 RADV_FROM_HANDLE(radv_device, device, _device);
4110 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4111
4112 if (!pool)
4113 return;
4114
4115 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4116 &pool->cmd_buffers, pool_link) {
4117 radv_cmd_buffer_destroy(cmd_buffer);
4118 }
4119
4120 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4121 &pool->free_cmd_buffers, pool_link) {
4122 radv_cmd_buffer_destroy(cmd_buffer);
4123 }
4124
4125 vk_free2(&device->alloc, pAllocator, pool);
4126 }
4127
4128 VkResult radv_ResetCommandPool(
4129 VkDevice device,
4130 VkCommandPool commandPool,
4131 VkCommandPoolResetFlags flags)
4132 {
4133 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4134 VkResult result;
4135
4136 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4137 &pool->cmd_buffers, pool_link) {
4138 result = radv_reset_cmd_buffer(cmd_buffer);
4139 if (result != VK_SUCCESS)
4140 return result;
4141 }
4142
4143 return VK_SUCCESS;
4144 }
4145
4146 void radv_TrimCommandPool(
4147 VkDevice device,
4148 VkCommandPool commandPool,
4149 VkCommandPoolTrimFlags flags)
4150 {
4151 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4152
4153 if (!pool)
4154 return;
4155
4156 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4157 &pool->free_cmd_buffers, pool_link) {
4158 radv_cmd_buffer_destroy(cmd_buffer);
4159 }
4160 }
4161
4162 static void
4163 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4164 uint32_t subpass_id)
4165 {
4166 struct radv_cmd_state *state = &cmd_buffer->state;
4167 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4168
4169 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4170 cmd_buffer->cs, 4096);
4171
4172 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4173
4174 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4175
4176 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4177 const uint32_t a = subpass->attachments[i].attachment;
4178 if (a == VK_ATTACHMENT_UNUSED)
4179 continue;
4180
4181 radv_handle_subpass_image_transition(cmd_buffer,
4182 subpass->attachments[i],
4183 true);
4184 }
4185
4186 radv_cmd_buffer_clear_subpass(cmd_buffer);
4187
4188 assert(cmd_buffer->cs->cdw <= cdw_max);
4189 }
4190
4191 static void
4192 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4193 {
4194 struct radv_cmd_state *state = &cmd_buffer->state;
4195 const struct radv_subpass *subpass = state->subpass;
4196 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4197
4198 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4199
4200 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4201 const uint32_t a = subpass->attachments[i].attachment;
4202 if (a == VK_ATTACHMENT_UNUSED)
4203 continue;
4204
4205 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4206 continue;
4207
4208 VkImageLayout layout = state->pass->attachments[a].final_layout;
4209 struct radv_subpass_attachment att = { a, layout };
4210 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4211 }
4212 }
4213
4214 void radv_CmdBeginRenderPass(
4215 VkCommandBuffer commandBuffer,
4216 const VkRenderPassBeginInfo* pRenderPassBegin,
4217 VkSubpassContents contents)
4218 {
4219 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4220 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4221 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4222 VkResult result;
4223
4224 cmd_buffer->state.framebuffer = framebuffer;
4225 cmd_buffer->state.pass = pass;
4226 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4227
4228 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4229 if (result != VK_SUCCESS)
4230 return;
4231
4232 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4233 if (result != VK_SUCCESS)
4234 return;
4235
4236 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4237 }
4238
4239 void radv_CmdBeginRenderPass2KHR(
4240 VkCommandBuffer commandBuffer,
4241 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4242 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4243 {
4244 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4245 pSubpassBeginInfo->contents);
4246 }
4247
4248 void radv_CmdNextSubpass(
4249 VkCommandBuffer commandBuffer,
4250 VkSubpassContents contents)
4251 {
4252 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4253
4254 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4255 radv_cmd_buffer_end_subpass(cmd_buffer);
4256 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4257 }
4258
4259 void radv_CmdNextSubpass2KHR(
4260 VkCommandBuffer commandBuffer,
4261 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4262 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4263 {
4264 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4265 }
4266
4267 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4268 {
4269 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4270 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4271 if (!radv_get_shader(pipeline, stage))
4272 continue;
4273
4274 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4275 if (loc->sgpr_idx == -1)
4276 continue;
4277 uint32_t base_reg = pipeline->user_data_0[stage];
4278 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4279
4280 }
4281 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4282 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4283 if (loc->sgpr_idx != -1) {
4284 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4285 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4286 }
4287 }
4288 }
4289
4290 static void
4291 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4292 uint32_t vertex_count,
4293 bool use_opaque)
4294 {
4295 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4296 radeon_emit(cmd_buffer->cs, vertex_count);
4297 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4298 S_0287F0_USE_OPAQUE(use_opaque));
4299 }
4300
4301 static void
4302 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4303 uint64_t index_va,
4304 uint32_t index_count)
4305 {
4306 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4307 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4308 radeon_emit(cmd_buffer->cs, index_va);
4309 radeon_emit(cmd_buffer->cs, index_va >> 32);
4310 radeon_emit(cmd_buffer->cs, index_count);
4311 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4312 }
4313
4314 static void
4315 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4316 bool indexed,
4317 uint32_t draw_count,
4318 uint64_t count_va,
4319 uint32_t stride)
4320 {
4321 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4322 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4323 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4324 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4325 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4326 bool predicating = cmd_buffer->state.predicating;
4327 assert(base_reg);
4328
4329 /* just reset draw state for vertex data */
4330 cmd_buffer->state.last_first_instance = -1;
4331 cmd_buffer->state.last_num_instances = -1;
4332 cmd_buffer->state.last_vertex_offset = -1;
4333
4334 if (draw_count == 1 && !count_va && !draw_id_enable) {
4335 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4336 PKT3_DRAW_INDIRECT, 3, predicating));
4337 radeon_emit(cs, 0);
4338 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4339 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4340 radeon_emit(cs, di_src_sel);
4341 } else {
4342 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4343 PKT3_DRAW_INDIRECT_MULTI,
4344 8, predicating));
4345 radeon_emit(cs, 0);
4346 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4347 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4348 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4349 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4350 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4351 radeon_emit(cs, draw_count); /* count */
4352 radeon_emit(cs, count_va); /* count_addr */
4353 radeon_emit(cs, count_va >> 32);
4354 radeon_emit(cs, stride); /* stride */
4355 radeon_emit(cs, di_src_sel);
4356 }
4357 }
4358
4359 static void
4360 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4361 const struct radv_draw_info *info)
4362 {
4363 struct radv_cmd_state *state = &cmd_buffer->state;
4364 struct radeon_winsys *ws = cmd_buffer->device->ws;
4365 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4366
4367 if (info->indirect) {
4368 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4369 uint64_t count_va = 0;
4370
4371 va += info->indirect->offset + info->indirect_offset;
4372
4373 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4374
4375 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4376 radeon_emit(cs, 1);
4377 radeon_emit(cs, va);
4378 radeon_emit(cs, va >> 32);
4379
4380 if (info->count_buffer) {
4381 count_va = radv_buffer_get_va(info->count_buffer->bo);
4382 count_va += info->count_buffer->offset +
4383 info->count_buffer_offset;
4384
4385 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4386 }
4387
4388 if (!state->subpass->view_mask) {
4389 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4390 info->indexed,
4391 info->count,
4392 count_va,
4393 info->stride);
4394 } else {
4395 unsigned i;
4396 for_each_bit(i, state->subpass->view_mask) {
4397 radv_emit_view_index(cmd_buffer, i);
4398
4399 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4400 info->indexed,
4401 info->count,
4402 count_va,
4403 info->stride);
4404 }
4405 }
4406 } else {
4407 assert(state->pipeline->graphics.vtx_base_sgpr);
4408
4409 if (info->vertex_offset != state->last_vertex_offset ||
4410 info->first_instance != state->last_first_instance) {
4411 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4412 state->pipeline->graphics.vtx_emit_num);
4413
4414 radeon_emit(cs, info->vertex_offset);
4415 radeon_emit(cs, info->first_instance);
4416 if (state->pipeline->graphics.vtx_emit_num == 3)
4417 radeon_emit(cs, 0);
4418 state->last_first_instance = info->first_instance;
4419 state->last_vertex_offset = info->vertex_offset;
4420 }
4421
4422 if (state->last_num_instances != info->instance_count) {
4423 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4424 radeon_emit(cs, info->instance_count);
4425 state->last_num_instances = info->instance_count;
4426 }
4427
4428 if (info->indexed) {
4429 int index_size = radv_get_vgt_index_size(state->index_type);
4430 uint64_t index_va;
4431
4432 /* Skip draw calls with 0-sized index buffers. They
4433 * cause a hang on some chips, like Navi10-14.
4434 */
4435 if (!cmd_buffer->state.max_index_count)
4436 return;
4437
4438 index_va = state->index_va;
4439 index_va += info->first_index * index_size;
4440
4441 if (!state->subpass->view_mask) {
4442 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4443 index_va,
4444 info->count);
4445 } else {
4446 unsigned i;
4447 for_each_bit(i, state->subpass->view_mask) {
4448 radv_emit_view_index(cmd_buffer, i);
4449
4450 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4451 index_va,
4452 info->count);
4453 }
4454 }
4455 } else {
4456 if (!state->subpass->view_mask) {
4457 radv_cs_emit_draw_packet(cmd_buffer,
4458 info->count,
4459 !!info->strmout_buffer);
4460 } else {
4461 unsigned i;
4462 for_each_bit(i, state->subpass->view_mask) {
4463 radv_emit_view_index(cmd_buffer, i);
4464
4465 radv_cs_emit_draw_packet(cmd_buffer,
4466 info->count,
4467 !!info->strmout_buffer);
4468 }
4469 }
4470 }
4471 }
4472 }
4473
4474 /*
4475 * Vega and raven have a bug which triggers if there are multiple context
4476 * register contexts active at the same time with different scissor values.
4477 *
4478 * There are two possible workarounds:
4479 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4480 * there is only ever 1 active set of scissor values at the same time.
4481 *
4482 * 2) Whenever the hardware switches contexts we have to set the scissor
4483 * registers again even if it is a noop. That way the new context gets
4484 * the correct scissor values.
4485 *
4486 * This implements option 2. radv_need_late_scissor_emission needs to
4487 * return true on affected HW if radv_emit_all_graphics_states sets
4488 * any context registers.
4489 */
4490 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4491 const struct radv_draw_info *info)
4492 {
4493 struct radv_cmd_state *state = &cmd_buffer->state;
4494
4495 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4496 return false;
4497
4498 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4499 return true;
4500
4501 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4502
4503 /* Index, vertex and streamout buffers don't change context regs, and
4504 * pipeline is already handled.
4505 */
4506 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4507 RADV_CMD_DIRTY_VERTEX_BUFFER |
4508 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4509 RADV_CMD_DIRTY_PIPELINE);
4510
4511 if (cmd_buffer->state.dirty & used_states)
4512 return true;
4513
4514 uint32_t primitive_reset_index =
4515 radv_get_primitive_reset_index(cmd_buffer);
4516
4517 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4518 primitive_reset_index != state->last_primitive_reset_index)
4519 return true;
4520
4521 return false;
4522 }
4523
4524 static void
4525 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4526 const struct radv_draw_info *info)
4527 {
4528 bool late_scissor_emission;
4529
4530 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4531 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4532 radv_emit_rbplus_state(cmd_buffer);
4533
4534 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4535 radv_emit_graphics_pipeline(cmd_buffer);
4536
4537 /* This should be before the cmd_buffer->state.dirty is cleared
4538 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4539 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4540 late_scissor_emission =
4541 radv_need_late_scissor_emission(cmd_buffer, info);
4542
4543 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4544 radv_emit_framebuffer_state(cmd_buffer);
4545
4546 if (info->indexed) {
4547 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4548 radv_emit_index_buffer(cmd_buffer);
4549 } else {
4550 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4551 * so the state must be re-emitted before the next indexed
4552 * draw.
4553 */
4554 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4555 cmd_buffer->state.last_index_type = -1;
4556 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4557 }
4558 }
4559
4560 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4561
4562 radv_emit_draw_registers(cmd_buffer, info);
4563
4564 if (late_scissor_emission)
4565 radv_emit_scissor(cmd_buffer);
4566 }
4567
4568 static void
4569 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4570 const struct radv_draw_info *info)
4571 {
4572 struct radeon_info *rad_info =
4573 &cmd_buffer->device->physical_device->rad_info;
4574 bool has_prefetch =
4575 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4576 bool pipeline_is_dirty =
4577 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4578 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4579
4580 ASSERTED unsigned cdw_max =
4581 radeon_check_space(cmd_buffer->device->ws,
4582 cmd_buffer->cs, 4096);
4583
4584 if (likely(!info->indirect)) {
4585 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4586 * no workaround for indirect draws, but we can at least skip
4587 * direct draws.
4588 */
4589 if (unlikely(!info->instance_count))
4590 return;
4591
4592 /* Handle count == 0. */
4593 if (unlikely(!info->count && !info->strmout_buffer))
4594 return;
4595 }
4596
4597 /* Use optimal packet order based on whether we need to sync the
4598 * pipeline.
4599 */
4600 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4601 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4602 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4603 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4604 /* If we have to wait for idle, set all states first, so that
4605 * all SET packets are processed in parallel with previous draw
4606 * calls. Then upload descriptors, set shader pointers, and
4607 * draw, and prefetch at the end. This ensures that the time
4608 * the CUs are idle is very short. (there are only SET_SH
4609 * packets between the wait and the draw)
4610 */
4611 radv_emit_all_graphics_states(cmd_buffer, info);
4612 si_emit_cache_flush(cmd_buffer);
4613 /* <-- CUs are idle here --> */
4614
4615 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4616
4617 radv_emit_draw_packets(cmd_buffer, info);
4618 /* <-- CUs are busy here --> */
4619
4620 /* Start prefetches after the draw has been started. Both will
4621 * run in parallel, but starting the draw first is more
4622 * important.
4623 */
4624 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4625 radv_emit_prefetch_L2(cmd_buffer,
4626 cmd_buffer->state.pipeline, false);
4627 }
4628 } else {
4629 /* If we don't wait for idle, start prefetches first, then set
4630 * states, and draw at the end.
4631 */
4632 si_emit_cache_flush(cmd_buffer);
4633
4634 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4635 /* Only prefetch the vertex shader and VBO descriptors
4636 * in order to start the draw as soon as possible.
4637 */
4638 radv_emit_prefetch_L2(cmd_buffer,
4639 cmd_buffer->state.pipeline, true);
4640 }
4641
4642 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4643
4644 radv_emit_all_graphics_states(cmd_buffer, info);
4645 radv_emit_draw_packets(cmd_buffer, info);
4646
4647 /* Prefetch the remaining shaders after the draw has been
4648 * started.
4649 */
4650 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4651 radv_emit_prefetch_L2(cmd_buffer,
4652 cmd_buffer->state.pipeline, false);
4653 }
4654 }
4655
4656 /* Workaround for a VGT hang when streamout is enabled.
4657 * It must be done after drawing.
4658 */
4659 if (cmd_buffer->state.streamout.streamout_enabled &&
4660 (rad_info->family == CHIP_HAWAII ||
4661 rad_info->family == CHIP_TONGA ||
4662 rad_info->family == CHIP_FIJI)) {
4663 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4664 }
4665
4666 assert(cmd_buffer->cs->cdw <= cdw_max);
4667 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4668 }
4669
4670 void radv_CmdDraw(
4671 VkCommandBuffer commandBuffer,
4672 uint32_t vertexCount,
4673 uint32_t instanceCount,
4674 uint32_t firstVertex,
4675 uint32_t firstInstance)
4676 {
4677 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4678 struct radv_draw_info info = {};
4679
4680 info.count = vertexCount;
4681 info.instance_count = instanceCount;
4682 info.first_instance = firstInstance;
4683 info.vertex_offset = firstVertex;
4684
4685 radv_draw(cmd_buffer, &info);
4686 }
4687
4688 void radv_CmdDrawIndexed(
4689 VkCommandBuffer commandBuffer,
4690 uint32_t indexCount,
4691 uint32_t instanceCount,
4692 uint32_t firstIndex,
4693 int32_t vertexOffset,
4694 uint32_t firstInstance)
4695 {
4696 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4697 struct radv_draw_info info = {};
4698
4699 info.indexed = true;
4700 info.count = indexCount;
4701 info.instance_count = instanceCount;
4702 info.first_index = firstIndex;
4703 info.vertex_offset = vertexOffset;
4704 info.first_instance = firstInstance;
4705
4706 radv_draw(cmd_buffer, &info);
4707 }
4708
4709 void radv_CmdDrawIndirect(
4710 VkCommandBuffer commandBuffer,
4711 VkBuffer _buffer,
4712 VkDeviceSize offset,
4713 uint32_t drawCount,
4714 uint32_t stride)
4715 {
4716 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4717 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4718 struct radv_draw_info info = {};
4719
4720 info.count = drawCount;
4721 info.indirect = buffer;
4722 info.indirect_offset = offset;
4723 info.stride = stride;
4724
4725 radv_draw(cmd_buffer, &info);
4726 }
4727
4728 void radv_CmdDrawIndexedIndirect(
4729 VkCommandBuffer commandBuffer,
4730 VkBuffer _buffer,
4731 VkDeviceSize offset,
4732 uint32_t drawCount,
4733 uint32_t stride)
4734 {
4735 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4736 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4737 struct radv_draw_info info = {};
4738
4739 info.indexed = true;
4740 info.count = drawCount;
4741 info.indirect = buffer;
4742 info.indirect_offset = offset;
4743 info.stride = stride;
4744
4745 radv_draw(cmd_buffer, &info);
4746 }
4747
4748 void radv_CmdDrawIndirectCountKHR(
4749 VkCommandBuffer commandBuffer,
4750 VkBuffer _buffer,
4751 VkDeviceSize offset,
4752 VkBuffer _countBuffer,
4753 VkDeviceSize countBufferOffset,
4754 uint32_t maxDrawCount,
4755 uint32_t stride)
4756 {
4757 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4758 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4759 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4760 struct radv_draw_info info = {};
4761
4762 info.count = maxDrawCount;
4763 info.indirect = buffer;
4764 info.indirect_offset = offset;
4765 info.count_buffer = count_buffer;
4766 info.count_buffer_offset = countBufferOffset;
4767 info.stride = stride;
4768
4769 radv_draw(cmd_buffer, &info);
4770 }
4771
4772 void radv_CmdDrawIndexedIndirectCountKHR(
4773 VkCommandBuffer commandBuffer,
4774 VkBuffer _buffer,
4775 VkDeviceSize offset,
4776 VkBuffer _countBuffer,
4777 VkDeviceSize countBufferOffset,
4778 uint32_t maxDrawCount,
4779 uint32_t stride)
4780 {
4781 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4782 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4783 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4784 struct radv_draw_info info = {};
4785
4786 info.indexed = true;
4787 info.count = maxDrawCount;
4788 info.indirect = buffer;
4789 info.indirect_offset = offset;
4790 info.count_buffer = count_buffer;
4791 info.count_buffer_offset = countBufferOffset;
4792 info.stride = stride;
4793
4794 radv_draw(cmd_buffer, &info);
4795 }
4796
4797 struct radv_dispatch_info {
4798 /**
4799 * Determine the layout of the grid (in block units) to be used.
4800 */
4801 uint32_t blocks[3];
4802
4803 /**
4804 * A starting offset for the grid. If unaligned is set, the offset
4805 * must still be aligned.
4806 */
4807 uint32_t offsets[3];
4808 /**
4809 * Whether it's an unaligned compute dispatch.
4810 */
4811 bool unaligned;
4812
4813 /**
4814 * Indirect compute parameters resource.
4815 */
4816 struct radv_buffer *indirect;
4817 uint64_t indirect_offset;
4818 };
4819
4820 static void
4821 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4822 const struct radv_dispatch_info *info)
4823 {
4824 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4825 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4826 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4827 struct radeon_winsys *ws = cmd_buffer->device->ws;
4828 bool predicating = cmd_buffer->state.predicating;
4829 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4830 struct radv_userdata_info *loc;
4831
4832 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4833 AC_UD_CS_GRID_SIZE);
4834
4835 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4836
4837 if (info->indirect) {
4838 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4839
4840 va += info->indirect->offset + info->indirect_offset;
4841
4842 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4843
4844 if (loc->sgpr_idx != -1) {
4845 for (unsigned i = 0; i < 3; ++i) {
4846 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4847 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4848 COPY_DATA_DST_SEL(COPY_DATA_REG));
4849 radeon_emit(cs, (va + 4 * i));
4850 radeon_emit(cs, (va + 4 * i) >> 32);
4851 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4852 + loc->sgpr_idx * 4) >> 2) + i);
4853 radeon_emit(cs, 0);
4854 }
4855 }
4856
4857 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4858 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4859 PKT3_SHADER_TYPE_S(1));
4860 radeon_emit(cs, va);
4861 radeon_emit(cs, va >> 32);
4862 radeon_emit(cs, dispatch_initiator);
4863 } else {
4864 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4865 PKT3_SHADER_TYPE_S(1));
4866 radeon_emit(cs, 1);
4867 radeon_emit(cs, va);
4868 radeon_emit(cs, va >> 32);
4869
4870 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4871 PKT3_SHADER_TYPE_S(1));
4872 radeon_emit(cs, 0);
4873 radeon_emit(cs, dispatch_initiator);
4874 }
4875 } else {
4876 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4877 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4878
4879 if (info->unaligned) {
4880 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4881 unsigned remainder[3];
4882
4883 /* If aligned, these should be an entire block size,
4884 * not 0.
4885 */
4886 remainder[0] = blocks[0] + cs_block_size[0] -
4887 align_u32_npot(blocks[0], cs_block_size[0]);
4888 remainder[1] = blocks[1] + cs_block_size[1] -
4889 align_u32_npot(blocks[1], cs_block_size[1]);
4890 remainder[2] = blocks[2] + cs_block_size[2] -
4891 align_u32_npot(blocks[2], cs_block_size[2]);
4892
4893 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4894 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4895 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4896
4897 for(unsigned i = 0; i < 3; ++i) {
4898 assert(offsets[i] % cs_block_size[i] == 0);
4899 offsets[i] /= cs_block_size[i];
4900 }
4901
4902 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4903 radeon_emit(cs,
4904 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4905 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4906 radeon_emit(cs,
4907 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4908 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4909 radeon_emit(cs,
4910 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4911 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4912
4913 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4914 }
4915
4916 if (loc->sgpr_idx != -1) {
4917 assert(loc->num_sgprs == 3);
4918
4919 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4920 loc->sgpr_idx * 4, 3);
4921 radeon_emit(cs, blocks[0]);
4922 radeon_emit(cs, blocks[1]);
4923 radeon_emit(cs, blocks[2]);
4924 }
4925
4926 if (offsets[0] || offsets[1] || offsets[2]) {
4927 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4928 radeon_emit(cs, offsets[0]);
4929 radeon_emit(cs, offsets[1]);
4930 radeon_emit(cs, offsets[2]);
4931
4932 /* The blocks in the packet are not counts but end values. */
4933 for (unsigned i = 0; i < 3; ++i)
4934 blocks[i] += offsets[i];
4935 } else {
4936 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4937 }
4938
4939 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4940 PKT3_SHADER_TYPE_S(1));
4941 radeon_emit(cs, blocks[0]);
4942 radeon_emit(cs, blocks[1]);
4943 radeon_emit(cs, blocks[2]);
4944 radeon_emit(cs, dispatch_initiator);
4945 }
4946
4947 assert(cmd_buffer->cs->cdw <= cdw_max);
4948 }
4949
4950 static void
4951 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4952 {
4953 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4954 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4955 }
4956
4957 static void
4958 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4959 const struct radv_dispatch_info *info)
4960 {
4961 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4962 bool has_prefetch =
4963 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4964 bool pipeline_is_dirty = pipeline &&
4965 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4966
4967 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4968 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4969 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4970 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4971 /* If we have to wait for idle, set all states first, so that
4972 * all SET packets are processed in parallel with previous draw
4973 * calls. Then upload descriptors, set shader pointers, and
4974 * dispatch, and prefetch at the end. This ensures that the
4975 * time the CUs are idle is very short. (there are only SET_SH
4976 * packets between the wait and the draw)
4977 */
4978 radv_emit_compute_pipeline(cmd_buffer);
4979 si_emit_cache_flush(cmd_buffer);
4980 /* <-- CUs are idle here --> */
4981
4982 radv_upload_compute_shader_descriptors(cmd_buffer);
4983
4984 radv_emit_dispatch_packets(cmd_buffer, info);
4985 /* <-- CUs are busy here --> */
4986
4987 /* Start prefetches after the dispatch has been started. Both
4988 * will run in parallel, but starting the dispatch first is
4989 * more important.
4990 */
4991 if (has_prefetch && pipeline_is_dirty) {
4992 radv_emit_shader_prefetch(cmd_buffer,
4993 pipeline->shaders[MESA_SHADER_COMPUTE]);
4994 }
4995 } else {
4996 /* If we don't wait for idle, start prefetches first, then set
4997 * states, and dispatch at the end.
4998 */
4999 si_emit_cache_flush(cmd_buffer);
5000
5001 if (has_prefetch && pipeline_is_dirty) {
5002 radv_emit_shader_prefetch(cmd_buffer,
5003 pipeline->shaders[MESA_SHADER_COMPUTE]);
5004 }
5005
5006 radv_upload_compute_shader_descriptors(cmd_buffer);
5007
5008 radv_emit_compute_pipeline(cmd_buffer);
5009 radv_emit_dispatch_packets(cmd_buffer, info);
5010 }
5011
5012 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5013 }
5014
5015 void radv_CmdDispatchBase(
5016 VkCommandBuffer commandBuffer,
5017 uint32_t base_x,
5018 uint32_t base_y,
5019 uint32_t base_z,
5020 uint32_t x,
5021 uint32_t y,
5022 uint32_t z)
5023 {
5024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5025 struct radv_dispatch_info info = {};
5026
5027 info.blocks[0] = x;
5028 info.blocks[1] = y;
5029 info.blocks[2] = z;
5030
5031 info.offsets[0] = base_x;
5032 info.offsets[1] = base_y;
5033 info.offsets[2] = base_z;
5034 radv_dispatch(cmd_buffer, &info);
5035 }
5036
5037 void radv_CmdDispatch(
5038 VkCommandBuffer commandBuffer,
5039 uint32_t x,
5040 uint32_t y,
5041 uint32_t z)
5042 {
5043 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5044 }
5045
5046 void radv_CmdDispatchIndirect(
5047 VkCommandBuffer commandBuffer,
5048 VkBuffer _buffer,
5049 VkDeviceSize offset)
5050 {
5051 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5052 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5053 struct radv_dispatch_info info = {};
5054
5055 info.indirect = buffer;
5056 info.indirect_offset = offset;
5057
5058 radv_dispatch(cmd_buffer, &info);
5059 }
5060
5061 void radv_unaligned_dispatch(
5062 struct radv_cmd_buffer *cmd_buffer,
5063 uint32_t x,
5064 uint32_t y,
5065 uint32_t z)
5066 {
5067 struct radv_dispatch_info info = {};
5068
5069 info.blocks[0] = x;
5070 info.blocks[1] = y;
5071 info.blocks[2] = z;
5072 info.unaligned = 1;
5073
5074 radv_dispatch(cmd_buffer, &info);
5075 }
5076
5077 void radv_CmdEndRenderPass(
5078 VkCommandBuffer commandBuffer)
5079 {
5080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5081
5082 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5083
5084 radv_cmd_buffer_end_subpass(cmd_buffer);
5085
5086 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5087 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5088
5089 cmd_buffer->state.pass = NULL;
5090 cmd_buffer->state.subpass = NULL;
5091 cmd_buffer->state.attachments = NULL;
5092 cmd_buffer->state.framebuffer = NULL;
5093 cmd_buffer->state.subpass_sample_locs = NULL;
5094 }
5095
5096 void radv_CmdEndRenderPass2KHR(
5097 VkCommandBuffer commandBuffer,
5098 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5099 {
5100 radv_CmdEndRenderPass(commandBuffer);
5101 }
5102
5103 /*
5104 * For HTILE we have the following interesting clear words:
5105 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5106 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5107 * 0xfffffff0: Clear depth to 1.0
5108 * 0x00000000: Clear depth to 0.0
5109 */
5110 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5111 struct radv_image *image,
5112 const VkImageSubresourceRange *range,
5113 uint32_t clear_word)
5114 {
5115 assert(range->baseMipLevel == 0);
5116 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5117 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5118 struct radv_cmd_state *state = &cmd_buffer->state;
5119 VkClearDepthStencilValue value = {};
5120
5121 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5122 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5123
5124 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5125
5126 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5127
5128 if (vk_format_is_stencil(image->vk_format))
5129 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5130
5131 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5132
5133 if (radv_image_is_tc_compat_htile(image)) {
5134 /* Initialize the TC-compat metada value to 0 because by
5135 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5136 * need have to conditionally update its value when performing
5137 * a fast depth clear.
5138 */
5139 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5140 }
5141 }
5142
5143 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5144 struct radv_image *image,
5145 VkImageLayout src_layout,
5146 bool src_render_loop,
5147 VkImageLayout dst_layout,
5148 bool dst_render_loop,
5149 unsigned src_queue_mask,
5150 unsigned dst_queue_mask,
5151 const VkImageSubresourceRange *range,
5152 struct radv_sample_locations_state *sample_locs)
5153 {
5154 if (!radv_image_has_htile(image))
5155 return;
5156
5157 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5158 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5159
5160 if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
5161 dst_queue_mask)) {
5162 clear_value = 0;
5163 }
5164
5165 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5166 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5167 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5168 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5169 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5170 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5171 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5172 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5173 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5174
5175 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5176 sample_locs);
5177
5178 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5179 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5180 }
5181 }
5182
5183 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5184 struct radv_image *image,
5185 const VkImageSubresourceRange *range,
5186 uint32_t value)
5187 {
5188 struct radv_cmd_state *state = &cmd_buffer->state;
5189
5190 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5191 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5192
5193 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5194
5195 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5196 }
5197
5198 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5199 struct radv_image *image,
5200 const VkImageSubresourceRange *range)
5201 {
5202 struct radv_cmd_state *state = &cmd_buffer->state;
5203 static const uint32_t fmask_clear_values[4] = {
5204 0x00000000,
5205 0x02020202,
5206 0xE4E4E4E4,
5207 0x76543210
5208 };
5209 uint32_t log2_samples = util_logbase2(image->info.samples);
5210 uint32_t value = fmask_clear_values[log2_samples];
5211
5212 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5213 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5214
5215 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5216
5217 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5218 }
5219
5220 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5221 struct radv_image *image,
5222 const VkImageSubresourceRange *range, uint32_t value)
5223 {
5224 struct radv_cmd_state *state = &cmd_buffer->state;
5225 unsigned size = 0;
5226
5227 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5228 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5229
5230 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5231
5232 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5233 /* When DCC is enabled with mipmaps, some levels might not
5234 * support fast clears and we have to initialize them as "fully
5235 * expanded".
5236 */
5237 /* Compute the size of all fast clearable DCC levels. */
5238 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5239 struct legacy_surf_level *surf_level =
5240 &image->planes[0].surface.u.legacy.level[i];
5241 unsigned dcc_fast_clear_size =
5242 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5243
5244 if (!dcc_fast_clear_size)
5245 break;
5246
5247 size = surf_level->dcc_offset + dcc_fast_clear_size;
5248 }
5249
5250 /* Initialize the mipmap levels without DCC. */
5251 if (size != image->planes[0].surface.dcc_size) {
5252 state->flush_bits |=
5253 radv_fill_buffer(cmd_buffer, image->bo,
5254 image->offset + image->dcc_offset + size,
5255 image->planes[0].surface.dcc_size - size,
5256 0xffffffff);
5257 }
5258 }
5259
5260 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5261 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5262 }
5263
5264 /**
5265 * Initialize DCC/FMASK/CMASK metadata for a color image.
5266 */
5267 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5268 struct radv_image *image,
5269 VkImageLayout src_layout,
5270 bool src_render_loop,
5271 VkImageLayout dst_layout,
5272 bool dst_render_loop,
5273 unsigned src_queue_mask,
5274 unsigned dst_queue_mask,
5275 const VkImageSubresourceRange *range)
5276 {
5277 if (radv_image_has_cmask(image)) {
5278 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5279
5280 /* TODO: clarify this. */
5281 if (radv_image_has_fmask(image)) {
5282 value = 0xccccccccu;
5283 }
5284
5285 radv_initialise_cmask(cmd_buffer, image, range, value);
5286 }
5287
5288 if (radv_image_has_fmask(image)) {
5289 radv_initialize_fmask(cmd_buffer, image, range);
5290 }
5291
5292 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5293 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5294 bool need_decompress_pass = false;
5295
5296 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5297 dst_render_loop,
5298 dst_queue_mask)) {
5299 value = 0x20202020u;
5300 need_decompress_pass = true;
5301 }
5302
5303 radv_initialize_dcc(cmd_buffer, image, range, value);
5304
5305 radv_update_fce_metadata(cmd_buffer, image, range,
5306 need_decompress_pass);
5307 }
5308
5309 if (radv_image_has_cmask(image) ||
5310 radv_dcc_enabled(image, range->baseMipLevel)) {
5311 uint32_t color_values[2] = {};
5312 radv_set_color_clear_metadata(cmd_buffer, image, range,
5313 color_values);
5314 }
5315 }
5316
5317 /**
5318 * Handle color image transitions for DCC/FMASK/CMASK.
5319 */
5320 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5321 struct radv_image *image,
5322 VkImageLayout src_layout,
5323 bool src_render_loop,
5324 VkImageLayout dst_layout,
5325 bool dst_render_loop,
5326 unsigned src_queue_mask,
5327 unsigned dst_queue_mask,
5328 const VkImageSubresourceRange *range)
5329 {
5330 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5331 radv_init_color_image_metadata(cmd_buffer, image,
5332 src_layout, src_render_loop,
5333 dst_layout, dst_render_loop,
5334 src_queue_mask, dst_queue_mask,
5335 range);
5336 return;
5337 }
5338
5339 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5340 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5341 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5342 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5343 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5344 radv_decompress_dcc(cmd_buffer, image, range);
5345 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5346 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5347 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5348 }
5349 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5350 bool fce_eliminate = false, fmask_expand = false;
5351
5352 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5353 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5354 fce_eliminate = true;
5355 }
5356
5357 if (radv_image_has_fmask(image)) {
5358 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5359 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5360 /* A FMASK decompress is required before doing
5361 * a MSAA decompress using FMASK.
5362 */
5363 fmask_expand = true;
5364 }
5365 }
5366
5367 if (fce_eliminate || fmask_expand)
5368 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5369
5370 if (fmask_expand)
5371 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5372 }
5373 }
5374
5375 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5376 struct radv_image *image,
5377 VkImageLayout src_layout,
5378 bool src_render_loop,
5379 VkImageLayout dst_layout,
5380 bool dst_render_loop,
5381 uint32_t src_family,
5382 uint32_t dst_family,
5383 const VkImageSubresourceRange *range,
5384 struct radv_sample_locations_state *sample_locs)
5385 {
5386 if (image->exclusive && src_family != dst_family) {
5387 /* This is an acquire or a release operation and there will be
5388 * a corresponding release/acquire. Do the transition in the
5389 * most flexible queue. */
5390
5391 assert(src_family == cmd_buffer->queue_family_index ||
5392 dst_family == cmd_buffer->queue_family_index);
5393
5394 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5395 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5396 return;
5397
5398 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5399 return;
5400
5401 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5402 (src_family == RADV_QUEUE_GENERAL ||
5403 dst_family == RADV_QUEUE_GENERAL))
5404 return;
5405 }
5406
5407 if (src_layout == dst_layout)
5408 return;
5409
5410 unsigned src_queue_mask =
5411 radv_image_queue_family_mask(image, src_family,
5412 cmd_buffer->queue_family_index);
5413 unsigned dst_queue_mask =
5414 radv_image_queue_family_mask(image, dst_family,
5415 cmd_buffer->queue_family_index);
5416
5417 if (vk_format_is_depth(image->vk_format)) {
5418 radv_handle_depth_image_transition(cmd_buffer, image,
5419 src_layout, src_render_loop,
5420 dst_layout, dst_render_loop,
5421 src_queue_mask, dst_queue_mask,
5422 range, sample_locs);
5423 } else {
5424 radv_handle_color_image_transition(cmd_buffer, image,
5425 src_layout, src_render_loop,
5426 dst_layout, dst_render_loop,
5427 src_queue_mask, dst_queue_mask,
5428 range);
5429 }
5430 }
5431
5432 struct radv_barrier_info {
5433 uint32_t eventCount;
5434 const VkEvent *pEvents;
5435 VkPipelineStageFlags srcStageMask;
5436 VkPipelineStageFlags dstStageMask;
5437 };
5438
5439 static void
5440 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5441 uint32_t memoryBarrierCount,
5442 const VkMemoryBarrier *pMemoryBarriers,
5443 uint32_t bufferMemoryBarrierCount,
5444 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5445 uint32_t imageMemoryBarrierCount,
5446 const VkImageMemoryBarrier *pImageMemoryBarriers,
5447 const struct radv_barrier_info *info)
5448 {
5449 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5450 enum radv_cmd_flush_bits src_flush_bits = 0;
5451 enum radv_cmd_flush_bits dst_flush_bits = 0;
5452
5453 for (unsigned i = 0; i < info->eventCount; ++i) {
5454 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5455 uint64_t va = radv_buffer_get_va(event->bo);
5456
5457 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5458
5459 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5460
5461 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5462 assert(cmd_buffer->cs->cdw <= cdw_max);
5463 }
5464
5465 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5466 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5467 NULL);
5468 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5469 NULL);
5470 }
5471
5472 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5473 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5474 NULL);
5475 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5476 NULL);
5477 }
5478
5479 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5480 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5481
5482 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5483 image);
5484 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5485 image);
5486 }
5487
5488 /* The Vulkan spec 1.1.98 says:
5489 *
5490 * "An execution dependency with only
5491 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5492 * will only prevent that stage from executing in subsequently
5493 * submitted commands. As this stage does not perform any actual
5494 * execution, this is not observable - in effect, it does not delay
5495 * processing of subsequent commands. Similarly an execution dependency
5496 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5497 * will effectively not wait for any prior commands to complete."
5498 */
5499 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5500 radv_stage_flush(cmd_buffer, info->srcStageMask);
5501 cmd_buffer->state.flush_bits |= src_flush_bits;
5502
5503 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5504 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5505
5506 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5507 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5508 SAMPLE_LOCATIONS_INFO_EXT);
5509 struct radv_sample_locations_state sample_locations = {};
5510
5511 if (sample_locs_info) {
5512 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5513 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5514 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5515 sample_locations.count = sample_locs_info->sampleLocationsCount;
5516 typed_memcpy(&sample_locations.locations[0],
5517 sample_locs_info->pSampleLocations,
5518 sample_locs_info->sampleLocationsCount);
5519 }
5520
5521 radv_handle_image_transition(cmd_buffer, image,
5522 pImageMemoryBarriers[i].oldLayout,
5523 false, /* Outside of a renderpass we are never in a renderloop */
5524 pImageMemoryBarriers[i].newLayout,
5525 false, /* Outside of a renderpass we are never in a renderloop */
5526 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5527 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5528 &pImageMemoryBarriers[i].subresourceRange,
5529 sample_locs_info ? &sample_locations : NULL);
5530 }
5531
5532 /* Make sure CP DMA is idle because the driver might have performed a
5533 * DMA operation for copying or filling buffers/images.
5534 */
5535 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5536 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5537 si_cp_dma_wait_for_idle(cmd_buffer);
5538
5539 cmd_buffer->state.flush_bits |= dst_flush_bits;
5540 }
5541
5542 void radv_CmdPipelineBarrier(
5543 VkCommandBuffer commandBuffer,
5544 VkPipelineStageFlags srcStageMask,
5545 VkPipelineStageFlags destStageMask,
5546 VkBool32 byRegion,
5547 uint32_t memoryBarrierCount,
5548 const VkMemoryBarrier* pMemoryBarriers,
5549 uint32_t bufferMemoryBarrierCount,
5550 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5551 uint32_t imageMemoryBarrierCount,
5552 const VkImageMemoryBarrier* pImageMemoryBarriers)
5553 {
5554 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5555 struct radv_barrier_info info;
5556
5557 info.eventCount = 0;
5558 info.pEvents = NULL;
5559 info.srcStageMask = srcStageMask;
5560 info.dstStageMask = destStageMask;
5561
5562 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5563 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5564 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5565 }
5566
5567
5568 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5569 struct radv_event *event,
5570 VkPipelineStageFlags stageMask,
5571 unsigned value)
5572 {
5573 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5574 uint64_t va = radv_buffer_get_va(event->bo);
5575
5576 si_emit_cache_flush(cmd_buffer);
5577
5578 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5579
5580 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5581
5582 /* Flags that only require a top-of-pipe event. */
5583 VkPipelineStageFlags top_of_pipe_flags =
5584 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5585
5586 /* Flags that only require a post-index-fetch event. */
5587 VkPipelineStageFlags post_index_fetch_flags =
5588 top_of_pipe_flags |
5589 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5590 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5591
5592 /* Make sure CP DMA is idle because the driver might have performed a
5593 * DMA operation for copying or filling buffers/images.
5594 */
5595 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5596 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5597 si_cp_dma_wait_for_idle(cmd_buffer);
5598
5599 /* TODO: Emit EOS events for syncing PS/CS stages. */
5600
5601 if (!(stageMask & ~top_of_pipe_flags)) {
5602 /* Just need to sync the PFP engine. */
5603 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5604 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5605 S_370_WR_CONFIRM(1) |
5606 S_370_ENGINE_SEL(V_370_PFP));
5607 radeon_emit(cs, va);
5608 radeon_emit(cs, va >> 32);
5609 radeon_emit(cs, value);
5610 } else if (!(stageMask & ~post_index_fetch_flags)) {
5611 /* Sync ME because PFP reads index and indirect buffers. */
5612 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5613 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5614 S_370_WR_CONFIRM(1) |
5615 S_370_ENGINE_SEL(V_370_ME));
5616 radeon_emit(cs, va);
5617 radeon_emit(cs, va >> 32);
5618 radeon_emit(cs, value);
5619 } else {
5620 /* Otherwise, sync all prior GPU work using an EOP event. */
5621 si_cs_emit_write_event_eop(cs,
5622 cmd_buffer->device->physical_device->rad_info.chip_class,
5623 radv_cmd_buffer_uses_mec(cmd_buffer),
5624 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5625 EOP_DST_SEL_MEM,
5626 EOP_DATA_SEL_VALUE_32BIT, va, value,
5627 cmd_buffer->gfx9_eop_bug_va);
5628 }
5629
5630 assert(cmd_buffer->cs->cdw <= cdw_max);
5631 }
5632
5633 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5634 VkEvent _event,
5635 VkPipelineStageFlags stageMask)
5636 {
5637 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5638 RADV_FROM_HANDLE(radv_event, event, _event);
5639
5640 write_event(cmd_buffer, event, stageMask, 1);
5641 }
5642
5643 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5644 VkEvent _event,
5645 VkPipelineStageFlags stageMask)
5646 {
5647 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5648 RADV_FROM_HANDLE(radv_event, event, _event);
5649
5650 write_event(cmd_buffer, event, stageMask, 0);
5651 }
5652
5653 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5654 uint32_t eventCount,
5655 const VkEvent* pEvents,
5656 VkPipelineStageFlags srcStageMask,
5657 VkPipelineStageFlags dstStageMask,
5658 uint32_t memoryBarrierCount,
5659 const VkMemoryBarrier* pMemoryBarriers,
5660 uint32_t bufferMemoryBarrierCount,
5661 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5662 uint32_t imageMemoryBarrierCount,
5663 const VkImageMemoryBarrier* pImageMemoryBarriers)
5664 {
5665 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5666 struct radv_barrier_info info;
5667
5668 info.eventCount = eventCount;
5669 info.pEvents = pEvents;
5670 info.srcStageMask = 0;
5671
5672 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5673 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5674 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5675 }
5676
5677
5678 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5679 uint32_t deviceMask)
5680 {
5681 /* No-op */
5682 }
5683
5684 /* VK_EXT_conditional_rendering */
5685 void radv_CmdBeginConditionalRenderingEXT(
5686 VkCommandBuffer commandBuffer,
5687 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5688 {
5689 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5690 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5691 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5692 bool draw_visible = true;
5693 uint64_t pred_value = 0;
5694 uint64_t va, new_va;
5695 unsigned pred_offset;
5696
5697 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5698
5699 /* By default, if the 32-bit value at offset in buffer memory is zero,
5700 * then the rendering commands are discarded, otherwise they are
5701 * executed as normal. If the inverted flag is set, all commands are
5702 * discarded if the value is non zero.
5703 */
5704 if (pConditionalRenderingBegin->flags &
5705 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5706 draw_visible = false;
5707 }
5708
5709 si_emit_cache_flush(cmd_buffer);
5710
5711 /* From the Vulkan spec 1.1.107:
5712 *
5713 * "If the 32-bit value at offset in buffer memory is zero, then the
5714 * rendering commands are discarded, otherwise they are executed as
5715 * normal. If the value of the predicate in buffer memory changes while
5716 * conditional rendering is active, the rendering commands may be
5717 * discarded in an implementation-dependent way. Some implementations
5718 * may latch the value of the predicate upon beginning conditional
5719 * rendering while others may read it before every rendering command."
5720 *
5721 * But, the AMD hardware treats the predicate as a 64-bit value which
5722 * means we need a workaround in the driver. Luckily, it's not required
5723 * to support if the value changes when predication is active.
5724 *
5725 * The workaround is as follows:
5726 * 1) allocate a 64-value in the upload BO and initialize it to 0
5727 * 2) copy the 32-bit predicate value to the upload BO
5728 * 3) use the new allocated VA address for predication
5729 *
5730 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5731 * in ME (+ sync PFP) instead of PFP.
5732 */
5733 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5734
5735 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5736
5737 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5738 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5739 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5740 COPY_DATA_WR_CONFIRM);
5741 radeon_emit(cs, va);
5742 radeon_emit(cs, va >> 32);
5743 radeon_emit(cs, new_va);
5744 radeon_emit(cs, new_va >> 32);
5745
5746 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5747 radeon_emit(cs, 0);
5748
5749 /* Enable predication for this command buffer. */
5750 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5751 cmd_buffer->state.predicating = true;
5752
5753 /* Store conditional rendering user info. */
5754 cmd_buffer->state.predication_type = draw_visible;
5755 cmd_buffer->state.predication_va = new_va;
5756 }
5757
5758 void radv_CmdEndConditionalRenderingEXT(
5759 VkCommandBuffer commandBuffer)
5760 {
5761 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5762
5763 /* Disable predication for this command buffer. */
5764 si_emit_set_predication_state(cmd_buffer, false, 0);
5765 cmd_buffer->state.predicating = false;
5766
5767 /* Reset conditional rendering user info. */
5768 cmd_buffer->state.predication_type = -1;
5769 cmd_buffer->state.predication_va = 0;
5770 }
5771
5772 /* VK_EXT_transform_feedback */
5773 void radv_CmdBindTransformFeedbackBuffersEXT(
5774 VkCommandBuffer commandBuffer,
5775 uint32_t firstBinding,
5776 uint32_t bindingCount,
5777 const VkBuffer* pBuffers,
5778 const VkDeviceSize* pOffsets,
5779 const VkDeviceSize* pSizes)
5780 {
5781 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5782 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5783 uint8_t enabled_mask = 0;
5784
5785 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5786 for (uint32_t i = 0; i < bindingCount; i++) {
5787 uint32_t idx = firstBinding + i;
5788
5789 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5790 sb[idx].offset = pOffsets[i];
5791 sb[idx].size = pSizes[i];
5792
5793 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5794 sb[idx].buffer->bo);
5795
5796 enabled_mask |= 1 << idx;
5797 }
5798
5799 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5800
5801 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5802 }
5803
5804 static void
5805 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5806 {
5807 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5808 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5809
5810 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5811 radeon_emit(cs,
5812 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5813 S_028B94_RAST_STREAM(0) |
5814 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5815 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5816 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5817 radeon_emit(cs, so->hw_enabled_mask &
5818 so->enabled_stream_buffers_mask);
5819
5820 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5821 }
5822
5823 static void
5824 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5825 {
5826 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5827 bool old_streamout_enabled = so->streamout_enabled;
5828 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5829
5830 so->streamout_enabled = enable;
5831
5832 so->hw_enabled_mask = so->enabled_mask |
5833 (so->enabled_mask << 4) |
5834 (so->enabled_mask << 8) |
5835 (so->enabled_mask << 12);
5836
5837 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5838 ((old_streamout_enabled != so->streamout_enabled) ||
5839 (old_hw_enabled_mask != so->hw_enabled_mask)))
5840 radv_emit_streamout_enable(cmd_buffer);
5841
5842 if (cmd_buffer->device->physical_device->use_ngg_streamout)
5843 cmd_buffer->gds_needed = true;
5844 }
5845
5846 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5847 {
5848 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5849 unsigned reg_strmout_cntl;
5850
5851 /* The register is at different places on different ASICs. */
5852 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5853 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5854 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5855 } else {
5856 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5857 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5858 }
5859
5860 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5861 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5862
5863 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5864 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5865 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5866 radeon_emit(cs, 0);
5867 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5868 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5869 radeon_emit(cs, 4); /* poll interval */
5870 }
5871
5872 static void
5873 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5874 uint32_t firstCounterBuffer,
5875 uint32_t counterBufferCount,
5876 const VkBuffer *pCounterBuffers,
5877 const VkDeviceSize *pCounterBufferOffsets)
5878
5879 {
5880 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5881 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5882 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5883 uint32_t i;
5884
5885 radv_flush_vgt_streamout(cmd_buffer);
5886
5887 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5888 for_each_bit(i, so->enabled_mask) {
5889 int32_t counter_buffer_idx = i - firstCounterBuffer;
5890 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5891 counter_buffer_idx = -1;
5892
5893 /* AMD GCN binds streamout buffers as shader resources.
5894 * VGT only counts primitives and tells the shader through
5895 * SGPRs what to do.
5896 */
5897 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5898 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5899 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5900
5901 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5902
5903 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5904 /* The array of counter buffers is optional. */
5905 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5906 uint64_t va = radv_buffer_get_va(buffer->bo);
5907
5908 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5909
5910 /* Append */
5911 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5912 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5913 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5914 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5915 radeon_emit(cs, 0); /* unused */
5916 radeon_emit(cs, 0); /* unused */
5917 radeon_emit(cs, va); /* src address lo */
5918 radeon_emit(cs, va >> 32); /* src address hi */
5919
5920 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5921 } else {
5922 /* Start from the beginning. */
5923 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5924 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5925 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5926 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5927 radeon_emit(cs, 0); /* unused */
5928 radeon_emit(cs, 0); /* unused */
5929 radeon_emit(cs, 0); /* unused */
5930 radeon_emit(cs, 0); /* unused */
5931 }
5932 }
5933
5934 radv_set_streamout_enable(cmd_buffer, true);
5935 }
5936
5937 static void
5938 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5939 uint32_t firstCounterBuffer,
5940 uint32_t counterBufferCount,
5941 const VkBuffer *pCounterBuffers,
5942 const VkDeviceSize *pCounterBufferOffsets)
5943 {
5944 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5945 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
5946 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5947 uint32_t i;
5948
5949 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5950 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5951
5952 /* Sync because the next streamout operation will overwrite GDS and we
5953 * have to make sure it's idle.
5954 * TODO: Improve by tracking if there is a streamout operation in
5955 * flight.
5956 */
5957 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
5958 si_emit_cache_flush(cmd_buffer);
5959
5960 for_each_bit(i, so->enabled_mask) {
5961 int32_t counter_buffer_idx = i - firstCounterBuffer;
5962 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5963 counter_buffer_idx = -1;
5964
5965 bool append = counter_buffer_idx >= 0 &&
5966 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
5967 uint64_t va = 0;
5968
5969 if (append) {
5970 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5971
5972 va += radv_buffer_get_va(buffer->bo);
5973 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5974
5975 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5976 }
5977
5978 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
5979 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
5980 S_411_DST_SEL(V_411_GDS) |
5981 S_411_CP_SYNC(i == last_target));
5982 radeon_emit(cs, va);
5983 radeon_emit(cs, va >> 32);
5984 radeon_emit(cs, 4 * i); /* destination in GDS */
5985 radeon_emit(cs, 0);
5986 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
5987 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
5988 }
5989
5990 radv_set_streamout_enable(cmd_buffer, true);
5991 }
5992
5993 void radv_CmdBeginTransformFeedbackEXT(
5994 VkCommandBuffer commandBuffer,
5995 uint32_t firstCounterBuffer,
5996 uint32_t counterBufferCount,
5997 const VkBuffer* pCounterBuffers,
5998 const VkDeviceSize* pCounterBufferOffsets)
5999 {
6000 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6001
6002 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6003 gfx10_emit_streamout_begin(cmd_buffer,
6004 firstCounterBuffer, counterBufferCount,
6005 pCounterBuffers, pCounterBufferOffsets);
6006 } else {
6007 radv_emit_streamout_begin(cmd_buffer,
6008 firstCounterBuffer, counterBufferCount,
6009 pCounterBuffers, pCounterBufferOffsets);
6010 }
6011 }
6012
6013 static void
6014 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6015 uint32_t firstCounterBuffer,
6016 uint32_t counterBufferCount,
6017 const VkBuffer *pCounterBuffers,
6018 const VkDeviceSize *pCounterBufferOffsets)
6019 {
6020 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6021 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6022 uint32_t i;
6023
6024 radv_flush_vgt_streamout(cmd_buffer);
6025
6026 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6027 for_each_bit(i, so->enabled_mask) {
6028 int32_t counter_buffer_idx = i - firstCounterBuffer;
6029 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6030 counter_buffer_idx = -1;
6031
6032 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6033 /* The array of counters buffer is optional. */
6034 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6035 uint64_t va = radv_buffer_get_va(buffer->bo);
6036
6037 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6038
6039 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6040 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6041 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6042 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6043 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6044 radeon_emit(cs, va); /* dst address lo */
6045 radeon_emit(cs, va >> 32); /* dst address hi */
6046 radeon_emit(cs, 0); /* unused */
6047 radeon_emit(cs, 0); /* unused */
6048
6049 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6050 }
6051
6052 /* Deactivate transform feedback by zeroing the buffer size.
6053 * The counters (primitives generated, primitives emitted) may
6054 * be enabled even if there is not buffer bound. This ensures
6055 * that the primitives-emitted query won't increment.
6056 */
6057 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6058
6059 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6060 }
6061
6062 radv_set_streamout_enable(cmd_buffer, false);
6063 }
6064
6065 static void
6066 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6067 uint32_t firstCounterBuffer,
6068 uint32_t counterBufferCount,
6069 const VkBuffer *pCounterBuffers,
6070 const VkDeviceSize *pCounterBufferOffsets)
6071 {
6072 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6073 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6074 uint32_t i;
6075
6076 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6077 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6078
6079 for_each_bit(i, so->enabled_mask) {
6080 int32_t counter_buffer_idx = i - firstCounterBuffer;
6081 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6082 counter_buffer_idx = -1;
6083
6084 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6085 /* The array of counters buffer is optional. */
6086 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6087 uint64_t va = radv_buffer_get_va(buffer->bo);
6088
6089 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6090
6091 si_cs_emit_write_event_eop(cs,
6092 cmd_buffer->device->physical_device->rad_info.chip_class,
6093 radv_cmd_buffer_uses_mec(cmd_buffer),
6094 V_028A90_PS_DONE, 0,
6095 EOP_DST_SEL_TC_L2,
6096 EOP_DATA_SEL_GDS,
6097 va, EOP_DATA_GDS(i, 1), 0);
6098
6099 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6100 }
6101 }
6102
6103 radv_set_streamout_enable(cmd_buffer, false);
6104 }
6105
6106 void radv_CmdEndTransformFeedbackEXT(
6107 VkCommandBuffer commandBuffer,
6108 uint32_t firstCounterBuffer,
6109 uint32_t counterBufferCount,
6110 const VkBuffer* pCounterBuffers,
6111 const VkDeviceSize* pCounterBufferOffsets)
6112 {
6113 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6114
6115 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6116 gfx10_emit_streamout_end(cmd_buffer,
6117 firstCounterBuffer, counterBufferCount,
6118 pCounterBuffers, pCounterBufferOffsets);
6119 } else {
6120 radv_emit_streamout_end(cmd_buffer,
6121 firstCounterBuffer, counterBufferCount,
6122 pCounterBuffers, pCounterBufferOffsets);
6123 }
6124 }
6125
6126 void radv_CmdDrawIndirectByteCountEXT(
6127 VkCommandBuffer commandBuffer,
6128 uint32_t instanceCount,
6129 uint32_t firstInstance,
6130 VkBuffer _counterBuffer,
6131 VkDeviceSize counterBufferOffset,
6132 uint32_t counterOffset,
6133 uint32_t vertexStride)
6134 {
6135 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6136 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6137 struct radv_draw_info info = {};
6138
6139 info.instance_count = instanceCount;
6140 info.first_instance = firstInstance;
6141 info.strmout_buffer = counterBuffer;
6142 info.strmout_buffer_offset = counterBufferOffset;
6143 info.stride = vertexStride;
6144
6145 radv_draw(cmd_buffer, &info);
6146 }
6147
6148 /* VK_AMD_buffer_marker */
6149 void radv_CmdWriteBufferMarkerAMD(
6150 VkCommandBuffer commandBuffer,
6151 VkPipelineStageFlagBits pipelineStage,
6152 VkBuffer dstBuffer,
6153 VkDeviceSize dstOffset,
6154 uint32_t marker)
6155 {
6156 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6157 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6158 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6159 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6160
6161 si_emit_cache_flush(cmd_buffer);
6162
6163 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6164 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6165 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6166 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6167 COPY_DATA_WR_CONFIRM);
6168 radeon_emit(cs, marker);
6169 radeon_emit(cs, 0);
6170 radeon_emit(cs, va);
6171 radeon_emit(cs, va >> 32);
6172 } else {
6173 si_cs_emit_write_event_eop(cs,
6174 cmd_buffer->device->physical_device->rad_info.chip_class,
6175 radv_cmd_buffer_uses_mec(cmd_buffer),
6176 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6177 EOP_DST_SEL_MEM,
6178 EOP_DATA_SEL_VALUE_32BIT,
6179 va, marker,
6180 cmd_buffer->gfx9_eop_bug_va);
6181 }
6182 }